├── .github └── workflows │ └── regression-tests.yml ├── .gitignore ├── .test_durations ├── AUTHORS ├── COPYING ├── README.md ├── example ├── 520N_MX │ └── fpga_10g │ │ ├── README.md │ │ ├── common │ │ └── quartus_pro.mk │ │ ├── fpga.qsf │ │ ├── fpga.sdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ ├── eth_xcvr.tcl │ │ ├── eth_xcvr_pll.tcl │ │ ├── eth_xcvr_reset.tcl │ │ └── reset_release.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── eth_xcvr_phy_quad_wrapper.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ADM_PCIE_9V3 │ ├── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ └── Makefile │ │ ├── ip │ │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── eth_xcvr_phy_wrapper.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ └── fpga_25g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ATLYS │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── clock.ucf │ │ ├── common │ │ └── xilinx.mk │ │ ├── fpga.ucf │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── AU200 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── AU250 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── AU280 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── AU50 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── Arty │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── C10LP │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── quartus.mk │ │ ├── fpga.qsf │ │ ├── fpga.sdc │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── DE2-115 │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── quartus.mk │ │ ├── fpga.qsf │ │ ├── fpga.sdc │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── hex_display.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── DE5-Net │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── altera.mk │ │ ├── cores │ │ ├── Makefile │ │ ├── phy.v │ │ └── phy_reconfig.v │ │ ├── fpga.qsf │ │ ├── fpga.sdc │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── i2c_master.v │ │ ├── si570_i2c_init.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ExaNIC_X10 │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ExaNIC_X25 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── HTG9200 │ └── fpga_10g │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── Si5341-RevD-fpga-161-osc-Registers.txt │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── i2c_master.v │ │ ├── si5341_i2c_init.py │ │ ├── si5341_i2c_init.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── HXT100G │ ├── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ │ └── xilinx.mk │ │ ├── coregen │ │ │ ├── Makefile │ │ │ ├── coregen.cgp │ │ │ ├── ten_gig_eth_pcs_pma_v2_6.xco │ │ │ └── ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco │ │ ├── fpga.ucf │ │ ├── fpga │ │ │ └── Makefile │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── eth_gth_phy_quad.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ ├── gth_i2c_init.v │ │ │ ├── i2c_master.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ └── fpga_cxpt16 │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── xilinx.mk │ │ ├── coregen │ │ ├── Makefile │ │ ├── coregen.cgp │ │ ├── ten_gig_eth_pcs_pma_v2_6.xco │ │ └── ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco │ │ ├── fpga.ucf │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_gth_phy_quad.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── gth_i2c_init.v │ │ ├── i2c_master.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── KC705 │ ├── fpga_gmii │ │ ├── Makefile │ │ ├── README.md │ │ ├── clock.xdc │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ └── Makefile │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ ├── fpga_rgmii │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ │ └── vivado.mk │ │ ├── eth.xdc │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ ├── Makefile │ │ │ └── generate_bit_iodelay.tcl │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ └── fpga_sgmii │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ML605 │ ├── fpga_gmii │ │ ├── Makefile │ │ ├── README.md │ │ ├── clock.ucf │ │ ├── common │ │ │ └── xilinx.mk │ │ ├── fpga.ucf │ │ ├── fpga_130t │ │ │ └── Makefile │ │ ├── fpga_240t │ │ │ └── Makefile │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ ├── fpga_rgmii │ │ ├── Makefile │ │ ├── README.md │ │ ├── clock.ucf │ │ ├── common │ │ │ └── xilinx.mk │ │ ├── fpga.ucf │ │ ├── fpga_130t │ │ │ └── Makefile │ │ ├── fpga_240t │ │ │ └── Makefile │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ └── fpga_sgmii │ │ ├── Makefile │ │ ├── README.md │ │ ├── clock.ucf │ │ ├── common │ │ └── xilinx.mk │ │ ├── coregen │ │ ├── Makefile │ │ ├── coregen.cgp │ │ └── gig_eth_pcs_pma_v11_5.xco │ │ ├── fpga.ucf │ │ ├── fpga_130t │ │ └── Makefile │ │ ├── fpga_240t │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── NetFPGA_SUME │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ ├── ten_gig_eth_pcs_pma_0.tcl │ │ └── ten_gig_eth_pcs_pma_1.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── i2c_master.v │ │ └── si5324_i2c_init.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── NexysVideo │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── eth.xdc │ │ ├── fpga.xdc │ │ ├── fpga │ │ ├── Makefile │ │ └── generate_bit_iodelay.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── RV901T │ └── fpga │ │ ├── README.md │ │ ├── clock.ucf │ │ ├── common │ │ └── xilinx.mk │ │ ├── fpga.ucf │ │ ├── fpga │ │ └── Makefile │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── fpga.v │ │ └── fpga_core.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── S10DX_DK │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── quartus_pro.mk │ │ ├── fpga.qsf │ │ ├── fpga.sdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ ├── mac.tcl │ │ └── reset_release.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── avst2axis.v │ │ ├── axis2avst.v │ │ ├── debounce_switch.v │ │ ├── eth_mac_quad_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── sync_signal.v │ │ └── xcvr_ctrl.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── S10MX_DK │ └── fpga_10g │ │ ├── README.md │ │ ├── common │ │ └── quartus_pro.mk │ │ ├── fpga.qsf │ │ ├── fpga.sdc │ │ ├── fpga_1sm21b │ │ └── Makefile │ │ ├── fpga_1sm21c │ │ └── Makefile │ │ ├── ip │ │ ├── eth_xcvr.tcl │ │ ├── eth_xcvr_pll.tcl │ │ ├── eth_xcvr_reset.tcl │ │ └── reset_release.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── eth_xcvr_phy_quad_wrapper.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── VCU108 │ ├── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ │ └── vivado.mk │ │ ├── eth.xdc │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ └── Makefile │ │ ├── ip │ │ │ ├── eth_xcvr_gt.tcl │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── eth_xcvr_phy_wrapper.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ └── fpga_1g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── eth.xdc │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── VCU118 │ ├── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ └── Makefile │ │ ├── ip │ │ │ ├── eth_xcvr_gt.tcl │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── eth_xcvr_phy_wrapper.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ ├── mdio_master.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ ├── fpga_1g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ │ └── Makefile │ │ ├── ip │ │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ ├── lib │ │ │ └── eth │ │ ├── rtl │ │ │ ├── debounce_switch.v │ │ │ ├── fpga.v │ │ │ ├── fpga_core.v │ │ │ ├── mdio_master.v │ │ │ └── sync_signal.v │ │ └── tb │ │ │ └── fpga_core │ │ │ ├── Makefile │ │ │ └── test_fpga_core.py │ └── fpga_25g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ ├── eth_xcvr_gt.tcl │ │ └── gig_ethernet_pcs_pma_0.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ ├── mdio_master.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── VCU1525 │ └── fpga_10g │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ZCU102 │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py ├── ZCU106 │ └── fpga │ │ ├── Makefile │ │ ├── README.md │ │ ├── common │ │ └── vivado.mk │ │ ├── fpga.xdc │ │ ├── fpga │ │ └── Makefile │ │ ├── ip │ │ └── eth_xcvr_gt.tcl │ │ ├── lib │ │ └── eth │ │ ├── rtl │ │ ├── debounce_switch.v │ │ ├── eth_xcvr_phy_wrapper.v │ │ ├── fpga.v │ │ ├── fpga_core.v │ │ └── sync_signal.v │ │ └── tb │ │ └── fpga_core │ │ ├── Makefile │ │ └── test_fpga_core.py └── fb2CG │ └── fpga_10g │ ├── Makefile │ ├── README.md │ ├── common │ └── vivado.mk │ ├── fpga.xdc │ ├── fpga │ └── Makefile │ ├── ip │ └── eth_xcvr_gt.tcl │ ├── led.tcl │ ├── lib │ └── eth │ ├── rtl │ ├── eth_xcvr_phy_wrapper.v │ ├── fpga.v │ ├── fpga_core.v │ ├── led_sreg_driver.v │ └── sync_signal.v │ └── tb │ └── fpga_core │ ├── Makefile │ └── test_fpga_core.py ├── lib ├── axis │ ├── .github │ │ └── workflows │ │ │ └── regression-tests.yml │ ├── .gitignore │ ├── .test_durations │ ├── AUTHORS │ ├── COPYING │ ├── README │ ├── README.md │ ├── rtl │ │ ├── arbiter.v │ │ ├── axis_adapter.v │ │ ├── axis_arb_mux.v │ │ ├── axis_arb_mux_wrap.py │ │ ├── axis_async_fifo.v │ │ ├── axis_async_fifo_adapter.v │ │ ├── axis_broadcast.v │ │ ├── axis_broadcast_wrap.py │ │ ├── axis_cobs_decode.v │ │ ├── axis_cobs_encode.v │ │ ├── axis_crosspoint.v │ │ ├── axis_crosspoint_wrap.py │ │ ├── axis_demux.v │ │ ├── axis_demux_wrap.py │ │ ├── axis_fifo.v │ │ ├── axis_fifo_adapter.v │ │ ├── axis_frame_join.v │ │ ├── axis_frame_join_wrap.py │ │ ├── axis_frame_len.v │ │ ├── axis_frame_length_adjust.v │ │ ├── axis_frame_length_adjust_fifo.v │ │ ├── axis_ll_bridge.v │ │ ├── axis_mux.v │ │ ├── axis_mux_wrap.py │ │ ├── axis_pipeline_fifo.v │ │ ├── axis_pipeline_register.v │ │ ├── axis_ram_switch.v │ │ ├── axis_ram_switch_wrap.py │ │ ├── axis_rate_limit.v │ │ ├── axis_register.v │ │ ├── axis_srl_fifo.v │ │ ├── axis_srl_register.v │ │ ├── axis_stat_counter.v │ │ ├── axis_switch.v │ │ ├── axis_switch_wrap.py │ │ ├── axis_tap.v │ │ ├── ll_axis_bridge.v │ │ ├── priority_encoder.v │ │ └── sync_reset.v │ ├── syn │ │ ├── quartus │ │ │ ├── axis_async_fifo.sdc │ │ │ └── sync_reset.sdc │ │ ├── quartus_pro │ │ │ ├── axis_async_fifo.sdc │ │ │ └── sync_reset.sdc │ │ └── vivado │ │ │ ├── axis_async_fifo.tcl │ │ │ └── sync_reset.tcl │ ├── tb │ │ ├── Makefile │ │ ├── axis_adapter │ │ │ ├── Makefile │ │ │ └── test_axis_adapter.py │ │ ├── axis_arb_mux │ │ │ ├── Makefile │ │ │ └── test_axis_arb_mux.py │ │ ├── axis_async_fifo │ │ │ ├── Makefile │ │ │ └── test_axis_async_fifo.py │ │ ├── axis_async_fifo_adapter │ │ │ ├── Makefile │ │ │ └── test_axis_async_fifo_adapter.py │ │ ├── axis_broadcast │ │ │ ├── Makefile │ │ │ └── test_axis_broadcast.py │ │ ├── axis_cobs_decode │ │ │ ├── Makefile │ │ │ └── test_axis_cobs_decode.py │ │ ├── axis_cobs_encode │ │ │ ├── Makefile │ │ │ └── test_axis_cobs_encode.py │ │ ├── axis_demux │ │ │ ├── Makefile │ │ │ └── test_axis_demux.py │ │ ├── axis_ep.py │ │ ├── axis_fifo │ │ │ ├── Makefile │ │ │ └── test_axis_fifo.py │ │ ├── axis_fifo_adapter │ │ │ ├── Makefile │ │ │ └── test_axis_fifo_adapter.py │ │ ├── axis_frame_length_adjust │ │ │ ├── Makefile │ │ │ └── test_axis_frame_length_adjust.py │ │ ├── axis_frame_length_adjust_fifo │ │ │ ├── Makefile │ │ │ └── test_axis_frame_length_adjust_fifo.py │ │ ├── axis_mux │ │ │ ├── Makefile │ │ │ └── test_axis_mux.py │ │ ├── axis_pipeline_fifo │ │ │ ├── Makefile │ │ │ └── test_axis_pipeline_fifo.py │ │ ├── axis_pipeline_register │ │ │ ├── Makefile │ │ │ └── test_axis_pipeline_register.py │ │ ├── axis_ram_switch │ │ │ ├── Makefile │ │ │ └── test_axis_ram_switch.py │ │ ├── axis_rate_limit │ │ │ ├── Makefile │ │ │ └── test_axis_rate_limit.py │ │ ├── axis_register │ │ │ ├── Makefile │ │ │ └── test_axis_register.py │ │ ├── axis_srl_fifo │ │ │ ├── Makefile │ │ │ └── test_axis_srl_fifo.py │ │ ├── axis_srl_register │ │ │ ├── Makefile │ │ │ └── test_axis_srl_register.py │ │ ├── axis_switch │ │ │ ├── Makefile │ │ │ └── test_axis_switch.py │ │ ├── ll_ep.py │ │ ├── test_arbiter.py │ │ ├── test_arbiter.v │ │ ├── test_arbiter_rr.py │ │ ├── test_arbiter_rr.v │ │ ├── test_axis_adapter_64_8.py │ │ ├── test_axis_adapter_64_8.v │ │ ├── test_axis_adapter_8_64.py │ │ ├── test_axis_adapter_8_64.v │ │ ├── test_axis_arb_mux_4.py │ │ ├── test_axis_arb_mux_4.v │ │ ├── test_axis_arb_mux_4_64.py │ │ ├── test_axis_arb_mux_4_64.v │ │ ├── test_axis_async_fifo.py │ │ ├── test_axis_async_fifo.v │ │ ├── test_axis_async_fifo_64.py │ │ ├── test_axis_async_fifo_64.v │ │ ├── test_axis_async_fifo_adapter_64_8.py │ │ ├── test_axis_async_fifo_adapter_64_8.v │ │ ├── test_axis_async_fifo_adapter_8_64.py │ │ ├── test_axis_async_fifo_adapter_8_64.v │ │ ├── test_axis_async_frame_fifo.py │ │ ├── test_axis_async_frame_fifo.v │ │ ├── test_axis_async_frame_fifo_64.py │ │ ├── test_axis_async_frame_fifo_64.v │ │ ├── test_axis_broadcast_4.py │ │ ├── test_axis_broadcast_4.v │ │ ├── test_axis_cobs_decode.py │ │ ├── test_axis_cobs_decode.v │ │ ├── test_axis_cobs_encode.py │ │ ├── test_axis_cobs_encode.v │ │ ├── test_axis_cobs_encode_zero_frame.py │ │ ├── test_axis_cobs_encode_zero_frame.v │ │ ├── test_axis_crosspoint_4x4.py │ │ ├── test_axis_crosspoint_4x4.v │ │ ├── test_axis_crosspoint_4x4_64.py │ │ ├── test_axis_crosspoint_4x4_64.v │ │ ├── test_axis_demux_4.py │ │ ├── test_axis_demux_4.v │ │ ├── test_axis_demux_4_64.py │ │ ├── test_axis_demux_4_64.v │ │ ├── test_axis_fifo.py │ │ ├── test_axis_fifo.v │ │ ├── test_axis_fifo_64.py │ │ ├── test_axis_fifo_64.v │ │ ├── test_axis_fifo_adapter_64_8.py │ │ ├── test_axis_fifo_adapter_64_8.v │ │ ├── test_axis_fifo_adapter_8_64.py │ │ ├── test_axis_fifo_adapter_8_64.v │ │ ├── test_axis_frame_fifo.py │ │ ├── test_axis_frame_fifo.v │ │ ├── test_axis_frame_fifo_64.py │ │ ├── test_axis_frame_fifo_64.v │ │ ├── test_axis_frame_join_4.py │ │ ├── test_axis_frame_join_4.v │ │ ├── test_axis_frame_len_64.py │ │ ├── test_axis_frame_len_64.v │ │ ├── test_axis_frame_len_8.py │ │ ├── test_axis_frame_len_8.v │ │ ├── test_axis_frame_length_adjust_64.py │ │ ├── test_axis_frame_length_adjust_64.v │ │ ├── test_axis_frame_length_adjust_8.py │ │ ├── test_axis_frame_length_adjust_8.v │ │ ├── test_axis_frame_length_adjust_fifo.py │ │ ├── test_axis_frame_length_adjust_fifo.v │ │ ├── test_axis_frame_length_adjust_fifo_64.py │ │ ├── test_axis_frame_length_adjust_fifo_64.v │ │ ├── test_axis_ll_bridge.py │ │ ├── test_axis_ll_bridge.v │ │ ├── test_axis_mux_4.py │ │ ├── test_axis_mux_4.v │ │ ├── test_axis_mux_4_64.py │ │ ├── test_axis_mux_4_64.v │ │ ├── test_axis_ram_switch_1x4_256_64.py │ │ ├── test_axis_ram_switch_1x4_256_64.v │ │ ├── test_axis_ram_switch_4x1_64_256.py │ │ ├── test_axis_ram_switch_4x1_64_256.v │ │ ├── test_axis_ram_switch_4x4_64_64.py │ │ ├── test_axis_ram_switch_4x4_64_64.v │ │ ├── test_axis_rate_limit.py │ │ ├── test_axis_rate_limit.v │ │ ├── test_axis_rate_limit_64.py │ │ ├── test_axis_rate_limit_64.v │ │ ├── test_axis_register.py │ │ ├── test_axis_register.v │ │ ├── test_axis_register_64.py │ │ ├── test_axis_register_64.v │ │ ├── test_axis_srl_fifo.py │ │ ├── test_axis_srl_fifo.v │ │ ├── test_axis_srl_fifo_64.py │ │ ├── test_axis_srl_fifo_64.v │ │ ├── test_axis_srl_register.py │ │ ├── test_axis_srl_register.v │ │ ├── test_axis_srl_register_64.py │ │ ├── test_axis_srl_register_64.v │ │ ├── test_axis_stat_counter.py │ │ ├── test_axis_stat_counter.v │ │ ├── test_axis_switch_4x4.py │ │ ├── test_axis_switch_4x4.v │ │ ├── test_axis_switch_4x4_64.py │ │ ├── test_axis_switch_4x4_64.v │ │ ├── test_axis_tap.py │ │ ├── test_axis_tap.v │ │ ├── test_axis_tap_64.py │ │ ├── test_axis_tap_64.v │ │ ├── test_ll_axis_bridge.py │ │ ├── test_ll_axis_bridge.v │ │ ├── test_priority_encoder.py │ │ └── test_priority_encoder.v │ └── tox.ini └── update-axis.sh ├── rtl ├── arp.v ├── arp_cache.v ├── arp_eth_rx.v ├── arp_eth_tx.v ├── axis_baser_rx_64.v ├── axis_baser_tx_64.v ├── axis_eth_fcs.v ├── axis_eth_fcs_check.v ├── axis_eth_fcs_check_64.v ├── axis_eth_fcs_insert.v ├── axis_eth_fcs_insert_64.v ├── axis_gmii_rx.v ├── axis_gmii_tx.v ├── axis_xgmii_rx_32.v ├── axis_xgmii_rx_64.v ├── axis_xgmii_tx_32.v ├── axis_xgmii_tx_64.v ├── eth_arb_mux.v ├── eth_axis_rx.v ├── eth_axis_tx.v ├── eth_demux.v ├── eth_mac_10g.v ├── eth_mac_10g_fifo.v ├── eth_mac_1g.v ├── eth_mac_1g_fifo.v ├── eth_mac_1g_gmii.v ├── eth_mac_1g_gmii_fifo.v ├── eth_mac_1g_rgmii.v ├── eth_mac_1g_rgmii_fifo.v ├── eth_mac_mii.v ├── eth_mac_mii_fifo.v ├── eth_mac_phy_10g.v ├── eth_mac_phy_10g_fifo.v ├── eth_mac_phy_10g_rx.v ├── eth_mac_phy_10g_tx.v ├── eth_mux.v ├── eth_phy_10g.v ├── eth_phy_10g_rx.v ├── eth_phy_10g_rx_ber_mon.v ├── eth_phy_10g_rx_frame_sync.v ├── eth_phy_10g_rx_if.v ├── eth_phy_10g_rx_watchdog.v ├── eth_phy_10g_tx.v ├── eth_phy_10g_tx_if.v ├── gmii_phy_if.v ├── iddr.v ├── ip.v ├── ip_64.v ├── ip_arb_mux.v ├── ip_complete.v ├── ip_complete_64.v ├── ip_demux.v ├── ip_eth_rx.v ├── ip_eth_rx_64.v ├── ip_eth_tx.v ├── ip_eth_tx_64.v ├── ip_mux.v ├── lfsr.v ├── mii_phy_if.v ├── oddr.v ├── ptp_clock.v ├── ptp_clock_cdc.v ├── ptp_perout.v ├── ptp_tag_insert.v ├── ptp_ts_extract.v ├── rgmii_phy_if.v ├── ssio_ddr_in.v ├── ssio_ddr_in_diff.v ├── ssio_ddr_out.v ├── ssio_ddr_out_diff.v ├── ssio_sdr_in.v ├── ssio_sdr_in_diff.v ├── ssio_sdr_out.v ├── ssio_sdr_out_diff.v ├── udp.v ├── udp_64.v ├── udp_arb_mux.v ├── udp_checksum_gen.v ├── udp_checksum_gen_64.v ├── udp_complete.v ├── udp_complete_64.v ├── udp_demux.v ├── udp_ip_rx.v ├── udp_ip_rx_64.v ├── udp_ip_tx.v ├── udp_ip_tx_64.v ├── udp_mux.v ├── xgmii_baser_dec_64.v ├── xgmii_baser_enc_64.v ├── xgmii_deinterleave.v └── xgmii_interleave.v ├── scripts ├── dev-netns-shell.sh └── udp_test.py ├── syn ├── quartus │ ├── eth_mac_1g_gmii.sdc │ ├── eth_mac_1g_rgmii.sdc │ ├── gmii_phy_if.sdc │ ├── mii_phy_if.sdc │ ├── rgmii_io.sdc │ └── rgmii_phy_if.sdc ├── quartus_pro │ ├── eth_mac_1g_gmii.sdc │ ├── eth_mac_1g_rgmii.sdc │ ├── eth_mac_fifo.sdc │ ├── gmii_phy_if.sdc │ ├── mii_phy_if.sdc │ └── rgmii_phy_if.sdc └── vivado │ ├── eth_mac_1g_gmii.tcl │ ├── eth_mac_1g_rgmii.tcl │ ├── eth_mac_fifo.tcl │ ├── gmii_phy_if.tcl │ ├── mii_phy_if.tcl │ ├── ptp_clock_cdc.tcl │ └── rgmii_phy_if.tcl ├── tb ├── arp │ ├── Makefile │ └── test_arp.py ├── arp_cache │ ├── Makefile │ └── test_arp_cache.py ├── arp_ep.py ├── arp_eth_rx │ ├── Makefile │ └── test_arp_eth_rx.py ├── arp_eth_tx │ ├── Makefile │ └── test_arp_eth_tx.py ├── axis_baser_rx_64 │ ├── Makefile │ ├── baser.py │ └── test_axis_baser_rx_64.py ├── axis_baser_tx_64 │ ├── Makefile │ ├── baser.py │ └── test_axis_baser_tx_64.py ├── axis_ep.py ├── axis_gmii_rx │ ├── Makefile │ └── test_axis_gmii_rx.py ├── axis_gmii_tx │ ├── Makefile │ └── test_axis_gmii_tx.py ├── axis_xgmii_rx_32 │ ├── Makefile │ └── test_axis_xgmii_rx_32.py ├── axis_xgmii_rx_64 │ ├── Makefile │ └── test_axis_xgmii_rx_64.py ├── axis_xgmii_tx_32 │ ├── Makefile │ └── test_axis_xgmii_tx_32.py ├── axis_xgmii_tx_64 │ ├── Makefile │ └── test_axis_xgmii_tx_64.py ├── baser.py ├── baser_serdes_ep.py ├── eth_axis_rx │ ├── Makefile │ └── test_eth_axis_rx.py ├── eth_axis_tx │ ├── Makefile │ └── test_eth_axis_tx.py ├── eth_ep.py ├── eth_mac_10g │ ├── Makefile │ └── test_eth_mac_10g.py ├── eth_mac_10g_fifo │ ├── Makefile │ └── test_eth_mac_10g_fifo.py ├── eth_mac_1g │ ├── Makefile │ └── test_eth_mac_1g.py ├── eth_mac_1g_fifo │ ├── Makefile │ └── test_eth_mac_1g_fifo.py ├── eth_mac_1g_gmii │ ├── Makefile │ └── test_eth_mac_1g_gmii.py ├── eth_mac_1g_gmii_fifo │ ├── Makefile │ └── test_eth_mac_1g_gmii_fifo.py ├── eth_mac_1g_rgmii │ ├── Makefile │ └── test_eth_mac_1g_rgmii.py ├── eth_mac_1g_rgmii_fifo │ ├── Makefile │ └── test_eth_mac_1g_rgmii_fifo.py ├── eth_mac_mii │ ├── Makefile │ └── test_eth_mac_mii.py ├── eth_mac_mii_fifo │ ├── Makefile │ └── test_eth_mac_mii_fifo.py ├── eth_mac_phy_10g │ ├── Makefile │ ├── baser.py │ └── test_eth_mac_phy_10g.py ├── eth_mac_phy_10g_fifo │ ├── Makefile │ ├── baser.py │ └── test_eth_mac_phy_10g_fifo.py ├── eth_phy_10g │ ├── Makefile │ ├── baser.py │ └── test_eth_phy_10g.py ├── gmii_ep.py ├── ip_ep.py ├── mii_ep.py ├── ptp.py ├── ptp_clock │ ├── Makefile │ └── test_ptp_clock.py ├── ptp_clock_cdc │ ├── Makefile │ └── test_ptp_clock_cdc.py ├── ptp_perout │ ├── Makefile │ └── test_ptp_perout.py ├── rgmii_ep.py ├── test_arp.py ├── test_arp.v ├── test_arp_64.py ├── test_arp_64.v ├── test_arp_cache.py ├── test_arp_cache.v ├── test_arp_eth_rx.py ├── test_arp_eth_rx.v ├── test_arp_eth_rx_64.py ├── test_arp_eth_rx_64.v ├── test_arp_eth_tx.py ├── test_arp_eth_tx.v ├── test_arp_eth_tx_64.py ├── test_arp_eth_tx_64.v ├── test_axis_baser_rx_64.py ├── test_axis_baser_rx_64.v ├── test_axis_baser_tx_64.py ├── test_axis_baser_tx_64.v ├── test_axis_eth_fcs.py ├── test_axis_eth_fcs.v ├── test_axis_eth_fcs_64.py ├── test_axis_eth_fcs_64.v ├── test_axis_eth_fcs_check.py ├── test_axis_eth_fcs_check.v ├── test_axis_eth_fcs_check_64.py ├── test_axis_eth_fcs_check_64.v ├── test_axis_eth_fcs_insert.py ├── test_axis_eth_fcs_insert.v ├── test_axis_eth_fcs_insert_64.py ├── test_axis_eth_fcs_insert_64.v ├── test_axis_eth_fcs_insert_64_pad.py ├── test_axis_eth_fcs_insert_64_pad.v ├── test_axis_eth_fcs_insert_pad.py ├── test_axis_eth_fcs_insert_pad.v ├── test_axis_gmii_rx.py ├── test_axis_gmii_rx.v ├── test_axis_gmii_tx.py ├── test_axis_gmii_tx.v ├── test_axis_xgmii_rx_32.py ├── test_axis_xgmii_rx_32.v ├── test_axis_xgmii_rx_64.py ├── test_axis_xgmii_rx_64.v ├── test_axis_xgmii_tx_32.py ├── test_axis_xgmii_tx_32.v ├── test_axis_xgmii_tx_64.py ├── test_axis_xgmii_tx_64.v ├── test_eth_arb_mux_4.py ├── test_eth_arb_mux_4.v ├── test_eth_arb_mux_64_4.py ├── test_eth_arb_mux_64_4.v ├── test_eth_axis_rx.py ├── test_eth_axis_rx.v ├── test_eth_axis_rx_64.py ├── test_eth_axis_rx_64.v ├── test_eth_axis_tx.py ├── test_eth_axis_tx.v ├── test_eth_axis_tx_64.py ├── test_eth_axis_tx_64.v ├── test_eth_demux_4.py ├── test_eth_demux_4.v ├── test_eth_demux_64_4.py ├── test_eth_demux_64_4.v ├── test_eth_mac_10g_32.py ├── test_eth_mac_10g_32.v ├── test_eth_mac_10g_64.py ├── test_eth_mac_10g_64.v ├── test_eth_mac_10g_fifo_32.py ├── test_eth_mac_10g_fifo_32.v ├── test_eth_mac_10g_fifo_64.py ├── test_eth_mac_10g_fifo_64.v ├── test_eth_mac_10g_fifo_ptp_32.py ├── test_eth_mac_10g_fifo_ptp_32.v ├── test_eth_mac_10g_fifo_ptp_64.py ├── test_eth_mac_10g_fifo_ptp_64.v ├── test_eth_mac_1g.py ├── test_eth_mac_1g.v ├── test_eth_mac_1g_fifo.py ├── test_eth_mac_1g_fifo.v ├── test_eth_mac_1g_gmii.py ├── test_eth_mac_1g_gmii.v ├── test_eth_mac_1g_gmii_fifo.py ├── test_eth_mac_1g_gmii_fifo.v ├── test_eth_mac_1g_rgmii.py ├── test_eth_mac_1g_rgmii.v ├── test_eth_mac_1g_rgmii_fifo.py ├── test_eth_mac_1g_rgmii_fifo.v ├── test_eth_mac_mii.py ├── test_eth_mac_mii.v ├── test_eth_mac_mii_fifo.py ├── test_eth_mac_mii_fifo.v ├── test_eth_mac_phy_10g.py ├── test_eth_mac_phy_10g.v ├── test_eth_mac_phy_10g_fifo.py ├── test_eth_mac_phy_10g_fifo.v ├── test_eth_mac_phy_10g_fifo_ptp.py ├── test_eth_mac_phy_10g_fifo_ptp.v ├── test_eth_mux_4.py ├── test_eth_mux_4.v ├── test_eth_mux_64_4.py ├── test_eth_mux_64_4.v ├── test_eth_phy_10g_64.py ├── test_eth_phy_10g_64.v ├── test_eth_phy_10g_rx_64.py ├── test_eth_phy_10g_rx_64.v ├── test_eth_phy_10g_tx_64.py ├── test_eth_phy_10g_tx_64.v ├── test_ip.py ├── test_ip.v ├── test_ip_64.py ├── test_ip_64.v ├── test_ip_arb_mux_4.py ├── test_ip_arb_mux_4.v ├── test_ip_arb_mux_64_4.py ├── test_ip_arb_mux_64_4.v ├── test_ip_complete.py ├── test_ip_complete.v ├── test_ip_complete_64.py ├── test_ip_complete_64.v ├── test_ip_demux_4.py ├── test_ip_demux_4.v ├── test_ip_demux_64_4.py ├── test_ip_demux_64_4.v ├── test_ip_eth_rx.py ├── test_ip_eth_rx.v ├── test_ip_eth_rx_64.py ├── test_ip_eth_rx_64.v ├── test_ip_eth_tx.py ├── test_ip_eth_tx.v ├── test_ip_eth_tx_64.py ├── test_ip_eth_tx_64.v ├── test_ip_mux_4.py ├── test_ip_mux_4.v ├── test_ip_mux_64_4.py ├── test_ip_mux_64_4.v ├── test_ptp_clock.py ├── test_ptp_clock.v ├── test_ptp_clock_cdc_64.py ├── test_ptp_clock_cdc_64.v ├── test_ptp_clock_cdc_96.py ├── test_ptp_clock_cdc_96.v ├── test_ptp_perout.py ├── test_ptp_perout.v ├── test_udp.py ├── test_udp.v ├── test_udp_64.py ├── test_udp_64.v ├── test_udp_arb_mux_4.py ├── test_udp_arb_mux_4.v ├── test_udp_arb_mux_64_4.py ├── test_udp_arb_mux_64_4.v ├── test_udp_checksum_gen.py ├── test_udp_checksum_gen.v ├── test_udp_checksum_gen_64.py ├── test_udp_checksum_gen_64.v ├── test_udp_complete.py ├── test_udp_complete.v ├── test_udp_complete_64.py ├── test_udp_complete_64.v ├── test_udp_demux_4.py ├── test_udp_demux_4.v ├── test_udp_demux_64_4.py ├── test_udp_demux_64_4.v ├── test_udp_ip_rx.py ├── test_udp_ip_rx.v ├── test_udp_ip_rx_64.py ├── test_udp_ip_rx_64.v ├── test_udp_ip_tx.py ├── test_udp_ip_tx.v ├── test_udp_ip_tx_64.py ├── test_udp_ip_tx_64.v ├── test_udp_mux_4.py ├── test_udp_mux_4.v ├── test_udp_mux_64_4.py ├── test_udp_mux_64_4.v ├── test_xgmii_baser_dec_64.py ├── test_xgmii_baser_dec_64.v ├── test_xgmii_baser_enc_64.py ├── test_xgmii_baser_enc_64.v ├── udp_ep.py ├── xgmii_baser_dec_64 │ ├── Makefile │ ├── baser.py │ └── test_xgmii_baser_dec_64.py ├── xgmii_baser_enc_64 │ ├── Makefile │ ├── baser.py │ └── test_xgmii_baser_enc_64.py └── xgmii_ep.py └── tox.ini /.github/workflows/regression-tests.yml: -------------------------------------------------------------------------------- 1 | name: Regression Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | build: 7 | name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10) 8 | runs-on: ubuntu-22.04 9 | 10 | strategy: 11 | matrix: 12 | python-version: ["3.10"] 13 | group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10] 14 | 15 | steps: 16 | - uses: actions/checkout@v3 17 | 18 | - name: Set up Python ${{ matrix.python-version }} 19 | uses: actions/setup-python@v4 20 | with: 21 | python-version: ${{ matrix.python-version }} 22 | 23 | - name: Install Icarus Verilog 24 | run: | 25 | sudo apt install -y --no-install-recommends iverilog 26 | 27 | - name: Install Python dependencies 28 | run: | 29 | python -m pip install --upgrade pip 30 | pip install tox tox-gh-actions 31 | 32 | - name: Test with tox 33 | run: tox -- -n auto --verbose --splits 10 --group ${{ matrix.group }} --splitting-algorithm least_duration 34 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.lxt 3 | *.pyc 4 | *.vvp 5 | *.kate-swp 6 | 7 | -------------------------------------------------------------------------------- /AUTHORS: -------------------------------------------------------------------------------- 1 | Alex Forencich 2 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | Copyright (c) 2014-2018 Alex Forencich 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in 11 | all copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | THE SOFTWARE. 20 | -------------------------------------------------------------------------------- /example/520N_MX/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet BittWare 520N-MX Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the BittWare 520N-MX board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: 1SM21CHU2F53E2VG 12 | * PHY: Transceiver in 10G BASE-R native mode 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Intel Quartus Prime Pro toolchain 17 | components are in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the board with the Intel software. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/520N_MX/fpga_10g/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 20.4 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {1SM21CHU2F53E2VG} 8 | set_project_property DEVICE_FAMILY {Stratix 10} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # add the exports 22 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 23 | 24 | # set values for exposed HDL parameters 25 | 26 | # set the the module properties 27 | set_module_property BONUS_DATA { 28 | 29 | 30 | 31 | 32 | 33 | } 34 | set_module_property FILE {reset_release.ip} 35 | set_module_property GENERATION_ID {0x00000000} 36 | set_module_property NAME {reset_release} 37 | 38 | # save the system 39 | sync_sysinfo_parameters 40 | save_system reset_release 41 | } 42 | 43 | proc do_set_exported_interface_sysinfo_parameters {} { 44 | } 45 | 46 | # create all the systems, from bottom up 47 | do_create_reset_release 48 | 49 | # set system info parameters on exported interface, from bottom up 50 | do_set_exported_interface_sysinfo_parameters 51 | -------------------------------------------------------------------------------- /example/520N_MX/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/520N_MX/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ADM-PCIE-9V3 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcvu3p-ffvc1517-2-i 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_25g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ADM-PCIE-9V3 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcvu3p-ffvc1517-2-i 12 | * PHY: 25G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the ADM-PCIE-9V3 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_25g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ATLYS/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ATLYS/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Atlys Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Digilent Atlys FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: XC6SLX45CSG324-2 12 | * PHY: Marvell 88E1111 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx ISE toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Atlys board with the Digilent command line 22 | tools. Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | -------------------------------------------------------------------------------- /example/ATLYS/fpga/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_int" TNM = "ffs_clk_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_int_to_gmii_rx_clk" = FROM "ffs_clk_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_int" 10 ns; 7 | -------------------------------------------------------------------------------- /example/ATLYS/fpga/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_PART = xc6slx45-2csg324 4 | FPGA_TOP = fpga 5 | FPGA_ARCH = spartan6 6 | 7 | # PROM settings 8 | #PROM = xc18v04 9 | #SPI_PROM_SIZE = (in bytes) 10 | 11 | # Files for synthesis 12 | SYN_FILES = rtl/fpga.v 13 | SYN_FILES += rtl/fpga_core.v 14 | SYN_FILES += rtl/debounce_switch.v 15 | SYN_FILES += rtl/sync_signal.v 16 | SYN_FILES += lib/eth/rtl/iddr.v 17 | SYN_FILES += lib/eth/rtl/oddr.v 18 | SYN_FILES += lib/eth/rtl/ssio_sdr_in.v 19 | SYN_FILES += lib/eth/rtl/ssio_sdr_out.v 20 | SYN_FILES += lib/eth/rtl/gmii_phy_if.v 21 | SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii_fifo.v 22 | SYN_FILES += lib/eth/rtl/eth_mac_1g_gmii.v 23 | SYN_FILES += lib/eth/rtl/eth_mac_1g.v 24 | SYN_FILES += lib/eth/rtl/axis_gmii_rx.v 25 | SYN_FILES += lib/eth/rtl/axis_gmii_tx.v 26 | SYN_FILES += lib/eth/rtl/lfsr.v 27 | SYN_FILES += lib/eth/rtl/eth_axis_rx.v 28 | SYN_FILES += lib/eth/rtl/eth_axis_tx.v 29 | SYN_FILES += lib/eth/rtl/udp_complete.v 30 | SYN_FILES += lib/eth/rtl/udp_checksum_gen.v 31 | SYN_FILES += lib/eth/rtl/udp.v 32 | SYN_FILES += lib/eth/rtl/udp_ip_rx.v 33 | SYN_FILES += lib/eth/rtl/udp_ip_tx.v 34 | SYN_FILES += lib/eth/rtl/ip_complete.v 35 | SYN_FILES += lib/eth/rtl/ip.v 36 | SYN_FILES += lib/eth/rtl/ip_eth_rx.v 37 | SYN_FILES += lib/eth/rtl/ip_eth_tx.v 38 | SYN_FILES += lib/eth/rtl/ip_arb_mux.v 39 | SYN_FILES += lib/eth/rtl/arp.v 40 | SYN_FILES += lib/eth/rtl/arp_cache.v 41 | SYN_FILES += lib/eth/rtl/arp_eth_rx.v 42 | SYN_FILES += lib/eth/rtl/arp_eth_tx.v 43 | SYN_FILES += lib/eth/rtl/eth_arb_mux.v 44 | SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v 45 | SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v 46 | SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v 47 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v 48 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v 49 | SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v 50 | #SYN_FILES += coregen/dcm_i100_o125/dcm_i100_o125.v 51 | 52 | # UCF files 53 | UCF_FILES = fpga.ucf 54 | UCF_FILES += clock.ucf 55 | 56 | # NGC paths for ngdbuild 57 | #NGC_PATHS = coregen/dcm_i100_o125 58 | 59 | # Bitgen options 60 | BITGEN_OPTIONS = -g StartupClk:Cclk -g ConfigRate:26 61 | 62 | include ../common/xilinx.mk 63 | 64 | program: $(FPGA_TOP).bit 65 | djtgcfg prog -d Atlys --index 0 --file $(FPGA_TOP).bit 66 | 67 | -------------------------------------------------------------------------------- /example/ATLYS/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ATLYS/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU200/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/AU200/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Alveo U200 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U200 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcu200-fsgd2104-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Alveo U200 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/AU200/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU200/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU250/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/AU250/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Alveo U250 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U250 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcu250-figd2104-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Alveo U250 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/AU250/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU250/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU280/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/AU280/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Alveo U280 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U280 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcu280-fsvh2892-2L-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Alveo U280 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/AU280/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU280/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU50/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/AU50/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Alveo U50 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U50 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcu50-fsvh2104-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Alveo U50 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/AU50/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU50/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/Arty/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/Arty/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Arty Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Digilent Arty FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: XC7A35TICSG324-1L 12 | * PHY: TI DP83848J 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Arty board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/Arty/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/Arty/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/C10LP/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /example/C10LP/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Cyclone 10 LP Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Intel Cyclone 10 LP FPGA development board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: 5SGXEA7N2F45C2 12 | * PHY: Intel XWAY PHY11G PEF7071 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Altera Quartus toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the board with the Altera software. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/C10LP/fpga/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Cyclone 10 LP" 5 | FPGA_DEVICE = 10CL025YU256I7G 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/debounce_switch.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += lib/eth/rtl/iddr.v 13 | SYN_FILES += lib/eth/rtl/oddr.v 14 | SYN_FILES += lib/eth/rtl/ssio_ddr_in.v 15 | SYN_FILES += lib/eth/rtl/ssio_ddr_out.v 16 | SYN_FILES += lib/eth/rtl/rgmii_phy_if.v 17 | SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v 18 | SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v 19 | SYN_FILES += lib/eth/rtl/eth_mac_1g.v 20 | SYN_FILES += lib/eth/rtl/axis_gmii_rx.v 21 | SYN_FILES += lib/eth/rtl/axis_gmii_tx.v 22 | SYN_FILES += lib/eth/rtl/lfsr.v 23 | SYN_FILES += lib/eth/rtl/eth_axis_rx.v 24 | SYN_FILES += lib/eth/rtl/eth_axis_tx.v 25 | SYN_FILES += lib/eth/rtl/udp_complete.v 26 | SYN_FILES += lib/eth/rtl/udp_checksum_gen.v 27 | SYN_FILES += lib/eth/rtl/udp.v 28 | SYN_FILES += lib/eth/rtl/udp_ip_rx.v 29 | SYN_FILES += lib/eth/rtl/udp_ip_tx.v 30 | SYN_FILES += lib/eth/rtl/ip_complete.v 31 | SYN_FILES += lib/eth/rtl/ip.v 32 | SYN_FILES += lib/eth/rtl/ip_eth_rx.v 33 | SYN_FILES += lib/eth/rtl/ip_eth_tx.v 34 | SYN_FILES += lib/eth/rtl/ip_arb_mux.v 35 | SYN_FILES += lib/eth/rtl/ip_mux.v 36 | SYN_FILES += lib/eth/rtl/arp.v 37 | SYN_FILES += lib/eth/rtl/arp_cache.v 38 | SYN_FILES += lib/eth/rtl/arp_eth_rx.v 39 | SYN_FILES += lib/eth/rtl/arp_eth_tx.v 40 | SYN_FILES += lib/eth/rtl/eth_arb_mux.v 41 | SYN_FILES += lib/eth/rtl/eth_mux.v 42 | SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v 43 | SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v 44 | SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v 45 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v 46 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v 47 | SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v 48 | 49 | # QSF files 50 | QSF_FILES = fpga.qsf 51 | 52 | # SDC files 53 | SDC_FILES = fpga.sdc 54 | 55 | include ../common/quartus.mk 56 | 57 | program: fpga 58 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof" 59 | -------------------------------------------------------------------------------- /example/C10LP/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/C10LP/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/DE2-115/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /example/DE2-115/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet DE2-115 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Terasic DE2-115 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: EP4CE115F29C7 12 | * PHY: Marvell Alaska 88E1111 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Altera Quartus toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the board with the Altera software. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/DE2-115/fpga/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Cyclone IV E" 5 | FPGA_DEVICE = EP4CE115F29C7 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/debounce_switch.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/hex_display.v 13 | SYN_FILES += lib/eth/rtl/iddr.v 14 | SYN_FILES += lib/eth/rtl/oddr.v 15 | SYN_FILES += lib/eth/rtl/ssio_ddr_in.v 16 | SYN_FILES += lib/eth/rtl/ssio_ddr_out.v 17 | SYN_FILES += lib/eth/rtl/rgmii_phy_if.v 18 | SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v 19 | SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v 20 | SYN_FILES += lib/eth/rtl/eth_mac_1g.v 21 | SYN_FILES += lib/eth/rtl/axis_gmii_rx.v 22 | SYN_FILES += lib/eth/rtl/axis_gmii_tx.v 23 | SYN_FILES += lib/eth/rtl/lfsr.v 24 | SYN_FILES += lib/eth/rtl/eth_axis_rx.v 25 | SYN_FILES += lib/eth/rtl/eth_axis_tx.v 26 | SYN_FILES += lib/eth/rtl/udp_complete.v 27 | SYN_FILES += lib/eth/rtl/udp_checksum_gen.v 28 | SYN_FILES += lib/eth/rtl/udp.v 29 | SYN_FILES += lib/eth/rtl/udp_ip_rx.v 30 | SYN_FILES += lib/eth/rtl/udp_ip_tx.v 31 | SYN_FILES += lib/eth/rtl/ip_complete.v 32 | SYN_FILES += lib/eth/rtl/ip.v 33 | SYN_FILES += lib/eth/rtl/ip_eth_rx.v 34 | SYN_FILES += lib/eth/rtl/ip_eth_tx.v 35 | SYN_FILES += lib/eth/rtl/ip_arb_mux.v 36 | SYN_FILES += lib/eth/rtl/ip_mux.v 37 | SYN_FILES += lib/eth/rtl/arp.v 38 | SYN_FILES += lib/eth/rtl/arp_cache.v 39 | SYN_FILES += lib/eth/rtl/arp_eth_rx.v 40 | SYN_FILES += lib/eth/rtl/arp_eth_tx.v 41 | SYN_FILES += lib/eth/rtl/eth_arb_mux.v 42 | SYN_FILES += lib/eth/rtl/eth_mux.v 43 | SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v 44 | SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v 45 | SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v 46 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v 47 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v 48 | SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v 49 | 50 | # QSF files 51 | QSF_FILES = fpga.qsf 52 | 53 | # SDC files 54 | SDC_FILES = fpga.sdc 55 | 56 | include ../common/quartus.mk 57 | 58 | program: fpga 59 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof" 60 | -------------------------------------------------------------------------------- /example/DE2-115/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/DE2-115/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/DE5-Net/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = cores fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /example/DE5-Net/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet DE5-Net Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Terasic DE5-Net FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: 5SGXEA7N2F45C2 12 | * PHY: 10G BASE-R PHY MegaCore 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Altera Quartus toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the DE5-Net board with the Altera software. Then 22 | run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | -------------------------------------------------------------------------------- /example/DE5-Net/fpga/cores/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | QMEGAWIZ=qmegawiz 3 | 4 | # Sources 5 | QMWSRC=phy.v 6 | QMWSRC+=phy_reconfig.v 7 | 8 | # Targets 9 | TARGETS=$(QMWSRC:.v=) 10 | 11 | # Rules 12 | .PHONY: all 13 | all: $(TARGETS) 14 | 15 | .PHONY: clean 16 | clean: 17 | -rm -rf $(TARGETS) 18 | 19 | %: %.v 20 | mkdir -p $@ 21 | cp -a $< $@ 22 | cd $@ && $(QMEGAWIZ) -silent $< 23 | 24 | -------------------------------------------------------------------------------- /example/DE5-Net/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/DE5-Net/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ExaNIC X10 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X10 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcku035-fbva676-2-c 12 | * PHY: 10G BASE-R PHY IP core and internal GTH transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the ExaNIC X10 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ExaNIC X25 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X25 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcku3p-ffvb676-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the ExaNIC X25 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/HTG9200/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet HTG-9200 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the HiTech Global HTG-9200 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcvu9p-flgb2104-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the HTG-9200 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/HTG9200/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/HTG9200/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2017 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/HXT100G/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = coregen fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/HXT100G/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet HXT100G Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the HiTech Global HXT100G FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: XC6VHX565T-2FFG1923 12 | * PHY: 10G BASE-R PHY IP core and internal GTH transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx ISE toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the HXT100G board with the Xilinx Impact software. 22 | Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | -------------------------------------------------------------------------------- /example/HXT100G/fpga/coregen/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | COREGEN:=coregen 3 | XAW2VERILOG:=xaw2verilog 4 | 5 | # Source 6 | XCO:=ten_gig_eth_pcs_pma_v2_6.xco ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco 7 | XAW:= 8 | 9 | # Targets 10 | TARGETS += $(XCO:.xco=) 11 | TARGETS += $(XAW:.xaw=) 12 | 13 | # Rules 14 | .PHONY: all 15 | all: $(TARGETS) 16 | 17 | .PHONY: clean 18 | clean: 19 | -rm -rf $(TARGETS) 20 | 21 | %: %.xco 22 | $(eval $@_TMP := $(shell mktemp -d)) 23 | cp -a coregen.cgp $($@_TMP) 24 | cp -a $< $($@_TMP) 25 | cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<) 26 | mv $($@_TMP) $@ 27 | 28 | %: %.xaw 29 | $(eval $@_TMP := $(shell mktemp -d)) 30 | cp -a coregen.cgp $($@_TMP) 31 | cp -a $< $($@_TMP) 32 | cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*) 33 | mv $($@_TMP) $@ 34 | -------------------------------------------------------------------------------- /example/HXT100G/fpga/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Wed Apr 1 17:38:18 2015 2 | 3 | SET addpads = false 4 | SET asysymbol = true 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = Verilog 8 | SET device = xc6vhx565t 9 | SET devicefamily = virtex6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = ff1923 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -2 18 | SET verilogsim = true 19 | SET vhdlsim = false 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 3d2f7d04 23 | -------------------------------------------------------------------------------- /example/HXT100G/fpga/coregen/ten_gig_eth_pcs_pma_v2_6.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Wed Apr 1 17:39:05 2015 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:ten_gig_eth_pcs_pma:2.6 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vhx565t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1923 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Ten_Gigabit_Ethernet_PCS/PMA_(10GBASE-R/KR) xilinx.com:ip:ten_gig_eth_pcs_pma:2.6 40 | # END Select 41 | # BEGIN Parameters 42 | CSET autonegotiation=false 43 | CSET base_kr=BASE-R 44 | CSET component_name=ten_gig_eth_pcs_pma_v2_6 45 | CSET fec=false 46 | CSET ieee_1588=None 47 | CSET mdio_management=false 48 | # END Parameters 49 | # BEGIN Extra information 50 | MISC pkg_timestamp=2012-10-08T14:58:05Z 51 | # END Extra information 52 | GENERATE 53 | # CRC: d3dbdcf5 54 | -------------------------------------------------------------------------------- /example/HXT100G/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/HXT100G/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = coregen fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet HXT100G Crosspoint Switch Design 2 | 3 | ## Introduction 4 | 5 | This design targets the HiTech Global HXT100G FPGA board. 6 | 7 | The design forms a 16x16 crosspoint switch for 10G Ethernet. It is capable of 8 | connecting any output port to any input port based on configuration frames 9 | received over a dedicated configuration interface. 10 | 11 | * FPGA: XC6VHX565T-2FFG1923 12 | * PHY: 10G BASE-R PHY IP core and internal GTH transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx ISE toolchain components are 17 | in PATH. 18 | 19 | ## How to use 20 | 21 | SFP left ports 0-7 are connected to crosspoint input/output ports 0-7, SFP 22 | right ports 0-7 are connected to crosspoint input/output ports 8-15. SFP port 23 | left 11 is the control port. Send an Ethernet frame with ethtype 0x8099 to 24 | this port to reconfigure the switch, the first 16 payload bytes corresponding 25 | to the 16 switch output ports, each byte selecting which input port will be 26 | connected. It is possible to connect multiple output ports to the same input 27 | port. 28 | -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/coregen/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | COREGEN:=coregen 3 | XAW2VERILOG:=xaw2verilog 4 | 5 | # Source 6 | XCO:=ten_gig_eth_pcs_pma_v2_6.xco ten_gig_eth_pcs_pma_v2_6_v6gth_wrapper.xco 7 | XAW:= 8 | 9 | # Targets 10 | TARGETS += $(XCO:.xco=) 11 | TARGETS += $(XAW:.xaw=) 12 | 13 | # Rules 14 | .PHONY: all 15 | all: $(TARGETS) 16 | 17 | .PHONY: clean 18 | clean: 19 | -rm -rf $(TARGETS) 20 | 21 | %: %.xco 22 | $(eval $@_TMP := $(shell mktemp -d)) 23 | cp -a coregen.cgp $($@_TMP) 24 | cp -a $< $($@_TMP) 25 | cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<) 26 | mv $($@_TMP) $@ 27 | 28 | %: %.xaw 29 | $(eval $@_TMP := $(shell mktemp -d)) 30 | cp -a coregen.cgp $($@_TMP) 31 | cp -a $< $($@_TMP) 32 | cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*) 33 | mv $($@_TMP) $@ 34 | -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Wed Apr 1 17:38:18 2015 2 | 3 | SET addpads = false 4 | SET asysymbol = true 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = Verilog 8 | SET device = xc6vhx565t 9 | SET devicefamily = virtex6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = ff1923 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -2 18 | SET verilogsim = true 19 | SET vhdlsim = false 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 3d2f7d04 23 | -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/coregen/ten_gig_eth_pcs_pma_v2_6.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Wed Apr 1 17:39:05 2015 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:ten_gig_eth_pcs_pma:2.6 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vhx565t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1923 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Ten_Gigabit_Ethernet_PCS/PMA_(10GBASE-R/KR) xilinx.com:ip:ten_gig_eth_pcs_pma:2.6 40 | # END Select 41 | # BEGIN Parameters 42 | CSET autonegotiation=false 43 | CSET base_kr=BASE-R 44 | CSET component_name=ten_gig_eth_pcs_pma_v2_6 45 | CSET fec=false 46 | CSET ieee_1588=None 47 | CSET mdio_management=false 48 | # END Parameters 49 | # BEGIN Extra information 50 | MISC pkg_timestamp=2012-10-08T14:58:05Z 51 | # END Extra information 52 | GENERATE 53 | # CRC: d3dbdcf5 54 | -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/HXT100G/fpga_cxpt16/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/KC705/fpga_gmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/KC705/fpga_gmii/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet KC705 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx KC705 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | Configure the PHY for GMII by placing J29 and J30 across pins 1 and 2 and 12 | opening J64. 13 | 14 | * FPGA: XC7K325T-2FFG900C 15 | * PHY: Marvell 88E1111 16 | 17 | ## How to build 18 | 19 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 20 | in PATH. 21 | 22 | ## How to test 23 | 24 | Run make program to program the KC705 board with Vivado. Then run 25 | 26 | netcat -u 192.168.1.128 1234 27 | 28 | to open a UDP connection to port 1234. Any text entered into netcat will be 29 | echoed back after pressing enter. 30 | 31 | It is also possible to use hping to test the design by running 32 | 33 | hping 192.168.1.128 -2 -p 1234 -d 1024 34 | -------------------------------------------------------------------------------- /example/KC705/fpga_gmii/clock.xdc: -------------------------------------------------------------------------------- 1 | # Clock constraints 2 | 3 | # BUFGMUX outputs 4 | set_clock_groups -physically_exclusive -group clk_mmcm_out -group phy_tx_clk 5 | -------------------------------------------------------------------------------- /example/KC705/fpga_gmii/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/KC705/fpga_gmii/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/KC705/fpga_rgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/KC705/fpga_rgmii/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet KC705 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx KC705 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | Configure the PHY for RGMII by placing J29 across pins 1 and 2, opening J30, 12 | and shorting J64. 13 | 14 | * FPGA: XC7K325T-2FFG900C 15 | * PHY: Marvell 88E1111 16 | 17 | ## How to build 18 | 19 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 20 | in PATH. 21 | 22 | ## How to test 23 | 24 | Run make program to program the KC705 board with Vivado. Then run 25 | 26 | netcat -u 192.168.1.128 1234 27 | 28 | to open a UDP connection to port 1234. Any text entered into netcat will be 29 | echoed back after pressing enter. 30 | 31 | It is also possible to use hping to test the design by running 32 | 33 | hping 192.168.1.128 -2 -p 1234 -d 1024 34 | -------------------------------------------------------------------------------- /example/KC705/fpga_rgmii/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | # IDELAY on RGMII from PHY chip 4 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 5 | 6 | -------------------------------------------------------------------------------- /example/KC705/fpga_rgmii/fpga/generate_bit_iodelay.tcl: -------------------------------------------------------------------------------- 1 | open_project fpga.xpr 2 | open_run impl_1 3 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 4 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 5 | write_bitstream -force fpga.bit 6 | exit 7 | -------------------------------------------------------------------------------- /example/KC705/fpga_rgmii/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/KC705/fpga_rgmii/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/KC705/fpga_sgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/KC705/fpga_sgmii/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet KC705 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx KC705 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | Configure the PHY for SGMII by placing J29 and J30 across pins 2 and 3 and 12 | opening J64. 13 | 14 | * FPGA: XC7K325T-2FFG900C 15 | * PHY: Marvell 88E1111 16 | 17 | ## How to build 18 | 19 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 20 | in PATH. 21 | 22 | ## How to test 23 | 24 | Run make program to program the KC705 board with Vivado. Then run 25 | 26 | netcat -u 192.168.1.128 1234 27 | 28 | to open a UDP connection to port 1234. Any text entered into netcat will be 29 | echoed back after pressing enter. 30 | 31 | It is also possible to use hping to test the design by running 32 | 33 | hping 192.168.1.128 -2 -p 1234 -d 1024 34 | -------------------------------------------------------------------------------- /example/KC705/fpga_sgmii/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {Transceiver} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | ] [get_ips gig_ethernet_pcs_pma_0] 10 | -------------------------------------------------------------------------------- /example/KC705/fpga_sgmii/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/KC705/fpga_sgmii/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ML605/fpga_gmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ML605/fpga_gmii/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ML605 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ML605 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | Configure the PHY for GMII by placing J66 and J67 across pins 1 and 2 and 12 | opening J68. 13 | 14 | * FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 15 | * PHY: Marvell M88E1111 16 | 17 | ## How to build 18 | 19 | Run make to build. Ensure that the Xilinx ISE toolchain components are 20 | in PATH. 21 | 22 | ## How to test 23 | 24 | Run make program to program the ML605 board with the Xilinx Impact software. 25 | Then run 26 | 27 | netcat -u 192.168.1.128 1234 28 | 29 | to open a UDP connection to port 1234. Any text entered into netcat will be 30 | echoed back after pressing enter. 31 | 32 | It is also possible to use hping to test the design by running 33 | 34 | hping 192.168.1.128 -2 -p 1234 -d 1024 35 | -------------------------------------------------------------------------------- /example/ML605/fpga_gmii/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns; 7 | -------------------------------------------------------------------------------- /example/ML605/fpga_gmii/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ML605/fpga_gmii/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ML605/fpga_rgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ML605/fpga_rgmii/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ML605 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ML605 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | Configure the PHY for RGMII by placing J66 across pins 1 and 2, opening J67, 12 | and shorting J68. 13 | 14 | * FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 15 | * PHY: Marvell M88E1111 16 | 17 | ## How to build 18 | 19 | Run make to build. Ensure that the Xilinx ISE toolchain components are 20 | in PATH. 21 | 22 | ## How to test 23 | 24 | Run make program to program the ML605 board with the Xilinx Impact software. 25 | Then run 26 | 27 | netcat -u 192.168.1.128 1234 28 | 29 | to open a UDP connection to port 1234. Any text entered into netcat will be 30 | echoed back after pressing enter. 31 | 32 | It is also possible to use hping to test the design by running 33 | 34 | hping 192.168.1.128 -2 -p 1234 -d 1024 35 | -------------------------------------------------------------------------------- /example/ML605/fpga_rgmii/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns; 7 | -------------------------------------------------------------------------------- /example/ML605/fpga_rgmii/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ML605/fpga_rgmii/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = coregen fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ML605 SGMII Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ML605 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | Configure the PHY for SGMII by placing J66 and J67 across pins 2 and 3 and 12 | opening J68. 13 | 14 | * FPGA: XC6VLX130T-1FF1156 or XC6VLX240T-1FF1156 15 | * PHY: Marvell M88E1111 16 | 17 | ## How to build 18 | 19 | Run make to build. Ensure that the Xilinx ISE toolchain components are 20 | in PATH. 21 | 22 | ## How to test 23 | 24 | Run make program to program the ML605 board with the Xilinx Impact software. 25 | Then run 26 | 27 | netcat -u 192.168.1.128 1234 28 | 29 | to open a UDP connection to port 1234. Any text entered into netcat will be 30 | echoed back after pressing enter. 31 | 32 | It is also possible to use hping to test the design by running 33 | 34 | hping 192.168.1.128 -2 -p 1234 -d 1024 35 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "phy_sgmii_txoutclk" TNM_NET = "txoutclk"; 4 | TIMESPEC "TS_txoutclk" = PERIOD "txoutclk" 8 ns HIGH 50 %; 5 | 6 | NET "eth_pcspma/transceiver_inst/RXRECCLK" TNM_NET = "rxrecclk"; 7 | TIMESPEC "ts_rxrecclk" = PERIOD "rxrecclk" 8 ns; 8 | 9 | # Identify clock domain crossing registers 10 | INST "eth_pcspma/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray*" TNM = "wr_graycode"; 11 | INST "eth_pcspma/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray*" TNM = "rd_graycode"; 12 | 13 | # Control Gray Code delay and skew across clock boundary 14 | TIMESPEC "ts_rx_skew_control1" = FROM "wr_graycode" TO "FFS" 14 ns DATAPATHONLY; 15 | TIMESPEC "ts_rx_skew_control2" = FROM "rd_graycode" TO "FFS" 14 ns DATAPATHONLY; 16 | 17 | # Constrain between Distributed Memory (output data) and the 1st set of flip-flops 18 | INST "eth_pcspma/transceiver_inst/rx_elastic_buffer_inst/*rd_data*" TNM = "fifo_read"; 19 | TIMESPEC "ts_ram_read_false_path" = FROM "RAMS" TO "fifo_read" 6 ns DATAPATHONLY; 20 | 21 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 22 | NET "phy_sgmii_txoutclk" TNM = "ffs_sgmii_clk"; 23 | TIMESPEC "TS_clk_125mhz_int_to_sgmii_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_sgmii_clk" 10 ns; 24 | TIMESPEC "TS_sgmii_clk_to_clk_125mhz_int" = FROM "ffs_sgmii_clk" TO "ffs_clk_125mhz_int" 10 ns; 25 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/coregen/Makefile: -------------------------------------------------------------------------------- 1 | # Tools 2 | COREGEN:=coregen 3 | XAW2VERILOG:=xaw2verilog 4 | 5 | # Source 6 | XCO:=gig_eth_pcs_pma_v11_5.xco 7 | XAW:= 8 | 9 | # Targets 10 | TARGETS += $(XCO:.xco=) 11 | TARGETS += $(XAW:.xaw=) 12 | 13 | # Rules 14 | .PHONY: all 15 | all: $(TARGETS) 16 | 17 | .PHONY: clean 18 | clean: 19 | -rm -rf $(TARGETS) 20 | 21 | %: %.xco 22 | $(eval $@_TMP := $(shell mktemp -d)) 23 | cp -a coregen.cgp $($@_TMP) 24 | cp -a $< $($@_TMP) 25 | cd $($@_TMP) && $(COREGEN) -p coregen.cgp -b $(notdir $<) 26 | mv $($@_TMP) $@ 27 | 28 | %: %.xaw 29 | $(eval $@_TMP := $(shell mktemp -d)) 30 | cp -a coregen.cgp $($@_TMP) 31 | cp -a $< $($@_TMP) 32 | cd $($@_TMP) && $(XAW2VERILOG) -st $(notdir $<) $(notdir $*) 33 | mv $($@_TMP) $@ 34 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/coregen/coregen.cgp: -------------------------------------------------------------------------------- 1 | # Date: Wed Jun 21 16:05:33 2017 2 | 3 | SET addpads = false 4 | SET asysymbol = true 5 | SET busformat = BusFormatAngleBracketNotRipped 6 | SET createndf = false 7 | SET designentry = Verilog 8 | SET device = xc6vlx130t 9 | SET devicefamily = virtex6 10 | SET flowvendor = Other 11 | SET formalverification = false 12 | SET foundationsym = false 13 | SET implementationfiletype = Ngc 14 | SET package = ff1156 15 | SET removerpms = false 16 | SET simulationfiles = Behavioral 17 | SET speedgrade = -1 18 | SET verilogsim = true 19 | SET vhdlsim = false 20 | SET workingdirectory = ./tmp/ 21 | 22 | # CRC: 2db0eed3 23 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/coregen/gig_eth_pcs_pma_v11_5.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Wed Jun 21 16:07:22 2017 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.5 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6vlx130t 26 | SET devicefamily = virtex6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = ff1156 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -1 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.5 40 | # END Select 41 | # BEGIN Parameters 42 | CSET auto_negotiation=true 43 | CSET component_name=gig_eth_pcs_pma_v11_5 44 | CSET enable_1588=false 45 | CSET management_interface=false 46 | CSET physical_interface=Transceiver 47 | CSET sgmii_mode=10_100_1000 48 | CSET sgmii_phy_mode=false 49 | CSET standard=SGMII 50 | CSET timing_sim=false 51 | CSET transceiver_tile=A 52 | # END Parameters 53 | # BEGIN Extra information 54 | MISC pkg_timestamp=2012-07-11T07:25:50Z 55 | # END Extra information 56 | GENERATE 57 | # CRC: 7ca270ae 58 | -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ML605/fpga_sgmii/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/NetFPGA_SUME/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/NetFPGA_SUME/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet NetFPGA SUME Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the NetFPGA SUME FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xc7vx690tffg1761-3 12 | * PHY: 10G BASE-R PHY IP core and internal GTH transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the NetFPGA SUME board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.MDIO_Management {false} \ 6 | CONFIG.base_kr {BASE-R} \ 7 | CONFIG.SupportLevel {1} \ 8 | CONFIG.DClkRate {125} \ 9 | ] [get_ips ten_gig_eth_pcs_pma_0] 10 | -------------------------------------------------------------------------------- /example/NetFPGA_SUME/fpga/ip/ten_gig_eth_pcs_pma_1.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -module_name ten_gig_eth_pcs_pma_1 3 | 4 | set_property -dict [list \ 5 | CONFIG.MDIO_Management {false} \ 6 | CONFIG.base_kr {BASE-R} \ 7 | CONFIG.SupportLevel {0} \ 8 | CONFIG.DClkRate {125} \ 9 | ] [get_ips ten_gig_eth_pcs_pma_1] 10 | -------------------------------------------------------------------------------- /example/NetFPGA_SUME/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/NexysVideo/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/NexysVideo/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Nexys Video Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Digilent Nexys Video FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: XC7A200TSBG484-1 12 | * PHY: Realtek RTL8211E 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the Nexys Video board with the Digilent command 22 | line tools. Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | -------------------------------------------------------------------------------- /example/NexysVideo/fpga/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | # IDELAY on RGMII from PHY chip 4 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 5 | 6 | -------------------------------------------------------------------------------- /example/NexysVideo/fpga/fpga/generate_bit_iodelay.tcl: -------------------------------------------------------------------------------- 1 | open_project fpga.xpr 2 | open_run impl_1 3 | set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}] 4 | set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst] 5 | write_bitstream -force fpga.bit 6 | exit 7 | -------------------------------------------------------------------------------- /example/NexysVideo/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/NexysVideo/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/RV901T/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet RV901T Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Linsn RV901T FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: XC6SLX16T-2FT256 12 | * PHY: Broadcom B50612 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx ISE toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the RV901T board with the Xilinx Impact software. 22 | Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | -------------------------------------------------------------------------------- /example/RV901T/fpga/clock.ucf: -------------------------------------------------------------------------------- 1 | # UCF file for clock module domain crossing constraints 2 | 3 | NET "clk_125mhz_int" TNM = "ffs_clk_125mhz_int"; 4 | NET "core_inst/eth_mac_inst/rx_clk" TNM = "ffs_gmii_rx_clk"; 5 | TIMESPEC "TS_clk_125mhz_int_to_gmii_rx_clk" = FROM "ffs_clk_125mhz_int" TO "ffs_gmii_rx_clk" 10 ns; 6 | TIMESPEC "TS_gmii_rx_clk_to_clk_125mhz_int" = FROM "ffs_gmii_rx_clk" TO "ffs_clk_125mhz_int" 10 ns; 7 | -------------------------------------------------------------------------------- /example/RV901T/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/S10DX_DK/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #program commands 26 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Stratix 10 DX Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Intel Stratix 10 DX FPGA development board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: 1SD280PT2F55E1VG 12 | * PHY: Transceiver in 10G BASE-R native mode 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Intel Quartus Prime Pro toolchain 17 | components are in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the board with the Intel software. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga_10g/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Stratix 10 DX" 5 | FPGA_DEVICE = 1SD280PT2F55E1VG 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/debounce_switch.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/eth_mac_quad_wrapper.v 13 | SYN_FILES += rtl/xcvr_ctrl.v 14 | SYN_FILES += rtl/axis2avst.v 15 | SYN_FILES += rtl/avst2axis.v 16 | SYN_FILES += lib/eth/rtl/lfsr.v 17 | SYN_FILES += lib/eth/rtl/eth_axis_rx.v 18 | SYN_FILES += lib/eth/rtl/eth_axis_tx.v 19 | SYN_FILES += lib/eth/rtl/udp_complete_64.v 20 | SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v 21 | SYN_FILES += lib/eth/rtl/udp_64.v 22 | SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v 23 | SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v 24 | SYN_FILES += lib/eth/rtl/ip_complete_64.v 25 | SYN_FILES += lib/eth/rtl/ip_64.v 26 | SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v 27 | SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v 28 | SYN_FILES += lib/eth/rtl/ip_arb_mux.v 29 | SYN_FILES += lib/eth/rtl/ip_mux.v 30 | SYN_FILES += lib/eth/rtl/arp.v 31 | SYN_FILES += lib/eth/rtl/arp_cache.v 32 | SYN_FILES += lib/eth/rtl/arp_eth_rx.v 33 | SYN_FILES += lib/eth/rtl/arp_eth_tx.v 34 | SYN_FILES += lib/eth/rtl/eth_arb_mux.v 35 | SYN_FILES += lib/eth/rtl/eth_mux.v 36 | SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v 37 | SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v 38 | SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v 39 | SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v 40 | SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v 41 | 42 | # IP files 43 | IP_TCL_FILES += ip/reset_release.tcl 44 | IP_TCL_FILES += ip/mac.tcl 45 | 46 | # QSF files 47 | QSF_FILES = fpga.qsf 48 | 49 | # SDC files 50 | SDC_FILES = fpga.sdc 51 | 52 | include ../common/quartus_pro.mk 53 | 54 | program: fpga 55 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2" 56 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga_10g/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 20.4 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {1SD280PT2F55E1VG} 8 | set_project_property DEVICE_FAMILY {Stratix 10} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Reset Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # add the exports 22 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 23 | 24 | # set values for exposed HDL parameters 25 | 26 | # set the the module properties 27 | set_module_property BONUS_DATA { 28 | 29 | 30 | 31 | 32 | 33 | } 34 | set_module_property FILE {reset_release.ip} 35 | set_module_property GENERATION_ID {0x00000000} 36 | set_module_property NAME {reset_release} 37 | 38 | # save the system 39 | sync_sysinfo_parameters 40 | save_system reset_release 41 | } 42 | 43 | proc do_set_exported_interface_sysinfo_parameters {} { 44 | } 45 | 46 | # create all the systems, from bottom up 47 | do_create_reset_release 48 | 49 | # set system info parameters on exported interface, from bottom up 50 | do_set_exported_interface_sysinfo_parameters 51 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/S10DX_DK/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet Stratix 10 MX Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Intel Stratix 10 MX FPGA development board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: 1SM21BHU2F53E1VG (8 GB HBM2) or 1SM21CHU1F53E1VG (16 GB HBM2) 12 | * PHY: Transceiver in 10G BASE-R native mode 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Intel Quartus Prime Pro toolchain 17 | components are in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the board with the Intel software. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga_10g/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 20.4 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {1SM21CHU1F53E1VG} 8 | set_project_property DEVICE_FAMILY {Stratix 10} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # add the exports 22 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 23 | 24 | # set values for exposed HDL parameters 25 | 26 | # set the the module properties 27 | set_module_property BONUS_DATA { 28 | 29 | 30 | 31 | 32 | 33 | } 34 | set_module_property FILE {reset_release.ip} 35 | set_module_property GENERATION_ID {0x00000000} 36 | set_module_property NAME {reset_release} 37 | 38 | # save the system 39 | sync_sysinfo_parameters 40 | save_system reset_release 41 | } 42 | 43 | proc do_set_exported_interface_sysinfo_parameters {} { 44 | } 45 | 46 | # create all the systems, from bottom up 47 | do_create_reset_release 48 | 49 | # set system info parameters on exported interface, from bottom up 50 | do_set_exported_interface_sysinfo_parameters 51 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/S10MX_DK/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU108/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU108/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU108 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. The design also enables the gigabit Ethernet interface for 10 | testing with a QSFP loopback adapter. 11 | 12 | * FPGA: xcvu095-ffva2104-2-e 13 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 14 | 15 | ## How to build 16 | 17 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 18 | in PATH. 19 | 20 | ## How to test 21 | 22 | Run make program to program the VCU108 board with Vivado. Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | 33 | Note that the gigabit PHY is also enabled for debugging. The gigabit port can 34 | be inserted into the 10G data path between the 10G MAC and 10G PHY so that the 35 | 10G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to 36 | insert the gigabit port into the 10G data path, or off to bypass the gigabit 37 | port. Turn on SW12.2 to place the port in the TX path or off to place the 38 | port in the RX path. 39 | 40 | 41 | -------------------------------------------------------------------------------- /example/VCU108/fpga_10g/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | set_property LOC BITSLICE_RX_TX_X1Y35 [get_cells -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/idelay_cal}] 4 | #set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_inst/RST} -include_replicated_objects ] 5 | -------------------------------------------------------------------------------- /example/VCU108/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | ] [get_ips gig_ethernet_pcs_pma_0] 11 | -------------------------------------------------------------------------------- /example/VCU108/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU108/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU108/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU108/fpga_1g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU108 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcvu095-ffva2104-2-e 12 | * PHY: Marvell M88E1111 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the VCU108 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/VCU108/fpga_1g/eth.xdc: -------------------------------------------------------------------------------- 1 | # Ethernet constraints 2 | 3 | set_property LOC BITSLICE_RX_TX_X1Y35 [get_cells -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/idelay_cal}] 4 | #set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_inst/RST} -include_replicated_objects ] 5 | -------------------------------------------------------------------------------- /example/VCU108/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | ] [get_ips gig_ethernet_pcs_pma_0] 11 | -------------------------------------------------------------------------------- /example/VCU108/fpga_1g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU108/fpga_1g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU118/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU118/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. The design also enables the gigabit Ethernet interface for 10 | testing with a QSFP loopback adapter. 11 | 12 | * FPGA: xcvu9p-flga2104-2L-e 13 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 14 | 15 | ## How to build 16 | 17 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 18 | in PATH. 19 | 20 | ## How to test 21 | 22 | Run make program to program the VCU118 board with Vivado. Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | 33 | Note that the gigabit PHY is also enabled for debugging. The gigabit port can 34 | be inserted into the 10G data path between the 10G MAC and 10G PHY so that the 35 | 10G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to 36 | insert the gigabit port into the 10G data path, or off to bypass the gigabit 37 | port. Turn on SW12.2 to place the port in the TX path or off to place the 38 | port in the RX path. 39 | 40 | 41 | -------------------------------------------------------------------------------- /example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 11 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 12 | CONFIG.Tx_In_Upper_Nibble {0} \ 13 | ] [get_ips gig_ethernet_pcs_pma_0] 14 | -------------------------------------------------------------------------------- /example/VCU118/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU118/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU118/fpga_1g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU118/fpga_1g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcvu9p-flga2104-2L-e 12 | * PHY: TI DP83867ISRGZ 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the VCU108 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/VCU118/fpga_1g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 11 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 12 | CONFIG.Tx_In_Upper_Nibble {0} \ 13 | ] [get_ips gig_ethernet_pcs_pma_0] 14 | -------------------------------------------------------------------------------- /example/VCU118/fpga_1g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU118/fpga_1g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU118/fpga_25g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU118/fpga_25g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. The design also enables the gigabit Ethernet interface for 10 | testing with a QSFP loopback adapter. 11 | 12 | * FPGA: xcvu9p-flga2104-2L-e 13 | * PHY: 25G BASE-R PHY IP core and internal GTY transceiver 14 | 15 | ## How to build 16 | 17 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 18 | in PATH. 19 | 20 | ## How to test 21 | 22 | Run make program to program the VCU118 board with Vivado. Then run 23 | 24 | netcat -u 192.168.1.128 1234 25 | 26 | to open a UDP connection to port 1234. Any text entered into netcat will be 27 | echoed back after pressing enter. 28 | 29 | It is also possible to use hping to test the design by running 30 | 31 | hping 192.168.1.128 -2 -p 1234 -d 1024 32 | 33 | Note that the gigabit PHY is also enabled for debugging. The gigabit port can 34 | be inserted into the 25G data path between the 25G MAC and 25G PHY so that the 35 | 25G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to 36 | insert the gigabit port into the 25G data path, or off to bypass the gigabit 37 | port. Turn on SW12.2 to place the port in the TX path or off to place the 38 | port in the RX path. 39 | 40 | 41 | -------------------------------------------------------------------------------- /example/VCU118/fpga_25g/ip/gig_ethernet_pcs_pma_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.Standard {SGMII} \ 6 | CONFIG.Physical_Interface {LVDS} \ 7 | CONFIG.Management_Interface {false} \ 8 | CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ 9 | CONFIG.LvdsRefClk {625} \ 10 | CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ 11 | CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ 12 | CONFIG.Tx_In_Upper_Nibble {0} \ 13 | ] [get_ips gig_ethernet_pcs_pma_0] 14 | -------------------------------------------------------------------------------- /example/VCU118/fpga_25g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU118/fpga_25g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU1525 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU1525 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcvu9p-fsgd2104-2L-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the VCU1525 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU1525/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ZCU102/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ZCU102/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ZCU102 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU102 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xczu9eg-ffvb1156-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the ZCU102 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/ZCU102/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ZCU102/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ZCU106/fpga/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ZCU106/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ZCU106 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU106 FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xczu7ev-ffvc1156-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the ZCU106 board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/ZCU106/fpga/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ZCU106/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_10g/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_10g/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet fb2CG@KU15P Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Silicom fb2CG@KU15P FPGA board. 6 | 7 | The design by default listens to UDP port 1234 at IP address 192.168.1.128 and 8 | will echo back any packets received. The design will also respond correctly 9 | to ARP requests. 10 | 11 | * FPGA: xcku15p-ffve1760-2-e 12 | * PHY: 10G BASE-R PHY IP core and internal GTY transceiver 13 | 14 | ## How to build 15 | 16 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 17 | in PATH. 18 | 19 | ## How to test 20 | 21 | Run make program to program the fb2CG@KU15P board with Vivado. Then run 22 | 23 | netcat -u 192.168.1.128 1234 24 | 25 | to open a UDP connection to port 1234. Any text entered into netcat will be 26 | echoed back after pressing enter. 27 | 28 | It is also possible to use hping to test the design by running 29 | 30 | hping 192.168.1.128 -2 -p 1234 -d 1024 31 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_10g/led.tcl: -------------------------------------------------------------------------------- 1 | # Timing constraints for led_sreg_driver 2 | 3 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { 4 | puts "Inserting timing constraints for led_sreg_driver instance $inst" 5 | 6 | set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] 7 | 8 | if {[llength $select_ffs]} { 9 | set_property ASYNC_REG TRUE $select_ffs 10 | set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_10g/lib/eth: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/fb2CG/fpga_10g/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /lib/axis/.github/workflows/regression-tests.yml: -------------------------------------------------------------------------------- 1 | name: Regression Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | build: 7 | name: Python ${{ matrix.python-version }} (${{ matrix.group }}/10) 8 | runs-on: ubuntu-22.04 9 | 10 | strategy: 11 | matrix: 12 | python-version: ["3.10"] 13 | group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10] 14 | 15 | steps: 16 | - uses: actions/checkout@v3 17 | 18 | - name: Set up Python ${{ matrix.python-version }} 19 | uses: actions/setup-python@v4 20 | with: 21 | python-version: ${{ matrix.python-version }} 22 | 23 | - name: Install Icarus Verilog 24 | run: | 25 | sudo apt install -y --no-install-recommends iverilog 26 | 27 | - name: Install Python dependencies 28 | run: | 29 | python -m pip install --upgrade pip 30 | pip install tox tox-gh-actions 31 | 32 | - name: Test with tox 33 | run: tox -- -n auto --verbose --splits 10 --group ${{ matrix.group }} 34 | -------------------------------------------------------------------------------- /lib/axis/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.lxt 3 | *.pyc 4 | *.vvp 5 | *.kate-swp 6 | 7 | -------------------------------------------------------------------------------- /lib/axis/AUTHORS: -------------------------------------------------------------------------------- 1 | Alex Forencich 2 | -------------------------------------------------------------------------------- /lib/axis/COPYING: -------------------------------------------------------------------------------- 1 | Copyright (c) 2014-2018 Alex Forencich 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in 11 | all copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | THE SOFTWARE. 20 | -------------------------------------------------------------------------------- /lib/axis/README: -------------------------------------------------------------------------------- 1 | README.md -------------------------------------------------------------------------------- /lib/axis/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2020 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset # 36 | ( 37 | // depth of synchronizer 38 | parameter N = 2 39 | ) 40 | ( 41 | input wire clk, 42 | input wire rst, 43 | output wire out 44 | ); 45 | 46 | (* srl_style = "register" *) 47 | reg [N-1:0] sync_reg = {N{1'b1}}; 48 | 49 | assign out = sync_reg[N-1]; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | sync_reg <= {N{1'b1}}; 54 | end else begin 55 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 56 | end 57 | end 58 | 59 | endmodule 60 | 61 | `resetall 62 | -------------------------------------------------------------------------------- /lib/axis/syn/quartus/sync_reset.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # reset synchronizer timing constraints 22 | 23 | proc constrain_sync_reset_inst { inst } { 24 | puts "Inserting timing constraints for sync_reset instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|sync_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /lib/axis/syn/quartus_pro/sync_reset.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # reset synchronizer timing constraints 22 | 23 | proc constrain_sync_reset_inst { inst } { 24 | puts "Inserting timing constraints for sync_reset instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|sync_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /lib/axis/syn/vivado/sync_reset.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # reset synchronizer timing constraints 22 | 23 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == sync_reset || REF_NAME == sync_reset)}] { 24 | puts "Inserting timing constraints for sync_reset instance $inst" 25 | 26 | # reset synchronization 27 | set reset_ffs [get_cells -quiet -hier -regexp ".*/sync_reg_reg\\\[\\d+\\\]" -filter "PARENT == $inst"] 28 | 29 | set_property ASYNC_REG TRUE $reset_ffs 30 | set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}] 31 | } 32 | -------------------------------------------------------------------------------- /lib/axis/tb/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPTARGETS := all clean 22 | 23 | SUBDIRS := $(wildcard */.) 24 | 25 | $(TOPTARGETS): $(SUBDIRS) 26 | $(SUBDIRS): 27 | $(MAKE) -C $@ $(MAKECMDGOALS) 28 | 29 | .PHONY: $(TOPTARGETS) $(SUBDIRS) 30 | 31 | -------------------------------------------------------------------------------- /lib/axis/tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.20 21 | jinja2 == 3.1.2 22 | 23 | commands = 24 | pytest {posargs:-n auto --verbose} 25 | 26 | # pytest configuration 27 | [pytest] 28 | testpaths = 29 | tb 30 | addopts = 31 | --ignore-glob=tb/test_*.py 32 | --import-mode importlib 33 | -------------------------------------------------------------------------------- /scripts/dev-netns-shell.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | ns="" 4 | 5 | while getopts h-: option; do 6 | case "${option}" in 7 | -) 8 | case "${OPTARG}" in 9 | ns) 10 | val="${!OPTIND}"; OPTIND=$(( $OPTIND + 1 )) 11 | ns=$val 12 | ;; 13 | ns=*) 14 | val=${OPTARG#*=} 15 | ns=$val 16 | ;; 17 | *) 18 | if [ "$OPTERR" = 1 ] && [ "${optspec:0:1}" != ":" ]; then 19 | echo "Unknown option --${OPTARG}" >&2 20 | fi 21 | ;; 22 | esac;; 23 | h) 24 | echo $(basename $0): usage: $(basename $0) [-h] [--ns=name] [dev] [dev] 25 | exit 0 26 | ;; 27 | esac 28 | done 29 | shift $((OPTIND -1)) 30 | 31 | dev=$1 32 | 33 | if [ -z "$ns" ]; then 34 | if [ -z "$dev" ]; then 35 | echo "Error: must specify either device or network namespace name" 36 | exit 1 37 | fi 38 | 39 | ns=$dev 40 | fi 41 | 42 | if [ -f "/var/run/netns/$ns" ]; then 43 | echo "Network namespace '$ns' already exists" 44 | else 45 | echo "Creating network namespace '$ns'" 46 | ip netns add $ns 47 | for d in "$@" 48 | do 49 | echo "Adding interface '$d' to network namespace '$ns'" 50 | ip link set dev $d netns $ns 51 | ip netns exec $ns ip link set dev $d up 52 | done 53 | fi 54 | 55 | if [ -f "/var/run/netns/$ns" ]; then 56 | echo "Starting shell in network namespace '$ns'" 57 | echo "Note: \$dev='$dev'" 58 | export dev 59 | ip netns exec $ns bash 60 | else 61 | echo "Error: network namespace not found" 62 | fi 63 | 64 | if [ -f "/var/run/netns/$ns" -a -z "$(ip netns pids $ns)" ]; then 65 | echo "Deleting network namespace '$ns'" 66 | ip netns del $ns 67 | fi 68 | 69 | -------------------------------------------------------------------------------- /scripts/udp_test.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python 2 | """ 3 | UDP echo test 4 | """ 5 | 6 | import argparse 7 | import socket 8 | 9 | def main(): 10 | parser = argparse.ArgumentParser(description=__doc__.strip()) 11 | parser.add_argument('host', help="Host") 12 | parser.add_argument('port', help="UDP port", nargs='?', type=int, default=1234) 13 | parser.add_argument('-n', help="Number of packets", type=int, default=1000) 14 | 15 | args = parser.parse_args() 16 | 17 | host = args.host 18 | port = args.port 19 | n = args.n 20 | 21 | sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) 22 | sock.settimeout(0) 23 | 24 | sent = 0 25 | recv = 0 26 | 27 | data = b'testing'*100 28 | 29 | print(f"Sending {n} UDP packets to {host} on {port}...") 30 | 31 | while sent < n: 32 | try: 33 | sock.sendto(data, (host, port)) 34 | sent += 1 35 | except BlockingIOError: 36 | pass 37 | 38 | try: 39 | ret = sock.recvfrom(1024) 40 | recv += 1 41 | except BlockingIOError: 42 | pass 43 | 44 | sock.settimeout(1) 45 | 46 | while True: 47 | 48 | try: 49 | ret = sock.recvfrom(1024) 50 | recv += 1 51 | except socket.timeout: 52 | break 53 | 54 | print(f"Sent {sent} packets") 55 | print(f"Received {recv} packets ({recv/sent*100}%)") 56 | print(f"Missed {sent-recv} packets ({(sent-recv)/sent*100}%)") 57 | 58 | 59 | if __name__ == "__main__": 60 | main() 61 | -------------------------------------------------------------------------------- /syn/quartus/eth_mac_1g_gmii.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # GMII Gigabit Ethernet MAC timing constraints 22 | 23 | proc constrain_eth_mac_1g_gmii_inst { inst } { 24 | puts "Inserting timing constraints for eth_mac_1g_gmii instance $inst" 25 | 26 | # MII select sync 27 | set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] 8.000 28 | set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] 8.000 29 | 30 | # RX prescale sync 31 | set_max_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] 8.000 32 | 33 | constrain_gmii_phy_if_inst "$inst|gmii_phy_if_inst" 34 | } 35 | -------------------------------------------------------------------------------- /syn/quartus/eth_mac_1g_rgmii.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # RGMII Gigabit Ethernet MAC timing constraints 22 | 23 | proc constrain_eth_mac_1g_rgmii_inst { inst } { 24 | puts "Inserting timing constraints for eth_mac_1g_rgmii instance $inst" 25 | 26 | # MII select sync 27 | set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] 8.000 28 | set_max_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] 8.000 29 | 30 | # RX prescale sync 31 | set_max_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] 8.000 32 | 33 | constrain_rgmii_phy_if_inst "$inst|rgmii_phy_if_inst" 34 | } 35 | -------------------------------------------------------------------------------- /syn/quartus/gmii_phy_if.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # GMII PHY IF timing constraints 22 | 23 | proc constrain_gmii_phy_if_inst { inst } { 24 | puts "Inserting timing constraints for gmii_phy_if instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /syn/quartus/mii_phy_if.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # MII PHY IF timing constraints 22 | 23 | proc constrain_mii_phy_if_inst { inst } { 24 | puts "Inserting timing constraints for mii_phy_if instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /syn/quartus/rgmii_phy_if.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # RGMII PHY IF timing constraints 22 | 23 | proc constrain_rgmii_phy_if_inst { inst } { 24 | puts "Inserting timing constraints for rgmii_phy_if instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] 28 | 29 | # clock output 30 | # set_max_delay -from [get_registers "$inst|rgmii_tx_clk_1"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000 31 | # set_max_delay -from [get_registers "$inst|rgmii_tx_clk_2"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000 32 | } 33 | -------------------------------------------------------------------------------- /syn/quartus_pro/eth_mac_1g_gmii.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # GMII Gigabit Ethernet MAC timing constraints 22 | 23 | proc constrain_eth_mac_1g_gmii_inst { inst } { 24 | puts "Inserting timing constraints for eth_mac_1g_gmii instance $inst" 25 | 26 | # MII select sync 27 | set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 28 | set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 29 | 30 | # RX prescale sync 31 | set_data_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 32 | 33 | constrain_gmii_phy_if_inst "$inst|gmii_phy_if_inst" 34 | } 35 | -------------------------------------------------------------------------------- /syn/quartus_pro/eth_mac_1g_rgmii.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # RGMII Gigabit Ethernet MAC timing constraints 22 | 23 | proc constrain_eth_mac_1g_rgmii_inst { inst } { 24 | puts "Inserting timing constraints for eth_mac_1g_rgmii instance $inst" 25 | 26 | # MII select sync 27 | set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|tx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 28 | set_data_delay -from [get_registers "$inst|mii_select_reg"] -to [get_registers "$inst|rx_mii_select_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 29 | 30 | # RX prescale sync 31 | set_data_delay -from [get_registers "$inst|rx_prescale[2]"] -to [get_registers "$inst|rx_prescale_sync[0]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 32 | 33 | constrain_rgmii_phy_if_inst "$inst|rgmii_phy_if_inst" 34 | } 35 | -------------------------------------------------------------------------------- /syn/quartus_pro/eth_mac_fifo.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # Ethernet MAC with FIFO timing constraints 22 | 23 | proc constrain_eth_mac_fifo_inst { inst } { 24 | puts "Inserting timing constraints for ethernet MAC with FIFO instance $inst" 25 | 26 | # RX status sync 27 | set_data_delay -from [get_registers "$inst|rx_sync_reg_1_reg[*]"] -to [get_registers "$inst|rx_sync_reg_2_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 28 | 29 | # TX status sync 30 | set_data_delay -from [get_registers "$inst|tx_sync_reg_1_reg[*]"] -to [get_registers "$inst|tx_sync_reg_2_reg[*]"] -override -get_value_from_clock_period dst_clock_period -value_multiplier 0.8 31 | } 32 | -------------------------------------------------------------------------------- /syn/quartus_pro/gmii_phy_if.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # GMII PHY IF timing constraints 22 | 23 | proc constrain_gmii_phy_if_inst { inst } { 24 | puts "Inserting timing constraints for gmii_phy_if instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /syn/quartus_pro/mii_phy_if.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # MII PHY IF timing constraints 22 | 23 | proc constrain_mii_phy_if_inst { inst } { 24 | puts "Inserting timing constraints for mii_phy_if instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] 28 | } 29 | -------------------------------------------------------------------------------- /syn/quartus_pro/rgmii_phy_if.sdc: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2021 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # RGMII PHY IF timing constraints 22 | 23 | proc constrain_rgmii_phy_if_inst { inst } { 24 | puts "Inserting timing constraints for rgmii_phy_if instance $inst" 25 | 26 | # reset synchronization 27 | set_false_path -from * -to [get_registers "$inst|tx_rst_reg[*] $inst|rx_rst_reg[*]"] 28 | 29 | # clock output 30 | # set_max_delay -from [get_registers "$inst|rgmii_tx_clk_1"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000 31 | # set_max_delay -from [get_registers "$inst|rgmii_tx_clk_2"] -to [get_cells "$inst|clk_oddr_inst|altddio_out_inst|auto_generated|ddio_outa[0]"] 2.000 32 | } 33 | -------------------------------------------------------------------------------- /syn/vivado/gmii_phy_if.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2019 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # GMII PHY IF timing constraints 22 | 23 | foreach if_inst [get_cells -hier -filter {(ORIG_REF_NAME == gmii_phy_if || REF_NAME == gmii_phy_if)}] { 24 | puts "Inserting timing constraints for gmii_phy_if instance $if_inst" 25 | 26 | # reset synchronization 27 | set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $if_inst"] 28 | 29 | set_property ASYNC_REG TRUE $reset_ffs 30 | set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}] 31 | } 32 | -------------------------------------------------------------------------------- /syn/vivado/mii_phy_if.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2019 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | # MII PHY IF timing constraints 22 | 23 | foreach if_inst [get_cells -hier -filter {(ORIG_REF_NAME == mii_phy_if || REF_NAME == mii_phy_if)}] { 24 | puts "Inserting timing constraints for mii_phy_if instance $if_inst" 25 | 26 | # reset synchronization 27 | set reset_ffs [get_cells -hier -regexp ".*/(rx|tx)_rst_reg_reg\\\[\\d\\\]" -filter "PARENT == $if_inst"] 28 | 29 | set_property ASYNC_REG TRUE $reset_ffs 30 | set_false_path -to [get_pins -of_objects $reset_ffs -filter {IS_PRESET || IS_RESET}] 31 | } 32 | -------------------------------------------------------------------------------- /tb/axis_baser_rx_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tb/axis_baser_tx_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tb/axis_ep.py: -------------------------------------------------------------------------------- 1 | ../lib/axis/tb/axis_ep.py -------------------------------------------------------------------------------- /tb/eth_mac_phy_10g/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tb/eth_mac_phy_10g_fifo/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tb/eth_phy_10g/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tb/xgmii_baser_dec_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tb/xgmii_baser_enc_64/baser.py: -------------------------------------------------------------------------------- 1 | ../baser.py -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.20 21 | cocotbext-eth == 0.1.20 22 | scapy == 2.5.0 23 | jinja2 == 3.1.2 24 | 25 | commands = 26 | pytest {posargs:-n auto --verbose} 27 | 28 | # pytest configuration 29 | [pytest] 30 | testpaths = 31 | tb 32 | example 33 | norecursedirs = 34 | lib 35 | addopts = 36 | --ignore-glob=tb/test_*.py 37 | --import-mode importlib 38 | --------------------------------------------------------------------------------