├── README ├── example ├── AU50 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── driver │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4c_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4c_uscale_plus_0.tcl │ │ └── rtl │ │ ├── sync_reset.v │ │ └── sync_signal.v ├── 520N_MX │ └── fpga │ │ ├── lib │ │ └── pcie │ │ ├── rtl │ │ ├── common │ │ ├── sync_reset.v │ │ └── sync_signal.v │ │ ├── README.md │ │ ├── ip │ │ └── reset_release.tcl │ │ └── fpga │ │ └── Makefile ├── AU200 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── driver │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ ├── sync_reset.v │ │ └── sync_signal.v ├── AU250 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── driver │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ ├── sync_reset.v │ │ └── sync_signal.v ├── AU280 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── driver │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4c_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4c_uscale_plus_0.tcl │ │ └── rtl │ │ ├── sync_reset.v │ │ └── sync_signal.v ├── S10DX_DK │ └── fpga │ │ ├── lib │ │ └── pcie │ │ ├── rtl │ │ ├── common │ │ ├── sync_reset.v │ │ └── sync_signal.v │ │ ├── README.md │ │ ├── ip │ │ └── reset_release.tcl │ │ └── fpga │ │ └── Makefile ├── S10MX_DK │ └── fpga │ │ ├── lib │ │ └── pcie │ │ ├── rtl │ │ ├── common │ │ ├── sync_reset.v │ │ └── sync_signal.v │ │ ├── README.md │ │ ├── ip │ │ └── reset_release.tcl │ │ ├── fpga_1sm21b │ │ └── Makefile │ │ └── fpga_1sm21c │ │ └── Makefile ├── VCU108 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── driver │ │ ├── README.md │ │ └── ip │ │ │ └── pcie3_ultrascale_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie3_ultrascale_0.tcl │ │ └── rtl │ │ ├── sync_reset.v │ │ └── sync_signal.v ├── VCU118 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── driver │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ ├── sync_reset.v │ │ └── sync_signal.v ├── VCU1525 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── driver │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ └── sync_reset.v ├── ZCU106 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── rtl │ │ │ ├── common │ │ │ └── sync_reset.v │ │ ├── driver │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ ├── fpga │ │ └── Makefile │ │ └── rtl │ │ └── sync_reset.v ├── fb2CG │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── driver │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── led.tcl │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── led.tcl │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ └── sync_reset.v ├── ADM_PCIE_9V3 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── rtl │ │ │ ├── common │ │ │ └── sync_reset.v │ │ ├── driver │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ └── sync_reset.v ├── DE10_Agilex │ └── fpga │ │ ├── lib │ │ └── pcie │ │ ├── rtl │ │ ├── common │ │ └── sync_reset.v │ │ ├── README.md │ │ ├── ip │ │ └── reset_release.tcl │ │ ├── fpga_24B │ │ └── Makefile │ │ └── fpga_24AR0 │ │ └── Makefile ├── ExaNIC_X10 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── driver │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── README.md │ │ └── ip │ │ │ └── pcie3_ultrascale_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie3_ultrascale_0.tcl │ │ └── rtl │ │ └── sync_reset.v ├── ExaNIC_X25 │ ├── fpga │ │ ├── lib │ │ │ └── pcie │ │ ├── driver │ │ ├── rtl │ │ │ ├── common │ │ │ ├── sync_reset.v │ │ │ └── sync_signal.v │ │ ├── README.md │ │ └── ip │ │ │ └── pcie4_uscale_plus_0.tcl │ └── fpga_axi │ │ ├── lib │ │ └── pcie │ │ ├── driver │ │ ├── Makefile │ │ ├── README.md │ │ ├── ip │ │ └── pcie4_uscale_plus_0.tcl │ │ └── rtl │ │ └── sync_reset.v └── common │ ├── tb │ └── example_core_pcie │ │ └── pcie_if.py │ └── driver │ └── example │ ├── Makefile │ └── example_driver.h ├── tb ├── pcie_msix │ └── pcie_if.py ├── pcie_s10_if │ └── pcie_if.py ├── pcie_us_if │ └── pcie_if.py ├── dma_if_pcie_rd │ ├── pcie_if.py │ └── dma_psdp_ram.py ├── dma_if_pcie_wr │ ├── pcie_if.py │ └── dma_psdp_ram.py ├── pcie_axi_master │ └── pcie_if.py ├── pcie_axil_master │ └── pcie_if.py ├── pcie_ptile_if │ └── pcie_if.py ├── pcie_ptile_if_rx │ └── pcie_if.py ├── pcie_ptile_if_tx │ └── pcie_if.py ├── pcie_s10_if_rx │ └── pcie_if.py ├── pcie_s10_if_tx │ └── pcie_if.py ├── pcie_tlp_demux │ └── pcie_if.py ├── pcie_tlp_fifo │ └── pcie_if.py ├── pcie_tlp_mux │ └── pcie_if.py ├── pcie_us_if_cc │ └── pcie_if.py ├── pcie_us_if_cq │ └── pcie_if.py ├── pcie_us_if_rc │ └── pcie_if.py ├── pcie_us_if_rq │ └── pcie_if.py ├── dma_if_axi │ └── dma_psdp_ram.py ├── dma_psdpram │ └── dma_psdp_ram.py ├── pcie_axi_master_rd │ └── pcie_if.py ├── pcie_axi_master_wr │ └── pcie_if.py ├── pcie_tlp_demux_bar │ └── pcie_if.py ├── pcie_tlp_fifo_mux │ └── pcie_if.py ├── dma_if_axi_rd │ └── dma_psdp_ram.py ├── dma_if_axi_wr │ └── dma_psdp_ram.py ├── dma_if_pcie_us │ └── dma_psdp_ram.py ├── pcie_axil_master_minimal │ └── pcie_if.py ├── dma_client_axis_sink │ └── dma_psdp_ram.py ├── dma_if_pcie_us_rd │ └── dma_psdp_ram.py ├── dma_if_pcie_us_wr │ └── dma_psdp_ram.py ├── dma_psdpram_async │ └── dma_psdp_ram.py ├── dma_client_axis_source │ └── dma_psdp_ram.py └── Makefile ├── AUTHORS ├── .gitignore ├── scripts ├── pcie_rescan.sh ├── pcie_flr.sh ├── pcie_reset.sh ├── pcie_ext_tag.sh ├── pcie_disable_fatal_err.sh ├── pcie_hot_reset.sh └── pcie_set_speed.sh ├── tox.ini ├── .github └── workflows │ └── regression-tests.yml └── COPYING /README: -------------------------------------------------------------------------------- 1 | README.md -------------------------------------------------------------------------------- /example/AU50/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /tb/pcie_msix/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_s10_if/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_us_if/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /example/520N_MX/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU200/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU200/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU250/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU250/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU280/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU280/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU50/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU108/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU118/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU1525/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ZCU106/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/fb2CG/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /tb/dma_if_pcie_rd/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/dma_if_pcie_wr/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_axi_master/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_axil_master/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_ptile_if/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_ptile_if_rx/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_ptile_if_tx/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_s10_if_rx/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_s10_if_tx/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_tlp_demux/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_tlp_fifo/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_tlp_mux/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_us_if_cc/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_us_if_cq/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_us_if_rc/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_us_if_rq/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU50/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU108/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU118/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/VCU1525/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /tb/dma_if_axi/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_psdpram/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/pcie_axi_master_rd/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_axi_master_wr/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_tlp_demux_bar/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /tb/pcie_tlp_fifo_mux/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /AUTHORS: -------------------------------------------------------------------------------- 1 | Alex Forencich 2 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_axi/lib/pcie: -------------------------------------------------------------------------------- 1 | ../../../../ -------------------------------------------------------------------------------- /example/AU200/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/AU200/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/AU250/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/AU250/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/AU280/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/AU280/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/AU50/fpga/driver: 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-------------------------------------------------------------------------------- /example/fb2CG/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/fb2CG/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /tb/dma_if_axi_rd/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_if_axi_wr/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_if_pcie_rd/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_if_pcie_us/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_if_pcie_wr/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/pcie_axil_master_minimal/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../pcie_if.py -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/AU200/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/AU250/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/AU280/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/AU50/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../../../common/rtl/ -------------------------------------------------------------------------------- /example/VCU108/fpga/driver: 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../../common/driver/example/ -------------------------------------------------------------------------------- /example/ZCU106/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /tb/dma_client_axis_sink/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_if_pcie_us_rd/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_if_pcie_us_wr/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /tb/dma_psdpram_async/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /example/520N_MX/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../lib/pcie/example/common/rtl/ -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../lib/pcie/example/common/rtl/ -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../lib/pcie/example/common/rtl/ -------------------------------------------------------------------------------- /example/VCU1525/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /tb/dma_client_axis_source/dma_psdp_ram.py: -------------------------------------------------------------------------------- 1 | ../dma_psdp_ram.py -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.lxt 3 | *.pyc 4 | *.vvp 5 | *.kate-swp 6 | 7 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_axi/driver: -------------------------------------------------------------------------------- 1 | ../../common/driver/example/ -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/rtl/common: -------------------------------------------------------------------------------- 1 | ../lib/pcie/example/common/rtl/ -------------------------------------------------------------------------------- /example/common/tb/example_core_pcie/pcie_if.py: -------------------------------------------------------------------------------- 1 | ../../../../tb/pcie_if.py -------------------------------------------------------------------------------- /scripts/pcie_rescan.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | echo 1 > /sys/bus/pci/rescan 4 | 5 | 6 | -------------------------------------------------------------------------------- /example/common/driver/example/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # object files to build 3 | obj-m += example.o 4 | example-objs += example_driver.o 5 | 6 | all: 7 | make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules 8 | 9 | clean: 10 | make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean 11 | 12 | -------------------------------------------------------------------------------- /scripts/pcie_flr.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | 5 | if [ -z "$dev" ]; then 6 | echo "Error: no device specified" 7 | exit 1 8 | fi 9 | 10 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 11 | dev="0000:$dev" 12 | fi 13 | 14 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 15 | echo "Error: device $dev not found" 16 | exit 1 17 | fi 18 | 19 | echo "Resetting function $dev..." 20 | 21 | echo 1 > "/sys/bus/pci/devices/$dev/reset" 22 | 23 | 24 | -------------------------------------------------------------------------------- /example/AU50/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /scripts/pcie_reset.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | 5 | if [ -z "$dev" ]; then 6 | echo "Error: no device specified" 7 | exit 1 8 | fi 9 | 10 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 11 | dev="0000:$dev" 12 | fi 13 | 14 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 15 | echo "Error: device $dev not found" 16 | exit 1 17 | fi 18 | 19 | echo "Removing $dev..." 20 | 21 | echo 1 > "/sys/bus/pci/devices/$dev/remove" 22 | 23 | echo "Rescanning bus..." 24 | 25 | echo 1 > "/sys/bus/pci/rescan" 26 | 27 | 28 | -------------------------------------------------------------------------------- /example/AU200/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/AU250/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/AU280/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU108/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU118/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/fb2CG/fpga/led.tcl: -------------------------------------------------------------------------------- 1 | # Timing constraints for led_sreg_driver 2 | 3 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { 4 | puts "Inserting timing constraints for led_sreg_driver instance $inst" 5 | 6 | set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] 7 | 8 | if {[llength $select_ffs]} { 9 | set_property ASYNC_REG TRUE $select_ffs 10 | set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_axi/Makefile: -------------------------------------------------------------------------------- 1 | # Targets 2 | TARGETS:= 3 | 4 | # Subdirectories 5 | SUBDIRS = fpga 6 | SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) 7 | 8 | # Rules 9 | .PHONY: all 10 | all: $(SUBDIRS) $(TARGETS) 11 | 12 | .PHONY: $(SUBDIRS) 13 | $(SUBDIRS): 14 | cd $@ && $(MAKE) 15 | 16 | .PHONY: $(SUBDIRS_CLEAN) 17 | $(SUBDIRS_CLEAN): 18 | cd $(@:.clean=) && $(MAKE) clean 19 | 20 | .PHONY: clean 21 | clean: $(SUBDIRS_CLEAN) 22 | -rm -rf $(TARGETS) 23 | 24 | program: 25 | #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit 26 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/led.tcl: -------------------------------------------------------------------------------- 1 | # Timing constraints for led_sreg_driver 2 | 3 | foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] { 4 | puts "Inserting timing constraints for led_sreg_driver instance $inst" 5 | 6 | set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"] 7 | 8 | if {[llength $select_ffs]} { 9 | set_property ASYNC_REG TRUE $select_ffs 10 | set_false_path -to [get_pins "$inst/led_sync_reg_1_reg[*]/D"] 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /tox.ini: -------------------------------------------------------------------------------- 1 | # tox configuration 2 | [tox] 3 | envlist = py3 4 | skipsdist = True 5 | minversion = 3.2.0 6 | requires = virtualenv >= 16.1 7 | 8 | [gh-actions] 9 | python = 10 | 3.10: py3 11 | 12 | [testenv] 13 | deps = 14 | pytest == 7.2.1 15 | pytest-xdist == 3.1.0 16 | pytest-split == 0.8.0 17 | cocotb == 1.7.2 18 | cocotb-bus == 0.2.1 19 | cocotb-test == 0.2.4 20 | cocotbext-axi == 0.1.24 21 | cocotbext-pcie == 0.2.14 22 | jinja2 == 3.1.2 23 | 24 | commands = 25 | pytest {posargs:-n auto --verbose} 26 | 27 | # pytest configuration 28 | [pytest] 29 | testpaths = 30 | tb 31 | example 32 | norecursedirs = 33 | lib 34 | addopts = 35 | --ignore-glob=tb/test_*.py 36 | --import-mode importlib 37 | -------------------------------------------------------------------------------- /example/VCU108/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU108 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu095-ffva2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the VCU108 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/VCU118/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu9p-flga2104-2L-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the VCU118 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/ZCU106/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ZCU106 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU106 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xczu7ev-ffvc1156-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ZCU106 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/AU50/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U50 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U50 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu50-fsvh2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U50 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/VCU1525/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU1525 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU1525 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu9p-fsgd2104-2L-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the VCU1525 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/AU200/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U200 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U200 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu200-fsgd2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U200 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/AU250/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U250 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U250 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu250-figd2104-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U250 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/AU280/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U280 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U280 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcu280-fsvh2892-2L-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Alveo U280 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/520N_MX/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe BittWare 520N-MX Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the BittWare 520N-MX FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: 1SM21CHU2F53E2VG 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Intel Quartus Pro components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the 520N-MX board with Quartus Pro. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Terasic DE10-Agilex Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Terasic DE10-Agilex. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: AGFB014R24B2E2V 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Intel Quartus Pro components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the DE10-Agilex with Quartus Pro. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ExaNIC X25 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X25 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcku3p-ffvb676-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ExaNIC X25 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/fb2CG/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe fb2CG@KU15P Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Silicom fb2CG@KU15P FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcku15p-ffve1760-2-e 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado toolchain components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the fb2CG@KU15P board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ADM-PCIE-9V3 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcvu3p-ffvc1517-2-i 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ADM-PCIE-9V3 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ExaNIC X10 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X10 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: xcku035-fbva676-2-c 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Xilinx Vivado toolchain components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the ExaNIC X10 board with Vivado. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /scripts/pcie_ext_tag.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | en=$2 5 | 6 | if [ -z "$dev" ]; then 7 | echo "Error: no device specified" 8 | exit 1 9 | fi 10 | 11 | if [ -z "$en" ]; then 12 | echo "Error: must specify operation" 13 | exit 1 14 | fi 15 | 16 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 17 | dev="0000:$dev" 18 | fi 19 | 20 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 21 | echo "Error: device $dev not found" 22 | exit 1 23 | fi 24 | 25 | echo "Device control:" $(setpci -s $dev CAP_EXP+8.w) 26 | 27 | if (($en > 0)); then 28 | echo "Enabling ext tag on $dev..." 29 | setpci -s $dev CAP_EXP+8.w=0100:0100 30 | else 31 | echo "Disabling ext tag on $dev..." 32 | setpci -s $dev CAP_EXP+8.w=0000:0100 33 | fi 34 | 35 | echo "Device control:" $(setpci -s $dev CAP_EXP+8.w) 36 | -------------------------------------------------------------------------------- /example/VCU118/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU118 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU118 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu9p-flga2104-2L-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the VCU118 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ZCU106 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx ZCU106 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xczu7ev-ffvc1156-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the ZCU106 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/VCU108/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet VCU108 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU108 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu095-ffva2104-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the VCU108 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe VCU1525 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx VCU1525 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu9p-fsgd2104-2L-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the VCU1525 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/AU200/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U200 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U200 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcu200-fsgd2104-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the Alveo U200 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/AU250/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U250 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U250 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcu250-figd2104-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the Alveo U250 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/AU50/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U50 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U50 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | * FPGA: xcu50-fsvh2104-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the Alveo U50 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/AU280/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Alveo U280 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Xilinx Alveo U280 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | * FPGA: xcu280-fsvh2892-2L-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the Alveo U280 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ExaNIC X25 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X25 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcku3p-ffvb676-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the ExaNIC X25 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe fb2CG@KU15P Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Silicom fb2CG@KU15P FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcku15p-ffve1760-2-e 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the fb2CG@KU15P board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog Ethernet ExaNIC X10 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Exablaze ExaNIC X10 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcku035-fbva676-2-c 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the ExaNIC X10 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Intel Stratix 10 DX Development Kit Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Intel Stratix 10 DX Development Kit. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: 1SD280PT2F55E1VG 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Intel Quartus Pro components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Stratix 10 DX development kit with Quartus Pro. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_axi/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe ADM-PCIE-9V3 Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Alpha Data ADM-PCIE-9V3 FPGA board. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master 8 | module, and the PCIe AXI DMA module. A very simple Linux driver is included 9 | to test the FPGA design. 10 | 11 | FPGA: xcvu3p-ffvc1517-2-i 12 | 13 | ## How to build 14 | 15 | Run make to build. Ensure that the Xilinx Vivado toolchain components are 16 | in PATH. 17 | 18 | Run make to build the driver. Ensure the headers for the running kernel are 19 | installed, otherwise the driver cannot be compiled. 20 | 21 | ## How to test 22 | 23 | Run make program to program the ADM-PCIE-9V3 board with Vivado. Then load the 24 | driver with insmod example.ko. Check dmesg for the output. 25 | 26 | 27 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/README.md: -------------------------------------------------------------------------------- 1 | # Verilog PCIe Intel Stratix 10 MX Development Kit Example Design 2 | 3 | ## Introduction 4 | 5 | This example design targets the Intel Stratix 10 MX Development Kit. 6 | 7 | The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module. A very simple Linux driver is included to test the FPGA design. 8 | 9 | * FPGA: 1SM21BHU2F53E1VG (8 GB HBM2) or 1SM21CHU1F53E1VG (16 GB HBM2) 10 | 11 | ## How to build 12 | 13 | Run `make` to build. Ensure that the Intel Quartus Pro components are in PATH. 14 | 15 | Run `make` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. 16 | 17 | ## How to test 18 | 19 | Run `make program` to program the Stratix 10 MX development kit with Quartus Pro. Then load the driver with `insmod example.ko`. Check dmesg for the output. 20 | -------------------------------------------------------------------------------- /.github/workflows/regression-tests.yml: -------------------------------------------------------------------------------- 1 | name: Regression Tests 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | build: 7 | name: Python ${{ matrix.python-version }} (${{ matrix.group }}/20) 8 | runs-on: ubuntu-22.04 9 | 10 | strategy: 11 | matrix: 12 | python-version: ["3.10"] 13 | group: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] 14 | 15 | steps: 16 | - uses: actions/checkout@v3 17 | 18 | - name: Set up Python ${{ matrix.python-version }} 19 | uses: actions/setup-python@v4 20 | with: 21 | python-version: ${{ matrix.python-version }} 22 | 23 | - name: Install Icarus Verilog 24 | run: | 25 | sudo apt install -y --no-install-recommends iverilog 26 | 27 | - name: Install Python dependencies 28 | run: | 29 | python -m pip install --upgrade pip 30 | pip install tox tox-gh-actions 31 | 32 | - name: Test with tox 33 | run: tox -- -n auto --verbose --splits 20 --group ${{ matrix.group }} --splitting-algorithm least_duration 34 | -------------------------------------------------------------------------------- /scripts/pcie_disable_fatal_err.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | 5 | if [ -z "$dev" ]; then 6 | echo "Error: no device specified" 7 | exit 1 8 | fi 9 | 10 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 11 | dev="0000:$dev" 12 | fi 13 | 14 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 15 | echo "Error: device $dev not found" 16 | exit 1 17 | fi 18 | 19 | port=$(basename $(dirname $(readlink "/sys/bus/pci/devices/$dev"))) 20 | 21 | if [ ! -e "/sys/bus/pci/devices/$port" ]; then 22 | echo "Error: device $port not found" 23 | exit 1 24 | fi 25 | 26 | echo "Disabling fatal error reporting on port $port..." 27 | 28 | echo "Command:" $(setpci -s $port COMMAND) 29 | 30 | # clear SERR bit in command register 31 | setpci -s $port COMMAND=0000:0100 32 | 33 | echo "Command:" $(setpci -s $port COMMAND) 34 | 35 | echo "Device control:" $(setpci -s $port CAP_EXP+8.w) 36 | 37 | # clear fatal error reporting enable bit in device control register 38 | setpci -s $port CAP_EXP+8.w=0000:0004 39 | 40 | echo "Device control:" $(setpci -s $port CAP_EXP+8.w) 41 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- 1 | Copyright (c) 2018 Alex Forencich 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in 11 | all copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | THE SOFTWARE. 20 | -------------------------------------------------------------------------------- /scripts/pcie_hot_reset.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | 5 | if [ -z "$dev" ]; then 6 | echo "Error: no device specified" 7 | exit 1 8 | fi 9 | 10 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 11 | dev="0000:$dev" 12 | fi 13 | 14 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 15 | echo "Error: device $dev not found" 16 | exit 1 17 | fi 18 | 19 | port=$(basename $(dirname $(readlink "/sys/bus/pci/devices/$dev"))) 20 | 21 | if [ ! -e "/sys/bus/pci/devices/$port" ]; then 22 | echo "Error: device $port not found" 23 | exit 1 24 | fi 25 | 26 | echo "Removing $dev..." 27 | 28 | echo 1 > "/sys/bus/pci/devices/$dev/remove" 29 | 30 | echo "Performing hot reset of port $port..." 31 | 32 | echo "Bridge control:" $(setpci -s $port BRIDGE_CONTROL) 33 | 34 | setpci -s $port BRIDGE_CONTROL=40:40 35 | sleep 0.5 36 | setpci -s $port BRIDGE_CONTROL=00:40 37 | sleep 0.5 38 | 39 | echo "Rescanning bus..." 40 | 41 | if [ -e "/sys/bus/pci/devices/$port/dev_rescan" ]; then 42 | echo 1 > "/sys/bus/pci/devices/$port/dev_rescan" 43 | else 44 | echo 1 > "/sys/bus/pci/devices/$port/rescan" 45 | fi 46 | 47 | 48 | -------------------------------------------------------------------------------- /example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {256_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {806c} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie3_ultrascale_0] 32 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {256_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {0003} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1ce4} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie3_ultrascale_0] 32 | -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X4} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {128_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {906a} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/AU200/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {90c8} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {90fa} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {9032} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4c_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/VCU118/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {9076} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {95f5} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {a00e} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1c2c} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {9003} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {4144} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /example/AU280/fpga_axi/ip/pcie4c_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {512_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {9118} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | ] [get_ips pcie4c_uscale_plus_0] 32 | -------------------------------------------------------------------------------- /tb/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2020 Alex Forencich 2 | # 3 | # Permission is hereby granted, free of charge, to any person obtaining a copy 4 | # of this software and associated documentation files (the "Software"), to deal 5 | # in the Software without restriction, including without limitation the rights 6 | # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | # copies of the Software, and to permit persons to whom the Software is 8 | # furnished to do so, subject to the following conditions: 9 | # 10 | # The above copyright notice and this permission notice shall be included in 11 | # all copies or substantial portions of the Software. 12 | # 13 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 15 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 | # THE SOFTWARE. 20 | 21 | TOPTARGETS := all clean 22 | 23 | SUBDIRS := $(wildcard */.) 24 | 25 | $(TOPTARGETS): $(SUBDIRS) 26 | $(SUBDIRS): 27 | $(MAKE) -C $@ $(MAKECMDGOALS) 28 | 29 | .PHONY: $(TOPTARGETS) $(SUBDIRS) 30 | 31 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {256_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {0009} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1ce4} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_msi_enabled {true} \ 28 | CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ 29 | CONFIG.vendor_id {1234} \ 30 | CONFIG.en_msi_per_vec_masking {true} \ 31 | CONFIG.mode_selection {Advanced} \ 32 | CONFIG.en_gt_selection {true} \ 33 | CONFIG.MASTER_GT {GTYE4_CHANNEL_X0Y7} \ 34 | ] [get_ips pcie4_uscale_plus_0] 35 | -------------------------------------------------------------------------------- /scripts/pcie_set_speed.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | dev=$1 4 | speed=$2 5 | 6 | if [ -z "$dev" ]; then 7 | echo "Error: no device specified" 8 | exit 1 9 | fi 10 | 11 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 12 | dev="0000:$dev" 13 | fi 14 | 15 | if [ ! -e "/sys/bus/pci/devices/$dev" ]; then 16 | echo "Error: device $dev not found" 17 | exit 1 18 | fi 19 | 20 | pciec=$(setpci -s $dev CAP_EXP+02.W) 21 | pt=$(((0x$pciec & 0xF0) >> 4)) 22 | 23 | port=$(basename $(dirname $(readlink "/sys/bus/pci/devices/$dev"))) 24 | 25 | if (($pt == 0)) || (($pt == 1)) || (($pt == 5)); then 26 | dev=$port 27 | fi 28 | 29 | lc=$(setpci -s $dev CAP_EXP+0c.L) 30 | ls=$(setpci -s $dev CAP_EXP+12.W) 31 | 32 | max_speed=$((0x$lc & 0xF)) 33 | 34 | echo "Link capabilities:" $lc 35 | echo "Max link speed:" $max_speed 36 | echo "Link status:" $ls 37 | echo "Current link speed:" $((0x$ls & 0xF)) 38 | 39 | if [ -z "$speed" ]; then 40 | speed=$max_speed 41 | fi 42 | 43 | if (($speed > $max_speed)); then 44 | speed=$max_speed 45 | fi 46 | 47 | echo "Configuring $dev..." 48 | 49 | lc2=$(setpci -s $dev CAP_EXP+30.L) 50 | 51 | echo "Original link control 2:" $lc2 52 | echo "Original link target speed:" $((0x$lc2 & 0xF)) 53 | 54 | lc2n=$(printf "%08x" $(((0x$lc2 & 0xFFFFFFF0) | $speed))) 55 | 56 | echo "New target link speed:" $speed 57 | echo "New link control 2:" $lc2n 58 | 59 | setpci -s $dev CAP_EXP+30.L=$lc2n 60 | 61 | echo "Triggering link retraining..." 62 | 63 | setpci -s $dev CAP_EXP+10.L=20:20 64 | 65 | sleep 0.1 66 | 67 | ls=$(setpci -s $dev CAP_EXP+12.W) 68 | 69 | echo "Link status:" $ls 70 | echo "Current link speed:" $((0x$ls & 0xF)) 71 | -------------------------------------------------------------------------------- /example/520N_MX/fpga/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 20.4 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {1SM21CHU2F53E2VG} 8 | set_project_property DEVICE_FAMILY {Stratix 10} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # add the exports 22 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 23 | 24 | # set values for exposed HDL parameters 25 | 26 | # set the the module properties 27 | set_module_property BONUS_DATA { 28 | 29 | 30 | 31 | 32 | 33 | } 34 | set_module_property FILE {reset_release.ip} 35 | set_module_property GENERATION_ID {0x00000000} 36 | set_module_property NAME {reset_release} 37 | 38 | # save the system 39 | sync_sysinfo_parameters 40 | save_system reset_release 41 | } 42 | 43 | proc do_set_exported_interface_sysinfo_parameters {} { 44 | } 45 | 46 | # create all the systems, from bottom up 47 | do_create_reset_release 48 | 49 | # set system info parameters on exported interface, from bottom up 50 | do_set_exported_interface_sysinfo_parameters 51 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 20.4 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {1SM21CHU1F53E1VG} 8 | set_project_property DEVICE_FAMILY {Stratix 10} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # add the exports 22 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 23 | 24 | # set values for exposed HDL parameters 25 | 26 | # set the the module properties 27 | set_module_property BONUS_DATA { 28 | 29 | 30 | 31 | 32 | 33 | } 34 | set_module_property FILE {reset_release.ip} 35 | set_module_property GENERATION_ID {0x00000000} 36 | set_module_property NAME {reset_release} 37 | 38 | # save the system 39 | sync_sysinfo_parameters 40 | save_system reset_release 41 | } 42 | 43 | proc do_set_exported_interface_sysinfo_parameters {} { 44 | } 45 | 46 | # create all the systems, from bottom up 47 | do_create_reset_release 48 | 49 | # set system info parameters on exported interface, from bottom up 50 | do_set_exported_interface_sysinfo_parameters 51 | -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 21.3 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {AGFB014R24B2E2V} 8 | set_project_property DEVICE_FAMILY {Agilex} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # preserve ports for debug 22 | 23 | # add the exports 24 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 25 | 26 | # set values for exposed HDL parameters 27 | 28 | # set the the module properties 29 | set_module_property BONUS_DATA { 30 | 31 | 32 | 33 | 34 | 35 | } 36 | set_module_property FILE {reset_release.ip} 37 | set_module_property GENERATION_ID {0x00000000} 38 | set_module_property NAME {reset_release} 39 | 40 | # save the system 41 | sync_sysinfo_parameters 42 | save_system reset_release 43 | } 44 | 45 | proc do_set_exported_interface_sysinfo_parameters {} { 46 | } 47 | 48 | # create all the systems, from bottom up 49 | do_create_reset_release 50 | 51 | # set system info parameters on exported interface, from bottom up 52 | do_set_exported_interface_sysinfo_parameters 53 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/ip/reset_release.tcl: -------------------------------------------------------------------------------- 1 | package require -exact qsys 21.3 2 | 3 | # create the system "reset_release" 4 | proc do_create_reset_release {} { 5 | # create the system 6 | create_system reset_release 7 | set_project_property DEVICE {1SD280PT2F55E1VG} 8 | set_project_property DEVICE_FAMILY {Stratix 10} 9 | set_project_property HIDE_FROM_IP_CATALOG {true} 10 | set_use_testbench_naming_pattern 0 {} 11 | 12 | # add HDL parameters 13 | 14 | # add the components 15 | add_instance s10_user_rst_clkgate_0 altera_s10_user_rst_clkgate 16 | set_instance_parameter_value s10_user_rst_clkgate_0 {outputType} {Conduit Interface} 17 | set_instance_property s10_user_rst_clkgate_0 AUTO_EXPORT true 18 | 19 | # add wirelevel expressions 20 | 21 | # preserve ports for debug 22 | 23 | # add the exports 24 | set_interface_property ninit_done EXPORT_OF s10_user_rst_clkgate_0.ninit_done 25 | 26 | # set values for exposed HDL parameters 27 | 28 | # set the the module properties 29 | set_module_property BONUS_DATA { 30 | 31 | 32 | 33 | 34 | 35 | } 36 | set_module_property FILE {reset_release.ip} 37 | set_module_property GENERATION_ID {0x00000000} 38 | set_module_property NAME {reset_release} 39 | 40 | # save the system 41 | sync_sysinfo_parameters 42 | save_system reset_release 43 | } 44 | 45 | proc do_set_exported_interface_sysinfo_parameters {} { 46 | } 47 | 48 | # create all the systems, from bottom up 49 | do_create_reset_release 50 | 51 | # set system info parameters on exported interface, from bottom up 52 | do_set_exported_interface_sysinfo_parameters 53 | -------------------------------------------------------------------------------- /example/VCU108/fpga/ip/pcie3_ultrascale_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {true} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {256_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {806c} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_bar4_64bit {true} \ 28 | CONFIG.pf0_bar4_prefetchable {true} \ 29 | CONFIG.pf0_bar4_enabled {true} \ 30 | CONFIG.pf0_bar4_type {Memory} \ 31 | CONFIG.pf0_bar4_scale {Kilobytes} \ 32 | CONFIG.pf0_bar4_size {64} \ 33 | CONFIG.pf0_msi_enabled {false} \ 34 | CONFIG.pf0_msix_enabled {true} \ 35 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 36 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 38 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 40 | CONFIG.vendor_id {1234} \ 41 | ] [get_ips pcie3_ultrascale_0] 42 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/ip/pcie3_ultrascale_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {true} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {256_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {0003} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1ce4} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_bar4_64bit {true} \ 28 | CONFIG.pf0_bar4_prefetchable {true} \ 29 | CONFIG.pf0_bar4_enabled {true} \ 30 | CONFIG.pf0_bar4_type {Memory} \ 31 | CONFIG.pf0_bar4_scale {Kilobytes} \ 32 | CONFIG.pf0_bar4_size {64} \ 33 | CONFIG.pf0_msi_enabled {false} \ 34 | CONFIG.pf0_msix_enabled {true} \ 35 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 36 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 38 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 40 | CONFIG.vendor_id {1234} \ 41 | ] [get_ips pcie3_ultrascale_0] 42 | -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_PART = xczu7ev-ffvc1156-2-e 4 | FPGA_TOP = fpga 5 | FPGA_ARCH = zynquplus 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/debounce_switch.v 11 | SYN_FILES += rtl/sync_reset.v 12 | SYN_FILES += rtl/sync_signal.v 13 | SYN_FILES += rtl/axi_ram.v 14 | SYN_FILES += rtl/axis_register.v 15 | SYN_FILES += lib/pcie/rtl/axis_arb_mux.v 16 | SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v 17 | SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v 18 | SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v 19 | SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v 20 | SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v 21 | SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v 22 | SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v 23 | SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v 24 | SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v 25 | SYN_FILES += lib/pcie/rtl/pcie_us_msi.v 26 | SYN_FILES += lib/pcie/rtl/arbiter.v 27 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 28 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 29 | 30 | # XDC files 31 | XDC_FILES = fpga.xdc 32 | 33 | # IP 34 | IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl 35 | 36 | include ../common/vivado.mk 37 | 38 | program: $(FPGA_TOP).bit 39 | echo "open_hw" > program.tcl 40 | echo "connect_hw_server" >> program.tcl 41 | echo "open_hw_target" >> program.tcl 42 | echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl 43 | echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl 44 | echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl 45 | echo "program_hw_devices [current_hw_device]" >> program.tcl 46 | echo "exit" >> program.tcl 47 | vivado -nojournal -nolog -mode batch -source program.tcl 48 | 49 | -------------------------------------------------------------------------------- /example/common/driver/example/example_driver.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: MIT */ 2 | /* 3 | * Copyright (c) 2018-2021 Alex Forencich 4 | * 5 | * Permission is hereby granted, free of charge, to any person obtaining a copy 6 | * of this software and associated documentation files (the "Software"), to deal 7 | * in the Software without restriction, including without limitation the rights 8 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | * copies of the Software, and to permit persons to whom the Software is 10 | * furnished to do so, subject to the following conditions: 11 | * 12 | * The above copyright notice and this permission notice shall be included in 13 | * all copies or substantial portions of the Software. 14 | * 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | * THE SOFTWARE. 22 | */ 23 | 24 | #ifndef EXAMPLE_DRIVER_H 25 | #define EXAMPLE_DRIVER_H 26 | 27 | #include 28 | 29 | #define DRIVER_NAME "edev" 30 | #define DRIVER_VERSION "0.1" 31 | 32 | struct example_dev { 33 | struct pci_dev *pdev; 34 | struct device *dev; 35 | 36 | // BAR pointers 37 | void __iomem *bar[6]; 38 | resource_size_t bar_len[6]; 39 | 40 | // DMA buffer 41 | size_t dma_region_len; 42 | void *dma_region; 43 | dma_addr_t dma_region_addr; 44 | 45 | int irqcount; 46 | }; 47 | 48 | #endif /* EXAMPLE_DRIVER_H */ 49 | -------------------------------------------------------------------------------- /example/ZCU106/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X4} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {128_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {906a} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_bar4_64bit {true} \ 28 | CONFIG.pf0_bar4_prefetchable {true} \ 29 | CONFIG.pf0_bar4_enabled {true} \ 30 | CONFIG.pf0_bar4_type {Memory} \ 31 | CONFIG.pf0_bar4_scale {Kilobytes} \ 32 | CONFIG.pf0_bar4_size {64} \ 33 | CONFIG.pf0_msi_enabled {false} \ 34 | CONFIG.pf0_msix_enabled {true} \ 35 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 36 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 38 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 40 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 41 | CONFIG.vendor_id {1234} \ 42 | ] [get_ips pcie4_uscale_plus_0] 43 | -------------------------------------------------------------------------------- /example/520N_MX/fpga/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Stratix 10 MX" 5 | FPGA_DEVICE = 1SM21CHU2F53E2VG 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/sync_reset.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/common/example_core_pcie_s10.v 13 | SYN_FILES += rtl/common/example_core_pcie.v 14 | SYN_FILES += rtl/common/example_core.v 15 | SYN_FILES += rtl/common/axi_ram.v 16 | SYN_FILES += lib/pcie/rtl/pcie_s10_if.v 17 | SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v 18 | SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v 19 | SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v 20 | SYN_FILES += lib/pcie/rtl/pcie_axil_master.v 21 | SYN_FILES += lib/pcie/rtl/pcie_axi_master.v 22 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v 23 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v 24 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v 25 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v 26 | SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v 27 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v 28 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v 29 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v 30 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v 31 | SYN_FILES += lib/pcie/rtl/pcie_msix.v 32 | SYN_FILES += lib/pcie/rtl/dma_if_pcie.v 33 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v 34 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v 35 | SYN_FILES += lib/pcie/rtl/dma_psdpram.v 36 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 37 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 38 | 39 | # IP files 40 | IP_TCL_FILES += ip/reset_release.tcl 41 | IP_TCL_FILES += ip/pcie.tcl 42 | 43 | # QSF files 44 | QSF_FILES = fpga.qsf 45 | 46 | # SDC files 47 | SDC_FILES = fpga.sdc 48 | 49 | include ../common/quartus_pro.mk 50 | 51 | program: fpga 52 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" 53 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/fpga_1sm21b/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Stratix 10 MX" 5 | FPGA_DEVICE = 1SM21BHU2F53E1VG 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/sync_reset.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/common/example_core_pcie_s10.v 13 | SYN_FILES += rtl/common/example_core_pcie.v 14 | SYN_FILES += rtl/common/example_core.v 15 | SYN_FILES += rtl/common/axi_ram.v 16 | SYN_FILES += lib/pcie/rtl/pcie_s10_if.v 17 | SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v 18 | SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v 19 | SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v 20 | SYN_FILES += lib/pcie/rtl/pcie_axil_master.v 21 | SYN_FILES += lib/pcie/rtl/pcie_axi_master.v 22 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v 23 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v 24 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v 25 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v 26 | SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v 27 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v 28 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v 29 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v 30 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v 31 | SYN_FILES += lib/pcie/rtl/pcie_msix.v 32 | SYN_FILES += lib/pcie/rtl/dma_if_pcie.v 33 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v 34 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v 35 | SYN_FILES += lib/pcie/rtl/dma_psdpram.v 36 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 37 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 38 | 39 | # IP files 40 | IP_TCL_FILES += ip/reset_release.tcl 41 | IP_TCL_FILES += ip/pcie.tcl 42 | 43 | # QSF files 44 | QSF_FILES = fpga.qsf 45 | 46 | # SDC files 47 | SDC_FILES = fpga.sdc 48 | 49 | include ../common/quartus_pro.mk 50 | 51 | program: fpga 52 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" 53 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/fpga_1sm21c/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Stratix 10 MX" 5 | FPGA_DEVICE = 1SM21CHU1F53E1VG 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/sync_reset.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/common/example_core_pcie_s10.v 13 | SYN_FILES += rtl/common/example_core_pcie.v 14 | SYN_FILES += rtl/common/example_core.v 15 | SYN_FILES += rtl/common/axi_ram.v 16 | SYN_FILES += lib/pcie/rtl/pcie_s10_if.v 17 | SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v 18 | SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v 19 | SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v 20 | SYN_FILES += lib/pcie/rtl/pcie_axil_master.v 21 | SYN_FILES += lib/pcie/rtl/pcie_axi_master.v 22 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v 23 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v 24 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v 25 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v 26 | SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v 27 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v 28 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v 29 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v 30 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v 31 | SYN_FILES += lib/pcie/rtl/pcie_msix.v 32 | SYN_FILES += lib/pcie/rtl/dma_if_pcie.v 33 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v 34 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v 35 | SYN_FILES += lib/pcie/rtl/dma_psdpram.v 36 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 37 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 38 | 39 | # IP files 40 | IP_TCL_FILES += ip/reset_release.tcl 41 | IP_TCL_FILES += ip/pcie.tcl 42 | 43 | # QSF files 44 | QSF_FILES = fpga.qsf 45 | 46 | # SDC files 47 | SDC_FILES = fpga.sdc 48 | 49 | include ../common/quartus_pro.mk 50 | 51 | program: fpga 52 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" 53 | -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/fpga_24B/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Agilex" 5 | FPGA_DEVICE = AGFB014R24B2E2V 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/sync_reset.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/common/example_core_pcie_ptile.v 13 | SYN_FILES += rtl/common/example_core_pcie.v 14 | SYN_FILES += rtl/common/example_core.v 15 | SYN_FILES += rtl/common/axi_ram.v 16 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v 17 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v 18 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v 19 | SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v 20 | SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v 21 | SYN_FILES += lib/pcie/rtl/pcie_axil_master.v 22 | SYN_FILES += lib/pcie/rtl/pcie_axi_master.v 23 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v 24 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v 25 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v 26 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v 27 | SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v 28 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v 29 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v 30 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v 31 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v 32 | SYN_FILES += lib/pcie/rtl/pcie_msix.v 33 | SYN_FILES += lib/pcie/rtl/dma_if_pcie.v 34 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v 35 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v 36 | SYN_FILES += lib/pcie/rtl/dma_psdpram.v 37 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 38 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 39 | 40 | # IP files 41 | IP_TCL_FILES += ip/reset_release.tcl 42 | IP_TCL_FILES += ip/pcie.tcl 43 | 44 | # QSF files 45 | QSF_FILES = fpga.qsf 46 | 47 | # SDC files 48 | SDC_FILES = fpga.sdc 49 | 50 | include ../common/quartus_pro.mk 51 | 52 | program: fpga 53 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" 54 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/fpga/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Stratix 10 DX" 5 | FPGA_DEVICE = 1SD280PT2F55E1VG 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/sync_reset.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/common/example_core_pcie_ptile.v 13 | SYN_FILES += rtl/common/example_core_pcie.v 14 | SYN_FILES += rtl/common/example_core.v 15 | SYN_FILES += rtl/common/axi_ram.v 16 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v 17 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v 18 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v 19 | SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v 20 | SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v 21 | SYN_FILES += lib/pcie/rtl/pcie_axil_master.v 22 | SYN_FILES += lib/pcie/rtl/pcie_axi_master.v 23 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v 24 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v 25 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v 26 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v 27 | SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v 28 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v 29 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v 30 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v 31 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v 32 | SYN_FILES += lib/pcie/rtl/pcie_msix.v 33 | SYN_FILES += lib/pcie/rtl/dma_if_pcie.v 34 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v 35 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v 36 | SYN_FILES += lib/pcie/rtl/dma_psdpram.v 37 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 38 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 39 | 40 | # IP files 41 | IP_TCL_FILES += ip/reset_release.tcl 42 | IP_TCL_FILES += ip/pcie.tcl 43 | 44 | # QSF files 45 | QSF_FILES = fpga.qsf 46 | 47 | # SDC files 48 | SDC_FILES = fpga.sdc 49 | 50 | include ../common/quartus_pro.mk 51 | 52 | program: fpga 53 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@2" 54 | -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/fpga_24AR0/Makefile: -------------------------------------------------------------------------------- 1 | 2 | # FPGA settings 3 | FPGA_TOP = fpga 4 | FPGA_FAMILY = "Agilex" 5 | FPGA_DEVICE = AGFB014R24A2E2VR0 6 | 7 | # Files for synthesis 8 | SYN_FILES = rtl/fpga.v 9 | SYN_FILES += rtl/fpga_core.v 10 | SYN_FILES += rtl/sync_reset.v 11 | SYN_FILES += rtl/sync_signal.v 12 | SYN_FILES += rtl/common/example_core_pcie_ptile.v 13 | SYN_FILES += rtl/common/example_core_pcie.v 14 | SYN_FILES += rtl/common/example_core.v 15 | SYN_FILES += rtl/common/axi_ram.v 16 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if.v 17 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if_rx.v 18 | SYN_FILES += lib/pcie/rtl/pcie_ptile_if_tx.v 19 | SYN_FILES += lib/pcie/rtl/pcie_ptile_cfg.v 20 | SYN_FILES += lib/pcie/rtl/pcie_ptile_fc_counter.v 21 | SYN_FILES += lib/pcie/rtl/pcie_axil_master.v 22 | SYN_FILES += lib/pcie/rtl/pcie_axi_master.v 23 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v 24 | SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v 25 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v 26 | SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v 27 | SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v 28 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fc_count.v 29 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v 30 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v 31 | SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v 32 | SYN_FILES += lib/pcie/rtl/pcie_msix.v 33 | SYN_FILES += lib/pcie/rtl/dma_if_pcie.v 34 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v 35 | SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v 36 | SYN_FILES += lib/pcie/rtl/dma_psdpram.v 37 | SYN_FILES += lib/pcie/rtl/priority_encoder.v 38 | SYN_FILES += lib/pcie/rtl/pulse_merge.v 39 | 40 | # IP files 41 | IP_TCL_FILES += ip/reset_release.tcl 42 | IP_TCL_FILES += ip/pcie.tcl 43 | 44 | # QSF files 45 | QSF_FILES = fpga.qsf 46 | 47 | # SDC files 48 | SDC_FILES = fpga.sdc 49 | 50 | include ../common/quartus_pro.mk 51 | 52 | program: fpga 53 | quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1" 54 | -------------------------------------------------------------------------------- /example/AU50/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU200/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU200/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU250/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU250/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU280/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU280/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU50/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/VCU108/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/VCU118/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/VCU1525/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ZCU106/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/fb2CG/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/fb2CG/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/VCU108/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/VCU118/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/VCU1525/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ZCU106/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga_axi/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset #( 36 | parameter N=2 // depth of synchronizer 37 | )( 38 | input wire clk, 39 | input wire rst, 40 | output wire sync_reset_out 41 | ); 42 | 43 | reg [N-1:0] sync_reg = {N{1'b1}}; 44 | 45 | assign sync_reset_out = sync_reg[N-1]; 46 | 47 | always @(posedge clk or posedge rst) begin 48 | if (rst) 49 | sync_reg <= {N{1'b1}}; 50 | else 51 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 52 | end 53 | 54 | endmodule 55 | 56 | `resetall 57 | -------------------------------------------------------------------------------- /example/AU200/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {90c8} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/AU250/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {90fa} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/AU280/fpga/ip/pcie4c_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {9118} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4c_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/AU50/fpga/ip/pcie4c_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {9032} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4c_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/VCU118/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {9076} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/VCU1525/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {95f5} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/fb2CG/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {a00e} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1c2c} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/ADM_PCIE_9V3/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ 7 | CONFIG.AXISTEN_IF_EXT_512_CQ_STRADDLE {true} \ 8 | CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {true} \ 9 | CONFIG.AXISTEN_IF_EXT_512_RC_4TLP_STRADDLE {true} \ 10 | CONFIG.axisten_if_enable_client_tag {true} \ 11 | CONFIG.axisten_if_width {512_bit} \ 12 | CONFIG.extended_tag_field {true} \ 13 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 14 | CONFIG.axisten_freq {250} \ 15 | CONFIG.PF0_CLASS_CODE {058000} \ 16 | CONFIG.PF0_DEVICE_ID {0001} \ 17 | CONFIG.PF0_SUBSYSTEM_ID {9003} \ 18 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {4144} \ 19 | CONFIG.pf0_bar0_64bit {true} \ 20 | CONFIG.pf0_bar0_prefetchable {true} \ 21 | CONFIG.pf0_bar0_scale {Megabytes} \ 22 | CONFIG.pf0_bar0_size {16} \ 23 | CONFIG.pf0_bar2_64bit {true} \ 24 | CONFIG.pf0_bar2_prefetchable {true} \ 25 | CONFIG.pf0_bar2_enabled {true} \ 26 | CONFIG.pf0_bar2_type {Memory} \ 27 | CONFIG.pf0_bar2_scale {Megabytes} \ 28 | CONFIG.pf0_bar2_size {16} \ 29 | CONFIG.pf0_bar4_64bit {true} \ 30 | CONFIG.pf0_bar4_prefetchable {true} \ 31 | CONFIG.pf0_bar4_enabled {true} \ 32 | CONFIG.pf0_bar4_type {Memory} \ 33 | CONFIG.pf0_bar4_scale {Kilobytes} \ 34 | CONFIG.pf0_bar4_size {64} \ 35 | CONFIG.pf0_msi_enabled {false} \ 36 | CONFIG.pf0_msix_enabled {true} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 38 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 40 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 41 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 42 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 43 | CONFIG.vendor_id {1234} \ 44 | ] [get_ips pcie4_uscale_plus_0] 45 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/ip/pcie4_uscale_plus_0.tcl: -------------------------------------------------------------------------------- 1 | 2 | create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 3 | 4 | set_property -dict [list \ 5 | CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ 6 | CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ 7 | CONFIG.AXISTEN_IF_RC_STRADDLE {true} \ 8 | CONFIG.axisten_if_enable_client_tag {true} \ 9 | CONFIG.axisten_if_width {256_bit} \ 10 | CONFIG.extended_tag_field {true} \ 11 | CONFIG.pf0_dev_cap_max_payload {1024_bytes} \ 12 | CONFIG.axisten_freq {250} \ 13 | CONFIG.PF0_CLASS_CODE {058000} \ 14 | CONFIG.PF0_DEVICE_ID {0001} \ 15 | CONFIG.PF0_SUBSYSTEM_ID {0009} \ 16 | CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1ce4} \ 17 | CONFIG.pf0_bar0_64bit {true} \ 18 | CONFIG.pf0_bar0_prefetchable {true} \ 19 | CONFIG.pf0_bar0_scale {Megabytes} \ 20 | CONFIG.pf0_bar0_size {16} \ 21 | CONFIG.pf0_bar2_64bit {true} \ 22 | CONFIG.pf0_bar2_prefetchable {true} \ 23 | CONFIG.pf0_bar2_enabled {true} \ 24 | CONFIG.pf0_bar2_type {Memory} \ 25 | CONFIG.pf0_bar2_scale {Megabytes} \ 26 | CONFIG.pf0_bar2_size {16} \ 27 | CONFIG.pf0_bar4_64bit {true} \ 28 | CONFIG.pf0_bar4_prefetchable {true} \ 29 | CONFIG.pf0_bar4_enabled {true} \ 30 | CONFIG.pf0_bar4_type {Memory} \ 31 | CONFIG.pf0_bar4_scale {Kilobytes} \ 32 | CONFIG.pf0_bar4_size {64} \ 33 | CONFIG.pf0_msi_enabled {false} \ 34 | CONFIG.pf0_msix_enabled {true} \ 35 | CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \ 36 | CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \ 37 | CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \ 38 | CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \ 39 | CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \ 40 | CONFIG.MSI_X_OPTIONS {MSI-X_External} \ 41 | CONFIG.vendor_id {1234} \ 42 | CONFIG.mode_selection {Advanced} \ 43 | CONFIG.en_gt_selection {true} \ 44 | CONFIG.MASTER_GT {GTYE4_CHANNEL_X0Y7} \ 45 | ] [get_ips pcie4_uscale_plus_0] 46 | -------------------------------------------------------------------------------- /example/520N_MX/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2020 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset # 36 | ( 37 | // depth of synchronizer 38 | parameter N = 2 39 | ) 40 | ( 41 | input wire clk, 42 | input wire rst, 43 | output wire out 44 | ); 45 | 46 | (* srl_style = "register" *) 47 | reg [N-1:0] sync_reg = {N{1'b1}}; 48 | 49 | assign out = sync_reg[N-1]; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | sync_reg <= {N{1'b1}}; 54 | end else begin 55 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 56 | end 57 | end 58 | 59 | endmodule 60 | 61 | `resetall 62 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2020 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset # 36 | ( 37 | // depth of synchronizer 38 | parameter N = 2 39 | ) 40 | ( 41 | input wire clk, 42 | input wire rst, 43 | output wire out 44 | ); 45 | 46 | (* srl_style = "register" *) 47 | reg [N-1:0] sync_reg = {N{1'b1}}; 48 | 49 | assign out = sync_reg[N-1]; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | sync_reg <= {N{1'b1}}; 54 | end else begin 55 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 56 | end 57 | end 58 | 59 | endmodule 60 | 61 | `resetall 62 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2020 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset # 36 | ( 37 | // depth of synchronizer 38 | parameter N = 2 39 | ) 40 | ( 41 | input wire clk, 42 | input wire rst, 43 | output wire out 44 | ); 45 | 46 | (* srl_style = "register" *) 47 | reg [N-1:0] sync_reg = {N{1'b1}}; 48 | 49 | assign out = sync_reg[N-1]; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | sync_reg <= {N{1'b1}}; 54 | end else begin 55 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 56 | end 57 | end 58 | 59 | endmodule 60 | 61 | `resetall 62 | -------------------------------------------------------------------------------- /example/DE10_Agilex/fpga/rtl/sync_reset.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2020 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1ns / 1ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an active-high asynchronous reset signal to a given clock by 33 | * using a pipeline of N registers. 34 | */ 35 | module sync_reset # 36 | ( 37 | // depth of synchronizer 38 | parameter N = 2 39 | ) 40 | ( 41 | input wire clk, 42 | input wire rst, 43 | output wire out 44 | ); 45 | 46 | (* srl_style = "register" *) 47 | reg [N-1:0] sync_reg = {N{1'b1}}; 48 | 49 | assign out = sync_reg[N-1]; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | sync_reg <= {N{1'b1}}; 54 | end else begin 55 | sync_reg <= {sync_reg[N-2:0], 1'b0}; 56 | end 57 | end 58 | 59 | endmodule 60 | 61 | `resetall 62 | -------------------------------------------------------------------------------- /example/AU200/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU250/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU280/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU50/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/fb2CG/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/520N_MX/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU200/fpga_axi/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU250/fpga_axi/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU280/fpga_axi/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/AU50/fpga_axi/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ExaNIC_X10/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/ExaNIC_X25/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/S10DX_DK/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/S10MX_DK/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU108/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU108/fpga_axi/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU118/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU118/fpga_axi/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | -------------------------------------------------------------------------------- /example/VCU1525/fpga/rtl/sync_signal.v: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) 2014-2018 Alex Forencich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in 13 | all copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 21 | THE SOFTWARE. 22 | 23 | */ 24 | 25 | // Language: Verilog-2001 26 | 27 | `resetall 28 | `timescale 1 ns / 1 ps 29 | `default_nettype none 30 | 31 | /* 32 | * Synchronizes an asyncronous signal to a given clock by using a pipeline of 33 | * two registers. 34 | */ 35 | module sync_signal #( 36 | parameter WIDTH=1, // width of the input and output signals 37 | parameter N=2 // depth of synchronizer 38 | )( 39 | input wire clk, 40 | input wire [WIDTH-1:0] in, 41 | output wire [WIDTH-1:0] out 42 | ); 43 | 44 | reg [WIDTH-1:0] sync_reg[N-1:0]; 45 | 46 | /* 47 | * The synchronized output is the last register in the pipeline. 48 | */ 49 | assign out = sync_reg[N-1]; 50 | 51 | integer k; 52 | 53 | always @(posedge clk) begin 54 | sync_reg[0] <= in; 55 | for (k = 1; k < N; k = k + 1) begin 56 | sync_reg[k] <= sync_reg[k-1]; 57 | end 58 | end 59 | 60 | endmodule 61 | 62 | `resetall 63 | --------------------------------------------------------------------------------