├── 20_SYNTH ├── discrete_RT.constr ├── LTL_LED.lib ├── discrete_RTPG_techmap.v ├── 2N7002.lib ├── DMG301.lib ├── amux.lib ├── spice_testbench.sp ├── flow_discrete_74LVC.ys ├── flow_discrete_nmos.ys ├── flow_discrete_LTL.ys ├── discrete_amux_logic_spice_subckt.lib ├── flow_discrete_RTPG.ys ├── flow_discrete_amux.ys ├── discrete_amux_logic_cells.v ├── cells_wokwi.v ├── discrete_RTPG_logic_cells.v ├── discrete_RT_techmap.v ├── discrete_RT_logic_cells.v ├── PMBT3904.lib ├── PMBT2369.lib ├── discrete_LTL_logic_cells.v ├── flow_discrete_RT.ys ├── flow_v_discrete_LTL.ys ├── discrete_nmos_logic_cells.v ├── RTL_NPN.lib ├── discrete_74LVC_logic_liberty.lib ├── discrete_RTPG_logic_liberty.lib ├── discrete_amux_logic_liberty.lib ├── discrete_RT_logic_liberty.lib ├── microcell_spice_subckt.lib ├── discrete_nmos_logic_liberty.lib └── discrete_LTL_logic_liberty.lib ├── .gitignore ├── Images ├── example.png ├── mcpu_routed.png ├── flow_numbered.png ├── screenshot_pip.png ├── screenshot_placement.png ├── screenshot_synthesis.png └── PCBFlow_numbered.drawio ├── run_11_Digital_Simulation.sh ├── run_10_HDL_analysis.sh ├── run_30_Placement.sh ├── run_21_Post_Synthesis_Simulation.sh ├── run_31_Post_Layout_Simulation.sh ├── run_32_Post_Layout_Simulation_tpd.sh ├── run_33_Post_Layout_Simulation_fmax.sh ├── run_34_Post_Layout_Simulation_mcpu.sh ├── clean_all.sh ├── 10_HDL ├── gates.vhd ├── counter_clr.vhd ├── counter.vhd ├── gtkviewsettings.gtkw ├── counter_tb.vhd ├── moregates.vhd ├── dice_johnson.vhd ├── Makefile ├── dice.vhd ├── mcpu.vhd ├── mcpu_clr.vhd └── mcpu_sepdata.vhd ├── LICENSE ├── 30_PLACE ├── spice_testbench_extracted.sp ├── spice_testbench_mcpu_extracted.sp ├── spice_testbench_tpd_extracted.sp ├── spice_testbench_fmax_extracted.sp └── board_template.brd ├── run_22_Synthesis_Verilog.sh ├── run_25_Synthesis_Wokwi.sh ├── run_20_Synthesis.sh ├── README.md └── Docs └── Technologies.md /20_SYNTH/discrete_RT.constr: -------------------------------------------------------------------------------- 1 | set_driving_cell rt_BUF 2 | set_load 8.0 -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | Work/** 2 | *.cf 3 | *.ghw 4 | *.o 5 | *.lst 6 | *.txt 7 | 10_HDL/testbench -------------------------------------------------------------------------------- /Images/example.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cpldcpu/PCBFlow/HEAD/Images/example.png -------------------------------------------------------------------------------- /run_11_Digital_Simulation.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd 10_HDL 4 | make view 5 | cd .. 6 | -------------------------------------------------------------------------------- /run_10_HDL_analysis.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | cd 10_HDL 4 | make work-obj93.cf 5 | cd .. 6 | -------------------------------------------------------------------------------- /Images/mcpu_routed.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cpldcpu/PCBFlow/HEAD/Images/mcpu_routed.png -------------------------------------------------------------------------------- /Images/flow_numbered.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cpldcpu/PCBFlow/HEAD/Images/flow_numbered.png -------------------------------------------------------------------------------- /Images/screenshot_pip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cpldcpu/PCBFlow/HEAD/Images/screenshot_pip.png -------------------------------------------------------------------------------- /Images/screenshot_placement.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cpldcpu/PCBFlow/HEAD/Images/screenshot_placement.png -------------------------------------------------------------------------------- /Images/screenshot_synthesis.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cpldcpu/PCBFlow/HEAD/Images/screenshot_synthesis.png -------------------------------------------------------------------------------- /run_30_Placement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Run placement 3 | 4 | cd Work 5 | python3 ../30_PLACE/PCBPlace.py 6 | cd .. 7 | -------------------------------------------------------------------------------- /run_21_Post_Synthesis_Simulation.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Simulated synthesized logic circuit 3 | # Invokes NGspice 4 | 5 | cd Work 6 | ngspice ../20_SYNTH/spice_testbench.sp 7 | -------------------------------------------------------------------------------- /run_31_Post_Layout_Simulation.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Simulated synthesized logic circuit 3 | # Invokes NGspice 4 | # 5 | 6 | cd Work 7 | ngspice ../30_PLACE/spice_testbench_extracted.sp 8 | -------------------------------------------------------------------------------- /run_32_Post_Layout_Simulation_tpd.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Simulated synthesized logic circuit 3 | # Invokes NGspice 4 | # 5 | 6 | cd Work 7 | ngspice ../30_PLACE/spice_testbench_tpd_extracted.sp 8 | -------------------------------------------------------------------------------- /run_33_Post_Layout_Simulation_fmax.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Simulated synthesized logic circuit 3 | # Invokes NGspice 4 | # 5 | 6 | cd Work 7 | ngspice ../30_PLACE/spice_testbench_fmax_extracted.sp 8 | -------------------------------------------------------------------------------- /run_34_Post_Layout_Simulation_mcpu.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Simulated synthesized logic circuit 3 | # Invokes NGspice 4 | # 5 | 6 | cd Work 7 | ngspice ../30_PLACE/spice_testbench_mcpu_extracted.sp 8 | -------------------------------------------------------------------------------- /clean_all.sh: -------------------------------------------------------------------------------- 1 | echo "Cleaning HDL files" 2 | cd 10_HDL/ 3 | make clean 4 | cd .. 5 | 6 | echo "Cleaning work directory" 7 | cd Work/ 8 | rm -f *.cf *.dot *.pdf *.txt *.sp *.o *.json *.csv *.brd *.pro *.b* *.vcd *.v 9 | cd .. -------------------------------------------------------------------------------- /20_SYNTH/LTL_LED.lib: -------------------------------------------------------------------------------- 1 | 2 | * LED Models for LTL 3 | 4 | * Base LED (Green) 5 | .MODEL LEDW D(Cjo=30p IS=3.9447E-12 N=4.9950 RS=16.382) 6 | 7 | * Wired and LED (Red) 8 | .MODEL LEDR D(Cjo=10p IS=2.6432E-24 N=1.4571 RS=2.0918 IKF=3.9036E-3) 9 | -------------------------------------------------------------------------------- /10_HDL/gates.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity gatesx is 6 | port (a,b: in std_logic; 7 | c,d: in std_logic; 8 | x,y,cout: out std_logic 9 | ); 10 | end; 11 | 12 | architecture main of gatesx is 13 | signal adder: unsigned(1 downto 0); 14 | begin 15 | x <= a AND b; 16 | 17 | adder <= ("0" & c) + ("0" & d); 18 | y <= adder(0); 19 | cout <= adder(1); 20 | end; 21 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_RTPG_techmap.v: -------------------------------------------------------------------------------- 1 | 2 | module \$_DLATCH_P_ (input E, input D, output Q); 3 | LATCH_N _TECHMAP_REPLACE_ ( 4 | .EN(!E), 5 | .D(D), 6 | .Q(Q) 7 | ); 8 | endmodule 9 | 10 | module \$_DLATCH_N_ (input E, input D, output Q); 11 | LATCH_N _TECHMAP_REPLACE_ ( 12 | .EN(E), 13 | .D(D), 14 | .Q(Q) 15 | ); 16 | endmodule 17 | 18 | module \$_TBUF_ (input A, input E, output Y); 19 | TBUF _TECHMAP_REPLACE_ ( 20 | .A(A), 21 | .E(E), 22 | .Y(Y) 23 | ); 24 | endmodule 25 | -------------------------------------------------------------------------------- /10_HDL/counter_clr.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity counterx is 6 | port (clk: in std_logic; 7 | rst: in std_logic; 8 | count: out std_logic_vector(2 downto 0) 9 | ); 10 | end; 11 | 12 | architecture main of counterx is 13 | signal cnt: unsigned(2 downto 0); 14 | begin 15 | 16 | process (clk,rst) 17 | begin 18 | if rst = '0' then 19 | cnt <= (others => '0'); 20 | elsif rising_edge(clk) then 21 | cnt <= cnt + 1; 22 | end if; 23 | end process; 24 | 25 | count <= std_logic_vector(cnt); 26 | end; 27 | -------------------------------------------------------------------------------- /10_HDL/counter.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity counterx is 6 | port (clk: in std_logic; 7 | nrst: in std_logic; 8 | count: out std_logic_vector(2 downto 0) 9 | ); 10 | end; 11 | 12 | architecture main of counterx is 13 | signal cnt: unsigned(2 downto 0); 14 | begin 15 | 16 | process (clk,nrst) 17 | begin 18 | if rising_edge(clk) then 19 | if (nrst = '0') then 20 | cnt <= (others => '0'); 21 | else 22 | cnt <= cnt + 1; 23 | end if; 24 | end if; 25 | end process; 26 | 27 | count <= std_logic_vector(cnt); 28 | end; 29 | -------------------------------------------------------------------------------- /20_SYNTH/2N7002.lib: -------------------------------------------------------------------------------- 1 | *---------- 2N7002 Spice Model ---------- 2 | .SUBCKT NMOS_MOSFET 10 20 30 3 | * TERMINALS: D G S 4 | M1 1 2 3 3 NMOS L = 1E-006 W = 1E-006 5 | RD 10 1 0.976 6 | RS 30 3 0.001 7 | RG 20 2 160.6 8 | CGS 2 3 2E-011 9 | EGD 12 0 2 1 1 10 | VFB 14 0 0 11 | FFB 2 1 VFB 1 12 | CGD 13 14 5.9E-011 13 | R1 13 0 1 14 | D1 12 13 DLIM 15 | DDG 15 14 DCGD 16 | R2 12 15 1 17 | D2 15 0 DLIM 18 | DSD 3 10 DSUB 19 | .MODEL NMOS NMOS LEVEL = 3 VMAX = 1E+006 ETA = 0 VTO = 2.154 20 | + TOX = 6E-008 NSUB = 1E+016 KP = 0.4654 KAPPA = 1E-015 U0 = 400 21 | .MODEL DCGD D CJO = 1.2E-011 VJ = 0.6 M = 0.6 22 | .MODEL DSUB D IS = 6.808E-010 N = 1.576 RS = 0.1408 BV = 72 CJO = 8E-012 VJ = 0.8 M = 0.6474 23 | .MODEL DLIM D IS = 0.0001 24 | .ENDS 25 | *Diodes N7002 Spice Model v0 Last Revised 2017/2/9 26 | -------------------------------------------------------------------------------- /10_HDL/gtkviewsettings.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI 3 | [*] Mon Nov 01 13:05:35 2021 4 | [*] 5 | [dumpfile] "D:\VHDL\PCBFlow\01_HDL\waveforms.ghw" 6 | [dumpfile_mtime] "Mon Nov 01 13:04:22 2021" 7 | [dumpfile_size] 21477 8 | [savefile] "D:\VHDL\PCBFlow\01_HDL\gtkviewsettings.gtkw" 9 | [timestart] 0 10 | [size] 2048 1089 11 | [pos] -1 -1 12 | *-28.436033 132000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] top. 14 | [treeopen] top.testbench. 15 | [sst_width] 197 16 | [signals_width] 120 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 325 19 | @28 20 | top.testbench.clk 21 | top.testbench.rst 22 | @29 23 | #{top.testbench.count[2:0]} top.testbench.count[2] top.testbench.count[1] top.testbench.count[0] 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /20_SYNTH/DMG301.lib: -------------------------------------------------------------------------------- 1 | *---------- DMG301NU Spice Model ---------- 2 | .SUBCKT NMOS_MOSFET 10 20 30 3 | * TERMINALS: D G S 4 | M1 1 2 3 3 NMOS L = 1E-006 W = 1E-006 5 | RD 10 1 0.5296 6 | RS 30 3 0.08274 7 | RG 20 2 84 8 | CGS 2 3 2.421E-011 9 | EGD 12 0 2 1 1 10 | VFB 14 0 0 11 | FFB 2 1 VFB 1 12 | CGD 13 14 6.2E-011 13 | R1 13 0 1 14 | D1 12 13 DLIM 15 | DDG 15 14 DCGD 16 | R2 12 15 1 17 | D2 15 0 DLIM 18 | DSD 3 10 DSUB 19 | .MODEL NMOS NMOS LEVEL = 3 VMAX = 8E+005 ETA = 0.001 VTO = 0.9252 20 | + TOX = 6E-008 NSUB = 1E+016 KP = 1.517 U0 = 400 KAPPA = 4.441E-010 21 | .MODEL DCGD D CJO = 1.033E-011 VJ = 0.2003 M = 0.3 22 | .MODEL DSUB D IS = 1.714E-009 N = 1.454 RS = 0.03011 BV = 35 CJO = 1.259E-011 VJ = 0.6 M = 0.3013 23 | .MODEL DLIM D IS = 0.0001 24 | .ENDS 25 | 26 | *Diodes DMG301NU Spice Model v1.0 Last Revised 2015/6/4 -------------------------------------------------------------------------------- /20_SYNTH/amux.lib: -------------------------------------------------------------------------------- 1 | ** AMUX behavioral spice model (74LVC1G3157) 2 | ** LTSpice model: tim 2020 3 | ** Netslist adoption: Joan Iluch 4 | 5 | 6 | ***************** 7 | * Connections 8 | * 1 = B2 (NO) 9 | * 2 = GND 10 | * 3 = B1 (NC) 11 | * 4 = A 12 | * 5 = VCC 13 | * 6 = S 14 | ***************** 15 | 16 | .SUBCKT 74LVC1G3157 1 2 3 4 5 6 17 | X1 1 3 4 6 5 2 ANALOG_SPDT 18 | .ENDS 19 | 20 | 21 | ***************** 22 | * Connections 23 | * 1 = NO 24 | * 2 = NC 25 | * 3 = CO (Common) 26 | * 4 = SEL 27 | * 5 = VCC 28 | * 6 = GND 29 | ***************** 30 | 31 | .subckt ANALOG_SPDT 1 2 3 4 5 6 32 | R0 4 p0 1 33 | C0 p0 6 2.3p 34 | R1 2 p1 1 35 | C1 p1 3 16p 36 | R2 1 p2 1 37 | C2 p2 3 16p 38 | S1 p1 3 5 p0 switch 39 | S2 p2 3 p0 6 switch 40 | .model switch sw (vt=2.5 vh=0.2 ron=5 roff=1g) 41 | .ends ANALOG_SPDT 42 | -------------------------------------------------------------------------------- /20_SYNTH/spice_testbench.sp: -------------------------------------------------------------------------------- 1 | * Spice testbench for discrete logic counterx 2 | * Bases on Yosys "CMOS" example 3 | 4 | * supply voltages 5 | .global Vee Vcc 6 | Vee Vee 0 DC 0 7 | Vcc Vcc 0 DC 5 8 | 9 | * load design and library 10 | .include ../20_SYNTH/discrete_logic_spice_subckt.lib 11 | .include ../20_SYNTH/RTL_NPN.lib 12 | .include 209_synthesized_output.sp 13 | 14 | * Define base and load resistor 15 | .param RL=4.7k 16 | .param RB=4.7k 17 | 18 | * input signals 19 | 20 | Vclk clk 0 PULSE(0 5 10u 20n 20n 8u 20u) 21 | Vrst rst 0 PULSE(0 5 5u 20n 20n 29u 400u) 22 | 23 | 24 | * Note: No pull up needed on outputs since they are internally connected. B 25 | * Pull ups may have to be added for other designs 26 | 27 | Xuut clk rst out0 out1 out2 main 28 | 29 | .tran 20n 400u 30 | 31 | .control 32 | run 33 | plot v(clk)+5 v(rst) v(out0)+10 v(out1)+15 v(out2)+20 34 | .endc 35 | 36 | .end 37 | -------------------------------------------------------------------------------- /10_HDL/counter_tb.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity testbench is 6 | end; 7 | 8 | architecture testmain of testbench is 9 | 10 | component counterx is 11 | port (clk: in std_logic; 12 | nrst: in std_logic; 13 | count: out std_logic_vector(2 downto 0) 14 | ); 15 | end component; 16 | 17 | signal clk,nrst: std_logic; 18 | signal count: std_logic_vector(2 downto 0); 19 | 20 | begin 21 | 22 | ctr: counterx port map(clk => clk, nrst => nrst, count => count); 23 | 24 | process 25 | begin 26 | nrst <= '0'; 27 | clk <= '0'; 28 | WAIT FOR 50 ns; 29 | clk <= '1'; 30 | WAIT FOR 50 ns; 31 | nrst <= '1'; 32 | 33 | loop 34 | clk <= '0'; 35 | WAIT FOR 50 ns; 36 | clk <= '1'; 37 | WAIT FOR 50 ns; -- clock. 38 | end loop ; -- identifier 39 | 40 | assert false report "END of testbench reached"; 41 | 42 | end process; 43 | end; 44 | 45 | 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /20_SYNTH/flow_discrete_74LVC.ys: -------------------------------------------------------------------------------- 1 | # VHDL to Discrete RT-logic 2 | 3 | 4 | # elaborate VHDL code from GHDL 5 | ghdl 6 | hierarchy -check 7 | 8 | flatten 9 | 10 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 11 | rename -top main 12 | 13 | # Draw netlist of elaborated design 14 | show -format pdf -prefix 200_diagramm_hdl_elaborated 15 | 16 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 17 | tribuf 18 | 19 | # Technology mapping 20 | techmap 21 | 22 | proc; opt; fsm; opt; 23 | dfflibmap -liberty ../20_SYNTH/discrete_74LVC_logic_liberty.lib 24 | abc -liberty ../20_SYNTH/discrete_74LVC_logic_liberty.lib 25 | opt_clean -purge 26 | 27 | # Print Statistics 28 | stat -liberty ../20_SYNTH/discrete_74LVC_logic_liberty.lib 29 | 30 | # Draw netlist of optimized and mapped design 31 | show -format pdf -prefix 208_diagramm_after_mapping 32 | 33 | # Write out in spice format 34 | write_spice 209_synthesized_output.sp 35 | write_json 210_synthesized_output.json 36 | 37 | 38 | 39 | -------------------------------------------------------------------------------- /10_HDL/moregates.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity gatesx is 6 | port (inv_a: in std_logic; 7 | inv_y: out std_logic; 8 | 9 | xor_a: in std_logic; 10 | xor_b: in std_logic; 11 | xor_y: out std_logic; 12 | 13 | and_a: in std_logic; 14 | and_b: in std_logic; 15 | and_y: out std_logic; 16 | 17 | d,clk: in std_logic; 18 | q: out std_logic; 19 | 20 | ld,en: in std_logic; 21 | lq: out std_logic 22 | ); 23 | end; 24 | 25 | architecture main of gatesx is 26 | signal reg: std_logic; 27 | signal latch: std_logic; 28 | begin 29 | process (clk) 30 | begin 31 | if rising_edge(clk) then 32 | reg <= d; 33 | end if; 34 | end process; 35 | 36 | q <= reg; 37 | 38 | process(en,ld) 39 | begin 40 | if (en ='1') then 41 | latch <= ld; 42 | end if; 43 | end process; 44 | 45 | lq <= latch; 46 | 47 | and_y <= and_a AND and_b; 48 | xor_y <= xor_a XOR xor_b; 49 | inv_y <= NOT inv_a; 50 | end; 51 | -------------------------------------------------------------------------------- /20_SYNTH/flow_discrete_nmos.ys: -------------------------------------------------------------------------------- 1 | # VHDL to Discrete nmos-logic 2 | 3 | # elaborate VHDL code from GHDL 4 | ghdl 5 | hierarchy -check 6 | 7 | flatten 8 | 9 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 10 | rename -top main 11 | 12 | # Read verilog description of cells 13 | read_verilog -lib ../20_SYNTH/discrete_nmos_logic_cells.v 14 | 15 | # Draw netlist of elaborated design 16 | show -format pdf -prefix 200_diagramm_hdl_elaborated 17 | 18 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 19 | tribuf 20 | 21 | # Technology mapping 22 | techmap 23 | 24 | proc; opt; fsm; opt; 25 | dfflibmap -liberty ../20_SYNTH/discrete_nmos_logic_liberty.lib 26 | proc; opt; 27 | abc -liberty ../20_SYNTH/discrete_nmos_logic_liberty.lib 28 | opt_clean -purge 29 | 30 | # Print Statistics 31 | stat -liberty ../20_SYNTH/discrete_nmos_logic_liberty.lib 32 | 33 | # Draw netlist of optimized and mapped design 34 | show -format pdf -prefix 201_diagramm_after_mapping 35 | 36 | # Write out in spice format 37 | write_spice 209_synthesized_output.sp 38 | write_json 210_synthesized_output.json 39 | 40 | 41 | -------------------------------------------------------------------------------- /20_SYNTH/flow_discrete_LTL.ys: -------------------------------------------------------------------------------- 1 | # VHDL to Discrete LED-Transistor-Logic 2 | 3 | # elaborate VHDL code from GHDL 4 | ghdl 5 | hierarchy -check 6 | 7 | flatten 8 | 9 | # Read verilog description of cells 10 | read_verilog -lib ../20_SYNTH/discrete_LTL_logic_cells.v 11 | 12 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 13 | rename -top main 14 | 15 | # Draw netlist of elaborated design 16 | show -format pdf -prefix 200_diagramm_hdl_elaborated 17 | 18 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 19 | tribuf 20 | 21 | # Technology mapping 22 | techmap 23 | 24 | proc; opt; fsm; opt; 25 | dfflibmap -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 26 | proc; opt; 27 | abc -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 28 | opt_clean -purge 29 | 30 | # Print Statistics 31 | stat -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 32 | 33 | # Draw netlist of optimized and mapped design 34 | show -format pdf -prefix 201_diagramm_after_mapping 35 | 36 | 37 | # Write out in spice format 38 | write_spice 209_synthesized_output.sp 39 | write_json 210_synthesized_output.json 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_amux_logic_spice_subckt.lib: -------------------------------------------------------------------------------- 1 | * Spice library implementing logic gates in analog multiplexer logic 2 | * 2021-Nov-09 cpldcpu 3 | 4 | * Supported gate types: 5 | * BUF 6 | * NOT 7 | * AND2 8 | * OR2 9 | * XOR2 10 | * DLATCH 11 | * DFF 12 | 13 | * Global nodes: 14 | * VCC positive supply 15 | * VEE negative supply 16 | 17 | ***************** 18 | * 74LVC1G3157 Connections 19 | * 1 = B2 (NO) 20 | * 2 = GND 21 | * 3 = B1 (NC) 22 | * 4 = A 23 | * 5 = VCC 24 | * 6 = S 25 | ***************** 26 | 27 | .SUBCKT am_NOT A Y 28 | X1 VEE VEE VCC Y VCC A 74LVC1G3157 29 | .ENDS 30 | 31 | .SUBCKT am_AND2 A B Y 32 | X1 B VEE VEE Y VCC A 74LVC1G3157 33 | .ENDS 34 | 35 | .SUBCKT am_OR2 A B Y 36 | X1 VCC VEE B Y VCC A 74LVC1G3157 37 | .ENDS 38 | 39 | .SUBCKT am_XOR2 A B Y 40 | X1 N001 VEE B Y VCC A 74LVC1G3157 41 | X2 B N001 am_NOT 42 | .ENDS 43 | 44 | .SUBCKT am_MUX2 A B S Y 45 | X1 A VEE B Y VCC S 74LVC1G3157 46 | .ENDS 47 | 48 | .SUBCKT am_LATCH E D Q 49 | X1 D VEE Q N001 VCC E 74LVC1G3157 50 | X2 VCC VEE GND Q VCC N001 74LVC1G3157 51 | .ENDS 52 | 53 | .SUBCKT am_DFF C D Q 54 | X1 nC D t am_LATCH 55 | X2 C t Q am_LATCH 56 | X3 C nC am_NOT 57 | .ENDS 58 | -------------------------------------------------------------------------------- /20_SYNTH/flow_discrete_RTPG.ys: -------------------------------------------------------------------------------- 1 | # VHDL to Discrete RT+Pass gate-logic 2 | 3 | 4 | # elaborate VHDL code from GHDL 5 | ghdl 6 | hierarchy -check 7 | 8 | flatten 9 | 10 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 11 | rename -top main 12 | 13 | # Read verilog description of cells 14 | read_verilog -lib ../20_SYNTH/discrete_RTPG_logic_cells.v 15 | 16 | # Draw netlist of elaborated design 17 | show -format pdf -prefix 200_diagramm_hdl_elaborated 18 | 19 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 20 | tribuf 21 | 22 | # Technology mapping 23 | techmap 24 | 25 | proc; opt; 26 | 27 | techmap -map ../20_SYNTH/discrete_RTPG_techmap.v # map TBUF 28 | 29 | #proc; opt; fsm; opt; 30 | dfflibmap -liberty ../20_SYNTH/discrete_RTPG_logic_liberty.lib 31 | proc; opt; 32 | abc -liberty ../20_SYNTH/discrete_RTPG_logic_liberty.lib 33 | opt_clean -purge 34 | 35 | # Print Statistics 36 | stat -liberty ../20_SYNTH/discrete_RTPG_logic_liberty.lib 37 | 38 | # Draw netlist of optimized and mapped design 39 | show -format pdf -prefix 208_diagramm_after_mapping 40 | 41 | 42 | # Write out in spice format 43 | write_spice 209_synthesized_output.sp 44 | write_json 210_synthesized_output.json 45 | 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /20_SYNTH/flow_discrete_amux.ys: -------------------------------------------------------------------------------- 1 | # VHDL to Discrete RT-logic 2 | 3 | 4 | # elaborate VHDL code from GHDL 5 | ghdl 6 | hierarchy -check 7 | 8 | flatten 9 | 10 | # Read verilog description of cells 11 | read_verilog -lib ../20_SYNTH/discrete_amux_logic_cells.v 12 | 13 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 14 | rename -top main 15 | 16 | # Draw netlist of elaborated design 17 | show -format pdf -prefix 200_diagramm_hdl_elaborated 18 | 19 | # simulation 20 | # sim -vcd 207_simulation.vcd -clock clk -rstlen 10 -resetn nrst -n 100 main 21 | 22 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 23 | tribuf 24 | 25 | # Technology mapping 26 | techmap 27 | 28 | proc; opt; 29 | # proc; opt; fsm; opt; 30 | dfflibmap -liberty ../20_SYNTH/discrete_amux_logic_liberty.lib 31 | abc -liberty ../20_SYNTH/discrete_amux_logic_liberty.lib 32 | opt_clean -purge 33 | 34 | # Print Statistics 35 | stat -liberty ../20_SYNTH/discrete_amux_logic_liberty.lib 36 | 37 | # Draw netlist of optimized and mapped design 38 | show -format pdf -prefix 201_diagramm_after_mapping 39 | 40 | # Write out in spice format 41 | write_spice -inames 209_synthesized_output.sp 42 | write_json 210_synthesized_output.json 43 | 44 | 45 | 46 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_amux_logic_cells.v: -------------------------------------------------------------------------------- 1 | /* 2 | Verilog description of cell library to allow for proper port mapping 3 | 4 | Based on Yosys cmos example 5 | */ 6 | 7 | module am_BUF(A, Y); 8 | input A; 9 | output Y; 10 | assign Y = A; 11 | endmodule 12 | 13 | module am_NOT(A, Y); 14 | input A; 15 | output Y; 16 | assign Y = ~A; 17 | endmodule 18 | 19 | module am_NAND2(A, B, Y); 20 | input A, B; 21 | output Y; 22 | assign Y = ~(A & B); 23 | endmodule 24 | 25 | module am_AND2(A, B, Y); 26 | input A, B; 27 | output Y; 28 | assign Y = (A & B); 29 | endmodule 30 | 31 | module am_OR2(A, B, Y); 32 | input A, B; 33 | output Y; 34 | assign Y = (A | B); 35 | endmodule 36 | 37 | module am_ORN2(A, B, Y); 38 | input A, B; 39 | output Y; 40 | assign Y = (~A | B); 41 | endmodule 42 | 43 | 44 | module am_ANDN2(A, B, Y); 45 | input A, B; 46 | output Y; 47 | assign Y = (~A & B); 48 | endmodule 49 | 50 | 51 | module am_NOR2(A, B, Y); 52 | input A, B; 53 | output Y; 54 | assign Y = ~(A | B); 55 | endmodule 56 | 57 | module am_DFF(C, D, Q); 58 | input C, D; 59 | output reg Q; 60 | always @(posedge C) 61 | Q <= D; 62 | endmodule 63 | 64 | module am_MUX2(A, B, S, Y); 65 | input A, B , S; 66 | output Y; 67 | assign Y = (A & S) | (B & ~S); 68 | endmodule 69 | 70 | module am_XNOR2(A, B, Y); 71 | input A, B; 72 | output Y; 73 | assign Y = ~(A ^ B); 74 | endmodule 75 | -------------------------------------------------------------------------------- /10_HDL/dice_johnson.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | 6 | 7 | 8 | entity dice555johnson is 9 | port (clk: in std_logic; 10 | -- n_clk: in std_logic; 11 | nrst: in std_logic; 12 | dice: out std_logic_vector(3 downto 0) 13 | ); 14 | end; 15 | 16 | architecture main of dice555johnson is 17 | signal cnt: unsigned(2 downto 0); 18 | begin 19 | process (clk,nrst) 20 | begin 21 | -- sync reset implementation to allow using yosys internal digital simulation 22 | -- if rising_edge(clk) then 23 | -- if nrst = '0' then 24 | -- cnt <= "000"; 25 | -- else 26 | -- cnt <= cnt(1 downto 0) & NOT cnt(2); 27 | -- end if; 28 | -- end if; 29 | 30 | -- async reset for synthesis 31 | if nrst = '0' then 32 | cnt <= "000"; 33 | elsif rising_edge(clk) then 34 | cnt <= cnt(1 downto 0) & NOT cnt(2); 35 | end if; 36 | end process; 37 | 38 | -- 1 2 39 | -- 3 0 3 40 | -- 2 1 41 | 42 | -- Encoding: 43 | -- 011 0 44 | -- 000 1 45 | -- 001 0,1 46 | -- 110 1,2 47 | -- 111 0,1,2 48 | -- 100 1,2,3 49 | 50 | -- 101 invalid 51 | -- 010 invalid 52 | 53 | -- drive inverted LEDs 54 | dice(0) <= NOT cnt(0); 55 | dice(1) <= '1' when (cnt = "011") else '0'; 56 | dice(2) <= NOT cnt(2); 57 | dice(3) <= '0' when (cnt(2 downto 1) = "10") else '1'; 58 | 59 | end; 60 | -------------------------------------------------------------------------------- /20_SYNTH/cells_wokwi.v: -------------------------------------------------------------------------------- 1 | `define default_netname none 2 | 3 | module buffer_cell ( 4 | input wire in, 5 | output wire out 6 | ); 7 | assign out = in; 8 | endmodule 9 | 10 | module and_cell ( 11 | input wire a, 12 | input wire b, 13 | output wire out 14 | ); 15 | 16 | assign out = a & b; 17 | endmodule 18 | 19 | module or_cell ( 20 | input wire a, 21 | input wire b, 22 | output wire out 23 | ); 24 | 25 | assign out = a | b; 26 | endmodule 27 | 28 | module xor_cell ( 29 | input wire a, 30 | input wire b, 31 | output wire out 32 | ); 33 | 34 | assign out = a ^ b; 35 | endmodule 36 | 37 | module nand_cell ( 38 | input wire a, 39 | input wire b, 40 | output wire out 41 | ); 42 | 43 | assign out = !(a&b); 44 | endmodule 45 | 46 | module not_cell ( 47 | input wire in, 48 | output wire out 49 | ); 50 | 51 | assign out = !in; 52 | endmodule 53 | 54 | module mux_cell ( 55 | input wire a, 56 | input wire b, 57 | input wire sel, 58 | output wire out 59 | ); 60 | 61 | assign out = sel ? b : a; 62 | endmodule 63 | 64 | module dff_cell ( 65 | input wire clk, 66 | input wire d, 67 | output reg q, 68 | output wire notq 69 | ); 70 | 71 | always @(posedge clk) 72 | q <= d; 73 | 74 | assign notq = !q; 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 2-Clause License 2 | 3 | Copyright (c) 2021, Tim 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 20 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_RTPG_logic_cells.v: -------------------------------------------------------------------------------- 1 | /* 2 | Verilog description of cell library to allow for proper port mapping 3 | 4 | Based on Yosys cmos example 5 | */ 6 | 7 | module BUF(A, Y); 8 | input A; 9 | output Y; 10 | assign Y = A; 11 | endmodule 12 | 13 | module rtpg_NOT(A, Y); 14 | input A; 15 | output Y; 16 | assign Y = ~A; 17 | endmodule 18 | 19 | module rtpg_XOR2(A, B, Y); 20 | input A, B; 21 | output Y; 22 | assign Y = (A ^ B); 23 | endmodule 24 | 25 | module rtpg_NOR2(A, B, Y); 26 | input A, B; 27 | output Y; 28 | assign Y = ~(A | B); 29 | endmodule 30 | 31 | module rtpg_NOR3(A, B, C, Y); 32 | input A, B , C; 33 | output Y; 34 | assign Y = ~(A | B | C); 35 | endmodule 36 | 37 | module rtpg_NOR4(A, B, C, D, Y); 38 | input A, B , C, D; 39 | output Y; 40 | assign Y = ~(A | B | C | D); 41 | endmodule 42 | 43 | module rtpg_DFF7T(nC, D, Q); 44 | input nC, D; 45 | output reg Q; 46 | always @(negedge nC) 47 | Q <= D; 48 | endmodule 49 | 50 | module rtpg_DFF7T_PN(nC, D, Q, QN); 51 | input nC, D; 52 | output reg Q; 53 | output QN; 54 | 55 | always @(negedge cC) 56 | Q <= D; 57 | assign QN = ~Q; 58 | 59 | endmodule 60 | 61 | module rtpg_DFF7T_CLR(C, CD, D, Q, QN); 62 | input C, D, CD; 63 | output reg Q; 64 | output QN; 65 | always @(negedge C or negedge CD) 66 | begin 67 | if (CD == 1'b0) 68 | Q <= 1'b0; 69 | else 70 | Q <= D; 71 | end 72 | 73 | assign QN = ~Q; 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /30_PLACE/spice_testbench_extracted.sp: -------------------------------------------------------------------------------- 1 | * Spice testbench for discrete logic counterx 2 | * Bases on Yosys "CMOS" example 3 | 4 | * supply voltages 5 | .global Vee Vcc gnd 6 | Vee Vee 0 DC 0 7 | Vcc Vcc 0 DC 5 8 | 9 | * load design and library 10 | .include ../20_SYNTH/microcell_spice_subckt.lib 11 | .include ../20_SYNTH/2N7002.lib 12 | .include ../20_SYNTH/PMBT2369.lib 13 | * .include ../20_SYNTH/PMBT3904.lib 14 | .include ../20_SYNTH/LTL_LED.lib 15 | .include ../20_SYNTH/amux.lib 16 | .include 308_extracted_netlist.sp 17 | 18 | * Define base and load resistor 19 | * .param RL=3.3k 20 | * .param RB=3.3k 21 | *.param CB=68p 22 | 23 | .param RL=1.5k 24 | .param RB=3.3k 25 | .param CB=68p 26 | 27 | * input signals 28 | 29 | * Vrst rst 0 DC 0 30 | Vrst nrst 0 dc 0 PULSE(5 0 500n 5n 5n 6u 180u) 31 | * Vclk clk 0 dc 0 PULSE(5 2 1u 5n 5n 4u 8u) 32 | Vclk clk 0 dc 0 PULSE(0 5 4u 150n 150n 4u 8u) 33 | 34 | * Note: No pull up needed on outputs since they are internally connected. B 35 | * Pull ups may have to be added for other designs 36 | 37 | Xuut clk nrst out0 out1 out2 main 38 | * Xuut clk nrst out0 out1 out2 out3 main 39 | 40 | .tran 500p 100u 41 | * .measure tran maxv MAX out0 42 | * .measure tran out0tr TRIG out0 VAL=0.2*maxv RISE=1 TARG out0 VAL=0.8*maxv RISE=1 43 | 44 | .control 45 | run 46 | plot v(clk)+5 v(nrst) v(out0)+10 v(out1)+15 v(out2)+20 47 | * plot v(clk)+5 v(nrst) v(out0)+10 v(out1)+15 v(out2)+20 v(out3)+25 48 | .endc 49 | 50 | .end 51 | 52 | 53 | .end 54 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_RT_techmap.v: -------------------------------------------------------------------------------- 1 | 2 | module \$_SDFF_NP0_ (input D, input C, input R, output Q, output Qn); 3 | DFFXXX _TECHMAP_REPLACE_ ( 4 | .D(D), 5 | .C(C), 6 | .R(R), 7 | .Q(Q), 8 | .Qn(Qn), 9 | ); 10 | endmodule 11 | 12 | module \$_DLATCH_P_ (input E, input D, output Q); 13 | LATCH_N _TECHMAP_REPLACE_ ( 14 | .EN(!E), 15 | .D(D), 16 | .Q(Q) 17 | ); 18 | endmodule 19 | 20 | 21 | module \$_DLATCH_N_ (input E, input D, output Q); 22 | LATCH_N _TECHMAP_REPLACE_ ( 23 | .EN(E), 24 | .D(D), 25 | .Q(Q) 26 | ); 27 | endmodule 28 | 29 | module \$_TBUF_ (input A, input E, output Y); 30 | rt_TBUF_N _TECHMAP_REPLACE_ ( 31 | .A(A), 32 | .nE(!E), 33 | .Y(Y) 34 | ); 35 | endmodule 36 | 37 | // module \$add (A, B, Y); // Uncomment to use ripple adder 38 | module \$___add (A, B, Y); 39 | 40 | parameter A_SIGNED = 0; 41 | parameter B_SIGNED = 0; 42 | parameter A_WIDTH = 0; 43 | parameter B_WIDTH = 0; 44 | parameter Y_WIDTH = 0; 45 | 46 | input [A_WIDTH-1:0] A; 47 | input [B_WIDTH-1:0] B; 48 | output [Y_WIDTH-1:0] Y; 49 | wire [Y_WIDTH-1:0] CO; 50 | wire [Y_WIDTH-1:0] C = {CO, 1'b0}; 51 | wire [Y_WIDTH-1:0] HA; 52 | 53 | genvar i; 54 | generate for (i=0; i dice <= "0001"; 53 | -- when "010" => dice <= "0010"; 54 | -- when "011" => dice <= "0011"; 55 | -- when "100" => dice <= "0110"; 56 | -- when "101" => dice <= "0111"; 57 | -- when "110" => dice <= "1110"; 58 | -- when others => null; 59 | -- end case; 60 | -- end process; 61 | end; 62 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_LTL_logic_cells.v: -------------------------------------------------------------------------------- 1 | /* 2 | Verilog description of cell library to allow for proper port mapping 3 | 4 | Based on Yosys cmos example 5 | */ 6 | 7 | module ltl_BUF(A, Y); 8 | input A; 9 | output Y; 10 | assign Y = A; 11 | endmodule 12 | 13 | module ltl_NOT(A, Y); 14 | input A; 15 | output Y; 16 | assign Y = ~A; 17 | endmodule 18 | 19 | module ltl_NAND2(A, B, Y); 20 | input A, B; 21 | output Y; 22 | assign Y = ~(A & B); 23 | endmodule 24 | 25 | module ltl_NAND3(A, B, C,Y); 26 | input A, B, C; 27 | output Y; 28 | assign Y = ~(A & B & C); 29 | endmodule 30 | 31 | module ltl_AOI2_2(A, B, C, D, Y); 32 | input A, B, C, D; 33 | output Y; 34 | assign Y = ~((A & B) | (C & D)); 35 | endmodule 36 | 37 | module ltl_AOI1_2(A, B, C, Y); 38 | input A, B, C; 39 | output Y; 40 | assign Y = ~((A & B) | (B & C)); 41 | endmodule 42 | 43 | 44 | module ltl_NOR2(A, B, Y); 45 | input A, B; 46 | output Y; 47 | assign Y = ~(A | B); 48 | endmodule 49 | 50 | module ltl_NOR3(A, B, C, Y); 51 | input A, B , C; 52 | output Y; 53 | assign Y = ~(A | B | C); 54 | endmodule 55 | /* 56 | module ltl_DFF(C, D, Q); 57 | input C, D; 58 | output reg Q; 59 | always @(posedge C) 60 | Q <= D; 61 | endmodule 62 | */ 63 | 64 | module ltl_DFFNP(C, D, Q, QN); 65 | input C, D; 66 | output reg Q; 67 | output QN; 68 | always @(posedge C) 69 | Q <= D; 70 | 71 | assign QN = ~Q; 72 | 73 | endmodule 74 | 75 | module ltl_DFFNP_CLR(C, CD, D, Q, QN); 76 | input C, D, CD; 77 | output reg Q; 78 | output QN; 79 | always @(posedge C or negedge CD) 80 | begin 81 | if (CD == 1'b0) 82 | Q <= 1'b0; 83 | else 84 | Q <= D; 85 | end 86 | 87 | assign QN = ~Q; 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /20_SYNTH/flow_discrete_RT.ys: -------------------------------------------------------------------------------- 1 | # VHDL to Discrete RT-logic 2 | 3 | 4 | # elaborate VHDL code from GHDL 5 | ghdl 6 | hierarchy -check 7 | 8 | flatten 9 | 10 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 11 | rename -top main 12 | 13 | # Read verilog description of cells 14 | read_verilog -lib ../20_SYNTH/discrete_RT_logic_cells.v 15 | 16 | # Draw netlist of elaborated design 17 | show -format pdf -prefix 200_diagramm_hdl_elaborated 18 | 19 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 20 | tribuf 21 | 22 | # Technology mapping 23 | techmap -map ../20_SYNTH/discrete_RT_techmap.v # map add 24 | techmap 25 | techmap -map ../20_SYNTH/discrete_RT_techmap.v # map TBUF 26 | 27 | 28 | stat 29 | # Work around to map DFF with sync set/reset, since this is not possible in liberty file 30 | # proc; opt; 31 | # dfflegalize -cell $_SDFF_NP0_ x 32 | # techmap -map ../20_SYNTH/discrete_RT_techmap.v # map TBUF 33 | 34 | proc; opt; fsm; opt; 35 | dfflibmap -liberty ../20_SYNTH/discrete_RT_logic_liberty.lib 36 | proc; opt; 37 | #abc -liberty ../20_SYNTH/discrete_RT_logic_liberty.lib -constr ../20_SYNTH/discrete_RT.constr # -script +strash;dretime;map,{D};buffer 38 | abc -liberty ../20_SYNTH/discrete_RT_logic_liberty.lib 39 | 40 | opt_clean -purge 41 | 42 | # Print Statistics 43 | stat -liberty ../20_SYNTH/discrete_RT_logic_liberty.lib 44 | 45 | # Draw netlist of optimized and mapped design 46 | show -format pdf -prefix 208_diagramm_after_mapping 47 | 48 | 49 | # Write out in spice format 50 | write_spice 209_synthesized_output.sp 51 | write_json 210_synthesized_output.json 52 | 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /20_SYNTH/flow_v_discrete_LTL.ys: -------------------------------------------------------------------------------- 1 | # Verilog to Discrete LED-Transistor-Logic 2 | 3 | # read design source 4 | read_verilog design.v 5 | hierarchy -check 6 | flatten 7 | 8 | # Read verilog description of cells 9 | read_verilog -lib ../20_SYNTH/discrete_LTL_logic_cells.v 10 | 11 | #Wokwi cells library 12 | #read_verilog ../20_SYNTH/cells_wokwi.v 13 | 14 | #Synth is required here to properly map the DFF 15 | synth 16 | 17 | # read design source 18 | # read_verilog design.v 19 | 20 | # flatten, prep 21 | # prep -flatten -auto-top 22 | 23 | # Rename top entity to 'main'. This is important, otherwise other parts of the flow may break. 24 | rename -top main 25 | 26 | # Draw netlist of elaborated design 27 | show -format pdf -prefix 200_diagramm_hdl_elaborated 28 | 29 | dfflibmap -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 30 | 31 | #stat 32 | 33 | # Insert tristate buffers (ATTENTION: Currently not a supported cell type during P&R) 34 | # tribuf 35 | 36 | # Technology mapping 37 | techmap 38 | 39 | proc; opt; fsm; opt; 40 | #dfflibmap -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 41 | proc; opt; 42 | abc -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 43 | opt -purge 44 | opt_clean -purge 45 | # hierarchy -purge_lib 46 | 47 | # Print Statistics 48 | stat -liberty ../20_SYNTH/discrete_LTL_logic_liberty.lib 49 | 50 | # Draw netlist of optimized and mapped design 51 | show -format pdf -prefix 201_diagramm_after_mapping 52 | 53 | # Remove top attribute from main module, so a proper spice subckt is generated 54 | setattr -mod -unset top main 55 | 56 | # Write out in spice format 57 | write_spice 209_synthesized_output.sp 58 | write_json 210_synthesized_output.json 59 | 60 | 61 | 62 | -------------------------------------------------------------------------------- /run_22_Synthesis_Verilog.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Run Synthesis from VHDL to Discrete Logic 3 | # Invokes GHDL, Yosys and ABC (via Yosys) 4 | # 5 | 6 | # --->>>> Requires name of HDL source file as argument <<<<--- 7 | 8 | # set HDLCODE = "counter.vhd" # Name of source file from "10_HDL" 9 | 10 | if [ "$1" == "" ]; then 11 | echo "Usage: run_20_Synthesis.sh design [technology] " 12 | echo " 'design' is the ID of your Wokwi project." 13 | echo " 'technology' selects technology (optional)" 14 | echo "" 15 | echo "Technologies:" 16 | echo " RT Bipolar Resistor Transistor Logic (default)" 17 | echo " RTPG Bipolar Resistor Transistor Logic with pass gates" 18 | echo " nmos nmos transistor logic" 19 | echo " amux analog multiplexer logic" 20 | echo " 74LVC 74LVC single gate logic" 21 | echo " YG YG strip logic" 22 | echo " LTL LED Transistor Logic" 23 | exit 1 24 | else 25 | FILE="$1" 26 | fi 27 | 28 | 29 | if [ "$2" == "" ]; then 30 | APP="RT" 31 | else 32 | APP="$2" 33 | fi 34 | 35 | if [ "$APP" == "RT" ]; then 36 | echo "Synthesizing to bipolar resistor transistor logic" 37 | elif [ "$APP" == "RTPG" ]; then 38 | echo "Synthesizing to bipolar resistor transistor/pass gate logic" 39 | elif [ "$APP" == "nmos" ]; then 40 | echo "Synthesizing to nmos transistor logic" 41 | elif [ "$APP" == "amux" ]; then 42 | echo "Synthesizing to analog multiplexer logic" 43 | elif [ "$APP" == "74LVC" ]; then 44 | echo "Synthesizing to single gate TTL logic (74LVC)" 45 | elif [ "$APP" == "LTL" ]; then 46 | echo "Synthesizing to LED²-Transistor-Logic" 47 | else 48 | echo "Unknown logic style :$APP" 49 | exit 1 50 | fi 51 | 52 | 53 | cd Work 54 | 55 | cp ../10_HDL/$FILE.v design.v 56 | 57 | yosys ../20_SYNTH/flow_v_discrete_$APP.ys >208_log_yosys.txt 58 | 59 | grep -i 'Chip area' -A 4 -B 16 208_log_yosys.txt 60 | cd .. 61 | 62 | 63 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_nmos_logic_cells.v: -------------------------------------------------------------------------------- 1 | /* 2 | Verilog description of cell library to allow for proper port mapping 3 | 4 | Based on Yosys cmos example 5 | */ 6 | 7 | module nm_BUF(A, Y); 8 | input A; 9 | output Y; 10 | assign Y = A; 11 | endmodule 12 | 13 | module nm_NOT(A, Y); 14 | input A; 15 | output Y; 16 | assign Y = ~A; 17 | endmodule 18 | 19 | module nm_NAND2(A, B, Y); 20 | input A, B; 21 | output Y; 22 | assign Y = ~(A & B); 23 | endmodule 24 | 25 | module nm_NAND3(A, B, C,Y); 26 | input A, B, C; 27 | output Y; 28 | assign Y = ~(A & B & C); 29 | endmodule 30 | 31 | module nm_AOI2_2(A, B, C, D, Y); 32 | input A, B, C, D; 33 | output Y; 34 | assign Y = ~((A & B) | (C & D)); 35 | endmodule 36 | 37 | module nm_AOI1_2(A, B, C, Y); 38 | input A, B, C; 39 | output Y; 40 | assign Y = ~((A & B) | (B & C)); 41 | endmodule 42 | 43 | 44 | module nm_NOR2(A, B, Y); 45 | input A, B; 46 | output Y; 47 | assign Y = ~(A | B); 48 | endmodule 49 | 50 | module nm_NOR3(A, B, C, Y); 51 | input A, B , C; 52 | output Y; 53 | assign Y = ~(A | B | C); 54 | endmodule 55 | 56 | module nm_DFF(C, D, Q); 57 | input C, D; 58 | output reg Q; 59 | always @(posedge C) 60 | Q <= D; 61 | endmodule 62 | 63 | module hy_XOR2(A, B, Y); 64 | input A, B; 65 | output Y; 66 | assign Y = (A ^ B); 67 | endmodule 68 | 69 | 70 | module hy_DFF7T(C, D, Q); 71 | input C, D; 72 | output reg Q; 73 | always @(posedge C) 74 | Q <= D; 75 | endmodule 76 | 77 | 78 | module nm_DFFNP(C, D, Q, QN); 79 | input C, D; 80 | output reg Q; 81 | output QN; 82 | always @(posedge C) 83 | Q <= D; 84 | 85 | assign QN = ~Q; 86 | 87 | endmodule 88 | 89 | module nm_DFFNP_CLR(C, CD, D, Q, QN); 90 | input C, D, CD; 91 | output reg Q; 92 | output QN; 93 | always @(posedge C or negedge CD) 94 | begin 95 | if (CD == 1'b0) 96 | Q <= 1'b0; 97 | else 98 | Q <= D; 99 | end 100 | 101 | assign QN = ~Q; 102 | 103 | endmodule 104 | 105 | -------------------------------------------------------------------------------- /run_25_Synthesis_Wokwi.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Run Synthesis from VHDL to Discrete Logic 3 | # Invokes GHDL, Yosys and ABC (via Yosys) 4 | # 5 | 6 | # --->>>> Requires name of HDL source file as argument <<<<--- 7 | 8 | # set HDLCODE = "counter.vhd" # Name of source file from "10_HDL" 9 | 10 | if [ "$1" == "" ]; then 11 | echo "Usage: run_20_Synthesis.sh design [technology] " 12 | echo " 'design' is the ID of your Wokwi project." 13 | echo " 'technology' selects technology (optional)" 14 | echo "" 15 | echo "Technologies:" 16 | echo " RT Bipolar Resistor Transistor Logic (default)" 17 | echo " RTPG Bipolar Resistor Transistor Logic with pass gates" 18 | echo " nmos nmos transistor logic" 19 | echo " amux analog multiplexer logic" 20 | echo " 74LVC 74LVC single gate logic" 21 | echo " YG YG strip logic" 22 | echo " LTL LED Transistor Logic" 23 | exit 1 24 | else 25 | FILE="$1" 26 | fi 27 | 28 | 29 | if [ "$2" == "" ]; then 30 | APP="RT" 31 | else 32 | APP="$2" 33 | fi 34 | 35 | if [ "$APP" == "RT" ]; then 36 | echo "Synthesizing to bipolar resistor transistor logic" 37 | elif [ "$APP" == "RTPG" ]; then 38 | echo "Synthesizing to bipolar resistor transistor/pass gate logic" 39 | elif [ "$APP" == "nmos" ]; then 40 | echo "Synthesizing to nmos transistor logic" 41 | elif [ "$APP" == "amux" ]; then 42 | echo "Synthesizing to analog multiplexer logic" 43 | elif [ "$APP" == "74LVC" ]; then 44 | echo "Synthesizing to single gate TTL logic (74LVC)" 45 | elif [ "$APP" == "LTL" ]; then 46 | echo "Synthesizing to LED²-Transistor-Logic" 47 | else 48 | echo "Unknown logic style :$APP" 49 | exit 1 50 | fi 51 | 52 | 53 | cd Work 54 | 55 | echo "Fetching verilog from Wokwi" 56 | curl https://wokwi.com/api/projects/$FILE/verilog >design.v 57 | 58 | yosys ../20_SYNTH/flow_v_discrete_$APP.ys >208_log_yosys.txt 59 | 60 | grep -i 'Chip area' -A 4 -B 16 208_log_yosys.txt 61 | cd .. 62 | 63 | 64 | -------------------------------------------------------------------------------- /20_SYNTH/RTL_NPN.lib: -------------------------------------------------------------------------------- 1 | 2 | * This is the transistor model used to simulate RTL gates 3 | * It can be changed to implement different transistor types without having to edit all subckt files. 4 | 5 | *********************************************************** 6 | * 7 | * PMBT3904 8 | * 9 | * Nexperia 10 | * 11 | * NPN switching Transistor 12 | * IC = 200 mA 13 | * VCEO = 40 V 14 | * hFE = 100 - 300 @ 1V/10mA 15 | * 16 | * 17 | * 18 | * 19 | * Package pinning does not match Spice model pinning. 20 | * Package: SOT 23 21 | * 22 | * Package Pin 1: Base 23 | * Package Pin 2: Emitter 24 | * Package Pin 3: Collector 25 | * 26 | * 27 | * Extraction date (week/year): 25/2014 28 | * Spicemodel includes temperature dependency 29 | * 30 | ********************************************************** 31 | 32 | * .MODEL RTL_NPN npn(IS=1.11089e-14 BF=320.82 NF=0.980954 VAF=13.7591 IKF=0.0454909 ISE=1e-16 NE=1.17033 BR=4.34852 NR=1.0038 VAR=99.7542 IKR=0.156455 ISC=9.81183e-14 NC=2.87399 RB=0.1 IRB=0.2 RBM=0.1 RE=1.81526 RC=0.001 XTB=1.73971 XTI=1 EG=1.206 CJE=7.02461e-12 VJE=0.74856 MJE=0.331575 TF=1e-09 XTF=1 VTF=10 ITF=0.01 CJC=4.71202e-12 VJC=0.95 MJC=0.401177 XCJC=0.9 FC=0.5) 33 | 34 | 35 | .MODEL RTL_DIODE D 36 | + IS = 1.82E-013 37 | + N = 1.042 38 | + BV = 1000 39 | + IBV = 0.001 40 | + RS = 380.9 41 | + CJO = 0 42 | + VJ = 1 43 | + M = 0.5 44 | + FC = 0 45 | + TT = 0 46 | + EG = 1.11 47 | + XTI = 3 48 | 49 | .MODEL RTL_NPN NPN 50 | + IS = 2.612E-015 51 | + NF = 1.005 52 | + ISE = 2.958E-015 53 | + NE = 1.533 54 | + BF = 169 55 | + IKF = 0.08351 56 | + VAF = 53.92 57 | + NR = 0.9982 58 | + ISC = 3.177E-016 59 | + NC = 1.094 60 | + BR = 2.107 61 | + IKR = 0.5 62 | + VAR = 100 63 | + RB = 114 64 | + IRB = 0.001 65 | + RBM = 6.2 66 | + RE = 0.04181 67 | + RC = 0.9576 68 | + XTB = 1.522 69 | + EG = 1.11 70 | + XTI = 4.633 71 | + CJE = 1.032E-011 72 | + VJE = 0.6333 73 | + MJE = 0.2056 74 | + TF = 3.55E-010 75 | + XTF = 10 76 | + VTF = 2 77 | + ITF = 0.3 78 | + PTF = 0 79 | + CJC = 3.181E-012 80 | + VJC = 0.8831 81 | + MJC = 0.3242 82 | + XCJC = 1 83 | + TR = 0.7E-007 84 | + CJS = 0 85 | + VJS = 0.75 86 | + MJS = 0.333 87 | + FC = 0.78 -------------------------------------------------------------------------------- /30_PLACE/spice_testbench_mcpu_extracted.sp: -------------------------------------------------------------------------------- 1 | * Spice testbench for mcpu 2 | 3 | * supply voltages 4 | .global Vee Vcc gnd 5 | Vee Vee 0 DC 0 6 | Vcc Vcc 0 DC 5 7 | 8 | * load design and library 9 | .include ../20_SYNTH/microcell_spice_subckt.lib 10 | .include ../20_SYNTH/2N7002.lib 11 | * .include ../20_SYNTH/PMBT2369.lib 12 | .include ../20_SYNTH/PMBT3904.lib 13 | .include ../20_SYNTH/LTL_LED.lib 14 | .include ../20_SYNTH/amux.lib 15 | .include 308_extracted_netlist.sp 16 | 17 | * Define base and load resistor 18 | * .param RL=3.3k 19 | * .param RB=3.3k 20 | *.param CB=68p 21 | 22 | .param RL=4.7k 23 | .param RB=4.7k 24 | .param CB=68p 25 | 26 | * input signals 27 | 28 | * Vrst rst 0 DC 0 29 | Vrst rst 0 dc 0 PULSE(5 0 500n 5n 5n 6u 180u) 30 | * Vclk clk 0 dc 0 PULSE(5 2 1u 5n 5n 4u 8u) 31 | Vclk clk 0 dc 0 PULSE(0 5 4u 150n 150n 4u 8u) 32 | 33 | *Vdat6 data.6 0 dc 0 34 | Vdat7 data.7 0 dc 0 35 | * Note: No pull up needed on outputs since they are internally connected. B 36 | * Pull ups may have to be added for other designs 37 | 38 | RPwe Vcc we {RL} 39 | RPoe Vcc oe {RL} 40 | 41 | Xuut rst clk data.0 data.1 data.2 data.3 data.4 data.5 data.6 data.7 adress.0 adress.1 adress.2 adress.3 adress.4 adress.5 oe we main 42 | *Xuut clk nrst out0 out1 out2 main 43 | * Xuut clk nrst out0 out1 out2 out3 main 44 | 45 | .tran 500p 50u 46 | * .measure tran maxv MAX out0 47 | * .measure tran out0tr TRIG out0 VAL=0.2*maxv RISE=1 TARG out0 VAL=0.8*maxv RISE=1 48 | 49 | .control 50 | run 51 | plot v(clk)+5 v(rst) v(adress.0)+10 v(adress.1)+15 v(adress.2)+20 v(adress.3)+25 v(adress.4)+30 v(adress.5)+35 52 | plot v(clk)+5 v(rst) v(data.0)+10 v(data.1)+15 v(data.2)+20 v(data.3)+25 v(data.4)+30 v(data.5)+35 v(data.6)+40 v(data.7)+45 53 | plot v(clk)+5 v(rst) v(Xuut._33.A.0)+10 v(Xuut._33.A.1)+15 v(Xuut._33.A.2)+20 v(Xuut._33.A.3)+25 v(Xuut._33.A.4)+30 v(Xuut._33.A.5)+35 v(Xuut._33.A.6)+40 v(Xuut._33.A.7)+45 54 | plot v(clk)+5 v(rst) v(oe)+10 v(we)+15 55 | plot i(vee) 56 | *plot v(clk)+5 v(nrst) v(out0)+10 v(out1)+15 v(out2)+20 57 | * plot v(clk)+5 v(nrst) v(out0)+10 v(out1)+15 v(out2)+20 v(out3)+25 58 | .endc 59 | 60 | .end 61 | 62 | 63 | .end 64 | -------------------------------------------------------------------------------- /run_20_Synthesis.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # Run Synthesis from VHDL to Discrete Logic 3 | # Invokes GHDL, Yosys and ABC (via Yosys) 4 | # 5 | 6 | # --->>>> Requires name of HDL source file as argument <<<<--- 7 | 8 | # set HDLCODE = "counter.vhd" # Name of source file from "10_HDL" 9 | 10 | if [ "$1" == "" ]; then 11 | echo "Usage: run_20_Synthesis.sh design [technology] " 12 | echo " 'design' is the name of your VHDL sourcecode without extension." 13 | echo " 'technology' selects technology (optional)" 14 | echo "" 15 | echo "Technologies:" 16 | echo " RT Bipolar Resistor Transistor Logic (default)" 17 | echo " RTPG Bipolar Resistor Transistor Logic with pass gates" 18 | echo " nmos nmos transistor logic" 19 | echo " amux analog multiplexer logic" 20 | echo " 74LVC 74LVC single gate logic" 21 | echo " YG YG strip logic" 22 | echo " LTL LED Transistor Logic" 23 | exit 1 24 | else 25 | FILE="$1" 26 | fi 27 | 28 | 29 | if [ "$2" == "" ]; then 30 | APP="RT" 31 | else 32 | APP="$2" 33 | fi 34 | 35 | if [ "$APP" == "RT" ]; then 36 | echo "Synthesizing to bipolar resistor transistor logic" 37 | elif [ "$APP" == "RTPG" ]; then 38 | echo "Synthesizing to bipolar resistor transistor/pass gate logic" 39 | elif [ "$APP" == "nmos" ]; then 40 | echo "Synthesizing to nmos transistor logic" 41 | elif [ "$APP" == "amux" ]; then 42 | echo "Synthesizing to analog multiplexer logic" 43 | elif [ "$APP" == "74LVC" ]; then 44 | echo "Synthesizing to single gate TTL logic (74LVC)" 45 | elif [ "$APP" == "LTL" ]; then 46 | echo "Synthesizing to LED²-Transistor-Logic" 47 | else 48 | echo "Unknown logic style :$APP" 49 | exit 1 50 | fi 51 | 52 | 53 | cd Work 54 | ghdl -a --std=02 ../10_HDL/$FILE.vhd 55 | 56 | if [ "$(yosys -H | grep ghdl)" == "" ]; then 57 | echo "Invoking Yosys with external GHDL plugin" 58 | yosys -m ghdl ../20_SYNTH/flow_discrete_$APP.ys >208_log_yosys.txt 59 | else 60 | echo "Yosys has GHDL integrated" 61 | yosys ../20_SYNTH/flow_discrete_$APP.ys >208_log_yosys.txt 62 | fi 63 | 64 | grep -i 'Printing' -A 28 208_log_yosys.txt 65 | cd .. 66 | 67 | 68 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_74LVC_logic_liberty.lib: -------------------------------------------------------------------------------- 1 | /* 2 | Basic logic cells for a logic family based on 74LVC1G57 and 74LVC1G175 3 | 4 | */ 5 | 6 | 7 | library(SingleLogicCells) { 8 | 9 | cell(BUF) { 10 | area: 1000; 11 | pin(A) { direction: input; } 12 | pin(Y) { direction: output; 13 | function: "A"; } 14 | } 15 | 16 | cell(lvc_NOT) { 17 | area: 1; 18 | pin(A) { direction: input; } 19 | pin(Y) { direction: output; 20 | function: "A'"; } 21 | } 22 | 23 | cell(lvc_NOR2) { 24 | area: 1; 25 | pin(A) { direction: input; } 26 | pin(B) { direction: input; } 27 | pin(Y) { direction: output; 28 | function: "(A+B)'"; } 29 | } 30 | 31 | cell(lvc_AND2) { 32 | area: 1; 33 | pin(A) { direction: input; } 34 | pin(B) { direction: input; } 35 | pin(Y) { direction: output; 36 | function: "(A*B)"; } 37 | } 38 | 39 | cell(lvc_SZ57) { 40 | area: 1; 41 | pin(A) { direction: input; } 42 | pin(B) { direction: input; } 43 | pin(C) { direction: input; } 44 | pin(Y) { direction: output; 45 | function: "((A'*C')+(B*C))"; } 46 | } 47 | 48 | cell(lvc_NNAND2) { 49 | area: 1; 50 | pin(A) { direction: input; } 51 | pin(B) { direction: input; } 52 | pin(Y) { direction: output; 53 | function: "(A'*B)'"; } 54 | } 55 | 56 | cell(lvc_XNOR2) { 57 | area: 1; 58 | pin(A) { direction: input; } 59 | pin(B) { direction: input; } 60 | pin(Y) { direction: output; 61 | function: "(A^B)'"; } 62 | } 63 | 64 | cell(lvc_DFF) { 65 | area: 1; 66 | ff(IQ, IQN) { clocked_on: C; 67 | next_state: D; } 68 | pin(C) { direction: input; 69 | clock: true; } 70 | pin(D) { direction: input; } 71 | pin(Q) { direction: output; 72 | function: "IQ"; } 73 | } 74 | 75 | cell(lvc_DFF_clear) { 76 | area: 1; 77 | ff(IQ, IQN) { clocked_on: C; 78 | next_state: D; 79 | clear: "CD'";} 80 | pin(C) { direction: input; 81 | clock: true; } 82 | pin(D) { direction: input; } 83 | pin(CD) { direction: input; } 84 | pin(Q) { direction: output; 85 | function: "IQ"; } 86 | } 87 | 88 | } 89 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_RTPG_logic_liberty.lib: -------------------------------------------------------------------------------- 1 | /* 2 | Basic logic cells for a logic family based on discrete NPN transistors (Resistor Transistor Logic) 3 | BUF 4 | 5 | Logic gates: 6 | NOT 7 | NOR2 8 | NOR3 9 | 10 | D-Flop: 11 | DFF 12 | */ 13 | 14 | 15 | library(SingleLogicCells) { 16 | 17 | cell(BUF) { 18 | area: 6; 19 | pin(A) { direction: input; } 20 | pin(Y) { direction: output; 21 | function: "A"; } 22 | } 23 | 24 | cell(TBUF) { 25 | area: 1; 26 | pin(A) { direction: input; } 27 | pin(E) { direction: input; } 28 | pin(Y) { direction: output; 29 | function : "A"; 30 | three_state : "E"; } 31 | } 32 | 33 | cell(rtpg_NOT) { 34 | area: 1; 35 | pin(A) { direction: input; } 36 | pin(Y) { direction: output; 37 | function: "A'"; } 38 | } 39 | 40 | cell(rtpg_NOR2) { 41 | area: 2; 42 | pin(A) { direction: input; } 43 | pin(B) { direction: input; } 44 | pin(Y) { direction: output; 45 | function: "(A+B)'"; } 46 | } 47 | 48 | cell(rtpg_NOR3) { 49 | area: 3; 50 | pin(A) { direction: input; } 51 | pin(B) { direction: input; } 52 | pin(C) { direction: input; } 53 | pin(Y) { direction: output; 54 | function: "(A+B+C)'"; } 55 | } 56 | 57 | cell(rtpg_NOR4) { 58 | area: 4; 59 | pin(A) { direction: input; } 60 | pin(B) { direction: input; } 61 | pin(C) { direction: input; } 62 | pin(D) { direction: input; } 63 | pin(Y) { direction: output; 64 | function: "(A+B+C+D)'"; } 65 | } 66 | 67 | 68 | cell(rtpg_XOR2) { 69 | area: 3; 70 | pin(A) { direction: input; } 71 | pin(B) { direction: input; } 72 | pin(Y) { direction: output; 73 | function: "(A^B)"; } 74 | } 75 | /* 76 | cell(rtpg_DFF7T) { 77 | area: 7; 78 | ff(IQ, IQN) { clocked_on: "nC'"; 79 | next_state: D; } 80 | pin(nC) { direction: input; 81 | clock: true; } 82 | pin(D) { direction: input; } 83 | pin(Q) { direction: output; 84 | function: "IQ"; } 85 | } 86 | */ 87 | 88 | cell(rtpg_DFF7T_PN) { 89 | area: 7; 90 | ff(IQ, IQN) { clocked_on: "nC'"; 91 | next_state: D; } 92 | pin(nC) { direction: input; 93 | clock: true; } 94 | pin(D) { direction: input; } 95 | pin(Q) { direction: output; 96 | function: "IQ"; } 97 | pin(QN) { direction: output; 98 | function: "IQN"; } 99 | } 100 | 101 | } 102 | -------------------------------------------------------------------------------- /10_HDL/mcpu.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Minimal 8 Bit CPU 3 | -- 4 | -- rev 15102001 5 | -- 6 | -- 01-02/2001 Tim B"oscke 7 | -- 10 /2001 slight changes for proper simulation. 8 | -- 9 | -- t.boescke@tuhh.de 10 | -- 11 | 12 | library ieee; 13 | use ieee.std_logic_1164.all; 14 | use ieee.numeric_std.all; 15 | -- use ieee.std_logic_unsigned.all; 16 | 17 | entity CPU8BIT2 is 18 | port ( 19 | data: inout std_logic_vector(7 downto 0); 20 | adress: out std_logic_vector(5 downto 0); 21 | oe: out std_logic; 22 | we: out std_logic; -- Asynchronous memory interface 23 | rst: in std_logic; 24 | clk: in std_logic); 25 | end; 26 | 27 | architecture CPU_ARCH of CPU8BIT2 is 28 | -- signal akku: std_logic_vector(8 downto 0); -- akku(8) is carry ! 29 | -- signal adreg: std_logic_vector(5 downto 0); 30 | -- signal pc: std_logic_vector(5 downto 0); 31 | -- signal states: std_logic_vector(2 downto 0); 32 | signal akku: unsigned(8 downto 0); -- akku(8) is carry ! 33 | signal adreg: unsigned(5 downto 0); 34 | signal pc: unsigned(5 downto 0); 35 | signal states: unsigned(2 downto 0); 36 | begin 37 | process(clk,rst) 38 | begin 39 | 40 | if rising_edge(clk) then 41 | 42 | if (rst = '0') then 43 | adreg <= (others => '0'); -- start execution at memory location 0 44 | states <= "000"; 45 | akku <= (others => '0'); 46 | pc <= (others => '0'); 47 | else 48 | -- PC / Adress path 49 | if (states = "000") then 50 | pc <= adreg + 1; 51 | adreg <= unsigned(data(5 downto 0)); 52 | else 53 | adreg <= pc; 54 | end if; 55 | 56 | -- ALU / Data Path 57 | case states is 58 | when "010" => akku <= ("0" & akku(7 downto 0)) + ("0" & unsigned(data)); -- add 59 | when "011" => akku(7 downto 0) <= akku(7 downto 0) nor unsigned(data); -- nor 60 | when "101" => akku(8) <= '0'; -- branch not taken, clear carry 61 | when others => null; -- instr. fetch, jcc taken (000), sta (001) 62 | end case; 63 | 64 | -- State machine 65 | if (states /= "000") then states <= "000"; -- fetch next opcode 66 | elsif (data(7 downto 6) = "11" and akku(8)='1') then states <= "101"; -- branch not taken 67 | else states <= "0" & not unsigned(data(7 downto 6)); -- execute instruction 68 | end if; 69 | end if; 70 | end if; 71 | end process; 72 | 73 | -- output 74 | adress <= std_logic_vector(adreg); 75 | data <= "ZZZZZZZZ" when states /= "001" else std_logic_vector(akku(7 downto 0)); 76 | oe <= '1' when (clk='1' or states = "001" or rst='0' or states = "101") else '0'; -- no memory access during reset and 77 | we <= '1' when (clk='1' or states /= "001" or rst='0') else '0'; -- state "101" (branch not taken) 78 | 79 | end CPU_ARCH; 80 | 81 | -------------------------------------------------------------------------------- /30_PLACE/spice_testbench_tpd_extracted.sp: -------------------------------------------------------------------------------- 1 | * Spice testbench for discrete logic counterx 2 | * Bases on Yosys "CMOS" example 3 | 4 | * supply voltages 5 | .global Vee Vcc gnd 6 | Vee Vee 0 DC 0 7 | Vcc Vcc 0 DC 5 8 | 9 | * load design and library 10 | .include ../20_SYNTH/microcell_spice_subckt.lib 11 | * .include ../20_SYNTH/2N7002.lib 12 | .include ../20_SYNTH/DMG301.lib 13 | .include ../20_SYNTH/PMBT2369.lib 14 | * .include ../20_SYNTH/PMBT3904.lib 15 | 16 | .include ../20_SYNTH/LTL_LED.lib 17 | .include ../20_SYNTH/amux.lib 18 | .include 308_extracted_netlist.sp 19 | 20 | * Define base and load resistor 21 | * .param RL=3.3k 22 | * .param RB=3.3k 23 | * .param CB=22p 24 | 25 | .param RL=1.8k 26 | .param RB=3.3k 27 | .param CB=22p 28 | 29 | * input signals 30 | 31 | * Vrst rst 0 DC 0 32 | Vrst nrst 0 dc 0 PULSE(5 0 500n 5n 5n 5u 80u) 33 | * Vclk clk 0 dc 0 PULSE(0 5 2u 5n 5n 4u 8u) 34 | Vclk clk 0 dc 0 PULSE(5 2 1u 5n 5n 4u 8u) 35 | 36 | * Note: No pull up needed on outputs since they are internally connected. B 37 | * Pull ups may have to be added for other designs 38 | 39 | Xuut clk nrst out0 out1 out2 main 40 | 41 | .tran 500p 26u 42 | * .measure tran maxv MAX out0 43 | * .measure tran out0tr TRIG out0 VAL=0.2*maxv RISE=1 TARG out0 VAL=0.8*maxv RISE=1 44 | 45 | .control 46 | let startv = 5V 47 | let endv = 5.5V 48 | let ixx = startv 49 | let step = 0.5V 50 | 51 | echo "VCC, out0 tr [ns], out0 tf [ns], out0 delay rise [ns], out0 delay fall [ns], MaxV [V], AvgI [mA]" >> "320_tpd_simulation.txt" 52 | while ixx le endv 53 | alter Vcc = ixx 54 | alter @Vclk[puse] = [0 1 4u 5n 5n 4u 8u] 55 | alter Vclk = [0 1 4u 5n 5n 4u 8u] 56 | run 57 | meas tran maxv MAX out0 58 | meas tran avgi AVG i(vcc) 59 | let trigmin = 0.2 * maxv 60 | let trigmax = 0.8 * maxv 61 | meas tran out0tr TRIG out0 td=2550n VAL=trigmin RISE=LAST TARG out0 VAL=trigmax RISE=LAST 62 | meas tran out0tf TRIG out0 TD=2550n VAL=trigmax FALL=LAST TARG out0 VAL=trigmin FALL=LAST 63 | meas tran out0tdrise TRIG clk td=2550n VAL=trigmin RISE=1 TARG out0 VAL=trigmin RISE=LAST 64 | meas tran out0tdfall TRIG clk td=2550n VAL=trigmin RISE=2 TARG out0 VAL=trigmin FALL=LAST 65 | let out0tr = out0tr * 1e9 66 | let out0tf = out0tf * 1e9 67 | let out0tdrise = out0tdrise * 1e9 68 | let out0tdfall = out0tdfall * 1e9 69 | let avgi = - avgi * 1e3 70 | * plot v(clk) v(out0)+5 v(nrst)+10 71 | echo "$&ixx, $&out0tr, $&out0tf, $&out0tdrise, $&out0tdfall, $&maxv, $&avgi" >> "320_tpd_simulation.txt" 72 | let ixx = ixx + step 73 | end 74 | plot v(clk) v(out0)+5 v(nrst)+10 75 | *run 76 | * plot v(clk)+5 v(rst) v(out0)+10 v(out1)+15 v(out2)+20 77 | * plot i(vee) 78 | .endc 79 | 80 | .end 81 | -------------------------------------------------------------------------------- /10_HDL/mcpu_clr.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Minimal 8 Bit CPU 3 | -- 4 | -- rev 15102001 5 | -- 6 | -- 01-02/2001 Tim B"oscke 7 | -- 10 /2001 slight changes for proper simulation. 8 | -- 9 | -- t.boescke@tuhh.de 10 | -- 11 | 12 | library ieee; 13 | use ieee.std_logic_1164.all; 14 | use ieee.numeric_std.all; 15 | -- use ieee.std_logic_unsigned.all; 16 | 17 | entity CPU8BIT2 is 18 | port ( 19 | data: inout std_logic_vector(7 downto 0); 20 | adress: out std_logic_vector(5 downto 0); 21 | oe: out std_logic; 22 | we: out std_logic; -- Asynchronous memory interface 23 | rst: in std_logic; 24 | clk: in std_logic); 25 | end; 26 | 27 | architecture CPU_ARCH of CPU8BIT2 is 28 | -- signal akku: std_logic_vector(8 downto 0); -- akku(8) is carry ! 29 | -- signal adreg: std_logic_vector(5 downto 0); 30 | -- signal pc: std_logic_vector(5 downto 0); 31 | -- signal states: std_logic_vector(2 downto 0); 32 | signal akku: unsigned(8 downto 0); -- akku(8) is carry ! 33 | signal adreg: unsigned(5 downto 0); 34 | signal pc: unsigned(5 downto 0); 35 | signal states: unsigned(2 downto 0); 36 | begin 37 | process(clk,rst) 38 | begin 39 | 40 | if (rst = '0') then 41 | adreg <= (others => '0'); -- start execution at memory location 0 42 | states <= "000"; 43 | akku <= (others => '0'); 44 | pc <= (others => '0'); 45 | elsif rising_edge(clk) then 46 | -- PC / Adress path 47 | if (states = "000") then 48 | pc <= adreg + 1; 49 | adreg <= unsigned(data(5 downto 0)); 50 | else 51 | adreg <= pc; 52 | end if; 53 | 54 | -- ALU / Data Path 55 | case states is 56 | when "010" => akku <= ("0" & akku(7 downto 0)) + ("0" & unsigned(data)); -- add 57 | when "011" => akku(7 downto 0) <= akku(7 downto 0) nor unsigned(data); -- nor 58 | when "101" => akku(8) <= '0'; -- branch not taken, clear carry 59 | when others => null; -- instr. fetch, jcc taken (000), sta (001) 60 | end case; 61 | 62 | -- State machine 63 | if (states /= "000") then states <= "000"; -- fetch next opcode 64 | elsif (data(7 downto 6) = "11" and akku(8)='1') then states <= "101"; -- branch not taken 65 | else states <= "0" & not unsigned(data(7 downto 6)); -- execute instruction 66 | end if; 67 | end if; 68 | end process; 69 | 70 | -- output 71 | adress <= std_logic_vector(adreg); 72 | data <= "ZZZZZZZZ" when states /= "001" else std_logic_vector(akku(7 downto 0)); 73 | oe <= '1' when (clk='1' or states = "001" or rst='0' or states = "101") else '0'; -- no memory access during reset and 74 | we <= '1' when (clk='1' or states /= "001" or rst='0') else '0'; -- state "101" (branch not taken) 75 | 76 | end CPU_ARCH; 77 | 78 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_amux_logic_liberty.lib: -------------------------------------------------------------------------------- 1 | /* 2 | Basic logic cellsam_ for a logic family based on discrete NPN transistors (Resistor Transistor Logic) 3 | BUF 4 | 5 | Logic gates: 6 | NOT - 1 7 | AND2 - 1 8 | XOR2 - 2 9 | OR2 - 1 10 | 11 | D-Flop: 12 | DFF - 5 13 | Latch - 2 14 | 15 | */ 16 | 17 | 18 | library(SingleLogicCells) { 19 | 20 | cell(am_BUF) { 21 | area: 1; 22 | pin(A) { direction: input; } 23 | pin(Y) { direction: output; 24 | function: "A"; } 25 | } 26 | 27 | cell(am_NOT) { 28 | area: 1; 29 | pin(A) { direction: input; } 30 | pin(Y) { direction: output; 31 | function: "A'"; } 32 | } 33 | 34 | cell(am_OR2) { 35 | area: 1; 36 | pin(A) { direction: input; } 37 | pin(B) { direction: input; } 38 | pin(Y) { direction: output; 39 | function: "(A+B)"; } 40 | } 41 | 42 | cell(am_ORN2) { 43 | area: 1; 44 | pin(A) { direction: input; } 45 | pin(B) { direction: input; } 46 | pin(Y) { direction: output; 47 | function: "(A'+B)"; } 48 | } 49 | 50 | cell(am_AND2) { 51 | area: 1; 52 | pin(A) { direction: input; } 53 | pin(B) { direction: input; } 54 | pin(Y) { direction: output; 55 | function: "(A*B)"; } 56 | } 57 | 58 | cell(am_ANDN2) { 59 | area: 1; 60 | pin(A) { direction: input; } 61 | pin(B) { direction: input; } 62 | pin(Y) { direction: output; 63 | function: "(A'*B)"; } 64 | } 65 | 66 | cell(am_XOR2) { 67 | area: 2; 68 | pin(A) { direction: input; } 69 | pin(B) { direction: input; } 70 | pin(Y) { direction: output; 71 | function: "(A^B)"; } 72 | } 73 | 74 | cell(am_XNOR2) { 75 | area: 2; 76 | pin(A) { direction: input; } 77 | pin(B) { direction: input; } 78 | pin(Y) { direction: output; 79 | function: "(A^B)'"; } 80 | } 81 | 82 | cell(am_MUX2) { 83 | area: 1; 84 | pin(A) { direction: input; } 85 | pin(B) { direction: input; } 86 | pin(S) { direction: input; } 87 | pin(Y) { direction: output; 88 | function: "(A*S)+(B*S')"; } 89 | } 90 | 91 | cell(am_DFF) { 92 | area: 4; 93 | ff(IQ, IQN) { clocked_on: C; 94 | next_state: D; } 95 | pin(C) { direction: input; 96 | clock: true; } 97 | pin(D) { direction: input; } 98 | pin(Q) { direction: output; 99 | function: "IQ"; } 100 | } 101 | /* 102 | cell(lvc_DFF) { 103 | area: 1; 104 | ff(IQ, IQN) { clocked_on: C; 105 | next_state: D; } 106 | pin(C) { direction: input; 107 | clock: true; } 108 | pin(D) { direction: input; } 109 | pin(Q) { direction: output; 110 | function: "IQ"; } 111 | } 112 | */ 113 | } 114 | -------------------------------------------------------------------------------- /10_HDL/mcpu_sepdata.vhd: -------------------------------------------------------------------------------- 1 | -- 2 | -- Minimal 8 Bit CPU 3 | -- 4 | -- rev 15102001 5 | -- 6 | -- 01-02/2001 Tim B"oscke 7 | -- 10 /2001 slight changes for proper simulation. 8 | -- 9 | -- t.boescke@tuhh.de 10 | -- 11 | 12 | library ieee; 13 | use ieee.std_logic_1164.all; 14 | use ieee.numeric_std.all; 15 | -- use ieee.std_logic_unsigned.all; 16 | 17 | entity CPU8BIT2 is 18 | port ( 19 | datain: in std_logic_vector(7 downto 0); 20 | dataout: out std_logic_vector(7 downto 0); 21 | adress: out std_logic_vector(5 downto 0); 22 | oe: out std_logic; 23 | we: out std_logic; -- Asynchronous memory interface 24 | rst: in std_logic; 25 | clk: in std_logic); 26 | end; 27 | 28 | architecture CPU_ARCH of CPU8BIT2 is 29 | -- signal akku: std_logic_vector(8 downto 0); -- akku(8) is carry ! 30 | -- signal adreg: std_logic_vector(5 downto 0); 31 | -- signal pc: std_logic_vector(5 downto 0); 32 | -- signal states: std_logic_vector(2 downto 0); 33 | signal akku: unsigned(8 downto 0); -- akku(8) is carry ! 34 | signal adreg: unsigned(5 downto 0); 35 | signal pc: unsigned(5 downto 0); 36 | signal states: unsigned(2 downto 0); 37 | begin 38 | process(clk,rst) 39 | begin 40 | 41 | if rising_edge(clk) then 42 | 43 | if (rst = '0') then 44 | adreg <= (others => '0'); -- start execution at memory location 0 45 | states <= "000"; 46 | akku <= (others => '0'); 47 | pc <= (others => '0'); 48 | else 49 | -- PC / Adress path 50 | if (states = "000") then 51 | pc <= adreg + 1; 52 | adreg <= unsigned(datain(5 downto 0)); 53 | else 54 | adreg <= pc; 55 | end if; 56 | 57 | -- ALU / Data Path 58 | case states is 59 | when "010" => akku <= ("0" & akku(7 downto 0)) + ("0" & unsigned(datain)); -- add 60 | when "011" => akku(7 downto 0) <= akku(7 downto 0) nor unsigned(datain); -- nor 61 | when "101" => akku(8) <= '0'; -- branch not taken, clear carry 62 | when others => null; -- instr. fetch, jcc taken (000), sta (001) 63 | end case; 64 | 65 | -- State machine 66 | if (states /= "000") then states <= "000"; -- fetch next opcode 67 | elsif (datain(7 downto 6) = "11" and akku(8)='1') then states <= "101"; -- branch not taken 68 | else states <= "0" & not unsigned(datain(7 downto 6)); -- execute instruction 69 | end if; 70 | end if; 71 | end if; 72 | end process; 73 | 74 | -- output 75 | adress <= std_logic_vector(adreg); 76 | -- data <= "ZZZZZZZZ" when states /= "001" else std_logic_vector(akku(7 downto 0)); 77 | dataout <= "11111111" when states /= "001" else std_logic_vector(akku(7 downto 0)); 78 | -- dataout <= std_logic_vector(akku(7 downto 0)); 79 | oe <= '1' when (clk='1' or states = "001" or rst='0' or states = "101") else '0'; -- no memory access during reset and 80 | we <= '1' when (clk='1' or states /= "001" or rst='0') else '0'; -- state "101" (branch not taken) 81 | 82 | end CPU_ARCH; 83 | 84 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_RT_logic_liberty.lib: -------------------------------------------------------------------------------- 1 | /* 2 | Basic logic cells for a logic family based on discrete NPN transistors (Resistor Transistor Logic) 3 | BUF 4 | 5 | Logic gates: 6 | NOT 7 | NOR2 8 | NOR3 9 | 10 | D-Flop: 11 | DFF 12 | */ 13 | 14 | 15 | library(SingleLogicCells) { 16 | 17 | default_fanout_load : 1.0; 18 | 19 | cell(BUF) { 20 | area: 6; 21 | pin(A) { direction: input; } 22 | pin(Y) { direction: output; 23 | function: "A"; } 24 | } 25 | 26 | cell(rt_TBUF_N) { 27 | area: 3; 28 | pin(A) { direction: input; } 29 | pin(nE) { direction: input; } 30 | pin(Y) { direction: output; 31 | function : "A"; 32 | three_state : "nE'"; } 33 | } 34 | 35 | cell(rt_NOT) { 36 | area: 1; 37 | pin(A) { direction: input; 38 | fanout_load : 1 ;} 39 | pin(Y) { direction: output; 40 | max_fanout : 8 ; 41 | function: "A'"; } 42 | } 43 | 44 | cell(rt_NOR2) { 45 | area: 2; 46 | pin(A) { direction: input; } 47 | pin(B) { direction: input; } 48 | pin(Y) { direction: output; 49 | max_fanout : 8 ; 50 | function: "(A+B)'"; } 51 | } 52 | 53 | cell(rt_NOR3) { 54 | area: 3; 55 | pin(A) { direction: input; } 56 | pin(B) { direction: input; } 57 | pin(C) { direction: input; } 58 | pin(Y) { direction: output; 59 | max_fanout : 8 ; 60 | function: "(A+B+C)'"; } 61 | } 62 | /* 63 | // PH-Master Slave FF 64 | cell(rt_DFF) { 65 | area: 16; 66 | ff(IQ, IQN) { clocked_on: C; 67 | next_state: D; } 68 | pin(C) { direction: input; 69 | clock: true; } 70 | pin(D) { direction: input; } 71 | pin(Q) { direction: output; 72 | function: "IQ"; } 73 | } 74 | */ 75 | 76 | // Falling edge clock: C' 77 | 78 | cell(rt_DFF6NOR_NP) { 79 | area: 13; 80 | ff(IQ, IQN) { clocked_on: "C'"; 81 | next_state: D; } 82 | pin(C) { direction: input; 83 | clock: true; } 84 | pin(D) { direction: input; 85 | nextstate_type: data; } 86 | pin(Q) { direction: output; 87 | function: "IQ"; } 88 | pin(QN) { direction: output; 89 | function: "IQN"; } 90 | } 91 | 92 | // Clocked on falling edge, SYNC CLR is high active 93 | cell(rt_DFF6NOR_NPCLR) { 94 | area: 15; 95 | ff(IQ, IQN) { clocked_on: "C'"; 96 | next_state: "D"; 97 | clear: "CLR"; } 98 | pin(C) { direction: input; 99 | clock: true; } 100 | pin(CLR) { direction: input; } 101 | pin(D) { direction: input; 102 | nextstate_type: data; } 103 | pin(Q) { direction: output; 104 | function: "IQ"; } 105 | pin(QN) { direction: output; 106 | function: "IQN"; } 107 | } 108 | 109 | 110 | 111 | // Clocked on falling edge, SYNC SET is high active 112 | cell(rt_DFF6NOR_NPSET) { 113 | area: 14; 114 | ff(IQ, IQN) { clocked_on: "C'"; 115 | preset: "SET"; 116 | next_state: "D"; } 117 | pin(C) { direction: input; 118 | clock: true; } 119 | pin(SET) { direction: input; } 120 | pin(D) { direction: input; 121 | nextstate_type: data; } 122 | pin(Q) { direction: output; 123 | function: "IQ"; } 124 | pin(QN) { direction: output; 125 | function: "IQN"; } 126 | } 127 | 128 | } 129 | -------------------------------------------------------------------------------- /20_SYNTH/microcell_spice_subckt.lib: -------------------------------------------------------------------------------- 1 | * Spice library implementing microcells for simulation of post-layout netlists 2 | * 2021-Nov-20 cpldcpu 3 | 4 | * Extracted circuit microcell 5 | 6 | ******************************************************************************** 7 | *nmos logic 8 | ******************************************************************************** 9 | 10 | * NMOS inverter 11 | .SUBCKT NM G D S 12 | X1 D G S NMOS_MOSFET 13 | R1 VCC D {RL} 14 | .ENDS NM 15 | 16 | * NMOS with open drain 17 | .SUBCKT NMod G D S 18 | X1 D G S NMOS_MOSFET 19 | .ENDS NM 20 | 21 | * .SUBCKT NMg A G D 22 | * X1 D G GND 2N7002 23 | * R1 VCC A {RL} 24 | * R2 A G {RL} 25 | * .ENDS NM 26 | 27 | ******************************************************************************** 28 | * Resistor Transistor Logic 29 | ******************************************************************************** 30 | 31 | .SUBCKT rt_NOT A Y 32 | Q1 Y N001 VEE 0 RTL_NPN 33 | R1 VCC A {RL} 34 | R2 N001 A {RB} 35 | C1 A N001 {CB} 36 | .ENDS NOT 37 | 38 | ******************************************************************************** 39 | * RTPG 40 | ******************************************************************************** 41 | 42 | *rtpg_NOT 43 | *rtpg_NOToc 44 | *rtpg_TBUFc 45 | *rtpg_NOTb 46 | *rtpg_TBUFe 47 | 48 | .SUBCKT rtpg_NOT A Y 49 | Q1 Y N001 VEE 0 RTL_NPN 50 | R1 VCC Y {RL} 51 | R2 N001 A {RB} 52 | .ENDS rtpg_NOT 53 | 54 | .SUBCKT rtpg_NOToc A Y 55 | Q1 Y N001 VEE 0 RTL_NPN 56 | R2 N001 A {RB} 57 | .ENDS rtpg_NOToc 58 | 59 | .SUBCKT rtpg_NOTb A base Y 60 | Q1 Y base VEE 0 RTL_NPN 61 | R1 VCC Y {RL} 62 | R2 base A {RB} 63 | .ENDS rtpg_NOTb 64 | 65 | * npn pass transistor with collector at input 66 | .SUBCKT rtpg_TBUFc E A Y 67 | Q1 A N001 Y 0 RTL_NPN 68 | R1 E N001 {RB} 69 | R2 VCC E {RB} 70 | .ENDS rtpg_TBUFc 71 | 72 | * npn pass transistor with emitter at input 73 | .SUBCKT rtpg_TBUFe E A Y 74 | Q1 Y N001 A 0 RTL_NPN 75 | R1 E N001 {RB} 76 | R2 VCC Y {RB} 77 | .ENDS rtpg_TBUFe 78 | 79 | ******************************************************************************** 80 | * amux 81 | ******************************************************************************** 82 | 83 | .SUBCKT AMUX B1 B2 S A 84 | X1 B2 GND B1 A VCC S 74LVC1G3157 85 | .ENDS 86 | 87 | ******************************************************************************** 88 | * LED and IO cells 89 | ******************************************************************************** 90 | 91 | .SUBCKT LED A 92 | Q1 N002 N001 VEE 0 RTL_NPN 93 | R1 VCC N002 {RL} 94 | R2 N001 A {RB} 95 | .ENDS LED 96 | 97 | .SUBCKT IOP A 98 | R1 VCC A {RL} 99 | .ENDS IOP 100 | 101 | ******************************************************************************** 102 | * LTL 103 | ******************************************************************************** 104 | 105 | .SUBCKT ltl_NOTs A Y 106 | Q1 Y N001 VEE 0 RTL_NPN 107 | R1 VCC Y {RL} 108 | D1 A N001 LEDW 109 | .ENDS ltl_NOTs 110 | 111 | .SUBCKT ltl_NOTb A B Y 112 | Q1 Y B VEE 0 RTL_NPN 113 | R1 VCC Y {RL} 114 | D1 A B LEDW 115 | .ENDS ltl_NOTb 116 | 117 | .SUBCKT ltl_WAND1 A Y 118 | R1 VCC Y {RB} 119 | D1 Y A LEDR 120 | .ENDS ltl_WAND1 121 | 122 | .SUBCKT ltl_WAND2 A B Y 123 | R1 VCC Y {RB} 124 | D1 Y A LEDR 125 | D2 Y B LEDR 126 | .ENDS ltl_WAND2 127 | 128 | .SUBCKT ltl_WAND3 A B C Y 129 | R1 VCC Y {RB} 130 | D1 Y A LEDR 131 | D2 Y B LEDR 132 | D3 Y C LEDR 133 | .ENDS ltl_WAND3 134 | 135 | .SUBCKT ltl_WAND4 A B C D Y 136 | R1 VCC Y {RB} 137 | D1 Y A LEDR 138 | D2 Y B LEDR 139 | D3 Y C LEDR 140 | D4 Y D LEDR 141 | .ENDS ltl_WAND4 142 | 143 | -------------------------------------------------------------------------------- /30_PLACE/spice_testbench_fmax_extracted.sp: -------------------------------------------------------------------------------- 1 | * Spice testbench for discrete logic counterx 2 | * Bases on Yosys "CMOS" example 3 | 4 | * supply voltages 5 | .global Vee Vcc gnd 6 | Vee Vee 0 DC 0 7 | Vcc Vcc 0 DC 5 8 | 9 | * load design and library 10 | .include ../20_SYNTH/microcell_spice_subckt.lib 11 | * .include ../20_SYNTH/2N7002.lib 12 | .include ../20_SYNTH/DMG301.lib 13 | * .include ../20_SYNTH/PMBT2369.lib 14 | .include ../20_SYNTH/PMBT3904.lib 15 | .include ../20_SYNTH/LTL_LED.lib 16 | .include ../20_SYNTH/amux.lib 17 | .include 308_extracted_netlist.sp 18 | 19 | * Define base and load resistor 20 | *.param RL=4.7k 21 | *.param RB=4.7k 22 | *.param CB=22p 23 | 24 | .param RL=2.2k 25 | .param RB=10k 26 | .param CB=22p 27 | 28 | 29 | * input signals 30 | 31 | * Vrst rst 0 DC 0 32 | Vrst nrst 0 dc 0 PULSE(5 0 500n 5n 5n 2u 80u) 33 | Vclk clk 0 dc 0 PULSE(0 5 2u 5n 5n 4u 8u) 34 | 35 | * Note: No pull up needed on outputs since they are internally connected. B 36 | * Pull ups may have to be added for other designs 37 | 38 | Xuut clk nrst out0 out1 out2 main 39 | 40 | .tran 500p 26u 41 | * .measure tran maxv MAX out0 42 | * .measure tran out0tr TRIG out0 VAL=0.2*maxv RISE=1 TARG out0 VAL=0.8*maxv RISE=1 43 | 44 | .control 45 | let startv = 5V 46 | let endv = 6V 47 | let ixx = startv 48 | let step = 1V 49 | let pw = 0.5e-6 50 | 51 | let freq = 20e6 52 | let freqstep = freq/2 53 | let step = 1 54 | let maxf = 0 55 | 56 | echo "Step, Period [µS], f_clk [MHz], ratio_0 , ratio_1 , ratio_2 , MaxFreq [MHz], MaxV [V], AvgI [mA]" >> "330_fmax_simulation.txt" 57 | * dowhile freqclk/freq0 > 1.8 58 | dowhile step < 10 59 | alter Vcc = ixx 60 | let period = 1/freq 61 | let pw = period / 2 62 | alter @Vclk[pulse] = (0 5 2u 5n 5n $&pw $&period) 63 | 64 | run 65 | meas tran maxv MAX out0 66 | meas tran avgi AVG i(vcc) 67 | 68 | let trigmin = 0.2 * maxv 69 | let trigmax = 0.5 * maxv 70 | * 0.8 for RTL, 0.5 for amux 71 | 72 | meas tran periodclk TRIG clk td=3000n VAL=trigmax RISE=1 TARG clk td=3000n VAL=trigmax RISE=2 73 | meas tran period0 TRIG out0 td=3000n VAL=trigmax RISE=1 TARG out0 td=3000n VAL=trigmax RISE=2 74 | meas tran period1 TRIG out1 td=3000n VAL=trigmax RISE=1 TARG out1 td=3000n VAL=trigmax RISE=2 75 | meas tran period2 TRIG out2 td=3000n VAL=trigmax RISE=1 TARG out2 td=3000n VAL=trigmax RISE=2 76 | 77 | let freqclk = 1e-6 / periodclk 78 | let freq0 = 1e-6 / period0 79 | let freq1 = 1e-6 / period1 80 | let freq2 = 1e-6 / period2 81 | 82 | let ratio0 = 0.5 * freqclk/freq0 83 | let ratio1 = 0.25 * freqclk/freq1 84 | let ratio2 = 0.125 * freqclk/freq2 85 | 86 | let period = period * 1e6 87 | let avgi = - avgi * 1e3 88 | * plot v(clk)+5 v(nrst) v(out0)+10 v(out1)+15 v(out2)+20 89 | 90 | if ratio0 > 0.95 and ratio0 < 1.05 and ratio1 >0.95 and ratio1 <1.05 91 | let maxf = freq / 1e6 92 | let freq = freq + freqstep 93 | else 94 | let freq = freq - freqstep 95 | end 96 | 97 | let freqstep = freqstep / 2 98 | 99 | echo "$&step, $&period, $&freqclk, $&ratio0, $&ratio1, $&ratio1, $&maxf, $&maxv, $&avgi" >> "330_fmax_simulation.txt" 100 | 101 | let step = step + 1 102 | 103 | end 104 | * plot v(clk) v(out0)+5 v(nrst)+10 105 | *run 106 | * plot v(clk)+5 v(nrst) v(out0)+10 v(out1)+15 v(out2)+20 107 | * plot i(vee) 108 | .endc 109 | 110 | .end 111 | 112 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PCBFlow 2 | 3 | Highly experimental set of scripts and a placement tool written in Python that transform a digital circuit described in a hardware description language (VHDL or Verilog) into a discrete transistor circuit on a PCB (Disclaimer: I don't know what I am doing). To be regarded as proof-of-concept. 4 | 5 | Makes use of: 6 | - GHDL 7 | - Yosys with GHDL plugin 8 | - ABC (Integrated in Yosys) 9 | - GTKView 10 | - NGspice 11 | - Python3 (Packages: lxml, pandas) 12 | - PCBPlace - my own placement tool written in Python 13 | - Freerouting (Optional) 14 | - Eagle (Optional) 15 | - EasyEDA (Optional) 16 | 17 | Should work in a Linux shell. I am currently using WSL2. 18 | 19 | For details see [Project logs on HaD.io](https://hackaday.io/project/180839-vhdlverilog-to-discrete-logic-flow) 20 | 21 | # Flow Architecture 22 | 23 | ![Flow Architecture](Images/flow_numbered.png) 24 | 25 | The diagram above shows how the individual steps of the flow are connected. The starting point is the design (A VHDL source file) in the blue file box. In subsequent steps, this design will be transformed by various tools into new intermediate representations (grey). To aid this, technology description files and testbenches are needed (orange). The output at the end of the flow are the three green files, which describe the PCB layout (Gerber), the part list (BOM) and where the parts have to be placed on the PCB (Pick & Place). 26 | 27 | At the core of the flow is PCBPlace.py, which is a placement and footprint generation tool written in Python. The remaining steps are covered by existing Open-Source or freely accessible Tools. 28 | 29 | Right now, everything is based on shell scripts that have to be invoked manually. The numbers in the process boxes indicate the number of the script that performs this step. Scripts ending on zero (10,20,30) are mandatory steps for the flow, scripts ending on other digits are optional, e.g. for intermediate simulation. 30 | 31 | The technology description files and additional data reside in subfolders [10_HDL](10_HDL/), [20_SYNTH](20_SYNTH/), [30_PLACE](30_PLACE/). [10_HDL](10_HDL/) also holds the design files. All intermediate and output files are stored in the [Work](Work/) folder. It can be cleaned by calling the "clean_all.sh" script. 32 | 33 | The output of the automated part of the flow is an unrouted PCB. Routing and design file generation has to be invoked manually with the indicated tools. Please be aware that the placement tool is in a very early experimental stage. Constants in the code may have to be tuned for better results depending on input design. 34 | 35 | # Examples 36 | 37 | The image below shows a basic example, implementing a full adder and an AND gate, going from source code via intermediate representations to the final 3D rendered PCB. 38 | 39 | ![Example](Images/example.png) 40 | 41 | As a more complex example, you can see the synthesized [MCPU](https://github.com/cpldcpu/MCPU) below. The design consists of 771 transistors and twice as many resistors. Routing was performed with Freerouting. In the current state there is no optimization of power grid or insertion of decoupling capacitances, most likely severely limiting the speed of such a large design. 42 | 43 | ![MCPU](Images/mcpu_routed.png) 44 | 45 | # Usage 46 | 47 | Most tools needed to implement this toolchain can be found in the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build), including Yosys with GHDL plugin. The [nightly builds](https://github.com/YosysHQ/oss-cad-suite-build/releases) should work out-of-the-box under WSL2 and native Linux. No installation is required, other than invoking the environment with ```source environment``` in the folder where you unpacked the archive. 48 | 49 | Viewing graphical output of NgSpice or GTKWave under Windows in WSL2 requires an XServer. I am using [VcXsrv](https://sourceforge.net/projects/vcxsrv/). 50 | 51 | See screenshot below for an example of how to invoke the OSS CAD Suite, synthesize the counter example and execute placement. The resulting files can be found in the "Work" folder. Please keep in mind that the toolchain is still highly experimental, right now the placement tool is controlled by variables defined within PCBPlace.py 52 | 53 | ## Invoke Environment and Run Synthesis 54 | ![Synthesis](Images/screenshot_synthesis.png) 55 | ## Install missing Python Packages (optional) 56 | ![python](Images/screenshot_pip.png) 57 | ## Run Placement 58 | ![placement](Images/screenshot_placement.png) 59 | 60 | 61 | 62 | 63 | 64 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_nmos_logic_liberty.lib: -------------------------------------------------------------------------------- 1 | /* 2 | Basic logic cells for a logic family based on discrete nmos transistors (nmos Logic) 3 | BUF 4 | 5 | Logic gates: 6 | NOT 7 | NAND2 8 | NAND3 9 | NOR2 10 | NOR3 11 | AOI2_2 12 | 13 | D-Flop: 14 | DFF 15 | */ 16 | 17 | 18 | library(SingleLogicCells) { 19 | 20 | cell(nm_BUF) { 21 | area: 6; 22 | pin(A) { direction: input; } 23 | pin(Y) { direction: output; 24 | function: "A"; } 25 | } 26 | 27 | cell(nm_NOT) { 28 | area: 1; 29 | pin(A) { direction: input; } 30 | pin(Y) { direction: output; 31 | function: "A'"; } 32 | } 33 | 34 | 35 | cell(nm_NAND2) { 36 | area: 2; 37 | pin(A) { direction: input; } 38 | pin(B) { direction: input; } 39 | pin(Y) { direction: output; 40 | function: "(A*B)'"; } 41 | } 42 | 43 | cell(nm_NAND3) { 44 | area: 3; 45 | pin(A) { direction: input; } 46 | pin(B) { direction: input; } 47 | pin(C) { direction: input; } 48 | pin(Y) { direction: output; 49 | function: "(A*B*C)'"; } 50 | } 51 | 52 | cell(nm_AOI2_2) { 53 | area: 4; 54 | pin(A) { direction: input; } 55 | pin(B) { direction: input; } 56 | pin(C) { direction: input; } 57 | pin(D) { direction: input; } 58 | pin(Y) { direction: output; 59 | function: "((A*B)+(C*D))'"; } 60 | } 61 | 62 | cell(nm_AOI1_2) { 63 | area: 3; 64 | pin(A) { direction: input; } 65 | pin(B) { direction: input; } 66 | pin(C) { direction: input; } 67 | pin(Y) { direction: output; 68 | function: "(A+(B*C))'"; } 69 | } 70 | 71 | cell(nm_AOI2_2_2) { 72 | area: 6; 73 | pin(A) { direction: input; } 74 | pin(B) { direction: input; } 75 | pin(C) { direction: input; } 76 | pin(D) { direction: input; } 77 | pin(E) { direction: input; } 78 | pin(F) { direction: input; } 79 | pin(Y) { direction: output; 80 | function: "((A*B)+(C*D)+(E*F))'"; } 81 | } 82 | 83 | cell(nm_NOR2) { 84 | area: 2; 85 | pin(A) { direction: input; } 86 | pin(B) { direction: input; } 87 | pin(Y) { direction: output; 88 | function: "(A+B)'"; } 89 | } 90 | 91 | cell(nm_NOR3) { 92 | area: 3; 93 | pin(A) { direction: input; } 94 | pin(B) { direction: input; } 95 | pin(C) { direction: input; } 96 | pin(Y) { direction: output; 97 | function: "(A+B+C)'"; } 98 | } 99 | 100 | cell(nm_DFFNP) { 101 | area: 13; 102 | ff(IQ, IQN) { clocked_on: C; 103 | next_state: D; } 104 | pin(C) { direction: input; 105 | clock: true; } 106 | pin(D) { direction: input; } 107 | pin(Q) { direction: output; 108 | function: "IQ"; } 109 | pin(QN) { direction: output; 110 | function: "IQN"; } 111 | } 112 | 113 | cell(nm_DFFNP_CLR) { 114 | area: 15; 115 | ff(IQ, IQN) { clocked_on: C; 116 | next_state: D; 117 | clear: "CD'";} 118 | pin(C) { direction: input; 119 | clock: true; } 120 | pin(D) { direction: input; } 121 | pin(CD) { direction: input; } 122 | pin(Q) { direction: output; 123 | function: "IQ"; } 124 | pin(QN) { direction: output; 125 | function: "IQN"; } 126 | } 127 | /* 128 | cell(hy_XOR2) { 129 | area: 3; 130 | pin(A) { direction: input; } 131 | pin(B) { direction: input; } 132 | pin(Y) { direction: output; 133 | function: "(A^B)"; } 134 | } 135 | */ 136 | 137 | /* 138 | cell(lvc_DFF) { 139 | area: 1; 140 | ff(IQ, IQN) { clocked_on: C; 141 | next_state: D; } 142 | pin(C) { direction: input; 143 | clock: true; } 144 | pin(D) { direction: input; } 145 | pin(Q) { direction: output; 146 | function: "IQ"; } 147 | } 148 | cell(lvc_DFF_clear) { 149 | area: 1; 150 | ff(IQ, IQN) { clocked_on: C; 151 | next_state: D; 152 | clear: "CD'";} 153 | pin(C) { direction: input; 154 | clock: true; } 155 | pin(D) { direction: input; } 156 | pin(CD) { direction: input; } 157 | pin(Q) { direction: output; 158 | function: "IQ"; } 159 | } 160 | */ 161 | /* 162 | cell(nm_DFF) { 163 | area: 15; 164 | ff(IQ, IQN) { clocked_on: C; 165 | next_state: D; } 166 | pin(C) { direction: input; 167 | clock: true; } 168 | pin(D) { direction: input; } 169 | pin(Q) { direction: output; 170 | function: "IQ"; } 171 | } 172 | */ 173 | } 174 | -------------------------------------------------------------------------------- /20_SYNTH/discrete_LTL_logic_liberty.lib: -------------------------------------------------------------------------------- 1 | /* 2 | Basic logic cells for a logic family based on discrete ltlos transistors (ltlos Logic) 3 | BUF 4 | 5 | Logic gates: 6 | NOT 7 | NAND2 8 | NAND3 9 | NOR2 10 | NOR3 11 | AOI2_2 12 | 13 | D-Flop: 14 | DFF 15 | */ 16 | 17 | 18 | library(SingleLogicCells) { 19 | 20 | cell(ltl_BUF) { 21 | area: 6; 22 | pin(A) { direction: input; } 23 | pin(Y) { direction: output; 24 | function: "A"; } 25 | } 26 | 27 | cell(ltl_NOT) { 28 | area: 2; 29 | pin(A) { direction: input; } 30 | pin(Y) { direction: output; 31 | function: "A'"; } 32 | } 33 | 34 | 35 | cell(ltl_NAND2) { 36 | area: 2; 37 | pin(A) { direction: input; } 38 | pin(B) { direction: input; } 39 | pin(Y) { direction: output; 40 | function: "(A*B)'"; } 41 | } 42 | 43 | cell(ltl_NAND3) { 44 | area: 2; 45 | pin(A) { direction: input; } 46 | pin(B) { direction: input; } 47 | pin(C) { direction: input; } 48 | pin(Y) { direction: output; 49 | function: "(A*B*C)'"; } 50 | } 51 | 52 | cell(ltl_NAND4) { 53 | area: 2; 54 | pin(A) { direction: input; } 55 | pin(B) { direction: input; } 56 | pin(C) { direction: input; } 57 | pin(Y) { direction: output; 58 | function: "(A*B*C)'"; } 59 | } 60 | 61 | /* 62 | cell(ltl_AOI2_2) { 63 | area: 4; 64 | pin(A) { direction: input; } 65 | pin(B) { direction: input; } 66 | pin(C) { direction: input; } 67 | pin(D) { direction: input; } 68 | pin(Y) { direction: output; 69 | function: "((A*B)+(C*D))'"; } 70 | } 71 | 72 | cell(ltl_AOI1_2) { 73 | area: 4; 74 | pin(A) { direction: input; } 75 | pin(B) { direction: input; } 76 | pin(C) { direction: input; } 77 | pin(Y) { direction: output; 78 | function: "(A+(B*C))'"; } 79 | } 80 | 81 | cell(ltl_AOI2_2_2) { 82 | area: 6; 83 | pin(A) { direction: input; } 84 | pin(B) { direction: input; } 85 | pin(C) { direction: input; } 86 | pin(D) { direction: input; } 87 | pin(E) { direction: input; } 88 | pin(F) { direction: input; } 89 | pin(Y) { direction: output; 90 | function: "((A*B)+(C*D)+(E*F))'"; } 91 | } 92 | */ 93 | /* 94 | cell(ltl_NOR2) { 95 | area: 4; 96 | pin(A) { direction: input; } 97 | pin(B) { direction: input; } 98 | pin(Y) { direction: output; 99 | function: "(A+B)'"; } 100 | } 101 | 102 | cell(ltl_NOR3) { 103 | area: 6; 104 | pin(A) { direction: input; } 105 | pin(B) { direction: input; } 106 | pin(C) { direction: input; } 107 | pin(Y) { direction: output; 108 | function: "(A+B+C)'"; } 109 | } 110 | */ 111 | 112 | /* 113 | cell(ltl_DFF) { 114 | area: 12; 115 | ff(IQ, IQN) { clocked_on: C; 116 | next_state: D; } 117 | pin(C) { direction: input; 118 | clock: true; } 119 | pin(D) { direction: input; } 120 | pin(Q) { direction: output; 121 | function: "IQ"; } 122 | } 123 | } 124 | */ 125 | cell(ltl_DFFNP) { 126 | area: 12; 127 | ff(IQ, IQN) { clocked_on: C; 128 | next_state: D; } 129 | pin(C) { direction: input; 130 | clock: true; } 131 | pin(D) { direction: input; } 132 | pin(Q) { direction: output; 133 | function: "IQ"; } 134 | pin(QN) { direction: output; 135 | function: "IQN"; } 136 | } 137 | 138 | cell(ltl_DFFNP_CLR) { 139 | area: 12; 140 | ff(IQ, IQN) { clocked_on: C; 141 | next_state: D; 142 | clear: "CD'";} 143 | pin(C) { direction: input; 144 | clock: true; } 145 | pin(D) { direction: input; } 146 | pin(CD) { direction: input; } 147 | pin(Q) { direction: output; 148 | function: "IQ"; } 149 | pin(QN) { direction: output; 150 | function: "IQN"; } 151 | } 152 | 153 | /* 154 | cell(lvc_DFF) { 155 | area: 1; 156 | ff(IQ, IQN) { clocked_on: C; 157 | next_state: D; } 158 | pin(C) { direction: input; 159 | clock: true; } 160 | pin(D) { direction: input; } 161 | pin(Q) { direction: output; 162 | function: "IQ"; } 163 | } 164 | cell(lvc_DFF_clear) { 165 | area: 1; 166 | ff(IQ, IQN) { clocked_on: C; 167 | next_state: D; 168 | clear: "CD'";} 169 | pin(C) { direction: input; 170 | clock: true; } 171 | pin(D) { direction: input; } 172 | pin(CD) { direction: input; } 173 | pin(Q) { direction: output; 174 | function: "IQ"; } 175 | } 176 | */ 177 | 178 | } 179 | -------------------------------------------------------------------------------- /Docs/Technologies.md: -------------------------------------------------------------------------------- 1 | 2 | # Technologies 3 | 4 | # RT - Bipolar Resistor Transistor Logic (default) 5 | 6 | - "CDC6600 style RTL logic" 7 | - High performance NOR based logic with high power consumption and medium area. 8 | - Balanced voltage levels by using pull ups on inputs. 9 | - Reach through capacitor to speed up switching. 10 | - Can achieve ~10 MHz with counter.vhd 11 | - Supported gates: NOT, NOR2, NOR3, NOR4 12 | - Flip-Flop: 13 | - DFF: 6x NOR DFF_PN (Default) 14 | - Latch: CDC6600-Style Polarity hold latch 15 | - DFF: Master-Slave DFF based on PH-Latch 16 | - Cell size: 0.15" x 0.25" 17 | - Recommended components: PMBT2369, RL=3.3k, RB=3.3k, Cp=22p for 5V. 18 | 19 | ### Post Layout Simulation of counter.vhd 20 | 1) PMBT2369/3.3k/3.3k/68p/ DFF6_PNxNOR @ 5V 21 | - 58 micro-cells (58 transistors, 116 resistors, 58 caps) 22 | - Functional: Pass 23 | - Fmax: 25.5 MHZ @ 70.2 mA (for RL=RB=4.7 Fmax is 19.3 MHz@49mA. with MMBT3904: 5.5 MHz) 24 | - clock-to-out0 delay rise: 14.3 ns fall: 14.8 ns 25 | 26 | 2) PMBT2369/3.3k/3.3k/22p/ M-S PH-Latch @ 5V 27 | - 69 micro-cells 28 | - Functional: Pass 29 | - Fmax: 6.4 MHZ @ 79 mA 30 | - clock-to-out0 delay rise: 11.5 ns fall: 26.7 ns 31 | 32 | 33 | ### TODO 34 | - Clock distribution -> new dff has clock buffer. Manage fanout ? 35 | 36 | --- 37 | 38 | # RTPG - Bipolar Resistor Transistor Logic with pass gates 39 | 40 | - Low speed logic optimized for low component count. **Attention:** Use with care: High Fan out may create nonfunctional circuit. 41 | - Uses NOR style logic with additional "artistic" gates based on pass-gate NPN transistors. 42 | - No voltage balancing, instead strong high level to allow fan out. 43 | - Achieves 300-500kHz with MMBT3904 clones (e.g. CJ) 44 | - Supported gates: NOT, NOR2, NOR3, NOR4, XOR2 45 | - Flip-Flop: 3T master slave FF with pass gate 46 | - Cell size: 0.15" x 0.25" 47 | - Recommended Components: MMBT3904, Rl=3.3k, Rb=10k for 5V (FOmax=4). **Attention**: PMBT2369 will not work in this logic style due to too low reverse beta 48 | 49 | ### Post Layout Simulation of counter.vhd 50 | 51 | 1) MMBT3904/3.3k/10k/DFF7T_PN/XOR @5V 52 | - 37 micro-cells (37 transistors, 68 resistors) 53 | - Functional: Pass 54 | - Fmax: 0.625 MHZ @ 27.2 mA 55 | - clock-to-out0 delay rise: 550 ns fall: 371 ns 56 | 57 | 2) MMBT3904/3.3k/10k/DFF7T/XOR @5V 58 | - 40 micro-cells 59 | - Functional: Pass 60 | - Fmax: 0.625 MHZ @ 30.2 mA 61 | - clock-to-out0 delay rise: 589 ns fall: 370 ns 62 | 63 | 64 | ### TODO 65 | - Implement TBUFc / TBUFe changes also in layout -> done 66 | - Implement cells with RL on output -> done 67 | - Clock distribution 68 | - DFF_NP with clear -> done 69 | - Adopt to 0.15" y-pitch -> done 70 | 71 | --- 72 | # nmos - NMOS transistor logic 73 | 74 | - NMOS logic based on power mosfet supporting wide number of gate types at low component count. Relatively robust, but slow. 75 | - Can achive 500kHz-2 MHz with counter depending on transitor type 76 | - Supported gates: NOT, NOR2, NOR3, NAND2, NAND3, AOI2_2, AOI1_2, AOI2_2_2 77 | - Flip-Flop: 6x NAND with clear 78 | - Cell size: 0.15" x 0.25" 79 | - Recommended Components: 80 | - low cost: 2N7002, Rl=1k, 81 | - High speed: FDV301/DMG301, Rl=1K 82 | - Is very noisy on supply. Some improvement of speed/power trade-off could be achieved by balancing the load resistor for fanout. 83 | ### Post Layout Simulation of counter.vhd 84 | 1) 2N7002/1k/DFF7T @5V 85 | - 58 micro-cells (58 transistor, 27 resistor) 86 | - Functional: Pass 87 | - Fmax: 1.17 MHZ @ 66.6 mA (RL=2.2k: Fmax=0.55 MHz@30 mA) 88 | - clock-to-out0 delay rise: 77.8 ns fall: 183 ns 89 | 90 | 1) DMG301/1k/DFF7T @5V 91 | - 58 micro-cells (58 transistor, 27 resistor) 92 | - Functional: Pass 93 | - Fmax: 2.1 MHZ @ 75.6 mA (RL=2.2k: Fmax=1.25 MHz@36 mA) 94 | - clock-to-out0 delay rise: 65.3 ns fall: 67.9 ns 95 | 96 | ### TODO 97 | - Clock distribution 98 | 99 | --- 100 | # LTL - LED Transistor Logic 101 | 102 | - The bestest and fastest. Diode Transistor logic that emits light while being active. 103 | - Can achive 500kHz-1 MHz with counter depending on transitor type 104 | - Supported gates: NOT, NAND2,NAND3,NAND4, (AOI2_2, AOI1_2, AOI2_2_2) 105 | - Flip-Flop: 6x NAND with clear 106 | - Minimum cell size: 0.15" x 0.25" 107 | - Recommended Components: 108 | 109 | ### Post Layout Simulation of counter.vhd 110 | 1) PMBT2369/1.8k/3.3k @5V 111 | - xx micro-cells (xx) 112 | - Functional: xx 113 | - Fmax: xx MHZ @ 66.6 mA (RL=2.2k: Fmax=0.55 MHz@30 mA) 114 | - clock-to-out0 delay rise: xx ns fall: xx ns 115 | 116 | ### TODO 117 | - Fix and validate LED spice models for post layout simulation 118 | - Clock distribution 119 | 120 | --- 121 | # amux - analog multiplexer logic 122 | 123 | ### TODO 124 | - Implement clear in DFF 125 | - Merge both into one. 126 | 127 | --- 128 | # Deprecated 129 | 130 | ## 74LVC - 74LVC single gate logic 131 | 132 | - Using single gate logic: 74LVC1G175 and 74LVC1G57 multi gates. Very versatile and area efficient, however 1G57 is not always easy to obtain and expensive. Rather use amux logic. Not PCB proven yet 133 | - 134 | 135 | ## YG - YG strip logic 136 | 137 | - not finished 138 | - removed to clean up before refactoring 139 | ## NE - NE555 logic 140 | 141 | - More of a joke 142 | - Removed to declutter source 143 | 144 | ## hybrid - hybrid nmos/bipolar logic 145 | 146 | - Nasty logic level, neither fast nor stable. Don't use. 147 | - Removed to declutter before refactoring 148 | 149 | -------------------------------------------------------------------------------- /Images/PCBFlow_numbered.drawio: -------------------------------------------------------------------------------- 1 | 7V1Xl5s61/4t30XWOudisug2l2Cwjcfghhs376IZg2nGYAy//pNwL1OSTDJJjiaZMQghpK3d9OyN/IVsBLtWosdLObJs/wuBWbsvpPCFIHCMYcEHLCn2JQzF7AucxLUOlc4FI7e0j3ceSjPXsjdXFdMo8lM3vi40ozC0zfSqTE+SKL+utoj866fGumPfFYxM3b8vnbpWujyU4sdxwQtt23WWx0czNLW/EujH2oehbJa6FeUXRaT4hWwkUZTuj4Jdw/Yh9Y6E2d/XfOHqqWeJHabvuWHSszxcTuaSqC/DqLEeMw3s6TAbW93PDiM+dDYtjiRIoiy0bNgI/oXk86Wb2qNYN+HVHEw6KFumgX+4bOmb5anuwvX9RuRHSdUQaeMWbddA+SZNopV9cYVlaqTOwCsrOzWXh9vvB3gY89ZOUnt3UXQYcMuOAjtNClDleLV+IP6B/UjscJ6fJ5NiDmXLy3k8VtQPDOSc2j6TGBwcqPyY4gJmJL1QqmOMiu+exGeNdM0nnHyb5LYFmPBwGiXpMnKiUPfFcyl/Lu1GUXwgmGenaXGQIT1Lo+upeR9tN1GWmPYr/T90P9UTx05fG+dhWHAsr05VYvt66m6vBe7DyX5PdcHeuE74hWB8MAzeSMCRA4/+mbSF7r93cwLEN4aHVmRmQUW1t2TB2AtO1/Afy4Ol2/WF+UgesOofuHItex8tHfS1cIDn3gkHTjwQDuanyQb9Z8vGkeffFg7qs4SD+iQKXxmGn0hu8rfSOsceXpBb9HUjSsCzowe651RyLGgBXXQsBD0wzhVvJu0NXfRzFQmB/XaahP3DNQn1Xk1S/70Y/l6/jIowXQJbu/kCOYDRA8ia+7/7khsZUG1APwKT9Th2Q+cdMjKPNsXm9xcS8rczt6cx/KlCUn+nkByp+nFCUt3KJYleXFSIIzdMNxct92HBhb9F01ccQOI3K7Zvqw8O9j04c8BpKD/gKGN/k4fwbg5hfy81Wr+bBMVOfXeTPlivjGIXEAGCG0mgp79i5WJXP49WLiRDsqT1C1Yu79Cl+C/Vpe9AUn6+LgUUTYrZ5ckcnGBf6eOpAAmInc6Kw9n3S9hRtV5K2P8kj5KnPL16qgV+zcDS3FGfaj9FBd/pTOrGyp6s7rGJfUcPd91M+geoT+JefcqumURmde+t7Dp2aL97LdBv8H0fiOzXuPj9vZ1bCSWJT5fQz1r6fpAtO3b3NwYXXu33Bd2hi++7xgNb1nUNwGLFL7Vmi4VpsuwnWjPyxs/DP92akbU/XFbod8oKyfxesnIPgDajKI2TvY37e83FLYL00Fz82sXxvQv+Z4lA7Z0icOS530UE7lUP4GRQoNpBDDpgP7Aaou74cAX01Uis/4TFuBUXCv90cbkHXI/r0o0bZP57tZbiHG773TUW89vBeeRnRZZPq07sK3FaaVYLzzeWnR8Vkj5mhvxhKM+x35drRf20VsQCmE2zeQXwCfeQ0H9C49G1a3F76CP/WnH7w4PV5HvXkx8vNY+hmxpzo1Hx90E33wrD19jHz3kJhq9Rr9b/STD8o1XzJjXsEEbH7lSC4myO1tZM3Pi/oRNq5G+nE/7wsPNxOfz2uvn3CjuT9+j7OATMlwLeI7Bq/fDpi4bfIGhyJS2fv8Sm/nCUiXxvdJH6vVAm8h7aGAJZeV+2xVFsYBcIrJnYdnJ97++7ZKN/t0Uz9YfnAh8do7cFgPitBODY7wu69zKwlgoBY4MWMWHY+GZJEPVNIQrcHycFNPvZUkDfz8afJQXvXUhRP2ch9a3rn9tENOaN9c9tfbpO3sz5T1j/0OSv4QF756azi+OLfAlwdsat4MkHw1bv5hsa/y34hrpZNzO3Lxx9W/2fxDfUr+Ub7CtbrYHPvMMwtVe554yWfvmmHB3YSN9OXEAhO/ksTvxwO/4xGoz8Ng3GMOTrnIu/Wv/ncO5xEh68ooSBpeTe0/ihBKJT9nVobOLKgflDXJbbcNfn+yzU7x0dftsV+TkZ0XeShN9IEn07I3vd9NPS8ah7YGiIYKFX1wMPXpH9xbJ1D6K27MQARo/AmkARbn7BrJiWbdSNT5yVWxN0Epw3p4X+SdNy9EIvEzNcc/Xl0Vs9VeLRf2KaiFvLVPtKf/ZE3TsSfE/+T8wG+dgv/CVz8eANc9dxUx3W+aYUmD/znc9fGnz7LV62eJGIl+utB4mon/aK8n3Cwmsh5V+1DcKnh5HpT2TkjbiOak4+SSgvMdnuuJhNR0/3YbETZ50nAgwuvSa07sPFIimYgBQQIeAhCVxT97nDhcC1rIrzE7CuLHWjagrCCIf1NmiX5r/QAmwLsP5mLwX43dSEUWjfzOOxKArTo9Dhx/NDMxDf8HXD9nndXDnVlN7cvb8aJZadPGj3gjGaTQz8fMzs32V31O6nn3ww+8TPmv2j43cx/cciNP0fPv3EbTLQp0//vZuNI+n/VdOPf/r03zvvBJL+nzX91G+n/O9XESSa/p81/cwNyELWf930P9yO79Fr//mX/Z6He8Ty/ErXmzzx3ol7P+888vTPvjmclJc3cbhmjx+fO/L4usNRdNkHuMvxxcrLySM/YPJee8P9Eh+Dk1Wtkt639U1XL6IMVo7i1A2AmB4Qg6uozd/26t9tcO6X5iU+nMgHLlg/gltvYP5xgu4n4b/xltMvzZl7PDn3DtIdyX7x/jQ/EtH/1tyTF+f0zQ04jlx9gztdw1Uzv647M3+VrJ0g1Z+LvraR91bpw0ODtVvjW2O/HhMi34gO3rd1q0MetPVxG388Ju8Dzw2t234VanPa9uUXeG6Pp/9+d5GLfV/Qu3yvvctHf75R+TZoHL1t9XvM2meFgS5feK5Rl0Yf/4phb5n9e9/hNq3vw438hxtvhmBh4mMNq9fIWp2hHnPGt5pxpgZbvW7rnft3fWsKIXPDzcdk1Re7Vidfq//DKYGPZ/OzXpD62Qx+zp49ervziyvf6Ple+q+vavefLhR18itNfrRQ1EjmK4Wzp5/6NR/WsK8kdvFT+ynicvvO9FviUju+kfmTxKVXi8jVsMfMBB/j4p4cCeHu4ZdZ7G235W7BBdPXN/vxMuss2qfPynaYGTrwXMNUd0OYY3a8diVmx8II2MuFD7/Gg4NWDrjmdrivGwPPu1r9V1d0YxP5WWrvr5lZsoHWGl6x7IWeHVb9mHFyqp/MvUGHVRLH+IeA6VbwXaTLg38PzV1XxfbXjx+HStD5flrogesX+6pPehz79tOm2KR2sK/L+264knVzVJU1IziDjS8XWNVh1CPbiaC3M5bAn4meuNUq5KbS27c+qr/vzlPm7k8z92mjh5unDVAYi31R2/a3NlwR7U858HT/cO9NzdsncHDAoHzvKxGYGESe++3dfuG+M5X3Sy5IY5yKd5cX9vwDr4RwOzv/4toWkhF8glWenmYJ/JKbV+uZevxSlfzgbMGL1GGFhflAwdvJ0wY4nPDlzLs7oyReAvrtLxD7Mrg6fTosSLmK//UkvbjkAvcyPDwIO460upImoC24Zd/xQeGB9Suvt+rFA0IAz7H6hp6LLuRgIXnd6dODwDiNlQueBR+494KfDr7nfYcs2zzssv+ULl1zFdqbw4PcEMjpsQe3dS9m7NV6FyJ4XQ8a2Kve+PbilmLJebpOZcuLOWSo2yED0X1KbOekXqxEd/a44omLr5HGNxXeG3ruwbQdlizw6e4m9vWDWjH8yFydpvM4GfXzyGLdsq4mE8x19Xd/TLPHikfg45IDT+DHGxrWiHZQDE/PMSo84gkU38wL+SZtw+jpTfLqLxBXqlTrq5R9NMqqd3eUdUP4RurTBYHfpfhvWPVWIF+0RZUIXxK4MrjYVxxu3G/rGxuI/9Me/cY2D6aWqabz8u9xZm+p2KzeZjlB3zqi7kdSV7TcFFH3Z1F34sKALKLuz6EuXBSEDlIOP0857MCzNoi+P4u+YLESfz91MQjagNXA5tcRGocLdUjjy4PvJzeB/Z8bxFGS6uEH0Z6+o339Bdq/RndQVrnE97NxT92PYMWXXOTXfNgL95kkHq0LSOZYGuiJ44YXa86jN12v/uKnihFcSaWHfmBf6/TRXa7c40S33OywLCKPt7yCSVDYkUXo/QH97909blB9pSq8J0v8f26XzZae6uDqvhbR3GydLwS/g8AjbwBmgKBZoy+wlDHNHSuYFCbhbw0Pc+URlUsu7xuBstVafqaVmGvNhkFXddx+ST332wqhFTyhzTqlPmWz/kjadT3RlVr+qj/qNOfBJNMm9R1oA7S9y0xwv94eYqYQbbukRVoFTcoFvTUDcyt7XC432NIKTFdqL1OjRZe9cLnRp3QC2oqs9jDvufUtuIvshmbZDdhCK+q7nrqiu+S+HnwO6ENuth3QxoqVPD63G9JzY8QT+nRCDgK2ui4JnCN7Ei4JUqGMJMckh7TRGrMS6O982tloI9ydT5VEIztba0qvegHtWwV3fZ+62fdTiEuz1fQ0FXPNdsc3iUlhBWO370T1Q7uO1fZzeN1qTSirwXomKcPrnW6oYPIsDfTpbtNzFXHoaYIsyrXF4HAtPF1rDVca+J3Da/UuqWD2dOdXz2g1Mb3Be0arWUL6muQA0hvSX4F97QrSThlR2LzkNuCz7KqDTC5yuuvN096IAtdXmRLkeVfgJaU0M3map4owyHoNDAP1cVWY511P2siqjBmCU3Q9M5VVDnxam54gZfIop5QGhU+8/XNsV9q+0K/i1C/VwcDzQZugf94y6qpSCdvrwnN1ANv2QFtkVxUz2YV9dVLFpYqqrwW2k/152ZvKeVedw36CNgagT6Av8Bqsp4qgDQW0y2Xy2KEBHxMNx/f29cFYq+sypAd2PK7uh+3O5iVoY3egF9UVBuAaB+8D/TDBcWffT6Hqp6QIXKa0ZNg/UJc79CO/6FNe9cnyQF8ObcO+yI2cAOPa90G46INb1S910K48dTDQd3JeHvq9r5de3LN/RjhP5Qa1s1zs2Pd9f9RxpjQqmpT7cUr7+oRT1dfBHBuChFX0BXOptJwd4IkS9G8je4AHRjkG7sVGgojJxLeNsaJfVR/2YT+mfZ+lzaEPgK+akSKImULIFS3kYz314p6q3x2imssZGGcJ7gXy8eYYMXnXA3yswL55Y0i/x+fu4bwduV2o0/Y6CCjIhgMtVGWkrrTpvfq9NjCHpJLTwW3tC+QSGjj6fHBbM7FjW09PCMnx9GULjxN0AE089D8g3HSy7j+Cuzwy7Xuo6xAYOHtUUze0ohyYsDBNIv8tj+rKXu+/m5w/HD2lh43noTnMgiNkuqfAP+TeEJLA/P77tok/wVAn+36BBZKPbD5xqvkeusGNQvwL544+dO/y4N9XKfwScGhkaQpTG/eA7hU1b0gfAH/uWPtVmlfE1RNbP3Dgl+NWauejTayHVwWHUOWth7Xw7QOVvGyTuouimvcTVn3J/ZXL/ATGEGzuL166YA+h2fN0ZBuIrtt+9a3zV87fS6StfJ2LbIljPRgYvCDURerEqcZVha1r53y0u6qB7T1UDMb/MfzlPsTwW+kB8a5nrLoL2+LLJxzfPuHlzcRdIu0Xt32FOzrVXxXW/ePuiitKvMdB/wBu1Hc/yI0E4sb0tRqvsuPxzzfyI/aEf2UYpmY/MVscA2yJAbbEyuAJph9ULA4/l0+1ryxb31Z/l9Xfd7Mu/ZvzrelHYGn8Y5xLIs79fs4lDn++jXOZr3WKZUA5/KW/4jRGnQ6esOpipWv3R0+HC1cfd/Uv7ntU/3zbS/UfdOX2nvPReyWI/KkC9C2le2H7ThwHpUmgNAmUJvHr0yQyc/mkm4+g0627cQ3XP6GW702yejk169Lw4MfhX5AEfwNQ3hucewXzILXjPv/j8jkXS+urPl2UvwQcw1XVRVMnAYLlV23RbwzmTgE/0sifXemFsh/2vxx75Fr2db4f5tjN6rtGvy8H8OxJfVcG4K1mPPlFB4j+zGN4Be2DRoGneMDj4deEV6mBBHY8oO4goQv8HuUU/jnGEtnE/5hNfJQVWFZ02x0XdtcmBj8jhhdjISjsrELA6jG4afIV8/qKP/9NOlZwdSfRg2sdeyiErxFaSRRf6dhUNw7jvF6J/To1/FrQ86hk4b6ke6V5pQ/PyvtE4+jwZRK3AXOkY5GORTr2E3WsG27s9FJ7HvXlKTOZoM6u/HetUb49I/v8ZnW/Sop4VetVic5L3TrqvUpFYUfNdHHw72lMlznXp+XP68nUlev5YIX0yiLr7KiS5+jWyVbR55SUyyxx4lR6tYbBmfqNG3z3dgx91MXng3+v7rhglb3P/Jaef63Jj01v2aeqkPp0iOkC5ioC50qtpa9Prcg6nh/STl5JNylkgcu7JGwLKDu+3xr6WijDoza/BPf4ZkA5+nTASoFVgE/QphVr7WHUH0mY3JAcvTWJNWKJHc9hmoTVmhSGP8n02RA+G4cpJGOSX86JSR+Ul9pIOj6h5Tga6K06gskoYi6JuaPApBSVc0DZTm5wVRk8h+X7etK5nleVFad63mU9+VyvrMrKU72yqgcopsVGKwejo7dGMAajUzAzYBOY3CIRg1wT+BUclVH13sdsUC43KJj4UVrtzlYnxqlF+CswDlbyRBhwPyaKVIkhkjCokmzUxiHZpsFVVNICf2OAcRsBm2n7hJ3CIFIfUNGrntka5K89o0ueZgdSssGutKlW9r1doU0V7GKOdmB+fdBSpE39UG8PYAu53BifRx6CuWo4nkZ2Yq2xOrQO+KGkviNV4Gm/vnx6Cwx57Az+hhAJTpH4SygJ8V5N+FDw34xQANdyc1u2cP19KsZNoAc6w6O9Qn+xvYXd0rPNBjgavJ9VbYRXbYyqV0k5H7gMN+bDEuyte8hQvAyEfK1dVQT+TeUKXxqa6kmvcMFtp2673FssoLG96+xtw5h17feT1xeLVy4+6HZUPZV/u/PH7t12u+lHEQRYFvDzaCSEy8ZIUqDoGnXVk33tU7bl5TLmK/W+Ph+83Vc7fejcbZ8bUVBxsX1P7RfaBtWId9ANi2L49TI3JHDDD5uFi57fDgrojtB6iddbiR4Dv/E7hvSgE4cn3V85iOy9Anwg358NmX4yrqrqxnvx04ODdsYx7oFN4ujHXhzcG7C7lfoR1aTI4wGF4M3fc+mNYoEvr8n/umX3q289vPam8ftieg/etb5Yxz9EQS/A1jNg+lH4pxpF/p+2p8Tphekzsb4t4IQ0LNKwf4yG/W+hnu/cguLkkJ33n7h6++yt9+7eVIhv6MGftecEfYGCYjfvx73DF30tyP4IjH2MI54efdeZAyb9CmH1F8jahTtvXhE1ddMbou7fV8f+2W88SPACfFUAznVFpfDfN+bko1/LrfaZOmaJfserocBOHt9C2XM1LLx8G5J4yAJ7qJ++nvVHM1516bjH2A+4J9eW+7yv2A3LEt8vU6M42S/4j4dPiyqLBUzqDVM8WIHdJIe8A8mOISnPGLY74XvDHHtuOREHfpTReCmOHXDEj8GvPWhwMjwpytlzH1bAJ7w8EcfwsJRL6fAr4oo6vjyHn4XsSRdlVTnT86Kb8qoupggc+JVyWeDAdfHimgivgU/5sk1QBssHD54h0z11BbrXwFNjViVJw/9soAVz2PpA5Lmg42qq2+/UbBLMSlMjhrnZ5hwJfo8ovwjp5XzaLE1SAZUb0frZBfRcgwft1DEOX5qck0ppGq3dBnSAzOt9fjBuCg7VE+Dbpvmm23CiZ76vYuwUxgxiGhLruT0cqb7MLSlBEC28XgOXAt8Ll9uJY9NhsJQHLrXk6tluRUh+u9ebmzhGyKB33hSr1zvggPBddQDGldKdodgc20qyIXt4FmDcYGm36FDqNyJpjQ9g00BFN+WQneHP7C4VOZkddgdBTyiLHm5OwHUlLb3Rcum1V8MV54SsIDf0eTicSa3ewEqnwQovh9MA2yoKo5eg/hz8bonFTKNdFRJ1pVFaaztWVAacDDtZA/Z0Mhk+N/nanM/TcI6vyCWRG5HeLurD5qBBTFqZiQs1EptOuyOiJWlETZepYqyCptl0pneVnA2wQGIzYHrjYdcGmonXisaiCeYgN1frCTnl201N37W7zUTZTWJnPBlOPQfSyHeJqbFoU9NiNw+n5mSCDctac+4RzIy1y4GZieRkvpqVzdE8Dlh7zcTrkZspc073ILWwltvcPW/pVOytd5PFBMvSpLHSIOO0GzM161mtkpDaz4YwpHOrw/QtexhIm8XWFQWsQWuTWuQtqHptS7OLfnujQlMDb9bxeYi3O1Y08qTxjG/RM0fnbW8pzyeByvK4NRz3FI96TothWwmU1bgrzG2BaLQmnqsBzdd7xr1JNn+WYq+j9moBa0XbrRiSBpiTptCmKApbEGAAFrvY+pMlOKK63eyZMeV6a2I+P6+CNamt1/zCWOr2ggpBhdj1+MxStDbZBme9KalEkAKGGkxm3sJ0+wZQ2s3WZFAbjJl0uh5PaR9YgEUbyMWC2UmswO2s9WBMhjSdjesEHniElo3X2GgeEe6Wo1N1uVuRyTOTgXazZJ5q7vo5a7lTWVwZMdA5zV6zK6nStkgW9iol6Wlr6237TM8Xh3kf8BM/GZMsZDqowcEHNlKX/bq3qg7tiLOXQ69nBNZSB4Of54vMlDebWqb3J00yUZcKeILYZhZtcr4UU9IQ8FL281aawTmp63SZtDvZkFGKZPUsP9MKvV4vWHvLzKnlorUY9ROzpk21dX+QDPo6FGC6sbDrzR5NB+QsMTd1lVSb4/kAK9ce7an9SAaadVBSRtJc1gVyR3fZXugUwwLcK4k61nH4oa/zU07qzIvJ3JsLTarWzxUghk0156ThAmod3m2ahR355tL1dEiEfm1n7ZlI2towVtfx4zxMLA1csHeWAAWPgmPtC2UfYxTNMuvbPtWuTZ+bs66x9gbmmFVrA23bXLYtpWqK34RWUDB+YzAcsM89rj6McHXnpek8G/szmn+mwVoHrpKZeUeaer7SHIqruNuZtQbZtIfhNhH09TEVc3ht3a65ov28GG6SZL2Es5piy86gL3ZGEWDjfjPubGxMyrC+MlAmIyXsZXWt3Z9qZl0dL1e8IzaG7kqTk5iardkprvQzYyVJ44BahklauKuR5K1BZzxzRRo9frCKwxGfrMZsjev6NTLurGeLpklzfmetkOZsG6nis1R2zIzuj8Tmuu22YkZfQi4iSY1MpmlcLsXFM84Ivfps5pIjYittF+NGO4ynYFK1ttuecM1xC3sedCLR8Vpea9hs4T5rrAnaKforKeIU3hR1gxXE/oKouY0VhU2MqY5l/TozXckbddDuD9r8KOx02o0ijXFryo5LwuQHUYT1xfUEfuFxMyEMGcNJvNFNu+W4MRm7Vs6GTAb4d16XrHA8l+2U4FXTHKfSYrQMSwYLeJuhO7qahV1I6Mla5QzDFnEpaJjk1scZ2ZREd2qSaaPhC7Qgs9yqpjW1Br/SxEm5XC0k4MI2Q6ZtWFCi8iZJ8p1Ru55oJrOVRhWcHPppA+4oA8whQTdHqVUSBbbUZiLO+klKx3itphRD+IYh32sbkHnby7IDxp73iWyeeNsSX7KErW5sRSwFgycgFN/szfF+wU6VHPLr2gsVaGGDbRjk4Xy18xZ4Cg0hN63N/I1R6h1SrwllG98syLEV1wKI2Ji9BYPTmynBjKzFtpU09J0xoXw2FPUQm2G7tagPE2MbhH7SamZkX1XI0BpH3V6mx9N6T+iWmdWdRIHc5mrwrZimnAPlG6gB7IvR08IRq5gdYQM1D03C/kz75SA0FJ2FRBtGjb5PcM/rnvHc3PqpyEf9rTnJlTzQt7teQUpC3uT81bQx7fPrZUdo1FvpBtzTmkt10x0UQyi9JGiq0W23N2axmW0XWBGWU6k32PQTMp/6/mqnDDYrAXaoDndXlZZufd1oBDiNzeKeMQtNYtiEPTQ76+GSE2muHUt1vqcZbVodWP6Mr3e4sSg1KG67avZHsuhD0g2g2YYRLh42aviMHTZTSNRtDZoN4J80TfBrt0dTsjFWhi1FKzzH1ZS2yCymhMEsGHLSGpmN9mgr1RpgvtqQAeehOqbIRpE3XW4RqnCaoWnxs7BNEjVqSLeI0thiQBt7LFQ7JQufNq7F6/6MJvqaZ8kknS2Y7W5DRou4xrLPmb8g+HpDNInOxNt2AqYnqXSjx/bt1VaAilutMbWZo5pECVyeULQcp1Bpe0ZAoqzYohVv2/hqvZVogpQmixFXWv6UcIyMLEPA+zwD7Hyz0zQX0iLFfL7nQpXVYUwj4FWto1r9iF1MAG83yVgP1uq42dD93mSVhRMLuLa0MdIJJayNu56PcbUISpPeShmNUZ/H8aRRg95Pd5RMy7Ua1YBwAIe5B/0al6hvlu00c3zanM0Ao3XDYt6eaNAFK2vsuFUrKDescetSZ2NoiFN+M+vjfD1vTMkAw4vJes22yJwEurA52ytn3I81eioaz1ZPDZXNzp2nQNL40PF8ot7MIb2XeSvvcvAVwUCwpRHFcLtp2CPkSQg8VYaAHuJG32TcrujE6iaGaweemTph7LdiqRt38c6QwH0tpVeENkqafZHCudQWoUkbsOskpOvraa3mK3K9VtvMZlBRL8xWN4ZequOKqtYDbsA8C9o9Y/csDDDdLpc7g1gA1YDJU3+71kb4qMw3Hc3a+Bm5Yxdz3a63m7O5zT2b0sT2dnnp5CY2FxlPLYHx4bJ1bwQe01LnZAJ3UkgCYcc9h7WJ2OegzOoB5OvaPKvbW8xZhKu2ufI9tR6OIn0BndSVrThj29OfjSxpAZoxLNNUJHOWpHDWi86yPjCgvdetrYPxeaexYpgB8PzJ6XaXznBHLkeCVsAa/LheEL0hOIqcYlXLaeh4KdHuYDtHGBUrWZg/r+OUFQy2sAOOaEUrb60uW/CuYIN3bKDmWWKZ0QWhGRu6Rxt2LVglGdH2Y8ekPYqkZGAU3TW2XjuzSBdWOeBKAp9gm5rlzKH6XXRn7ExW8cza0cyws1bXC1pf+0NyO1mnvak+j4G7paRTIgVWe2bknCZhY7xMIgnKsDucshE/6aVdeqAC80OobSz0nXA2HK033VVrBhOeOiGvNrwontgt056tgDbkYAh6NS7Clhzio6Q9s7012S+oMZ23Z9o29bNOOusRNehcbpuFzLM70W9KQL0xi3HQ9NhZwIwSpjZKOMZgqdYiptrdjUEkI5kmJyM53tjPuFkzNjPDNpcbqnR6pOiOtxtm9VxLnc048B1f7640V5uM0rLHl1E/6bR7I3ziTIb0PFP7sxIcz8CxvHd6Mnbn+KtCG6rEdO0sfSOcmPUGZHkqSHfDmN7ytdluWjNysptvi1zC4oSWFaatKMnYheHjsdajIiYtd5mb9bBWBgz32MrIVm9Cykyi22pGKEFdh3Nr8/5EwPkwmnhRnmJt3gnnNN5P1hZUk2yxSzv0vD1d2a3nTR7tOplstjJpHj1bUf7cG1CzXbSFPdOghV0tx3V5wdRxnXSAymhizjzF+17LmuAdqNADfkRDg0bXy8QY9GxeZMq4pTlcbRMMS8dkBGL37PeGfsMdT56TxWgDVqCTzJdopg+Vyay9reMOIzBFvwkTzuTJtNERfLfbsRaRvJzMo7w/nW9WeLbKm3jmchk+hEuiJb0lcsWoJ1DF9bCYb3G6+9xdW1AE8e244TZHDWupSt50GaZcbi/m9EbeDae4GnVCrc4+ewM1zFplazzlcaG76qSZj0WLyAzJUW9B53JGBhlbW5NYSyFsll3ahPMsxh4jrLa551GpbRi0VQdL+WyZjTudem3BMgtKhzTGez5Qra3hwoEcPF3ajXFzsxBxxozFprKj7R3wMts7jC0tkuL0ocU1GgL0ilSgwf3mFjf80nkeErazo8sdDKrbNhZD+2Z5xpBqSpNoUULrMbYnTK1FQkZPyNCFy9U2RvXghIRA2mr+GppaPueLxQBCANxoPOkNn+nGXJIe5nUdgcQnskbu9/+62aDlEnDCH0G759I9lHbx1tETdXPpBJU+kd8VNnMD5wKBezHff3v8XqRz6WEv4CtoC+j0q2Sqa9DKcReXoNUQ81s9wV8KA07hJI7n2mnNPkE94H8B3ZQGvlTGDV6cz4bLqYgP4G5kcFctnZhgUqvja4Sf9UfdbVarH3cXmyljLFdnvKBNl/GoHRfaRGFUf+jZQer1pgO4Q5nTbzuM3cJzYzrB5qPjLmQxBe5fai3W1dQYnqcaeG63kBxbiCljxmN6ibmD6XA7D8YO7I8kKlsTHCsjKu9O5VyBiZOemMFdsZTSJLsNrpAFMe+WXNEtRbgDFdnz5KLncbnUgHBV9ev2Xa5uBsOg53fE4WlXNND31pyVgiVmtTmmW7CkRZqZVcqZQXZC0B6EybayIG1lT0rh/d2ZQhvhEAgMnpmFfG53NfRNQil0OIYpm0ntzkrz4uU8YHGY5nreiQ2Ok7t8JmiH3tNkRHsG3Bm61QTjAWNs1C93ZEtNERi7ixRZI5Sz+Z5W2Zxg0y65XJqN+q7rcVtjim0vnllaTTCX3sUucARddoPmyiA6fjdQtsaIpeYzbgt3nuuSytie8T7wcMCYWNwMFH8cTAIJzhOY095KKbRpEwM0GhsEuwF94vf95wd6iwXlSmSQnDPAZVwScZiQmlktttQb+/vVMcaMpnRpgZXInJh0hoA+sLwbAKdNiBtDEVj1VacpeyKmiPJOHo/xnrDCB5hMyx74q3LUwFMEeXRub9hiPWuKA7s1vGhveN1e+WZ7EI4QdpATFVWNRW3Wia1gshqGHUAh/kDFODZCBZtPaU8b+yIYPZzRTJ/6q95qUPbGcil7WkNWB9jAE3dDsAzoqRNhUK4KRRjsZGHZgHtkVWmz+/bALCg4kJTMEs/taa2r9oS326tXvc+3j/gR8mmXrHhyNBTnh5oHqaukENbok8u82n9vNnC0KQ2lvZA82C632PsJ0NKX0DXehvANoaaBs/1+UV8I21pGbiAmk8RMbxHQtupRWdsh2ZpFKludsLwZns7GGNsdYtDn6JVm2S02obSrG82d3G/kZgOuuRKintXWdNa1idQYlZuklScMkybP2Xqtu2G8nq4i5nkZdaAfEWqFEcTB3Kf1id/pjVZao+9FhOxS644r2a3lfCQ4UYtbkDS7aKeMPVuSVjjBTLKzM1tsBqQj0QM/0gjN11qKO5/yi5mPm1M8BgxuTScTQG2/OVAxWlHF9Hk0XraHq4k4wDr8QIB06at5reetKKWc44CDCsBL266LbZ6LKH5umEFnNPAkV3TaO8pqg/VEa+jMmsvxWNxJQ5EDC+9B3m04K4nP502ekxscsILSYiXCT/C7qWwih3ECPF+2ZI8Ju+SA8yZtKWN0sIDsp1NwpfZGDOS13IqL6Ch1Fx09RZEusk2ot02h/g2hHTvW91mXrw/hYTDs0VsbV7b+/Hrgo1eEX8m8u/MNbrYjfbog2+2lE/XeQakXNmr93gioFkVwa91/OLg9LS9H2cbOl7bto9Dnj4Q+XwtwvhwWvWBO+qWsq+NOhMhdRO4icheRu4jcReQu/jHuIv6iu4hcw1/rGvL3Wye+6BtKcHPEfxppAp2wSkaxf5QsAH7Uv1+OOyb+le7jJTL4eJ/Gt7/G6wYgvPFFv8HfvPmuAubDEuNKMMvuW7toopw4lBOHcuJQThzKiUM5cSgnDuXEoZw4lBOHcuJQThzKiUM5cSgnDuXEoZy4PzInjmWYH0uJ+zY08hGa+xEIZa/C8o4Q5RMCKP86gLIiBkIoEUKJEEqEUCKEEiGUCKFECCVCKBFCiRBKhFAihBIhlAihRAglQij/PoQS33/p36dClCjh9OMSTrFgJ7gbuBmt9Qa2Ow6t6Izq8tpbiO1D/PFlDPYjAN6/Ecf9CMQ2q6YOwbUIrkVwLYJrEVyL4FoE1yK4FsG1CK5FcC2CaxFci+BaBNciuBbBtX8fXMsS2GejtR+HQA7tKwRyjhDIPwaBTGyEQCIEEiGQCIFECCRCIBECiRBIhEAiBBIhkAiBRAgkQiARAokQSIRA/p0IJENRn41AonzRz8gXFWzfrkDAf/ZHCK39Y9Ba6zB1CK9FeC3CaxFei/BahNcivBbhtQivRXgtwmsRXovwWoTXIrwW4bUIr/378Fq8jvDa/yReq8Lc2mYShRd7t/KjpbuAFq6J0Ns/Br1No8V+FhF8i+BbBN8i+BbBtwi+RfAtgm8RfIvgWwTfIvgWwbcIvkXwLYJvEXz798G3FMb8RW/8V5gkr5urB5AkjyDJPwiSNKpJRIgkQiQRIokQSYRIIkQSIZIIkUSIJEIkESKJEEmESCJEEiGSCJFEiOTfiEjiKKP0P5lR2nQr+LMBgdWvX78iuPZPgWsXYOL29EWILUJsEWKLEFuE2CLEFiG2CLFFiC1CbBFiixBbhNgixBYhtgixRYjtX4jYEgT72YDtx4GQXTe0EQj5B4KQmzSJVjaCIREMiWBIBEMiGBLBkAiGRDAkgiERDIlgSARDIhgSwZAIhkQwJIIh/1oYslYn/h4YcrTUAW8j9PGPQR/fM18IeETAIwIeEfCIgEcEPCLgEQGPCHhEwCMCHhHwiIBHBDwi4BEBjwh4/DOBR5L+bOARvbD+cS+sv4rLNqIwtM0K/3ydnh8Btr6I5P4EFJakPhmFxR6j2fmyglfBNftInjzR48MtWzsBA8v3V5auZdnhobvRJX0S2wcE3tofBvea72UDBPkiyBdBvgjyRZAvgnwR5IsgXwT5IsgXQb4I8kWQL4J8EeSLIF8E+f6RkC9Z+9Gvvb9HQLGXYE7su2BON3Au8LcLSAq7gqy2uu864VWFwLUs374GtoBGv6xyA1k57uISshpifqsn+EthwCmcxPFcO63ZJ6AH/C+gk9LAl8q4wYvz2XA5FfFBX2Aps9X0dGKCSa2OrxF+1h91t1mt7kotf9UfdWbKGMvVGS9o02U8aseFNlEY1R96dpB6venA7ZeU0287jN3Cc2M6weYjnjKmu8wsYwrcv9RarKupMTxPNfDcbiE5thBTxozH9BJzB9Phdh6MHdgfSVS2JjhWRlTencq54nGO4omZrMqYUppkt8EVsiDm3ZIruqVYdFWR7Hly0fO4XGpAsKr6dfsuVzeDYdDzO+LQPfWn0FpzVgqWmNXmmG7BkhZpZlYpZwbZCUF7ECTbyoK0lT0phfd3ZwpthEMgLnhmFvK53dXQNwml0OEYpmwmtTsrzYuX84DFLQFzpfMzwTi5y2eCdug9TUa0ZwBmsFtNMB4wxgageXuZGi267IXL1BSBqRt1Iqs9zHtufWuEcjbf0yqbE2zaJZdLs1HfdT1ua0yx7cUzS6sJ5tLDXL09xEwh2nYJuuwGzZVBdPxuoGyNEUvNZ9xWhnQmlbE9433g34AxsbgZKP44mAQSnCcwp72VUmjTJgZoNDYIdgP6xO/7zw/0FgvKlcggOWeAy7gk4ss54CGrxZZ6Y3+/OsaY0ZQuLbAOmROTzhDQB5Z3A+CyCXFjKAKbvuo0ZU/EFFHeyeMx3hNW+ACTadkDf1WOGniKII/O7Q1brGdNcWC1hhftDa/bK99sD4IRwg5yoqKqsajNOrEVTFbDsAMoxB+oGMdGqGDzKe1pY18Eo4czmulTf9VbDcreWC5lT2vI6gAbeOJuCBYBPXUiDMpVoQiDnSwsGzIm78DsHNsDs6DgQFIySzy3p7Wu2hPebq9e9T7fPuJHyKddsuLJ0VCcH2oepK6SQlijTy7z+VRJtNnA0aY0lPZC8mC73GLvJUA7X0LHeBtScN1n4Gy/X9QXwraWkRuIyCQx01sEtK16VNZ2SLZmkcpWJyxvhqezMcZ2hxj0OHqlWXaLTSjt6kZzJ/cbudmAK66EqGe1NZ11bSI1RuUmaeUJw6TJc7Ze624Yr6eriHleRh3oRYRaYQRxMPdpfeJ3eqOV1uh7ESG71LrjSnZrOR8JTtTiFiTNLtopY8+WpBVOMJPs7MwWmwHpSPTAjzRC87WW4s6n/GLm4+YUjwGDW9PJBFDbbw5UjFZUMX0ejZft4WoiDrAOPxAgXfpqXut5K0op5zjgoALw0rbrYpvnIoqfG2bQGQ08yRWd9o6y2mA10Ro6s+ZyPBZ30lDkwLJ7kHcbzkri83mT5+QGB2ygtFiJ8BP8biqLyGGcAM+XLdljwi454LxJW8oYHSwf++kUXKm9EQG5jsToxibys/QQ4LoI8p3CSCezRx9LziaSeEfE75tfyng13jfViyrytkHhvv9wuC9K0mXkRKHuo3AfCvehcB8K96FwHwr3oXAfCvehcB8K96FwHwr3oXAfCvehcB8K96Fw398Y7sMJ6gf3lkHhPhTuQ+E+FO5D4T4U7kPhvp8Z7kOvQv74q5Bd3bCvQ133kVEp3NhwqYb9I0SZ4dum75qrakLBH/d4EYY8//0bYqcPw51XUVKy8hDp7wiFfnzQ88ozrb/BG98SCY397K1QOIqBohgoioGiGCiKgaIYKIqBohgoioGiGCiKgaIYKIqBohgoioGiGCiKgf6RMVCSJT48BvpEvYRnPpEoCoqioCgKiqKgKAqKoqAoCoqioL/phrAq/DavvyHAefly6Gd/I9cLL4e+GvD8rhjqR4RE03dwAIqJopgoiomimCiKiaKYKIqJopgoiomimCiKiaKYKIqJopgoiomimCiKif6RMVGCpT58G9gnAkU+UeQTRT5R5BNFPlHk878d+XyHKbyLfL4c47sP3jWjJNBhZKyvh/CFR+yfRpqAT360dBdwsdK/fnfxnVHC7wimMo+8hHPpVcSN+Kgo24sxxfeE366n1nI3sa8f7nBD3w3tJ8OPzNXNLJ9GdMEL53DjIgrTp41bHkJ4OHUfTX667gUN3Bv69Hlb9+iTcfcu2kWtvVvz4XG5Sp4OcTku6g5YFR60ZsPmtD1UDULDLOAaaQP+aNI6xrQZapOOD0wtbZq+XwXywMp/0lxiwEWRe5X5PJlwqLz3P0JegUM8MICpbzV4V5tasQGMcK2WQZDK5YF5wtxJOVFkEc8HxCTSx0vGDCaqvaLHczJO5qW/2itgaJYqJ6CF+1ZLhIZvAxwAxgYtHJwABp7vHS7oOOwdMKu1YaXV3tBLzcrZE4Dh9iVhDBwM3JOFeS4Jc+A0iKUimKRS5I7scTvgfOSyW9/JLrZTygiYoCiXzw6VI3nQyTsZlFN/oPG5dFIs4FJ1Q6DrA7bQivoOOFT03lmTiu4M3O/ipT2lsfnMScH93kW7wPwqnhn4YAz+1nB56Kwx82lna80GrORKZxqAcb7XMbp2xKCZf6dTROBptzg/0ySHI206f6cjx5aTtp9rI3YExgT63/EgR2muXDl4phALYNaXwEkqJi12awhnJ3jcWm4r56nF5sAZVpURrwATDVyQ4dYknP39wDHsrfwM9GlpAGdtNAb0gbzSoGN9OmB6ggWcoDkNfoEjNCBltdlUVOA+eMAdUjla8Zy8J4yLoXrZHng+OUmBG4BdtLe6ak/l3mwPuhVnJ20CHBJgakVgtwnMOdCQ0V90BiNKwYDD7vniUBgTQ8HcO2+qRMgYdH1WRE/gKEXtNHvAuTy2p73oDF60p77Z3vbCabrmRcijDbbix/Fq2NrXu1jwqOD61UJqkkFJN12IHfX9UB5ATBbqiA7wBMZDaNz7p4UZ2dyZ6kJ199a/AZzE3riqTxtmPoJarNE8xLBjdy4OBEEcdGSZ44Eqc3fmAMO4biS4/aGZczzv8IzACX7Bznf1HDbId4ZjWkxWHQcs8YE5fLSW/lbz/oIhz3x/Yya2HSJ7/dPtNf0322tuUNlrvz/F3IqH/VMeDRQHX6uFlVnmZvs8kUHPmGvV/XElKQ3F8sCp0dpxBcWJS9pRcp5v8UUk8ZyU2byFE+rYW1dtiH5TXY2yQdBo/CzJaES+r8cbSAlxF+sw1ocE5McF5CalD8eIfTbf5cG/75Al/G1ZeiMxEDmyyJFFjuxHO7KK4BCKKJLKeI7L4wkPHU8Zk0hwDBxPE1OwedEbS9SgFN/lyJ7a87g32/tBRxbrCXNsoJo4cGR3Q+D1AcezHHgmOB4AvhyQQ0+iB96yQjXf4cie21PfbO9nObIwQrQeRzBdlJNPjqwSaoSxhwq3l/EG2nASm6oM7NGlPf3Pee55HWLwYhfzxcFkSBFBxxk6sjzkNrn8zD3LgsANec+p++AjGjLPUrBqY7lqFI7KzPURJQSwG9y8v2r4PVEQBOxdYaOf4xn9ODZmJA89AS6OfZg8DoyoudRDx34K7RzawUfPJK68BALaLFBeJWWP9jnZwiEde5kGPjjDT7cdDTi8D98Xbe0EtHBRRIpfyEawa9lRYKdJAaocr+Iktr+n2BcQx/ODMwLLjkVHV+SyTN8PmnBOTcOA7f6BMHK7a9i+f3x+dQzcAWt/z8yv687MXyVrJ0j156KvbeSn2mEIup8diHFHHdty7NHh9PzVQuK5lD+XdiPoPlTk8uw0LUaVhyDoWRpdE3OzslNzeTgBBE2K2eXJHJxgX+njqQDph53OisPZvquwf1fzcTdF9/Nxzsa/uO8RcQ+39qF7dp5Hkr6eRpJiv9aZ61Y2UZaY9uHG8yzdt0W83VYKPE07vWurmvHTqL6fCep3TCDugLdqpjb0W0M79d1Neil/ezn6ZxS7pl05gxCY/veOczZLPYaHVmRmwd7tfUPGDKg+bKtrHAsWru839t4raJG0qx/IP2kSreyLKyRDsiQYJJ/sm3jEZy+I67s45nADjV3PFoXfCzCOP5Bg5mdJMPtJEnwSWuzbhPZa8nduWrXxlarXD+ewGfwrhjGH83M78KS4OOnbiQuIWKUQfIs+gGsyKJz7ov8Bj1Se8vTqqRb4NQNLc0c96sW94L0lOh+uX6gbLiPrGCDI+eemwfeqGupGbVHEq82+oHW4JNGLi2rHbxx8eTDs9VMp7Ibp9y2+U6XBZOcI2vNzdaBGlnJk2bDG/wM= -------------------------------------------------------------------------------- /30_PLACE/board_template.brd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | Discrete logic components 66 | 67 | 68 | SOT23-3 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | SOIC-8 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | SOD-323 Diode 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | SOD-123 Diode 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | Pin Header 165 | 166 | >VALUE 167 | 168 | 169 | 170 | 0402 SMD Resistor 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | SC70-6 package, 0.65 mm pitch 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | SOT-23-6 package, 0.95 mm pitch 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 0402 SMD Capacitor 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 0603 LED 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | Please make sure your boards conform to these design rules. 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | 433 | 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