├── .cargo └── config.toml ├── .github ├── renovate.json └── workflows │ ├── ci.yml │ └── update-yosys.yml ├── .gitignore ├── .gitmodules ├── .readthedocs.yaml ├── CHANGELOG.md ├── Cargo.lock ├── Cargo.toml ├── LICENSE.md ├── README.md ├── ci └── oss-cad-suite-version ├── cliff.toml ├── doc ├── .gitignore ├── Transparent.png ├── White Background Ver.png ├── _static │ └── blockdiag.png ├── blockdiag.odg ├── blockdiag.png ├── changes.md ├── conf.py ├── development │ ├── guidelines.md │ ├── internals.md │ ├── microcode.md │ ├── overview.md │ ├── support-code.md │ └── testing.md ├── index.md ├── todo.md └── usage │ ├── installation.md │ ├── quickstart.md │ └── reference.md ├── dodo.py ├── examples └── attosoc.py ├── pdm.lock ├── pyproject.toml ├── sentinel-rt ├── Cargo.toml ├── examples │ ├── attosoc.rs │ └── device.x └── src │ └── lib.rs ├── src └── sentinel │ ├── __init__.py │ ├── align.py │ ├── alu.py │ ├── control.py │ ├── csr.py │ ├── datapath.py │ ├── decode.py │ ├── exception.py │ ├── formal.py │ ├── gen.py │ ├── insn.py │ ├── microcode.asm │ ├── top.py │ ├── ucodefields.py │ └── ucoderom.py └── tests ├── __init__.py ├── conftest.py ├── formal ├── README.md ├── checks.cfg ├── disasm.py └── wrapper.sv ├── riscof ├── .gitignore ├── README.md ├── bin │ └── riscv_sim_RV32.gz ├── config.ini ├── sail_cSim │ ├── __init__.py │ ├── env │ │ ├── link.ld │ │ └── model_test.h │ └── riscof_sail_cSim.py └── sentinel │ ├── env │ ├── link.ld │ └── model_test.h │ ├── riscof_sentinel.py │ ├── sentinel_isa.yaml │ └── sentinel_platform.yaml ├── sim ├── conftest.py ├── test_soc.py ├── test_top.py ├── test_ucode.py ├── test_witness.py └── witness │ └── csrrc_bad_rd.yw └── upstream ├── README.md ├── binaries ├── .gitignore ├── add ├── add.dump ├── addi ├── addi.dump ├── and ├── and.dump ├── andi ├── andi.dump ├── auipc ├── auipc.dump ├── beq ├── beq.dump ├── bge ├── bge.dump ├── bgeu ├── bgeu.dump ├── blt ├── blt.dump ├── bltu ├── bltu.dump ├── bne ├── bne.dump ├── csr ├── csr.dump ├── fence_i ├── fence_i.dump ├── illegal ├── illegal.dump ├── jal ├── jal.dump ├── jalr ├── jalr.dump ├── lb ├── lb.dump ├── lbu ├── lbu.dump ├── lh ├── lh-misaligned ├── lh-misaligned.dump ├── lh.dump ├── lhu ├── lhu.dump ├── lui ├── lui.dump ├── lw ├── lw-misaligned ├── lw-misaligned.dump ├── lw.dump ├── ma_addr ├── ma_addr.dump ├── ma_data ├── ma_data.dump ├── ma_fetch ├── ma_fetch.dump ├── mcsr ├── mcsr.dump ├── or ├── or.dump ├── ori ├── ori.dump ├── sb ├── sb.dump ├── sbreak ├── sbreak.dump ├── scall ├── scall.dump ├── sh ├── sh-misaligned ├── sh-misaligned.dump ├── sh.dump ├── shamt ├── shamt.dump ├── simple ├── simple.dump ├── sll ├── sll.dump ├── slli ├── slli.dump ├── slt ├── slt.dump ├── slti ├── slti.dump ├── sltiu ├── sltiu.dump ├── sltu ├── sltu.dump ├── sra ├── sra.dump ├── srai ├── srai.dump ├── srl ├── srl.dump ├── srli ├── srli.dump ├── sub ├── sub.dump ├── sw ├── sw-misaligned ├── sw-misaligned.dump ├── sw.dump ├── xor ├── xor.dump ├── xori ├── xori.dump ├── zicntr └── zicntr.dump ├── link.ld ├── riscv_test.h └── test_upstream.py /.cargo/config.toml: -------------------------------------------------------------------------------- 1 | [build] 2 | target="riscv32i-unknown-none-elf" 3 | 4 | [target.riscv32i-unknown-none-elf] 5 | rustflags = [ 6 | "-C", "link-arg=--threads=1", # --threads=1 fixes Windows issue: https://github.com/rust-lang/rust/issues/115985 7 | "-C", "link-arg=-Tsentinel-rt/examples/device.x" 8 | ] 9 | -------------------------------------------------------------------------------- /.github/renovate.json: -------------------------------------------------------------------------------- 1 | { 2 | "$schema": "https://docs.renovatebot.com/renovate-schema.json", 3 | "extends": [ 4 | "config:recommended", 5 | "schedule:weekly", 6 | "group:all", 7 | ":approveMajorUpdates" 8 | ], 9 | "baseBranches": ["main", "next"] 10 | } 11 | -------------------------------------------------------------------------------- /.github/workflows/update-yosys.yml: -------------------------------------------------------------------------------- 1 | on: 2 | workflow_dispatch: 3 | schedule: 4 | - cron: '0 5 1 * *' 5 | 6 | name: Update Yosys (and OSS Cad Suite) 7 | 8 | # https://github.com/peter-evans/create-pull-request/blob/main/docs/concepts-guidelines.md#workarounds-to-trigger-further-workflow-runs 9 | jobs: 10 | update: 11 | name: Update OSS Cad Suite Version 12 | strategy: 13 | matrix: 14 | branch: [main, next] 15 | os: [ubuntu-latest] 16 | runs-on: ${{ matrix.os }} 17 | 18 | steps: 19 | - uses: actions/checkout@v4 20 | with: 21 | ref: ${{ matrix.branch }} 22 | 23 | # Yesterday, because CAD suite versions are made at the end of the 24 | # night. 25 | - name: Update OSS CAD Suite version file (and save new value) 26 | run: | 27 | date -d today +%Y-%m-%d > ci/oss-cad-suite-version 28 | echo >> $GITHUB_ENV OSS_CAD_SUITE_DATE=$(cat ci/oss-cad-suite-version) 29 | if [ ${{ github.event_name }} = "workflow_dispatch" ]; then 30 | echo >> $GITHUB_ENV PR_REASON="Manual update" 31 | else 32 | echo >> $GITHUB_ENV PR_REASON="Monthly update" 33 | fi 34 | 35 | - name: Create Pull Request 36 | id: cpr 37 | uses: peter-evans/create-pull-request@v6 38 | with: 39 | token: ${{ secrets.PAT }} 40 | commit-message: Update OSS CAD Suite version to ${{ env.OSS_CAD_SUITE_DATE }}. 41 | committer: GitHub 42 | author: ${{ github.actor }} <${{ github.actor }}@users.noreply.github.com> 43 | signoff: false 44 | branch: update-yosys-${{ env.OSS_CAD_SUITE_DATE }}-${{ matrix.branch }} 45 | delete-branch: true 46 | base: ${{ matrix.branch }} 47 | title: Update OSS CAD Suite version to ${{ env.OSS_CAD_SUITE_DATE }}. 48 | body: | 49 | ${{ env.PR_REASON }}; auto-generated by [create-pull-request][1]. 50 | 51 | [1]: https://github.com/peter-evans/create-pull-request 52 | labels: | 53 | automated pr 54 | assignees: cr1901 55 | draft: false 56 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Python 2 | __pycache__/ 3 | *.egg-info 4 | /dist 5 | 6 | # pdm 7 | /.pdm-plugins 8 | /.pdm-python 9 | /.venv 10 | # Part of dynamic version generation. 11 | /src/sentinel/version.txt 12 | 13 | # pytest 14 | /.pytest_cache 15 | 16 | # Amaranth 17 | /build* 18 | 19 | # GtkWave 20 | *.vcd 21 | *.gtkw 22 | 23 | # Doit 24 | .doit.db.* 25 | 26 | # logluts 27 | /LUTs.csv 28 | 29 | # m5meta 30 | *.asm*.fdef 31 | *.asm*.hex 32 | 33 | # Yosys 34 | /abc.history 35 | 36 | # RVFormal disassembled counterexamples 37 | *.s 38 | 39 | # YoWASP setup 40 | .env.toolchain 41 | 42 | # Added by cargo 43 | 44 | /target 45 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "tests/upstream/riscv-tests"] 2 | path = tests/upstream/riscv-tests 3 | url = https://github.com/riscv/riscv-tests 4 | [submodule "tests/formal/riscv-formal"] 5 | path = tests/formal/riscv-formal 6 | url = https://github.com/YosysHQ/riscv-formal 7 | [submodule "tests/riscof/sail-riscv"] 8 | path = tests/riscof/sail-riscv 9 | url = https://github.com/riscv/sail-riscv.git 10 | [submodule "tests/riscof/riscv-arch-test"] 11 | path = tests/riscof/riscv-arch-test 12 | url = https://github.com/riscv-non-isa/riscv-arch-test 13 | -------------------------------------------------------------------------------- /.readthedocs.yaml: -------------------------------------------------------------------------------- 1 | # Read the Docs configuration file for Sphinx projects 2 | # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details 3 | 4 | # Required 5 | version: 2 6 | 7 | # Set the OS, Python version and other tools you might need 8 | build: 9 | os: ubuntu-22.04 10 | tools: 11 | python: "3.12" 12 | # You can also specify other tool versions: 13 | # nodejs: "20" 14 | # rust: "1.70" 15 | # golang: "1.20" 16 | jobs: 17 | post_checkout: 18 | # Reconstruct tags. 19 | - git fetch --unshallow --tags 20 | post_create_environment: 21 | # Install PDM 22 | - pip install -U pdm 23 | post_install: 24 | # See: 25 | # * https://github.com/readthedocs/readthedocs.org/pull/11152/ 26 | # * https://github.com/pdm-project/pdm/pull/2736/files#diff-03efc769b870804394632e45d7885272b44c16939517fb31c9d7c614d2ffae57 27 | # * and https://docs.readthedocs.io/en/stable/build-customization.html#install-dependencies-with-poetry 28 | # This replaces requirements.txt specified in: https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html 29 | - VIRTUAL_ENV=$READTHEDOCS_VIRTUALENV_PATH pdm install -G doc -G examples 30 | 31 | # Build documentation in the "docs/" directory with Sphinx 32 | sphinx: 33 | configuration: doc/conf.py 34 | # You can configure Sphinx to use a different builder, for instance use the dirhtml builder for simpler URLs 35 | # builder: "dirhtml" 36 | # Fail on all warnings to avoid broken references 37 | # fail_on_warning: true 38 | 39 | # Optionally build your docs in additional formats such as PDF and ePub 40 | # formats: 41 | # - pdf 42 | # - epub 43 | -------------------------------------------------------------------------------- /Cargo.lock: -------------------------------------------------------------------------------- 1 | # This file is automatically @generated by Cargo. 2 | # It is not intended for manual editing. 3 | version = 3 4 | 5 | [[package]] 6 | name = "atoi" 7 | version = "2.0.0" 8 | source = "registry+https://github.com/rust-lang/crates.io-index" 9 | checksum = "f28d99ec8bfea296261ca1af174f24225171fea9664ba9003cbebee704810528" 10 | dependencies = [ 11 | "num-traits", 12 | ] 13 | 14 | [[package]] 15 | name = "autocfg" 16 | version = "1.4.0" 17 | source = "registry+https://github.com/rust-lang/crates.io-index" 18 | checksum = "ace50bade8e6234aa140d9a2f552bbee1db4d353f69b8217bc503490fc1a9f26" 19 | 20 | [[package]] 21 | name = "bitvec" 22 | version = "1.0.1" 23 | source = "registry+https://github.com/rust-lang/crates.io-index" 24 | checksum = "1bc2832c24239b0141d5674bb9174f9d68a8b5b3f2753311927c172ca46f7e9c" 25 | dependencies = [ 26 | "funty", 27 | "radium", 28 | "tap", 29 | "wyz", 30 | ] 31 | 32 | [[package]] 33 | name = "byteorder" 34 | version = "1.5.0" 35 | source = "registry+https://github.com/rust-lang/crates.io-index" 36 | checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b" 37 | 38 | [[package]] 39 | name = "critical-section" 40 | version = "1.1.3" 41 | source = "registry+https://github.com/rust-lang/crates.io-index" 42 | checksum = "f64009896348fc5af4222e9cf7d7d82a95a256c634ebcf61c53e4ea461422242" 43 | 44 | [[package]] 45 | name = "embedded-hal" 46 | version = "1.0.0" 47 | source = "registry+https://github.com/rust-lang/crates.io-index" 48 | checksum = "361a90feb7004eca4019fb28352a9465666b24f840f5c3cddf0ff13920590b89" 49 | 50 | [[package]] 51 | name = "funty" 52 | version = "2.0.0" 53 | source = "registry+https://github.com/rust-lang/crates.io-index" 54 | checksum = "e6d5a32815ae3f33302d95fdcb2ce17862f8c65363dcfd29360480ba1001fc9c" 55 | 56 | [[package]] 57 | name = "hash32" 58 | version = "0.3.1" 59 | source = "registry+https://github.com/rust-lang/crates.io-index" 60 | checksum = "47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606" 61 | dependencies = [ 62 | "byteorder", 63 | ] 64 | 65 | [[package]] 66 | name = "heapless" 67 | version = "0.8.0" 68 | source = "registry+https://github.com/rust-lang/crates.io-index" 69 | checksum = "0bfb9eb618601c89945a70e254898da93b13be0388091d42117462b265bb3fad" 70 | dependencies = [ 71 | "hash32", 72 | "portable-atomic", 73 | "stable_deref_trait", 74 | ] 75 | 76 | [[package]] 77 | name = "num-traits" 78 | version = "0.2.19" 79 | source = "registry+https://github.com/rust-lang/crates.io-index" 80 | checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841" 81 | dependencies = [ 82 | "autocfg", 83 | ] 84 | 85 | [[package]] 86 | name = "once_cell" 87 | version = "1.20.1" 88 | source = "registry+https://github.com/rust-lang/crates.io-index" 89 | checksum = "82881c4be219ab5faaf2ad5e5e5ecdff8c66bd7402ca3160975c93b24961afd1" 90 | 91 | [[package]] 92 | name = "panic-halt" 93 | version = "0.2.0" 94 | source = "registry+https://github.com/rust-lang/crates.io-index" 95 | checksum = "de96540e0ebde571dc55c73d60ef407c653844e6f9a1e2fdbd40c07b9252d812" 96 | 97 | [[package]] 98 | name = "portable-atomic" 99 | version = "1.9.0" 100 | source = "registry+https://github.com/rust-lang/crates.io-index" 101 | checksum = "cc9c68a3f6da06753e9335d63e27f6b9754dd1920d941135b7ea8224f141adb2" 102 | 103 | [[package]] 104 | name = "proc-macro2" 105 | version = "1.0.86" 106 | source = "registry+https://github.com/rust-lang/crates.io-index" 107 | checksum = "5e719e8df665df0d1c8fbfd238015744736151d4445ec0836b8e628aae103b77" 108 | dependencies = [ 109 | "unicode-ident", 110 | ] 111 | 112 | [[package]] 113 | name = "quote" 114 | version = "1.0.37" 115 | source = "registry+https://github.com/rust-lang/crates.io-index" 116 | checksum = "b5b9d34b8991d19d98081b46eacdd8eb58c6f2b201139f7c5f643cc155a633af" 117 | dependencies = [ 118 | "proc-macro2", 119 | ] 120 | 121 | [[package]] 122 | name = "radium" 123 | version = "0.7.0" 124 | source = "registry+https://github.com/rust-lang/crates.io-index" 125 | checksum = "dc33ff2d4973d518d823d61aa239014831e521c75da58e3df4840d3f47749d09" 126 | 127 | [[package]] 128 | name = "riscv" 129 | version = "0.11.1" 130 | source = "registry+https://github.com/rust-lang/crates.io-index" 131 | checksum = "2f5c1b8bf41ea746266cdee443d1d1e9125c86ce1447e1a2615abd34330d33a9" 132 | dependencies = [ 133 | "critical-section", 134 | "embedded-hal", 135 | ] 136 | 137 | [[package]] 138 | name = "riscv-rt" 139 | version = "0.12.2" 140 | source = "registry+https://github.com/rust-lang/crates.io-index" 141 | checksum = "c0d35e32cf1383183e8885d8a9aa4402a087fd094dc34c2cb6df6687d0229dfe" 142 | dependencies = [ 143 | "riscv", 144 | "riscv-rt-macros", 145 | ] 146 | 147 | [[package]] 148 | name = "riscv-rt-macros" 149 | version = "0.2.1" 150 | source = "registry+https://github.com/rust-lang/crates.io-index" 151 | checksum = "a8d100d466dbb76681ef6a9386f3da9abc570d57394e86da0ba5af8c4408486d" 152 | dependencies = [ 153 | "proc-macro2", 154 | "quote", 155 | "syn", 156 | ] 157 | 158 | [[package]] 159 | name = "sentinel-rt" 160 | version = "0.1.0" 161 | dependencies = [ 162 | "atoi", 163 | "bitvec", 164 | "critical-section", 165 | "heapless", 166 | "once_cell", 167 | "panic-halt", 168 | "portable-atomic", 169 | "riscv", 170 | "riscv-rt", 171 | ] 172 | 173 | [[package]] 174 | name = "stable_deref_trait" 175 | version = "1.2.0" 176 | source = "registry+https://github.com/rust-lang/crates.io-index" 177 | checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3" 178 | 179 | [[package]] 180 | name = "syn" 181 | version = "1.0.109" 182 | source = "registry+https://github.com/rust-lang/crates.io-index" 183 | checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237" 184 | dependencies = [ 185 | "proc-macro2", 186 | "quote", 187 | "unicode-ident", 188 | ] 189 | 190 | [[package]] 191 | name = "tap" 192 | version = "1.0.1" 193 | source = "registry+https://github.com/rust-lang/crates.io-index" 194 | checksum = "55937e1799185b12863d447f42597ed69d9928686b8d88a1df17376a097d8369" 195 | 196 | [[package]] 197 | name = "unicode-ident" 198 | version = "1.0.13" 199 | source = "registry+https://github.com/rust-lang/crates.io-index" 200 | checksum = "e91b56cd4cadaeb79bbf1a5645f6b4f8dc5bde8834ad5894a8db35fda9efa1fe" 201 | 202 | [[package]] 203 | name = "wyz" 204 | version = "0.5.1" 205 | source = "registry+https://github.com/rust-lang/crates.io-index" 206 | checksum = "05f360fc0b24296329c78fda852a1e9ae82de9cf7b27dae4b7f62f118f77b9ed" 207 | dependencies = [ 208 | "tap", 209 | ] 210 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [workspace] 2 | resolver = "2" 3 | members = ["sentinel-rt"] 4 | 5 | [workspace.lints.rust] 6 | missing_docs = "warn" 7 | 8 | [workspace.lints.clippy] 9 | pedantic = { level = "warn", priority = -1} 10 | # { level="warn", doc-valid-idents = ["SoC", "AttoSoC", ".."] } unimplemented: https://github.com/rust-lang/cargo/issues/12917#issuecomment-1795069197 11 | doc_markdown = "allow" 12 | 13 | [workspace.lints.rustdoc] 14 | broken-intra-doc-links = "deny" 15 | 16 | [profile.release] 17 | lto = "fat" 18 | codegen-units = 1 19 | opt-level = "z" 20 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | BSD 2-Clause License 2 | 3 | Copyright (c) 2023, William D. Jones 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 19 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |

2 | Sentinel Logo. A lighthouse is shining its light on a PCB and computer 4 | chip. The silicon die of the computer chip is visible. The text "Sentinel" 5 | in a black and gray gradient stretches in parallel with the lighthouse's beam. 6 | The text covers the base of the lighthouse and is below the chip. 7 |

8 | 9 |

10 | Logo by Tokino Kei. 11 |

12 | 13 | [![Documentation Status](https://readthedocs.org/projects/sentinel-cpu/badge/?version=latest)](https://sentinel-cpu.readthedocs.io/en/latest/?badge=latest) 14 | [![main](https://github.com/cr1901/sentinel/actions/workflows/ci.yml/badge.svg?branch=main)](https://github.com/cr1901/sentinel/actions/workflows/ci.yml) 15 | [![next](https://github.com/cr1901/sentinel/actions/workflows/ci.yml/badge.svg?branch=next)](https://github.com/cr1901/sentinel/actions/workflows/ci.yml) 16 | 17 | # `sentinel` 18 | 19 | Sentinel is a small RISC-V CPU (`RV32I_Zicsr`) written in [Amaranth](https://amaranth-lang.org/). 20 | It implements the Machine Mode privileged spec, and is designed to fit into 21 | ~1000 4-input LUTs or less on an FPGA. It is a good candidate for control tasks 22 | where a programmable state machine or custom size-tailored core would otherwise 23 | be used. 24 | 25 | Unlike most RISC-V implementations, Sentinel is [microcoded](https://en.wikipedia.org/wiki/Microcode), 26 | not pipelined. Instructions require multiple clock cycles to execute. Sentinel 27 | is therefore not necessarily a good fit for applications where high throughput/ 28 | IPC is required. Short version: minimum of 4 CPI for basic arithmetic, 29 | maximum of 69 for a 31-bit shift (_yes, shift instructions need work_). 30 | 31 | Sentinel has been tested against RISC-V Formal and the RISCOF frameworks, and 32 | passes both. Once I have added [a few extra tests](https://github.com/YosysHQ/riscv-formal/blob/a5443540f965cc948c5cf63321c405474f34ced3/docs/procedure.md#other-checks), 33 | the core can be considered correct with respect to the RISC-V Formal model. 34 | The core is also _probably_ correct with respect to the SAIL golden model. 35 | 36 | ## Why The Name `sentinel`? 37 | 38 | I've like the way the word "sentinel" sounds ever since I first learned of the 39 | word, either from the title of [a book on NJ lighthouses](http://www.down-the-shore.com/sentinl.html), 40 | or on an [enemy](https://shining.fandom.com/wiki/Sentinel_(Shining_in_the_Darkness)) 41 | from an [old Sega Genesis RPG](https://en.wikipedia.org/wiki/Shining_in_the_Darkness). 42 | The term has always stuck with me since then, albeit in a much more positive 43 | light than "the soldier golems of the forces of Darkness" :). Since "sentinel" 44 | means "one who stands watch", I think it's an apt name for a CPU intended to 45 | watch over the rest of your silicon, but otherwise stay out of the way. Also, 46 | since lighthouses are indeed "Sentinels Of The Shore", I wanted to shoehorn a 47 | lighthouse into the logo :). 48 | 49 | ## Quick Quick Start 50 | 51 | The absolute fastest way to get started is to check out the source code, 52 | install `pdm`, use `pdm` to create a virtual environment with appropriate 53 | tools, and generate an `.env.toolchain` file that `pdm` uses to set some 54 | environment variables for Amaranth: 55 | 56 | ``` 57 | pipx install pdm 58 | git clone https://github.com/cr1901/sentinel.git 59 | cd sentinel 60 | pdm venv create -n quick-quickstart 61 | pdm install --venv quick-quickstart -G examples -G yowasp 62 | pdm run use-yowasp 63 | ``` 64 | 65 | Use `pip` or `pipx` to install `pdm` depending on your Python install's 66 | [recommendation](https://packaging.python.org/en/latest/specifications/externally-managed-environments/#guide-users-towards-virtual-environments). 67 | 68 | Then, to generate Verilog core with a Wishbone Classic bus, and `clk`, 69 | `rst`, and `irq` input pins, run: 70 | 71 | ``` 72 | pdm run --venv quick-quickstart gen 73 | ``` 74 | 75 | To create a demo bitstream that counts primes and sets LEDs accordingly (for the 76 | [iCE40-HX8K Breakout Board](https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx)), 77 | run: 78 | 79 | ``` 80 | pdm run --venv quick-quickstart demo -i csr -p ice40_hx8k_b_evn 81 | ``` 82 | 83 | The output will be available in `build/` at the source code root. 84 | 85 | If you have [Rust](https://www.rust-lang.org/) [installed](https://rustup.rs/) 86 | with the `riscv32i-unknown-none-elf` [target](https://rust-lang.github.io/rustup/cross-compilation.html), 87 | you can create a [Rule 110](https://en.wikipedia.org/wiki/Rule_110) demo that 88 | prints neat patterns to the serial port: 89 | 90 | ``` 91 | pdm run --venv quick-quickstart demo-rust -i csr -p ice40_hx8k_b_evn 92 | ``` 93 | 94 | The output will be available in `build-rust/` at the source code root. 95 | 96 | Run `pdm run --venv quick-quickstart gen -h` and 97 | `pdm run --venv quick-quickstart demo -h` for help, and experiment! 98 | 99 | When you're done, unset the environment variables and optionally destroy the 100 | virtual environment, as we will not be using it again: 101 | 102 | ``` 103 | pdm run use-local 104 | pdm venv remove quick-quickstart 105 | ``` 106 | 107 | Note that **extra dependencies are required for development**. See the next 108 | section. 109 | 110 | ## Quick Doc Links 111 | 112 | * To get started with an environment suitable for development, consult the 113 | [Installation](https://sentinel-cpu.readthedocs.io/en/latest/usage/installation.html) doc page. 114 | * For information on the source code development environment, click 115 | [here](https://sentinel-cpu.readthedocs.io/en/latest/development/overview.html). 116 | * Source code guidelines are found on the 117 | [Development Guidelines](https://sentinel-cpu.readthedocs.io/en/latest/development/guidelines.html) 118 | page. 119 | * For other use cases, consult the [Quickstart](https://sentinel-cpu.readthedocs.io/en/latest/usage/quickstart.html) 120 | page. Note that they are a little less quick than the [Quick Quick Start](#quick-quick-start) :). 121 | * Sentinel has multiple test suites. External submodules [have](./tests/formal/README.md) 122 | [their](./tests/upstream/README.md) [own](./tests/riscof/README.md) 123 | `README.md`s for context and quick instructions. The [Testing](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html) 124 | page and subpages give further instructions and information. 125 | * The Public API has its [own page](https://sentinel-cpu.readthedocs.io/en/latest/usage/reference.html). 126 | * Internal Amaranth [Components](https://amaranth-lang.org/docs/amaranth/latest/stdlib/wiring.html#amaranth.lib.wiring.Component) 127 | are documented on the [Internals](https://sentinel-cpu.readthedocs.io/en/latest/development/internals.html) 128 | page. 129 | * A copy of the below block diagram, detailed instruction cycle counts, and 130 | implemented CSRs are also on the [Internals](https://sentinel-cpu.readthedocs.io/en/latest/development/internals.html) 131 | page. 132 | * Microcode information has its [own page](https://sentinel-cpu.readthedocs.io/en/latest/development/microcode.html). 133 | 134 | ## Block Diagram 135 | 136 | ![Simplified block diagram of Sentinel. Black arrows are physical connections. 137 | Blue arrows represent microcode ROM outputs to Sentinel components, including 138 | feedback into the microcode ROM as inputs. Purple arrows represent microcode 139 | ROM inputs from the other components.](doc/blockdiag.png) 140 | -------------------------------------------------------------------------------- /ci/oss-cad-suite-version: -------------------------------------------------------------------------------- 1 | 2025-05-01 2 | -------------------------------------------------------------------------------- /cliff.toml: -------------------------------------------------------------------------------- 1 | # git-cliff ~ configuration file 2 | # https://git-cliff.org/docs/configuration 3 | 4 | # Adapted from: https://github.com/orhun/git-cliff/blob/main/examples/github-keepachangelog.toml 5 | # This is not a science, and I don't directly use commits to generate a 6 | # CHANGELOG.md. This is simply meant to help me organize commits neatly to make 7 | # the "real" CHANGELOG.md. 8 | # 9 | # If tags for previous releases exist, initial generation is done with "git-cliff". 10 | # All other usage will be done with "git-cliff --unreleased --tag [tag]". 11 | 12 | [changelog] 13 | # changelog header 14 | header = """ 15 | # Changelog\n 16 | All notable changes to this project will be documented in this file. 17 | 18 | The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), 19 | and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).\n 20 | """ 21 | # template for the changelog body 22 | # https://keats.github.io/tera/docs/#introduction 23 | body = """ 24 | {%- macro remote_url() -%} 25 | https://github.com/{{ remote.github.owner }}/{{ remote.github.repo }} 26 | {%- endmacro -%} 27 | 28 | {% if version -%} 29 | ## [{{ version | trim_start_matches(pat="v") }}] - {{ timestamp | date(format="%Y-%m-%d") }} 30 | {% else -%} 31 | ## [Unreleased] 32 | {% endif -%} 33 | 34 | {% for group, commits in commits | group_by(attribute="group") %} 35 | ### {{ group | upper_first }} 36 | {%- for commit in commits %} 37 | - {{ commit.message | upper_first | trim }} 38 | {% endfor %} 39 | {% endfor %}\n 40 | """ 41 | # template for the changelog footer 42 | footer = """ 43 | {%- macro remote_url() -%} 44 | https://github.com/{{ remote.github.owner }}/{{ remote.github.repo }} 45 | {%- endmacro -%} 46 | 47 | {% for release in releases -%} 48 | {% if release.version -%} 49 | {% if loop.index0 == 0 -%} 50 | [Unreleased]: {{ self::remote_url() }}/compare/{{ release.version }}..HEAD 51 | {% endif -%} 52 | {% if release.previous.version -%} 53 | [{{ release.version | trim_start_matches(pat="v") }}]: \ 54 | {{ self::remote_url() }}/compare/{{ release.previous.version }}..{{ release.version }} 55 | {% endif -%} 56 | {% if loop.last and not release.previous.version -%} 57 | [{{ release.version | trim_start_matches(pat="v") }}]: \ 58 | {{ self::remote_url() }}/releases/tag/{{ release.version }} 59 | {% endif -%} 60 | {% else -%} 61 | {% if loop.index0 == 0 -%} 62 | [Unreleased]: {{ self::remote_url() }}/compare/{{ release.previous.version }}..next 63 | {% else -%} 64 | {{ throw(message="No release version found. Run 'git cliff --unreleased --tag [tag]'") }} 65 | {% endif -%} 66 | {% endif -%} 67 | {% endfor %} 68 | 69 | """ 70 | # remove the leading and trailing whitespace from the templates 71 | trim = true 72 | 73 | [git] 74 | # parse the commits based on https://www.conventionalcommits.org 75 | conventional_commits = false 76 | # filter out the commits that are not conventional 77 | filter_unconventional = false 78 | # process each line of a commit as an individual commit 79 | split_commits = false 80 | # regex for preprocessing the commit messages 81 | commit_preprocessors = [ 82 | # remove issue numbers from commits 83 | { pattern = '\((\w+\s)?#([0-9]+)\)', replace = "" }, 84 | ] 85 | # regex for parsing and grouping commits 86 | commit_parsers = [ 87 | { message = "^.*([Cc]argo).*(fmt|fix|clippy)", skip = true }, 88 | { message = "^.*([Uu]pdate).*(CHANGELOG|README)", skip = true }, 89 | { message = "^Merge", skip = true }, 90 | { message = "^Revert", group = "Removed" }, 91 | { message = "^.*([Aa]dd|[Ii]mplement)", group = "Added" }, 92 | { message = "^.*([Ff]ix)", group = "Fixed" }, 93 | { message = "^.*([Rr]emove|[Rr]evert|[Dd]elete)", group = "Removed" }, 94 | { message = "^.*([Dd]eprecate)", group = "Deprecate" }, 95 | { message = "^.*", group = "Changed" }, 96 | ] 97 | # protect breaking changes from being skipped due to matching a skipping commit_parser 98 | protect_breaking_commits = false 99 | # filter out the commits that are not matched by commit parsers 100 | filter_commits = false 101 | # regex for matching git tags 102 | tag_pattern = "v[0-9].*" 103 | # regex for skipping tags 104 | skip_tags = "" 105 | # regex for ignoring tags 106 | ignore_tags = "" 107 | # sort the tags topologically 108 | topo_order = false 109 | # sort the commits inside sections by oldest/newest order 110 | sort_commits = "newest" 111 | 112 | [remote.github] 113 | owner = "cr1901" 114 | repo = "sentinel" 115 | -------------------------------------------------------------------------------- /doc/.gitignore: -------------------------------------------------------------------------------- 1 | # LibreOffice lockfiles 2 | .~lock.* 3 | 4 | # Sphinx 5 | _build/ 6 | _linkcheck/ 7 | -------------------------------------------------------------------------------- /doc/Transparent.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/doc/Transparent.png -------------------------------------------------------------------------------- /doc/White Background Ver.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/doc/White Background Ver.png -------------------------------------------------------------------------------- /doc/_static/blockdiag.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/doc/_static/blockdiag.png -------------------------------------------------------------------------------- /doc/blockdiag.odg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/doc/blockdiag.odg -------------------------------------------------------------------------------- /doc/blockdiag.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/doc/blockdiag.png -------------------------------------------------------------------------------- /doc/changes.md: -------------------------------------------------------------------------------- 1 | ```{include} ../CHANGELOG.md 2 | ``` 3 | -------------------------------------------------------------------------------- /doc/conf.py: -------------------------------------------------------------------------------- 1 | # ruff: noqa: D100 2 | # Configuration file for the Sphinx documentation builder. 3 | # 4 | # For the full list of built-in configuration values, see the documentation: 5 | # https://www.sphinx-doc.org/en/master/usage/configuration.html 6 | 7 | # -- Project information ----------------------------------------------------- 8 | # https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information 9 | 10 | import sys 11 | import os 12 | import importlib.metadata 13 | import warnings 14 | from packaging.version import Version 15 | 16 | project = 'sentinel' 17 | copyright = '2024, William D. Jones' 18 | author = 'William D. Jones' 19 | release = '0.1.0' 20 | 21 | # Don't hide DeprecationWarnings: 22 | # https://docs.python.org/3/library/warnings.html#overriding-the-default-filter 23 | warnings.simplefilter("default") 24 | 25 | try: 26 | sent_ver = Version(importlib.metadata.version("sentinel")) 27 | am_ver = Version(importlib.metadata.version("amaranth")) 28 | # riscof_ver = Version(importlib.metadata.version("riscof")) 29 | except importlib.metadata.PackageNotFoundError as e: 30 | msg = "run \"pdm install --dev -G dev -G doc\" before building docs" 31 | raise RuntimeError(msg) from e 32 | 33 | if am_ver.is_devrelease: 34 | # If I get "(exception: '<' not supported between instances of 'dict' and 35 | # 'dict')", it's because of this: 36 | # https://github.com/sphinx-doc/sphinx/issues/11466 37 | # We'll have to remove the docs manually for now... 38 | am_ver = "latest" 39 | else: 40 | am_ver = f"v{am_ver.public}" 41 | 42 | # https://github.com/amaranth-lang/amaranth/commit/e356ee2cac1f4b12339cd1a16f328510e6407b87 43 | version = str(sent_ver).replace(".editable", "") 44 | release = sent_ver.public 45 | author = 'William D. Jones' 46 | 47 | # Won't be picked up otherwise b/c RTD bypasses PDM and uses a different 48 | # working directory? 49 | on_rtd = os.environ.get("READTHEDOCS") == "True" 50 | if on_rtd: 51 | sys.path.append(os.path.abspath('../src')) 52 | sys.path.append(os.path.abspath('..')) 53 | else: 54 | # And yet locally, docs build just without this, but doc-linkck doesn't 55 | # find examples module?! I got nothing... 56 | sys.path.append(os.path.abspath('../src')) 57 | sys.path.append(os.path.abspath('..')) 58 | 59 | # -- General configuration --------------------------------------------------- 60 | # https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration 61 | 62 | extensions = ["myst_parser", 63 | "sphinx.ext.autodoc", 64 | "sphinx.ext.intersphinx", 65 | "sphinx_rtd_theme", 66 | "sphinx.ext.doctest", 67 | "sphinx.ext.napoleon", 68 | "sphinx.ext.todo", 69 | "sphinx_prompt"] 70 | 71 | templates_path = ['_templates'] 72 | exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store'] 73 | 74 | intersphinx_mapping = {'python': ('https://docs.python.org/3', None), 75 | 'amaranth': (f'https://amaranth-lang.org/docs/amaranth/{am_ver}/', None), # noqa: E501 76 | # 'riscof': (f'https://riscof.readthedocs.io/en/{riscof_ver}/', None)} # noqa: E501 77 | 'riscof': ('https://riscof.readthedocs.io/en/stable/', None)} # noqa: E501 78 | autodoc_default_options = {"members": True, 79 | "undoc-members": True, 80 | "member-order": "bysource"} 81 | todo_include_todos = True 82 | napoleon_custom_sections = ["Registers"] 83 | 84 | myst_footnote_transition = False 85 | myst_heading_anchors = 3 86 | myst_enable_extensions = ["deflist"] 87 | 88 | # -- Options for HTML output ------------------------------------------------- 89 | # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output 90 | 91 | html_theme = "sphinx_rtd_theme" 92 | html_static_path = ['_static'] 93 | html_theme_options = { 94 | 'navigation_depth': 5 95 | } 96 | 97 | html_logo = "Transparent.png" 98 | -------------------------------------------------------------------------------- /doc/development/guidelines.md: -------------------------------------------------------------------------------- 1 | # Development Guidelines 2 | 3 | I've developed this coding guidelines for me over the past year (2024). It 4 | took a long time for me to be happy with code style, and the codebase doesn't 5 | consistently follow them yet. What's more, my guidelines are *potentially* 6 | still in flux; I *have* changed my mind about style things like `Component` 7 | variable annotations (forbid => allow) as I write more Amaranth. Bringing 8 | Sentinel up to date with guidelines and/or further refining the below list is a 9 | long term effort. 10 | 11 | With that in mind, I've found the following coding style guidelines useful for 12 | keeping Sentinel managable: 13 | 14 | ## Privacy 15 | 16 | _Technically, all `Component`s except `Top` should be treated as "not likely 17 | to change but still private"._ However, I don't think the majority of objects 18 | in the package beginning with underscores looks nice. The compromise I've been 19 | using is that "non-nested `Component`s should not begin with underscores". 20 | Private top-level objects that _are not_ `Component`s are fine. 21 | 22 | _Actual_ private classes, objects, functions, etc (begin with an underscore) 23 | should have at least a single-line docstring, and more if Ruff complains 24 | (e.g. a "Yields" section). 25 | 26 | ### Public API 27 | 28 | The `Top` and `FormalTop` `Signatures`s are part of the public interface. 29 | However, `Top`'s `rvfi` `Signature` member is private. 30 | 31 | ## Signatures 32 | 33 | ```{todo} 34 | 35 | This section of guidelines is still in flux. The source code does not 36 | necessarily reflect this section's guidelines. 37 | ``` 38 | 39 | `Signature` objects are not publicly exposed, except _maybe_ the top-level 40 | signature in `Top`. Bindings for `Signature` objects are allowed, but 41 | should be private/local to a `Component`. Despite being private, local 42 | `Signature` objects should *not* begin with an underscore if they're shared 43 | between Python modules (to avoid proliferation of a bunch of attributes 44 | beginning with underscores in public interfaces). 45 | 46 | (sig-pov)= 47 | `Signature` objects are _always_ from the point-of-view of transfer 48 | initiator, _even `Signature` objects without bindings_. If a responder 49 | signature is required, generate one using `Signature.flip`. 50 | 51 | ## Variable Annotations 52 | 53 | ### Components And Data Structures 54 | 55 | `Component` class variable annotations _for `Signature`s_ should be used when 56 | possible. There is no way to express "always from initiator point-of-view" in 57 | variable annotations. However, variable annotations for `Signature`s have the 58 | benefit of more compact class `__init__` and documentation. I use the following 59 | rules to limit confusion over directions, and it seems to work fine: 60 | 61 | * In contrast to the {ref}`previous paragraph `, top-level 62 | `In` and `Out` {class}`~amaranth:amaranth.lib.wiring.Flow`s for `Component` 63 | variable annotations are from the point-of-view of the `Component`, even if 64 | `Component` is a responder (`In`) on some of its constituent interfaces. 65 | * _However_, if a `Component` contains {ref}`nested interface members `, 66 | their annotations should have `Signatures` from the transfer initiator 67 | point-of-view, _even `Signature` objects without bindings_. If a responder 68 | `Member` for a nested `Signature` is required, generate one using `In`. 69 | 70 | Note that Parametric `Component`s can't use class variable annotations; use 71 | an "Attributes" section in the `__init__` docstring for these `Components`. 72 | 73 | Likewise, for prefer `Struct`, `Union`, etc over `StructLayout`, `UnionLayout`, 74 | etc. Their variable annotations make them more compact than `Layout`s, and they 75 | can still be used anywhere a `Layout` can. 76 | 77 | ### Class Variables 78 | 79 | All class variable annotations (`enum`s, `Component`s, `Struct`s, etc) should 80 | use [doc comments](https://www.sphinx-doc.org/en/master/usage/extensions/autodoc.html#doc-comments-and-docstrings) 81 | (`#:`). Try to limit class variables to where they have readily-apparent 82 | benefits (e.g. `enum`s, `Component` `Signatures`, `Struct`s, etc). 83 | 84 | When useful for cross-referencing (_on a best-effort basis_), doc comments 85 | for class variables should start with a type (e.g. (`#: type: Docs go here`)). 86 | This is especially useful for `Components`, because Sphinx tends to fail to 87 | generate useful links from `In(MyType)`/`Out(MyType)` annotations by themselves. 88 | 89 | ## Class Nesting 90 | 91 | Mild `class` nesting is allowed at your own discretion. These can either be 92 | private or public member class variables. If I think functionality will be 93 | useful to others, nested classes/vars are public (e.g. `MCause.Cause`). 94 | If I think it's purely an implementation detail that a user shouldn't access, 95 | the nested class is private (e.g. `Insn._CSR` was _previously_ private). 96 | 97 | ## Type Annotations 98 | 99 | Type annotations are very much a work-in-progress (and likely out-of-date). 100 | -------------------------------------------------------------------------------- /doc/development/support-code.md: -------------------------------------------------------------------------------- 1 | # Support Code 2 | 3 | ## `sentinel-rt` 4 | 5 | `sentinel-rt` is an _currently-empty_ Rust support crate. If necessary, it will 6 | contain support routines optimized for the Sentinel RISC-V _implementation_ 7 | that LLVM or Rust wouldn't generally know about. I have three potential use 8 | cases: 9 | 10 | 1. Wrappers over custom opcodes[^1] and the slow shift operators :), 11 | 2. Related to 1., [`compiler-builtins`](https://github.com/rust-lang/compiler-builtins) 12 | specialization if possible[^2]. 13 | 3. Runtime/Machine Mode code that is incompatible with the existing 14 | [`riscv-rt`](https://github.com/rust-embedded/riscv/tree/master/riscv-rt), 15 | _but_ compatible with the RISC-V spec[^3]. 16 | 17 | However, at present, I don't need any special support code, so `sentinel-rt` 18 | is just a reserved crate with example code for demo bitstreams. 19 | 20 | ```{note} 21 | If I expand demos such that multiple linker scripts are required, the examples 22 | _directory_ will become an examples crate. Do not depend on 23 | `sentinel-rt/examples` being stable; the source root is _already_ 24 | a [workspace](https://doc.rust-lang.org/book/ch14-03-cargo-workspaces.html)! 25 | ``` 26 | 27 | ## Verilog Generator 28 | 29 | See {py:mod}`sentinel.gen`. 30 | 31 | ## Examples 32 | 33 | ### AttoSoC 34 | 35 | ```{eval-rst} 36 | .. automodule:: examples.attosoc 37 | :members: 38 | ``` 39 | 40 | ## Footnotes 41 | 42 | [^1]: A `memcpy` instruction is a good candidate for custom microcoded instruction 43 | with speedups. 44 | [^2]: Not clear to me that this _is_ possible! Just something I thought of. 45 | [^3]: The big one here is that RISC-V permits hardcoding `MTVEC`, but last I 46 | checked, this was not supported. This would likely be a size win, but 47 | I don't want to create a fork of `riscv-rt` just for this one edge case, 48 | so I deal. 49 | -------------------------------------------------------------------------------- /doc/index.md: -------------------------------------------------------------------------------- 1 | 5 | 6 | # Welcome to Sentinel's documentation! 7 | 8 | Sentinel is a [microcoded](https://en.wikipedia.org/wiki/Microcode) RISC-V CPU 9 | (`RV32I_Zicsr`) written in [Amaranth](https://amaranth-lang.org/), implementing 10 | the Machine Mode privileged spec. On FPGAs, it is designed to fit into: 11 | 12 | * ~1000 4-input LUTs. 13 | * ~400 FFs or less. 14 | * ≥ 3 256 x 16 bit block RAMs for at least the microcode store (256 x ≥ 15 | 48 bit). 16 | 17 | As is normal for microcoded designs, instructions take [multiple](development/internals.md#instruction-cycle-counts) 18 | clock cycles. The core's size and speed makes it well suited for control tasks 19 | and system initialization, where a programmable state machine or custom 20 | size-tailored core would otherwise be used. In essence, the core "stands watch" 21 | over a more complex design, which is how I came up with the name (in addition 22 | to liking the word "Sentinel" from 23 | [other](https://shining.fandom.com/wiki/Sentinel_(Shining_in_the_Darkness)) 24 | [sources](http://www.down-the-shore.com/sentinl.html) from my childhood). 25 | 26 | Sentinel will eventually be available on [PyPI](https://pypi.org/) under the 27 | package name `sentinel-cpu`. In the interim, use the 28 | [development repo](https://github.com/cr1901/sentinel) instead. 29 | 30 | The nice logo was contributed by the lovely [Tokino Kei](https://tokinokei.carrd.co/) :D. 31 | 32 | ```{toctree} 33 | :maxdepth: 2 34 | :caption: "Contents:" 35 | 36 | usage/installation 37 | usage/quickstart 38 | usage/reference 39 | development/overview 40 | CHANGELOG 41 | TODO List 42 | ``` 43 | 44 | 45 | # Indices and tables 46 | 47 | * [](genindex) 48 | * [](modindex) 49 | * [](search) 50 | -------------------------------------------------------------------------------- /doc/todo.md: -------------------------------------------------------------------------------- 1 | # `sentinel` TODO List 2 | 3 | This page summarizes the documentation that I need to write which hasn't been 4 | yet :). 5 | 6 | ```{todolist} 7 | 8 | ``` 9 | -------------------------------------------------------------------------------- /doc/usage/quickstart.md: -------------------------------------------------------------------------------- 1 | # Quick Start 2 | 3 | From a checkout of Sentinel's source, you have a few options to try out 4 | Sentinel risk free! _The below commands assume you and are running commands at 5 | the source code root, and that you've [installed](installation.md#prerequisites) 6 | `pdm`, `yosys`, and possibly `nextpnr-ice40`_: 7 | 8 | ``` 9 | pipx install pdm 10 | git clone https://github.com/cr1901/sentinel.git 11 | cd sentinel 12 | pdm install -G examples 13 | ``` 14 | 15 | If you don't have an external `yosys` or `nextpnr-ice40`, and don't wish to 16 | install them, you can use the [YoWASP flow](installation.md#yosys-and-foss-toolchains) 17 | for this section instead: 18 | 19 | ``` 20 | pipx install pdm 21 | git clone https://github.com/cr1901/sentinel.git 22 | cd sentinel 23 | pdm install -G examples -G yowasp 24 | pdm run use-yowasp 25 | ``` 26 | 27 | ```{note} 28 | An alternate take on the Quick Start using YoWASP (which will probably 29 | be seen by more people) is detailed in the "Quick Quick Start" section of the 30 | `README.md` at the [repo root](https://github.com/cr1901/sentinel). The 31 | `README.md` demonstrates creating and destroying a [separate virtual environment](https://pdm-project.org/en/latest/usage/venv/) 32 | for using the YoWASP flow. Both sets of commands should have the same results; 33 | I omit `venv` handling here to keep the docs simpler. 34 | ``` 35 | 36 | ## Generate A Verilog Core 37 | 38 | To generate Verilog for a Sentinel CPU with a [Wishbone classic](https://cdn.opencores.org/downloads/wbspec_b4.pdf) 39 | bus and an IRQ line, run: 40 | 41 | ``` 42 | pdm gen -o sentinel.v 43 | ``` 44 | 45 | _Verilog generation only generates a CPU, not a full SoC or design._ You must 46 | integrate the Sentinel source file into an larger external HDL project 47 | (Amaranth, Verilog, or otherwise). 48 | 49 | ## A Full Example SoC In Amaranth 50 | 51 | The {mod}`examples.attosoc` module shows one way to create a simple Sentinel 52 | SoC with a UART, timer, and GPIO. _Examples should not be taken as a canonical 53 | way to create Amaranth SoCs._ They are subject to change as Amaranth matures 54 | (and are also a good way for me to experiment :)). 55 | 56 | The {class}`~examples.attosoc.AttoSoC` `class` constructs the SoC from various 57 | peripheral `class`es contained within {mod}`~examples.attosoc`. Peripherals 58 | come with either a Wishbone bus {ref}`interface ` or 59 | a CSR bus interface from [`amaranth-soc`](https://github.com/amaranth-lang/amaranth-soc) 60 | (bridged to Wishbone). The {func}`~examples.attosoc.main` function provides 61 | an {mod}`python:argparse` command-line entry point, and 62 | {func}`~examples.attosoc.demo` actually {ref}`builds ` 63 | the SoC. 64 | 65 | Right now, {mod}`~examples.attosoc` uses Amaranth to build a SoC bitstream for 66 | several {doc}`platforms `: 67 | 68 | * [Lattice iCEstick](https://www.latticesemi.com/icestick), _if the demo fits!_ 69 | If when running the demo with iCEstick, you see an error like: 70 | 71 | ``` 72 | ERROR: Failed to expand region (0, 0) |_> (13, 17) of 1303 ICESTORM_LCs 73 | ``` 74 | 75 | that means the demo has decided it doesn't want to fit :). See [this issue](https://github.com/cr1901/sentinel/issues/2). 76 | * [iCE40-HX8K Breakout Board](https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx) 77 | * [Arty A7 35T](https://digilent.com/shop/arty-a7-100t-artix-7-fpga-development-board/) 78 | * [Cmod S7](https://digilent.com/shop/cmod-s7-breadboardable-spartan-7-fpga-module/) 79 | * [iCEBreaker v1.0](https://1bitsquared.com/collections/fpga/products/icebreaker) 80 | 81 | The `pdm` [scripts](https://pdm-project.org/latest/usage/scripts/) 82 | `demo` and `demo-rust` are thin wrappers over {func}`~examples.attosoc.main` 83 | Extra arguments can be sent by using `pdm demo [more] [args] [here...]`; be 84 | careful of overriding args hardcoded to be sent by the `pdm` script! 85 | 86 | ### Rust Demo 87 | 88 | If you have a Rust compiler {ref}`installed `, you can create a 89 | demo that prints a [Rule 110](https://en.wikipedia.org/wiki/Rule_110) pattern 90 | to a serial console: 91 | 92 | ``` 93 | pdm demo-rust [args ...] 94 | ``` 95 | 96 | This script compiles a Rule 110 example in the [`sentinel-rt`](../development/support-code.md) 97 | crate and sends the resulting [ELF](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format) 98 | file off to the `demo` function. The output bitstream will be available under 99 | the `build-rust` directory. 100 | 101 | ### Assembly Demo 102 | 103 | If you don't wish to or can't install a Rust compiler, I provide a fallback 104 | firmware written in assembly that requires no external dependencies. 105 | 106 | ``` 107 | pdm demo [args ...] 108 | ``` 109 | 110 | This firmware calculate primes up to 255, and lights up LEDs for each prime 111 | found. The output will be available under the `build` directory. 112 | 113 | ```{todo} 114 | `demo` parameters are only really documented in passing/prose right now, and 115 | not even all of them at that: 116 | 117 | * Punt the remaining params to development sections? 118 | * Prose might be enough? 119 | ``` 120 | 121 | For help on _all_ tweakable parameters, use the `-h` command-line option: 122 | 123 | ``` 124 | pdm gen -h 125 | pdm demo[-rust] -h 126 | ``` 127 | 128 | For use _outside of the source tree_, see the [Reference](./reference.md) 129 | page. 130 | -------------------------------------------------------------------------------- /doc/usage/reference.md: -------------------------------------------------------------------------------- 1 | # User Reference 2 | 3 | The [Quickstart](./quickstart.md) is a good reference for how to use Sentinel 4 | from the source repo. These next two sections discuss usage outside of the 5 | source tree. 6 | 7 | ## Generating Verilog From An Installed Package/As A Dependency 8 | 9 | If using Sentinel as an installed package in another project, the 10 | [Quickstart](./quickstart.md#generate-a-verilog-core) still applies, 11 | except the command is now: 12 | 13 | ``` 14 | [pdm run] python -m sentinel.gen 15 | ``` 16 | 17 | If you're using `pdm` to handle Python dependencies in e.g. a mixed Python/Verilog 18 | project, and Sentinel is a one of those Python dependencies, you may wish 19 | to use [scripts](https://pdm-project.org/latest/usage/scripts/#pdm-scripts) to 20 | provide a shortcut for Verilog generation in your `pyproject.toml` 21 | (_`call = "python -m sentinel.gen"` does not work!_): 22 | 23 | ```toml 24 | [tool.pdm.scripts] 25 | gen = { call = "sentinel.gen:generate", help="generate Sentinel Verilog file" } 26 | ``` 27 | 28 | ## Use In Amaranth Code 29 | 30 | Right now, even from Python, Sentinel consists of rather few tunable knobs. 31 | The only public Sentinel CPU module is the appropriately-named 32 | {py:class}`~sentinel.top.Top`. 33 | 34 | `Top` is an [interface object](https://amaranth-lang.org/rfcs/0002-interfaces.html#interface-definition-library-rfc) 35 | whose {py:class}`~amaranth.lib.wiring.Signature` consists of a [Wishbone](https://cdn.opencores.org/downloads/wbspec_b4.pdf) 36 | Classic bus and an Interrupt ReQuest (IRQ) line. All interface members are 37 | synchronous to the `sync` [clock domain](https://amaranth-lang.org/docs/amaranth/latest/guide.html#control-domains). 38 | Explicit `clk` and `rst` lines are generated for the `sync` domain in generated 39 | Verilog code. 40 | 41 | I expect most users to only need to `import` from `sentinel.top` to create 42 | their SoC: 43 | 44 | ```{testcode} 45 | from amaranth import Elaboratable 46 | from sentinel.top import Top 47 | 48 | class MySoC(Elaboratable): 49 | def __init__(self): 50 | self.cpu = Top() 51 | ... 52 | 53 | def elaborate(self, plat): 54 | m = Module() 55 | m.submodules.cpu = self.cpu 56 | ... 57 | ``` 58 | 59 | Since the Sentinel top-level is only a CPU, not a full computer system, 60 | _the user must provide some sort of memory, and I/O to effectively run 61 | programs_. One common way to do this is to connect Sentinel's Wishbone bus to 62 | a Wishbone address decoder, behind which memory and I/O live. 63 | 64 | See the {class}`~examples.attosoc.AttoSoC` `class`, and the corresponding 65 | [section](./quickstart.md#a-full-example-soc-in-amaranth) in the Quickstart, 66 | for a full working example. 67 | 68 | ## Public API 69 | 70 | ```{eval-rst} 71 | .. automodule:: sentinel 72 | ``` 73 | 74 | ```{eval-rst} 75 | .. automodule:: sentinel.top 76 | :members: 77 | ``` 78 | 79 | ```{eval-rst} 80 | .. automodule:: sentinel.gen 81 | :members: 82 | ``` 83 | -------------------------------------------------------------------------------- /sentinel-rt/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "sentinel-rt" 3 | version = "0.1.0" 4 | edition = "2021" 5 | 6 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 7 | 8 | [dependencies] 9 | riscv = { version = "0.11.1", features = ["critical-section-single-hart"] } 10 | riscv-rt = "0.12.2" 11 | 12 | [dev-dependencies] 13 | atoi = { version = "2.0.0", default-features = false } 14 | bitvec = { version = "1.0.1", default-features = false } 15 | critical-section = { version = "1.1.2", default-features = false } 16 | heapless = { version = "0.8.0", default-features = false, features = ["portable-atomic-unsafe-assume-single-core"] } 17 | once_cell = { version = "1.19.0", default-features = false } 18 | panic-halt = "0.2.0" 19 | portable-atomic = { version = "1.6.0", features = ["unsafe-assume-single-core"] } 20 | 21 | # Required for `cargo fix`. 22 | [lib] 23 | name = "sentinel_rt" 24 | test = false 25 | bench = false 26 | 27 | [lints] 28 | workspace = true 29 | -------------------------------------------------------------------------------- /sentinel-rt/examples/device.x: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | RAM : ORIGIN = 0x00000000, LENGTH = 4K 4 | } 5 | 6 | REGION_ALIAS("REGION_TEXT", RAM); 7 | REGION_ALIAS("REGION_RODATA", RAM); 8 | REGION_ALIAS("REGION_DATA", RAM); 9 | REGION_ALIAS("REGION_BSS", RAM); 10 | REGION_ALIAS("REGION_HEAP", RAM); 11 | REGION_ALIAS("REGION_STACK", RAM); 12 | 13 | _hart_stack_size = 256; 14 | INCLUDE link.x 15 | -------------------------------------------------------------------------------- /sentinel-rt/src/lib.rs: -------------------------------------------------------------------------------- 1 | /*! Stub crate for Sentinel-specific routines. 2 | 3 | Right now, there's nothing here except examples! In the future, helper 4 | routines and the like specific to Sentinel functionality will go in here. */ 5 | 6 | #![no_std] 7 | -------------------------------------------------------------------------------- /src/sentinel/__init__.py: -------------------------------------------------------------------------------- 1 | """The Sentinel RISC-V CPU Package. 2 | 3 | There is no ``__all__``; star imports are not presently supported. Users will 4 | likely want to import or run one of the following modules directly: 5 | 6 | .. testcode:: 7 | 8 | from sentinel.top import Top 9 | 10 | :: 11 | 12 | python -m sentinel.gen --help 13 | """ 14 | -------------------------------------------------------------------------------- /src/sentinel/gen.py: -------------------------------------------------------------------------------- 1 | """Verilog generation module/script for Sentinel. 2 | 3 | At present, only running this module directly from the command-line 4 | (as ``__main__``) or from PDM is supported: 5 | 6 | :: 7 | 8 | python -m sentinel.gen --help 9 | 10 | .. code-block:: toml 11 | 12 | [tool.pdm.scripts] 13 | gen = { call = "sentinel.gen:generate", help="generate Sentinel Verilog file" } 14 | 15 | Individual functions are documented for completeness and should not be treated 16 | as public (see :doc:`/development/guidelines`). 17 | """ # noqa: E501 18 | 19 | import argparse 20 | import sys 21 | from contextlib import contextmanager 22 | 23 | from amaranth.back import verilog 24 | 25 | from .formal import FormalTop 26 | from .top import Top 27 | 28 | 29 | @contextmanager 30 | def _file_or_stdout(fn): 31 | """Context manager to open either a file or stdout if "-" is passed. 32 | 33 | Yields 34 | ------ 35 | fp 36 | File-like object representing either stdout or a disk-backed file. 37 | """ 38 | is_stdout = not fn or fn == "-" 39 | 40 | if not is_stdout: 41 | fp = open(fn, "w") 42 | else: 43 | fp = sys.stdout 44 | 45 | try: 46 | yield fp 47 | finally: 48 | if not is_stdout: 49 | fp.close() 50 | 51 | 52 | def _generate_args(parser): 53 | """Add argparse arguments.""" 54 | parser.add_argument("-o", help="output filename") 55 | parser.add_argument("-n", help="top-level name") 56 | parser.add_argument("-f", action="store_true", help="add RVFI connections") 57 | 58 | 59 | def generate(args=None): 60 | """Intended programmatic entry point to generate Sentinel core. 61 | 62 | .. todo:: 63 | 64 | This function is not yet complete and only works in the context of invoking 65 | via ``pdm``: 66 | 67 | .. code-block:: toml 68 | 69 | [tool.pdm.scripts] 70 | gen = { call = "sentinel.gen:generate", help="generate Sentinel Verilog file" } 71 | 72 | Parameters 73 | ---------- 74 | args 75 | Used to detect whether we are running as a script or as an imported 76 | module. Leave as ``None`` until the function is completed in a later 77 | release. 78 | """ # noqa: E501 79 | def do_gen(*, n, o, f): 80 | with _file_or_stdout(o) as fp: 81 | if f: 82 | m = FormalTop() 83 | else: 84 | m = Top() 85 | v = verilog.convert(m, name=n or "sentinel") 86 | fp.write(v) 87 | 88 | if isinstance(args, argparse.Namespace): 89 | if len(sys.argv) < 2: 90 | m = Top() 91 | print(verilog.convert(m)) 92 | else: 93 | do_gen(**vars(args)) 94 | else: 95 | if len(sys.argv) < 2: 96 | m = Top() 97 | print(verilog.convert(m)) 98 | else: 99 | parser = argparse.ArgumentParser(description="Sentinel Verilog generator (invoked from PDM)") # noqa: E501 100 | _generate_args(parser) 101 | do_gen(**vars(parser.parse_args())) 102 | 103 | 104 | def _main(): 105 | """Scripting entry point to generate Sentinel core.""" 106 | parser = argparse.ArgumentParser(description="Sentinel Verilog generator") 107 | 108 | _generate_args(parser) 109 | args = parser.parse_args() 110 | generate(args) 111 | 112 | 113 | if __name__ == "__main__": 114 | _main() 115 | -------------------------------------------------------------------------------- /src/sentinel/insn.py: -------------------------------------------------------------------------------- 1 | """Instruction View classes. 2 | 3 | This file is used to avoid circular import problems I had when using it 4 | directly in :mod:`sentinel.decode` (IIRC). 5 | """ 6 | 7 | from amaranth import Cat, Value, C, unsigned 8 | from amaranth.lib import enum 9 | 10 | from .csr import Quadrant, AccessMode 11 | 12 | 13 | class Insn: 14 | """View of all immediately-apparent information in a RISC-V instruction. 15 | 16 | "Immediately-apparent" means "I can get this info with 17 | :ref:`concatenation, slices and replicates `". This 18 | class is morally equivalent to a :class:`~amaranth.lib.data.View` for the 19 | 32-bit :ref:`Signal ` representing a RISC-V 20 | instruction. However, it does not inherit from 21 | :class:`~amaranth.lib.data.View` because 22 | :class:`Layouts ` are not designed to retrieve 23 | non-contiguous bits. 24 | 25 | Parameters 26 | ---------- 27 | value: ~amaranth.hdl.Value 28 | Raw value to interpret as a RISC-V instruction. 29 | 30 | Attributes 31 | ---------- 32 | raw: ~amaranth.hdl.Value 33 | The raw instruction value. 34 | imm: Imm 35 | A moral equivalent to a :class:`~amaranth.lib.data.View` for extracting 36 | RISC-V immediate values from :attr:`raw`. 37 | csr: CSR 38 | A moral equivalent to a :class:`~amaranth.lib.data.View` for extracting 39 | CSR information from :attr:`raw`. 40 | """ 41 | 42 | #: Bit pattern for ``ECALL`` instruction. 43 | ECALL = 0b00000000000000000000000001110011 44 | #: Bit pattern for ``EBREAK`` instruction. 45 | EBREAK = 0b00000000000100000000000001110011 46 | #: Bit pattern for ``MRET`` instruction. 47 | MRET = 0b00110000001000000000000001110011 48 | #: Bit pattern for ``WFI`` instruction. 49 | WFI = 0b00010000010100000000000001110011 50 | 51 | class Imm: 52 | """Extract a RISC-V immediate value from an instruction. 53 | 54 | This class does *not* (and *can not*) check whether the given 55 | instruction contains an immediate field or whether the requested 56 | immediate type is correct. The user is expected to known which 57 | immediate type to use using external logic. See 58 | :class:`~sentinel.decode.ImmediateGenerator` for an example. 59 | 60 | Parameters 61 | ---------- 62 | value: ~amaranth.hdl.Value 63 | Raw value to interpret as a RISC-V immediate. 64 | 65 | Attributes 66 | ---------- 67 | raw: ~amaranth.hdl.Value 68 | The raw instruction value. 69 | sign: ~amaranth.hdl.Value 70 | """ 71 | 72 | def __init__(self, value): 73 | self.raw = value 74 | self.sign = self.raw[-1] 75 | 76 | @property 77 | def I(self): # noqa: E743 78 | """~amaranth.hdl.Value: Extract an ``I``-type immediate.""" 79 | return Cat(self.raw[20:31], Value.replicate(self.sign, 21)) 80 | 81 | @property 82 | def S(self): 83 | """~amaranth.hdl.Value: Extract an ``S``-type immediate.""" 84 | return Cat(self.raw[7], self.raw[8:12], self.raw[25:31], 85 | Value.replicate(self.sign, 21)) 86 | 87 | @property 88 | def B(self): 89 | """~amaranth.hdl.Value: Extract a ``B``-type immediate.""" 90 | return Cat(C(0), self.raw[8:12], self.raw[25:31], self.raw[7], 91 | Value.replicate(self.sign, 20)) 92 | 93 | @property 94 | def U(self): 95 | """~amaranth.hdl.Value: Extract a ``U``-type immediate.""" 96 | return Cat(C(0, 12), self.raw[12:20], self.raw[20:31], self.sign) 97 | 98 | @property 99 | def J(self): 100 | """~amaranth.hdl.Value: Extract a ``J``-type immediate.""" 101 | return Cat(C(0), self.raw[21:25], self.raw[25:31], self.raw[20], 102 | self.raw[12:20], Value.replicate(self.sign, 12)) 103 | 104 | class CSR: 105 | """Extract RISC-V CSR info from an instruction. 106 | 107 | This class does *not* (and *can not*) check whether the given 108 | instruction is a CSR instruction. The user is expected to know a priori 109 | that the current instruction is a CSR instruction for results from 110 | this class to be valid. See :class:`~sentinel.decode.ExceptionControl` 111 | for an example. 112 | 113 | .. todo:: 114 | 115 | Constants aren't meaningfully used that much. Get rid of them 116 | and convert uses into properties? 117 | 118 | Parameters 119 | ---------- 120 | value: ~amaranth.hdl.Value 121 | Raw value from which to retrieve CSR info. 122 | 123 | Attributes 124 | ---------- 125 | raw: ~amaranth.hdl.Value 126 | The top 12 bits of the raw instruction value. 127 | """ 128 | 129 | #: Read-Write CSR instruction. 130 | RW = 0b001 131 | #: Read-Set CSR instruction. 132 | RS = 0b010 133 | #: Read-Clear CSR instruction. 134 | RC = 0b011 135 | #: Read-Write Immediate CSR instruction. 136 | RWI = 0b101 137 | #: Read-Set Immediate CSR instruction. 138 | RSI = 0b110 139 | #: Read-Clear Immediate CSR instruction. 140 | RCI = 0b111 141 | 142 | def __init__(self, value): 143 | self.raw = value[20:] 144 | 145 | @property 146 | def addr(self): 147 | """~amaranth.hdl.Value: Return the CSR address.""" 148 | return self.raw 149 | 150 | @property 151 | def quadrant(self): 152 | """~amaranth.lib.enum.EnumView: Return the CSR privilege level. 153 | 154 | :attr:`raw` is interpreted as a :class:`~sentinel.csr.Quadrant`. 155 | """ 156 | return enum.EnumView(Quadrant, self.raw[8:10]) 157 | 158 | @property 159 | def access(self): 160 | """~amaranth.lib.enum.EnumView: Return whether the CSR is read-only. 161 | 162 | :attr:`raw` is interpreted as an 163 | :class:`~sentinel.csr.AccessMode`. 164 | """ # noqa: E501 165 | return enum.EnumView(AccessMode, self.raw[10:]) 166 | 167 | def __init__(self, value): 168 | self.raw = value 169 | self.imm = Insn.Imm(self.raw) 170 | self.csr = Insn.CSR(self.raw) 171 | 172 | @property 173 | def opcode(self): 174 | """OpcodeType: Return the major opcode.""" 175 | return OpcodeType(self.raw[2:7]) 176 | 177 | @property 178 | def rd(self): 179 | """~amaranth.hdl.Value: Return the destination register bits.""" 180 | return self.raw[7:12] 181 | 182 | @property 183 | def funct3(self): 184 | """~amaranth.hdl.Value: Return the minor opcode/``funct3`` bits.""" 185 | return self.raw[12:15] 186 | 187 | @property 188 | def rs1(self): 189 | """~amaranth.hdl.Value: Return the first source register bits.""" 190 | return self.raw[15:20] 191 | 192 | @property 193 | def rs2(self): 194 | """~amaranth.hdl.Value: Return the second source register bits.""" 195 | return self.raw[20:25] 196 | 197 | @property 198 | def funct7(self): 199 | """~amaranth.hdl.Value: Return the ``funct7`` bits.""" 200 | return self.raw[25:] 201 | 202 | @property 203 | def funct12(self): 204 | """~amaranth.hdl.Value: Return the ``funct12`` bits.""" 205 | return self.raw[20:] 206 | 207 | @property 208 | def sign(self): 209 | """~amaranth.hdl.Value: Return the sign bit.""" 210 | return self.raw[-1] 211 | 212 | 213 | class OpcodeType(enum.Enum, shape=unsigned(5)): 214 | """Enumeration of RV32I Major Opcode bit patterns.""" 215 | 216 | #: Immediate Op instructions. 217 | OP_IMM = 0b00100 218 | #: Load Unsigned Immediate. 219 | LUI = 0b01101 220 | #: Add Upper Immediate To Program Counter. 221 | AUIPC = 0b00101 222 | #: Register Op instructions. 223 | OP = 0b01100 224 | #: Jump And Link. 225 | JAL = 0b11011 226 | #: Jump And Link Register. 227 | JALR = 0b11001 228 | #: Branch instructions. 229 | BRANCH = 0b11000 230 | #: Load instructions. 231 | LOAD = 0b00000 232 | #: Store instructions. 233 | STORE = 0b01000 234 | #: Unused Major Opcode for future custom instructions. 235 | CUSTOM_0 = 0b00010 236 | #: Miscellaneous instructions. 237 | MISC_MEM = 0b00011 238 | #: System instructions. 239 | SYSTEM = 0b11100 240 | -------------------------------------------------------------------------------- /tests/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/__init__.py -------------------------------------------------------------------------------- /tests/conftest.py: -------------------------------------------------------------------------------- 1 | from typing import Union 2 | import pytest 3 | 4 | from dataclasses import astuple, dataclass, field 5 | from bronzebeard.asm import assemble 6 | 7 | 8 | def pytest_addoption(parser): 9 | parser.addoption( 10 | "--runbench", action="store_true", default=False, help="run benchmarks" 11 | ) 12 | parser.addoption( 13 | "--runsoc", action="store_true", default=False, 14 | help="run SoC simulation" 15 | ) 16 | 17 | 18 | def pytest_collection_modifyitems(config, items): 19 | if not config.getoption("--runbench"): 20 | skip_bench = pytest.mark.skip(reason="need --runbench option to run") 21 | for item in items: 22 | if "bench" in item.keywords: 23 | item.add_marker(skip_bench) 24 | 25 | if not config.getoption("--runsoc"): 26 | skip_soc = pytest.mark.skip(reason="need --runsoc option to run") 27 | for item in items: 28 | if "soc" in item.keywords: 29 | item.add_marker(skip_soc) 30 | 31 | 32 | @pytest.fixture 33 | def ucode_panic(mod): 34 | m = mod 35 | 36 | async def ucode_panic(ctx): 37 | addr = 0 38 | prev_addr = 2 39 | count = 0 40 | async for *_, addr in ctx.tick().sample(m.control.ucoderom.addr): 41 | if addr == 255: 42 | raise AssertionError("microcode panic (not implemented)") 43 | 44 | if prev_addr == addr: 45 | count += 1 46 | if count > 100: 47 | raise AssertionError("microcode probably stuck in " 48 | "infinite loop") 49 | else: 50 | count = 0 51 | 52 | prev_addr = addr 53 | 54 | return ucode_panic 55 | 56 | 57 | @dataclass 58 | class MemoryArgs: 59 | start: int = 0 60 | size: int = 400 61 | init: Union[str, bytes, bytearray, list[int]] = field(default_factory=list) 62 | 63 | 64 | class Memory(list): 65 | def __init__(self, start, size): 66 | super().__init__([0] * size) 67 | self.range = range(start, start + size) 68 | 69 | 70 | @pytest.fixture 71 | def memory(request): 72 | (start, size, source_or_list) = astuple(request.param) 73 | mem = Memory(start, size) 74 | 75 | if isinstance(source_or_list, str): 76 | insns = assemble(source_or_list) 77 | for adr in range(0, len(insns) // 4): 78 | mem[adr] = int.from_bytes(insns[4 * adr:4 * adr + 4], 79 | byteorder="little") 80 | elif isinstance(source_or_list, (bytes, bytearray)): 81 | for adr in range(0, len(source_or_list) // 4): 82 | mem[adr] = int.from_bytes(source_or_list[4 * adr:4 * adr + 4], 83 | byteorder="little") 84 | else: 85 | for adr in range(0, len(source_or_list)): 86 | mem[adr] = source_or_list[adr] 87 | 88 | return mem 89 | 90 | 91 | async def mproc_inner(mod, ctx, memory): 92 | m = mod 93 | 94 | stims = [m.bus.cyc & m.bus.stb, m.bus.adr, m.bus.dat_w, m.bus.we, 95 | m.bus.sel] 96 | 97 | while True: 98 | clk_hit, rst_active, wb_cyc, addr, dat_w, we, sel = \ 99 | await ctx.tick().sample(*stims) 100 | 101 | if rst_active: 102 | pass 103 | elif clk_hit and wb_cyc and addr in memory.range: 104 | if we: 105 | dat_r = memory[addr - memory.range.start] 106 | 107 | if sel & 0x1: 108 | dat_r = (dat_r & 0xffffff00) | (dat_w & 0x000000ff) 109 | if sel & 0x2: 110 | dat_r = (dat_r & 0xffff00ff) | (dat_w & 0x0000ff00) 111 | if sel & 0x4: 112 | dat_r = (dat_r & 0xff00ffff) | (dat_w & 0x00ff0000) 113 | if sel & 0x8: 114 | dat_r = (dat_r & 0x00ffffff) | (dat_w & 0xff000000) 115 | 116 | memory[addr] = dat_r 117 | else: 118 | # TODO: Some memories will dup byte/half data on the 119 | # inactive lines. Worth adding? 120 | ctx.set(m.bus.dat_r, memory[addr - memory.range.start]) 121 | ctx.set(m.bus.ack, 1) 122 | # TODO: Wait states? See bus_proc_aux in previous versions for 123 | # inspiration. 124 | await ctx.tick() 125 | ctx.set(m.bus.ack, 0) 126 | 127 | 128 | @pytest.fixture 129 | def memory_process(mod, memory): 130 | m = mod 131 | 132 | async def memory_process(ctx): 133 | await mproc_inner(m, ctx, memory) 134 | 135 | return memory_process 136 | -------------------------------------------------------------------------------- /tests/formal/README.md: -------------------------------------------------------------------------------- 1 | # RISCV-Formal Tests 2 | 3 | Tests from [RISC-V Formal](https://github.com/YosysHQ/riscv-formal) and 4 | support config files/code go here. Running the solvers used for RISC-V Formal 5 | is orchestrated by the [`dodo.py`](https://pydoit.org) at the root of this 6 | repo. 7 | 8 | Make sure `doit` and `click` are installed via `pdm install -G dev`. _You must 9 | provide your own copy of `yosys`, `sby` and `boolector`_. Then, run the 10 | RISC-V Formal suite using `pdm run rvformal-all [-n num_cores]`. 11 | 12 | See [Testing Prerequisites](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html#prerequisites) 13 | and [RISC-V Formal docs](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html#risc-v-formal) 14 | for more information. 15 | -------------------------------------------------------------------------------- /tests/formal/checks.cfg: -------------------------------------------------------------------------------- 1 | [options] 2 | isa rv32i 3 | 4 | [groups] 5 | # Shift insns make a true full formal test take a long time (10+ mins just 6 | # to check assumptions), probably for little gain. Neverless, allow the 7 | # possibility for running long tests. 8 | full 9 | # Group for experimenting with IRQ line. Not currently used (in particular, 10 | # my intended use-case of "irq_cover" creates a BMC, not a cover check.) 11 | irq 12 | 13 | [depth] 14 | insn 20 15 | full_insn_slli 80 16 | full_insn_srli 80 17 | full_insn_srai 80 18 | full_insn_sll 80 19 | full_insn_srl 80 20 | full_insn_sra 80 21 | reg 15 25 22 | pc_fwd 10 30 23 | pc_bwd 10 30 24 | liveness 1 12 39 25 | full_liveness 1 12 150 26 | unique 1 12 30 27 | causal 10 30 28 | cover 1 30 29 | 30 | csrw 20 31 | csr_ill 20 32 | csrw_misa 20 33 | csrc_any 1 20 34 | csrc_zero 1 20 35 | csrc_const 1 20 36 | 37 | [csrs] 38 | mscratch any 39 | mcause 40 | mip zero_mask="32'h0000F7FF" 41 | mie zero_mask="32'h0000F7FF" 42 | mstatus const="32'h0001800"_mask="32'hFFFFFFF7" 43 | mtvec zero_mask="32'h00000003" 44 | mepc zero_mask="32'h00000003" 45 | # Read-only zero registers 46 | mvendorid zero 47 | marchid zero 48 | mimpid zero 49 | mhartid zero 50 | mconfigptr zero 51 | # R/W zero registers 52 | misa zero 53 | mstatush zero 54 | mcountinhibit zero 55 | mtval zero 56 | mcycle zero # no mcycleh in RISC-V Formal 57 | minstret zero # no minstreth in RISC-V Formal 58 | # All 3-31 are zero. Just test one of each for now to avoid explosion of 59 | # tests. No "h" regs for either. 60 | mhpmcounter3 zero 61 | mhpmevent3 zero 62 | 63 | [illegal_csrs] 64 | # Most CSRs are illegal. It is cost-prohibitive to test all of them. 65 | # Choose a dummy register outside of M-Mode. 66 | eff m rw 67 | # Not-implemented M-Mode registers. In order: medeleg, mideleg, mcounteren, 68 | # mtinst, mtval2, menvcfg, menvcfgh 69 | # mseccfg/h not implemented in RISC-V Formal 70 | 302 m rw 71 | 303 m rw 72 | 306 m rw 73 | 34a m rw 74 | 34b m rw 75 | 30a m rw 76 | 31a m rw 77 | 78 | # Bug? I think the "!" shouldn't be required. 79 | [assume !csrw_mip] 80 | // In the presence of external/async interrupts, it may not be possible to 81 | // ensure the data read into GP regs from MIP matches the data actually in 82 | // MIP, or ensure that a CSR write that ends up being a no-op (or a skipped 83 | // write) actually leaves MIP.MEIP alone, among other things. So assume 84 | // external ints are disabled for checking MIP. 85 | always @* assume((rvfi_csr_mip_rdata & 32'h00000800) == 0); 86 | 87 | [defines] 88 | `define RISCV_FORMAL_ALIGNED_MEM 89 | 90 | [defines liveness] 91 | `define MEMIO_FAIRNESS 92 | 93 | [defines full_liveness] 94 | `define MEMIO_FAIRNESS 95 | `define NO_SHIFT_FAIRNESS 96 | 97 | [verilog-files] 98 | @basedir@/cores/@core@/wrapper.sv 99 | @basedir@/cores/@core@/@core@.v 100 | 101 | [cover] 102 | // Create a trace which executes 5 insns. 103 | always @* if (!reset) cover (channel[0].cnt_insns == 5); 104 | // Get an idea of how many clocks required to meaningfully write MSCRATCH. 105 | always @* if (!reset) cover (rvfi_valid 106 | && rvfi_csr_mscratch_rdata == 32'hFEEDCAFE); 107 | // Generate a trace that takes an IRQ. 108 | always @* if (!reset) cover (rvfi_valid && 109 | rvfi_csr_mcause_wdata == 32'h8000000B && 110 | // TODO: Trace that takes an IRQ and executes MRET? 111 | // Will at least need rvfi_trap_prev signal. 112 | // rvfi_insn == 32'b00110000001000000000000001110011 && 113 | rvfi_csr_mstatus_rdata[7] == 1 && 114 | rvfi_csr_mip_rdata[11] == 1 && 115 | rvfi_csr_mie_rdata[11] == 1 && 116 | rvfi_trap); 117 | `ifdef TRAP_TRACE 118 | // Create a trace which demonstrates trapping. 119 | reg rvfi_trap_prev = 0; 120 | always @(posedge clock) if (rvfi_valid) rvfi_trap_prev <= rvfi_trap; 121 | always @* if (!reset) cover (channel[0].cnt_insns == 5 && rvfi_valid && rvfi_trap_prev); 122 | `endif 123 | -------------------------------------------------------------------------------- /tests/formal/disasm.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from Verilog_VCD.Verilog_VCD import parse_vcd 4 | from os import system 5 | from sys import argv 6 | from pathlib import Path 7 | 8 | rvfi_valid = None 9 | rvfi_order = None 10 | rvfi_insn = None 11 | 12 | for netinfo in parse_vcd(argv[1]).values(): 13 | for net in netinfo['nets']: 14 | # print(net["hier"], net["name"]) 15 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_valid": # noqa: E501 16 | rvfi_valid = netinfo['tv'] 17 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_order": # noqa: E501 18 | rvfi_order = netinfo['tv'] 19 | if net["hier"] == "rvfi_testbench.wrapper" and net["name"] == "rvfi_insn": # noqa: E501 20 | rvfi_insn = netinfo['tv'] 21 | 22 | assert len(rvfi_valid) == len(rvfi_order) 23 | assert len(rvfi_valid) == len(rvfi_insn) 24 | 25 | prog = list() 26 | 27 | for tv_valid, tv_order, tv_insn in zip(rvfi_valid, rvfi_order, rvfi_insn): 28 | if tv_valid[1] == '1': 29 | prog.append((int(tv_order[1], 2), int(tv_insn[1], 2))) 30 | 31 | # These are my local modifications to disasm.py- potentially attach a unique 32 | # suffix, so that disasm generation can be parallelized. 33 | if len(argv) > 1: 34 | disasm = Path(f"disasm-{argv[2]}.s") 35 | else: 36 | disasm = Path("disasm.s") 37 | with open(disasm, "w") as f: 38 | for tv_order, tv_insn in sorted(prog): 39 | if tv_insn & 3 != 3 and tv_insn & 0xffff0000 == 0: 40 | print(".hword 0x%04x # %d" % (tv_insn, tv_order), file=f) 41 | else: 42 | print(".word 0x%08x # %d" % (tv_insn, tv_order), file=f) 43 | 44 | system(f"riscv64-unknown-elf-gcc -c {disasm}") 45 | system(f"""riscv64-unknown-elf-objdump -d -M numeric,no-aliases {disasm.with_suffix(".o")}""") # noqa: E501 46 | -------------------------------------------------------------------------------- /tests/formal/wrapper.sv: -------------------------------------------------------------------------------- 1 | module rvfi_wrapper ( 2 | input clock, 3 | input reset, 4 | `RVFI_OUTPUTS 5 | ); 6 | 7 | // Convert from RVFI naming scheme to Amaranth interface naming scheme. 8 | `define RVFI_AMARANTH_PORT(suff) .rvfi__``suff(rvfi_``suff) 9 | `define RVFI_CSR_AMARANTH_PORTS(csr) \ 10 | .rvfi__csr__``csr``__rmask(rvfi_csr_``csr``_rmask), \ 11 | .rvfi__csr__``csr``__wmask(rvfi_csr_``csr``_wmask), \ 12 | .rvfi__csr__``csr``__rdata(rvfi_csr_``csr``_rdata), \ 13 | .rvfi__csr__``csr``__wdata(rvfi_csr_``csr``_wdata) 14 | 15 | (* keep *) `rvformal_rand_reg bus__ack; 16 | (* keep *) `rvformal_rand_reg irq; 17 | (* keep *) `rvformal_rand_reg [31:0] bus__dat_r; 18 | 19 | (* keep *) wire bus__cyc; 20 | (* keep *) wire bus__stb; 21 | (* keep *) wire [3:0] bus__sel; 22 | (* keep *) wire bus__we; 23 | (* keep *) wire [29:0] bus__adr; 24 | (* keep *) wire [31:0] bus__dat_w; 25 | 26 | sentinel uut( 27 | .clk(clock), 28 | .rst(reset), 29 | 30 | .bus__adr (bus__adr), 31 | .bus__cyc (bus__cyc), 32 | .bus__dat_r (bus__dat_r), 33 | .bus__dat_w (bus__dat_w), 34 | .bus__sel (bus__sel), 35 | .bus__stb (bus__stb), 36 | .bus__we (bus__we), 37 | .bus__ack (bus__ack), 38 | 39 | .irq (irq), 40 | 41 | `RVFI_AMARANTH_PORT(valid), 42 | `RVFI_AMARANTH_PORT(order), 43 | `RVFI_AMARANTH_PORT(insn), 44 | `RVFI_AMARANTH_PORT(trap), 45 | `RVFI_AMARANTH_PORT(halt), 46 | `RVFI_AMARANTH_PORT(intr), 47 | `RVFI_AMARANTH_PORT(mode), 48 | `RVFI_AMARANTH_PORT(ixl), 49 | `RVFI_AMARANTH_PORT(rs1_addr), 50 | `RVFI_AMARANTH_PORT(rs2_addr), 51 | `RVFI_AMARANTH_PORT(rs1_rdata), 52 | `RVFI_AMARANTH_PORT(rs2_rdata), 53 | `RVFI_AMARANTH_PORT(rd_addr), 54 | `RVFI_AMARANTH_PORT(rd_wdata), 55 | `RVFI_AMARANTH_PORT(pc_rdata), 56 | `RVFI_AMARANTH_PORT(pc_wdata), 57 | `RVFI_AMARANTH_PORT(mem_addr), 58 | `RVFI_AMARANTH_PORT(mem_rmask), 59 | `RVFI_AMARANTH_PORT(mem_wmask), 60 | `RVFI_AMARANTH_PORT(mem_rdata), 61 | `RVFI_AMARANTH_PORT(mem_wdata), 62 | 63 | `RVFI_CSR_AMARANTH_PORTS(mscratch), 64 | `RVFI_CSR_AMARANTH_PORTS(mcause), 65 | `RVFI_CSR_AMARANTH_PORTS(mip), 66 | `RVFI_CSR_AMARANTH_PORTS(mie), 67 | `RVFI_CSR_AMARANTH_PORTS(mstatus), 68 | `RVFI_CSR_AMARANTH_PORTS(mtvec), 69 | `RVFI_CSR_AMARANTH_PORTS(mepc), 70 | `RVFI_CSR_AMARANTH_PORTS(mvendorid), 71 | `RVFI_CSR_AMARANTH_PORTS(marchid), 72 | `RVFI_CSR_AMARANTH_PORTS(mimpid), 73 | `RVFI_CSR_AMARANTH_PORTS(mhartid), 74 | `RVFI_CSR_AMARANTH_PORTS(mconfigptr), 75 | `RVFI_CSR_AMARANTH_PORTS(misa), 76 | `RVFI_CSR_AMARANTH_PORTS(mstatush), 77 | `RVFI_CSR_AMARANTH_PORTS(mcountinhibit), 78 | `RVFI_CSR_AMARANTH_PORTS(mtval), 79 | `RVFI_CSR_AMARANTH_PORTS(mcycle), 80 | `RVFI_CSR_AMARANTH_PORTS(minstret), 81 | `RVFI_CSR_AMARANTH_PORTS(mhpmcounter3), 82 | `RVFI_CSR_AMARANTH_PORTS(mhpmevent3) 83 | ); 84 | 85 | reg [2:0] timeout_bus = 0; 86 | reg [1:0] trap_nest = 0; 87 | 88 | always @(posedge clock) begin 89 | timeout_bus <= 0; 90 | 91 | if (bus__cyc && !bus__ack) 92 | timeout_bus <= timeout_bus + 1; 93 | 94 | if (rvfi_trap && bus__ack) begin 95 | trap_nest <= trap_nest + 2'b01; 96 | 97 | // If mret and in trap, decrement nesting cntr. 98 | if((rvfi_insn == 32'b00110000001000000000000001110011) && 99 | |trap_nest) begin 100 | trap_nest <= trap_nest - 2'b01; 101 | end 102 | end 103 | 104 | `ifdef RISCV_FORMAL_FAIRNESS 105 | // Prevent peripherals from hogging the bus with exorbitant wait states. 106 | // That way, if progress is never made, it's Sentinel's fault. 107 | `ifdef MEMIO_FAIRNESS 108 | assume (!timeout_bus[2]); 109 | `endif 110 | 111 | `ifndef NO_SHIFT_FAIRNESS 112 | // Constrain shift ops to either shift 0 or 1. 113 | // Was for testing; generates interesting CEX w/ nested exceptions. 114 | // if((rvfi_insn[0:6] == 7'b0010011) && 115 | // (rvfi_insn[12:14] == 3'b001)) begin 116 | // assert (rvfi_insn[20:24] < 2); 117 | // end 118 | 119 | // SLLI 120 | if((rvfi_insn[0:6] == 7'b0010011) && 121 | (rvfi_insn[12:14] == 3'b001)) begin 122 | assume (rvfi_insn[20:24] < 2); 123 | end 124 | 125 | // SR*I 126 | if((rvfi_insn[0:6] == 7'b0010011) && 127 | (rvfi_insn[12:14] == 3'b101)) begin 128 | assume (rvfi_insn[20:24] < 2); 129 | end 130 | 131 | // SR* 132 | if((rvfi_insn[0:6] == 7'b0110011) && 133 | (rvfi_insn[12:14] == 3'b101)) begin 134 | assume (rvfi_rs2_rdata < 2); 135 | end 136 | 137 | // SLL 138 | if((rvfi_insn[0:6] == 7'b0110011) && 139 | (rvfi_insn[12:14] == 3'b001)) begin 140 | assume (rvfi_rs2_rdata < 2); 141 | end 142 | `endif 143 | `endif 144 | 145 | // Assume peripherals are well-behaved and take at least one cycle to 146 | // respond. 147 | if(~|timeout_bus && bus__cyc) 148 | assume(!bus__ack); 149 | 150 | // Nested traps not supported yet. Easy enough to lock the core into an 151 | // illegal insn and then repeatedly grab illegal insns. 152 | // TODO: Move into RISCV_FORMAL_FAIRNESS ifdef block? 153 | assume(trap_nest < 2); 154 | end 155 | endmodule 156 | -------------------------------------------------------------------------------- /tests/riscof/.gitignore: -------------------------------------------------------------------------------- 1 | riscof_work/ 2 | bin/riscv_sim_RV32 3 | bin/riscv_sim_RV64 4 | -------------------------------------------------------------------------------- /tests/riscof/README.md: -------------------------------------------------------------------------------- 1 | # RISCOF Framework Tests 2 | 3 | Tests from the [RISCOF Framework](https://github.com/riscv-non-isa/riscv-arch-test) 4 | go here. _The tests in this directory at present only support Linux due to me 5 | having trouble installing `opam`/`ocaml` on Windows._ 6 | 7 | Make sure `riscof` is installed via `pdm install -G dev -G riscof`. _You must 8 | provide your own copies of `gcc`, `ocaml`, `opam`, and `sail`_. Additionally, 9 | `riscv64-unknown-elf-gcc` must be provided. Then, run the RISCOF framework 10 | tests using `pdm run riscof-all`. 11 | 12 | Building the [SAIL RISC-V emulators](https://github.com/riscv/sail-riscv) required 13 | by RISCOF is something of a pain. A gzipped Linux binary of SAIL is provided 14 | under the [bin](bin) directory, and will be decompressed on demand. The 15 | [`dodo.py`](https://pydoit.org) at the root of this repo provides a 16 | `_build_sail` task for rebuilding the SAIL emulators in an `opam` environment. 17 | However, this should not be relied upon for normal development. 18 | 19 | See [Testing Prerequisites](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html#prerequisites) 20 | and [RISC-V Formal docs](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html#riscof) 21 | for more information. 22 | -------------------------------------------------------------------------------- /tests/riscof/bin/riscv_sim_RV32.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/riscof/bin/riscv_sim_RV32.gz -------------------------------------------------------------------------------- /tests/riscof/config.ini: -------------------------------------------------------------------------------- 1 | [RISCOF] 2 | ReferencePlugin=sail_cSim 3 | ReferencePluginPath=./sail_cSim 4 | DUTPlugin=sentinel 5 | DUTPluginPath=./sentinel 6 | 7 | [sentinel] 8 | pluginpath=./sentinel 9 | ispec=./sentinel/sentinel_isa.yaml 10 | pspec=./sentinel/sentinel_platform.yaml 11 | target_run=1 12 | 13 | [sail_cSim] 14 | pluginpath=./sail_cSim 15 | -------------------------------------------------------------------------------- /tests/riscof/sail_cSim/__init__.py: -------------------------------------------------------------------------------- 1 | from pkgutil import extend_path 2 | __path__ = extend_path(__path__, __name__) -------------------------------------------------------------------------------- /tests/riscof/sail_cSim/env/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(rvtest_entry_point) 3 | 4 | SECTIONS 5 | { 6 | . = 0x80000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x1000); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x1000); 11 | .text : { *(.text) } 12 | . = ALIGN(0x1000); 13 | .data : { *(.data) } 14 | .data.string : { *(.data.string)} 15 | .bss : { *(.bss) } 16 | _end = .; 17 | } 18 | 19 | -------------------------------------------------------------------------------- /tests/riscof/sail_cSim/env/model_test.h: -------------------------------------------------------------------------------- 1 | #ifndef _COMPLIANCE_MODEL_H 2 | #define _COMPLIANCE_MODEL_H 3 | 4 | #define RVMODEL_DATA_SECTION \ 5 | .pushsection .tohost,"aw",@progbits; \ 6 | .align 8; .global tohost; tohost: .dword 0; \ 7 | .align 8; .global fromhost; fromhost: .dword 0; \ 8 | .popsection; \ 9 | .align 8; .global begin_regstate; begin_regstate: \ 10 | .word 128; \ 11 | .align 8; .global end_regstate; end_regstate: \ 12 | .word 4; 13 | 14 | //RV_COMPLIANCE_HALT 15 | #define RVMODEL_HALT \ 16 | li x1, 1; \ 17 | write_tohost: \ 18 | sw x1, tohost, t5; \ 19 | j write_tohost; 20 | 21 | #define RVMODEL_BOOT 22 | 23 | //RV_COMPLIANCE_DATA_BEGIN 24 | #define RVMODEL_DATA_BEGIN \ 25 | RVMODEL_DATA_SECTION \ 26 | .align 4;\ 27 | .global begin_signature; begin_signature: 28 | 29 | //RV_COMPLIANCE_DATA_END 30 | #define RVMODEL_DATA_END \ 31 | .align 4; .global end_signature; end_signature: 32 | 33 | //RVTEST_IO_INIT 34 | #define RVMODEL_IO_INIT 35 | //RVTEST_IO_WRITE_STR 36 | #define RVMODEL_IO_WRITE_STR(_R, _STR) 37 | //RVTEST_IO_CHECK 38 | #define RVMODEL_IO_CHECK() 39 | //RVTEST_IO_ASSERT_GPR_EQ 40 | #define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) 41 | //RVTEST_IO_ASSERT_SFPR_EQ 42 | #define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) 43 | //RVTEST_IO_ASSERT_DFPR_EQ 44 | #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) 45 | 46 | #define RVMODEL_SET_MSW_INT 47 | 48 | #define RVMODEL_CLEAR_MSW_INT 49 | 50 | #define RVMODEL_CLEAR_MTIMER_INT 51 | 52 | #define RVMODEL_CLEAR_MEXT_INT 53 | 54 | 55 | #endif // _COMPLIANCE_MODEL_H 56 | -------------------------------------------------------------------------------- /tests/riscof/sail_cSim/riscof_sail_cSim.py: -------------------------------------------------------------------------------- 1 | import os 2 | import re 3 | import shutil 4 | import subprocess 5 | import shlex 6 | import logging 7 | import random 8 | import string 9 | from string import Template 10 | 11 | import riscof.utils as utils 12 | from riscof.pluginTemplate import pluginTemplate 13 | import riscof.constants as constants 14 | from riscv_isac.isac import isac 15 | 16 | logger = logging.getLogger() 17 | 18 | class sail_cSim(pluginTemplate): 19 | __model__ = "sail_c_simulator" 20 | __version__ = "0.5.0" 21 | 22 | def __init__(self, *args, **kwargs): 23 | sclass = super().__init__(*args, **kwargs) 24 | 25 | config = kwargs.get('config') 26 | if config is None: 27 | logger.error("Config node for sail_cSim missing.") 28 | raise SystemExit(1) 29 | self.num_jobs = str(config['jobs'] if 'jobs' in config else 1) 30 | self.pluginpath = os.path.abspath(config['pluginpath']) 31 | self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV32"), 32 | '64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV64")} 33 | self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else '' 34 | self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else '' 35 | self.make = config['make'] if 'make' in config else 'make' 36 | logger.debug("SAIL CSim plugin initialised using the following configuration.") 37 | for entry in config: 38 | logger.debug(entry+' : '+config[entry]) 39 | return sclass 40 | 41 | def initialise(self, suite, work_dir, archtest_env): 42 | self.suite = suite 43 | self.work_dir = work_dir 44 | self.objdump_cmd = 'riscv64-unknown-elf-objdump -D {0} > {1};' 45 | self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \ 46 | -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles\ 47 | -T '+self.pluginpath+'/env/link.ld\ 48 | -I '+self.pluginpath+'/env/\ 49 | -I ' + archtest_env 50 | 51 | def build(self, isa_yaml, platform_yaml): 52 | ispec = utils.load_yaml(isa_yaml)['hart0'] 53 | self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') 54 | self.isa = 'rv' + self.xlen 55 | self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else 'ilp32 ') 56 | if "I" in ispec["ISA"]: 57 | self.isa += 'i' 58 | if "M" in ispec["ISA"]: 59 | self.isa += 'm' 60 | if "C" in ispec["ISA"]: 61 | self.isa += 'c' 62 | if "F" in ispec["ISA"]: 63 | self.isa += 'f' 64 | if "D" in ispec["ISA"]: 65 | self.isa += 'd' 66 | objdump = "riscv64-unknown-elf-objdump" 67 | if shutil.which(objdump) is None: 68 | logger.error(objdump+": executable not found. Please check environment setup.") 69 | raise SystemExit(1) 70 | compiler = "riscv64-unknown-elf-gcc" 71 | if shutil.which(compiler) is None: 72 | logger.error(compiler+": executable not found. Please check environment setup.") 73 | raise SystemExit(1) 74 | if shutil.which(self.sail_exe[self.xlen]) is None: 75 | logger.error(self.sail_exe[self.xlen]+ ": executable not found. Please check environment setup.") 76 | raise SystemExit(1) 77 | if shutil.which(self.make) is None: 78 | logger.error(self.make+": executable not found. Please check environment setup.") 79 | raise SystemExit(1) 80 | 81 | 82 | def runTests(self, testList, cgf_file=None): 83 | if os.path.exists(self.work_dir+ "/Makefile." + self.name[:-1]): 84 | os.remove(self.work_dir+ "/Makefile." + self.name[:-1]) 85 | make = utils.makeUtil(makefilePath=os.path.join(self.work_dir, "Makefile." + self.name[:-1])) 86 | make.makeCommand = self.make + ' -j' + self.num_jobs 87 | for file in testList: 88 | testentry = testList[file] 89 | test = testentry['test_path'] 90 | test_dir = testentry['work_dir'] 91 | test_name = test.rsplit('/',1)[1][:-2] 92 | 93 | elf = 'ref.elf' 94 | 95 | execute = "@cd "+testentry['work_dir']+";" 96 | 97 | cmd = self.compile_cmd.format(testentry['isa'].lower()) + ' ' + test + ' -o ' + elf 98 | compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) 99 | execute+=compile_cmd+";" 100 | 101 | execute += self.objdump_cmd.format(elf, 'ref.disass') 102 | sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") 103 | 104 | execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) 105 | 106 | cov_str = ' ' 107 | for label in testentry['coverage_labels']: 108 | cov_str+=' -l '+label 109 | 110 | if cgf_file is not None: 111 | coverage_cmd = 'riscv_isac --verbose info coverage -d \ 112 | -t {0}.log --parser-name c_sail -o coverage.rpt \ 113 | --sig-label begin_signature end_signature \ 114 | --test-label rvtest_code_begin rvtest_code_end \ 115 | -e ref.elf -c {1} -x{2} {3};'.format(\ 116 | test_name, ' -c '.join(cgf_file), self.xlen, cov_str) 117 | else: 118 | coverage_cmd = '' 119 | 120 | 121 | execute+=coverage_cmd 122 | 123 | make.add_target(execute) 124 | make.execute_all(self.work_dir) 125 | -------------------------------------------------------------------------------- /tests/riscof/sentinel/env/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(rvtest_entry_point) 3 | 4 | SECTIONS 5 | { 6 | . = 0x00000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x10); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x10); 11 | .text : { *(.text) } 12 | /* Unfortunately, . = ALIGN(0x10) doesn't get us much; there's an .align 12 13 | in arch_test.h for paged systems that essentially forces us to use at 14 | least 8Kb of simulated memory. */ 15 | . = ALIGN(0x10); 16 | .data : { *(.data) } 17 | .data.string : { *(.data.string)} 18 | .bss : { *(.bss) } 19 | _end = .; 20 | } 21 | -------------------------------------------------------------------------------- /tests/riscof/sentinel/env/model_test.h: -------------------------------------------------------------------------------- 1 | #ifndef _COMPLIANCE_MODEL_H 2 | #define _COMPLIANCE_MODEL_H 3 | #define RVMODEL_DATA_SECTION \ 4 | .pushsection .tohost,"aw",@progbits; \ 5 | .align 8; .global tohost; tohost: .dword 0; \ 6 | .align 8; .global fromhost; fromhost: .dword 0; \ 7 | .popsection; \ 8 | .align 8; .global begin_regstate; begin_regstate: \ 9 | .word 128; \ 10 | .align 8; .global end_regstate; end_regstate: \ 11 | .word 4; 12 | 13 | #define HOST_PORT 0x4000000 14 | 15 | //RV_COMPLIANCE_HALT 16 | #define RVMODEL_HALT \ 17 | la x1, begin_signature; \ 18 | la x2, end_signature; \ 19 | li t5, HOST_PORT; \ 20 | write_tohost: \ 21 | sw x1, 0(t5); \ 22 | sw x2, 4(t5); \ 23 | j write_tohost; 24 | 25 | #define RVMODEL_BOOT 26 | 27 | //RV_COMPLIANCE_DATA_BEGIN 28 | #define RVMODEL_DATA_BEGIN \ 29 | RVMODEL_DATA_SECTION \ 30 | .align 4;\ 31 | .global begin_signature; begin_signature: 32 | 33 | //RV_COMPLIANCE_DATA_END 34 | #define RVMODEL_DATA_END \ 35 | .align 4;\ 36 | .global end_signature; end_signature: 37 | 38 | //RVTEST_IO_INIT 39 | #define RVMODEL_IO_INIT 40 | //RVTEST_IO_WRITE_STR 41 | #define RVMODEL_IO_WRITE_STR(_R, _STR) 42 | //RVTEST_IO_CHECK 43 | #define RVMODEL_IO_CHECK() 44 | //RVTEST_IO_ASSERT_GPR_EQ 45 | #define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) 46 | //RVTEST_IO_ASSERT_SFPR_EQ 47 | #define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) 48 | //RVTEST_IO_ASSERT_DFPR_EQ 49 | #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) 50 | 51 | #define RVMODEL_SET_MSW_INT \ 52 | li t1, 1; \ 53 | li t2, 0x2000000; \ 54 | sw t1, 0(t2); 55 | 56 | #define RVMODEL_CLEAR_MSW_INT \ 57 | li t2, 0x2000000; \ 58 | sw x0, 0(t2); 59 | 60 | #define RVMODEL_CLEAR_MTIMER_INT 61 | 62 | #define RVMODEL_CLEAR_MEXT_INT 63 | 64 | 65 | #endif // _COMPLIANCE_MODEL_H 66 | -------------------------------------------------------------------------------- /tests/riscof/sentinel/sentinel_isa.yaml: -------------------------------------------------------------------------------- 1 | # Useful docs: https://riscv-config.readthedocs.io/en/stable/yaml-specs.html 2 | # https://github.com/riscv-software-src/riscv-config/blob/b550aaa38538797b6f63aba2e2385c83642f6756/riscv_config/schemas/schema_isa.yaml 3 | # This file references the schema to skip over CSR fields with already-correct 4 | # defaults. 5 | hart_ids: [0] 6 | hart0: 7 | # ISA: RV32IZicsr # Revisit once I-tests are working 8 | ISA: RV32I 9 | physical_addr_sz: 32 10 | User_Spec_Version: '2.3' 11 | # Privilege_Spec_Version: '1.11' # Revisit once I-tests are working 12 | hw_data_misaligned_support: False 13 | supported_xlen: [32] 14 | mstatus: 15 | reset-val: 0x00018000 16 | rv64: 17 | accessible: false 18 | rv32: 19 | mpp: 20 | type: 21 | ro_constant: 0b11 22 | sd: 23 | implemented: false 24 | mstatush: 25 | rv32: 26 | accessible: true 27 | -------------------------------------------------------------------------------- /tests/riscof/sentinel/sentinel_platform.yaml: -------------------------------------------------------------------------------- 1 | mtime: 2 | implemented: false 3 | mtimecmp: 4 | implemented: false 5 | nmi: 6 | label: nmi_vector 7 | reset: 8 | label: reset_vector 9 | -------------------------------------------------------------------------------- /tests/sim/conftest.py: -------------------------------------------------------------------------------- 1 | from dataclasses import dataclass 2 | 3 | 4 | @dataclass 5 | class RV32Regs: 6 | @classmethod 7 | def from_top_module(cls, m, ctx): 8 | gpregs = [] 9 | for r_id in range(32): 10 | gpregs.append(ctx.get(m.datapath.regfile.m_data[r_id])) 11 | 12 | return cls(*gpregs, PC=(ctx.get(m.datapath.pc.dat_r))) 13 | 14 | R0: int = 0 15 | R1: int = 0 16 | R2: int = 0 17 | R3: int = 0 18 | R4: int = 0 19 | R5: int = 0 20 | R6: int = 0 21 | R7: int = 0 22 | R8: int = 0 23 | R9: int = 0 24 | R10: int = 0 25 | R11: int = 0 26 | R12: int = 0 27 | R13: int = 0 28 | R14: int = 0 29 | R15: int = 0 30 | R16: int = 0 31 | R17: int = 0 32 | R18: int = 0 33 | R19: int = 0 34 | R20: int = 0 35 | R21: int = 0 36 | R22: int = 0 37 | R23: int = 0 38 | R24: int = 0 39 | R25: int = 0 40 | R26: int = 0 41 | R27: int = 0 42 | R28: int = 0 43 | R29: int = 0 44 | R30: int = 0 45 | R31: int = 0 46 | PC: int = 0 47 | 48 | 49 | @dataclass 50 | class CSRRegs: 51 | @classmethod 52 | def from_top_module(cls, m, ctx): 53 | csrregs = {} 54 | 55 | csrregs["MSCRATCH"] = ctx.get(m.datapath.regfile.m_data[0x28]) 56 | csrregs["MSTATUS"] = ctx.get(m.datapath.csr.mstatus_r.as_value()) 57 | csrregs["MTVEC"] = ctx.get(m.datapath.regfile.m_data[0x25]) 58 | csrregs["MIE"] = ctx.get(m.datapath.csr.mie_r.as_value()) 59 | csrregs["MIP"] = ctx.get(m.datapath.csr.mip_r.as_value()) 60 | csrregs["MEPC"] = ctx.get(m.datapath.regfile.m_data[0x29]) 61 | csrregs["MCAUSE"] = ctx.get(m.datapath.regfile.m_data[0x2A]) 62 | 63 | return cls(**csrregs) 64 | 65 | MSCRATCH: int = 0 66 | MSTATUS: int = 0b11000_0000_0000 67 | MTVEC: int = 0 68 | MEPC: int = 0 69 | MCAUSE: int = 0 70 | MIP: int = 0 71 | MIE: int = 0 72 | -------------------------------------------------------------------------------- /tests/sim/test_soc.py: -------------------------------------------------------------------------------- 1 | from pathlib import Path 2 | import pytest 3 | 4 | from itertools import islice 5 | from functools import reduce 6 | from elftools.elf.elffile import ELFFile 7 | 8 | 9 | # FIXME: Eventually drop the need for SoC and simulate memory purely with 10 | # a process like in RISCOF tests? This will be pretty invasive. 11 | from examples.attosoc import AttoSoC 12 | 13 | 14 | # Fixture overrides for SoC tests. 15 | # Required because we have to initialize memory before passing to sim fixture. 16 | # Otherwise amaranth 0.5 will throw an "AlreadyElaborated" error. 17 | @pytest.fixture 18 | def mod(request): 19 | m = AttoSoC(num_bytes=0x1000) 20 | 21 | firmware_dir = request.config.rootdir / \ 22 | Path("target/riscv32i-unknown-none-elf/release/examples") 23 | firmware_bin = firmware_dir / "attosoc" 24 | 25 | if not firmware_bin.isfile(): 26 | pytest.skip("attosoc binary not present") 27 | 28 | with open(firmware_bin, "rb") as fp: 29 | def append_bytes(a, b): 30 | return a + b 31 | 32 | def seg_data(seg): 33 | return seg.data() 34 | 35 | segs = ELFFile(fp).iter_segments() 36 | text_ro_and_data_segs = islice(segs, 2) 37 | m.rom = reduce(append_bytes, 38 | map(seg_data, text_ro_and_data_segs), 39 | b"") 40 | 41 | return m 42 | 43 | 44 | # Required because we're wrapping the CPU. 45 | @pytest.fixture 46 | def ucode_panic(mod): 47 | m = mod 48 | 49 | async def ucode_panic(ctx): 50 | addr = 0 51 | prev_addr = 2 52 | count = 0 53 | async for *_, addr in ctx.tick().sample(m.cpu.control.ucoderom.addr): 54 | if addr == 255: 55 | raise AssertionError("microcode panic (not implemented)") 56 | 57 | if prev_addr == addr: 58 | count += 1 59 | if count > 100: 60 | raise AssertionError("microcode probably stuck in " 61 | "infinite loop") 62 | else: 63 | count = 0 64 | 65 | prev_addr = addr 66 | 67 | return ucode_panic 68 | 69 | 70 | # Infrequently-used test mostly for testing address decoding. Should not cause 71 | # failure if user does not have Rust installed. 72 | @pytest.mark.parametrize("clks", [(1.0 / 12e6)]) 73 | @pytest.mark.soc 74 | def test_rust(sim, mod, ucode_panic): 75 | m = mod 76 | 77 | async def io_tb(ctx): 78 | *_, tx = await ctx.tick().sample(m.serial.tx).repeat(2000) 79 | assert tx == 0 80 | 81 | sim.run(testbenches=[io_tb], processes=[ucode_panic]) 82 | -------------------------------------------------------------------------------- /tests/sim/test_ucode.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | import enum 3 | 4 | from amaranth import Fragment, unsigned 5 | from io import StringIO 6 | 7 | from sentinel.ucoderom import UCodeROM 8 | 9 | 10 | M5META_TEST_FILE = """ 11 | space block_ram: width 32, size 256; 12 | 13 | space block_ram; 14 | origin 0; 15 | 16 | fields block_ram: { 17 | foo: width 8, origin 0, default 0; 18 | bar: enum { a = 0; b = 0; c = 1; }, default a; 19 | baz: bool, origin 12, default 0; 20 | }; 21 | 22 | foo => 0, bar => c, baz => true; 23 | foo => 1, bar => b, baz => false; 24 | """ 25 | 26 | 27 | class Bar(enum.Enum): 28 | A = 0 29 | B = 0 30 | C = 1 31 | 32 | 33 | # This is a test by itself because creating the signature from the microcode 34 | # assembly file can be tricky. 35 | def test_ucode_layout_gen(): 36 | m = UCodeROM(main_file=StringIO(M5META_TEST_FILE), 37 | field_map={"foo": unsigned(8), 38 | "bar": Bar, 39 | "baz": unsigned(1)}) 40 | # Use Fragment.get to ensure the Module is marked as used. 41 | Fragment.get(m, None) 42 | 43 | 44 | @pytest.mark.parametrize("mod,clks", [ 45 | (UCodeROM(main_file=StringIO(M5META_TEST_FILE), 46 | field_map={"foo": unsigned(8), 47 | "bar": Bar, 48 | "baz": unsigned(1)}), 49 | 1.0 / 12e6)]) 50 | @pytest.mark.parametrize("dummy", [1, 2]) 51 | @pytest.mark.skip(reason="Not yet implemented.") 52 | def test_twice_init(sim, mod, dummy): 53 | m = mod 54 | 55 | async def ucode_tb(ctx): 56 | ctx.set(m.addr, 0) 57 | ctx.tick() 58 | ctx.set(m.addr, 1) 59 | ctx.tick() 60 | 61 | sim.run(processes=[ucode_tb]) 62 | -------------------------------------------------------------------------------- /tests/sim/test_witness.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | from sentinel.top import Top 3 | 4 | from conftest import RV32Regs, CSRRegs 5 | 6 | 7 | # Semi-autogenerated (script not provided b/c it's a one-off) from a yosys 8 | # witness file for a failed reg_ch0 test at around f3d3e315b7. 9 | # 10 | # While looking at why the trace failed, which was a bug in my formal harness, 11 | # I found _another_ bug that is a legitimate bug in Sentinel. 12 | # Specifically, none of the sim tests before this altered dat_r in the middle 13 | # of an instruction, which seems to hide a few bugs. This particular set 14 | # of dat_r and acks is _intended_ to perform the following insns: 15 | # 16 | # csrrc x8, mstatus, x4 17 | # andi x1, x8, 40 18 | # 19 | # which writes to the nonexistant CSR with address 0b0001. 20 | # 21 | # The witness file is provided for reference; eventually the goal is to 22 | # autogenerate TBs from witness files (and allow the TBs to evolve 23 | # independent of the witness files as Sentinel changes). 24 | @pytest.fixture 25 | def csrrc_bad_rd_process(mod): 26 | m = mod 27 | 28 | async def proc(ctx): 29 | await ctx.tick() 30 | 31 | ctx.set(m.bus.ack, 0b0) 32 | ctx.set(m.bus.dat_r, 0b0) 33 | await ctx.tick() 34 | ctx.set(m.bus.ack, 0b0) 35 | ctx.set(m.bus.dat_r, 0b110000000011111111111111111111) 36 | await ctx.tick() 37 | ctx.set(m.bus.ack, 0b0) 38 | ctx.set(m.bus.dat_r, 0b110000000011111111111111111111) 39 | await ctx.tick() 40 | ctx.set(m.bus.ack, 0b0) 41 | ctx.set(m.bus.dat_r, 0b110000000111111111111111111111) 42 | await ctx.tick() 43 | ctx.set(m.bus.ack, 0b0) 44 | ctx.set(m.bus.dat_r, 0b110000000111111111111111111111) 45 | await ctx.tick() 46 | ctx.set(m.bus.ack, 0b0) 47 | ctx.set(m.bus.dat_r, 0b11110100010000100111111111111111) 48 | await ctx.tick() 49 | ctx.set(m.bus.ack, 0b1) 50 | ctx.set(m.bus.dat_r, 0b110000000000100011010001110011) 51 | await ctx.tick() 52 | ctx.set(m.bus.ack, 0b0) 53 | ctx.set(m.bus.dat_r, 0b10000001110011) 54 | await ctx.tick() 55 | ctx.set(m.bus.ack, 0b1) 56 | ctx.set(m.bus.dat_r, 0b110010000100010010001001110011) 57 | await ctx.tick() 58 | ctx.set(m.bus.ack, 0b0) 59 | ctx.set(m.bus.dat_r, 0b110000100000010100000000010011) 60 | await ctx.tick() 61 | ctx.set(m.bus.ack, 0b0) 62 | ctx.set(m.bus.dat_r, 0b100100011011010100110011) 63 | await ctx.tick() 64 | ctx.set(m.bus.ack, 0b0) 65 | ctx.set(m.bus.dat_r, 0b110100001011000000000110100011) 66 | await ctx.tick() 67 | ctx.set(m.bus.ack, 0b0) 68 | ctx.set(m.bus.dat_r, 0b110100000010011010000101110011) 69 | await ctx.tick() 70 | ctx.set(m.bus.ack, 0b0) 71 | ctx.set(m.bus.dat_r, 0b10010000000011) 72 | await ctx.tick() 73 | ctx.set(m.bus.ack, 0b0) 74 | ctx.set(m.bus.dat_r, 0b110000001000000000000001101111) 75 | await ctx.tick() 76 | ctx.set(m.bus.ack, 0b0) 77 | ctx.set(m.bus.dat_r, 0b100001110000111110011) 78 | await ctx.tick() 79 | 80 | assert ctx.get(m.datapath.csr.adr) == 0b0000 81 | 82 | ctx.set(m.bus.ack, 0b0) 83 | ctx.set(m.bus.dat_r, 0b1000100001000000101001101100011) 84 | await ctx.tick() 85 | ctx.set(m.bus.ack, 0b1) 86 | ctx.set(m.bus.dat_r, 0b10100001000111000010010011) 87 | await ctx.tick() 88 | ctx.set(m.bus.ack, 0b0) 89 | ctx.set(m.bus.dat_r, 0b10110000001000001001011111101111) 90 | await ctx.tick() 91 | ctx.set(m.bus.ack, 0b1) 92 | ctx.set(m.bus.dat_r, 0b100001001101000010010100) 93 | await ctx.tick() 94 | ctx.set(m.bus.ack, 0b0) 95 | ctx.set(m.bus.dat_r, 0b110000010000001000000100001111) 96 | await ctx.tick() 97 | ctx.set(m.bus.ack, 0b0) 98 | ctx.set(m.bus.dat_r, 0b11001000001000010110111) 99 | await ctx.tick() 100 | ctx.set(m.bus.ack, 0b0) 101 | ctx.set(m.bus.dat_r, 0b11111110110110000011000010011100) 102 | await ctx.tick() 103 | ctx.set(m.bus.ack, 0b0) 104 | ctx.set(m.bus.dat_r, 0b11011101010100101000111110010011) 105 | await ctx.tick() 106 | ctx.set(m.bus.ack, 0b0) 107 | ctx.set(m.bus.dat_r, 0b10000010100111000000001101101) 108 | await ctx.tick() 109 | ctx.set(m.bus.ack, 0b1) 110 | ctx.set(m.bus.dat_r, 0b0) 111 | await ctx.tick() 112 | 113 | expected_regs = RV32Regs(R8=0x00001800, PC=8 >> 2) 114 | actual_regs = RV32Regs.from_top_module(m, ctx) 115 | assert expected_regs == actual_regs 116 | 117 | expected_regs = CSRRegs() 118 | actual_regs = CSRRegs.from_top_module(m, ctx) 119 | assert expected_regs == actual_regs 120 | 121 | return proc 122 | 123 | 124 | # class WitnessTop(Elaboratable): 125 | # def __init__(self): 126 | # self.cpu = Top() 127 | 128 | # def elaborate(self, plat): 129 | # m = Module() 130 | # m.submodules.cpu = self.cpu 131 | 132 | # dummy = Signal() 133 | # m.d.sync += dummy.eq(dummy) 134 | 135 | # return m 136 | 137 | 138 | @pytest.mark.parametrize("mod,clks", [(Top(), 1.0 / 12e6)]) 139 | def test_csrrc_bad_rd(sim, csrrc_bad_rd_process, ucode_panic): 140 | sim.run(testbenches=[csrrc_bad_rd_process], 141 | processes=[ucode_panic]) 142 | -------------------------------------------------------------------------------- /tests/sim/witness/csrrc_bad_rd.yw: -------------------------------------------------------------------------------- 1 | { 2 | "format": "Yosys Witness Trace", 3 | "generator": "smtbmc", 4 | "clocks": [ 5 | {"path": ["\\clock"], "edge": "posedge", "offset": 0} 6 | ], 7 | "signals": [ 8 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3532"], "width": 1, "offset": 0, "init_only": false}, 9 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3534"], "width": 1, "offset": 0, "init_only": false}, 10 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3536"], "width": 1, "offset": 0, "init_only": false}, 11 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3538"], "width": 1, "offset": 0, "init_only": false}, 12 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3540"], "width": 1, "offset": 0, "init_only": false}, 13 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3542"], "width": 1, "offset": 0, "init_only": false}, 14 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3544"], "width": 1, "offset": 0, "init_only": false}, 15 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3546"], "width": 1, "offset": 0, "init_only": false}, 16 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3548"], "width": 1, "offset": 0, "init_only": false}, 17 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3550"], "width": 1, "offset": 0, "init_only": false}, 18 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3552"], "width": 1, "offset": 0, "init_only": false}, 19 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3554"], "width": 32, "offset": 0, "init_only": false}, 20 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3556"], "width": 6, "offset": 0, "init_only": false}, 21 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3558"], "width": 5, "offset": 0, "init_only": false}, 22 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3560"], "width": 1, "offset": 0, "init_only": false}, 23 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3562"], "width": 5, "offset": 0, "init_only": false}, 24 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3564"], "width": 5, "offset": 0, "init_only": false}, 25 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3566"], "width": 5, "offset": 0, "init_only": false}, 26 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3568"], "width": 5, "offset": 0, "init_only": false}, 27 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3570"], "width": 32, "offset": 0, "init_only": false}, 28 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3572"], "width": 1, "offset": 0, "init_only": false}, 29 | {"path": ["\\_witness_", "\\anyseq_auto_setundef_cc_533_execute_3574"], "width": 8, "offset": 0, "init_only": false}, 30 | {"path": ["\\clock"], "width": 1, "offset": 0, "init_only": false}, 31 | {"path": ["\\reset"], "width": 1, "offset": 0, "init_only": false}, 32 | {"path": ["\\wrapper", "\\bus__ack"], "width": 1, "offset": 0, "init_only": false}, 33 | {"path": ["\\wrapper", "\\uut", "\\bus__dat_r"], "width": 32, "offset": 0, "init_only": false}, 34 | {"path": ["\\checker_inst", "\\insn_order"], "width": 64, "offset": 0, "init_only": true}, 35 | {"path": ["\\checker_inst", "\\register_index"], "width": 5, "offset": 0, "init_only": true} 36 | ], 37 | "steps": [ 38 | {"bits": "0100000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 39 | {"bits": "0011000000001111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 40 | {"bits": "0011000000001111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 41 | {"bits": "0011000000011111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 42 | {"bits": "0011000000011111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 43 | {"bits": "1111010001000010011111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 44 | {"bits": "0011000000000010001101000111001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 45 | {"bits": "0000000000000000001000000111001100000000000010110000000000000101000001110100000000000000000000000000000000001111111111111111111111111111111000000000000"}, 46 | {"bits": "0011001000010001001000100111001110001010101101100110010000000000100000000000000000000000000000000000001001110011111111111111111111111111111000000000000"}, 47 | {"bits": "0011000010000001010000000001001100001001011100000000000000000000000000010000000000000000000000000000000011000000000000000000000000000000000000000000000"}, 48 | {"bits": "0000000010010001101101010011001100010011111100000000000000000000000000000000000000000000000000000000000110000000010000000000000000000000000000000000000"}, 49 | {"bits": "0011010000101100000000011010001100000000000100000000000000000000000000011000000000000000000000000000000000000000000000000000000000000000000100000000000"}, 50 | {"bits": "0011010000001001101000010111001100000111100100000000000000000000000000001000000000000000000000000000000000001000000000000000000000000000000100000000000"}, 51 | {"bits": "0000000000000000001001000000001100000111110100000000000000000000000000000000000000000000000000000000001011000000000000000000000000000000000000000000000"}, 52 | {"bits": "0011000000100000000000000110111100010110110000000000000000000000000000000000000000000000000000000000000110011101000000000001101000000110110000000000000"}, 53 | {"bits": "0000000000010000111000011111001100000000000100000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000"}, 54 | {"bits": "0100010000100000010100110110001100000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000100000000000"}, 55 | {"bits": "0000001010000100011100001001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 56 | {"bits": "1011000000100000100101111110111100000011000000000000000000000000000001101100000000000000000000000000001001111000000000000000000000000000000100000000000"}, 57 | {"bits": "0000000010000100110100001001010010001011000100000000000000000000000000000110000000000000000000000000000000011111111111111111111110100000000100000000000"}, 58 | {"bits": "0011000001000000100000010000111100000011000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000"}, 59 | {"bits": "0000000001100100000100001011011100000111010100000000000000000000000000000100000000000000000000000000000000000000000000000000000000000111001000000000000"}, 60 | {"bits": "1111111011011000001100001001110000000111011100000000000000000000000000000000000000000000000000000000001011000000010000000000000000000000100100000000000"}, 61 | {"bits": "1101110101010010100011111001001100000000000100000000000000000000000000000000000000000000000000000000000001100000000000000000000000000000000000000000000"}, 62 | {"bits": "0001000001010011100000000110110100010001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 63 | {"bits": "0000000000000000000000000000000010000000001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"} 64 | ] 65 | } 66 | -------------------------------------------------------------------------------- /tests/upstream/README.md: -------------------------------------------------------------------------------- 1 | # Upstream Tests 2 | 3 | Tests from the [upstream tests](https://github.com/riscv-software-src/riscv-tests) 4 | are in this directory. AFAICT, the [RISCOF tests](/tests/riscof/README.md) 5 | are (were?) originally derived from this repository and are more comprehensive. 6 | However, this repo looks easier to start with. 7 | 8 | Make sure `doit` is installed via `pdm install -G dev`. _You must provide your 9 | own copy of `riscv64-unknown-elf-gcc`_. Then, run using `pdm test` or 10 | `pdm test-quick`. 11 | 12 | See [Testing Prerequisites](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html#prerequisites) 13 | and [Sim And Upstream docs](https://sentinel-cpu.readthedocs.io/en/latest/development/testing.html#sim-and-upstream) 14 | for more information. 15 | -------------------------------------------------------------------------------- /tests/upstream/binaries/.gitignore: -------------------------------------------------------------------------------- 1 | *.elf 2 | -------------------------------------------------------------------------------- /tests/upstream/binaries/add: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/add -------------------------------------------------------------------------------- /tests/upstream/binaries/addi: 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/auipc -------------------------------------------------------------------------------- /tests/upstream/binaries/auipc.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/auipc.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffe30> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00000297 auipc t0,0x0 77 | f4: 01428293 addi t0,t0,20 # 104 78 | f8: 34129073 csrw mepc,t0 79 | fc: f1402573 csrr a0,mhartid 80 | 100: 30200073 mret 81 | 82 | 00000104 : 83 | 104: 00200193 li gp,2 84 | 108: 00002517 auipc a0,0x2 85 | 10c: 71c50513 addi a0,a0,1820 # 2824 <_end+0x2654> 86 | 110: 004005ef jal a1,114 87 | 114: 40b50533 sub a0,a0,a1 88 | 118: 000023b7 lui t2,0x2 89 | 11c: 71038393 addi t2,t2,1808 # 2710 <_end+0x2540> 90 | 120: 02751463 bne a0,t2,148 91 | 92 | 00000124 : 93 | 124: 00300193 li gp,3 94 | 128: ffffe517 auipc a0,0xffffe 95 | 12c: 8fc50513 addi a0,a0,-1796 # ffffda24 <_end+0xffffd854> 96 | 130: 004005ef jal a1,134 97 | 134: 40b50533 sub a0,a0,a1 98 | 138: ffffe3b7 lui t2,0xffffe 99 | 13c: 8f038393 addi t2,t2,-1808 # ffffd8f0 <_end+0xffffd720> 100 | 140: 00751463 bne a0,t2,148 101 | 144: 02301063 bne zero,gp,164 102 | 103 | 00000148 : 104 | 148: 0ff0000f fence 105 | 14c: 00018063 beqz gp,14c 106 | 150: 00119193 slli gp,gp,0x1 107 | 154: 0011e193 ori gp,gp,1 108 | 158: 05d00893 li a7,93 109 | 15c: 00018513 mv a0,gp 110 | 160: 00000073 ecall 111 | 112 | 00000164 : 113 | 164: 0ff0000f fence 114 | 168: 00100193 li gp,1 115 | 16c: 05d00893 li a7,93 116 | 170: 00000513 li a0,0 117 | 174: 00000073 ecall 118 | 178: c0001073 unimp 119 | -------------------------------------------------------------------------------- /tests/upstream/binaries/beq: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/beq -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/fence_i -------------------------------------------------------------------------------- /tests/upstream/binaries/fence_i.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/fence_i.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffd90> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00000297 auipc t0,0x0 77 | f4: 01428293 addi t0,t0,20 # 104 78 | f8: 34129073 csrw mepc,t0 79 | fc: f1402573 csrr a0,mhartid 80 | 100: 30200073 mret 81 | 104: 06f00693 li a3,111 82 | 108: 25001503 lh a0,592(zero) # 250 83 | 10c: 25201583 lh a1,594(zero) # 252 84 | 110: 00000013 nop 85 | 114: 00000013 nop 86 | 118: 00000013 nop 87 | 11c: 00000013 nop 88 | 120: 00000013 nop 89 | 124: 00000013 nop 90 | 128: 00000013 nop 91 | 12c: 00000013 nop 92 | 130: 00000013 nop 93 | 134: 00000013 nop 94 | 138: 00000013 nop 95 | 13c: 00000013 nop 96 | 140: 24a01a23 sh a0,596(zero) # 254 97 | 144: 24b01b23 sh a1,598(zero) # 256 98 | 148: 0000100f fence.i 99 | 14c: 25400793 li a5,596 100 | 150: 00078367 jalr t1,a5 101 | 102 | 00000154 : 103 | 154: 00200193 li gp,2 104 | 158: 00000013 nop 105 | 15c: 1bc00393 li t2,444 106 | 160: 02769e63 bne a3,t2,19c 107 | 164: 06400713 li a4,100 108 | 168: fff70713 addi a4,a4,-1 109 | 16c: fe071ee3 bnez a4,168 110 | 170: 24a01e23 sh a0,604(zero) # 25c 111 | 174: 24b01f23 sh a1,606(zero) # 25e 112 | 178: 0000100f fence.i 113 | 17c: 00000013 nop 114 | 180: 25c00793 li a5,604 115 | 184: 00078367 jalr t1,a5 116 | 117 | 00000188 : 118 | 188: 00300193 li gp,3 119 | 18c: 00000013 nop 120 | 190: 30900393 li t2,777 121 | 194: 00769463 bne a3,t2,19c 122 | 198: 02301063 bne zero,gp,1b8 123 | 124 | 0000019c : 125 | 19c: 0ff0000f fence 126 | 1a0: 00018063 beqz gp,1a0 127 | 1a4: 00119193 slli gp,gp,0x1 128 | 1a8: 0011e193 ori gp,gp,1 129 | 1ac: 05d00893 li a7,93 130 | 1b0: 00018513 mv a0,gp 131 | 1b4: 00000073 ecall 132 | 133 | 000001b8 : 134 | 1b8: 0ff0000f fence 135 | 1bc: 00100193 li gp,1 136 | 1c0: 05d00893 li a7,93 137 | 1c4: 00000513 li a0,0 138 | 1c8: 00000073 ecall 139 | 1cc: c0001073 unimp 140 | 1d0: 0000 unimp 141 | 1d2: 0000 unimp 142 | 1d4: 0000 unimp 143 | 1d6: 0000 unimp 144 | 1d8: 0000 unimp 145 | 1da: 0000 unimp 146 | 1dc: 0000 unimp 147 | 1de: 0000 unimp 148 | 149 | Disassembly of section .data: 150 | 151 | 00000250 : 152 | 250: 14d68693 addi a3,a3,333 153 | 254: 0de68693 addi a3,a3,222 154 | 258: 000307e7 jalr a5,t1 155 | 25c: 22b68693 addi a3,a3,555 156 | 260: 000307e7 jalr a5,t1 157 | 264: 0000 unimp 158 | 266: 0000 unimp 159 | 268: 0000 unimp 160 | 26a: 0000 unimp 161 | 26c: 0000 unimp 162 | 26e: 0000 unimp 163 | -------------------------------------------------------------------------------- /tests/upstream/binaries/illegal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/illegal -------------------------------------------------------------------------------- /tests/upstream/binaries/jal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/jal -------------------------------------------------------------------------------- /tests/upstream/binaries/jal.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/jal.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffdb0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00000297 auipc t0,0x0 77 | f4: 01428293 addi t0,t0,20 # 104 78 | f8: 34129073 csrw mepc,t0 79 | fc: f1402573 csrr a0,mhartid 80 | 100: 30200073 mret 81 | 82 | 00000104 : 83 | 104: 00200193 li gp,2 84 | 108: 00000093 li ra,0 85 | 10c: 0100026f jal tp,11c 86 | 87 | 00000110 : 88 | 110: 00000013 nop 89 | 114: 00000013 nop 90 | 118: 0400006f j 158 91 | 92 | 0000011c : 93 | 11c: 00000117 auipc sp,0x0 94 | 120: ff410113 addi sp,sp,-12 # 110 95 | 124: 02411a63 bne sp,tp,158 96 | 97 | 00000128 : 98 | 128: 00300193 li gp,3 99 | 12c: 00100093 li ra,1 100 | 130: 0140006f j 144 101 | 134: 00108093 addi ra,ra,1 102 | 138: 00108093 addi ra,ra,1 103 | 13c: 00108093 addi ra,ra,1 104 | 140: 00108093 addi ra,ra,1 105 | 144: 00108093 addi ra,ra,1 106 | 148: 00108093 addi ra,ra,1 107 | 14c: 00300393 li t2,3 108 | 150: 00709463 bne ra,t2,158 109 | 154: 02301063 bne zero,gp,174 110 | 111 | 00000158 : 112 | 158: 0ff0000f fence 113 | 15c: 00018063 beqz gp,15c 114 | 160: 00119193 slli gp,gp,0x1 115 | 164: 0011e193 ori gp,gp,1 116 | 168: 05d00893 li a7,93 117 | 16c: 00018513 mv a0,gp 118 | 170: 00000073 ecall 119 | 120 | 00000174 : 121 | 174: 0ff0000f fence 122 | 178: 00100193 li gp,1 123 | 17c: 05d00893 li a7,93 124 | 180: 00000513 li a0,0 125 | 184: 00000073 ecall 126 | 188: c0001073 unimp 127 | 18c: 0000 unimp 128 | 18e: 0000 unimp 129 | 190: 0000 unimp 130 | 192: 0000 unimp 131 | 194: 0000 unimp 132 | 196: 0000 unimp 133 | 198: 0000 unimp 134 | 19a: 0000 unimp 135 | 19c: 0000 unimp 136 | 19e: 0000 unimp 137 | 1a0: 0000 unimp 138 | 1a2: 0000 unimp 139 | 1a4: 0000 unimp 140 | 1a6: 0000 unimp 141 | 1a8: 0000 unimp 142 | 1aa: 0000 unimp 143 | 1ac: 0000 unimp 144 | 1ae: 0000 unimp 145 | 1b0: 0000 unimp 146 | 1b2: 0000 unimp 147 | 1b4: 0000 unimp 148 | 1b6: 0000 unimp 149 | 1b8: 0000 unimp 150 | 1ba: 0000 unimp 151 | 1bc: 0000 unimp 152 | 1be: 0000 unimp 153 | 1c0: 0000 unimp 154 | 1c2: 0000 unimp 155 | -------------------------------------------------------------------------------- /tests/upstream/binaries/jalr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/jalr -------------------------------------------------------------------------------- /tests/upstream/binaries/jalr.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/jalr.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffd30> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00000297 auipc t0,0x0 77 | f4: 01428293 addi t0,t0,20 # 104 78 | f8: 34129073 csrw mepc,t0 79 | fc: f1402573 csrr a0,mhartid 80 | 100: 30200073 mret 81 | 82 | 00000104 : 83 | 104: 00200193 li gp,2 84 | 108: 00000293 li t0,0 85 | 10c: 00000317 auipc t1,0x0 86 | 110: 01030313 addi t1,t1,16 # 11c 87 | 114: 000302e7 jalr t0,t1 88 | 89 | 00000118 : 90 | 118: 0e00006f j 1f8 91 | 92 | 0000011c : 93 | 11c: 00000317 auipc t1,0x0 94 | 120: ffc30313 addi t1,t1,-4 # 118 95 | 124: 0c629a63 bne t0,t1,1f8 96 | 97 | 00000128 : 98 | 128: 00300193 li gp,3 99 | 12c: 00000297 auipc t0,0x0 100 | 130: 01028293 addi t0,t0,16 # 13c 101 | 134: 000282e7 jalr t0,t0 102 | 103 | 00000138 : 104 | 138: 0c00006f j 1f8 105 | 106 | 0000013c : 107 | 13c: 00000317 auipc t1,0x0 108 | 140: ffc30313 addi t1,t1,-4 # 138 109 | 144: 0a629a63 bne t0,t1,1f8 110 | 111 | 00000148 : 112 | 148: 00400193 li gp,4 113 | 14c: 00000213 li tp,0 114 | 150: 00000317 auipc t1,0x0 115 | 154: 01030313 addi t1,t1,16 # 160 116 | 158: 000306e7 jalr a3,t1 117 | 15c: 08301e63 bne zero,gp,1f8 118 | 160: 00120213 addi tp,tp,1 # 1 <_start+0x1> 119 | 164: 00200293 li t0,2 120 | 168: fe5214e3 bne tp,t0,150 121 | 122 | 0000016c : 123 | 16c: 00500193 li gp,5 124 | 170: 00000213 li tp,0 125 | 174: 00000317 auipc t1,0x0 126 | 178: 01430313 addi t1,t1,20 # 188 127 | 17c: 00000013 nop 128 | 180: 000306e7 jalr a3,t1 129 | 184: 06301a63 bne zero,gp,1f8 130 | 188: 00120213 addi tp,tp,1 # 1 <_start+0x1> 131 | 18c: 00200293 li t0,2 132 | 190: fe5212e3 bne tp,t0,174 133 | 134 | 00000194 : 135 | 194: 00600193 li gp,6 136 | 198: 00000213 li tp,0 137 | 19c: 00000317 auipc t1,0x0 138 | 1a0: 01830313 addi t1,t1,24 # 1b4 139 | 1a4: 00000013 nop 140 | 1a8: 00000013 nop 141 | 1ac: 000306e7 jalr a3,t1 142 | 1b0: 04301463 bne zero,gp,1f8 143 | 1b4: 00120213 addi tp,tp,1 # 1 <_start+0x1> 144 | 1b8: 00200293 li t0,2 145 | 1bc: fe5210e3 bne tp,t0,19c 146 | 147 | 000001c0 : 148 | 1c0: 00700193 li gp,7 149 | 1c4: 00100293 li t0,1 150 | 1c8: 00000317 auipc t1,0x0 151 | 1cc: 01c30313 addi t1,t1,28 # 1e4 152 | 1d0: ffc30067 jr -4(t1) 153 | 1d4: 00128293 addi t0,t0,1 154 | 1d8: 00128293 addi t0,t0,1 155 | 1dc: 00128293 addi t0,t0,1 156 | 1e0: 00128293 addi t0,t0,1 157 | 1e4: 00128293 addi t0,t0,1 158 | 1e8: 00128293 addi t0,t0,1 159 | 1ec: 00400393 li t2,4 160 | 1f0: 00729463 bne t0,t2,1f8 161 | 1f4: 02301063 bne zero,gp,214 162 | 163 | 000001f8 : 164 | 1f8: 0ff0000f fence 165 | 1fc: 00018063 beqz gp,1fc 166 | 200: 00119193 slli gp,gp,0x1 167 | 204: 0011e193 ori gp,gp,1 168 | 208: 05d00893 li a7,93 169 | 20c: 00018513 mv a0,gp 170 | 210: 00000073 ecall 171 | 172 | 00000214 : 173 | 214: 0ff0000f fence 174 | 218: 00100193 li gp,1 175 | 21c: 05d00893 li a7,93 176 | 220: 00000513 li a0,0 177 | 224: 00000073 ecall 178 | 228: c0001073 unimp 179 | 22c: 0000 unimp 180 | 22e: 0000 unimp 181 | 230: 0000 unimp 182 | 232: 0000 unimp 183 | 234: 0000 unimp 184 | 236: 0000 unimp 185 | 238: 0000 unimp 186 | 23a: 0000 unimp 187 | 23c: 0000 unimp 188 | 23e: 0000 unimp 189 | 240: 0000 unimp 190 | 242: 0000 unimp 191 | -------------------------------------------------------------------------------- /tests/upstream/binaries/lb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lb -------------------------------------------------------------------------------- /tests/upstream/binaries/lbu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lbu -------------------------------------------------------------------------------- /tests/upstream/binaries/lh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lh -------------------------------------------------------------------------------- /tests/upstream/binaries/lh-misaligned: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lh-misaligned -------------------------------------------------------------------------------- /tests/upstream/binaries/lh-misaligned.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/lh-misaligned.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 164f0f13 addi t5,t5,356 # 174 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffde0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15e0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: 20100793 li a5,513 88 | 118: 21000093 li ra,528 89 | 11c: 00009703 lh a4,0(ra) 90 | 120: 20100393 li t2,513 91 | 124: 02771063 bne a4,t2,144 92 | 93 | 00000128 : 94 | 128: 00300193 li gp,3 95 | 12c: 30200793 li a5,770 96 | 130: 21000093 li ra,528 97 | 134: 00109703 lh a4,1(ra) 98 | 138: 30200393 li t2,770 99 | 13c: 00771463 bne a4,t2,144 100 | 140: 02301063 bne zero,gp,160 101 | 102 | 00000144 : 103 | 144: 0ff0000f fence 104 | 148: 00018063 beqz gp,148 105 | 14c: 00119193 slli gp,gp,0x1 106 | 150: 0011e193 ori gp,gp,1 107 | 154: 05d00893 li a7,93 108 | 158: 00018513 mv a0,gp 109 | 15c: 00000073 ecall 110 | 111 | 00000160 : 112 | 160: 0ff0000f fence 113 | 164: 00100193 li gp,1 114 | 168: 05d00893 li a7,93 115 | 16c: 00000513 li a0,0 116 | 170: 00000073 ecall 117 | 118 | 00000174 : 119 | 174: 00400293 li t0,4 120 | 178: 34202373 csrr t1,mcause 121 | 17c: fc6294e3 bne t0,t1,144 122 | 180: 00078713 mv a4,a5 123 | 184: 341022f3 csrr t0,mepc 124 | 188: 00428293 addi t0,t0,4 125 | 18c: 34129073 csrw mepc,t0 126 | 190: 30200073 mret 127 | 194: c0001073 unimp 128 | 198: 0000 unimp 129 | 19a: 0000 unimp 130 | 19c: 0000 unimp 131 | 19e: 0000 unimp 132 | 1a0: 0000 unimp 133 | 1a2: 0000 unimp 134 | 1a4: 0000 unimp 135 | 1a6: 0000 unimp 136 | 1a8: 0000 unimp 137 | 1aa: 0000 unimp 138 | 1ac: 0000 unimp 139 | 1ae: 0000 unimp 140 | 1b0: 0000 unimp 141 | 1b2: 0000 unimp 142 | 1b4: 0000 unimp 143 | 1b6: 0000 unimp 144 | 1b8: 0000 unimp 145 | 1ba: 0000 unimp 146 | 147 | Disassembly of section .data: 148 | 149 | 00000210 : 150 | 210: 0201 addi tp,tp,0 151 | 212: 00000403 lb s0,0(zero) # 0 <_start> 152 | 216: 0000 unimp 153 | 218: 0000 unimp 154 | 21a: 0000 unimp 155 | 21c: 0000 unimp 156 | 21e: 0000 unimp 157 | -------------------------------------------------------------------------------- /tests/upstream/binaries/lhu: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lhu -------------------------------------------------------------------------------- /tests/upstream/binaries/lui: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lui -------------------------------------------------------------------------------- /tests/upstream/binaries/lui.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/lui.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffdb0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00000297 auipc t0,0x0 77 | f4: 01428293 addi t0,t0,20 # 104 78 | f8: 34129073 csrw mepc,t0 79 | fc: f1402573 csrr a0,mhartid 80 | 100: 30200073 mret 81 | 82 | 00000104 : 83 | 104: 00200193 li gp,2 84 | 108: 000000b7 lui ra,0x0 85 | 10c: 00000393 li t2,0 86 | 110: 04709a63 bne ra,t2,164 87 | 88 | 00000114 : 89 | 114: 00300193 li gp,3 90 | 118: fffff0b7 lui ra,0xfffff 91 | 11c: 4010d093 srai ra,ra,0x1 92 | 120: 80000393 li t2,-2048 93 | 124: 04709063 bne ra,t2,164 94 | 95 | 00000128 : 96 | 128: 00400193 li gp,4 97 | 12c: 7ffff0b7 lui ra,0x7ffff 98 | 130: 4140d093 srai ra,ra,0x14 99 | 134: 7ff00393 li t2,2047 100 | 138: 02709663 bne ra,t2,164 101 | 102 | 0000013c : 103 | 13c: 00500193 li gp,5 104 | 140: 800000b7 lui ra,0x80000 105 | 144: 4140d093 srai ra,ra,0x14 106 | 148: 80000393 li t2,-2048 107 | 14c: 00709c63 bne ra,t2,164 108 | 109 | 00000150 : 110 | 150: 00600193 li gp,6 111 | 154: 80000037 lui zero,0x80000 112 | 158: 00000393 li t2,0 113 | 15c: 00701463 bne zero,t2,164 114 | 160: 02301063 bne zero,gp,180 115 | 116 | 00000164 : 117 | 164: 0ff0000f fence 118 | 168: 00018063 beqz gp,168 119 | 16c: 00119193 slli gp,gp,0x1 120 | 170: 0011e193 ori gp,gp,1 121 | 174: 05d00893 li a7,93 122 | 178: 00018513 mv a0,gp 123 | 17c: 00000073 ecall 124 | 125 | 00000180 : 126 | 180: 0ff0000f fence 127 | 184: 00100193 li gp,1 128 | 188: 05d00893 li a7,93 129 | 18c: 00000513 li a0,0 130 | 190: 00000073 ecall 131 | 194: c0001073 unimp 132 | 198: 0000 unimp 133 | 19a: 0000 unimp 134 | 19c: 0000 unimp 135 | 19e: 0000 unimp 136 | 1a0: 0000 unimp 137 | 1a2: 0000 unimp 138 | 1a4: 0000 unimp 139 | 1a6: 0000 unimp 140 | 1a8: 0000 unimp 141 | 1aa: 0000 unimp 142 | 1ac: 0000 unimp 143 | 1ae: 0000 unimp 144 | 1b0: 0000 unimp 145 | 1b2: 0000 unimp 146 | 1b4: 0000 unimp 147 | 1b6: 0000 unimp 148 | 1b8: 0000 unimp 149 | 1ba: 0000 unimp 150 | 1bc: 0000 unimp 151 | 1be: 0000 unimp 152 | 1c0: 0000 unimp 153 | 1c2: 0000 unimp 154 | -------------------------------------------------------------------------------- /tests/upstream/binaries/lw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lw -------------------------------------------------------------------------------- /tests/upstream/binaries/lw-misaligned: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/lw-misaligned -------------------------------------------------------------------------------- /tests/upstream/binaries/lw-misaligned.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/lw-misaligned.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 1b4f0f13 addi t5,t5,436 # 1c4 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffda0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15a0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: 040307b7 lui a5,0x4030 88 | 118: 20178793 addi a5,a5,513 # 4030201 <_end+0x402ffa1> 89 | 11c: 25000093 li ra,592 90 | 120: 0000a703 lw a4,0(ra) 91 | 124: 040303b7 lui t2,0x4030 92 | 128: 20138393 addi t2,t2,513 # 4030201 <_end+0x402ffa1> 93 | 12c: 06771463 bne a4,t2,194 94 | 95 | 00000130 : 96 | 130: 00300193 li gp,3 97 | 134: 050407b7 lui a5,0x5040 98 | 138: 30278793 addi a5,a5,770 # 5040302 <_end+0x50400a2> 99 | 13c: 25000093 li ra,592 100 | 140: 0010a703 lw a4,1(ra) 101 | 144: 050403b7 lui t2,0x5040 102 | 148: 30238393 addi t2,t2,770 # 5040302 <_end+0x50400a2> 103 | 14c: 04771463 bne a4,t2,194 104 | 105 | 00000150 : 106 | 150: 00400193 li gp,4 107 | 154: 060507b7 lui a5,0x6050 108 | 158: 40378793 addi a5,a5,1027 # 6050403 <_end+0x60501a3> 109 | 15c: 25000093 li ra,592 110 | 160: 0020a703 lw a4,2(ra) 111 | 164: 060503b7 lui t2,0x6050 112 | 168: 40338393 addi t2,t2,1027 # 6050403 <_end+0x60501a3> 113 | 16c: 02771463 bne a4,t2,194 114 | 115 | 00000170 : 116 | 170: 00500193 li gp,5 117 | 174: 070607b7 lui a5,0x7060 118 | 178: 50478793 addi a5,a5,1284 # 7060504 <_end+0x70602a4> 119 | 17c: 25000093 li ra,592 120 | 180: 0030a703 lw a4,3(ra) 121 | 184: 070603b7 lui t2,0x7060 122 | 188: 50438393 addi t2,t2,1284 # 7060504 <_end+0x70602a4> 123 | 18c: 00771463 bne a4,t2,194 124 | 190: 02301063 bne zero,gp,1b0 125 | 126 | 00000194 : 127 | 194: 0ff0000f fence 128 | 198: 00018063 beqz gp,198 129 | 19c: 00119193 slli gp,gp,0x1 130 | 1a0: 0011e193 ori gp,gp,1 131 | 1a4: 05d00893 li a7,93 132 | 1a8: 00018513 mv a0,gp 133 | 1ac: 00000073 ecall 134 | 135 | 000001b0 : 136 | 1b0: 0ff0000f fence 137 | 1b4: 00100193 li gp,1 138 | 1b8: 05d00893 li a7,93 139 | 1bc: 00000513 li a0,0 140 | 1c0: 00000073 ecall 141 | 142 | 000001c4 : 143 | 1c4: 00400293 li t0,4 144 | 1c8: 34202373 csrr t1,mcause 145 | 1cc: fc6294e3 bne t0,t1,194 146 | 1d0: 00078713 mv a4,a5 147 | 1d4: 341022f3 csrr t0,mepc 148 | 1d8: 00428293 addi t0,t0,4 149 | 1dc: 34129073 csrw mepc,t0 150 | 1e0: 30200073 mret 151 | 1e4: c0001073 unimp 152 | 1e8: 0000 unimp 153 | 1ea: 0000 unimp 154 | 1ec: 0000 unimp 155 | 1ee: 0000 unimp 156 | 1f0: 0000 unimp 157 | 1f2: 0000 unimp 158 | 159 | Disassembly of section .data: 160 | 161 | 00000250 : 162 | 250: 0201 addi tp,tp,0 163 | 252: 06050403 lb s0,96(a0) 164 | 256: 00000807 0x807 165 | 25a: 0000 unimp 166 | 25c: 0000 unimp 167 | 25e: 0000 unimp 168 | -------------------------------------------------------------------------------- /tests/upstream/binaries/ma_addr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/ma_addr -------------------------------------------------------------------------------- /tests/upstream/binaries/ma_data: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/ma_data -------------------------------------------------------------------------------- /tests/upstream/binaries/ma_fetch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/ma_fetch -------------------------------------------------------------------------------- /tests/upstream/binaries/mcsr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/mcsr -------------------------------------------------------------------------------- /tests/upstream/binaries/mcsr.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/mcsr.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffdf0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15f0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: 30102573 csrr a0,misa 88 | 118: 01e55513 srli a0,a0,0x1e 89 | 11c: 00100393 li t2,1 90 | 120: 02751863 bne a0,t2,150 91 | 92 | 00000124 : 93 | 124: 00300193 li gp,3 94 | 128: f1402573 csrr a0,mhartid 95 | 12c: 00000393 li t2,0 96 | 130: 02751063 bne a0,t2,150 97 | 134: f1302573 csrr a0,mimpid 98 | 138: f1202573 csrr a0,marchid 99 | 13c: f1102573 csrr a0,mvendorid 100 | 140: 00000293 li t0,0 101 | 144: 3052a073 csrs mtvec,t0 102 | 148: 3412a073 csrs mepc,t0 103 | 14c: 02301063 bne zero,gp,16c 104 | 105 | 00000150 : 106 | 150: 0ff0000f fence 107 | 154: 00018063 beqz gp,154 108 | 158: 00119193 slli gp,gp,0x1 109 | 15c: 0011e193 ori gp,gp,1 110 | 160: 05d00893 li a7,93 111 | 164: 00018513 mv a0,gp 112 | 168: 00000073 ecall 113 | 114 | 0000016c : 115 | 16c: 0ff0000f fence 116 | 170: 00100193 li gp,1 117 | 174: 05d00893 li a7,93 118 | 178: 00000513 li a0,0 119 | 17c: 00000073 ecall 120 | 180: c0001073 unimp 121 | -------------------------------------------------------------------------------- /tests/upstream/binaries/or: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/or -------------------------------------------------------------------------------- /tests/upstream/binaries/ori: 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-------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/sbreak.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 140f0f13 addi t5,t5,320 # 150 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffdf0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15f0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 110: 00200193 li gp,2 85 | 86 | 00000114 : 87 | 114: 00100073 ebreak 88 | 118: 0080006f j 120 89 | 11c: 02301063 bne zero,gp,13c 90 | 91 | 00000120 : 92 | 120: 0ff0000f fence 93 | 124: 00018063 beqz gp,124 94 | 128: 00119193 slli gp,gp,0x1 95 | 12c: 0011e193 ori gp,gp,1 96 | 130: 05d00893 li a7,93 97 | 134: 00018513 mv a0,gp 98 | 138: 00000073 ecall 99 | 100 | 0000013c : 101 | 13c: 0ff0000f fence 102 | 140: 00100193 li gp,1 103 | 144: 05d00893 li a7,93 104 | 148: 00000513 li a0,0 105 | 14c: 00000073 ecall 106 | 107 | 00000150 : 108 | 150: 00300313 li t1,3 109 | 154: 342022f3 csrr t0,mcause 110 | 158: 305023f3 csrr t2,mtvec 111 | 15c: 0023f393 andi t2,t2,2 112 | 160: 00038463 beqz t2,168 113 | 164: 0ff2f293 andi t0,t0,255 114 | 115 | 00000168 : 116 | 168: fa629ce3 bne t0,t1,120 117 | 16c: 00000317 auipc t1,0x0 118 | 170: fa830313 addi t1,t1,-88 # 114 119 | 174: 341022f3 csrr t0,mepc 120 | 178: fa6294e3 bne t0,t1,120 121 | 17c: fc1ff06f j 13c 122 | 180: c0001073 unimp 123 | -------------------------------------------------------------------------------- /tests/upstream/binaries/scall: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/scall -------------------------------------------------------------------------------- /tests/upstream/binaries/scall.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/scall.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 180f0f13 addi t5,t5,384 # 190 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffdb0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15b0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 110: 00200193 li gp,2 85 | 114: 00800313 li t1,8 86 | 118: 000022b7 lui t0,0x2 87 | 11c: 80028293 addi t0,t0,-2048 # 1800 <_end+0x15b0> 88 | 120: 3002b073 csrc mstatus,t0 89 | 124: 300023f3 csrr t2,mstatus 90 | 128: 0072f2b3 and t0,t0,t2 91 | 12c: 00028463 beqz t0,134 92 | 130: 00b00313 li t1,11 93 | 134: 000022b7 lui t0,0x2 94 | 138: 80028293 addi t0,t0,-2048 # 1800 <_end+0x15b0> 95 | 13c: 3002b073 csrc mstatus,t0 96 | 140: 00000297 auipc t0,0x0 97 | 144: 01028293 addi t0,t0,16 # 150 98 | 148: 34129073 csrw mepc,t0 99 | 14c: 30200073 mret 100 | 150: 00100193 li gp,1 101 | 102 | 00000154 : 103 | 154: 00000073 ecall 104 | 158: 0080006f j 160 105 | 15c: 02301063 bne zero,gp,17c 106 | 107 | 00000160 : 108 | 160: 0ff0000f fence 109 | 164: 00018063 beqz gp,164 110 | 168: 00119193 slli gp,gp,0x1 111 | 16c: 0011e193 ori gp,gp,1 112 | 170: 05d00893 li a7,93 113 | 174: 00018513 mv a0,gp 114 | 178: 00000073 ecall 115 | 116 | 0000017c : 117 | 17c: 0ff0000f fence 118 | 180: 00100193 li gp,1 119 | 184: 05d00893 li a7,93 120 | 188: 00000513 li a0,0 121 | 18c: 00000073 ecall 122 | 123 | 00000190 : 124 | 190: 342022f3 csrr t0,mcause 125 | 194: 305023f3 csrr t2,mtvec 126 | 198: 0023f393 andi t2,t2,2 127 | 19c: 00038463 beqz t2,1a4 128 | 1a0: 0ff2f293 andi t0,t0,255 129 | 130 | 000001a4 : 131 | 1a4: fa629ee3 bne t0,t1,160 132 | 1a8: 00000397 auipc t2,0x0 133 | 1ac: fac38393 addi t2,t2,-84 # 154 134 | 1b0: 341022f3 csrr t0,mepc 135 | 1b4: fa7296e3 bne t0,t2,160 136 | 1b8: fc5ff06f j 17c 137 | 1bc: c0001073 unimp 138 | 1c0: 0000 unimp 139 | 1c2: 0000 unimp 140 | -------------------------------------------------------------------------------- /tests/upstream/binaries/sh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/sh -------------------------------------------------------------------------------- /tests/upstream/binaries/sh-misaligned: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/sh-misaligned -------------------------------------------------------------------------------- /tests/upstream/binaries/sh-misaligned.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/sh-misaligned.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 19cf0f13 addi t5,t5,412 # 1ac 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffda0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15a0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: 25000093 li ra,592 88 | 118: 00001137 lui sp,0x1 89 | 11c: 23410113 addi sp,sp,564 # 1234 <_end+0xfd4> 90 | 120: 00000797 auipc a5,0x0 91 | 124: 01478793 addi a5,a5,20 # 134 92 | 128: 00209023 sh sp,0(ra) 93 | 12c: 00009703 lh a4,0(ra) 94 | 130: 0080006f j 138 95 | 134: 00010713 mv a4,sp 96 | 138: 000013b7 lui t2,0x1 97 | 13c: 23438393 addi t2,t2,564 # 1234 <_end+0xfd4> 98 | 140: 02771e63 bne a4,t2,17c 99 | 100 | 00000144 : 101 | 144: 00300193 li gp,3 102 | 148: 25000093 li ra,592 103 | 14c: 00005137 lui sp,0x5 104 | 150: 67810113 addi sp,sp,1656 # 5678 <_end+0x5418> 105 | 154: 00000797 auipc a5,0x0 106 | 158: 01478793 addi a5,a5,20 # 168 107 | 15c: 002090a3 sh sp,1(ra) 108 | 160: 00109703 lh a4,1(ra) 109 | 164: 0080006f j 16c 110 | 168: 00010713 mv a4,sp 111 | 16c: 000053b7 lui t2,0x5 112 | 170: 67838393 addi t2,t2,1656 # 5678 <_end+0x5418> 113 | 174: 00771463 bne a4,t2,17c 114 | 178: 02301063 bne zero,gp,198 115 | 116 | 0000017c : 117 | 17c: 0ff0000f fence 118 | 180: 00018063 beqz gp,180 119 | 184: 00119193 slli gp,gp,0x1 120 | 188: 0011e193 ori gp,gp,1 121 | 18c: 05d00893 li a7,93 122 | 190: 00018513 mv a0,gp 123 | 194: 00000073 ecall 124 | 125 | 00000198 : 126 | 198: 0ff0000f fence 127 | 19c: 00100193 li gp,1 128 | 1a0: 05d00893 li a7,93 129 | 1a4: 00000513 li a0,0 130 | 1a8: 00000073 ecall 131 | 132 | 000001ac : 133 | 1ac: 00600293 li t0,6 134 | 1b0: 34202373 csrr t1,mcause 135 | 1b4: fc6294e3 bne t0,t1,17c 136 | 1b8: 34179073 csrw mepc,a5 137 | 1bc: 30200073 mret 138 | 1c0: c0001073 unimp 139 | 1c4: 0000 unimp 140 | 1c6: 0000 unimp 141 | 1c8: 0000 unimp 142 | 1ca: 0000 unimp 143 | 1cc: 0000 unimp 144 | 1ce: 0000 unimp 145 | 1d0: 0000 unimp 146 | 1d2: 0000 unimp 147 | 1d4: 0000 unimp 148 | 1d6: 0000 unimp 149 | 1d8: 0000 unimp 150 | 1da: 0000 unimp 151 | 1dc: 0000 unimp 152 | 1de: 0000 unimp 153 | 1e0: 0000 unimp 154 | 1e2: 0000 unimp 155 | 1e4: 0000 unimp 156 | 1e6: 0000 unimp 157 | 1e8: 0000 unimp 158 | 1ea: 0000 unimp 159 | 1ec: 0000 unimp 160 | 1ee: 0000 unimp 161 | 1f0: 0000 unimp 162 | 1f2: 0000 unimp 163 | 1f4: 0000 unimp 164 | 1f6: 0000 unimp 165 | 1f8: 0000 unimp 166 | 1fa: 0000 unimp 167 | 168 | Disassembly of section .data: 169 | 170 | 00000250 : 171 | 250: 0000 unimp 172 | 252: 0000 unimp 173 | 254: 0000 unimp 174 | 256: 0000 unimp 175 | 258: 0000 unimp 176 | 25a: 0000 unimp 177 | 25c: 0000 unimp 178 | 25e: 0000 unimp 179 | -------------------------------------------------------------------------------- /tests/upstream/binaries/shamt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/shamt -------------------------------------------------------------------------------- /tests/upstream/binaries/shamt.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/shamt.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 158f0f13 addi t5,t5,344 # 168 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffdf0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x15f0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: 00100513 li a0,1 88 | 118: 01051513 slli a0,a0,0x10 89 | 11c: 000103b7 lui t2,0x10 90 | 120: 00751c63 bne a0,t2,138 91 | 92 | 00000124 : 93 | 124: 00300193 li gp,3 94 | 128: 02051513 slli a0,a0,0x20 95 | 12c: 00100393 li t2,1 96 | 130: 00701463 bne zero,t2,138 97 | 134: 02301063 bne zero,gp,154 98 | 99 | 00000138 : 100 | 138: 0ff0000f fence 101 | 13c: 00018063 beqz gp,13c 102 | 140: 00119193 slli gp,gp,0x1 103 | 144: 0011e193 ori gp,gp,1 104 | 148: 05d00893 li a7,93 105 | 14c: 00018513 mv a0,gp 106 | 150: 00000073 ecall 107 | 108 | 00000154 : 109 | 154: 0ff0000f fence 110 | 158: 00100193 li gp,1 111 | 15c: 05d00893 li a7,93 112 | 160: 00000513 li a0,0 113 | 164: 00000073 ecall 114 | 115 | 00000168 : 116 | 168: 00300293 li t0,3 117 | 16c: fc5196e3 bne gp,t0,138 118 | 170: 342022f3 csrr t0,mcause 119 | 174: 00200313 li t1,2 120 | 178: fc6290e3 bne t0,t1,138 121 | 17c: fd9ff06f j 154 122 | 180: c0001073 unimp 123 | -------------------------------------------------------------------------------- /tests/upstream/binaries/simple: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/simple -------------------------------------------------------------------------------- /tests/upstream/binaries/simple.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/simple.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: ff0f0f13 addi t5,t5,-16 # 0 <_start> 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffe30> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00000297 auipc t0,0x0 77 | f4: 01428293 addi t0,t0,20 # 104 78 | f8: 34129073 csrw mepc,t0 79 | fc: f1402573 csrr a0,mhartid 80 | 100: 30200073 mret 81 | 104: 0ff0000f fence 82 | 108: 00100193 li gp,1 83 | 10c: 05d00893 li a7,93 84 | 110: 00000513 li a0,0 85 | 114: 00000073 ecall 86 | 118: c0001073 unimp 87 | 11c: 0000 unimp 88 | 11e: 0000 unimp 89 | 120: 0000 unimp 90 | 122: 0000 unimp 91 | 124: 0000 unimp 92 | 126: 0000 unimp 93 | 128: 0000 unimp 94 | 12a: 0000 unimp 95 | 12c: 0000 unimp 96 | 12e: 0000 unimp 97 | 130: 0000 unimp 98 | 132: 0000 unimp 99 | 134: 0000 unimp 100 | 136: 0000 unimp 101 | 138: 0000 unimp 102 | 13a: 0000 unimp 103 | 13c: 0000 unimp 104 | 13e: 0000 unimp 105 | 140: 0000 unimp 106 | 142: 0000 unimp 107 | -------------------------------------------------------------------------------- /tests/upstream/binaries/sll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/sll -------------------------------------------------------------------------------- /tests/upstream/binaries/slli: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/slli -------------------------------------------------------------------------------- /tests/upstream/binaries/slt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/slt 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-------------------------------------------------------------------------------- /tests/upstream/binaries/sw-misaligned: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/sw-misaligned -------------------------------------------------------------------------------- /tests/upstream/binaries/sw-misaligned.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/sw-misaligned.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 204f0f13 addi t5,t5,516 # 214 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffd60> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x1560> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: 29000093 li ra,656 88 | 118: 12345137 lui sp,0x12345 89 | 11c: 67810113 addi sp,sp,1656 # 12345678 <_end+0x123453d8> 90 | 120: 00000797 auipc a5,0x0 91 | 124: 01478793 addi a5,a5,20 # 134 92 | 128: 0020a023 sw sp,0(ra) 93 | 12c: 0000a703 lw a4,0(ra) 94 | 130: 0080006f j 138 95 | 134: 00010713 mv a4,sp 96 | 138: 123453b7 lui t2,0x12345 97 | 13c: 67838393 addi t2,t2,1656 # 12345678 <_end+0x123453d8> 98 | 140: 0a771263 bne a4,t2,1e4 99 | 100 | 00000144 : 101 | 144: 00300193 li gp,3 102 | 148: 29000093 li ra,656 103 | 14c: 9abce137 lui sp,0x9abce 104 | 150: ef010113 addi sp,sp,-272 # 9abcdef0 <_end+0x9abcdc50> 105 | 154: 00000797 auipc a5,0x0 106 | 158: 01478793 addi a5,a5,20 # 168 107 | 15c: 0020a0a3 sw sp,1(ra) 108 | 160: 0010a703 lw a4,1(ra) 109 | 164: 0080006f j 16c 110 | 168: 00010713 mv a4,sp 111 | 16c: 9abce3b7 lui t2,0x9abce 112 | 170: ef038393 addi t2,t2,-272 # 9abcdef0 <_end+0x9abcdc50> 113 | 174: 06771863 bne a4,t2,1e4 114 | 115 | 00000178 : 116 | 178: 00400193 li gp,4 117 | 17c: 29000093 li ra,656 118 | 180: deadc137 lui sp,0xdeadc 119 | 184: eef10113 addi sp,sp,-273 # deadbeef <_end+0xdeadbc4f> 120 | 188: 00000797 auipc a5,0x0 121 | 18c: 01478793 addi a5,a5,20 # 19c 122 | 190: 0020a123 sw sp,2(ra) 123 | 194: 0020a703 lw a4,2(ra) 124 | 198: 0080006f j 1a0 125 | 19c: 00010713 mv a4,sp 126 | 1a0: deadc3b7 lui t2,0xdeadc 127 | 1a4: eef38393 addi t2,t2,-273 # deadbeef <_end+0xdeadbc4f> 128 | 1a8: 02771e63 bne a4,t2,1e4 129 | 130 | 000001ac : 131 | 1ac: 00500193 li gp,5 132 | 1b0: 29000093 li ra,656 133 | 1b4: feed0137 lui sp,0xfeed0 134 | 1b8: 01110113 addi sp,sp,17 # feed0011 <_end+0xfeecfd71> 135 | 1bc: 00000797 auipc a5,0x0 136 | 1c0: 01478793 addi a5,a5,20 # 1d0 137 | 1c4: 0020a1a3 sw sp,3(ra) 138 | 1c8: 0030a703 lw a4,3(ra) 139 | 1cc: 0080006f j 1d4 140 | 1d0: 00010713 mv a4,sp 141 | 1d4: feed03b7 lui t2,0xfeed0 142 | 1d8: 01138393 addi t2,t2,17 # feed0011 <_end+0xfeecfd71> 143 | 1dc: 00771463 bne a4,t2,1e4 144 | 1e0: 02301063 bne zero,gp,200 145 | 146 | 000001e4 : 147 | 1e4: 0ff0000f fence 148 | 1e8: 00018063 beqz gp,1e8 149 | 1ec: 00119193 slli gp,gp,0x1 150 | 1f0: 0011e193 ori gp,gp,1 151 | 1f4: 05d00893 li a7,93 152 | 1f8: 00018513 mv a0,gp 153 | 1fc: 00000073 ecall 154 | 155 | 00000200 : 156 | 200: 0ff0000f fence 157 | 204: 00100193 li gp,1 158 | 208: 05d00893 li a7,93 159 | 20c: 00000513 li a0,0 160 | 210: 00000073 ecall 161 | 162 | 00000214 : 163 | 214: 00600293 li t0,6 164 | 218: 34202373 csrr t1,mcause 165 | 21c: fc6294e3 bne t0,t1,1e4 166 | 220: 34179073 csrw mepc,a5 167 | 224: 30200073 mret 168 | 228: c0001073 unimp 169 | 22c: 0000 unimp 170 | 22e: 0000 unimp 171 | 230: 0000 unimp 172 | 232: 0000 unimp 173 | 174 | Disassembly of section .data: 175 | 176 | 00000290 : 177 | 290: 0000 unimp 178 | 292: 0000 unimp 179 | 294: 0000 unimp 180 | 296: 0000 unimp 181 | 298: 0000 unimp 182 | 29a: 0000 unimp 183 | 29c: 0000 unimp 184 | 29e: 0000 unimp 185 | -------------------------------------------------------------------------------- /tests/upstream/binaries/xor: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/xor -------------------------------------------------------------------------------- /tests/upstream/binaries/xori: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/xori -------------------------------------------------------------------------------- /tests/upstream/binaries/zicntr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cr1901/sentinel/9334c2cbb76091431cf8ca58b85694d4199ef9a4/tests/upstream/binaries/zicntr -------------------------------------------------------------------------------- /tests/upstream/binaries/zicntr.dump: -------------------------------------------------------------------------------- 1 | 2 | tests/upstream/binaries/zicntr.elf: file format elf32-littleriscv 3 | 4 | 5 | Disassembly of section .text.init: 6 | 7 | 00000000 <_start>: 8 | 0: 0400006f j 40 9 | 10 | 00000004 : 11 | 4: 34202f73 csrr t5,mcause 12 | 8: 00b00f93 li t6,11 13 | c: 03ff0263 beq t5,t6,30 14 | 10: 00000f17 auipc t5,0x0 15 | 14: 234f0f13 addi t5,t5,564 # 244 16 | 18: 000f0463 beqz t5,20 17 | 1c: 000f0067 jr t5 18 | 20: 34202f73 csrr t5,mcause 19 | 24: 000f5463 bgez t5,2c 20 | 28: 0040006f j 2c 21 | 22 | 0000002c : 23 | 2c: 5391e193 ori gp,gp,1337 24 | 25 | 00000030 : 26 | 30: 04000f37 lui t5,0x4000 27 | 34: 003f2023 sw gp,0(t5) # 4000000 <_end+0x3fffcf0> 28 | 38: 000f2223 sw zero,4(t5) 29 | 3c: ff5ff06f j 30 30 | 31 | 00000040 : 32 | 40: 00000093 li ra,0 33 | 44: 00000113 li sp,0 34 | 48: 00000193 li gp,0 35 | 4c: 00000213 li tp,0 36 | 50: 00000293 li t0,0 37 | 54: 00000313 li t1,0 38 | 58: 00000393 li t2,0 39 | 5c: 00000413 li s0,0 40 | 60: 00000493 li s1,0 41 | 64: 00000513 li a0,0 42 | 68: 00000593 li a1,0 43 | 6c: 00000613 li a2,0 44 | 70: 00000693 li a3,0 45 | 74: 00000713 li a4,0 46 | 78: 00000793 li a5,0 47 | 7c: 00000813 li a6,0 48 | 80: 00000893 li a7,0 49 | 84: 00000913 li s2,0 50 | 88: 00000993 li s3,0 51 | 8c: 00000a13 li s4,0 52 | 90: 00000a93 li s5,0 53 | 94: 00000b13 li s6,0 54 | 98: 00000b93 li s7,0 55 | 9c: 00000c13 li s8,0 56 | a0: 00000c93 li s9,0 57 | a4: 00000d13 li s10,0 58 | a8: 00000d93 li s11,0 59 | ac: 00000e13 li t3,0 60 | b0: 00000e93 li t4,0 61 | b4: 00000f13 li t5,0 62 | b8: 00000f93 li t6,0 63 | bc: 00000193 li gp,0 64 | c0: 00000297 auipc t0,0x0 65 | c4: f4428293 addi t0,t0,-188 # 4 66 | c8: 30529073 csrw mtvec,t0 67 | cc: 00100513 li a0,1 68 | d0: 01f51513 slli a0,a0,0x1f 69 | d4: 00054c63 bltz a0,ec 70 | d8: 0ff0000f fence 71 | dc: 00100193 li gp,1 72 | e0: 05d00893 li a7,93 73 | e4: 00000513 li a0,0 74 | e8: 00000073 ecall 75 | ec: 30005073 csrwi mstatus,0 76 | f0: 00002537 lui a0,0x2 77 | f4: 80050513 addi a0,a0,-2048 # 1800 <_end+0x14f0> 78 | f8: 30052073 csrs mstatus,a0 79 | fc: 00000297 auipc t0,0x0 80 | 100: 01428293 addi t0,t0,20 # 110 81 | 104: 34129073 csrw mepc,t0 82 | 108: f1402573 csrr a0,mhartid 83 | 10c: 30200073 mret 84 | 85 | 00000110 : 86 | 110: 00200193 li gp,2 87 | 114: c0003073 csrc cycle,zero 88 | 118: 00000393 li t2,0 89 | 11c: 0e701c63 bne zero,t2,214 90 | 91 | 00000120 : 92 | 120: 00300193 li gp,3 93 | 124: c0002073 rdcycle zero 94 | 128: 00000393 li t2,0 95 | 12c: 0e701463 bne zero,t2,214 96 | 97 | 00000130 : 98 | 130: 00400193 li gp,4 99 | 134: c0007073 csrci cycle,0 100 | 138: 00000393 li t2,0 101 | 13c: 0c701c63 bne zero,t2,214 102 | 103 | 00000140 : 104 | 140: 00500193 li gp,5 105 | 144: c0006073 csrsi cycle,0 106 | 148: 00000393 li t2,0 107 | 14c: 0c701463 bne zero,t2,214 108 | 109 | 00000150 : 110 | 150: 00600193 li gp,6 111 | 154: c0203073 csrc instret,zero 112 | 158: 00000393 li t2,0 113 | 15c: 0a701c63 bne zero,t2,214 114 | 115 | 00000160 : 116 | 160: 00700193 li gp,7 117 | 164: c0202073 rdinstret zero 118 | 168: 00000393 li t2,0 119 | 16c: 0a701463 bne zero,t2,214 120 | 121 | 00000170 : 122 | 170: 00800193 li gp,8 123 | 174: c0207073 csrci instret,0 124 | 178: 00000393 li t2,0 125 | 17c: 08701c63 bne zero,t2,214 126 | 127 | 00000180 : 128 | 180: 00900193 li gp,9 129 | 184: c0206073 csrsi instret,0 130 | 188: 00000393 li t2,0 131 | 18c: 08701463 bne zero,t2,214 132 | 133 | 00000190 : 134 | 190: 00c00193 li gp,12 135 | 194: c8003073 csrc cycleh,zero 136 | 198: 00000393 li t2,0 137 | 19c: 06701c63 bne zero,t2,214 138 | 139 | 000001a0 : 140 | 1a0: 00d00193 li gp,13 141 | 1a4: c8002073 rdcycleh zero 142 | 1a8: 00000393 li t2,0 143 | 1ac: 06701463 bne zero,t2,214 144 | 145 | 000001b0 : 146 | 1b0: 00e00193 li gp,14 147 | 1b4: c8007073 csrci cycleh,0 148 | 1b8: 00000393 li t2,0 149 | 1bc: 04701c63 bne zero,t2,214 150 | 151 | 000001c0 : 152 | 1c0: 00f00193 li gp,15 153 | 1c4: c8006073 csrsi cycleh,0 154 | 1c8: 00000393 li t2,0 155 | 1cc: 04701463 bne zero,t2,214 156 | 157 | 000001d0 : 158 | 1d0: 01000193 li gp,16 159 | 1d4: c8203073 csrc instreth,zero 160 | 1d8: 00000393 li t2,0 161 | 1dc: 02701c63 bne zero,t2,214 162 | 163 | 000001e0 : 164 | 1e0: 01100193 li gp,17 165 | 1e4: c8202073 rdinstreth zero 166 | 1e8: 00000393 li t2,0 167 | 1ec: 02701463 bne zero,t2,214 168 | 169 | 000001f0 : 170 | 1f0: 01200193 li gp,18 171 | 1f4: c8207073 csrci instreth,0 172 | 1f8: 00000393 li t2,0 173 | 1fc: 00701c63 bne zero,t2,214 174 | 175 | 00000200 : 176 | 200: 01300193 li gp,19 177 | 204: c8206073 csrsi instreth,0 178 | 208: 00000393 li t2,0 179 | 20c: 00701463 bne zero,t2,214 180 | 210: 02301063 bne zero,gp,230 181 | 182 | 00000214 : 183 | 214: 0ff0000f fence 184 | 218: 00018063 beqz gp,218 185 | 21c: 00119193 slli gp,gp,0x1 186 | 220: 0011e193 ori gp,gp,1 187 | 224: 05d00893 li a7,93 188 | 228: 00018513 mv a0,gp 189 | 22c: 00000073 ecall 190 | 191 | 00000230 : 192 | 230: 0ff0000f fence 193 | 234: 00100193 li gp,1 194 | 238: 05d00893 li a7,93 195 | 23c: 00000513 li a0,0 196 | 240: 00000073 ecall 197 | 198 | 00000244 : 199 | 244: fd1ff06f j 214 200 | 248: c0001073 unimp 201 | 24c: 0000 unimp 202 | 24e: 0000 unimp 203 | 250: 0000 unimp 204 | 252: 0000 unimp 205 | 254: 0000 unimp 206 | 256: 0000 unimp 207 | 258: 0000 unimp 208 | 25a: 0000 unimp 209 | 25c: 0000 unimp 210 | 25e: 0000 unimp 211 | 260: 0000 unimp 212 | 262: 0000 unimp 213 | 264: 0000 unimp 214 | 266: 0000 unimp 215 | 268: 0000 unimp 216 | 26a: 0000 unimp 217 | 26c: 0000 unimp 218 | 26e: 0000 unimp 219 | 270: 0000 unimp 220 | 272: 0000 unimp 221 | 274: 0000 unimp 222 | 276: 0000 unimp 223 | 278: 0000 unimp 224 | 27a: 0000 unimp 225 | 27c: 0000 unimp 226 | 27e: 0000 unimp 227 | 280: 0000 unimp 228 | 282: 0000 unimp 229 | -------------------------------------------------------------------------------- /tests/upstream/link.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY(_start) 3 | 4 | SECTIONS 5 | { 6 | . = 0x00000000; 7 | .text.init : { *(.text.init) } 8 | . = ALIGN(0x10); 9 | .tohost : { *(.tohost) } 10 | . = ALIGN(0x10); 11 | .text : { *(.text) } 12 | . = ALIGN(0x10); 13 | .data : { *(.data) } 14 | .bss : { *(.bss) } 15 | _end = .; 16 | } 17 | 18 | -------------------------------------------------------------------------------- /tests/upstream/test_upstream.py: -------------------------------------------------------------------------------- 1 | import pytest 2 | 3 | from enum import Enum, auto 4 | 5 | from sentinel.top import Top 6 | from tests.conftest import Memory 7 | 8 | 9 | # Generate prettier names by not bothering to parameterize on these. 10 | @pytest.fixture(scope="function") 11 | def mod(): 12 | return Top() 13 | 14 | 15 | @pytest.fixture(scope="module") 16 | def clks(): 17 | return 1.0 / 12e6 18 | 19 | 20 | # Special memory fixture to load the upstream tests. 21 | @pytest.fixture 22 | def memory(request): 23 | rootdir = request.config.rootdir 24 | test_name = rootdir / "tests" / "upstream" / "binaries" / request.param 25 | 26 | with open(test_name, "rb") as fp: 27 | bytebin = fp.read() 28 | 29 | mem = Memory(0, 4096) 30 | 31 | for adr in range(0, len(bytebin) // 4): 32 | mem[adr] = int.from_bytes(bytebin[4 * adr:4 * adr + 4], 33 | byteorder="little") 34 | 35 | return mem 36 | 37 | 38 | async def wfhw_inner(mod, ctx): 39 | class HOST_STATE(Enum): 40 | WAITING_FIRST = auto() 41 | FIRST_ACCESS_ACK = auto() 42 | WAITING_SECOND = auto() 43 | SECOND_ACCESS_ACK = auto() 44 | DONE = auto() 45 | TIMEOUT = auto() 46 | 47 | m = mod 48 | i = 0 49 | state = HOST_STATE.WAITING_FIRST 50 | val = 0xdeadbeef 51 | 52 | while True: 53 | stims = [m.bus.cyc & m.bus.stb, m.bus.adr, m.bus.dat_w, m.bus.we, 54 | m.bus.sel] 55 | *_, wb_cyc, addr, dat_w, we, sel = await ctx.tick().sample(*stims) 56 | 57 | i += 1 58 | if i > 65535: 59 | state = HOST_STATE.TIMEOUT 60 | 61 | match state: 62 | case HOST_STATE.WAITING_FIRST: 63 | if (addr == 0x4000000 >> 2) and (sel == 0b1111) and \ 64 | wb_cyc and we: 65 | ctx.set(m.bus.ack, 1) 66 | state = HOST_STATE.FIRST_ACCESS_ACK 67 | case HOST_STATE.FIRST_ACCESS_ACK: 68 | val = dat_w 69 | ctx.set(m.bus.ack, 0) 70 | state = HOST_STATE.WAITING_SECOND 71 | case HOST_STATE.WAITING_SECOND: 72 | if addr == ((0x4000000 + 4) >> 2) and (sel == 0b1111) and \ 73 | wb_cyc and we: 74 | ctx.set(m.bus.ack, 1) 75 | state = HOST_STATE.SECOND_ACCESS_ACK 76 | case HOST_STATE.SECOND_ACCESS_ACK: 77 | val |= (dat_w << 32) 78 | ctx.set(m.bus.ack, 0) 79 | state = HOST_STATE.DONE 80 | case HOST_STATE.DONE: 81 | break 82 | case HOST_STATE.TIMEOUT: 83 | raise AssertionError("CPU (but not microcode) probably " 84 | "stuck in infinite loop") 85 | 86 | return val 87 | 88 | 89 | @pytest.fixture 90 | def wait_for_host_write(mod, request): 91 | # TODO: Convert into SoC module (use wishbone.Decoder and friends)? 92 | async def wait_for_host_write(ctx): 93 | val = await wfhw_inner(mod, ctx) 94 | assert (val >> 1, val & 1) == (0, 1) 95 | 96 | return wait_for_host_write 97 | 98 | 99 | RV32UI_TESTS = [ 100 | "add", "addi", "and", "andi", "auipc", "beq", "bge", "bgeu", "blt", 101 | "bltu", "bne", 102 | pytest.param("fence_i", marks=pytest.mark.xfail(reason="Zifencei not implemented")), # noqa: E501 103 | "jal", "jalr", "lb", "lbu", "lh", "lhu", 104 | "lui", "lw", 105 | pytest.param("ma_data", marks=pytest.mark.xfail(reason="misaligned access are traps")), # noqa: E501 106 | "or", "ori", "sb", "sh", "simple", "sll", "slli", 107 | "slt", "slti", "sltiu", "sltu", "sra", "srai", "srl", "srli", "sub", "sw", 108 | "xor", "xori" 109 | ] 110 | 111 | 112 | @pytest.mark.parametrize("memory", RV32UI_TESTS, indirect=True) 113 | def test_rv32ui(sim, ucode_panic, wait_for_host_write, memory_process): 114 | sim.run(testbenches=[wait_for_host_write], processes=[ucode_panic, 115 | memory_process]) 116 | 117 | 118 | RV32MI_TESTS = [ 119 | "csr", "illegal", "lh-misaligned", "lw-misaligned", "ma_addr", 120 | "ma_fetch", 121 | pytest.param("mcsr", marks=pytest.mark.xfail(reason="writable misa not implemented")), # noqa: E501 122 | "sbreak", "scall", "sh-misaligned", "shamt", "sw-misaligned", 123 | pytest.param("zicntr", marks=pytest.mark.xfail(reason="Zicntr not implemented")) # noqa: E501 124 | ] 125 | 126 | 127 | @pytest.mark.parametrize("memory", RV32MI_TESTS, indirect=True) 128 | def test_rv32mi(sim, ucode_panic, wait_for_host_write, memory_process): 129 | sim.run(testbenches=[wait_for_host_write], processes=[ucode_panic, 130 | memory_process]) 131 | --------------------------------------------------------------------------------