├── reverse.v ├── clk.sdc ├── delay.v ├── clkdiv.v ├── ROM_tb.v ├── mic_fifo.v ├── vga_fifo.v ├── mem_dp.v ├── mic_translator_tb.v ├── ROM.v ├── FFT_controller_tb.v ├── vga_generator_tb.v ├── magnitude_estimate.v ├── twiddle_script.py ├── FFT_processor_tb.v ├── butterfly_pipeline.v ├── DAV.v ├── FFT_mem.v ├── FFT_processor.v ├── README.md ├── mic_translator.v ├── FFT_controller.v ├── vga_generator.v ├── zeros.txt ├── rom_i_init.txt └── rom_r_init.txt /reverse.v: -------------------------------------------------------------------------------- 1 | module reverse 2 | #(parameter WIDTH = 6) 3 | ( 4 | input [(WIDTH-1):0] data_in, 5 | output [(WIDTH-1):0] data_out 6 | ); 7 | 8 | genvar i; 9 | 10 | generate 11 | for (i = 0; i < WIDTH; i = i + 1) 12 | begin : reversal 13 | assign data_out[i] = data_in[WIDTH-1-i]; 14 | end 15 | endgenerate 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /clk.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name clk -period 20.000 [get_ports {clk}] 2 | create_generated_clock -name clk_2M5 -source [get_ports {clk}] -divide_by 20 [get_pins {generate_clk_2M5|clk_out|q}] 3 | create_generated_clock -name clk_25M -source [get_ports {clk}] -divide_by 2 [get_pins {generate_clk_25M|clk_out|q}] 4 | create_generated_clock -name newline -source [get_pins {generate_clk_25M|clk_out|q}] -divide_by 1600 [get_pins {vga|horizontal|newline_out|q}] -------------------------------------------------------------------------------- /delay.v: -------------------------------------------------------------------------------- 1 | module delay 2 | #(parameter WIDTH = 1, parameter CYCLES = 1) 3 | ( 4 | input clk, 5 | input [(WIDTH-1):0] data_in, 6 | output [(WIDTH-1):0] data_out 7 | ); 8 | 9 | reg [(WIDTH-1):0] regs [(CYCLES-1):0]; 10 | assign data_out = regs[CYCLES-1]; 11 | 12 | integer i; 13 | 14 | always @ (posedge clk) 15 | begin 16 | regs[0] <= data_in; 17 | for (i = 1; i < CYCLES; i = i+1) 18 | regs[i] <= regs[i-1]; 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /clkdiv.v: -------------------------------------------------------------------------------- 1 | module clkdiv 2 | #(parameter THRESHOLD = 1) 3 | ( 4 | input clk_in, 5 | output reg clk_out 6 | ); 7 | 8 | reg [31:0] clk_counter; 9 | 10 | 11 | initial begin 12 | clk_counter = 0; 13 | clk_out = 1; 14 | end 15 | 16 | always @ (posedge clk_in) begin 17 | if (clk_counter >= THRESHOLD) begin 18 | clk_counter <= 0; 19 | clk_out <= ~clk_out; 20 | end 21 | else begin 22 | clk_counter <= clk_counter + 1; 23 | clk_out <= clk_out; 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /ROM_tb.v: -------------------------------------------------------------------------------- 1 | module ROM_tb; 2 | 3 | parameter DATA_WIDTH=18; 4 | parameter ADDR_WIDTH=3; 5 | 6 | reg [(ADDR_WIDTH-1):0] addr; 7 | reg clk; 8 | wire [(DATA_WIDTH-1):0] q; 9 | 10 | ROM 11 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 12 | UUT 13 | ( 14 | .addr(addr), 15 | .clk(clk), 16 | .q(q) 17 | ); 18 | 19 | 20 | always 21 | begin 22 | #5 clk = ~clk; 23 | end 24 | 25 | initial 26 | begin 27 | clk = 0; 28 | addr = 0; 29 | 30 | #20 addr = 1; 31 | #20 addr = 2; 32 | #20 addr = 3; 33 | #20 addr = 4; 34 | end 35 | endmodule -------------------------------------------------------------------------------- /mic_fifo.v: -------------------------------------------------------------------------------- 1 | module mic_fifo 2 | #(parameter ADDR_WIDTH = 6, parameter DATA_WIDTH = 18) 3 | ( 4 | input clk, fifo_we, 5 | input [(ADDR_WIDTH-1):0] fifo_wr_addr, fifo_rd_addr, 6 | input [(DATA_WIDTH-1):0] fifo_wr_data, 7 | output reg [(DATA_WIDTH-1):0] fifo_rd_data 8 | ); 9 | 10 | reg [DATA_WIDTH-1:0] fifo [2**ADDR_WIDTH-1:0]; 11 | 12 | // FIFO write Port 13 | always @ (posedge clk) 14 | begin 15 | if (fifo_we) 16 | fifo[fifo_wr_addr] <= fifo_wr_data; 17 | end 18 | 19 | // FIFO read Port 20 | always @ (posedge clk) 21 | begin 22 | fifo_rd_data <= fifo[fifo_rd_addr]; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /vga_fifo.v: -------------------------------------------------------------------------------- 1 | module vga_fifo 2 | #(parameter ADDR_WIDTH = 6, parameter DATA_WIDTH = 18) 3 | ( 4 | input FFT_clk, vga_clk, fifo_we, 5 | input [(ADDR_WIDTH-1):0] fifo_wr_addr, fifo_rd_addr, 6 | input [(DATA_WIDTH-1):0] fifo_wr_data, 7 | output reg [(DATA_WIDTH-1):0] fifo_rd_data 8 | ); 9 | 10 | reg [DATA_WIDTH-1:0] fifo [2**ADDR_WIDTH-1:0]; 11 | 12 | 13 | initial 14 | begin 15 | $readmemb("zeros.txt", fifo); 16 | end 17 | 18 | 19 | // FIFO write Port 20 | always @ (posedge FFT_clk) 21 | begin 22 | if (fifo_we) 23 | fifo[fifo_wr_addr] <= fifo_wr_data; 24 | end 25 | 26 | // FIFO read Port 27 | always @ (posedge vga_clk) 28 | begin 29 | fifo_rd_data <= fifo[fifo_rd_addr]; 30 | end 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /mem_dp.v: -------------------------------------------------------------------------------- 1 | module mem_dp 2 | #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) 3 | ( 4 | input [(DATA_WIDTH-1):0] data_a, data_b, 5 | input [(ADDR_WIDTH-1):0] addr_a, addr_b, 6 | input we_a, we_b, clk, 7 | output reg [(DATA_WIDTH-1):0] q_a, q_b 8 | ); 9 | 10 | // Declare the RAM variable 11 | reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; 12 | 13 | // Port A 14 | always @ (posedge clk) 15 | begin 16 | if (we_a) 17 | begin 18 | ram[addr_a] <= data_a; 19 | q_a <= data_a; 20 | end 21 | else 22 | begin 23 | q_a <= ram[addr_a]; 24 | end 25 | end 26 | 27 | // Port B 28 | always @ (posedge clk) 29 | begin 30 | if (we_b) 31 | begin 32 | ram[addr_b] <= data_b; 33 | q_b <= data_b; 34 | end 35 | else 36 | begin 37 | q_b <= ram[addr_b]; 38 | end 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /mic_translator_tb.v: -------------------------------------------------------------------------------- 1 | module mic_translator_tb; 2 | 3 | parameter ADDR_WIDTH = 3; 4 | parameter DATA_WIDTH = 18; 5 | 6 | reg clk = 1; 7 | reg rst = 1; 8 | reg DOUT = 0; 9 | wire start; 10 | wire BCLK, LRCLK, mic_we; 11 | wire [(ADDR_WIDTH-1):0] mic_addr; 12 | wire [(DATA_WIDTH-1):0] mic_data; 13 | 14 | mic_translator 15 | #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) 16 | DUT 17 | ( 18 | .clk(clk), 19 | .rst(rst), 20 | .DOUT(DOUT), 21 | .start(start), 22 | .BCLK(BCLK), 23 | .LRCLK(LRCLK), 24 | .mic_we(mic_we), 25 | .mic_addr(mic_addr), 26 | .mic_data(mic_data) 27 | ); 28 | 29 | always 30 | begin 31 | #10 32 | clk = ~clk; 33 | DOUT = $random; 34 | #10 35 | clk = ~clk; 36 | end 37 | 38 | initial 39 | begin 40 | #25; 41 | rst = 0; 42 | #30; 43 | rst = 1; 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /ROM.v: -------------------------------------------------------------------------------- 1 | module ROM 2 | #(parameter DATA_WIDTH=18, parameter ADDR_WIDTH=3, parameter REAL = 1) 3 | ( 4 | input [(ADDR_WIDTH-1):0] addr, 5 | input clk, 6 | output reg [(DATA_WIDTH-1):0] q 7 | ); 8 | 9 | // Declare the ROM variable 10 | reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0]; 11 | 12 | // Initialize the ROM with $readmemb. Put the memory contents 13 | // in the file single_port_rom_init.txt. Without this file, 14 | // this design will not compile. 15 | 16 | // See Verilog LRM 1364-2001 Section 17.2.8 for details on the 17 | // format of this file, or see the "Using $readmemb and $readmemh" 18 | // template later in this section. 19 | 20 | generate 21 | if (REAL) 22 | begin : INIT_REAL 23 | initial 24 | begin 25 | $readmemb("rom_r_init.txt", rom); 26 | end 27 | end 28 | else 29 | begin : INIT_IMAG 30 | initial 31 | begin 32 | $readmemb("rom_i_init.txt", rom); 33 | end 34 | end 35 | endgenerate 36 | 37 | always @ (posedge clk) 38 | begin 39 | q <= rom[addr]; 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /FFT_controller_tb.v: -------------------------------------------------------------------------------- 1 | module FFT_controller_tb; 2 | 3 | parameter ADDR_WIDTH = 4; 4 | parameter DATA_WIDTH = 18; 5 | 6 | reg clk, rst, start; 7 | wire we_sel, q_sel; 8 | wire we_a, we_b; 9 | wire [(ADDR_WIDTH-1):0] addr0_a, addr0_b, addr1_a, addr1_b; 10 | wire [(DATA_WIDTH-1):0] twiddle_r, twiddle_i; 11 | wire done; 12 | 13 | FFT_controller 14 | #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) 15 | DUT 16 | ( 17 | .clk(clk), 18 | .rst(rst), 19 | .start(start), 20 | .we_sel(we_sel), 21 | .q_sel(q_sel), 22 | .we_a(we_a), 23 | .we_b(we_b), 24 | .addr0_a(addr0_a), 25 | .addr0_b(addr0_b), 26 | .addr1_a(addr1_a), 27 | .addr1_b(addr1_b), 28 | .twiddle_r(twiddle_r), 29 | .twiddle_i(twiddle_i), 30 | .done(done) 31 | ); 32 | 33 | always 34 | begin 35 | #5 clk = ~clk; 36 | end 37 | 38 | initial 39 | begin 40 | clk = 0; 41 | rst = 0; 42 | start = 0; 43 | 44 | #20; 45 | rst = 1; 46 | 47 | #20; 48 | start = 1; 49 | #10; 50 | start = 0; 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /vga_generator_tb.v: -------------------------------------------------------------------------------- 1 | module vga_generator_tb; 2 | 3 | parameter DATA_WIDTH = 18; 4 | parameter ADDR_WIDTH = 9; 5 | 6 | reg done, vga_clk, FFT_clk, rst; 7 | reg [(DATA_WIDTH-1):0] FFT_data_r, FFT_data_i; 8 | wire [(ADDR_WIDTH-2):0] FFT_addr; 9 | wire [3:0] VGA_R; 10 | wire [3:0] VGA_G, VGA_B; 11 | wire VGA_HS, VGA_VS; 12 | 13 | vga_generator 14 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 15 | DUT 16 | ( 17 | .done(done), 18 | .vga_clk(vga_clk), 19 | .FFT_clk(FFT_clk), 20 | .rst(rst), 21 | .FFT_data_r(FFT_data_r), 22 | .FFT_data_i(FFT_data_i), 23 | .FFT_addr(FFT_addr), 24 | .VGA_R(VGA_R), 25 | .VGA_G(VGA_G), 26 | .VGA_B(VGA_B), 27 | .VGA_VS(VGA_VS) 28 | ); 29 | 30 | 31 | always 32 | begin 33 | #5; 34 | vga_clk = ~vga_clk; 35 | FFT_clk = ~FFT_clk; 36 | 37 | #5; 38 | vga_clk = ~vga_clk; 39 | FFT_clk = ~FFT_clk; 40 | FFT_data_r = $random; 41 | FFT_data_i = $random; 42 | end 43 | 44 | initial 45 | begin 46 | vga_clk = 0; 47 | FFT_clk = 0; 48 | rst = 0; 49 | done = 0; 50 | 51 | #20; 52 | rst = 1; 53 | 54 | 55 | #60; 56 | done = 1; 57 | 58 | #10; 59 | done = 0; 60 | 61 | 62 | 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /magnitude_estimate.v: -------------------------------------------------------------------------------- 1 | module magnitude_estimate 2 | #(parameter ADDR_WIDTH = 6, parameter DATA_WIDTH = 18, parameter MEM_DATA_WIDTH = 9) 3 | ( 4 | input clk, rst, we, 5 | input [(ADDR_WIDTH-1):0] addr, 6 | input unsigned [(DATA_WIDTH-1):0] abs_FFT_data_r, abs_FFT_data_i, 7 | output delay_we, 8 | output [(ADDR_WIDTH-1):0] delay_addr, 9 | output reg unsigned [8:0] data 10 | ); 11 | 12 | //https://www.embedded.com/digital-signal-processing-tricks-high-speed-vector-magnitude-approximation/ 13 | 14 | reg unsigned [(DATA_WIDTH-1):0] reg_term_r, reg_term_i; 15 | reg unsigned [DATA_WIDTH:0] reg_term_sum, mag; 16 | reg [3:0] reg_we; 17 | 18 | assign delay_we = reg_we[3]; 19 | 20 | 21 | delay 22 | #(.WIDTH(ADDR_WIDTH), .CYCLES(4)) 23 | del_addr 24 | ( 25 | .clk(clk), 26 | .data_in(addr), 27 | .data_out(delay_addr) 28 | ); 29 | 30 | 31 | always @ (posedge clk) 32 | begin 33 | 34 | if (~rst) 35 | reg_we <= 0; 36 | else 37 | begin 38 | reg_we <= we; 39 | reg_we[3:1] <= reg_we[2:0]; 40 | end 41 | 42 | 43 | if (abs_FFT_data_r < abs_FFT_data_i) 44 | begin 45 | reg_term_r <= abs_FFT_data_r >> 1; 46 | reg_term_i <= abs_FFT_data_i; 47 | end 48 | else 49 | begin 50 | reg_term_r <= abs_FFT_data_r; 51 | reg_term_i <= abs_FFT_data_i >> 1; 52 | end 53 | 54 | reg_term_sum <= reg_term_r + reg_term_i; 55 | mag <= reg_term_sum - (reg_term_sum >> 4); 56 | data <= 480 - mag[DATA_WIDTH-2:DATA_WIDTH-MEM_DATA_WIDTH-1]; 57 | 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /twiddle_script.py: -------------------------------------------------------------------------------- 1 | import math 2 | 3 | zeros_filename = "zeros.txt" 4 | real_filename = "rom_r_init.txt" 5 | imag_filename = "rom_i_init.txt" 6 | sim_folder = "simulation/modelsim/" 7 | real_filename_sim = sim_folder + real_filename 8 | imag_filename_sim = sim_folder + imag_filename 9 | num_samples = 512 10 | data_width = 22 11 | multiplier = 2**(data_width-1); 12 | 13 | def main(): 14 | f_zeros = open(zeros_filename, "w") 15 | f_real = open(real_filename, "w") 16 | f_imag = open(imag_filename, "w") 17 | f_real_sim = open(real_filename_sim, "w") 18 | f_imag_sim = open(imag_filename_sim, "w") 19 | for k in range(int(num_samples/2)): 20 | real = math.cos(2*math.pi*k/num_samples) * multiplier 21 | imag = -math.sin(2*math.pi*k/num_samples) * multiplier 22 | real = int(round(real)) 23 | imag = int(round(imag)) 24 | 25 | if real < 0: 26 | real = real + 2 ** data_width 27 | elif real == multiplier: 28 | real = multiplier - 1 29 | 30 | if imag < 0: 31 | imag = imag + 2 ** data_width 32 | 33 | f_zeros.write(format(0, "0{}b".format(data_width)) + "\n") 34 | f_real.write(format(real, "0{}b".format(data_width)) + "\n") 35 | f_real_sim.write(format(real, "0{}b".format(data_width)) + "\n") 36 | f_imag.write(format(imag, "0{}b".format(data_width)) + "\n") 37 | f_imag_sim.write(format(imag, "0{}b".format(data_width)) + "\n") 38 | 39 | 40 | if __name__ == "__main__": 41 | main() 42 | -------------------------------------------------------------------------------- /FFT_processor_tb.v: -------------------------------------------------------------------------------- 1 | module FFT_processor_tb; 2 | 3 | parameter ADDR_WIDTH = 5; 4 | parameter DATA_WIDTH = 18; 5 | //depending on your compiler, you might need to add a single quote (') before the open bracket ({) 6 | parameter integer samples[0:2**ADDR_WIDTH-1] = {424, 326, -426, 401, 10, 140, -61, 208, -163, -345, -455, -420, -389, 95, 374, -65, 90, 435, -421, -127, -356, 111, 256, 465, -462, 47, -349, 111, -99, 220, 245, -193}; 7 | integer i; 8 | 9 | reg clk, rst, start; 10 | reg mic_we; 11 | reg [(ADDR_WIDTH-1):0] mic_addr; 12 | reg [(DATA_WIDTH-1):0] mic_data; 13 | reg [(ADDR_WIDTH-1):0] vga_addr; 14 | wire [(DATA_WIDTH-1):0] vga_data_r, vga_data_i; 15 | wire done; 16 | 17 | FFT_processor 18 | #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) 19 | DUT 20 | ( 21 | .clk(clk), 22 | .rst(rst), 23 | .start(start), 24 | .mic_we(mic_we), 25 | .mic_addr(mic_addr), 26 | .mic_data(mic_data), 27 | .vga_addr(vga_addr), 28 | .vga_data_r(vga_data_r), 29 | .vga_data_i(vga_data_i), 30 | .done(done) 31 | ); 32 | 33 | always 34 | begin 35 | #5 clk = ~clk; 36 | end 37 | 38 | initial 39 | begin 40 | clk = 0; 41 | rst = 0; 42 | start = 0; 43 | mic_we = 0; 44 | mic_addr = 0; 45 | mic_data = 0; 46 | vga_addr = 0; 47 | 48 | #20; 49 | rst = 1; 50 | 51 | #20; 52 | mic_we = 1; 53 | 54 | for (i = 0; i < 2**ADDR_WIDTH; i = i+1) 55 | begin 56 | mic_addr = i; 57 | mic_data = samples[i]; 58 | #10; 59 | end 60 | 61 | mic_we = 0; 62 | 63 | #20; 64 | start = 1; 65 | #10; 66 | start = 0; 67 | 68 | while (~done) 69 | #10; 70 | 71 | for (i = 0; i < 2**ADDR_WIDTH; i = i+1) 72 | begin 73 | vga_addr = i; 74 | #10; 75 | end 76 | end 77 | 78 | endmodule 79 | -------------------------------------------------------------------------------- /butterfly_pipeline.v: -------------------------------------------------------------------------------- 1 | module butterfly_pipeline 2 | #(parameter DATA_WIDTH=8) 3 | ( 4 | input clk, 5 | input signed [(DATA_WIDTH-1):0] in_ar, in_ai, in_br, in_bi, twiddle_r, twiddle_i, 6 | output reg signed [(DATA_WIDTH-1):0] out_ar, out_ai, out_br, out_bi 7 | ); 8 | 9 | wire [(DATA_WIDTH-1):0] delay_in_ar, delay_in_ai; 10 | reg signed [(DATA_WIDTH-1):0] reg_product0_r, reg_product0_i, reg_product1_r, reg_product1_i; 11 | reg signed [(DATA_WIDTH-1):0] reg_product_r, reg_product_i; 12 | 13 | wire signed [((DATA_WIDTH*2)-1):0] product0_r, product0_i, product1_r, product1_i; 14 | assign product0_r = twiddle_r * in_br; 15 | assign product0_i = twiddle_r * in_bi; 16 | assign product1_r = twiddle_i * in_bi; 17 | assign product1_i = twiddle_i * in_br; 18 | 19 | delay 20 | #(.WIDTH(DATA_WIDTH), .CYCLES(2)) 21 | delay_ar 22 | ( 23 | .clk(clk), 24 | .data_in(in_ar), 25 | .data_out(delay_in_ar) 26 | ); 27 | 28 | delay 29 | #(.WIDTH(DATA_WIDTH), .CYCLES(2)) 30 | delay_ai 31 | ( 32 | .clk(clk), 33 | .data_in(in_ai), 34 | .data_out(delay_in_ai) 35 | ); 36 | 37 | always @ (posedge clk) 38 | begin 39 | //--cycle 1 40 | //complex multiply individual products 41 | reg_product0_r <= product0_r[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)]; 42 | reg_product0_i <= product0_i[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)]; 43 | reg_product1_r <= product1_r[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)]; 44 | reg_product1_i <= product1_i[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)]; 45 | 46 | //--cycle 2 47 | //complex multiply full result 48 | reg_product_r <= reg_product0_r - reg_product1_r; 49 | reg_product_i <= reg_product0_i + reg_product1_i; 50 | 51 | //--cycle 3 52 | //set outputs 53 | out_ar <= delay_in_ar + reg_product_r; 54 | out_ai <= delay_in_ai + reg_product_i; 55 | out_br <= delay_in_ar - reg_product_r; 56 | out_bi <= delay_in_ai - reg_product_i; 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /DAV.v: -------------------------------------------------------------------------------- 1 | module DAV 2 | #(parameter ADDR_WIDTH = 9, parameter DATA_WIDTH = 22, parameter MIC_BITS = 18) 3 | ( 4 | input clk, rst, DOUT, 5 | output BCLK, LRCLK, 6 | output [3:0] VGA_R, VGA_G, VGA_B, 7 | output VGA_HS, VGA_VS 8 | ); 9 | 10 | wire clk_50M = clk; 11 | wire clk_2M5, clk_25M; 12 | 13 | wire start, mic_we; 14 | wire [(ADDR_WIDTH-1):0] mic_addr; 15 | wire [(MIC_BITS-1):0] mic_data; 16 | wire [(ADDR_WIDTH-2):0] vga_addr; 17 | wire [(DATA_WIDTH-1):0] vga_data_r, vga_data_i; 18 | wire done; 19 | 20 | 21 | clkdiv 22 | #(.THRESHOLD(0)) 23 | generate_clk_25M 24 | ( 25 | .clk_in(clk_50M), 26 | .clk_out(clk_25M) 27 | ); 28 | 29 | clkdiv 30 | #(.THRESHOLD(9)) 31 | generate_clk_2M5 32 | ( 33 | .clk_in(clk_50M), 34 | .clk_out(clk_2M5) 35 | ); 36 | 37 | mic_translator 38 | #(.ADDR_WIDTH(ADDR_WIDTH), .MIC_BITS(MIC_BITS)) 39 | mic 40 | ( 41 | .clk(clk_2M5), 42 | .rst(rst), 43 | .BCLK(BCLK), 44 | .DOUT(DOUT), 45 | .LRCLK(LRCLK), 46 | .mic_we(mic_we), 47 | .mic_addr(mic_addr), 48 | .mic_data(mic_data), 49 | .start(start) 50 | ); 51 | 52 | 53 | FFT_processor 54 | #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH), .MIC_BITS(MIC_BITS)) 55 | FFT 56 | ( 57 | .clk(clk_2M5), 58 | .rst(rst), 59 | .start(start), 60 | .mic_we(mic_we), 61 | .mic_addr(mic_addr), 62 | .mic_data(mic_data), 63 | .vga_addr(vga_addr), 64 | .vga_data_r(vga_data_r), 65 | .vga_data_i(vga_data_i), 66 | .done(done) 67 | ); 68 | 69 | vga_generator 70 | #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH), .MEM_DATA_WIDTH(9)) 71 | vga 72 | ( 73 | .done(done), 74 | .vga_clk(clk_25M), 75 | .FFT_clk(clk_2M5), 76 | .rst(rst), 77 | .FFT_addr(vga_addr), 78 | .FFT_data_r(vga_data_r), 79 | .FFT_data_i(vga_data_i), 80 | .VGA_R(VGA_R), 81 | .VGA_G(VGA_G), 82 | .VGA_B(VGA_B), 83 | .VGA_HS(VGA_HS), 84 | .VGA_VS(VGA_VS) 85 | ); 86 | 87 | endmodule 88 | -------------------------------------------------------------------------------- /FFT_mem.v: -------------------------------------------------------------------------------- 1 | module FFT_mem 2 | #(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) 3 | ( 4 | input [(DATA_WIDTH-1):0] data_ar, data_ai, data_br, data_bi, 5 | input [(ADDR_WIDTH-1):0] addr0_a, addr0_b, addr1_a, addr1_b, 6 | input we_a, we_b, we_sel, q_sel, clk, 7 | output reg [(DATA_WIDTH-1):0] q_ar, q_ai, q_br, q_bi, 8 | output [(DATA_WIDTH-1):0] vga_data_r, vga_data_i 9 | 10 | ); 11 | 12 | wire [DATA_WIDTH-1:0] q0_ar, q0_ai, q0_br, q0_bi, q1_ar, q1_ai, q1_br, q1_bi; 13 | 14 | assign vga_data_r = q1_ar; 15 | assign vga_data_i = q1_ai; 16 | 17 | mem_dp 18 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 19 | mem_dp0_r 20 | ( 21 | .data_a(data_ar), 22 | .data_b(data_br), 23 | .addr_a(addr0_a), 24 | .addr_b(addr0_b), 25 | .we_a(we_a & (~we_sel)), 26 | .we_b(we_b & (~we_sel)), 27 | .clk(clk), 28 | .q_a(q0_ar), 29 | .q_b(q0_br) 30 | ); 31 | 32 | mem_dp 33 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 34 | mem_dp0_i 35 | ( 36 | .data_a(data_ai), 37 | .data_b(data_bi), 38 | .addr_a(addr0_a), 39 | .addr_b(addr0_b), 40 | .we_a(we_a & (~we_sel)), 41 | .we_b(we_b & (~we_sel)), 42 | .clk(clk), 43 | .q_a(q0_ai), 44 | .q_b(q0_bi) 45 | ); 46 | 47 | mem_dp 48 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 49 | mem_dp1_r 50 | ( 51 | .data_a(data_ar), 52 | .data_b(data_br), 53 | .addr_a(addr1_a), 54 | .addr_b(addr1_b), 55 | .we_a(we_a & we_sel), 56 | .we_b(we_b & we_sel), 57 | .clk(clk), 58 | .q_a(q1_ar), 59 | .q_b(q1_br) 60 | ); 61 | 62 | mem_dp 63 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 64 | mem_dp1_i 65 | ( 66 | .data_a(data_ai), 67 | .data_b(data_bi), 68 | .addr_a(addr1_a), 69 | .addr_b(addr1_b), 70 | .we_a(we_a & we_sel), 71 | .we_b(we_b & we_sel), 72 | .clk(clk), 73 | .q_a(q1_ai), 74 | .q_b(q1_bi) 75 | ); 76 | 77 | 78 | always @ (posedge clk) 79 | begin 80 | if (q_sel) 81 | begin 82 | q_ar <= q1_ar; 83 | q_ai <= q1_ai; 84 | q_br <= q1_br; 85 | q_bi <= q1_bi; 86 | end 87 | else 88 | begin 89 | q_ar <= q0_ar; 90 | q_ai <= q0_ai; 91 | q_br <= q0_br; 92 | q_bi <= q0_bi; 93 | end 94 | end 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /FFT_processor.v: -------------------------------------------------------------------------------- 1 | module FFT_processor 2 | #(parameter DATA_WIDTH=18, parameter ADDR_WIDTH=5, parameter MIC_BITS = 18) 3 | ( 4 | input clk, rst, start, 5 | input mic_we, 6 | input [(ADDR_WIDTH-1):0] mic_addr, 7 | input [(MIC_BITS-1):0] mic_data, 8 | input [(ADDR_WIDTH-2):0] vga_addr, 9 | output [(DATA_WIDTH-1):0] vga_data_r, vga_data_i, 10 | output done 11 | ); 12 | 13 | wire [(DATA_WIDTH-1):0] mem_out_ar, mem_out_ai, mem_out_br, mem_out_bi; 14 | wire [(DATA_WIDTH-1):0] butterfly_out_ar, butterfly_out_ai, butterfly_out_br, butterfly_out_bi; 15 | wire [(ADDR_WIDTH-1):0] addr0_a, addr0_b, addr1_a, addr1_b; 16 | wire we_a, we_b, we_sel, q_sel; 17 | wire [(DATA_WIDTH-1):0] twiddle_r, twiddle_i; 18 | 19 | reg [(DATA_WIDTH-1):0] sel_mem_in_ar, sel_mem_in_ai, delay_mem_in_br, delay_mem_in_bi; 20 | 21 | 22 | FFT_mem 23 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 24 | mem 25 | ( 26 | .data_ar(sel_mem_in_ar), 27 | .data_ai(sel_mem_in_ai), 28 | .data_br(delay_mem_in_br), 29 | .data_bi(delay_mem_in_bi), 30 | .addr0_a(addr0_a), 31 | .addr0_b(addr0_b), 32 | .addr1_a(addr1_a), 33 | .addr1_b(addr1_b), 34 | .we_a(we_a), 35 | .we_b(we_b), 36 | .we_sel(we_sel), 37 | .q_sel(q_sel), 38 | .clk(clk), 39 | .q_ar(mem_out_ar), 40 | .q_ai(mem_out_ai), 41 | .q_br(mem_out_br), 42 | .q_bi(mem_out_bi), 43 | .vga_data_r(vga_data_r), 44 | .vga_data_i(vga_data_i) 45 | ); 46 | 47 | butterfly_pipeline 48 | #(.DATA_WIDTH(DATA_WIDTH)) 49 | butterfly 50 | ( 51 | .clk(clk), 52 | .in_ar(mem_out_ar), 53 | .in_ai(mem_out_ai), 54 | .in_br(mem_out_br), 55 | .in_bi(mem_out_bi), 56 | .twiddle_r(twiddle_r), 57 | .twiddle_i(twiddle_i), 58 | .out_ar(butterfly_out_ar), 59 | .out_ai(butterfly_out_ai), 60 | .out_br(butterfly_out_br), 61 | .out_bi(butterfly_out_bi) 62 | ); 63 | 64 | FFT_controller 65 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) 66 | controller 67 | ( 68 | .clk(clk), 69 | .rst(rst), 70 | .start(start), 71 | .we_a(we_a), 72 | .we_b(we_b), 73 | .we_sel(we_sel), 74 | .q_sel(q_sel), 75 | .addr0_a(addr0_a), 76 | .addr0_b(addr0_b), 77 | .addr1_a(addr1_a), 78 | .addr1_b(addr1_b), 79 | .twiddle_r(twiddle_r), 80 | .twiddle_i(twiddle_i), 81 | .mic_we(mic_we), 82 | .mic_addr(mic_addr), 83 | .vga_addr(vga_addr), 84 | .done(done) 85 | ); 86 | 87 | always @ (posedge clk) 88 | begin 89 | delay_mem_in_br <= butterfly_out_br; 90 | delay_mem_in_bi <= butterfly_out_bi; 91 | 92 | if(~done) 93 | begin 94 | sel_mem_in_ar <= butterfly_out_ar; 95 | sel_mem_in_ai <= butterfly_out_ai; 96 | end 97 | else 98 | begin 99 | sel_mem_in_ar <= {{(DATA_WIDTH - MIC_BITS){mic_data[MIC_BITS-1]}}, mic_data}; 100 | sel_mem_in_ai <= 0; 101 | end 102 | end 103 | endmodule 104 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA_AudioVisualizer 2 | Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA development board. Reads audio data from an external mic and displays the frequency components on a VGA monitor. 3 | 4 | This project is inspired by Kenny Chan's (@kennych418) repo of the same name, and sections of the Verilog from the mic translator and VGA generator are draw directly from his project. The architecture of the FFT processor is drawn from [this](http://web.mit.edu/6.111/www/f2017/handouts/FFTtutorial121102.pdf?fbclid=IwAR1bvgwIdH4KpCR6y5HdHb4cVpvUhySQTUzOMBI4a99tWIJc6waVf-O8PHQ) paper. 5 | 6 | ## To Run 7 | Create a new Quartus project, select the device you wish to use, and import the files in this repo (besides this README) into the project. Click Assignment -> Device, then click Device and Pin Options. Select the Configuration option on the left, and for Configuration mode select Single Uncompressed Image with Memory Initialization. 8 | 9 | Open the twiddle_script.py file and edit **data_width** to the number of bits you will carry in the FFT calculation, and edit the **addr_width** to log2(s), where s is the number of samples you wish to take. Running this script in your project folder will generate **rom_r_init.txt** and **rom_i_init.txt**, which are used to initialize the ROMs which hold the twiddle values for the FFT calculation. 10 | 11 | Similarly setting the **DATA_WIDTH** and **ADDR_WIDTH** parameters in DAV.v will cause these parameters to trickle down to the rest of the design units. Note that though much of the design units will adjust nicely based on these parameters, not everything will work immediately. Mainly, the interface between the FFT processor and the VGA generator requires **ADDR_WIDTH** to be an odd number (a small change needs to be made if **ADDR_WIDTH** is even), and the VGA generator output logic for VGA_R is hard coded to work for a 512-point DFT calculation. 12 | 13 | Finally, use the Quartus Pin Planner to associate the top module's ports to physical pins on the FPGA. 14 | 15 | ## Overview 16 | I will write a more detailed design description when I get a chance. For now, I will provide a super brief description of what is going on. 17 | 18 | The mic translator continuously reads audio data and fills the mic FIFO, which holds the data for one set of samples. Once this FIFO is filled, the data will be read out of the FIFO and written into one of the memories used in the FFT processor. Once the data is transferred, a start signal is sent to the FFT processor, which will start the DFT calculation. 19 | 20 | The idea behind the architecture of the FFT processor can be understood by reading the paper linked in the second paragraph of this README. 21 | 22 | Once the DFT calculation is done, the VGA generator reads the transform data out of one of the FFT memories, passes it through a complex magnitude estimator, and writes the result into the VGA FIFO (it’s not really a FIFO, but that's what I call it). As the VGA logic scans across the screen from left to right, the values are read from the memory one by one and compared to the vertical counter to determine whether to light up the pixel or not. Instead of showing all 512 points of the frequency data (about half of which are redundant due to the input signal being real), this design only displays frequencies 1 to 256 (inclusive, counting from 0) from the DFT calculation. With 256 points being displayed and 640 horizontal pixels assumed for the VGA monitor, each point gets 2.5 pixels. To accomplish this, the frequency points are alternately assigned 2 then 3 pixels each, allowing for the 256 frequency points to fill the whole display. 23 | 24 | The sampling rate of the mic translator is about 39 kHz. With 256 frequencies being displayed, the frequency range of the output is about 76 Hz to 19.5 kHz, which is approximately equal to the human range of hearing. 25 | -------------------------------------------------------------------------------- /mic_translator.v: -------------------------------------------------------------------------------- 1 | `define _CALIBRATION {13'd226, 5'd0} 2 | 3 | module mic_translator 4 | #(parameter ADDR_WIDTH = 6, parameter MIC_BITS = 18, parameter DELAY_START_BITS = 3) 5 | ( 6 | input clk, rst, DOUT, 7 | output start, 8 | output reg BCLK, LRCLK, mic_we, 9 | output reg [(ADDR_WIDTH-1):0] mic_addr, 10 | output [(MIC_BITS-1):0] mic_data 11 | ); 12 | 13 | reg [4:0] negedge_cnt, posedge_cnt; 14 | reg [(ADDR_WIDTH-1):0] fifo_wr_addr, fifo_rd_addr; 15 | reg [(MIC_BITS-1):0] fifo_wr_data, data_buffer; 16 | reg fifo_we, begin_transfer, reading, LR; 17 | reg [(DELAY_START_BITS - 1):0] delay_start; 18 | wire [(MIC_BITS-1):0] fifo_rd_data; 19 | 20 | assign start = delay_start[(DELAY_START_BITS - 1)]; 21 | assign mic_data = fifo_rd_data; 22 | 23 | 24 | mic_fifo 25 | #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(MIC_BITS)) 26 | mic_data_fifo 27 | ( 28 | .clk(clk), 29 | .fifo_we(fifo_we), 30 | .fifo_wr_addr(fifo_wr_addr), 31 | .fifo_rd_addr(fifo_rd_addr), 32 | .fifo_wr_data(fifo_wr_data), 33 | .fifo_rd_data(fifo_rd_data) 34 | ); 35 | 36 | 37 | initial 38 | begin 39 | BCLK = 1; 40 | LRCLK = 1; 41 | negedge_cnt = 0; 42 | LR = 1; 43 | begin_transfer = 0; 44 | fifo_wr_addr = 0; 45 | fifo_we = 0; 46 | posedge_cnt = 0; 47 | delay_start = 0; 48 | mic_we = 0; 49 | reading = 0; 50 | end 51 | 52 | 53 | always @ (clk) begin 54 | if (~rst) 55 | BCLK <= 1; 56 | else 57 | BCLK <= clk; 58 | end 59 | 60 | 61 | //output LRCLK to mic 62 | always @ (negedge BCLK, negedge rst) 63 | begin 64 | if (~rst) 65 | begin 66 | LRCLK <= 1; 67 | negedge_cnt <= 0; 68 | end 69 | else if (negedge_cnt < 31) 70 | begin 71 | LRCLK <= LRCLK; 72 | negedge_cnt <= negedge_cnt + 1; 73 | end 74 | else 75 | begin 76 | LRCLK <= ~LRCLK; 77 | negedge_cnt <= 0; 78 | end 79 | end 80 | 81 | 82 | //reading mic data and writing to FIFO 83 | always @ (posedge BCLK, negedge rst) 84 | begin 85 | if (~rst) 86 | begin 87 | LR <= 1; 88 | begin_transfer <= 0; 89 | fifo_wr_addr <= 0; 90 | fifo_we <= 0; 91 | posedge_cnt <= 0; 92 | end 93 | else if (posedge_cnt == MIC_BITS) 94 | begin 95 | LR <= LR; 96 | begin_transfer <= 0; 97 | fifo_wr_addr <= fifo_wr_addr; 98 | fifo_we <= (~LR); 99 | posedge_cnt <= posedge_cnt+1; 100 | end 101 | else if (posedge_cnt == 31) 102 | begin 103 | LR <= ~LR; 104 | begin_transfer <= ((~LR) && (fifo_wr_addr == (2**(ADDR_WIDTH)-1)))? 1 : 0; 105 | fifo_wr_addr <= (~LR)? fifo_wr_addr + 1 : fifo_wr_addr; 106 | fifo_we <= 0; 107 | posedge_cnt <= 0; 108 | end 109 | else 110 | begin 111 | LR <= LR; 112 | begin_transfer <= 0; 113 | fifo_wr_addr <= fifo_wr_addr; 114 | fifo_we <= 0; 115 | posedge_cnt <= posedge_cnt+1; 116 | end 117 | end 118 | 119 | always @ (posedge clk) 120 | begin 121 | fifo_wr_data <= data_buffer + `_CALIBRATION; 122 | 123 | if ((posedge_cnt < MIC_BITS) && (~LR)) 124 | begin 125 | data_buffer[0] <= DOUT; 126 | data_buffer[(MIC_BITS-1):1] <= data_buffer[(MIC_BITS-2):0]; 127 | end 128 | else 129 | data_buffer <= data_buffer; 130 | end 131 | 132 | 133 | //reading FIFO data and writing to FFT processor 134 | always @ (posedge clk) 135 | begin 136 | mic_addr <= fifo_rd_addr; 137 | 138 | if (~rst) 139 | begin 140 | delay_start <= 0; 141 | mic_we <= 0; 142 | reading <= 0; 143 | end 144 | else 145 | begin 146 | delay_start[(DELAY_START_BITS-1):1] <= delay_start[(DELAY_START_BITS-2):0]; 147 | mic_we <= reading; 148 | 149 | if (begin_transfer) 150 | begin 151 | reading <= 1; 152 | delay_start[0] <= 0; 153 | end 154 | else if (fifo_rd_addr == (2**ADDR_WIDTH-1)) 155 | begin 156 | reading <= 0; 157 | delay_start[0] <= 1; 158 | end 159 | else 160 | begin 161 | reading <= reading; 162 | delay_start[0] <= 0; 163 | end 164 | end 165 | 166 | if (reading) 167 | fifo_rd_addr <= fifo_rd_addr + 1; 168 | else 169 | fifo_rd_addr <= 0; 170 | 171 | end 172 | 173 | endmodule 174 | -------------------------------------------------------------------------------- /FFT_controller.v: -------------------------------------------------------------------------------- 1 | module FFT_controller 2 | #(parameter DATA_WIDTH=18, parameter ADDR_WIDTH=4, parameter PIPELINE_DELAY = 10) 3 | ( 4 | input clk, rst, start, 5 | output we_sel, q_sel, 6 | input mic_we, 7 | input [(ADDR_WIDTH-1):0] mic_addr, 8 | input [(ADDR_WIDTH-2):0] vga_addr, 9 | output reg we_a, we_b, 10 | output reg [(ADDR_WIDTH-1):0] addr0_a, addr0_b, addr1_a, addr1_b, 11 | output reg [(DATA_WIDTH-1):0] twiddle_r, twiddle_i, 12 | output reg done 13 | ); 14 | 15 | reg [($clog2(ADDR_WIDTH)-1):0] i, next_i; 16 | reg [($clog2(PIPELINE_DELAY+2**(ADDR_WIDTH-1)-1)-1):0] j, next_j; 17 | reg [(ADDR_WIDTH-1):0] mem_addr_unshifted_a, mem_addr_unshifted_b, mem_addr_a, mem_addr_b, next_mem_addr_a, next_mem_addr_b; 18 | reg [((ADDR_WIDTH*2)-1):0] temp_a, temp_b; 19 | reg [(ADDR_WIDTH-2):0] twiddle_addr, twiddle_mask, next_twiddle_mask; 20 | reg next_done; 21 | reg [(ADDR_WIDTH-1):0] next_addr0_a, next_addr0_b, next_addr1_a, next_addr1_b; 22 | reg next_we_a, next_we_b; 23 | wire [(DATA_WIDTH-1):0] rom_out_r, rom_out_i, delay_rom_out_r, delay_rom_out_i; 24 | wire [(ADDR_WIDTH-1):0] delay_mem_addr_a, delay_mem_addr_b; 25 | wire [(ADDR_WIDTH-1):0] mic_addr_reversed; 26 | 27 | assign we_sel = (~i[0]) & (~done); 28 | assign q_sel = i[0]; 29 | 30 | ROM 31 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH-1), .REAL(1)) 32 | twiddle_rom_r 33 | ( 34 | .addr(twiddle_addr), 35 | .clk(clk), 36 | .q(rom_out_r) 37 | ); 38 | 39 | ROM 40 | #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH-1), .REAL(0)) 41 | twiddle_rom_i 42 | ( 43 | .addr(twiddle_addr), 44 | .clk(clk), 45 | .q(rom_out_i) 46 | ); 47 | 48 | delay 49 | #(.WIDTH(DATA_WIDTH), .CYCLES(2)) 50 | delay_rom_r 51 | ( 52 | .clk(clk), 53 | .data_in(rom_out_r), 54 | .data_out(delay_rom_out_r) 55 | ); 56 | 57 | delay 58 | #(.WIDTH(DATA_WIDTH), .CYCLES(2)) 59 | delay_rom_i 60 | ( 61 | .clk(clk), 62 | .data_in(rom_out_i), 63 | .data_out(delay_rom_out_i) 64 | ); 65 | 66 | 67 | delay 68 | #(.WIDTH(ADDR_WIDTH), .CYCLES(PIPELINE_DELAY-4)) 69 | delay_mem_a 70 | ( 71 | .clk(clk), 72 | .data_in(mem_addr_a), 73 | .data_out(delay_mem_addr_a) 74 | ); 75 | 76 | delay 77 | #(.WIDTH(ADDR_WIDTH), .CYCLES(PIPELINE_DELAY-4)) 78 | delay_mem_b 79 | ( 80 | .clk(clk), 81 | .data_in(mem_addr_b), 82 | .data_out(delay_mem_addr_b) 83 | ); 84 | 85 | reverse 86 | #(.WIDTH(ADDR_WIDTH)) 87 | mic_reverse 88 | ( 89 | .data_in(mic_addr), 90 | .data_out(mic_addr_reversed) 91 | ); 92 | 93 | 94 | //sequential 95 | always @ (posedge clk) 96 | begin 97 | addr0_a <= next_addr0_a; 98 | addr0_b <= next_addr0_b; 99 | addr1_a <= next_addr1_a; 100 | addr1_b <= next_addr1_b; 101 | twiddle_r <= delay_rom_out_r; 102 | twiddle_i <= delay_rom_out_i; 103 | twiddle_addr <= j[(ADDR_WIDTH-2):0] & twiddle_mask; 104 | twiddle_mask <= next_twiddle_mask; 105 | mem_addr_unshifted_a[0] <= 0; 106 | mem_addr_unshifted_a[(ADDR_WIDTH-1):1] <= j[(ADDR_WIDTH-2):0]; 107 | mem_addr_unshifted_b[0] <= 1; 108 | mem_addr_unshifted_b[(ADDR_WIDTH-1):1] <= j[(ADDR_WIDTH-2):0]; 109 | mem_addr_a <= next_mem_addr_a; 110 | mem_addr_b <= next_mem_addr_b; 111 | 112 | 113 | if(~rst) 114 | begin 115 | done <= 1; 116 | we_a <= 0; 117 | we_b <= 0; 118 | i <= 0; 119 | j <= 0; 120 | end 121 | else 122 | begin 123 | done <= next_done; 124 | we_a <= next_we_a; 125 | we_b <= next_we_b; 126 | i <= next_i; 127 | j <= next_j; 128 | end 129 | 130 | end 131 | 132 | 133 | //combinational 134 | always @ (*) 135 | begin 136 | //default values 137 | next_i = 0; 138 | next_j = 0; 139 | next_twiddle_mask = 0; 140 | next_done = done; 141 | next_we_a = 0; 142 | next_we_b = 0; 143 | next_addr0_a = mem_addr_a; 144 | next_addr0_b = mem_addr_b; 145 | next_addr1_a = delay_mem_addr_a; 146 | next_addr1_b = delay_mem_addr_b; 147 | 148 | //barrel shifter 149 | temp_a = {mem_addr_unshifted_a, mem_addr_unshifted_a}; 150 | temp_b = {mem_addr_unshifted_b, mem_addr_unshifted_b}; 151 | temp_a = temp_a << i; 152 | temp_b = temp_b << i; 153 | next_mem_addr_a = temp_a[((ADDR_WIDTH*2)-1):ADDR_WIDTH]; 154 | next_mem_addr_b = temp_b[((ADDR_WIDTH*2)-1):ADDR_WIDTH]; 155 | 156 | 157 | if (~done) 158 | begin 159 | if (i[0]) 160 | begin 161 | next_addr0_a = delay_mem_addr_a; 162 | next_addr0_b = delay_mem_addr_b; 163 | next_addr1_a = mem_addr_a; 164 | next_addr1_b = mem_addr_b; 165 | end 166 | 167 | if (j >= (PIPELINE_DELAY-2) && j < (PIPELINE_DELAY+2**(ADDR_WIDTH-1)-2)) 168 | begin 169 | next_we_a = 1; 170 | next_we_b = 1; 171 | end 172 | end 173 | else 174 | begin 175 | next_we_a = mic_we; 176 | next_addr0_a = mic_addr_reversed; 177 | next_addr1_a = {1'b0, vga_addr} + 1; //plus one cuz i want to display points 1-256, not 0 to 255 178 | end 179 | 180 | 181 | if (~done) 182 | begin 183 | if (j == (PIPELINE_DELAY+2**(ADDR_WIDTH-1)-2)) 184 | begin 185 | if (i == (ADDR_WIDTH-1)) 186 | next_done = 1; 187 | else 188 | begin 189 | next_i = i + 1; 190 | next_j = 0; 191 | next_twiddle_mask[(ADDR_WIDTH-3):0] = twiddle_mask[(ADDR_WIDTH-2):1]; 192 | next_twiddle_mask[(ADDR_WIDTH-2)] = 1; 193 | end 194 | end 195 | else 196 | begin 197 | next_i = i; 198 | next_j = j + 1; 199 | next_twiddle_mask = twiddle_mask; 200 | end 201 | end 202 | else 203 | begin 204 | if (start) 205 | next_done = 0; 206 | end 207 | end 208 | endmodule 209 | -------------------------------------------------------------------------------- /vga_generator.v: -------------------------------------------------------------------------------- 1 | module vga_generator 2 | #(parameter ADDR_WIDTH = 9, parameter DATA_WIDTH = 18, parameter MEM_DATA_WIDTH = 9) 3 | ( 4 | input done, vga_clk, FFT_clk, rst, 5 | input [(DATA_WIDTH-1):0] FFT_data_r, FFT_data_i, 6 | output reg [(ADDR_WIDTH-2):0] FFT_addr, 7 | output reg [3:0] VGA_R, 8 | output [3:0] VGA_G, VGA_B, 9 | output VGA_HS, VGA_VS 10 | ); 11 | 12 | reg [(ADDR_WIDTH-2):0] vga_addr; 13 | wire [(ADDR_WIDTH-2):0] fifo_wr_addr; 14 | wire [(ADDR_WIDTH-2):0] delay_FFT_addr; 15 | wire [(MEM_DATA_WIDTH-1):0] vga_data, fifo_wr_data; 16 | reg [2:0] reg_done, reading, counter; 17 | wire hblank, vblank, newline; 18 | wire [9:0] horizontal_count, vertical_count; 19 | wire addr_rst, fifo_we; 20 | 21 | wire [(DATA_WIDTH-1):0] abs_FFT_data_r = (FFT_data_r[DATA_WIDTH-1])? ((~FFT_data_r) + 1) : FFT_data_r; 22 | wire [(DATA_WIDTH-1):0] abs_FFT_data_i = (FFT_data_i[DATA_WIDTH-1])? ((~FFT_data_i) + 1) : FFT_data_i; 23 | 24 | 25 | assign VGA_G = 0; 26 | assign VGA_B = 0; 27 | 28 | 29 | vga_fifo 30 | #(.ADDR_WIDTH(ADDR_WIDTH-1), .DATA_WIDTH(9)) 31 | vga_data_fifo 32 | ( 33 | .FFT_clk(FFT_clk), 34 | .vga_clk(vga_clk), 35 | .fifo_we(fifo_we), 36 | .fifo_wr_addr(fifo_wr_addr), 37 | .fifo_rd_addr(vga_addr), 38 | .fifo_wr_data(fifo_wr_data), 39 | .fifo_rd_data(vga_data) 40 | ); 41 | 42 | delay 43 | #(.WIDTH(ADDR_WIDTH-1), .CYCLES(2)) 44 | del_FFT_addr 45 | ( 46 | .clk(FFT_clk), 47 | .data_in(FFT_addr), 48 | .data_out(delay_FFT_addr) 49 | ); 50 | 51 | vsync vertical( 52 | .newline_in(newline), 53 | .rst(rst), 54 | .vsync_out(VGA_VS), 55 | .blank_out(vblank), 56 | .pixel_count(vertical_count) 57 | ); 58 | 59 | hsync horizontal 60 | ( 61 | .clk(vga_clk), 62 | .rst(rst), 63 | .hsync_out(VGA_HS), 64 | .blank_out(hblank), 65 | .newline_out(newline), 66 | .pixel_count(horizontal_count), 67 | .addr_rst(addr_rst) 68 | ); 69 | 70 | magnitude_estimate 71 | #(.ADDR_WIDTH(ADDR_WIDTH-1), .DATA_WIDTH(DATA_WIDTH), .MEM_DATA_WIDTH(MEM_DATA_WIDTH)) 72 | mag_est 73 | ( 74 | .clk(FFT_clk), 75 | .rst(rst), 76 | .we(reading[2]), 77 | .addr(delay_FFT_addr), 78 | .abs_FFT_data_r(abs_FFT_data_r), 79 | .abs_FFT_data_i(abs_FFT_data_i), 80 | .delay_we(fifo_we), 81 | .delay_addr(fifo_wr_addr), 82 | .data(fifo_wr_data) 83 | ); 84 | 85 | 86 | initial 87 | begin 88 | reg_done = 3'b111; 89 | reading = 0; 90 | end 91 | 92 | always @ (posedge FFT_clk) 93 | begin 94 | if (~rst) 95 | begin 96 | reg_done <= 3'b111; 97 | reading <= 0; 98 | end 99 | else 100 | begin 101 | reg_done[0] <= done; 102 | reg_done[2:1] <= reg_done[1:0]; 103 | reading[2:1] <= reading[1:0]; 104 | 105 | 106 | if ((~reg_done[2]) && reg_done[1]) 107 | reading[0] <= 1; 108 | else if (FFT_addr == (2**(ADDR_WIDTH-1)-1)) 109 | reading[0] <= 0; 110 | else 111 | reading[0] <= reading[0]; 112 | end 113 | 114 | if (reading[0]) 115 | FFT_addr <= FFT_addr + 1; 116 | else 117 | FFT_addr <= 0; 118 | 119 | 120 | end 121 | 122 | 123 | initial 124 | begin 125 | VGA_R = 0; 126 | vga_addr = 0; 127 | counter = 0; 128 | end 129 | 130 | 131 | always @ (posedge vga_clk) 132 | begin 133 | if (~rst) 134 | VGA_R <= 0; 135 | else if (hblank || vblank) 136 | VGA_R <= 0; 137 | else if (vertical_count[(MEM_DATA_WIDTH-1):0] > vga_data) 138 | VGA_R <= 4'b1100; 139 | else 140 | VGA_R <= 0; 141 | end 142 | 143 | always @ (posedge vga_clk) 144 | begin 145 | if (~rst) 146 | begin 147 | vga_addr <= 0; 148 | counter <= 0; 149 | end 150 | else if (addr_rst) 151 | begin 152 | vga_addr <= 0; 153 | counter <= 0; 154 | end 155 | else if (counter == 4) 156 | begin 157 | vga_addr <= vga_addr + 1; 158 | counter <= 0; 159 | end 160 | else if (counter == 1) 161 | begin 162 | vga_addr <= vga_addr + 1; 163 | counter <= counter + 1; 164 | end 165 | else 166 | begin 167 | vga_addr <= vga_addr; 168 | counter <= counter + 1; 169 | end 170 | 171 | end 172 | 173 | endmodule 174 | 175 | 176 | 177 | module hsync 178 | ( 179 | input clk, rst, 180 | output reg hsync_out, 181 | output reg blank_out, 182 | output reg newline_out, 183 | output [9:0] pixel_count, 184 | output reg addr_rst 185 | ); 186 | 187 | parameter TOTAL_COUNTER = 800; 188 | parameter SYNC = 96; 189 | parameter BACKPORCH = 48; 190 | parameter DISPLAY = 640; 191 | parameter FRONTPORCH = 16; 192 | 193 | reg [9:0] counter; 194 | 195 | assign pixel_count = counter; 196 | 197 | initial 198 | begin 199 | counter = 0; 200 | addr_rst = 0; 201 | hsync_out = 1; 202 | blank_out = 0; 203 | newline_out = 0; 204 | end 205 | 206 | 207 | always @ (posedge clk) begin 208 | if (~rst) 209 | counter <= 0; 210 | else if(counter < TOTAL_COUNTER) //reset counter if every 800 clk cycles 211 | counter <= counter + 1; 212 | else 213 | counter <= 0; 214 | end 215 | 216 | always @ (posedge clk) begin 217 | if(counter == TOTAL_COUNTER-1) //reset counter if every 800 clk cycles 218 | addr_rst <= 1; 219 | else 220 | addr_rst <= 0; 221 | end 222 | 223 | always @ (posedge clk) begin //hsync 224 | if(counter < (DISPLAY + FRONTPORCH)) 225 | hsync_out <= 1; 226 | else if(counter >= (DISPLAY + FRONTPORCH) && counter < (DISPLAY + FRONTPORCH + SYNC)) 227 | hsync_out <= 0; 228 | else if(counter >= (DISPLAY + FRONTPORCH + SYNC)) 229 | hsync_out <= 1; 230 | end 231 | 232 | always @ (posedge clk) begin //blank, high during display interval 233 | if(counter < DISPLAY) 234 | blank_out <= 0; 235 | else 236 | blank_out <= 1; 237 | end 238 | 239 | always @ (posedge clk) begin //newline 240 | if(counter == 0) 241 | newline_out <= 1; 242 | else 243 | newline_out <= 0; 244 | end 245 | 246 | endmodule 247 | 248 | 249 | module vsync 250 | ( 251 | input newline_in, rst, 252 | output reg vsync_out, 253 | output reg blank_out, 254 | output [9:0] pixel_count 255 | ); 256 | 257 | parameter TOTAL_COUNTER = 525; 258 | parameter SYNC = 2; 259 | parameter BACKPORCH = 33; 260 | parameter DISPLAY = 480; 261 | parameter FRONTPORCH = 10; 262 | 263 | reg [9:0] counter; 264 | 265 | assign pixel_count = counter; 266 | 267 | initial 268 | begin 269 | counter = 0; 270 | vsync_out = 0; 271 | blank_out = 0; 272 | end 273 | 274 | always @ (posedge newline_in) begin //counter 275 | if (~rst) 276 | counter <= 0; 277 | else if(counter < TOTAL_COUNTER) 278 | counter <= counter + 1; 279 | else 280 | counter <= 0; 281 | end 282 | 283 | always @ (posedge newline_in) begin //vsync 284 | if(counter < (DISPLAY + FRONTPORCH)) 285 | vsync_out <= 1; 286 | else if(counter >= (DISPLAY + FRONTPORCH) && counter < (DISPLAY + FRONTPORCH + SYNC)) 287 | vsync_out <= 0; 288 | else if(counter >= (DISPLAY + FRONTPORCH + SYNC)) 289 | vsync_out <= 1; 290 | end 291 | 292 | always @ (posedge newline_in) begin //blank 293 | if(counter < DISPLAY) 294 | blank_out <= 0; 295 | else 296 | blank_out <= 1; 297 | end 298 | 299 | endmodule 300 | 301 | 302 | -------------------------------------------------------------------------------- /zeros.txt: -------------------------------------------------------------------------------- 1 | 0000000000000000000000 2 | 0000000000000000000000 3 | 0000000000000000000000 4 | 0000000000000000000000 5 | 0000000000000000000000 6 | 0000000000000000000000 7 | 0000000000000000000000 8 | 0000000000000000000000 9 | 0000000000000000000000 10 | 0000000000000000000000 11 | 0000000000000000000000 12 | 0000000000000000000000 13 | 0000000000000000000000 14 | 0000000000000000000000 15 | 0000000000000000000000 16 | 0000000000000000000000 17 | 0000000000000000000000 18 | 0000000000000000000000 19 | 0000000000000000000000 20 | 0000000000000000000000 21 | 0000000000000000000000 22 | 0000000000000000000000 23 | 0000000000000000000000 24 | 0000000000000000000000 25 | 0000000000000000000000 26 | 0000000000000000000000 27 | 0000000000000000000000 28 | 0000000000000000000000 29 | 0000000000000000000000 30 | 0000000000000000000000 31 | 0000000000000000000000 32 | 0000000000000000000000 33 | 0000000000000000000000 34 | 0000000000000000000000 35 | 0000000000000000000000 36 | 0000000000000000000000 37 | 0000000000000000000000 38 | 0000000000000000000000 39 | 0000000000000000000000 40 | 0000000000000000000000 41 | 0000000000000000000000 42 | 0000000000000000000000 43 | 0000000000000000000000 44 | 0000000000000000000000 45 | 0000000000000000000000 46 | 0000000000000000000000 47 | 0000000000000000000000 48 | 0000000000000000000000 49 | 0000000000000000000000 50 | 0000000000000000000000 51 | 0000000000000000000000 52 | 0000000000000000000000 53 | 0000000000000000000000 54 | 0000000000000000000000 55 | 0000000000000000000000 56 | 0000000000000000000000 57 | 0000000000000000000000 58 | 0000000000000000000000 59 | 0000000000000000000000 60 | 0000000000000000000000 61 | 0000000000000000000000 62 | 0000000000000000000000 63 | 0000000000000000000000 64 | 0000000000000000000000 65 | 0000000000000000000000 66 | 0000000000000000000000 67 | 0000000000000000000000 68 | 0000000000000000000000 69 | 0000000000000000000000 70 | 0000000000000000000000 71 | 0000000000000000000000 72 | 0000000000000000000000 73 | 0000000000000000000000 74 | 0000000000000000000000 75 | 0000000000000000000000 76 | 0000000000000000000000 77 | 0000000000000000000000 78 | 0000000000000000000000 79 | 0000000000000000000000 80 | 0000000000000000000000 81 | 0000000000000000000000 82 | 0000000000000000000000 83 | 0000000000000000000000 84 | 0000000000000000000000 85 | 0000000000000000000000 86 | 0000000000000000000000 87 | 0000000000000000000000 88 | 0000000000000000000000 89 | 0000000000000000000000 90 | 0000000000000000000000 91 | 0000000000000000000000 92 | 0000000000000000000000 93 | 0000000000000000000000 94 | 0000000000000000000000 95 | 0000000000000000000000 96 | 0000000000000000000000 97 | 0000000000000000000000 98 | 0000000000000000000000 99 | 0000000000000000000000 100 | 0000000000000000000000 101 | 0000000000000000000000 102 | 0000000000000000000000 103 | 0000000000000000000000 104 | 0000000000000000000000 105 | 0000000000000000000000 106 | 0000000000000000000000 107 | 0000000000000000000000 108 | 0000000000000000000000 109 | 0000000000000000000000 110 | 0000000000000000000000 111 | 0000000000000000000000 112 | 0000000000000000000000 113 | 0000000000000000000000 114 | 0000000000000000000000 115 | 0000000000000000000000 116 | 0000000000000000000000 117 | 0000000000000000000000 118 | 0000000000000000000000 119 | 0000000000000000000000 120 | 0000000000000000000000 121 | 0000000000000000000000 122 | 0000000000000000000000 123 | 0000000000000000000000 124 | 0000000000000000000000 125 | 0000000000000000000000 126 | 0000000000000000000000 127 | 0000000000000000000000 128 | 0000000000000000000000 129 | 0000000000000000000000 130 | 0000000000000000000000 131 | 0000000000000000000000 132 | 0000000000000000000000 133 | 0000000000000000000000 134 | 0000000000000000000000 135 | 0000000000000000000000 136 | 0000000000000000000000 137 | 0000000000000000000000 138 | 0000000000000000000000 139 | 0000000000000000000000 140 | 0000000000000000000000 141 | 0000000000000000000000 142 | 0000000000000000000000 143 | 0000000000000000000000 144 | 0000000000000000000000 145 | 0000000000000000000000 146 | 0000000000000000000000 147 | 0000000000000000000000 148 | 0000000000000000000000 149 | 0000000000000000000000 150 | 0000000000000000000000 151 | 0000000000000000000000 152 | 0000000000000000000000 153 | 0000000000000000000000 154 | 0000000000000000000000 155 | 0000000000000000000000 156 | 0000000000000000000000 157 | 0000000000000000000000 158 | 0000000000000000000000 159 | 0000000000000000000000 160 | 0000000000000000000000 161 | 0000000000000000000000 162 | 0000000000000000000000 163 | 0000000000000000000000 164 | 0000000000000000000000 165 | 0000000000000000000000 166 | 0000000000000000000000 167 | 0000000000000000000000 168 | 0000000000000000000000 169 | 0000000000000000000000 170 | 0000000000000000000000 171 | 0000000000000000000000 172 | 0000000000000000000000 173 | 0000000000000000000000 174 | 0000000000000000000000 175 | 0000000000000000000000 176 | 0000000000000000000000 177 | 0000000000000000000000 178 | 0000000000000000000000 179 | 0000000000000000000000 180 | 0000000000000000000000 181 | 0000000000000000000000 182 | 0000000000000000000000 183 | 0000000000000000000000 184 | 0000000000000000000000 185 | 0000000000000000000000 186 | 0000000000000000000000 187 | 0000000000000000000000 188 | 0000000000000000000000 189 | 0000000000000000000000 190 | 0000000000000000000000 191 | 0000000000000000000000 192 | 0000000000000000000000 193 | 0000000000000000000000 194 | 0000000000000000000000 195 | 0000000000000000000000 196 | 0000000000000000000000 197 | 0000000000000000000000 198 | 0000000000000000000000 199 | 0000000000000000000000 200 | 0000000000000000000000 201 | 0000000000000000000000 202 | 0000000000000000000000 203 | 0000000000000000000000 204 | 0000000000000000000000 205 | 0000000000000000000000 206 | 0000000000000000000000 207 | 0000000000000000000000 208 | 0000000000000000000000 209 | 0000000000000000000000 210 | 0000000000000000000000 211 | 0000000000000000000000 212 | 0000000000000000000000 213 | 0000000000000000000000 214 | 0000000000000000000000 215 | 0000000000000000000000 216 | 0000000000000000000000 217 | 0000000000000000000000 218 | 0000000000000000000000 219 | 0000000000000000000000 220 | 0000000000000000000000 221 | 0000000000000000000000 222 | 0000000000000000000000 223 | 0000000000000000000000 224 | 0000000000000000000000 225 | 0000000000000000000000 226 | 0000000000000000000000 227 | 0000000000000000000000 228 | 0000000000000000000000 229 | 0000000000000000000000 230 | 0000000000000000000000 231 | 0000000000000000000000 232 | 0000000000000000000000 233 | 0000000000000000000000 234 | 0000000000000000000000 235 | 0000000000000000000000 236 | 0000000000000000000000 237 | 0000000000000000000000 238 | 0000000000000000000000 239 | 0000000000000000000000 240 | 0000000000000000000000 241 | 0000000000000000000000 242 | 0000000000000000000000 243 | 0000000000000000000000 244 | 0000000000000000000000 245 | 0000000000000000000000 246 | 0000000000000000000000 247 | 0000000000000000000000 248 | 0000000000000000000000 249 | 0000000000000000000000 250 | 0000000000000000000000 251 | 0000000000000000000000 252 | 0000000000000000000000 253 | 0000000000000000000000 254 | 0000000000000000000000 255 | 0000000000000000000000 256 | 0000000000000000000000 257 | -------------------------------------------------------------------------------- /rom_i_init.txt: -------------------------------------------------------------------------------- 1 | 0000000000000000000000 2 | 1111111001101101111001 3 | 1111110011011011110101 4 | 1111101101001001111010 5 | 1111100110111000001010 6 | 1111100000100110101001 7 | 1111011010010101011100 8 | 1111010100000100100110 9 | 1111001101110100001011 10 | 1111000111100100001111 11 | 1111000001010100110110 12 | 1110111011000110000100 13 | 1110110100110111111100 14 | 1110101110101010100010 15 | 1110101000011101111011 16 | 1110100010010010001010 17 | 1110011100000111010010 18 | 1110010101111101011000 19 | 1110001111110100011111 20 | 1110001001101100101100 21 | 1110000011100110000010 22 | 1101111101100000100100 23 | 1101110111011100010111 24 | 1101110001011001011110 25 | 1101101011010111111101 26 | 1101100101010111111000 27 | 1101011111011001010010 28 | 1101011001011100001111 29 | 1101010011100000110011 30 | 1101001101100111000001 31 | 1101000111101110111101 32 | 1101000001111000101011 33 | 1100111100000100001111 34 | 1100110110010001101011 35 | 1100110000100001000011 36 | 1100101010110010011100 37 | 1100100101000101111000 38 | 1100011111011011011011 39 | 1100011001110011001001 40 | 1100010100001101000100 41 | 1100001110101001010001 42 | 1100001001000111110011 43 | 1100000011101000101110 44 | 1011111110001100000011 45 | 1011111000110001111000 46 | 1011110011011010010000 47 | 1011101110000101001101 48 | 1011101000110010110011 49 | 1011100011100011000101 50 | 1011011110010110000110 51 | 1011011001001011111011 52 | 1011010100000100100101 53 | 1011001111000000001000 54 | 1011001001111110100111 55 | 1011000101000000000110 56 | 1011000000000100100111 57 | 1010111011001100001101 58 | 1010110110010110111011 59 | 1010110001100100110101 60 | 1010101100110101111101 61 | 1010101000001010010111 62 | 1010100011100010000100 63 | 1010011110111101001001 64 | 1010011010011011100111 65 | 1010010101111101100010 66 | 1010010001100010111100 67 | 1010001101001011111000 68 | 1010001000111000011001 69 | 1010000100101000100001 70 | 1010000000011100010011 71 | 1001111100010011110010 72 | 1001111000001111000000 73 | 1001110100001110000000 74 | 1001110000010000110011 75 | 1001101100010111011110 76 | 1001101000100010000001 77 | 1001100100110000100000 78 | 1001100001000010111100 79 | 1001011101011001011000 80 | 1001011001110011110111 81 | 1001010110010010011010 82 | 1001010010110101000011 83 | 1001001111011011110110 84 | 1001001100000110110011 85 | 1001001000110101111101 86 | 1001000101101001010110 87 | 1001000010100000111111 88 | 1000111111011100111100 89 | 1000111100011101001101 90 | 1000111001100001110101 91 | 1000110110101010110101 92 | 1000110011111000001111 93 | 1000110001001010000101 94 | 1000101110100000011001 95 | 1000101011111011001011 96 | 1000101001011010011111 97 | 1000100110111110010100 98 | 1000100100100110101110 99 | 1000100010010011101100 100 | 1000100000000101010010 101 | 1000011101111011011111 102 | 1000011011110110010110 103 | 1000011001110101110111 104 | 1000010111111010000100 105 | 1000010110000010111111 106 | 1000010100010000100111 107 | 1000010010100010111111 108 | 1000010000111010000111 109 | 1000001111010110000001 110 | 1000001101110110101101 111 | 1000001100011100001100 112 | 1000001011000110100000 113 | 1000001001110101101000 114 | 1000001000101001100110 115 | 1000000111100010011011 116 | 1000000110100000000111 117 | 1000000101100010101011 118 | 1000000100101010000111 119 | 1000000011110110011100 120 | 1000000011000111101010 121 | 1000000010011101110010 122 | 1000000001111000110101 123 | 1000000001011000110010 124 | 1000000000111101101011 125 | 1000000000100111011110 126 | 1000000000010110001101 127 | 1000000000001001111000 128 | 1000000000000010011110 129 | 1000000000000000000000 130 | 1000000000000010011110 131 | 1000000000001001111000 132 | 1000000000010110001101 133 | 1000000000100111011110 134 | 1000000000111101101011 135 | 1000000001011000110010 136 | 1000000001111000110101 137 | 1000000010011101110010 138 | 1000000011000111101010 139 | 1000000011110110011100 140 | 1000000100101010000111 141 | 1000000101100010101011 142 | 1000000110100000000111 143 | 1000000111100010011011 144 | 1000001000101001100110 145 | 1000001001110101101000 146 | 1000001011000110100000 147 | 1000001100011100001100 148 | 1000001101110110101101 149 | 1000001111010110000001 150 | 1000010000111010000111 151 | 1000010010100010111111 152 | 1000010100010000100111 153 | 1000010110000010111111 154 | 1000010111111010000100 155 | 1000011001110101110111 156 | 1000011011110110010110 157 | 1000011101111011011111 158 | 1000100000000101010010 159 | 1000100010010011101100 160 | 1000100100100110101110 161 | 1000100110111110010100 162 | 1000101001011010011111 163 | 1000101011111011001011 164 | 1000101110100000011001 165 | 1000110001001010000101 166 | 1000110011111000001111 167 | 1000110110101010110101 168 | 1000111001100001110101 169 | 1000111100011101001101 170 | 1000111111011100111100 171 | 1001000010100000111111 172 | 1001000101101001010110 173 | 1001001000110101111101 174 | 1001001100000110110011 175 | 1001001111011011110110 176 | 1001010010110101000011 177 | 1001010110010010011010 178 | 1001011001110011110111 179 | 1001011101011001011000 180 | 1001100001000010111100 181 | 1001100100110000100000 182 | 1001101000100010000001 183 | 1001101100010111011110 184 | 1001110000010000110011 185 | 1001110100001110000000 186 | 1001111000001111000000 187 | 1001111100010011110010 188 | 1010000000011100010011 189 | 1010000100101000100001 190 | 1010001000111000011001 191 | 1010001101001011111000 192 | 1010010001100010111100 193 | 1010010101111101100010 194 | 1010011010011011100111 195 | 1010011110111101001001 196 | 1010100011100010000100 197 | 1010101000001010010111 198 | 1010101100110101111101 199 | 1010110001100100110101 200 | 1010110110010110111011 201 | 1010111011001100001101 202 | 1011000000000100100111 203 | 1011000101000000000110 204 | 1011001001111110100111 205 | 1011001111000000001000 206 | 1011010100000100100101 207 | 1011011001001011111011 208 | 1011011110010110000110 209 | 1011100011100011000101 210 | 1011101000110010110011 211 | 1011101110000101001101 212 | 1011110011011010010000 213 | 1011111000110001111000 214 | 1011111110001100000011 215 | 1100000011101000101110 216 | 1100001001000111110011 217 | 1100001110101001010001 218 | 1100010100001101000100 219 | 1100011001110011001001 220 | 1100011111011011011011 221 | 1100100101000101111000 222 | 1100101010110010011100 223 | 1100110000100001000011 224 | 1100110110010001101011 225 | 1100111100000100001111 226 | 1101000001111000101011 227 | 1101000111101110111101 228 | 1101001101100111000001 229 | 1101010011100000110011 230 | 1101011001011100001111 231 | 1101011111011001010010 232 | 1101100101010111111000 233 | 1101101011010111111101 234 | 1101110001011001011110 235 | 1101110111011100010111 236 | 1101111101100000100100 237 | 1110000011100110000010 238 | 1110001001101100101100 239 | 1110001111110100011111 240 | 1110010101111101011000 241 | 1110011100000111010010 242 | 1110100010010010001010 243 | 1110101000011101111011 244 | 1110101110101010100010 245 | 1110110100110111111100 246 | 1110111011000110000100 247 | 1111000001010100110110 248 | 1111000111100100001111 249 | 1111001101110100001011 250 | 1111010100000100100110 251 | 1111011010010101011100 252 | 1111100000100110101001 253 | 1111100110111000001010 254 | 1111101101001001111010 255 | 1111110011011011110101 256 | 1111111001101101111001 257 | -------------------------------------------------------------------------------- /rom_r_init.txt: -------------------------------------------------------------------------------- 1 | 0111111111111111111111 2 | 0111111111111101100010 3 | 0111111111110110001000 4 | 0111111111101001110011 5 | 0111111111011000100010 6 | 0111111111000010010101 7 | 0111111110100111001110 8 | 0111111110000111001011 9 | 0111111101100010001110 10 | 0111111100111000010110 11 | 0111111100001001100100 12 | 0111111011010101111001 13 | 0111111010011101010101 14 | 0111111001011111111001 15 | 0111111000011101100101 16 | 0111110111010110011010 17 | 0111110110001010011000 18 | 0111110100111001100000 19 | 0111110011100011110100 20 | 0111110010001001010011 21 | 0111110000101001111111 22 | 0111101111000101111001 23 | 0111101101011101000001 24 | 0111101011101111011001 25 | 0111101001111101000001 26 | 0111101000000101111100 27 | 0111100110001010001001 28 | 0111100100001001101010 29 | 0111100010000100100001 30 | 0111011111111010101110 31 | 0111011101101100010100 32 | 0111011011011001010010 33 | 0111011001000001101100 34 | 0111010110100101100001 35 | 0111010100000100110101 36 | 0111010001011111100111 37 | 0111001110110101111011 38 | 0111001100000111110001 39 | 0111001001010101001011 40 | 0111000110011110001011 41 | 0111000011100010110011 42 | 0111000000100011000100 43 | 0110111101011111000001 44 | 0110111010010110101010 45 | 0110110111001010000011 46 | 0110110011111001001101 47 | 0110110000100100001010 48 | 0110101101001010111101 49 | 0110101001101101100110 50 | 0110100110001100001001 51 | 0110100010100110101000 52 | 0110011110111101000100 53 | 0110011011001111100000 54 | 0110010111011101111111 55 | 0110010011101000100010 56 | 0110001111101111001101 57 | 0110001011110010000000 58 | 0110000111110001000000 59 | 0110000011101100001110 60 | 0101111111100011101101 61 | 0101111011010111011111 62 | 0101110111000111100111 63 | 0101110010110100001000 64 | 0101101110011101000100 65 | 0101101010000010011110 66 | 0101100101100100011001 67 | 0101100001000010110111 68 | 0101011100011101111100 69 | 0101010111110101101001 70 | 0101010011001010000011 71 | 0101001110011011001011 72 | 0101001001101001000101 73 | 0101000100110011110011 74 | 0100111111111011011001 75 | 0100111010111111111010 76 | 0100110110000001011001 77 | 0100110000111111111000 78 | 0100101011111011011011 79 | 0100100110110100000101 80 | 0100100001101001111010 81 | 0100011100011100111011 82 | 0100010111001101001101 83 | 0100010001111010110011 84 | 0100001100100101110000 85 | 0100000111001110001000 86 | 0100000001110011111101 87 | 0011111100010111010010 88 | 0011110110111000001101 89 | 0011110001010110101111 90 | 0011101011110010111100 91 | 0011100110001100110111 92 | 0011100000100100100101 93 | 0011011010111010001000 94 | 0011010101001101100100 95 | 0011001111011110111101 96 | 0011001001101110010101 97 | 0011000011111011110001 98 | 0010111110000111010101 99 | 0010111000010001000011 100 | 0010110010011000111111 101 | 0010101100011111001101 102 | 0010100110100011110001 103 | 0010100000100110101110 104 | 0010011010101000001000 105 | 0010010100101000000011 106 | 0010001110100110100010 107 | 0010001000100011101001 108 | 0010000010011111011100 109 | 0001111100011001111110 110 | 0001110110010011010100 111 | 0001110000001011100001 112 | 0001101010000010101000 113 | 0001100011111000101110 114 | 0001011101101101110110 115 | 0001010111100010000101 116 | 0001010001010101011110 117 | 0001001011001000000100 118 | 0001000100111001111100 119 | 0000111110101011001010 120 | 0000111000011011110001 121 | 0000110010001011110101 122 | 0000101011111011011010 123 | 0000100101101010100100 124 | 0000011111011001010111 125 | 0000011001000111110110 126 | 0000010010110110000110 127 | 0000001100100100001011 128 | 0000000110010010000111 129 | 0000000000000000000000 130 | 1111111001101101111001 131 | 1111110011011011110101 132 | 1111101101001001111010 133 | 1111100110111000001010 134 | 1111100000100110101001 135 | 1111011010010101011100 136 | 1111010100000100100110 137 | 1111001101110100001011 138 | 1111000111100100001111 139 | 1111000001010100110110 140 | 1110111011000110000100 141 | 1110110100110111111100 142 | 1110101110101010100010 143 | 1110101000011101111011 144 | 1110100010010010001010 145 | 1110011100000111010010 146 | 1110010101111101011000 147 | 1110001111110100011111 148 | 1110001001101100101100 149 | 1110000011100110000010 150 | 1101111101100000100100 151 | 1101110111011100010111 152 | 1101110001011001011110 153 | 1101101011010111111101 154 | 1101100101010111111000 155 | 1101011111011001010010 156 | 1101011001011100001111 157 | 1101010011100000110011 158 | 1101001101100111000001 159 | 1101000111101110111101 160 | 1101000001111000101011 161 | 1100111100000100001111 162 | 1100110110010001101011 163 | 1100110000100001000011 164 | 1100101010110010011100 165 | 1100100101000101111000 166 | 1100011111011011011011 167 | 1100011001110011001001 168 | 1100010100001101000100 169 | 1100001110101001010001 170 | 1100001001000111110011 171 | 1100000011101000101110 172 | 1011111110001100000011 173 | 1011111000110001111000 174 | 1011110011011010010000 175 | 1011101110000101001101 176 | 1011101000110010110011 177 | 1011100011100011000101 178 | 1011011110010110000110 179 | 1011011001001011111011 180 | 1011010100000100100101 181 | 1011001111000000001000 182 | 1011001001111110100111 183 | 1011000101000000000110 184 | 1011000000000100100111 185 | 1010111011001100001101 186 | 1010110110010110111011 187 | 1010110001100100110101 188 | 1010101100110101111101 189 | 1010101000001010010111 190 | 1010100011100010000100 191 | 1010011110111101001001 192 | 1010011010011011100111 193 | 1010010101111101100010 194 | 1010010001100010111100 195 | 1010001101001011111000 196 | 1010001000111000011001 197 | 1010000100101000100001 198 | 1010000000011100010011 199 | 1001111100010011110010 200 | 1001111000001111000000 201 | 1001110100001110000000 202 | 1001110000010000110011 203 | 1001101100010111011110 204 | 1001101000100010000001 205 | 1001100100110000100000 206 | 1001100001000010111100 207 | 1001011101011001011000 208 | 1001011001110011110111 209 | 1001010110010010011010 210 | 1001010010110101000011 211 | 1001001111011011110110 212 | 1001001100000110110011 213 | 1001001000110101111101 214 | 1001000101101001010110 215 | 1001000010100000111111 216 | 1000111111011100111100 217 | 1000111100011101001101 218 | 1000111001100001110101 219 | 1000110110101010110101 220 | 1000110011111000001111 221 | 1000110001001010000101 222 | 1000101110100000011001 223 | 1000101011111011001011 224 | 1000101001011010011111 225 | 1000100110111110010100 226 | 1000100100100110101110 227 | 1000100010010011101100 228 | 1000100000000101010010 229 | 1000011101111011011111 230 | 1000011011110110010110 231 | 1000011001110101110111 232 | 1000010111111010000100 233 | 1000010110000010111111 234 | 1000010100010000100111 235 | 1000010010100010111111 236 | 1000010000111010000111 237 | 1000001111010110000001 238 | 1000001101110110101101 239 | 1000001100011100001100 240 | 1000001011000110100000 241 | 1000001001110101101000 242 | 1000001000101001100110 243 | 1000000111100010011011 244 | 1000000110100000000111 245 | 1000000101100010101011 246 | 1000000100101010000111 247 | 1000000011110110011100 248 | 1000000011000111101010 249 | 1000000010011101110010 250 | 1000000001111000110101 251 | 1000000001011000110010 252 | 1000000000111101101011 253 | 1000000000100111011110 254 | 1000000000010110001101 255 | 1000000000001001111000 256 | 1000000000000010011110 257 | --------------------------------------------------------------------------------