├── script ├── resize_sd.sh └── activate_wifi.sh ├── wifi_firmware ├── BCM43430A1.hcd ├── brcmfmac43430-sdio.bin ├── cyfmac43430-sdio.bin ├── brcmfmac43430-sdio.clm_blob ├── cyfmac43430-sdio.1DX.clm_blob └── brcmfmac43430-sdio.txt ├── system.sh.sample ├── 00003-remove-plus-from-kernel-version.patch ├── .gitmodules ├── version.sh ├── .gitignore ├── ch-mount.sh ├── error.sh ├── LICENSE ├── 00002-add-panel-simle-o4_lcd5_800_480.patch ├── .github └── workflows │ ├── manual-build-stm32mp157c-DK2.yml │ ├── manual-build-stm32mp157a-sodimm2.yml │ └── build-all-board.yml ├── rootfs.sh ├── gcc.sh ├── create-rootfs.sh ├── README.md ├── 00005-add-at-f-stm32mp157a-sodimm2-mx.patch ├── 00001-add-stm32mp157a-sodimm2-mx.patch └── 00004-add-u-boot-stm32mp157a-sodimm2-mx.patch /script/resize_sd.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | sudo growpart /dev/mmcblk0 4 4 | sudo resize2fs /dev/mmcblk0p4 5 | df -h 6 | -------------------------------------------------------------------------------- /wifi_firmware/BCM43430A1.hcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cvetaevvitaliy/stm32mp1-ubuntu/HEAD/wifi_firmware/BCM43430A1.hcd -------------------------------------------------------------------------------- /wifi_firmware/brcmfmac43430-sdio.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cvetaevvitaliy/stm32mp1-ubuntu/HEAD/wifi_firmware/brcmfmac43430-sdio.bin -------------------------------------------------------------------------------- /wifi_firmware/cyfmac43430-sdio.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cvetaevvitaliy/stm32mp1-ubuntu/HEAD/wifi_firmware/cyfmac43430-sdio.bin -------------------------------------------------------------------------------- /wifi_firmware/brcmfmac43430-sdio.clm_blob: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cvetaevvitaliy/stm32mp1-ubuntu/HEAD/wifi_firmware/brcmfmac43430-sdio.clm_blob -------------------------------------------------------------------------------- /wifi_firmware/cyfmac43430-sdio.1DX.clm_blob: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/cvetaevvitaliy/stm32mp1-ubuntu/HEAD/wifi_firmware/cyfmac43430-sdio.1DX.clm_blob -------------------------------------------------------------------------------- /script/activate_wifi.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | sudo apt update 4 | sudo apt install rfkill -y 5 | sudo rfkill list all 6 | sudo rfkill unblock all 7 | sudo ifconfig wlan0 up 8 | ifconfig 9 | -------------------------------------------------------------------------------- /system.sh.sample: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | #copy as "system.sh" and tweak for your system 3 | 4 | ARCH=$(uname -m) 5 | 6 | #ARM Native gcc compiler (running gcc on arm target) 7 | if [ "x${ARCH}" = "xarmv7l" ] ; then 8 | #Native arm gcc compiler 9 | CC= 10 | fi 11 | -------------------------------------------------------------------------------- /00003-remove-plus-from-kernel-version.patch: -------------------------------------------------------------------------------- 1 | diff --git a/scripts/setlocalversion b/scripts/setlocalversion 2 | index bb709eda96cd..3caced3bddf8 100755 3 | --- a/scripts/setlocalversion 4 | +++ b/scripts/setlocalversion 5 | @@ -33,6 +33,7 @@ scm_version() 6 | { 7 | local short 8 | short=false 9 | + return 10 | 11 | cd "$srctree" 12 | if test -e .scmversion; then 13 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "u-boot"] 2 | path = u-boot 3 | url = https://github.com/STMicroelectronics/u-boot 4 | branch = v2020.10-stm32mp 5 | 6 | [submodule "linux"] 7 | path = linux 8 | url = https://github.com/STMicroelectronics/linux 9 | branch = v5.10-stm32mp 10 | 11 | [submodule "arm-trusted-firmware"] 12 | path = arm-trusted-firmware 13 | url = https://github.com/STMicroelectronics/arm-trusted-firmware 14 | branch = v2.4-stm32mp 15 | 16 | [submodule "gcnano-binaries"] 17 | path = gcnano-binaries 18 | url = https://github.com/STMicroelectronics/gcnano-binaries 19 | branch = gcnano-6.4.3-binaries 20 | 21 | -------------------------------------------------------------------------------- /version.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # 3 | ARCH=$(uname -m) 4 | 5 | #board ?= "stm32mp157a-sodimm2-mx" 6 | #board="stm32mp157c-dk2" 7 | 8 | config="multi_v7_defconfig" 9 | 10 | # base rootfs 11 | link_ubuntu_relese="https://cdimage.ubuntu.com/ubuntu-base/releases/22.04/release" 12 | base_rootfs_name="ubuntu-base-22.04-base-armhf.tar.gz" 13 | 14 | # Googledrive link to rootfs 15 | fileid="1kEco22WrjYhaFoAfxaGbd41blzu6kYSC" 16 | rootfs_name="ubuntu-22.04-base-stm32mp1-armhf-16-05-2022.tar.gz" 17 | 18 | 19 | #arm 20 | KERNEL_ARCH=arm 21 | DEBARCH=armhf 22 | #toolchain="gcc_6_arm" 23 | #toolchain="gcc_7_arm" 24 | #toolchain="gcc_8_arm" 25 | #toolchain="gcc_9_arm" 26 | toolchain="gcc_10_arm" 27 | #toolchain="gcc_11_arm" 28 | 29 | # 30 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | download_dir/ 54 | toolchain/ 55 | output/ 56 | ubuntu-20.04.3/ 57 | ubuntu*/ 58 | 59 | debian_10_rootfs/ 60 | debian_11_rootfs/ 61 | debian_rootfs/ 62 | -------------------------------------------------------------------------------- /ch-mount.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | function mnt() { 3 | echo "MOUNTING" 4 | sudo mount -t proc /proc ${2}/proc 5 | sudo mount -t sysfs /sys ${2}/sys 6 | sudo mount -o bind /dev ${2}/dev 7 | sudo chroot ${2} 8 | 9 | } 10 | function umnt() { 11 | echo "UNMOUNTING" 12 | sudo umount ${2}/proc 13 | sudo umount ${2}/sys 14 | sudo umount ${2}/dev 15 | } 16 | if [ "$1" == "-m" ] && [ -n "$2" ]; 17 | then 18 | mnt $1 $2 19 | elif [ "$1" == "-u" ] && [ -n "$2" ]; 20 | then 21 | umnt $1 $2 22 | else 23 | echo "" 24 | echo "Either 1'st, 2'nd or both parameters were missing" 25 | echo "" 26 | echo "1'st parameter can be one of these: -m(mount) OR -u(umount)" 27 | echo "2'nd parameter is the full path of rootfs directory(with trailing '/')" 28 | echo "" 29 | echo "For example: ch-mount -m /media/sdcard/" 30 | echo "" 31 | echo 1st parameter : ${1} 32 | echo 2nd parameter : ${2} 33 | fi -------------------------------------------------------------------------------- /error.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh -e 2 | 3 | DIR=$PWD 4 | 5 | echo "\n\n\n" 6 | 7 | echo "-----------------------------" 8 | echo "Script Error: please cut and paste the following into to GitHub issue " 9 | echo "**********************************************************" 10 | echo "Error: [${ERROR_MSG}]" 11 | 12 | if [ -f "${DIR}/.git/config" ] ; then 13 | gitrepo=$(cat "${DIR}/.git/config" | grep url | awk '{print $3}') 14 | gitwhatchanged=$(git whatchanged -1) 15 | echo "git repo: [${gitrepo}]" 16 | echo "-----------------------------" 17 | echo "${gitwhatchanged}" 18 | echo "-----------------------------" 19 | else 20 | if [ "${BRANCH}" ] ; then 21 | echo "nongit: [${BRANCH}]" 22 | else 23 | echo "nongit: [master]" 24 | fi 25 | fi 26 | 27 | 28 | echo "uname -m" 29 | uname -m 30 | if [ "$(which lsb_release)" ] ; then 31 | echo "lsb_release -a" 32 | lsb_release -a 33 | fi 34 | echo "**********************************************************" 35 | 36 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Vitaliy 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /wifi_firmware/brcmfmac43430-sdio.txt: -------------------------------------------------------------------------------- 1 | # NVRAM file for BCM943430WLSELG 2 | # 2.4 GHz, 20 MHz BW mode 3 | 4 | # The following parameter values are just placeholders, need to be updated. 5 | manfid=0x2d0 6 | prodid=0x0726 7 | vendid=0x14e4 8 | devid=0x43e2 9 | boardtype=0x0726 10 | boardrev=0x1202 11 | boardnum=22 12 | macaddr=00:90:4c:c5:12:38 13 | sromrev=11 14 | boardflags=0x00404201 15 | boardflags3=0x08000000 16 | xtalfreq=37400 17 | #xtalfreq=19200 18 | nocrc=1 19 | ag0=255 20 | aa2g=1 21 | ccode=ALL 22 | 23 | pa0itssit=0x20 24 | extpagain2g=0 25 | 26 | #PA parameters for 2.4GHz, measured at CHIP OUTPUT 27 | pa2ga0=-168,7161,-820 28 | AvVmid_c0=0x0,0xc8 29 | cckpwroffset0=5 30 | 31 | # PPR params 32 | maxp2ga0=84 33 | txpwrbckof=6 34 | cckbw202gpo=0 35 | legofdmbw202gpo=0x66111111 36 | mcsbw202gpo=0x77711111 37 | propbw202gpo=0xdd 38 | 39 | # OFDM IIR : 40 | ofdmdigfilttype=18 41 | ofdmdigfilttypebe=18 42 | # PAPD mode: 43 | papdmode=1 44 | papdvalidtest=1 45 | pacalidx2g=32 46 | papdepsoffset=-36 47 | papdendidx=61 48 | 49 | il0macaddr=00:90:4c:c5:12:38 50 | wl0id=0x431b 51 | 52 | deadman_to=0xffffffff 53 | # muxenab: 0x1 for UART enable, 0x2 for GPIOs, 0x8 for JTAG 54 | muxenab=0x1 55 | # CLDO PWM voltage settings - 0x4 - 1.1 volt 56 | #cldo_pwm=0x4 57 | 58 | #VCO freq 326.4MHz 59 | spurconfig=0x3 60 | -------------------------------------------------------------------------------- /00002-add-panel-simle-o4_lcd5_800_480.patch: -------------------------------------------------------------------------------- 1 | diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c 2 | index 204674fccd64..afad51b712b9 100644 3 | --- a/drivers/gpu/drm/panel/panel-simple.c 4 | +++ b/drivers/gpu/drm/panel/panel-simple.c 5 | @@ -3900,6 +3900,29 @@ static const struct panel_desc arm_rtsm = { 6 | .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 7 | }; 8 | 9 | +static const struct drm_display_mode o4_lcd5_800_480_mode = { 10 | + .clock = 29700, 11 | + .hdisplay = 800, 12 | + .hsync_start = 800 + 15, 13 | + .hsync_end = 800 + 15 + 10, 14 | + .htotal = 800 + 15 + 10 + 14, 15 | + .vdisplay = 480, 16 | + .vsync_start = 480 + 98, 17 | + .vsync_end = 480 + 98 + 32, 18 | + .vtotal = 480 + 98 + 32 + 98, 19 | + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 20 | +}; 21 | + 22 | +static const struct panel_desc o4_lcd5_800_480 = { 23 | + .modes = &o4_lcd5_800_480_mode, 24 | + .num_modes = 1, 25 | + .bpc = 6, 26 | + .size = { 27 | + .width = 100, 28 | + .height = 68, 29 | + }, 30 | +}; 31 | + 32 | static const struct of_device_id platform_of_match[] = { 33 | { 34 | .compatible = "ampire,am-1280800n3tzqw-t00h", 35 | @@ -4300,6 +4323,9 @@ static const struct of_device_id platform_of_match[] = { 36 | }, { 37 | .compatible = "winstar,wf35ltiacd", 38 | .data = &winstar_wf35ltiacd, 39 | + }, { 40 | + .compatible = "out4,o4-lcd5-800-480", 41 | + .data = &o4_lcd5_800_480, 42 | }, { 43 | /* Must be the last entry */ 44 | .compatible = "panel-dpi", 45 | -------------------------------------------------------------------------------- /.github/workflows/manual-build-stm32mp157c-DK2.yml: -------------------------------------------------------------------------------- 1 | on: workflow_dispatch 2 | jobs: 3 | build: 4 | runs-on: ubuntu-latest 5 | steps: 6 | - uses: actions/checkout@v2 7 | with: 8 | path: stm32mp1-ubuntu 9 | 10 | 11 | - name: Install depends 12 | run: sudo apt-get install -y zip lzop lzma gettext libmpc-dev u-boot-tools libncurses5-dev pv gzip flex bison ncurses-base build-essential qemu-user-static device-tree-compiler 13 | 14 | - name: Get submodules 15 | working-directory: ./stm32mp1-ubuntu 16 | run: | 17 | git submodule update --init --recursive 18 | git submodule update --recursive --remote 19 | 20 | - name: Build U-boot and ARM trusted firmware 21 | working-directory: ./stm32mp1-ubuntu 22 | run: bash build-uboot.sh 23 | 24 | - name: Build kernel 25 | working-directory: ./stm32mp1-ubuntu 26 | run: bash build-linux.sh 27 | 28 | - name: Get rootfs 29 | working-directory: ./stm32mp1-ubuntu 30 | run: bash rootfs.sh 31 | 32 | - name: Make rootfs 33 | working-directory: ./stm32mp1-ubuntu 34 | run: bash create-rootfs.sh 35 | 36 | - name: ZIP artifact 37 | run: | 38 | mv -v ${{runner.workspace}}/stm32mp1-ubuntu/stm32mp1-ubuntu/artifacts/*.img ./ 39 | zip ubuntu-22.04-stm32mp157c-DK2.zip ./*.img 40 | 41 | - name: Upload artifacts 42 | uses: actions/upload-artifact@v2 43 | with: 44 | name: ubuntu-22.04-stm32mp157c-DK2 45 | path: ubuntu-22.04-stm32mp157c-DK2.zip 46 | -------------------------------------------------------------------------------- /.github/workflows/manual-build-stm32mp157a-sodimm2.yml: -------------------------------------------------------------------------------- 1 | on: workflow_dispatch 2 | jobs: 3 | build: 4 | runs-on: ubuntu-latest 5 | steps: 6 | - uses: actions/checkout@v2 7 | with: 8 | path: stm32mp1-ubuntu 9 | 10 | 11 | - name: Install depends 12 | run: sudo apt-get install -y zip lzop lzma gettext libmpc-dev u-boot-tools libncurses5-dev pv gzip flex bison ncurses-base build-essential qemu-user-static device-tree-compiler 13 | 14 | - name: Get submodules 15 | working-directory: ./stm32mp1-ubuntu 16 | run: | 17 | git submodule update --init --recursive 18 | git submodule update --recursive --remote 19 | 20 | - name: Build U-boot and ARM trusted firmware 21 | working-directory: ./stm32mp1-ubuntu 22 | run: bash build-uboot.sh stm32mp157a-sodimm2-mx 23 | 24 | - name: Build kernel 25 | working-directory: ./stm32mp1-ubuntu 26 | run: bash build-linux.sh 27 | 28 | - name: Get rootfs 29 | working-directory: ./stm32mp1-ubuntu 30 | run: bash rootfs.sh 31 | 32 | - name: Make rootfs 33 | working-directory: ./stm32mp1-ubuntu 34 | run: bash create-rootfs.sh stm32mp157a-sodimm2-mx 35 | 36 | - name: ZIP artifact 37 | run: | 38 | mv -v ${{runner.workspace}}/stm32mp1-ubuntu/stm32mp1-ubuntu/artifacts/*.img ./ 39 | zip ubuntu-22.04-stm32mp157a-sodimm2.zip ./*.img 40 | 41 | - name: Upload artifacts 42 | uses: actions/upload-artifact@v2 43 | with: 44 | name: ubuntu-22.04-stm32mp157a-sodimm2 45 | path: ubuntu-22.04-stm32mp157a-sodimm2.zip 46 | -------------------------------------------------------------------------------- /.github/workflows/build-all-board.yml: -------------------------------------------------------------------------------- 1 | on: workflow_dispatch 2 | jobs: 3 | build: 4 | runs-on: ubuntu-latest 5 | strategy: 6 | fail-fast: false 7 | # max-parallel: 4 8 | matrix: 9 | board: [ stm32mp157a-sodimm2-mx, stm32mp157a-avenger96, stm32mp157a-dk1, stm32mp157a-ed1, stm32mp157a-ev1, stm32mp157c-dk2, stm32mp157c-ed1, stm32mp157c-ev1, stm32mp157d-dk1, stm32mp157d-ed1, stm32mp157f-dk2, stm32mp157f-ed1, stm32mp157f-ev1 ] 10 | 11 | steps: 12 | - uses: actions/checkout@v2 13 | with: 14 | path: stm32mp1-ubuntu 15 | 16 | - name: Install depends 17 | run: sudo apt-get install -y zip lzop lzma gettext libmpc-dev u-boot-tools libncurses5-dev pv gzip flex bison ncurses-base build-essential device-tree-compiler 18 | 19 | - name: Submodules init 20 | working-directory: ./stm32mp1-ubuntu 21 | run: git submodule init 22 | 23 | - name: Get U-boot & AT-F 24 | working-directory: ./stm32mp1-ubuntu 25 | run: | 26 | git submodule update --recursive --remote u-boot 27 | git submodule update --recursive --remote arm-trusted-firmware 28 | 29 | - name: Build U-boot and ARM trusted firmware 30 | working-directory: ./stm32mp1-ubuntu 31 | run: bash build-uboot.sh ${{ matrix.board }} 32 | 33 | - name: Get kernel 34 | working-directory: ./stm32mp1-ubuntu 35 | run: git submodule update --recursive --remote linux 36 | 37 | - name: Build kernel 38 | env: 39 | HOSTNAME: Runner 40 | USER: GitHub 41 | working-directory: ./stm32mp1-ubuntu 42 | run: bash build-linux.sh 43 | 44 | - name: Get rootfs 45 | working-directory: ./stm32mp1-ubuntu 46 | run: bash rootfs.sh 47 | 48 | - name: Make rootfs 49 | working-directory: ./stm32mp1-ubuntu 50 | run: bash create-rootfs.sh ${{ matrix.board }} 51 | 52 | - name: ZIP artifact 53 | run: | 54 | mkdir -p ./upload 55 | mv -v ${{runner.workspace}}/stm32mp1-ubuntu/stm32mp1-ubuntu/artifacts/*${{ matrix.conboardfig }}*.img ./upload/ubuntu-22.04-${{ matrix.board }}.img 56 | echo "login: ubuntu" > ./upload/login-pass.txt 57 | echo "password: root" >> ./upload/login-pass.txt 58 | 59 | - name: Upload artifacts 60 | uses: actions/upload-artifact@v4 61 | with: 62 | name: ubuntu-22.04-${{ matrix.board }} (this is unzipped size) 63 | path: ./upload 64 | -------------------------------------------------------------------------------- /rootfs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | DIR=$PWD 4 | . "${DIR}/version.sh" 5 | 6 | # Create the download directory if it doesn't exist 7 | if [ ! -d "${DIR}/dl" ] ; then 8 | mkdir -p "${DIR}/dl" 9 | fi 10 | 11 | # Ensure ${DIR}/dl exists after attempt to create 12 | if [ ! -d "${DIR}/dl" ] ; then 13 | echo "Failed to create download directory: ${DIR}/dl" 14 | exit 1 15 | fi 16 | 17 | # Download the base_rootfs_name file if it doesn't exist 18 | if [ -f "${DIR}/dl/${base_rootfs_name}" ] ; then 19 | echo "File downloaded: ${DIR}/dl/${base_rootfs_name}" 20 | else 21 | wget -P "${DIR}/dl" "${link_ubuntu_relese}/${base_rootfs_name}" || { exit 1 ; } 22 | fi 23 | 24 | # Google Drive file details 25 | fileid="1kEco22WrjYhaFoAfxaGbd41blzu6kYSC" 26 | rootfs_name="ubuntu-22.04-base-stm32mp1-armhf-16-05-2022.tar.gz" 27 | BASE_URL="https://drive.google.com/uc?export=download" 28 | 29 | cd "${DIR}/dl" 30 | if [ -f "${DIR}/dl/${rootfs_name}" ] ; then 31 | echo "File downloaded: ${DIR}/dl/${rootfs_name}" 32 | else 33 | # Step 1: Fetch the download page and save cookies 34 | echo "Fetching initial download page..." 35 | wget --quiet --save-cookies cookies.txt --keep-session-cookies --no-check-certificate \ 36 | "${BASE_URL}&id=${fileid}" -O temp.html 37 | 38 | # Step 2: Extract the necessary IDs from the HTML response 39 | CONFIRM=$(grep -oP '&1 | grep "Target:" | grep ${check} || true) 185 | fi 186 | 187 | if [ "x${GCC_TEST}" = "x" ] ; then 188 | echo "-----------------------------" 189 | echo "scripts/gcc: Error: The GCC Cross Compiler you setup in system.sh (CC variable) is invalid." 190 | echo "-----------------------------" 191 | gcc_toolchain 192 | fi 193 | 194 | echo "-----------------------------" 195 | echo "scripts/gcc: Using: $(LC_ALL=C "${CC}"gcc --version)" 196 | echo "-----------------------------" 197 | echo "CC=${CC}" > "${DIR}/.CC" 198 | -------------------------------------------------------------------------------- /create-rootfs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | 4 | export LC_ALL=C 5 | DIR=$PWD 6 | 7 | . "${DIR}/version.sh" 8 | 9 | IMAGE_FILENAME="sdcard-stm32mp157.img" 10 | MOUNT_PATH="${DIR}/deploy/rootfs_tmp" 11 | 12 | 13 | init_image(){ 14 | 15 | if ! [ -f ${DIR}/deploy/${IMAGE_FILENAME} ]; then 16 | echo "Create ${IMAGE_FILENAME}" 17 | dd if=/dev/zero of=${DIR}/deploy/${IMAGE_FILENAME} bs=4096M count=2 || { exit 1 ; } 18 | 19 | echo "Create file systems ${IMAGE_FILENAME}" 20 | sgdisk --resize-table=128 -a 1 \ 21 | -n 1:34:545 -c 1:fsbl1 \ 22 | -n 2:546:1057 -c 2:fsbl2 \ 23 | -n 3:1058:5153 -c 3:fip \ 24 | -n 4:5154: -c 4:rootfs \ 25 | -p ${DIR}/deploy/${IMAGE_FILENAME} 26 | 27 | echo "" 28 | echo "Set legacy BIOS partition:" 29 | sgdisk -A 4:set:2 ${DIR}/deploy/${IMAGE_FILENAME} || { exit 1 ; } 30 | 31 | else 32 | echo "Found image ${IMAGE_FILENAME}" 33 | echo "" 34 | fi 35 | 36 | if ! [ -f ${DIR}/deploy/${IMAGE_FILENAME} ]; then 37 | echo "Error create ${IMAGE_FILENAME}" 38 | echo "" 39 | exit 1 ; 40 | fi 41 | 42 | } 43 | 44 | create_loop() { 45 | 46 | echo "Create loop device, need root access for use losetup" 47 | LOOP_DEVICE=$(sudo losetup --partscan --show --find ./deploy/${IMAGE_FILENAME}) 48 | echo "Create loop device '${LOOP_DEVICE}'" 49 | 50 | echo "Print info about loop" 51 | ls -l ${LOOP_DEVICE}* 52 | echo "" 53 | 54 | } 55 | 56 | clean_loop() { 57 | 58 | echo "Try umount folder: '${MOUNT_PATH}'" 59 | sudo umount ${MOUNT_PATH} 60 | case "$?" in 61 | 0) echo "umount '${MOUNT_PATH}' OK" ;; 62 | *) echo "Error mmount folder '${MOUNT_PATH}'" ;; 63 | esac 64 | 65 | echo "Clean up loop: '${LOOP_DEVICE}' " 66 | sudo losetup -D 67 | case "$?" in 68 | 0) echo "Clean loop '${LOOP_DEVICE}' device OK" ;; 69 | *) echo "Error clean '${LOOP_DEVICE}' device " ;; 70 | esac 71 | echo "Finish" 72 | } 73 | 74 | write_uboot() { 75 | echo "============================================" 76 | echo "Install U-Boot bootloader version ${UBOOT_VERSION}:" 77 | if [ -f ${DIR}/deploy/fip.bin ]; then 78 | #if [ -f ${DIR}/deploy/u-boot.img ]; then 79 | # sudo dd if=${DIR}/deploy/u-boot-spl.stm32 of=${LOOP_DEVICE}0p1 80 | # sudo dd if=${DIR}/deploy/u-boot-spl.stm32 of=${LOOP_DEVICE}p2 81 | # sudo dd if=${DIR}/deploy/u-boot.img of=${LOOP_DEVICE}p3 82 | sudo dd if=${DIR}/deploy/tf-a-${board}.stm32 of=${LOOP_DEVICE}p1 83 | sudo dd if=${DIR}/deploy/tf-a-${board}.stm32 of=${LOOP_DEVICE}p2 84 | sudo dd if=${DIR}/deploy/fip.bin of=${LOOP_DEVICE}p3 85 | else 86 | echo "Error, Uboot not found" 87 | clean_loop 88 | exit 1 89 | fi 90 | 91 | } 92 | 93 | write_rootfs(){ 94 | 95 | echo "Format RootFS Partition:" 96 | echo "" 97 | sudo mkfs.ext4 -L rootfs ${LOOP_DEVICE}p4 98 | 99 | echo "Mount rootfs file system to ${MOUNT_PATH}" 100 | echo "" 101 | sudo mkdir -p ${MOUNT_PATH} 102 | sudo mount ${LOOP_DEVICE}p4 ${MOUNT_PATH} 103 | 104 | if [ -d ${DIR}/deploy ]; then 105 | kernel_ver=$(cat "${DIR}/linux/include/generated/utsrelease.h" | awk '{print $3}' | sed 's/\"//g' ) 106 | echo "Kernel version ${kernel_ver}" 107 | else 108 | echo "First need build Kernel, please make './build.sh kernel'" 109 | clean_loop 110 | exit 1 111 | fi 112 | 113 | 114 | 115 | echo "" 116 | echo "Extract and copy Root File System: ${DIR}/dl/${rootfs_name}" 117 | if [ -f "${DIR}/dl/${rootfs_name}" ]; then 118 | # ubuntu-base-22.04-base-armhf.tar.gz 119 | # sudo tar xvfp ./deploy/${UBUNTU_18_VERSION}/*/*.tar -C ${MOUNT_PATH} 120 | # sudo tar xvfp ${DIR}/ubuntu-base-22.04-base-armhf.tar.gz -C ${MOUNT_PATH} 121 | #sudo tar xzpf ${DIR}/deploy/rootfs.tar.gz -C ${MOUNT_PATH} 122 | sudo tar xzpf ${DIR}/dl/${rootfs_name} -C ${MOUNT_PATH} || { clean_loop ; exit 1 ; } 123 | #sudo cp -ar ${DIR}/deploy/rootfs/. ${MOUNT_PATH} 124 | #sudo rsync -azvh ${DIR}/rootfs/. ${MOUNT_PATH} 125 | # sudo tar xfp ${DIR}/dl/${rootfs_name} -C ${MOUNT_PATH} 126 | else 127 | echo "First need get rootfs" 128 | clean_loop 129 | exit 1 130 | fi 131 | 132 | } 133 | 134 | copy_kernel_and_modules(){ 135 | #fbcon=rotate:3 136 | unset boot_instance 137 | 138 | echo "" 139 | echo "Setup extlinux.conf" 140 | sudo mkdir -p ${MOUNT_PATH}/boot/extlinux/ 141 | sudo sh -c "echo 'label Linux ${kernel_ver}' > ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 142 | sudo sh -c "echo ' kernel /boot/vmlinuz-${kernel_ver}' >> ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 143 | sudo sh -c "echo ' append console=ttySTM0,115200 console=tty1,115200 root=/dev/mmcblk\${boot_instance}p4 ro rootwait ' >> ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 144 | sudo sh -c "echo ' fdtdir /boot/dtbs/${kernel_ver}/' >> ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 145 | 146 | 147 | echo "" 148 | echo "Copy Kernel Image" 149 | sudo cp -v ./deploy/${kernel_ver}.zImage ${MOUNT_PATH}/boot/vmlinuz-${kernel_ver} 150 | 151 | echo "" 152 | echo "Copy Kernel Device Tree Binaries" 153 | sudo mkdir -p ${MOUNT_PATH}/boot/dtbs/${kernel_ver}/ 154 | sudo tar xfv ./deploy/${kernel_ver}-dtbs.tar.gz -C ${MOUNT_PATH}/boot/dtbs/${kernel_ver}/ 155 | 156 | echo "" 157 | echo "Copy Kernel Modules" 158 | sudo tar xf ./deploy/${kernel_ver}-modules.tar.gz -C ${MOUNT_PATH}/usr/ 159 | 160 | # echo "" 161 | # echo "Copy GPU video driver" # sudo depmod -a 162 | # echo "first start, need rescan all modules: 'sudo depmod -a'" 163 | # sudo mkdir -p ${MOUNT_PATH}/lib/modules/${kernel_ver}/extra/ 164 | # sudo cp -v ${DIR}/gcnano-driver-6.4.3/galcore.ko ${MOUNT_PATH}/lib/modules/${kernel_ver}/extra/ 165 | 166 | sudo sh -c "echo 'allow-hotplug eth0' >> ${MOUNT_PATH}/etc/network/interfaces" 167 | sudo sh -c "echo 'iface eth0 inet dhcp' >> ${MOUNT_PATH}/etc/network/interfaces" 168 | 169 | echo "" 170 | echo "Copy WiFi firmware" 171 | sudo mkdir -p ${MOUNT_PATH}/lib/firmware/brcm/ 172 | sudo cp -v ./wifi_firmware/* ${MOUNT_PATH}/lib/firmware/brcm/ 173 | sudo cp -v ./wifi_firmware/brcmfmac43430-sdio.txt ${MOUNT_PATH}/lib/firmware/brcm/brcmfmac43430-sdio.st,${board}.txt 174 | 175 | 176 | # add wellcome information 177 | sudo sh -c "echo 'Ubuntu 22.04 LTS \\l' > ${MOUNT_PATH}/etc/issue" 178 | sudo sh -c "echo 'Build: $(date +'%d/%m/%Y')' >> ${MOUNT_PATH}/etc/issue" 179 | sudo sh -c "echo ' ' >> ${MOUNT_PATH}/etc/issue" 180 | sudo sh -c "echo 'login: ubuntu' >> ${MOUNT_PATH}/etc/issue" 181 | sudo sh -c "echo 'passw: root' >> ${MOUNT_PATH}/etc/issue" 182 | sudo sh -c "echo ' ' >> ${MOUNT_PATH}/etc/issue" 183 | # activate welcome message 184 | # sudo chmod +x ${MOUNT_PATH}/etc/update-motd.d/00-header 185 | # sudo chmod +x ${MOUNT_PATH}/etc/update-motd.d/10-help-text 186 | # sudo chmod +x ${MOUNT_PATH}/etc/update-motd.d/50-motd-news 187 | # sudo chmod +x ${MOUNT_PATH}/etc/update-motd.d/80-esm 188 | # sudo chmod +x ${MOUNT_PATH}/etc/update-motd.d/80-livepatch 189 | 190 | echo "" 191 | echo "Copy helper scripts" 192 | sudo cp -v ./script/resize_sd.sh ${MOUNT_PATH}/usr/bin/ 193 | sudo cp -v ./script/activate_wifi.sh ${MOUNT_PATH}/usr/bin/ 194 | 195 | echo "" 196 | echo "File Systems Table (/etc/fstab)" 197 | sudo sh -c "echo '/dev/mmcblk0p4 / auto errors=remount-ro 0 1' >> ${MOUNT_PATH}/etc/fstab" 198 | 199 | ls -l ${MOUNT_PATH}/ 200 | ls -l ${MOUNT_PATH}/home/ 201 | 202 | sync 203 | case "$?" in 204 | 0) echo "Sync OK" ;; 205 | *) echo "Error sync " ;; 206 | esac 207 | 208 | mkdir -p ${DIR}/artifacts 209 | 210 | if [ -f "${DIR}/artifacts/$(date +'%d-%m-%Y')-Ubuntu-22.04-base-${board}.img" ]; then 211 | rm ${DIR}/artifacts/$(date +'%d-%m-%Y')-Ubuntu-22.04-base-${board}.img 212 | fi 213 | 214 | mv -v ${DIR}/deploy/${IMAGE_FILENAME} ${DIR}/artifacts/$(date +'%d-%m-%Y')-Ubuntu-22.04-base-${board}.img 215 | 216 | } 217 | 218 | OPTIONS="${@:-allff}" 219 | 220 | for option in ${OPTIONS}; do 221 | # echo "processing option: $option" 222 | case $option in 223 | stm32mp157a-sodimm2-mx) board=${OPTIONS} ;; 224 | stm32mp157c-dk2) board=${OPTIONS} ;; 225 | stm32mp157a-avenger96) board=${OPTIONS} ;; 226 | stm32mp157a-ev1) board=${OPTIONS} ;; 227 | stm32mp157a-iot-box) board=${OPTIONS} ;; 228 | stm32mp157a-stinger96) board=${OPTIONS} ;; 229 | stm32mp157c-dhcom-pdk2) board=${OPTIONS} ;; 230 | stm32mp157c-ed1) board=${OPTIONS} ;; 231 | stm32mp157c-ev1) board=${OPTIONS} ;; 232 | stm32mp157c-lxa-mc1) board=${OPTIONS} ;; 233 | stm32mp157c-odyssey) board=${OPTIONS} ;; 234 | stm32mp157d-dk1) board=${OPTIONS} ;; 235 | stm32mp157d-ed1) board=${OPTIONS} ;; 236 | stm32mp157d-ev1) board=${OPTIONS} ;; 237 | stm32mp157f-dk2) board=${OPTIONS} ;; 238 | stm32mp157f-ed1) board=${OPTIONS} ;; 239 | stm32mp157f-ev1) board=${OPTIONS} ;; 240 | stm32mp157a-dk1) board=${OPTIONS} ;; 241 | stm32mp157a-ed1) board=${OPTIONS} ;; 242 | 243 | *) board="stm32mp157c-dk2" ;; 244 | esac 245 | done 246 | 247 | 248 | 249 | init_image 250 | 251 | create_loop 252 | 253 | write_uboot 254 | 255 | write_rootfs 256 | 257 | copy_kernel_and_modules 258 | 259 | clean_loop 260 | 261 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Ubuntu 18.04, 20.04, 22.04 Debian 10, 11 for stm32mp1 2 | This repo for build Ubuntu/Debian on stm32mp1xx CPU
3 | Availability 4 | Boards: 5 | 6 | * [EV-STM32MP157-SODIMM](http://otladka.com.ua/index.php?option=com_virtuemart&page=shop.product_details&flypage=vmj_naru.tpl&category_id=41&product_id=284&Itemid=71) 7 | * [Discovery kit with STM32MP157D MPU 88 at Digi-Key](https://www.digikey.com/en/products/detail/stmicroelectronics/STM32MP157D-DK1/13536964) 8 | * [Discovery kit with STM32MP157F MPU 47 at Digi-Key](https://www.digikey.com/en/products/detail/stmicroelectronics/STM32MP157F-DK2/13536968) 9 | * [Evaluation board with STM32MP157D MPU 43 at Digi-Key](https://www.digikey.com/en/products/detail/stmicroelectronics/STM32MP157D-EV1/13536967) 10 | * [Evaluation board with STM32MP157F MPU 32 at Digi-Key](https://www.digikey.com/en/products/detail/stmicroelectronics/STM32MP157F-EV1/12395904) 11 | 12 | ## Basic Requirements 13 | Running a recent supported release of Debian, Fedora or Ubuntu on a x86 64bit based PC; without OS Virtualization Software.
14 | Many of the listed commands assume `/bin/bash` as the default shell.
15 | 16 | ARM Cross Compiler – GCC:
17 | * ARM Linux GCC Toolchain Binaries: https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/
18 | 19 | Bootloader
20 | * Das U-Boot – the Universal Boot Loader: http://www.denx.de/wiki/U-Boot
21 | * Source: https://github.com/STMicroelectronics/u-boot
22 | 23 | ATF
24 | * arm trusted firmware - https://trustedfirmware-a.readthedocs.io/en/latest/ 25 | * Source: https://github.com/STMicroelectronics/arm-trusted-firmware 26 | 27 | Linux Kernel
28 | * ST Mainline tree: https://github.com/STMicroelectronics/linux
29 | 30 | ARM based rootfs
31 | * Debian: https://www.debian.org
32 | * Ubuntu: https://www.ubuntu.com
33 | 34 | # Automatic build 35 | For full automatic build run: 36 | ```bash 37 | ./build.sh 38 | ``` 39 | *NOTE: Default build Ubuntu 22.04 Choosing a distribution to build in development.*
40 | *New contributors are welcome in development!* 41 | 42 | For separate build, uboot, kernel and rootfs 43 | ```bash 44 | ./build-uboot.sh 45 | ./build-linux.sh 46 | ``` 47 | For make sdcard.img image 48 | ```bash 49 | ./rootfs.sh # for get base rootfs sceleton 50 | ./create-rootfs.sh # make sd card image 51 | ``` 52 | 53 | ***update in progress build scripts** 54 | 55 | 56 | # Manual build 57 | For manual build, follow these steps. 58 | 59 | # Depends 60 | 61 | ``` 62 | sudo apt install flex bison ncurses-base build-essential qemu-user-static device-tree-compiler git libssl-dev libncurses-dev libgmp-dev libmpc-dev 63 | ``` 64 | 65 | ## ARM Cross Compiler: GCC 66 | This is a pre-built (64bit) version of GCC that runs on generic linux, sorry (32bit) x86 users, it’s time to upgrade… 67 | Download/Extract: 68 | 69 | ```bash 70 | #user@localhost:~$ 71 | wget -c https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/10.3.0/x86_64-gcc-10.3.0-nolibc-arm-linux-gnueabi.tar.gz 72 | tar xf x86_64-gcc-10.3.0-nolibc-arm-linux-gnueabi.tar.gz 73 | export CC=`pwd`/gcc-10.3.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi- 74 | ``` 75 | 76 | Test Cross Compiler: 77 | 78 | ```bash 79 | #user@localhost:~$ 80 | ${CC}gcc --version 81 | ``` 82 | 83 | ```bash 84 | #Test Output: 85 | arm-linux-gnueabi-gcc (GCC) 10.3.0 86 | Copyright (C) 2020 Free Software Foundation, Inc. 87 | This is free software; see the source for copying conditions. There is NO 88 | warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 89 | ``` 90 | 91 | 92 | ## Bootloader: U-Boot 93 | 94 | Das U-Boot – the Universal Boot Loader: http://www.denx.de/wiki/U-Boot
95 | Depending on your Linux Distrubution, you will also need a host gcc and other tools, so with Debian/Ubuntu start with installing the build-essential meta package.
96 | Download:
97 | 98 | ```bash 99 | #user@localhost:~$ 100 | git clone -b v2020.10-stm32mp https://github.com/STMicroelectronics/u-boot 101 | cd u-boot 102 | ``` 103 | 104 | Configure and Build:
105 | 106 | **stm32mp157a-sodimm2-mx** 107 | ```bash 108 | #user@localhost:~/u-boot$ 109 | make ARCH=arm CROSS_COMPILE=${CC} distclean 110 | make ARCH=arm CROSS_COMPILE=${CC} stm32mp15_trusted_defconfig 111 | make ARCH=arm CROSS_COMPILE=${CC} DEVICE_TREE=stm32mp157a-sodimm2-mx all 112 | ``` 113 | 114 | **stm32mp157c-ev1** 115 | ```bash 116 | #user@localhost:~/u-boot$ 117 | make ARCH=arm CROSS_COMPILE=${CC} distclean 118 | make ARCH=arm CROSS_COMPILE=${CC} stm32mp15_trusted_defconfig 119 | make ARCH=arm CROSS_COMPILE=${CC} DEVICE_TREE=stm32mp157c-ev1 all 120 | ``` 121 | 122 | **stm32mp157c-ed1** 123 | ```bash 124 | #user@localhost:~/u-boot$ 125 | make ARCH=arm CROSS_COMPILE=${CC} distclean 126 | make ARCH=arm CROSS_COMPILE=${CC} stm32mp15_trusted_defconfig 127 | make ARCH=arm CROSS_COMPILE=${CC} DEVICE_TREE=stm32mp157c-ed1 all 128 | ``` 129 | 130 | **stm32mp157a-dk1** 131 | ```bash 132 | #user@localhost:~/u-boot$ 133 | make ARCH=arm CROSS_COMPILE=${CC} distclean 134 | make ARCH=arm CROSS_COMPILE=${CC} stm32mp15_trusted_defconfig 135 | make ARCH=arm CROSS_COMPILE=${CC} DEVICE_TREE=stm32mp157a-dk1 all 136 | ``` 137 | 138 | **stm32mp157c-dk2** 139 | ```bash 140 | #user@localhost:~/u-boot$ 141 | make ARCH=arm CROSS_COMPILE=${CC} distclean 142 | make ARCH=arm CROSS_COMPILE=${CC} stm32mp15_trusted_defconfig 143 | make ARCH=arm CROSS_COMPILE=${CC} DEVICE_TREE=stm32mp157c-dk2 all 144 | ``` 145 | 146 | # arm-trusted-firmware 147 | 148 | ```bash 149 | cd .. 150 | git clone -b v2.4-stm32mp https://github.com/STMicroelectronics/arm-trusted-firmware 151 | cd arm-trusted-firmware 152 | ``` 153 | 154 | **stm32mp157a-sodimm2-mx** 155 | ```bash 156 | make CROSS_COMPILE=${CC} \ 157 | PLAT=stm32mp1 \ 158 | ARCH=aarch32 \ 159 | ARM_ARCH_MAJOR=7 \ 160 | STM32MP_SDMMC=1 \ 161 | STM32MP_EMMC=1 \ 162 | AARCH32_SP=sp_min \ 163 | DTB_FILE_NAME=stm32mp157a-sodimm2-mx.dtb \ 164 | BL33_CFG=../u-boot/u-boot.dtb \ 165 | BL33=../u-boot/u-boot-nodtb.bin \ 166 | all fip 167 | ``` 168 | 169 | **stm32mp157c-ev1** 170 | ```bash 171 | make CROSS_COMPILE=${CC} \ 172 | PLAT=stm32mp1 \ 173 | ARCH=aarch32 \ 174 | ARM_ARCH_MAJOR=7 \ 175 | STM32MP_SDMMC=1 \ 176 | STM32MP_EMMC=1 \ 177 | AARCH32_SP=sp_min \ 178 | DTB_FILE_NAME=stm32mp157c-ev1.dtb \ 179 | BL33_CFG=../u-boot/u-boot.dtb \ 180 | BL33=../u-boot/u-boot-nodtb.bin \ 181 | all fip 182 | ``` 183 | 184 | **stm32mp157c-ed1** 185 | ```bash 186 | make CROSS_COMPILE=${CC} \ 187 | PLAT=stm32mp1 \ 188 | ARCH=aarch32 \ 189 | ARM_ARCH_MAJOR=7 \ 190 | STM32MP_SDMMC=1 \ 191 | STM32MP_EMMC=1 \ 192 | AARCH32_SP=sp_min \ 193 | DTB_FILE_NAME=stm32mp157c-ed1.dtb \ 194 | BL33_CFG=../u-boot/u-boot.dtb \ 195 | BL33=../u-boot/u-boot-nodtb.bin \ 196 | all fip 197 | ``` 198 | 199 | **stm32mp157a-dk1** 200 | ```bash 201 | make CROSS_COMPILE=${CC} \ 202 | PLAT=stm32mp1 \ 203 | ARCH=aarch32 \ 204 | ARM_ARCH_MAJOR=7 \ 205 | STM32MP_SDMMC=1 \ 206 | STM32MP_EMMC=1 \ 207 | AARCH32_SP=sp_min \ 208 | DTB_FILE_NAME=stm32mp157a-dk1.dtb \ 209 | BL33_CFG=../u-boot/u-boot.dtb \ 210 | BL33=../u-boot/u-boot-nodtb.bin \ 211 | all fip 212 | ``` 213 | 214 | **stm32mp157c-dk2** 215 | ```bash 216 | make CROSS_COMPILE=${CC} \ 217 | PLAT=stm32mp1 \ 218 | ARCH=aarch32 \ 219 | ARM_ARCH_MAJOR=7 \ 220 | STM32MP_SDMMC=1 \ 221 | STM32MP_EMMC=1 \ 222 | AARCH32_SP=sp_min \ 223 | DTB_FILE_NAME=stm32mp157c-dk2.dtb \ 224 | BL33_CFG=../u-boot/u-boot.dtb \ 225 | BL33=../u-boot/u-boot-nodtb.bin \ 226 | all fip 227 | ``` 228 | 229 | 230 | ## Linux Kernel 231 | This script will build the kernel, modules, device tree binaries and copy them to the deploy directory. 232 | 233 | Download: 234 | ```bash 235 | #user@localhost:~$ 236 | cd .. 237 | git clone -b v5.10-stm32mp https://github.com/STMicroelectronics/linux 238 | cd linux 239 | ``` 240 | 241 | 242 | **Build:** 243 | ```bash 244 | # ST defconfig 245 | make ARCH=arm CROSS_COMPILE=${CC} multi_v7_defconfig fragment-01-multiv7_cleanup.config fragment-02-multiv7_addons.config 246 | 247 | # Choose the kernel modules you need 248 | make ARCH=arm CROSS_COMPILE=${CC} menuconfig 249 | make ARCH=arm CROSS_COMPILE=${CC} zImage modules -j16 250 | 251 | # build dts 252 | make ARCH=arm CROSS_COMPILE=${CC} dtbs 253 | 254 | # install kernel modules to pach 255 | mkdir -p ../deploy 256 | cp -v arch/arm/boot/zImage ../deploy 257 | mkdir -p ../deploy/modules 258 | make ARCH=arm CROSS_COMPILE=${CC} modules_install INSTALL_MOD_PATH="../deploy/modules" 259 | 260 | # install dtsb files to pach 261 | mkdir -p ../deploy/dtsb 262 | make ARCH=arm CROSS_COMPILE=${CC} dtbs_install INSTALL_DTBS_PATH=../deploy/dtsb 263 | 264 | # export kernel version 265 | export kernel_ver=$(cat "include/generated/utsrelease.h" | awk '{print $3}' | sed 's/\"//g' ) 266 | echo ${kernel_ver} 267 | cd .. 268 | ``` 269 | 270 | ## Root File System 271 | 272 | **Debian 11** 273 | 274 | **User and password:** `debian temppwd` `root root`
275 | 276 | Download: 277 | ```bash 278 | #user@localhost:~$ 279 | wget -c https://rcn-ee.com/rootfs/eewiki/minfs/debian-11.1-minimal-armhf-2021-11-02.tar.xz 280 | ``` 281 | 282 | Extract: 283 | ```bash 284 | #user@localhost:~$ 285 | tar xf debian-11.1-minimal-armhf-2021-11-02.tar.xz 286 | ``` 287 | 288 | 289 | ## Ubuntu 20.04 LTS 290 | **User and password:** `ubuntu temppwd` `root root`
291 | 292 | Download: 293 | ```bash 294 | #user@localhost:~$ 295 | wget -c https://rcn-ee.com/rootfs/eewiki/minfs/ubuntu-20.04.3-minimal-armhf-2021-11-02.tar.xz 296 | ``` 297 | 298 | Extract: 299 | ```bash 300 | #user@localhost:~$ 301 | tar xf ubuntu-20.04.3-minimal-armhf-2021-11-02.tar.xz 302 | ``` 303 | 304 | ## Ubuntu 18.04 LTS 305 | **User and password:** `ubuntu temppwd` `root root`
306 | 307 | Download: 308 | ```bash 309 | #user@localhost:~$ 310 | wget -c https://rcn-ee.com/rootfs/eewiki/minfs/ubuntu-18.04.6-minimal-armhf-2021-11-02.tar.xz 311 | ``` 312 | 313 | Extract: 314 | ```bash 315 | #user@localhost:~$ 316 | tar xf ubuntu-18.04.6-minimal-armhf-2021-11-02.tar.xz 317 | ``` 318 | 319 | Setup image for flash to microSD card 320 | 321 | **Create image and Partition Layout:** 322 | ```bash 323 | export DIR=$(pwd) 324 | export IMAGE_FILENAME="sdcard-stm32mp157.img" 325 | dd if=/dev/zero of=${DIR}/deploy/${IMAGE_FILENAME} bs=4096M count=2 326 | 327 | sgdisk --resize-table=128 -a 1 \ 328 | -n 1:34:545 -c 1:fsbl1 \ 329 | -n 2:546:1057 -c 2:fsbl2 \ 330 | -n 3:1058:5153 -c 3:fip \ 331 | -n 4:5154: -c 4:rootfs \ 332 | -p ./deploy/${IMAGE_FILENAME} 333 | 334 | ``` 335 | 336 | check output sgdisk: 337 | ```bash 338 | # 339 | # Disk /home/vitaliy/sdcard.img: 8388592 sectors, 4.0 GiB 340 | # Sector size (logical): 512 bytes 341 | # Disk identifier (GUID): 6473AC10-6A3A-4A4B-B3BF-59BD7982185D 342 | # Partition table holds up to 128 entries 343 | # Main partition table begins at sector 2 and ends at sector 33 344 | # First usable sector is 34, last usable sector is 8388558 345 | # Partitions will be aligned on 1-sector boundaries 346 | # Total free space is 0 sectors (0 bytes) 347 | 348 | Number Start (sector) End (sector) Size Code Name 349 | 1 34 545 256.0 KiB 8300 fsbl1 350 | 2 546 1057 256.0 KiB 8300 fsbl2 351 | 3 1058 5153 2.0 MiB 8300 ssbl 352 | 4 5154 8388558 4.0 GiB 8300 rootfs 353 | ``` 354 | 355 | **Set legacy BIOS partition:** 356 | 357 | ```bash 358 | sgdisk -A 4:set:2 ./deploy/${IMAGE_FILENAME} 359 | ``` 360 | 361 | **Create loop device** 362 | ```bash 363 | LOOP_DEVICE=$(sudo losetup --partscan --show --find ./deploy/${IMAGE_FILENAME}) 364 | ``` 365 | Check mounted partition: 366 | ``` 367 | ls -l ${LOOP_DEVICE}* 368 | ``` 369 | ```bash 370 | #user@localhost:~$ ls -l /dev/loop0* 371 | brw-rw---- 1 root disk 7, 0 лис 7 13:31 /dev/loop0 372 | brw-rw---- 1 root disk 259, 7 лис 7 13:31 /dev/loop0p1 373 | brw-rw---- 1 root disk 259, 8 лис 7 13:31 /dev/loop0p2 374 | brw-rw---- 1 root disk 259, 9 лис 7 13:31 /dev/loop0p3 375 | brw-rw---- 1 root disk 259, 10 лис 7 13:31 /dev/loop0p4 376 | ``` 377 | 378 | **Install U-Boot bootloader:** 379 | 380 | **stm32mp157a-sodimm2-mx** 381 | ```bash 382 | #user@localhost:~$ 383 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157a-sodimm2-mx.stm32 of=${LOOP_DEVICE}p1 384 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157a-sodimm2-mx.stm32 of=${LOOP_DEVICE}p2 385 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/fip.bin of=${LOOP_DEVICE}p3 386 | ``` 387 | 388 | **stm32mp157c-ev1** 389 | ```bash 390 | #user@localhost:~$ 391 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157c-ev1.stm32 of=${LOOP_DEVICE}p1 392 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157c-ev1.stm32 of=${LOOP_DEVICE}p2 393 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/fip.bin of=${LOOP_DEVICE}p3 394 | ``` 395 | 396 | **stm32mp157c-ed1** 397 | ```bash 398 | #user@localhost:~$ 399 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157c-ed1.stm32 of=${LOOP_DEVICE}p1 400 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157c-ed1.stm32 of=${LOOP_DEVICE}p2 401 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/fip.bin of=${LOOP_DEVICE}p3 402 | ``` 403 | 404 | **stm32mp157a-dk1** 405 | ```bash 406 | #user@localhost:~$ 407 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157a-dk1.stm32 of=${LOOP_DEVICE}p1 408 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157a-dk1.stm32 of=${LOOP_DEVICE}p2 409 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/fip.bin of=${LOOP_DEVICE}p3 410 | ``` 411 | 412 | **stm32mp157c-dk2** 413 | ```bash 414 | #user@localhost:~$ 415 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157c-dk2.stm32 of=${LOOP_DEVICE}p1 416 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/tf-a-stm32mp157c-dk2.stm32 of=${LOOP_DEVICE}p2 417 | sudo dd if=./arm-trusted-firmware/build/stm32mp1/release/fip.bin of=${LOOP_DEVICE}p3 418 | ``` 419 | 420 | 421 | 422 | **Format RootFS Partition:** 423 | ```bash 424 | sudo mkfs.ext4 -L rootfs ${LOOP_DEVICE}p4 425 | ``` 426 | 427 | **Mount rootfs file system** 428 | ```bash 429 | sudo mkdir -p deploy/rootfs 430 | MOUNT_PATH=deploy/rootfs 431 | sudo mount ${LOOP_DEVICE}p4 ${MOUNT_PATH} 432 | ``` 433 | 434 | ## Install Kernel and Root File System 435 | 436 | **Copy Root File System** 437 | ```bash 438 | #Debian; Root File System: user@localhost:~$ 439 | sudo tar xfvp ./debian-*-*-armhf-rootfs-*.tar -C ${MOUNT_PATH} 440 | sync 441 | ``` 442 | 443 | ```bash 444 | #Ubuntu; Root File System: user@localhost:~$ 445 | sudo tar xfvp ./ubuntu-base-XX.XX-base-armhf.tar.gz -C ${MOUNT_PATH} 446 | sync 447 | ``` 448 | 449 | **Setup extlinux.conf** 450 | ```bash 451 | #user@localhost:~$ 452 | sudo mkdir -p ${MOUNT_PATH}/boot/extlinux/ 453 | sudo sh -c "echo 'label Linux ${kernel_ver}' > ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 454 | sudo sh -c "echo ' kernel /boot/vmlinuz-${kernel_ver}' >> ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 455 | sudo sh -c "echo ' append console=ttySTM0,115200 console=tty1,115200 root=/dev/mmcblk\${boot_instance}p4 ro rootwait ' >> ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 456 | sudo sh -c "echo ' fdtdir /boot/dtbs/${kernel_ver}/' >> ${MOUNT_PATH}/boot/extlinux/extlinux.conf" 457 | ``` 458 | 459 | **Copy Kernel Image** 460 | ```bash 461 | #user@localhost:~$ 462 | sudo cp -v ./deploy/zImage ${MOUNT_PATH}/boot/vmlinuz-${kernel_ver} 463 | ``` 464 | 465 | **Copy Kernel Device Tree Binaries** 466 | ```bash 467 | #user@localhost:~$ 468 | sudo mkdir -p ${MOUNT_PATH}/boot/dtbs/${kernel_ver}/ 469 | sudo cp -r ./deploy/dtsb/* ${MOUNT_PATH}/boot/dtbs/${kernel_ver}/ 470 | ``` 471 | 472 | **Copy Kernel Modules** 473 | ```bash 474 | #user@localhost:~$ 475 | sudo cp -r ./deploy/modules/. ${MOUNT_PATH}/usr/ 476 | ``` 477 | 478 | **File Systems Table (/etc/fstab)** 479 | ```bash 480 | #user@localhost:~/$ 481 | sudo sh -c "echo '/dev/mmcblk0p4 / auto errors=remount-ro 0 1' >> ${MOUNT_PATH}/etc/fstab" 482 | ``` 483 | 484 | **For DK2 board. WiFi bin and config files** 485 | ```bash 486 | #user@localhost:~/$ 487 | mkdir wifi 488 | wget -P wifi https://github.com/cvetaevvitaliy/stm32mp1-ubuntu/raw/master/wifi_firmware/cyfmac43430-sdio.bin 489 | wget -P wifi https://github.com/cvetaevvitaliy/stm32mp1-ubuntu/raw/master/wifi_firmware/cyfmac43430-sdio.1DX.clm_blob 490 | wget -P wifi https://github.com/cvetaevvitaliy/stm32mp1-ubuntu/raw/master/wifi_firmware/brcmfmac43430-sdio.txt 491 | 492 | sudo mkdir -p ${MOUNT_PATH}/lib/firmware/brcm/ 493 | sudo cp -v ./wifi/brcmfmac43430-sdio.txt ${MOUNT_PATH}/lib/firmware/brcm/brcmfmac43430-sdio.st,stm32mp157c-dk2.txt 494 | sudo cp -v ./wifi/cyfmac43430-sdio.bin ${MOUNT_PATH}/lib/firmware/brcm/brcmfmac43430-sdio.bin 495 | sudo cp -v ./wifi/cyfmac43430-sdio.1DX.clm_blob ${MOUNT_PATH}/lib/firmware/brcm/brcmfmac43430-sdio.clm_blob 496 | 497 | ``` 498 | 499 | **Finish:** 500 | ```bash 501 | sync 502 | sudo umount ${MOUNT_PATH} 503 | sudo losetup -D 504 | ``` 505 | 506 | After successfully completing these steps, you will get `.img` image for writing to SD card 507 | 508 | ## How to flash .img to SD card 509 | 510 | For safe and easy writing to SD card download [balenaEtcher](https://www.balena.io/etcher/) 511 | 512 | **Steps:** 513 | * Insert SD card to card reader 514 | * Openn balenaEtcher 515 | * Select `sdcard.img` 516 | * Select connected SD card 517 | * Push button FLash 518 | * Done 519 | 520 | After flash remove sd card from PC and insert to STM32MP157 board 521 | 522 | ## Finished image for flash SD card for STM32MP157-DK2 523 | 524 | If you do not want to go through all the steps, you can download the finished SD card image, just write it to the SD card 525 | 526 | *update in progress 527 | 528 | -------------------------------------------------------------------------------- /00005-add-at-f-stm32mp157a-sodimm2-mx.patch: -------------------------------------------------------------------------------- 1 | diff --git a/fdts/stm32mp15-mx.dtsi b/fdts/stm32mp15-mx.dtsi 2 | new file mode 100644 3 | index 000000000..2b1e690de 4 | --- /dev/null 5 | +++ b/fdts/stm32mp15-mx.dtsi 6 | @@ -0,0 +1,119 @@ 7 | +/* 8 | + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved 9 | + * 10 | + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 11 | + * 12 | + */ 13 | + 14 | +/* 15 | + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs 16 | + * DDR type: DDR3 / DDR3L 17 | + * DDR width: 32bits 18 | + * DDR density: 8Gb 19 | + * System frequency: 533000kHz 20 | + * Relaxed Timing Mode: false 21 | + * Address mapping type: RBC 22 | + * 23 | + * Save Date: 2022.02.21, save Time: 13:47:46 24 | + */ 25 | + 26 | +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz" 27 | +#define DDR_MEM_SPEED 533000 28 | +#define DDR_MEM_SIZE 0x40000000 29 | + 30 | +#define DDR_MSTR 0x00040401 31 | +#define DDR_MRCTRL0 0x00000010 32 | +#define DDR_MRCTRL1 0x00000000 33 | +#define DDR_DERATEEN 0x00000000 34 | +#define DDR_DERATEINT 0x00800000 35 | +#define DDR_PWRCTL 0x00000000 36 | +#define DDR_PWRTMG 0x00400010 37 | +#define DDR_HWLPCTL 0x00000000 38 | +#define DDR_RFSHCTL0 0x00210000 39 | +#define DDR_RFSHCTL3 0x00000000 40 | +#define DDR_RFSHTMG 0x0081008B 41 | +#define DDR_CRCPARCTL0 0x00000000 42 | +#define DDR_DRAMTMG0 0x121B2414 43 | +#define DDR_DRAMTMG1 0x000A041C 44 | +#define DDR_DRAMTMG2 0x0608090F 45 | +#define DDR_DRAMTMG3 0x0050400C 46 | +#define DDR_DRAMTMG4 0x08040608 47 | +#define DDR_DRAMTMG5 0x06060403 48 | +#define DDR_DRAMTMG6 0x02020002 49 | +#define DDR_DRAMTMG7 0x00000202 50 | +#define DDR_DRAMTMG8 0x00001005 51 | +#define DDR_DRAMTMG14 0x000000A0 52 | +#define DDR_ZQCTL0 0xC2000040 53 | +#define DDR_DFITMG0 0x02060105 54 | +#define DDR_DFITMG1 0x00000202 55 | +#define DDR_DFILPCFG0 0x07000000 56 | +#define DDR_DFIUPD0 0xC0400003 57 | +#define DDR_DFIUPD1 0x00000000 58 | +#define DDR_DFIUPD2 0x00000000 59 | +#define DDR_DFIPHYMSTR 0x00000000 60 | +#define DDR_ODTCFG 0x06000600 61 | +#define DDR_ODTMAP 0x00000001 62 | +#define DDR_SCHED 0x00000C01 63 | +#define DDR_SCHED1 0x00000000 64 | +#define DDR_PERFHPR1 0x01000001 65 | +#define DDR_PERFLPR1 0x08000200 66 | +#define DDR_PERFWR1 0x08000400 67 | +#define DDR_DBG0 0x00000000 68 | +#define DDR_DBG1 0x00000000 69 | +#define DDR_DBGCMD 0x00000000 70 | +#define DDR_POISONCFG 0x00000000 71 | +#define DDR_PCCFG 0x00000010 72 | +#define DDR_PCFGR_0 0x00010000 73 | +#define DDR_PCFGW_0 0x00000000 74 | +#define DDR_PCFGQOS0_0 0x02100C03 75 | +#define DDR_PCFGQOS1_0 0x00800100 76 | +#define DDR_PCFGWQOS0_0 0x01100C03 77 | +#define DDR_PCFGWQOS1_0 0x01000200 78 | +#define DDR_PCFGR_1 0x00010000 79 | +#define DDR_PCFGW_1 0x00000000 80 | +#define DDR_PCFGQOS0_1 0x02100C03 81 | +#define DDR_PCFGQOS1_1 0x00800040 82 | +#define DDR_PCFGWQOS0_1 0x01100C03 83 | +#define DDR_PCFGWQOS1_1 0x01000200 84 | +#define DDR_ADDRMAP1 0x00080808 85 | +#define DDR_ADDRMAP2 0x00000000 86 | +#define DDR_ADDRMAP3 0x00000000 87 | +#define DDR_ADDRMAP4 0x00001F1F 88 | +#define DDR_ADDRMAP5 0x07070707 89 | +#define DDR_ADDRMAP6 0x0F070707 90 | +#define DDR_ADDRMAP9 0x00000000 91 | +#define DDR_ADDRMAP10 0x00000000 92 | +#define DDR_ADDRMAP11 0x00000000 93 | +#define DDR_PGCR 0x01442E02 94 | +#define DDR_PTR0 0x0022AA5B 95 | +#define DDR_PTR1 0x04841104 96 | +#define DDR_PTR2 0x042DA068 97 | +#define DDR_ACIOCR 0x10400812 98 | +#define DDR_DXCCR 0x00000C40 99 | +#define DDR_DSGCR 0xF200011F 100 | +#define DDR_DCR 0x0000000B 101 | +#define DDR_DTPR0 0x38D488D0 102 | +#define DDR_DTPR1 0x098B00D8 103 | +#define DDR_DTPR2 0x10023600 104 | +#define DDR_MR0 0x00000840 105 | +#define DDR_MR1 0x00000000 106 | +#define DDR_MR2 0x00000208 107 | +#define DDR_MR3 0x00000000 108 | +#define DDR_ODTCR 0x00010000 109 | +#define DDR_ZQ0CR1 0x00000038 110 | +#define DDR_DX0GCR 0x0000CE81 111 | +#define DDR_DX0DLLCR 0x40000000 112 | +#define DDR_DX0DQTR 0xFFFFFFFF 113 | +#define DDR_DX0DQSTR 0x3DB02000 114 | +#define DDR_DX1GCR 0x0000CE81 115 | +#define DDR_DX1DLLCR 0x40000000 116 | +#define DDR_DX1DQTR 0xFFFFFFFF 117 | +#define DDR_DX1DQSTR 0x3DB02000 118 | +#define DDR_DX2GCR 0x0000CE81 119 | +#define DDR_DX2DLLCR 0x40000000 120 | +#define DDR_DX2DQTR 0xFFFFFFFF 121 | +#define DDR_DX2DQSTR 0x3DB02000 122 | +#define DDR_DX3GCR 0x0000CE81 123 | +#define DDR_DX3DLLCR 0x40000000 124 | +#define DDR_DX3DQTR 0xFFFFFFFF 125 | +#define DDR_DX3DQSTR 0x3DB02000 126 | diff --git a/fdts/stm32mp157a-sodimm2-mx-fw-config.dts b/fdts/stm32mp157a-sodimm2-mx-fw-config.dts 127 | new file mode 100644 128 | index 000000000..d7dcbb0a4 129 | --- /dev/null 130 | +++ b/fdts/stm32mp157a-sodimm2-mx-fw-config.dts 131 | @@ -0,0 +1,12 @@ 132 | +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 133 | +/* 134 | + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 135 | + * Author: STM32CubeMX code generation for STMicroelectronics. 136 | + */ 137 | + 138 | +/* For more information on Device Tree configuration, please refer to 139 | + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 140 | + */ 141 | + 142 | +#define DDR_SIZE 0x40000000 /* 1GB */ 143 | +#include "stm32mp15-fw-config.dts" 144 | diff --git a/fdts/stm32mp157a-sodimm2-mx.dts b/fdts/stm32mp157a-sodimm2-mx.dts 145 | new file mode 100644 146 | index 000000000..cd86c1181 147 | --- /dev/null 148 | +++ b/fdts/stm32mp157a-sodimm2-mx.dts 149 | @@ -0,0 +1,801 @@ 150 | +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 151 | +/* 152 | + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 153 | + * Author: STM32CubeMX code generation for STMicroelectronics. 154 | + */ 155 | + 156 | +/* For more information on Device Tree configuration, please refer to 157 | + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 158 | + */ 159 | + 160 | +/dts-v1/; 161 | +#include 162 | +#include 163 | +#include 164 | +#include "stm32mp15-mx.dtsi" 165 | + 166 | +#include "stm32mp157.dtsi" 167 | +#include "stm32mp15xa.dtsi" 168 | +#include "stm32mp15xxaa-pinctrl.dtsi" 169 | +#include "stm32mp15-ddr.dtsi" 170 | + 171 | +/* USER CODE BEGIN includes */ 172 | +#include 173 | +/* USER CODE END includes */ 174 | + 175 | +/ { 176 | + model = "STMicroelectronics STM32MP157AAA3 SODIMM module"; 177 | + compatible = "st,stm32mp157a-sodimm2-mx", "st,stm32mp157"; 178 | + 179 | + memory@c0000000 { 180 | + device_type = "memory"; 181 | + reg = <0xc0000000 0x40000000>; 182 | + 183 | + /* USER CODE BEGIN memory */ 184 | + /* USER CODE END memory */ 185 | + }; 186 | + 187 | + /* USER CODE BEGIN root */ 188 | + 189 | + aliases{ 190 | + serial0 = &uart4; 191 | + //serial1 = &usart3; 192 | + }; 193 | + 194 | + vin:vin{ 195 | + compatible = "regulator-fixed"; 196 | + regulator-name = "vin"; 197 | + regulator-min-microvolt = <5000000>; 198 | + regulator-max-microvolt = <5000000>; 199 | + regulator-always-on; 200 | + }; 201 | + 202 | + chosen{ 203 | + stdout-path = "serial0:115200n8"; 204 | + }; 205 | + /* USER CODE END root */ 206 | + 207 | + clocks { 208 | + /* USER CODE BEGIN clocks */ 209 | + /* USER CODE END clocks */ 210 | + 211 | + clk_lse: clk-lse { 212 | + st,drive = < LSEDRV_MEDIUM_HIGH >; 213 | + 214 | + /* USER CODE BEGIN clk_lse */ 215 | + /* USER CODE END clk_lse */ 216 | + }; 217 | + 218 | + clk_hse: clk-hse { 219 | + st,digbypass; 220 | + 221 | + /* USER CODE BEGIN clk_hse */ 222 | + /* USER CODE END clk_hse */ 223 | + }; 224 | + }; 225 | + 226 | +}; /*root*/ 227 | + 228 | +&pinctrl { 229 | + quadspi_pins_mx: quadspi_mx-0 { 230 | + pins1 { 231 | + pinmux = , /* QUADSPI_BK1_NCS */ 232 | + ; /* QUADSPI_BK2_NCS */ 233 | + bias-pull-up; 234 | + drive-push-pull; 235 | + slew-rate = <1>; 236 | + }; 237 | + pins2 { 238 | + pinmux = ; /* QUADSPI_CLK */ 239 | + bias-disable; 240 | + drive-push-pull; 241 | + slew-rate = <3>; 242 | + }; 243 | + pins3 { 244 | + pinmux = , /* QUADSPI_BK1_IO3 */ 245 | + , /* QUADSPI_BK1_IO2 */ 246 | + , /* QUADSPI_BK1_IO0 */ 247 | + , /* QUADSPI_BK1_IO1 */ 248 | + , /* QUADSPI_BK2_IO3 */ 249 | + , /* QUADSPI_BK2_IO2 */ 250 | + , /* QUADSPI_BK2_IO0 */ 251 | + ; /* QUADSPI_BK2_IO1 */ 252 | + bias-disable; 253 | + drive-push-pull; 254 | + slew-rate = <1>; 255 | + }; 256 | + }; 257 | + 258 | + sdmmc1_pins_mx: sdmmc1_mx-0 { 259 | + pins1 { 260 | + pinmux = , /* SDMMC1_D0 */ 261 | + , /* SDMMC1_D1 */ 262 | + , /* SDMMC1_D2 */ 263 | + , /* SDMMC1_D3 */ 264 | + ; /* SDMMC1_CMD */ 265 | + bias-pull-up; 266 | + drive-push-pull; 267 | + slew-rate = <1>; 268 | + }; 269 | + pins2 { 270 | + pinmux = ; /* SDMMC1_CK */ 271 | + bias-pull-up; 272 | + drive-push-pull; 273 | + slew-rate = <2>; 274 | + }; 275 | + }; 276 | + 277 | + sdmmc2_pins_mx: sdmmc2_mx-0 { 278 | + pins1 { 279 | + pinmux = , /* SDMMC2_D4 */ 280 | + , /* SDMMC2_D5 */ 281 | + , /* SDMMC2_D2 */ 282 | + , /* SDMMC2_D3 */ 283 | + , /* SDMMC2_D0 */ 284 | + , /* SDMMC2_D1 */ 285 | + , /* SDMMC2_D7 */ 286 | + , /* SDMMC2_D6 */ 287 | + ; /* SDMMC2_CMD */ 288 | + bias-pull-up; 289 | + drive-push-pull; 290 | + slew-rate = <1>; 291 | + }; 292 | + pins2 { 293 | + pinmux = ; /* SDMMC2_CK */ 294 | + bias-pull-up; 295 | + drive-push-pull; 296 | + slew-rate = <2>; 297 | + }; 298 | + }; 299 | + 300 | + uart4_pins_mx: uart4_mx-0 { 301 | + pins1 { 302 | + pinmux = ; /* UART4_RX */ 303 | + bias-disable; 304 | + }; 305 | + pins2 { 306 | + pinmux = ; /* UART4_TX */ 307 | + bias-disable; 308 | + drive-push-pull; 309 | + slew-rate = <0>; 310 | + }; 311 | + }; 312 | + 313 | + usb_otg_hs_pins_mx: usb_otg_hs_mx-0 { 314 | + pins { 315 | + pinmux = ; /* USB_OTG_HS_ID */ 316 | + }; 317 | + }; 318 | + 319 | + /* USER CODE BEGIN pinctrl */ 320 | + /* USER CODE END pinctrl */ 321 | +}; 322 | + 323 | +&pinctrl_z { 324 | + i2c4_pins_z_mx: i2c4_mx-0 { 325 | + pins { 326 | + pinmux = , /* I2C4_SCL */ 327 | + ; /* I2C4_SDA */ 328 | + bias-disable; 329 | + drive-open-drain; 330 | + slew-rate = <0>; 331 | + }; 332 | + }; 333 | + 334 | + /* USER CODE BEGIN pinctrl_z */ 335 | + /* USER CODE END pinctrl_z */ 336 | +}; 337 | + 338 | +&bsec{ 339 | + status = "okay"; 340 | + secure-status = "okay"; 341 | + 342 | + /* USER CODE BEGIN bsec */ 343 | + 344 | + board_id:board_id@ec{ 345 | + reg = <0xec 0x4>; 346 | + st,non-secure-otp; 347 | + }; 348 | + /* USER CODE END bsec */ 349 | +}; 350 | + 351 | +&etzpc{ 352 | + secure-status = "okay"; 353 | + st,decprot = < 354 | + /*"Non Secured" peripherals*/ 355 | + DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 356 | + DECPROT(STM32MP1_ETZPC_DCMI_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 357 | + DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 358 | + DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 359 | + DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 360 | + DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 361 | + DECPROT(STM32MP1_ETZPC_TT_FDCAN_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 362 | + DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 363 | + DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 364 | + DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 365 | + DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 366 | + DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 367 | + DECPROT(STM32MP1_ETZPC_DLYBQ_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 368 | + DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 369 | + DECPROT(STM32MP1_ETZPC_TIM6_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 370 | + DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 371 | + DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK) 372 | + /*"NS_R S_W" peripherals*/ 373 | + DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK) 374 | + DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK) 375 | + /*"Secured" peripherals*/ 376 | + DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK) 377 | + 378 | + /*Restriction: following IDs are not managed - please to use User-Section if needed: 379 | + STM32MP1_ETZPC_SRAMx_ID STM32MP1_ETZPC_RETRAM_ID STM32MP1_ETZPC_BKPSRAM_ID*/ 380 | + 381 | + /* USER CODE BEGIN etzpc_decprot */ 382 | + /*STM32CubeMX generates a basic and standard configuration for ETZPC. 383 | + Additional device configurations can be added here if needed. 384 | + "etzpc" node could be also overloaded in "addons" User-Section.*/ 385 | + 386 | + DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK) 387 | + 388 | + /* USER CODE END etzpc_decprot */ 389 | + >; 390 | + 391 | + /* USER CODE BEGIN etzpc */ 392 | + /* USER CODE END etzpc */ 393 | +}; 394 | + 395 | +&hash1{ 396 | + status = "okay"; 397 | + 398 | + /* USER CODE BEGIN hash1 */ 399 | + /* USER CODE END hash1 */ 400 | +}; 401 | + 402 | +&i2c4{ 403 | + pinctrl-names = "default"; 404 | + pinctrl-0 = <&i2c4_pins_z_mx>; 405 | + status = "okay"; 406 | + secure-status = "okay"; 407 | + 408 | + /* USER CODE BEGIN i2c4 */ 409 | + i2c-scl-rising-time-ns = <185>; 410 | + i2c-scl-falling-time-ns = <20>; 411 | + clock-frequency = <400000>; 412 | + 413 | + pmic:stpmic@33{ 414 | + compatible = "st,stpmic1"; 415 | + reg = <0x33>; 416 | + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 417 | + interrupt-controller; 418 | + #interrupt-cells = <2>; 419 | + status = "okay"; 420 | + secure-status = "okay"; 421 | + 422 | + regulators{ 423 | + compatible = "st,stpmic1-regulators"; 424 | + buck1-supply = <&vin>; 425 | + buck2-supply = <&vin>; 426 | + buck3-supply = <&vin>; 427 | + buck4-supply = <&vin>; 428 | + ldo1-supply = <&v3v3>; 429 | + ldo2-supply = <&v3v3>; 430 | + ldo3-supply = <&vdd_ddr>; 431 | + ldo4-supply = <&vin>; 432 | + ldo5-supply = <&v3v3>; 433 | + ldo6-supply = <&v3v3>; 434 | + vref_ddr-supply = <&vin>; 435 | + boost-supply = <&vin>; 436 | + pwr_sw1-supply = <&bst_out>; 437 | + pwr_sw2-supply = <&bst_out>; 438 | + 439 | + vddcore:buck1{ 440 | + regulator-name = "vddcore"; 441 | + regulator-min-microvolt = <1200000>; 442 | + regulator-max-microvolt = <1350000>; 443 | + regulator-always-on; 444 | + regulator-initial-mode = <0>; 445 | + regulator-over-current-protection; 446 | + 447 | + lp-stop{ 448 | + regulator-on-in-suspend; 449 | + regulator-suspend-microvolt = <1200000>; 450 | + }; 451 | + 452 | + lplv-stop{ 453 | + regulator-on-in-suspend; 454 | + regulator-suspend-microvolt = <900000>; 455 | + }; 456 | + 457 | + standby-ddr-sr{ 458 | + regulator-off-in-suspend; 459 | + }; 460 | + 461 | + standby-ddr-off{ 462 | + regulator-off-in-suspend; 463 | + }; 464 | + }; 465 | + 466 | + vdd_ddr:buck2{ 467 | + regulator-name = "vdd_ddr"; 468 | + regulator-min-microvolt = <1350000>; 469 | + regulator-max-microvolt = <1350000>; 470 | + regulator-always-on; 471 | + regulator-initial-mode = <0>; 472 | + regulator-over-current-protection; 473 | + 474 | + lp-stop{ 475 | + regulator-suspend-microvolt = <1350000>; 476 | + regulator-on-in-suspend; 477 | + }; 478 | + 479 | + lplv-stop{ 480 | + regulator-suspend-microvolt = <1350000>; 481 | + regulator-on-in-suspend; 482 | + }; 483 | + 484 | + standby-ddr-sr{ 485 | + regulator-suspend-microvolt = <1350000>; 486 | + regulator-on-in-suspend; 487 | + }; 488 | + 489 | + standby-ddr-off{ 490 | + regulator-off-in-suspend; 491 | + }; 492 | + }; 493 | + 494 | + vdd:buck3{ 495 | + regulator-name = "vdd"; 496 | + regulator-min-microvolt = <3300000>; 497 | + regulator-max-microvolt = <3300000>; 498 | + regulator-always-on; 499 | + st,mask-reset; 500 | + regulator-initial-mode = <0>; 501 | + regulator-over-current-protection; 502 | + 503 | + lp-stop{ 504 | + regulator-suspend-microvolt = <3300000>; 505 | + regulator-on-in-suspend; 506 | + }; 507 | + 508 | + lplv-stop{ 509 | + regulator-suspend-microvolt = <3300000>; 510 | + regulator-on-in-suspend; 511 | + }; 512 | + 513 | + standby-ddr-sr{ 514 | + regulator-suspend-microvolt = <3300000>; 515 | + regulator-on-in-suspend; 516 | + }; 517 | + 518 | + standby-ddr-off{ 519 | + regulator-suspend-microvolt = <3300000>; 520 | + regulator-on-in-suspend; 521 | + }; 522 | + }; 523 | + 524 | + v3v3:buck4{ 525 | + regulator-name = "v3v3"; 526 | + regulator-min-microvolt = <3300000>; 527 | + regulator-max-microvolt = <3300000>; 528 | + regulator-always-on; 529 | + regulator-over-current-protection; 530 | + regulator-initial-mode = <0>; 531 | + 532 | + standby-ddr-sr{ 533 | + regulator-off-in-suspend; 534 | + }; 535 | + 536 | + standby-ddr-off{ 537 | + regulator-off-in-suspend; 538 | + }; 539 | + }; 540 | + 541 | + vdda:ldo1{ 542 | + regulator-name = "vdda"; 543 | + regulator-min-microvolt = <2900000>; 544 | + regulator-max-microvolt = <2900000>; 545 | + 546 | + standby-ddr-sr{ 547 | + regulator-off-in-suspend; 548 | + }; 549 | + 550 | + standby-ddr-off{ 551 | + regulator-off-in-suspend; 552 | + }; 553 | + }; 554 | + 555 | + v2v8:ldo2{ 556 | + regulator-name = "v2v8"; 557 | + regulator-min-microvolt = <2800000>; 558 | + regulator-max-microvolt = <2800000>; 559 | + 560 | + standby-ddr-sr{ 561 | + regulator-off-in-suspend; 562 | + }; 563 | + 564 | + standby-ddr-off{ 565 | + regulator-off-in-suspend; 566 | + }; 567 | + }; 568 | + 569 | + vtt_ddr:ldo3{ 570 | + regulator-name = "vtt_ddr"; 571 | + regulator-always-on; 572 | + regulator-over-current-protection; 573 | + st,regulator-sink-source; 574 | + 575 | + lp-stop{ 576 | + regulator-off-in-suspend; 577 | + }; 578 | + 579 | + lplv-stop{ 580 | + regulator-off-in-suspend; 581 | + }; 582 | + 583 | + standby-ddr-sr{ 584 | + regulator-off-in-suspend; 585 | + }; 586 | + 587 | + standby-ddr-off{ 588 | + regulator-off-in-suspend; 589 | + }; 590 | + }; 591 | + 592 | + vdd_usb:ldo4{ 593 | + regulator-name = "vdd_usb"; 594 | + regulator-min-microvolt = <3300000>; 595 | + regulator-max-microvolt = <3300000>; 596 | + 597 | + standby-ddr-sr{ 598 | + regulator-off-in-suspend; 599 | + }; 600 | + 601 | + standby-ddr-off{ 602 | + regulator-off-in-suspend; 603 | + }; 604 | + }; 605 | + 606 | + vdd_sd:ldo5{ 607 | + regulator-name = "vdd_sd"; 608 | + regulator-min-microvolt = <2900000>; 609 | + regulator-max-microvolt = <2900000>; 610 | + regulator-boot-on; 611 | + 612 | + standby-ddr-sr{ 613 | + regulator-off-in-suspend; 614 | + }; 615 | + 616 | + standby-ddr-off{ 617 | + regulator-off-in-suspend; 618 | + }; 619 | + }; 620 | + 621 | + v1v8:ldo6{ 622 | + regulator-name = "v1v8"; 623 | + regulator-min-microvolt = <1800000>; 624 | + regulator-max-microvolt = <1800000>; 625 | + regulator-enable-ramp-delay = <300000>; 626 | + 627 | + standby-ddr-sr{ 628 | + regulator-off-in-suspend; 629 | + }; 630 | + 631 | + standby-ddr-off{ 632 | + regulator-off-in-suspend; 633 | + }; 634 | + }; 635 | + 636 | + vref_ddr:vref_ddr{ 637 | + regulator-name = "vref_ddr"; 638 | + regulator-always-on; 639 | + 640 | + lp-stop{ 641 | + regulator-on-in-suspend; 642 | + }; 643 | + 644 | + lplv-stop{ 645 | + regulator-on-in-suspend; 646 | + }; 647 | + 648 | + standby-ddr-sr{ 649 | + regulator-on-in-suspend; 650 | + }; 651 | + 652 | + standby-ddr-off{ 653 | + regulator-off-in-suspend; 654 | + }; 655 | + }; 656 | + 657 | + bst_out:boost{ 658 | + regulator-name = "bst_out"; 659 | + }; 660 | + 661 | + vbus_otg:pwr_sw1{ 662 | + regulator-name = "vbus_otg"; 663 | + }; 664 | + 665 | + vbus_sw:pwr_sw2{ 666 | + regulator-name = "vbus_sw"; 667 | + regulator-active-discharge = <1>; 668 | + }; 669 | + }; 670 | + }; 671 | + /* USER CODE END i2c4 */ 672 | +}; 673 | + 674 | +&iwdg2{ 675 | + status = "okay"; 676 | + secure-status = "okay"; 677 | + 678 | + /* USER CODE BEGIN iwdg2 */ 679 | + timeout-sec = <32>; 680 | + secure-timeout-sec = <5>; 681 | + /* USER CODE END iwdg2 */ 682 | +}; 683 | + 684 | +&pwr_regulators{ 685 | + status = "okay"; 686 | + secure-status = "okay"; 687 | + 688 | + /* USER CODE BEGIN pwr_regulators */ 689 | + system_suspend_supported_soc_modes = < 690 | + STM32_PM_CSLEEP_RUN 691 | + STM32_PM_CSTOP_ALLOW_LP_STOP 692 | + STM32_PM_CSTOP_ALLOW_LPLV_STOP 693 | + STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR 694 | + >; 695 | + system_off_soc_mode = ; 696 | + vdd-supply = <&vdd>; 697 | + vdd_3v3_usbfs-supply = <&vdd_usb>; 698 | + /* USER CODE END pwr_regulators */ 699 | +}; 700 | + 701 | +&qspi{ 702 | + pinctrl-names = "default"; 703 | + pinctrl-0 = <&quadspi_pins_mx>; 704 | + status = "okay"; 705 | + 706 | + /* USER CODE BEGIN qspi */ 707 | + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 708 | + #address-cells = <1>; 709 | + #size-cells = <0>; 710 | + 711 | + flash0:mx66l51235l@0{ 712 | + compatible = "jedec,spi-nor"; 713 | + reg = <0>; 714 | + spi-rx-bus-width = <4>; 715 | + spi-max-frequency = <108000000>; 716 | + #address-cells = <1>; 717 | + #size-cells = <1>; 718 | + }; 719 | + /* USER CODE END qspi */ 720 | +}; 721 | + 722 | +&rcc{ 723 | + status = "okay"; 724 | + secure-status = "okay"; 725 | + st,csi-cal; 726 | + st,hsi-cal; 727 | + st,cal-sec = <60>; 728 | + st,clksrc = < 729 | + CLK_MPU_PLL1P 730 | + CLK_AXI_PLL2P 731 | + CLK_MCU_PLL3P 732 | + CLK_PLL12_HSE 733 | + CLK_PLL3_HSE 734 | + CLK_PLL4_HSE 735 | + CLK_RTC_LSE 736 | + CLK_MCO1_DISABLED 737 | + CLK_MCO2_DISABLED 738 | + >; 739 | + st,clkdiv = < 740 | + 1 /*MPU*/ 741 | + 0 /*AXI*/ 742 | + 0 /*MCU*/ 743 | + 1 /*APB1*/ 744 | + 1 /*APB2*/ 745 | + 1 /*APB3*/ 746 | + 1 /*APB4*/ 747 | + 2 /*APB5*/ 748 | + 23 /*RTC*/ 749 | + 0 /*MCO1*/ 750 | + 0 /*MCO2*/ 751 | + >; 752 | + st,pkcs = < 753 | + CLK_CKPER_DISABLED 754 | + CLK_QSPI_ACLK 755 | + CLK_ETH_PLL4P 756 | + CLK_SDMMC12_PLL4P 757 | + CLK_STGEN_HSE 758 | + CLK_USBPHY_HSE 759 | + CLK_SPI2S1_DISABLED 760 | + CLK_SPI2S23_DISABLED 761 | + CLK_SPI45_DISABLED 762 | + CLK_SPI6_DISABLED 763 | + CLK_I2C46_HSI 764 | + CLK_SDMMC3_DISABLED 765 | + CLK_USBO_USBPHY 766 | + CLK_ADC_PLL4R 767 | + CLK_CEC_DISABLED 768 | + CLK_I2C12_HSI 769 | + CLK_I2C35_PCLK1 770 | + CLK_UART1_DISABLED 771 | + CLK_UART24_HSI 772 | + CLK_UART35_DISABLED 773 | + CLK_UART6_DISABLED 774 | + CLK_UART78_DISABLED 775 | + CLK_SPDIF_DISABLED 776 | + CLK_FDCAN_PLL3Q 777 | + CLK_SAI1_DISABLED 778 | + CLK_SAI2_DISABLED 779 | + CLK_SAI3_DISABLED 780 | + CLK_SAI4_DISABLED 781 | + CLK_RNG1_LSI 782 | + CLK_LPTIM1_DISABLED 783 | + CLK_LPTIM23_DISABLED 784 | + CLK_LPTIM45_DISABLED 785 | + >; 786 | + pll2:st,pll@1 { 787 | + compatible = "st,stm32mp1-pll"; 788 | + reg = <1>; 789 | + cfg = < 2 65 1 0 0 PQR(1,1,1) >; 790 | + frac = < 0x1400 >; 791 | + }; 792 | + pll3:st,pll@2 { 793 | + compatible = "st,stm32mp1-pll"; 794 | + reg = <2>; 795 | + cfg = < 1 49 2 5 36 PQR(1,1,0) >; 796 | + }; 797 | + pll4:st,pll@3 { 798 | + compatible = "st,stm32mp1-pll"; 799 | + reg = <3>; 800 | + cfg = < 3 98 5 17 7 PQR(1,1,0) >; 801 | + }; 802 | + 803 | + /* USER CODE BEGIN rcc */ 804 | + /* USER CODE END rcc */ 805 | +}; 806 | + 807 | +&rng1{ 808 | + status = "okay"; 809 | + secure-status = "okay"; 810 | + 811 | + /* USER CODE BEGIN rng1 */ 812 | + /* USER CODE END rng1 */ 813 | +}; 814 | + 815 | +&rtc{ 816 | + status = "okay"; 817 | + secure-status = "okay"; 818 | + 819 | + /* USER CODE BEGIN rtc */ 820 | + /* USER CODE END rtc */ 821 | +}; 822 | + 823 | +&sdmmc1{ 824 | + pinctrl-names = "default"; 825 | + pinctrl-0 = <&sdmmc1_pins_mx>; 826 | + status = "okay"; 827 | + 828 | + /* USER CODE BEGIN sdmmc1 */ 829 | + broken-cd; 830 | + st,neg-edge; 831 | + bus-width = <4>; 832 | + vmmc-supply = <&vdd_sd>; 833 | + //sd-uhs-sdr12; 834 | + //sd-uhs-sdr25; 835 | + //sd-uhs-sdr50; 836 | + //sd-uhs-ddr50; 837 | + /* USER CODE END sdmmc1 */ 838 | +}; 839 | + 840 | +&sdmmc2{ 841 | + pinctrl-names = "default"; 842 | + pinctrl-0 = <&sdmmc2_pins_mx>; 843 | + status = "okay"; 844 | + 845 | + /* USER CODE BEGIN sdmmc2 */ 846 | + non-removable; 847 | + no-sd; 848 | + no-sdio; 849 | + st,neg-edge; 850 | + bus-width = <8>; 851 | + vmmc-supply = <&v3v3>; 852 | + vqmmc-supply = <&vdd>; 853 | + mmc-ddr-3_3v; 854 | + /* USER CODE END sdmmc2 */ 855 | +}; 856 | + 857 | +&tamp{ 858 | + status = "okay"; 859 | + secure-status = "okay"; 860 | + 861 | + /* USER CODE BEGIN tamp */ 862 | + /* USER CODE END tamp */ 863 | +}; 864 | + 865 | +&timers15{ 866 | + secure-status = "okay"; 867 | + 868 | + /* USER CODE BEGIN timers15 */ 869 | + st,hsi-cal-input = <7>; 870 | + st,csi-cal-input = <8>; 871 | + /* USER CODE END timers15 */ 872 | +}; 873 | + 874 | +&uart4{ 875 | + pinctrl-names = "default"; 876 | + pinctrl-0 = <&uart4_pins_mx>; 877 | + status = "okay"; 878 | + 879 | + /* USER CODE BEGIN uart4 */ 880 | + /* USER CODE END uart4 */ 881 | +}; 882 | + 883 | +&usbotg_hs{ 884 | + pinctrl-names = "default"; 885 | + pinctrl-0 = <&usb_otg_hs_pins_mx>; 886 | + status = "okay"; 887 | + 888 | + /* USER CODE BEGIN usbotg_hs */ 889 | + vbus-supply = <&vbus_otg>; 890 | + phys = <&usbphyc_port1 0>; 891 | + phy-names = "usb2-phy"; 892 | + /* USER CODE END usbotg_hs */ 893 | +}; 894 | + 895 | +&usbphyc{ 896 | + status = "okay"; 897 | + 898 | + /* USER CODE BEGIN usbphyc */ 899 | + /* USER CODE END usbphyc */ 900 | +}; 901 | + 902 | +&usbphyc_port0{ 903 | + status = "okay"; 904 | + 905 | + /* USER CODE BEGIN usbphyc_port0 */ 906 | + phy-supply = <&vdd_usb>; 907 | + /* USER CODE END usbphyc_port0 */ 908 | +}; 909 | + 910 | +&usbphyc_port1{ 911 | + status = "okay"; 912 | + 913 | + /* USER CODE BEGIN usbphyc_port1 */ 914 | + phy-supply = <&vdd_usb>; 915 | + /* USER CODE END usbphyc_port1 */ 916 | +}; 917 | + 918 | +/* USER CODE BEGIN addons */ 919 | + 920 | +&cpu0{ 921 | + cpu-supply = <&vddcore>; 922 | + clock-frequency = <650000000>; 923 | +}; 924 | + 925 | +&cpu1{ 926 | + cpu-supply = <&vddcore>; 927 | + clock-frequency = <650000000>; 928 | +}; 929 | + 930 | +&nvmem_layout{ 931 | + nvmem-cells = <&cfg0_otp>, 932 | + <&part_number_otp>, 933 | + <&monotonic_otp>, 934 | + <&nand_otp>, 935 | + <&uid_otp>, 936 | + <&package_otp>, 937 | + <&hw2_otp>, 938 | + <&pkh_otp>, 939 | + <&board_id>; 940 | + nvmem-cell-names = "cfg0_otp", 941 | + "part_number_otp", 942 | + "monotonic_otp", 943 | + "nand_otp", 944 | + "uid_otp", 945 | + "package_otp", 946 | + "hw2_otp", 947 | + "pkh_otp", 948 | + "board_id"; 949 | +}; 950 | +/* USER CODE END addons */ 951 | -------------------------------------------------------------------------------- /00001-add-stm32mp157a-sodimm2-mx.patch: -------------------------------------------------------------------------------- 1 | diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile 2 | index 4c3ba0468276..f82f1e9824b8 100644 3 | --- a/arch/arm/boot/dts/Makefile 4 | +++ b/arch/arm/boot/dts/Makefile 5 | @@ -30,6 +30,7 @@ DTC_FLAGS_stm32mp157c-ev1-a7-examples += -@ 6 | DTC_FLAGS_stm32mp157c-ev1-m4-examples += -@ 7 | DTC_FLAGS_stm32mp157f-ev1-a7-examples += -@ 8 | DTC_FLAGS_stm32mp157f-ev1-m4-examples += -@ 9 | +DTC_FLAGS_stm32mp157a-sodimm2-mx += -@ 10 | 11 | dtb-$(CONFIG_ARCH_ALPINE) += \ 12 | alpine-db.dtb 13 | @@ -1118,7 +1119,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ 14 | stm32mp157f-ev1-a7-examples.dtb \ 15 | stm32mp157f-ev1-m4-examples.dtb \ 16 | stm32mp157c-lxa-mc1.dtb \ 17 | - stm32mp157c-odyssey.dtb 18 | + stm32mp157c-odyssey.dtb \ 19 | + stm32mp157a-sodimm2-mx.dtb 20 | dtb-$(CONFIG_MACH_SUN4I) += \ 21 | sun4i-a10-a1000.dtb \ 22 | sun4i-a10-ba10-tvbox.dtb \ 23 | diff --git a/arch/arm/boot/dts/stm32mp157a-sodimm2-mx.dts b/arch/arm/boot/dts/stm32mp157a-sodimm2-mx.dts 24 | new file mode 100644 25 | index 000000000000..2867c4d45923 26 | --- /dev/null 27 | +++ b/arch/arm/boot/dts/stm32mp157a-sodimm2-mx.dts 28 | @@ -0,0 +1,1509 @@ 29 | +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 30 | +/* 31 | + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 32 | + * Author: STM32CubeMX code generation for STMicroelectronics. 33 | + */ 34 | + 35 | +/* For more information on Device Tree configuration, please refer to 36 | + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 37 | + */ 38 | + 39 | +/dts-v1/; 40 | +#include 41 | + 42 | +#include "stm32mp157.dtsi" 43 | +#include "stm32mp15xa.dtsi" 44 | +#include "stm32mp15xxaa-pinctrl.dtsi" 45 | +#include "stm32mp15-m4-srm.dtsi" 46 | + 47 | +/* USER CODE BEGIN includes */ 48 | +#include 49 | +#include 50 | +#include 51 | +#include 52 | +/* USER CODE END includes */ 53 | + 54 | +/ { 55 | + model = "STMicroelectronics STM32MP157AAA3 SODIMM module"; 56 | + compatible = "st,stm32mp157a-sodimm2-mx", "st,stm32mp157"; 57 | + 58 | + memory@c0000000 { 59 | + device_type = "memory"; 60 | + reg = <0xc0000000 0x40000000>; 61 | + 62 | + /* USER CODE BEGIN memory */ 63 | + /* USER CODE END memory */ 64 | + }; 65 | + 66 | + reserved-memory { 67 | + #address-cells = <1>; 68 | + #size-cells = <1>; 69 | + ranges; 70 | + 71 | + /* USER CODE BEGIN reserved-memory */ 72 | + 73 | + mcuram2:mcuram2@10000000{ 74 | + compatible = "shared-dma-pool"; 75 | + reg = <0x10000000 0x40000>; 76 | + no-map; 77 | + }; 78 | + 79 | + vdev0vring0:vdev0vring0@10040000{ 80 | + compatible = "shared-dma-pool"; 81 | + reg = <0x10040000 0x1000>; 82 | + no-map; 83 | + }; 84 | + 85 | + vdev0vring1:vdev0vring1@10041000{ 86 | + compatible = "shared-dma-pool"; 87 | + reg = <0x10041000 0x1000>; 88 | + no-map; 89 | + }; 90 | + 91 | + vdev0buffer:vdev0buffer@10042000{ 92 | + compatible = "shared-dma-pool"; 93 | + reg = <0x10042000 0x4000>; 94 | + no-map; 95 | + }; 96 | + 97 | + mcu_rsc_table:mcu_rsc_table@10048000{ 98 | + compatible = "shared-dma-pool"; 99 | + reg = <0x10048000 0x8000>; 100 | + no-map; 101 | + }; 102 | + 103 | + mcuram:mcuram@30000000{ 104 | + compatible = "shared-dma-pool"; 105 | + reg = <0x30000000 0x40000>; 106 | + no-map; 107 | + }; 108 | + 109 | + retram:retram@38000000{ 110 | + compatible = "shared-dma-pool"; 111 | + reg = <0x38000000 0x10000>; 112 | + no-map; 113 | + }; 114 | + 115 | + gpu_reserved:gpu@f6000000{ 116 | + reg = <0xf6000000 0x8000000>; 117 | + no-map; 118 | + }; 119 | + /* USER CODE END reserved-memory */ 120 | + }; 121 | + 122 | + /* USER CODE BEGIN root */ 123 | + 124 | + aliases{ 125 | + serial0 = &uart4; 126 | + ethernet0 = ðernet0; 127 | + spi0 = &qspi; 128 | + display0 = &lcd0; 129 | + //serial1 = &usart3; 130 | + }; 131 | + 132 | + reg_5v_host: reg-5v-host { 133 | + compatible = "regulator-fixed"; 134 | + regulator-name = "5v-host"; 135 | + regulator-min-microvolt = <5000000>; 136 | + regulator-max-microvolt = <5000000>; 137 | + pinctrl-names = "default", "sleep"; 138 | + pinctrl-0 = <&usb_5v_power_pins_mx>; 139 | + pinctrl-1 = <&usb_5v_power_sleep_pins_mx>; 140 | + //gpio = <&gpioi 11 GPIO_ACTIVE_HIGH>; //power USB port 141 | + enable-active-high; 142 | + default-on; 143 | + status = "okay"; 144 | + }; 145 | + 146 | + reg_5v_otg: reg-5v-otg { 147 | + compatible = "regulator-fixed"; 148 | + regulator-name = "5v-otg"; 149 | + regulator-min-microvolt = <5000000>; 150 | + regulator-max-microvolt = <5000000>; 151 | + pinctrl-names = "default", "sleep"; 152 | + pinctrl-0 = <&usb_otg_5v_power_pins_mx>; 153 | + pinctrl-1 = <&usb_otg_5v_power_sleep_pins_mx>; 154 | + //gpio = <&gpioc 13 GPIO_ACTIVE_HIGH>; //power for second port 155 | + enable-active-high; 156 | + default-on; 157 | + status = "okay"; 158 | + }; 159 | + 160 | + reg_3v3_rgb: regulator-3v3-rgb { 161 | + compatible = "regulator-fixed"; 162 | + regulator-name = "3v3-rgb"; 163 | + regulator-min-microvolt = <3300000>; 164 | + regulator-max-microvolt = <3300000>; 165 | + gpio = <&gpiog 2 GPIO_ACTIVE_HIGH>; 166 | + enable-active-high; 167 | + status = "okay"; 168 | + }; 169 | + 170 | + rgb_panel_backlight: rgb-panel-backlight { 171 | + compatible = "gpio-backlight"; 172 | + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; 173 | + enable-active-high; 174 | + default-off; 175 | + linux,default-trigger = "backlight"; 176 | + status = "okay"; 177 | + }; 178 | + 179 | + lcd0: display { 180 | + compatible = "out4,o4-lcd5-800-480", "panel-dpi"; 181 | + label = "display"; 182 | + power-supply = <®_3v3_rgb>; 183 | + backlight = <&rgb_panel_backlight>; 184 | + //bits-per-pixel = <32>; 185 | + //bus-width = <24>; 186 | + //connector-type = <17>; 187 | + 188 | + status = "okay"; 189 | + 190 | + port { 191 | + dsi_in: endpoint { 192 | + remote-endpoint = <<dc_ep0_out>; 193 | + }; 194 | + }; 195 | + 196 | + // panel-timing { 197 | + // clock-frequency = <33000000>; 198 | + // hactive = <800>; 199 | + // vactive = <480>; 200 | + // hfront-porch = <40>; 201 | + // hback-porch = <40>; 202 | + // hsync-len = <43>; 203 | + // vback-porch = <29>; 204 | + // vfront-porch = <13>; 205 | + // vsync-len = <3>; 206 | + // hsync-active = <0>; 207 | + // vsync-active = <0>; 208 | + // de-active = <1>; 209 | + // pixelclk-active = <1>; 210 | + // }; 211 | + 212 | + }; 213 | + 214 | + led { 215 | + compatible = "gpio-leds"; 216 | + status = "okay"; 217 | + 218 | + // for test external i2c GPIO expander 219 | + green1 { 220 | + label = "heartbeat"; 221 | + gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>; 222 | + linux,default-trigger = "heartbeat"; 223 | + default-state = "on"; 224 | + }; 225 | + 226 | + // for test external i2c GPIO expander 227 | + green2 { 228 | + label = "network"; 229 | + gpios = <&pcf8574a 7 GPIO_ACTIVE_LOW>; 230 | + linux,default-trigger = "netdev"; 231 | + default-state = "on"; 232 | + }; 233 | + }; 234 | + 235 | + vin:vin{ 236 | + compatible = "regulator-fixed"; 237 | + regulator-name = "vin"; 238 | + regulator-min-microvolt = <5000000>; 239 | + regulator-max-microvolt = <5000000>; 240 | + regulator-always-on; 241 | + }; 242 | + 243 | + chosen{ 244 | + stdout-path = "serial0:115200n8"; 245 | + }; 246 | + 247 | + 248 | + usb_phy_tuning:usb-phy-tuning{ 249 | + st,hs-dc-level = <2>; 250 | + st,fs-rftime-tuning; 251 | + st,hs-rftime-reduction; 252 | + st,hs-current-trim = <15>; 253 | + st,hs-impedance-trim = <1>; 254 | + st,squelch-level = <3>; 255 | + st,hs-rx-offset = <2>; 256 | + st,no-lsfs-sc; 257 | + }; 258 | + /* USER CODE END root */ 259 | + 260 | + clocks { 261 | + /* USER CODE BEGIN clocks */ 262 | + 263 | + clk_ext_camera:clk-ext-camera{ 264 | + #clock-cells = <0>; 265 | + compatible = "fixed-clock"; 266 | + clock-frequency = <24000000>; 267 | + }; 268 | + /* USER CODE END clocks */ 269 | + 270 | +#ifndef CONFIG_TFABOOT 271 | + clk_lsi: clk-lsi { 272 | + clock-frequency = <32000>; 273 | + }; 274 | + clk_hsi: clk-hsi { 275 | + clock-frequency = <64000000>; 276 | + }; 277 | + clk_csi: clk-csi { 278 | + clock-frequency = <4000000>; 279 | + }; 280 | + clk_lse: clk-lse { 281 | + clock-frequency = <32768>; 282 | + }; 283 | + clk_hse: clk-hse { 284 | + clock-frequency = <24000000>; 285 | + }; 286 | +#endif /*CONFIG_TFABOOT*/ 287 | + }; 288 | + 289 | +}; /*root*/ 290 | + 291 | +&pinctrl { 292 | + u-boot,dm-pre-reloc; 293 | + 294 | + dcmi_pins_mx: dcmi_mx-0 { 295 | + pins { 296 | + pinmux = , /* DCMI_PIXCLK */ 297 | + , /* DCMI_VSYNC */ 298 | + , /* DCMI_D6 */ 299 | + , /* DCMI_D7 */ 300 | + , /* DCMI_HSYNC */ 301 | + , /* DCMI_D0 */ 302 | + , /* DCMI_D1 */ 303 | + , /* DCMI_D2 */ 304 | + , /* DCMI_D3 */ 305 | + , /* DCMI_D4 */ 306 | + ; /* DCMI_D5 */ 307 | + bias-disable; 308 | + }; 309 | + }; 310 | + 311 | + dcmi_sleep_pins_mx: dcmi_sleep_mx-0 { 312 | + pins { 313 | + pinmux = , /* DCMI_PIXCLK */ 314 | + , /* DCMI_VSYNC */ 315 | + , /* DCMI_D6 */ 316 | + , /* DCMI_D7 */ 317 | + , /* DCMI_HSYNC */ 318 | + , /* DCMI_D0 */ 319 | + , /* DCMI_D1 */ 320 | + , /* DCMI_D2 */ 321 | + , /* DCMI_D3 */ 322 | + , /* DCMI_D4 */ 323 | + ; /* DCMI_D5 */ 324 | + }; 325 | + }; 326 | + 327 | + eth1_pins_mx: eth1_mx-0 { 328 | + pins1 { 329 | + pinmux = , /* ETH1_RX_CLK */ 330 | + , /* ETH1_RX_CTL */ 331 | + , /* ETH1_RXD2 */ 332 | + , /* ETH1_RXD3 */ 333 | + , /* ETH1_RXD0 */ 334 | + ; /* ETH1_RXD1 */ 335 | + bias-disable; 336 | + }; 337 | + pins2 { 338 | + pinmux = ; /* ETH1_MDIO */ 339 | + bias-disable; 340 | + drive-push-pull; 341 | + slew-rate = <0>; 342 | + }; 343 | + pins3 { 344 | + pinmux = , /* ETH1_TX_CTL */ 345 | + , /* ETH1_MDC */ 346 | + , /* ETH1_TXD2 */ 347 | + , /* ETH1_TXD3 */ 348 | + , /* ETH1_GTX_CLK */ 349 | + , /* ETH1_CLK125 */ 350 | + , /* ETH1_TXD0 */ 351 | + ; /* ETH1_TXD1 */ 352 | + bias-disable; 353 | + drive-push-pull; 354 | + slew-rate = <2>; 355 | + }; 356 | + }; 357 | + 358 | + eth1_sleep_pins_mx: eth1_sleep_mx-0 { 359 | + pins { 360 | + pinmux = , /* ETH1_RX_CLK */ 361 | + , /* ETH1_MDIO */ 362 | + , /* ETH1_RX_CTL */ 363 | + , /* ETH1_RXD2 */ 364 | + , /* ETH1_RXD3 */ 365 | + , /* ETH1_TX_CTL */ 366 | + , /* ETH1_MDC */ 367 | + , /* ETH1_TXD2 */ 368 | + , /* ETH1_RXD0 */ 369 | + , /* ETH1_RXD1 */ 370 | + , /* ETH1_TXD3 */ 371 | + , /* ETH1_GTX_CLK */ 372 | + , /* ETH1_CLK125 */ 373 | + , /* ETH1_TXD0 */ 374 | + ; /* ETH1_TXD1 */ 375 | + }; 376 | + }; 377 | + 378 | + fdcan1_pins_mx: fdcan1_mx-0 { 379 | + pins1 { 380 | + pinmux = ; /* FDCAN1_TX */ 381 | + bias-pull-up; 382 | + drive-push-pull; 383 | + slew-rate = <0>; 384 | + }; 385 | + pins2 { 386 | + pinmux = ; /* FDCAN1_RX */ 387 | + bias-pull-up; 388 | + }; 389 | + }; 390 | + 391 | + fdcan1_sleep_pins_mx: fdcan1_sleep_mx-0 { 392 | + pins { 393 | + pinmux = , /* FDCAN1_TX */ 394 | + ; /* FDCAN1_RX */ 395 | + }; 396 | + }; 397 | + 398 | + fdcan2_pins_mx: fdcan2_mx-0 { 399 | + pins1 { 400 | + pinmux = ; /* FDCAN2_TX */ 401 | + bias-pull-up; 402 | + drive-push-pull; 403 | + slew-rate = <0>; 404 | + }; 405 | + pins2 { 406 | + pinmux = ; /* FDCAN2_RX */ 407 | + bias-pull-up; 408 | + }; 409 | + }; 410 | + 411 | + fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 { 412 | + pins { 413 | + pinmux = , /* FDCAN2_RX */ 414 | + ; /* FDCAN2_TX */ 415 | + }; 416 | + }; 417 | + 418 | + i2c2_pins_mx: i2c2_mx-0 { 419 | + pins { 420 | + pinmux = , /* I2C2_SCL */ 421 | + ; /* I2C2_SDA */ 422 | + bias-disable; 423 | + drive-open-drain; 424 | + slew-rate = <0>; 425 | + }; 426 | + }; 427 | + 428 | + i2c2_sleep_pins_mx: i2c2_sleep_mx-0 { 429 | + pins { 430 | + pinmux = , /* I2C2_SCL */ 431 | + ; /* I2C2_SDA */ 432 | + }; 433 | + }; 434 | + 435 | + i2c5_pins_mx: i2c5_mx-0 { 436 | + pins { 437 | + pinmux = , /* I2C5_SDA */ 438 | + ; /* I2C5_SCL */ 439 | + bias-disable; 440 | + drive-open-drain; 441 | + slew-rate = <0>; 442 | + }; 443 | + }; 444 | + 445 | + i2c5_sleep_pins_mx: i2c5_sleep_mx-0 { 446 | + pins { 447 | + pinmux = , /* I2C5_SDA */ 448 | + ; /* I2C5_SCL */ 449 | + }; 450 | + }; 451 | + 452 | + ltdc_pins_mx: ltdc_mx-0 { 453 | + pins1 { 454 | + pinmux = , /* LTDC_HSYNC */ 455 | + , /* LTDC_VSYNC */ 456 | + , /* LTDC_R0 */ 457 | + , /* LTDC_R1 */ 458 | + , /* LTDC_R2 */ 459 | + , /* LTDC_R3 */ 460 | + , /* LTDC_R4 */ 461 | + , /* LTDC_R5 */ 462 | + , /* LTDC_R6 */ 463 | + , /* LTDC_R7 */ 464 | + , /* LTDC_G0 */ 465 | + , /* LTDC_G1 */ 466 | + , /* LTDC_G2 */ 467 | + , /* LTDC_G3 */ 468 | + , /* LTDC_G4 */ 469 | + , /* LTDC_B0 */ 470 | + , /* LTDC_B1 */ 471 | + , /* LTDC_B2 */ 472 | + , /* LTDC_B3 */ 473 | + , /* LTDC_G5 */ 474 | + , /* LTDC_G6 */ 475 | + , /* LTDC_G7 */ 476 | + , /* LTDC_B4 */ 477 | + , /* LTDC_B5 */ 478 | + , /* LTDC_B6 */ 479 | + , /* LTDC_B7 */ 480 | + ; /* LTDC_DE */ 481 | + bias-disable; 482 | + drive-push-pull; 483 | + slew-rate = <0>; 484 | + }; 485 | + pins2 { 486 | + pinmux = ; /* LTDC_CLK */ 487 | + bias-disable; 488 | + drive-push-pull; 489 | + slew-rate = <1>; 490 | + }; 491 | + }; 492 | + 493 | + ltdc_sleep_pins_mx: ltdc_sleep_mx-0 { 494 | + pins { 495 | + pinmux = , /* LTDC_HSYNC */ 496 | + , /* LTDC_VSYNC */ 497 | + , /* LTDC_CLK */ 498 | + , /* LTDC_R0 */ 499 | + , /* LTDC_R1 */ 500 | + , /* LTDC_R2 */ 501 | + , /* LTDC_R3 */ 502 | + , /* LTDC_R4 */ 503 | + , /* LTDC_R5 */ 504 | + , /* LTDC_R6 */ 505 | + , /* LTDC_R7 */ 506 | + , /* LTDC_G0 */ 507 | + , /* LTDC_G1 */ 508 | + , /* LTDC_G2 */ 509 | + , /* LTDC_G3 */ 510 | + , /* LTDC_G4 */ 511 | + , /* LTDC_B0 */ 512 | + , /* LTDC_B1 */ 513 | + , /* LTDC_B2 */ 514 | + , /* LTDC_B3 */ 515 | + , /* LTDC_G5 */ 516 | + , /* LTDC_G6 */ 517 | + , /* LTDC_G7 */ 518 | + , /* LTDC_B4 */ 519 | + , /* LTDC_B5 */ 520 | + , /* LTDC_B6 */ 521 | + , /* LTDC_B7 */ 522 | + ; /* LTDC_DE */ 523 | + }; 524 | + }; 525 | + 526 | + quadspi_pins_mx: quadspi_mx-0 { 527 | + u-boot,dm-pre-reloc; 528 | + pins1 { 529 | + u-boot,dm-pre-reloc; 530 | + pinmux = , /* QUADSPI_BK1_NCS */ 531 | + ; /* QUADSPI_BK2_NCS */ 532 | + bias-pull-up; 533 | + drive-push-pull; 534 | + slew-rate = <1>; 535 | + }; 536 | + pins2 { 537 | + u-boot,dm-pre-reloc; 538 | + pinmux = ; /* QUADSPI_CLK */ 539 | + bias-disable; 540 | + drive-push-pull; 541 | + slew-rate = <3>; 542 | + }; 543 | + pins3 { 544 | + u-boot,dm-pre-reloc; 545 | + pinmux = , /* QUADSPI_BK1_IO3 */ 546 | + , /* QUADSPI_BK1_IO2 */ 547 | + , /* QUADSPI_BK1_IO0 */ 548 | + , /* QUADSPI_BK1_IO1 */ 549 | + , /* QUADSPI_BK2_IO3 */ 550 | + , /* QUADSPI_BK2_IO2 */ 551 | + , /* QUADSPI_BK2_IO0 */ 552 | + ; /* QUADSPI_BK2_IO1 */ 553 | + bias-disable; 554 | + drive-push-pull; 555 | + slew-rate = <1>; 556 | + }; 557 | + }; 558 | + 559 | + quadspi_sleep_pins_mx: quadspi_sleep_mx-0 { 560 | + u-boot,dm-pre-reloc; 561 | + pins { 562 | + u-boot,dm-pre-reloc; 563 | + pinmux = , /* QUADSPI_BK1_NCS */ 564 | + , /* QUADSPI_BK2_NCS */ 565 | + , /* QUADSPI_BK1_IO3 */ 566 | + , /* QUADSPI_BK1_IO2 */ 567 | + , /* QUADSPI_BK1_IO0 */ 568 | + , /* QUADSPI_BK1_IO1 */ 569 | + , /* QUADSPI_CLK */ 570 | + , /* QUADSPI_BK2_IO3 */ 571 | + , /* QUADSPI_BK2_IO2 */ 572 | + , /* QUADSPI_BK2_IO0 */ 573 | + ; /* QUADSPI_BK2_IO1 */ 574 | + }; 575 | + }; 576 | + 577 | + sdmmc1_pins_mx: sdmmc1_mx-0 { 578 | + u-boot,dm-pre-reloc; 579 | + pins1 { 580 | + u-boot,dm-pre-reloc; 581 | + pinmux = , /* SDMMC1_D0 */ 582 | + , /* SDMMC1_D1 */ 583 | + , /* SDMMC1_D2 */ 584 | + , /* SDMMC1_D3 */ 585 | + ; /* SDMMC1_CMD */ 586 | + bias-pull-up; 587 | + drive-push-pull; 588 | + slew-rate = <1>; 589 | + }; 590 | + pins2 { 591 | + u-boot,dm-pre-reloc; 592 | + pinmux = ; /* SDMMC1_CK */ 593 | + bias-pull-up; 594 | + drive-push-pull; 595 | + slew-rate = <2>; 596 | + }; 597 | + }; 598 | + 599 | + sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { 600 | + u-boot,dm-pre-reloc; 601 | + pins1 { 602 | + u-boot,dm-pre-reloc; 603 | + pinmux = , /* SDMMC1_D0 */ 604 | + , /* SDMMC1_D1 */ 605 | + , /* SDMMC1_D2 */ 606 | + ; /* SDMMC1_D3 */ 607 | + bias-pull-up; 608 | + drive-push-pull; 609 | + slew-rate = <1>; 610 | + }; 611 | + pins2 { 612 | + u-boot,dm-pre-reloc; 613 | + pinmux = ; /* SDMMC1_CK */ 614 | + bias-pull-up; 615 | + drive-push-pull; 616 | + slew-rate = <2>; 617 | + }; 618 | + pins3 { 619 | + u-boot,dm-pre-reloc; 620 | + pinmux = ; /* SDMMC1_CMD */ 621 | + bias-pull-up; 622 | + drive-open-drain; 623 | + slew-rate = <1>; 624 | + }; 625 | + }; 626 | + 627 | + sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { 628 | + u-boot,dm-pre-reloc; 629 | + pins { 630 | + u-boot,dm-pre-reloc; 631 | + pinmux = , /* SDMMC1_D0 */ 632 | + , /* SDMMC1_D1 */ 633 | + , /* SDMMC1_D2 */ 634 | + , /* SDMMC1_D3 */ 635 | + , /* SDMMC1_CK */ 636 | + ; /* SDMMC1_CMD */ 637 | + }; 638 | + }; 639 | + 640 | + sdmmc2_pins_mx: sdmmc2_mx-0 { 641 | + u-boot,dm-pre-reloc; 642 | + pins1 { 643 | + u-boot,dm-pre-reloc; 644 | + pinmux = , /* SDMMC2_D4 */ 645 | + , /* SDMMC2_D5 */ 646 | + , /* SDMMC2_D2 */ 647 | + , /* SDMMC2_D3 */ 648 | + , /* SDMMC2_D0 */ 649 | + , /* SDMMC2_D1 */ 650 | + , /* SDMMC2_D7 */ 651 | + , /* SDMMC2_D6 */ 652 | + ; /* SDMMC2_CMD */ 653 | + bias-pull-up; 654 | + drive-push-pull; 655 | + slew-rate = <1>; 656 | + }; 657 | + pins2 { 658 | + u-boot,dm-pre-reloc; 659 | + pinmux = ; /* SDMMC2_CK */ 660 | + bias-pull-up; 661 | + drive-push-pull; 662 | + slew-rate = <2>; 663 | + }; 664 | + }; 665 | + 666 | + sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { 667 | + u-boot,dm-pre-reloc; 668 | + pins1 { 669 | + u-boot,dm-pre-reloc; 670 | + pinmux = , /* SDMMC2_D4 */ 671 | + , /* SDMMC2_D5 */ 672 | + , /* SDMMC2_D2 */ 673 | + , /* SDMMC2_D3 */ 674 | + , /* SDMMC2_D0 */ 675 | + , /* SDMMC2_D1 */ 676 | + , /* SDMMC2_D7 */ 677 | + ; /* SDMMC2_D6 */ 678 | + bias-pull-up; 679 | + drive-push-pull; 680 | + slew-rate = <1>; 681 | + }; 682 | + pins2 { 683 | + u-boot,dm-pre-reloc; 684 | + pinmux = ; /* SDMMC2_CK */ 685 | + bias-pull-up; 686 | + drive-push-pull; 687 | + slew-rate = <2>; 688 | + }; 689 | + pins3 { 690 | + u-boot,dm-pre-reloc; 691 | + pinmux = ; /* SDMMC2_CMD */ 692 | + bias-pull-up; 693 | + drive-open-drain; 694 | + slew-rate = <1>; 695 | + }; 696 | + }; 697 | + 698 | + sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { 699 | + u-boot,dm-pre-reloc; 700 | + pins { 701 | + u-boot,dm-pre-reloc; 702 | + pinmux = , /* SDMMC2_D4 */ 703 | + , /* SDMMC2_D5 */ 704 | + , /* SDMMC2_D2 */ 705 | + , /* SDMMC2_D3 */ 706 | + , /* SDMMC2_D0 */ 707 | + , /* SDMMC2_D1 */ 708 | + , /* SDMMC2_D7 */ 709 | + , /* SDMMC2_CK */ 710 | + , /* SDMMC2_D6 */ 711 | + ; /* SDMMC2_CMD */ 712 | + }; 713 | + }; 714 | + 715 | + uart4_pins_mx: uart4_mx-0 { 716 | + u-boot,dm-pre-reloc; 717 | + pins1 { 718 | + u-boot,dm-pre-reloc; 719 | + pinmux = ; /* UART4_RX */ 720 | + bias-disable; 721 | + }; 722 | + pins2 { 723 | + u-boot,dm-pre-reloc; 724 | + pinmux = ; /* UART4_TX */ 725 | + bias-disable; 726 | + drive-push-pull; 727 | + slew-rate = <0>; 728 | + }; 729 | + }; 730 | + 731 | + uart4_sleep_pins_mx: uart4_sleep_mx-0 { 732 | + u-boot,dm-pre-reloc; 733 | + pins { 734 | + u-boot,dm-pre-reloc; 735 | + pinmux = , /* UART4_RX */ 736 | + ; /* UART4_TX */ 737 | + }; 738 | + }; 739 | + 740 | + usb_otg_hs_pins_mx: usb_otg_hs_mx-0 { 741 | + u-boot,dm-pre-reloc; 742 | + pins { 743 | + u-boot,dm-pre-reloc; 744 | + pinmux = ; /* USB_OTG_HS_ID */ 745 | + }; 746 | + }; 747 | + 748 | + usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 { 749 | + u-boot,dm-pre-reloc; 750 | + pins { 751 | + u-boot,dm-pre-reloc; 752 | + pinmux = ; /* USB_OTG_HS_ID */ 753 | + }; 754 | + }; 755 | + 756 | + /* USER CODE BEGIN pinctrl */ 757 | + usb_5v_power_pins_mx: usb_5v_power_mx-0 { 758 | + u-boot,dm-pre-reloc; 759 | + pins { 760 | + u-boot,dm-pre-reloc; 761 | + pinmux = , /* USB_POWER_EN */ 762 | + ; /* USB_POWER_EN */ 763 | + bias-disable; 764 | + output-high; 765 | + }; 766 | + }; 767 | + 768 | + usb_5v_power_sleep_pins_mx: usb_5v_power_sleep_mx-0 { 769 | + u-boot,dm-pre-reloc; 770 | + pins { 771 | + u-boot,dm-pre-reloc; 772 | + pinmux = , /* USB_POWER_EN */ 773 | + ; /* USB_POWER_EN */ 774 | + bias-disable; 775 | + output-low; 776 | + }; 777 | + }; 778 | + 779 | + usb_otg_5v_power_pins_mx: usb_otg_5v_power_mx-0 { 780 | + u-boot,dm-pre-reloc; 781 | + pins { 782 | + u-boot,dm-pre-reloc; 783 | + pinmux = ; /* USB_POWER_EN */ 784 | + bias-disable; 785 | + output-high; 786 | + }; 787 | + }; 788 | + 789 | + usb_otg_5v_power_sleep_pins_mx: usb_otg_5v_power_sleep_mx-0 { 790 | + u-boot,dm-pre-reloc; 791 | + pins { 792 | + u-boot,dm-pre-reloc; 793 | + pinmux = ; /* USB_POWER_EN */ 794 | + bias-disable; 795 | + output-low; 796 | + }; 797 | + }; 798 | + 799 | + /* USER CODE END pinctrl */ 800 | +}; 801 | + 802 | +&pinctrl_z { 803 | + u-boot,dm-pre-reloc; 804 | + 805 | + i2c4_pins_z_mx: i2c4_mx-0 { 806 | + u-boot,dm-pre-reloc; 807 | + pins { 808 | + u-boot,dm-pre-reloc; 809 | + pinmux = , /* I2C4_SCL */ 810 | + ; /* I2C4_SDA */ 811 | + bias-disable; 812 | + drive-open-drain; 813 | + slew-rate = <0>; 814 | + }; 815 | + }; 816 | + 817 | + i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { 818 | + u-boot,dm-pre-reloc; 819 | + pins { 820 | + u-boot,dm-pre-reloc; 821 | + pinmux = , /* I2C4_SCL */ 822 | + ; /* I2C4_SDA */ 823 | + }; 824 | + }; 825 | + 826 | + /* USER CODE BEGIN pinctrl_z */ 827 | + /* USER CODE END pinctrl_z */ 828 | +}; 829 | + 830 | +&m4_rproc{ 831 | + /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/ 832 | + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; 833 | + mbox-names = "vq0", "vq1", "shutdown"; 834 | + status = "okay"; 835 | + 836 | + /* USER CODE BEGIN m4_rproc */ 837 | + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, 838 | + <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>; 839 | + interrupt-parent = <&exti>; 840 | + interrupts = <68 1>; 841 | + wakeup-source; 842 | + /* USER CODE END m4_rproc */ 843 | +}; 844 | + 845 | +&adc{ 846 | + status = "okay"; 847 | + 848 | + /* USER CODE BEGIN adc */ 849 | + /* USER CODE END adc */ 850 | +}; 851 | + 852 | +&bsec{ 853 | + status = "okay"; 854 | + 855 | + /* USER CODE BEGIN bsec */ 856 | + /* USER CODE END bsec */ 857 | +}; 858 | + 859 | +&crc1{ 860 | + status = "okay"; 861 | + 862 | + /* USER CODE BEGIN crc1 */ 863 | + /* USER CODE END crc1 */ 864 | +}; 865 | + 866 | +&dcmi{ 867 | + pinctrl-names = "default", "sleep"; 868 | + pinctrl-0 = <&dcmi_pins_mx>; 869 | + pinctrl-1 = <&dcmi_sleep_pins_mx>; 870 | + status = "okay"; 871 | + 872 | + /* USER CODE BEGIN dcmi */ 873 | + 874 | + port{ 875 | + 876 | + dcmi_0:endpoint{ 877 | + remote-endpoint = <&ov5640_0>; 878 | + bus-type = <5>; 879 | + bus-width = <8>; 880 | + hsync-active = <0>; 881 | + vsync-active = <0>; 882 | + pclk-sample = <1>; 883 | + pclk-max-frequency = <77000000>; 884 | + }; 885 | + }; 886 | + /* USER CODE END dcmi */ 887 | +}; 888 | + 889 | +&dma1{ 890 | + status = "okay"; 891 | + 892 | + /* USER CODE BEGIN dma1 */ 893 | + sram = <&dma_pool>; 894 | + /* USER CODE END dma1 */ 895 | +}; 896 | + 897 | +&dma2{ 898 | + status = "okay"; 899 | + 900 | + /* USER CODE BEGIN dma2 */ 901 | + sram = <&dma_pool>; 902 | + /* USER CODE END dma2 */ 903 | +}; 904 | + 905 | +&dmamux1{ 906 | + status = "okay"; 907 | + 908 | + dma-masters = <&dma1 &dma2>; 909 | + dma-channels = <16>; 910 | + 911 | + /* USER CODE BEGIN dmamux1 */ 912 | + /* USER CODE END dmamux1 */ 913 | +}; 914 | + 915 | +&dts{ 916 | + status = "okay"; 917 | + 918 | + /* USER CODE BEGIN dts */ 919 | + /* USER CODE END dts */ 920 | +}; 921 | + 922 | +ðernet0{ 923 | + pinctrl-names = "default", "sleep"; 924 | + pinctrl-0 = <ð1_pins_mx>; 925 | + pinctrl-1 = <ð1_sleep_pins_mx>; 926 | + status = "okay"; 927 | + 928 | + /* USER CODE BEGIN ethernet0 */ 929 | + phy-mode = "rgmii-id"; 930 | + max-speed = <1000>; 931 | + phy-handle = <&phy0>; 932 | + nvmem-cells = <ðernet_mac_address>; 933 | + nvmem-cell-names = "mac-address"; 934 | + 935 | + mdio0{ 936 | + #address-cells = <1>; 937 | + #size-cells = <0>; 938 | + compatible = "snps,dwmac-mdio"; 939 | + 940 | + phy0:ethernet-phy@0{ 941 | + reg = <0>; 942 | + }; 943 | + }; 944 | + /* USER CODE END ethernet0 */ 945 | +}; 946 | + 947 | +&gpu{ 948 | + status = "okay"; 949 | + 950 | + /* USER CODE BEGIN gpu */ 951 | + contiguous-area = <&gpu_reserved>; 952 | + /* USER CODE END gpu */ 953 | +}; 954 | + 955 | +&hash1{ 956 | + u-boot,dm-pre-reloc; 957 | + status = "okay"; 958 | + 959 | + /* USER CODE BEGIN hash1 */ 960 | + /* USER CODE END hash1 */ 961 | +}; 962 | + 963 | +&hsem{ 964 | + status = "okay"; 965 | + 966 | + /* USER CODE BEGIN hsem */ 967 | + /* USER CODE END hsem */ 968 | +}; 969 | + 970 | +&i2c2{ 971 | + pinctrl-names = "default", "sleep"; 972 | + pinctrl-0 = <&i2c2_pins_mx>; 973 | + pinctrl-1 = <&i2c2_sleep_pins_mx>; 974 | + status = "okay"; 975 | + 976 | + /* USER CODE BEGIN i2c2 */ 977 | + i2c-scl-rising-time-ns = <185>; 978 | + i2c-scl-falling-time-ns = <20>; 979 | + /delete-property/ dmas; 980 | + /delete-property/ dma-names; 981 | + 982 | + 983 | + ov5640:camera@3c{ 984 | + compatible = "ovti,ov5640"; 985 | + reg = <0x3c>; 986 | + clocks = <&clk_ext_camera>; 987 | + clock-names = "xclk"; 988 | + DOVDD-supply = <&v2v8>; 989 | + powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; 990 | + reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; 991 | + rotation = <180>; 992 | + status = "okay"; 993 | + 994 | + port{ 995 | + 996 | + ov5640_0:endpoint{ 997 | + remote-endpoint = <&dcmi_0>; 998 | + bus-width = <8>; 999 | + data-shift = <2>; 1000 | + hsync-active = <0>; 1001 | + vsync-active = <0>; 1002 | + pclk-sample = <1>; 1003 | + pclk-max-frequency = <77000000>; 1004 | + }; 1005 | + }; 1006 | + }; 1007 | + 1008 | + stmfx:stmfx@42{ 1009 | + compatible = "st,stmfx-0300"; 1010 | + reg = <0x42>; 1011 | + interrupts = <8 IRQ_TYPE_EDGE_RISING>; 1012 | + interrupt-parent = <&gpioi>; 1013 | + vdd-supply = <&v3v3>; 1014 | + 1015 | + stmfx_pinctrl:pinctrl{ 1016 | + compatible = "st,stmfx-0300-pinctrl"; 1017 | + gpio-controller; 1018 | + #gpio-cells = <2>; 1019 | + interrupt-controller; 1020 | + #interrupt-cells = <2>; 1021 | + gpio-ranges = <&stmfx_pinctrl 0 0 24>; 1022 | + 1023 | + goodix_pins:goodix{ 1024 | + pins = "gpio14"; 1025 | + bias-pull-down; 1026 | + }; 1027 | + 1028 | + }; 1029 | + }; 1030 | + 1031 | + /* 1032 | + gt9147:goodix_ts@5d{ 1033 | + compatible = "goodix,gt9147"; 1034 | + reg = <0x5d>; 1035 | + panel = <&panel_dsi>; 1036 | + pinctrl-0 = <&goodix_pins>; 1037 | + pinctrl-names = "default"; 1038 | + status = "okay"; 1039 | + interrupts = <14 IRQ_TYPE_EDGE_RISING>; 1040 | + interrupt-parent = <&stmfx_pinctrl>; 1041 | + }; 1042 | + */ 1043 | + gt911_rgb: touchscreen@14 { 1044 | + compatible = "goodix,gt911"; 1045 | + //reg = <0x5d>; 1046 | + reg = <0x14>; 1047 | + interrupt-parent = <&gpiog>; 1048 | + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 1049 | + irq-flags = ; 1050 | + irq-gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; 1051 | + reset-gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; 1052 | + panel = <&lcd0>; 1053 | + status = "okay"; 1054 | + }; 1055 | + 1056 | + pcf8574a: gpio@38 { 1057 | + compatible = "nxp,pcf8574a"; 1058 | + reg = <0x38>; 1059 | + gpio-controller; 1060 | + #gpio-cells = <2>; 1061 | + lines-initial-states = <0>; 1062 | + status = "okay"; 1063 | + }; 1064 | + 1065 | + pcf8574a_ext: gpio@3f { 1066 | + compatible = "nxp,pcf8574a"; 1067 | + reg = <0x3f>; 1068 | + gpio-controller; 1069 | + #gpio-cells = <2>; 1070 | + lines-initial-states = <0>; 1071 | + status = "okay"; 1072 | + }; 1073 | + /* USER CODE END i2c2 */ 1074 | +}; 1075 | + 1076 | +&i2c4{ 1077 | + u-boot,dm-pre-reloc; 1078 | + pinctrl-names = "default", "sleep"; 1079 | + pinctrl-0 = <&i2c4_pins_z_mx>; 1080 | + pinctrl-1 = <&i2c4_sleep_pins_z_mx>; 1081 | + status = "okay"; 1082 | + 1083 | + /* USER CODE BEGIN i2c4 */ 1084 | + i2c-scl-rising-time-ns = <185>; 1085 | + i2c-scl-falling-time-ns = <20>; 1086 | + clock-frequency = <400000>; 1087 | + /delete-property/ dmas; 1088 | + /delete-property/ dma-names; 1089 | + 1090 | + pmic:stpmic@33{ 1091 | + compatible = "st,stpmic1"; 1092 | + reg = <0x33>; 1093 | + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 1094 | + interrupt-controller; 1095 | + #interrupt-cells = <2>; 1096 | + status = "okay"; 1097 | + 1098 | + regulators{ 1099 | + compatible = "st,stpmic1-regulators"; 1100 | + buck1-supply = <&vin>; 1101 | + buck2-supply = <&vin>; 1102 | + buck3-supply = <&vin>; 1103 | + buck4-supply = <&vin>; 1104 | + ldo1-supply = <&v3v3>; 1105 | + ldo2-supply = <&v3v3>; 1106 | + ldo3-supply = <&vdd_ddr>; 1107 | + ldo4-supply = <&vin>; 1108 | + ldo5-supply = <&v3v3>; 1109 | + ldo6-supply = <&v3v3>; 1110 | + vref_ddr-supply = <&vin>; 1111 | + boost-supply = <&vin>; 1112 | + pwr_sw1-supply = <&bst_out>; 1113 | + pwr_sw2-supply = <&bst_out>; 1114 | + 1115 | + vddcore:buck1{ 1116 | + regulator-name = "vddcore"; 1117 | + regulator-min-microvolt = <1200000>; 1118 | + regulator-max-microvolt = <1350000>; 1119 | + regulator-always-on; 1120 | + regulator-initial-mode = <0>; 1121 | + regulator-over-current-protection; 1122 | + }; 1123 | + 1124 | + vdd_ddr:buck2{ 1125 | + regulator-name = "vdd_ddr"; 1126 | + regulator-min-microvolt = <1350000>; 1127 | + regulator-max-microvolt = <1350000>; 1128 | + regulator-always-on; 1129 | + regulator-initial-mode = <0>; 1130 | + regulator-over-current-protection; 1131 | + }; 1132 | + 1133 | + vdd:buck3{ 1134 | + regulator-name = "vdd"; 1135 | + regulator-min-microvolt = <3300000>; 1136 | + regulator-max-microvolt = <3300000>; 1137 | + regulator-always-on; 1138 | + st,mask-reset; 1139 | + regulator-initial-mode = <0>; 1140 | + regulator-over-current-protection; 1141 | + }; 1142 | + 1143 | + v3v3:buck4{ 1144 | + regulator-name = "v3v3"; 1145 | + regulator-min-microvolt = <3300000>; 1146 | + regulator-max-microvolt = <3300000>; 1147 | + regulator-always-on; 1148 | + regulator-over-current-protection; 1149 | + regulator-initial-mode = <0>; 1150 | + }; 1151 | + 1152 | + vdda:ldo1{ 1153 | + regulator-name = "vdda"; 1154 | + regulator-min-microvolt = <2900000>; 1155 | + regulator-max-microvolt = <2900000>; 1156 | + interrupts = ; 1157 | + }; 1158 | + 1159 | + v2v8:ldo2{ 1160 | + regulator-name = "v2v8"; 1161 | + regulator-min-microvolt = <2800000>; 1162 | + regulator-max-microvolt = <2800000>; 1163 | + interrupts = ; 1164 | + }; 1165 | + 1166 | + vtt_ddr:ldo3{ 1167 | + regulator-name = "vtt_ddr"; 1168 | + regulator-min-microvolt = <500000>; 1169 | + regulator-max-microvolt = <750000>; 1170 | + regulator-always-on; 1171 | + regulator-over-current-protection; 1172 | + }; 1173 | + 1174 | + vdd_usb:ldo4{ 1175 | + regulator-name = "vdd_usb"; 1176 | + regulator-min-microvolt = <3300000>; 1177 | + regulator-max-microvolt = <3300000>; 1178 | + interrupts = ; 1179 | + }; 1180 | + 1181 | + vdd_sd:ldo5{ 1182 | + regulator-name = "vdd_sd"; 1183 | + regulator-min-microvolt = <2900000>; 1184 | + regulator-max-microvolt = <2900000>; 1185 | + interrupts = ; 1186 | + regulator-boot-on; 1187 | + }; 1188 | + 1189 | + v1v8:ldo6{ 1190 | + regulator-name = "v1v8"; 1191 | + regulator-min-microvolt = <1800000>; 1192 | + regulator-max-microvolt = <1800000>; 1193 | + interrupts = ; 1194 | + regulator-enable-ramp-delay = <300000>; 1195 | + }; 1196 | + 1197 | + vref_ddr:vref_ddr{ 1198 | + regulator-name = "vref_ddr"; 1199 | + regulator-always-on; 1200 | + regulator-over-current-protection; 1201 | + }; 1202 | + 1203 | + bst_out:boost{ 1204 | + regulator-name = "bst_out"; 1205 | + interrupts = ; 1206 | + }; 1207 | + 1208 | + vbus_otg:pwr_sw1{ 1209 | + regulator-name = "vbus_otg"; 1210 | + interrupts = ; 1211 | + }; 1212 | + 1213 | + vbus_sw:pwr_sw2{ 1214 | + regulator-name = "vbus_sw"; 1215 | + interrupts = ; 1216 | + regulator-active-discharge = <1>; 1217 | + }; 1218 | + }; 1219 | + 1220 | + onkey{ 1221 | + compatible = "st,stpmic1-onkey"; 1222 | + interrupts = , ; 1223 | + interrupt-names = "onkey-falling", "onkey-rising"; 1224 | + power-off-time-sec = <10>; 1225 | + status = "okay"; 1226 | + }; 1227 | + 1228 | + watchdog{ 1229 | + compatible = "st,stpmic1-wdt"; 1230 | + status = "disabled"; 1231 | + }; 1232 | + }; 1233 | + /* USER CODE END i2c4 */ 1234 | +}; 1235 | + 1236 | +&i2c5{ 1237 | + pinctrl-names = "default", "sleep"; 1238 | + pinctrl-0 = <&i2c5_pins_mx>; 1239 | + pinctrl-1 = <&i2c5_sleep_pins_mx>; 1240 | + status = "okay"; 1241 | + 1242 | + /* USER CODE BEGIN i2c5 */ 1243 | + i2c-scl-rising-time-ns = <185>; 1244 | + i2c-scl-falling-time-ns = <20>; 1245 | + /delete-property/ dmas; 1246 | + /delete-property/ dma-names; 1247 | + /* USER CODE END i2c5 */ 1248 | +}; 1249 | + 1250 | +&ipcc{ 1251 | + status = "okay"; 1252 | + 1253 | + /* USER CODE BEGIN ipcc */ 1254 | + /* USER CODE END ipcc */ 1255 | +}; 1256 | + 1257 | +&iwdg2{ 1258 | + u-boot,dm-pre-reloc; 1259 | + status = "okay"; 1260 | + 1261 | + /* USER CODE BEGIN iwdg2 */ 1262 | + timeout-sec = <32>; 1263 | + /* USER CODE END iwdg2 */ 1264 | +}; 1265 | + 1266 | +<dc{ 1267 | + pinctrl-names = "default", "sleep"; 1268 | + pinctrl-0 = <<dc_pins_mx>; 1269 | + pinctrl-1 = <<dc_sleep_pins_mx>; 1270 | + status = "okay"; 1271 | + 1272 | + /* USER CODE BEGIN ltdc */ 1273 | + 1274 | + port{ 1275 | + 1276 | + ltdc_ep0_out:endpoint@0{ 1277 | + reg = <0>; 1278 | + remote-endpoint = <&dsi_in>; 1279 | + }; 1280 | + }; 1281 | + /* USER CODE END ltdc */ 1282 | +}; 1283 | + 1284 | +&m_can1{ 1285 | + pinctrl-names = "default", "sleep"; 1286 | + pinctrl-0 = <&fdcan1_pins_mx>; 1287 | + pinctrl-1 = <&fdcan1_sleep_pins_mx>; 1288 | + status = "okay"; 1289 | + 1290 | + /* USER CODE BEGIN m_can1 */ 1291 | + /* USER CODE END m_can1 */ 1292 | +}; 1293 | + 1294 | +&m_can2{ 1295 | + pinctrl-names = "default", "sleep"; 1296 | + pinctrl-0 = <&fdcan2_pins_mx>; 1297 | + pinctrl-1 = <&fdcan2_sleep_pins_mx>; 1298 | + status = "okay"; 1299 | + 1300 | + /* USER CODE BEGIN m_can2 */ 1301 | + /* USER CODE END m_can2 */ 1302 | +}; 1303 | + 1304 | +&mdma1{ 1305 | + status = "okay"; 1306 | + 1307 | + /* USER CODE BEGIN mdma1 */ 1308 | + /* USER CODE END mdma1 */ 1309 | +}; 1310 | + 1311 | +&pwr_regulators{ 1312 | + status = "okay"; 1313 | + 1314 | + /* USER CODE BEGIN pwr_regulators */ 1315 | + vdd-supply = <&vdd>; 1316 | + vdd_3v3_usbfs-supply = <&vdd_usb>; 1317 | + vbus-supply = <®_5v_host>; 1318 | + /* USER CODE END pwr_regulators */ 1319 | +}; 1320 | + 1321 | +&qspi{ 1322 | + u-boot,dm-pre-reloc; 1323 | + pinctrl-names = "default", "sleep"; 1324 | + pinctrl-0 = <&quadspi_pins_mx>; 1325 | + pinctrl-1 = <&quadspi_sleep_pins_mx>; 1326 | + status = "okay"; 1327 | + 1328 | + /* USER CODE BEGIN qspi */ 1329 | + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 1330 | + #address-cells = <1>; 1331 | + #size-cells = <0>; 1332 | + 1333 | + flash0:mx66l51235l@0{ 1334 | + compatible = "jedec,spi-nor"; 1335 | + reg = <0>; 1336 | + spi-rx-bus-width = <4>; 1337 | + spi-max-frequency = <108000000>; 1338 | + #address-cells = <1>; 1339 | + #size-cells = <1>; 1340 | + }; 1341 | + 1342 | + flash1:mx66l51235l@1{ 1343 | + compatible = "jedec,spi-nor"; 1344 | + reg = <1>; 1345 | + spi-rx-bus-width = <4>; 1346 | + spi-max-frequency = <108000000>; 1347 | + #address-cells = <1>; 1348 | + #size-cells = <1>; 1349 | + }; 1350 | + /* USER CODE END qspi */ 1351 | +}; 1352 | + 1353 | +&rcc{ 1354 | + u-boot,dm-pre-reloc; 1355 | + status = "okay"; 1356 | + 1357 | + /* USER CODE BEGIN rcc */ 1358 | + /* USER CODE END rcc */ 1359 | +}; 1360 | + 1361 | +&rng1{ 1362 | + status = "okay"; 1363 | + 1364 | + /* USER CODE BEGIN rng1 */ 1365 | + /* USER CODE END rng1 */ 1366 | +}; 1367 | + 1368 | +&rtc{ 1369 | + status = "okay"; 1370 | + 1371 | + /* USER CODE BEGIN rtc */ 1372 | + /* USER CODE END rtc */ 1373 | +}; 1374 | + 1375 | +&sdmmc1{ 1376 | + u-boot,dm-pre-reloc; 1377 | + pinctrl-names = "default", "opendrain", "sleep"; 1378 | + pinctrl-0 = <&sdmmc1_pins_mx>; 1379 | + pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; 1380 | + pinctrl-2 = <&sdmmc1_sleep_pins_mx>; 1381 | + status = "okay"; 1382 | + 1383 | + /* USER CODE BEGIN sdmmc1 */ 1384 | + broken-cd; 1385 | + st,neg-edge; 1386 | + bus-width = <4>; 1387 | + vmmc-supply = <&vdd_sd>; 1388 | + /* USER CODE END sdmmc1 */ 1389 | +}; 1390 | + 1391 | +&sdmmc2{ 1392 | + u-boot,dm-pre-reloc; 1393 | + pinctrl-names = "default", "opendrain", "sleep"; 1394 | + pinctrl-0 = <&sdmmc2_pins_mx>; 1395 | + pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; 1396 | + pinctrl-2 = <&sdmmc2_sleep_pins_mx>; 1397 | + status = "okay"; 1398 | + 1399 | + /* USER CODE BEGIN sdmmc2 */ 1400 | + non-removable; 1401 | + no-sd; 1402 | + no-sdio; 1403 | + st,neg-edge; 1404 | + bus-width = <8>; 1405 | + vmmc-supply = <&v3v3>; 1406 | + vqmmc-supply = <&vdd>; 1407 | + mmc-ddr-3_3v; 1408 | + /* USER CODE END sdmmc2 */ 1409 | +}; 1410 | + 1411 | +&tamp{ 1412 | + status = "okay"; 1413 | + 1414 | + /* USER CODE BEGIN tamp */ 1415 | + /* USER CODE END tamp */ 1416 | +}; 1417 | + 1418 | +&timers6{ 1419 | + status = "okay"; 1420 | + 1421 | + /* USER CODE BEGIN timers6 */ 1422 | + /delete-property/ dmas; 1423 | + /delete-property/ dma-names; 1424 | + 1425 | + timer@5{ 1426 | + status = "okay"; 1427 | + }; 1428 | + /* USER CODE END timers6 */ 1429 | +}; 1430 | + 1431 | +&uart4{ 1432 | + u-boot,dm-pre-reloc; 1433 | + pinctrl-names = "default", "sleep"; 1434 | + pinctrl-0 = <&uart4_pins_mx>; 1435 | + pinctrl-1 = <&uart4_sleep_pins_mx>; 1436 | + status = "okay"; 1437 | + 1438 | + /* USER CODE BEGIN uart4 */ 1439 | + /delete-property/ dmas; 1440 | + /delete-property/ dma-names; 1441 | + /* USER CODE END uart4 */ 1442 | +}; 1443 | + 1444 | +&usbh_ehci{ 1445 | + status = "okay"; 1446 | + 1447 | + /* USER CODE BEGIN usbh_ehci */ 1448 | + phys = <&usbphyc_port0>; 1449 | + phy-names = "usb"; 1450 | + vbus-supply = <®_5v_host>; 1451 | + /* USER CODE END usbh_ehci */ 1452 | +}; 1453 | + 1454 | +&usbh_ohci{ 1455 | + status = "okay"; 1456 | + 1457 | + /* USER CODE BEGIN usbh_ohci */ 1458 | + vbus-supply = <®_5v_host>; 1459 | + /* USER CODE END usbh_ohci */ 1460 | +}; 1461 | + 1462 | +&usbotg_hs{ 1463 | + u-boot,dm-pre-reloc; 1464 | + pinctrl-names = "default", "sleep"; 1465 | + pinctrl-0 = <&usb_otg_hs_pins_mx>; 1466 | + pinctrl-1 = <&usb_otg_hs_sleep_pins_mx>; 1467 | + status = "okay"; 1468 | + 1469 | + /* USER CODE BEGIN usbotg_hs */ 1470 | + //vbus-supply = <&vbus_otg>; 1471 | + vbus-supply = <®_5v_otg>; 1472 | + phys = <&usbphyc_port1 0>; 1473 | + phy-names = "usb2-phy"; 1474 | + /* USER CODE END usbotg_hs */ 1475 | +}; 1476 | + 1477 | +&usbphyc{ 1478 | + u-boot,dm-pre-reloc; 1479 | + status = "okay"; 1480 | + 1481 | + /* USER CODE BEGIN usbphyc */ 1482 | + /* USER CODE END usbphyc */ 1483 | +}; 1484 | + 1485 | +&usbphyc_port0{ 1486 | + u-boot,dm-pre-reloc; 1487 | + status = "okay"; 1488 | + 1489 | + /* USER CODE BEGIN usbphyc_port0 */ 1490 | + phy-supply = <&vdd_usb>; 1491 | + st,phy-tuning = <&usb_phy_tuning>; 1492 | + vbus-supply = <®_5v_host>; 1493 | + 1494 | + connector{ 1495 | + compatible = "usb-a-connector"; 1496 | + vbus-supply = <&v3v3>; 1497 | + }; 1498 | + /* USER CODE END usbphyc_port0 */ 1499 | +}; 1500 | + 1501 | +&usbphyc_port1{ 1502 | + u-boot,dm-pre-reloc; 1503 | + status = "okay"; 1504 | + 1505 | + /* USER CODE BEGIN usbphyc_port1 */ 1506 | + phy-supply = <&vdd_usb>; 1507 | + st,phy-tuning = <&usb_phy_tuning>; 1508 | + vbus-supply = <®_5v_host>; 1509 | + /* USER CODE END usbphyc_port1 */ 1510 | +}; 1511 | + 1512 | +/* USER CODE BEGIN addons */ 1513 | + 1514 | +&cpu0{ 1515 | + cpu-supply = <&vddcore>; 1516 | + clock-frequency = <650000000>; 1517 | +}; 1518 | + 1519 | +&cpu1{ 1520 | + cpu-supply = <&vddcore>; 1521 | + clock-frequency = <650000000>; 1522 | +}; 1523 | + 1524 | +&sram{ 1525 | + 1526 | + dma_pool:dma_pool@0{ 1527 | + reg = <0x50000 0x10000>; 1528 | + pool; 1529 | + }; 1530 | +}; 1531 | + 1532 | +&usbh_ohci { 1533 | + phys = <&usbphyc_port0>; 1534 | + phy-names = "usb"; 1535 | + vbus-supply = <&vbus_sw>; 1536 | +}; 1537 | +/* USER CODE END addons */ 1538 | -------------------------------------------------------------------------------- /00004-add-u-boot-stm32mp157a-sodimm2-mx.patch: -------------------------------------------------------------------------------- 1 | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile 2 | index 83677c3d4f..e04fb68ce6 100644 3 | --- a/arch/arm/dts/Makefile 4 | +++ b/arch/arm/dts/Makefile 5 | @@ -959,7 +959,8 @@ dtb-$(CONFIG_STM32MP15x) += \ 6 | stm32mp157f-ed1.dtb \ 7 | stm32mp157f-ev1.dtb \ 8 | stm32mp15xx-dhcom-pdk2.dtb \ 9 | - stm32mp15xx-dhcor-avenger96.dtb 10 | + stm32mp15xx-dhcor-avenger96.dtb \ 11 | + stm32mp157a-sodimm2-mx.dtb 12 | 13 | dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb 14 | dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ 15 | diff --git a/arch/arm/dts/stm32mp15-mx.dtsi b/arch/arm/dts/stm32mp15-mx.dtsi 16 | new file mode 100644 17 | index 0000000000..2b1e690de6 18 | --- /dev/null 19 | +++ b/arch/arm/dts/stm32mp15-mx.dtsi 20 | @@ -0,0 +1,119 @@ 21 | +/* 22 | + * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved 23 | + * 24 | + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 25 | + * 26 | + */ 27 | + 28 | +/* 29 | + * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs 30 | + * DDR type: DDR3 / DDR3L 31 | + * DDR width: 32bits 32 | + * DDR density: 8Gb 33 | + * System frequency: 533000kHz 34 | + * Relaxed Timing Mode: false 35 | + * Address mapping type: RBC 36 | + * 37 | + * Save Date: 2022.02.21, save Time: 13:47:46 38 | + */ 39 | + 40 | +#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000kHz" 41 | +#define DDR_MEM_SPEED 533000 42 | +#define DDR_MEM_SIZE 0x40000000 43 | + 44 | +#define DDR_MSTR 0x00040401 45 | +#define DDR_MRCTRL0 0x00000010 46 | +#define DDR_MRCTRL1 0x00000000 47 | +#define DDR_DERATEEN 0x00000000 48 | +#define DDR_DERATEINT 0x00800000 49 | +#define DDR_PWRCTL 0x00000000 50 | +#define DDR_PWRTMG 0x00400010 51 | +#define DDR_HWLPCTL 0x00000000 52 | +#define DDR_RFSHCTL0 0x00210000 53 | +#define DDR_RFSHCTL3 0x00000000 54 | +#define DDR_RFSHTMG 0x0081008B 55 | +#define DDR_CRCPARCTL0 0x00000000 56 | +#define DDR_DRAMTMG0 0x121B2414 57 | +#define DDR_DRAMTMG1 0x000A041C 58 | +#define DDR_DRAMTMG2 0x0608090F 59 | +#define DDR_DRAMTMG3 0x0050400C 60 | +#define DDR_DRAMTMG4 0x08040608 61 | +#define DDR_DRAMTMG5 0x06060403 62 | +#define DDR_DRAMTMG6 0x02020002 63 | +#define DDR_DRAMTMG7 0x00000202 64 | +#define DDR_DRAMTMG8 0x00001005 65 | +#define DDR_DRAMTMG14 0x000000A0 66 | +#define DDR_ZQCTL0 0xC2000040 67 | +#define DDR_DFITMG0 0x02060105 68 | +#define DDR_DFITMG1 0x00000202 69 | +#define DDR_DFILPCFG0 0x07000000 70 | +#define DDR_DFIUPD0 0xC0400003 71 | +#define DDR_DFIUPD1 0x00000000 72 | +#define DDR_DFIUPD2 0x00000000 73 | +#define DDR_DFIPHYMSTR 0x00000000 74 | +#define DDR_ODTCFG 0x06000600 75 | +#define DDR_ODTMAP 0x00000001 76 | +#define DDR_SCHED 0x00000C01 77 | +#define DDR_SCHED1 0x00000000 78 | +#define DDR_PERFHPR1 0x01000001 79 | +#define DDR_PERFLPR1 0x08000200 80 | +#define DDR_PERFWR1 0x08000400 81 | +#define DDR_DBG0 0x00000000 82 | +#define DDR_DBG1 0x00000000 83 | +#define DDR_DBGCMD 0x00000000 84 | +#define DDR_POISONCFG 0x00000000 85 | +#define DDR_PCCFG 0x00000010 86 | +#define DDR_PCFGR_0 0x00010000 87 | +#define DDR_PCFGW_0 0x00000000 88 | +#define DDR_PCFGQOS0_0 0x02100C03 89 | +#define DDR_PCFGQOS1_0 0x00800100 90 | +#define DDR_PCFGWQOS0_0 0x01100C03 91 | +#define DDR_PCFGWQOS1_0 0x01000200 92 | +#define DDR_PCFGR_1 0x00010000 93 | +#define DDR_PCFGW_1 0x00000000 94 | +#define DDR_PCFGQOS0_1 0x02100C03 95 | +#define DDR_PCFGQOS1_1 0x00800040 96 | +#define DDR_PCFGWQOS0_1 0x01100C03 97 | +#define DDR_PCFGWQOS1_1 0x01000200 98 | +#define DDR_ADDRMAP1 0x00080808 99 | +#define DDR_ADDRMAP2 0x00000000 100 | +#define DDR_ADDRMAP3 0x00000000 101 | +#define DDR_ADDRMAP4 0x00001F1F 102 | +#define DDR_ADDRMAP5 0x07070707 103 | +#define DDR_ADDRMAP6 0x0F070707 104 | +#define DDR_ADDRMAP9 0x00000000 105 | +#define DDR_ADDRMAP10 0x00000000 106 | +#define DDR_ADDRMAP11 0x00000000 107 | +#define DDR_PGCR 0x01442E02 108 | +#define DDR_PTR0 0x0022AA5B 109 | +#define DDR_PTR1 0x04841104 110 | +#define DDR_PTR2 0x042DA068 111 | +#define DDR_ACIOCR 0x10400812 112 | +#define DDR_DXCCR 0x00000C40 113 | +#define DDR_DSGCR 0xF200011F 114 | +#define DDR_DCR 0x0000000B 115 | +#define DDR_DTPR0 0x38D488D0 116 | +#define DDR_DTPR1 0x098B00D8 117 | +#define DDR_DTPR2 0x10023600 118 | +#define DDR_MR0 0x00000840 119 | +#define DDR_MR1 0x00000000 120 | +#define DDR_MR2 0x00000208 121 | +#define DDR_MR3 0x00000000 122 | +#define DDR_ODTCR 0x00010000 123 | +#define DDR_ZQ0CR1 0x00000038 124 | +#define DDR_DX0GCR 0x0000CE81 125 | +#define DDR_DX0DLLCR 0x40000000 126 | +#define DDR_DX0DQTR 0xFFFFFFFF 127 | +#define DDR_DX0DQSTR 0x3DB02000 128 | +#define DDR_DX1GCR 0x0000CE81 129 | +#define DDR_DX1DLLCR 0x40000000 130 | +#define DDR_DX1DQTR 0xFFFFFFFF 131 | +#define DDR_DX1DQSTR 0x3DB02000 132 | +#define DDR_DX2GCR 0x0000CE81 133 | +#define DDR_DX2DLLCR 0x40000000 134 | +#define DDR_DX2DQTR 0xFFFFFFFF 135 | +#define DDR_DX2DQSTR 0x3DB02000 136 | +#define DDR_DX3GCR 0x0000CE81 137 | +#define DDR_DX3DLLCR 0x40000000 138 | +#define DDR_DX3DQTR 0xFFFFFFFF 139 | +#define DDR_DX3DQSTR 0x3DB02000 140 | diff --git a/arch/arm/dts/stm32mp157a-sodimm2-mx-u-boot.dtsi b/arch/arm/dts/stm32mp157a-sodimm2-mx-u-boot.dtsi 141 | new file mode 100644 142 | index 0000000000..cc3038b5a4 143 | --- /dev/null 144 | +++ b/arch/arm/dts/stm32mp157a-sodimm2-mx-u-boot.dtsi 145 | @@ -0,0 +1,301 @@ 146 | +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/ 147 | +/* 148 | + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved 149 | + * Author: STM32CubeMX code generation for STMicroelectronics. 150 | + */ 151 | + 152 | +/* For more information on Device Tree configuration, please refer to 153 | + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 154 | + */ 155 | + 156 | +#include 157 | +#include "stm32mp15-mx.dtsi" 158 | + 159 | +#include "stm32mp15-u-boot.dtsi" 160 | +#include "stm32mp15-ddr.dtsi" 161 | + 162 | +/* USER CODE BEGIN includes */ 163 | +/* USER CODE END includes */ 164 | + 165 | +/ { 166 | + 167 | + /* USER CODE BEGIN root */ 168 | + 169 | + aliases{ 170 | + i2c3 = &i2c4; 171 | + mmc0 = &sdmmc1; 172 | + mmc1 = &sdmmc2; 173 | + gpio26 = &stmfx_pinctrl; 174 | + i2c1 = &i2c2; 175 | + i2c4 = &i2c5; 176 | + pinctrl2 = &stmfx_pinctrl; 177 | + spi0 = &qspi; 178 | + usb0 = &usbotg_hs; 179 | + }; 180 | + 181 | + config{ 182 | + u-boot,boot-led = "heartbeat"; 183 | + u-boot,error-led = "error"; 184 | + u-boot,mmc-env-partition = "fip"; 185 | + st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 186 | + st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 187 | + }; 188 | + 189 | + led{ 190 | + 191 | + led-red{ 192 | + label = "error"; 193 | + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; 194 | + default-state = "off"; 195 | + status = "okay"; 196 | + }; 197 | + }; 198 | + 199 | +#ifdef CONFIG_STM32MP15x_STM32IMAGE 200 | + 201 | + config{ 202 | + u-boot,mmc-env-partition = "ssbl"; 203 | + }; 204 | + 205 | + firmware{ 206 | + 207 | + optee{ 208 | + compatible = "linaro,optee-tz"; 209 | + method = "smc"; 210 | + }; 211 | + }; 212 | + 213 | + reserved-memory{ 214 | + 215 | + optee@fe000000{ 216 | + reg = <0xfe000000 0x02000000>; 217 | + no-map; 218 | + }; 219 | + }; 220 | +#endif 221 | + /* USER CODE END root */ 222 | + 223 | + clocks { 224 | + /* USER CODE BEGIN clocks */ 225 | + /* USER CODE END clocks */ 226 | + 227 | +#ifndef CONFIG_TFABOOT 228 | + clk_lsi: clk-lsi { 229 | + 230 | + /* USER CODE BEGIN clk_lsi */ 231 | + /* USER CODE END clk_lsi */ 232 | + }; 233 | + clk_hsi: clk-hsi { 234 | + 235 | + /* USER CODE BEGIN clk_hsi */ 236 | + /* USER CODE END clk_hsi */ 237 | + }; 238 | + clk_csi: clk-csi { 239 | + status = "disabled"; 240 | + 241 | + /* USER CODE BEGIN clk_csi */ 242 | + /* USER CODE END clk_csi */ 243 | + }; 244 | + clk_lse: clk-lse { 245 | + st,drive = < LSEDRV_MEDIUM_HIGH >; 246 | + 247 | + /* USER CODE BEGIN clk_lse */ 248 | + /* USER CODE END clk_lse */ 249 | + }; 250 | + clk_hse: clk-hse { 251 | + st,digbypass; 252 | + 253 | + /* USER CODE BEGIN clk_hse */ 254 | + /* USER CODE END clk_hse */ 255 | + }; 256 | +#endif /*CONFIG_TFABOOT*/ 257 | + }; 258 | + 259 | +}; /*root*/ 260 | + 261 | +#ifndef CONFIG_TFABOOT 262 | + 263 | +&rcc{ 264 | + u-boot,dm-pre-reloc; 265 | + st,clksrc = < 266 | + CLK_MPU_PLL1P 267 | + CLK_AXI_PLL2P 268 | + CLK_MCU_PLL3P 269 | + CLK_PLL12_HSE 270 | + CLK_PLL3_HSE 271 | + CLK_PLL4_HSE 272 | + CLK_RTC_LSE 273 | + CLK_MCO1_DISABLED 274 | + CLK_MCO2_DISABLED 275 | + >; 276 | + st,clkdiv = < 277 | + 1 /*MPU*/ 278 | + 0 /*AXI*/ 279 | + 0 /*MCU*/ 280 | + 1 /*APB1*/ 281 | + 1 /*APB2*/ 282 | + 1 /*APB3*/ 283 | + 1 /*APB4*/ 284 | + 2 /*APB5*/ 285 | + 23 /*RTC*/ 286 | + 0 /*MCO1*/ 287 | + 0 /*MCO2*/ 288 | + >; 289 | + st,pkcs = < 290 | + CLK_CKPER_DISABLED 291 | + CLK_QSPI_ACLK 292 | + CLK_ETH_PLL4P 293 | + CLK_SDMMC12_PLL4P 294 | + CLK_STGEN_HSE 295 | + CLK_USBPHY_HSE 296 | + CLK_SPI2S1_DISABLED 297 | + CLK_SPI2S23_DISABLED 298 | + CLK_SPI45_DISABLED 299 | + CLK_SPI6_DISABLED 300 | + CLK_I2C46_HSI 301 | + CLK_SDMMC3_DISABLED 302 | + CLK_USBO_USBPHY 303 | + CLK_ADC_PLL4R 304 | + CLK_CEC_DISABLED 305 | + CLK_I2C12_HSI 306 | + CLK_I2C35_PCLK1 307 | + CLK_UART1_DISABLED 308 | + CLK_UART24_HSI 309 | + CLK_UART35_DISABLED 310 | + CLK_UART6_DISABLED 311 | + CLK_UART78_DISABLED 312 | + CLK_SPDIF_DISABLED 313 | + CLK_FDCAN_PLL3Q 314 | + CLK_SAI1_DISABLED 315 | + CLK_SAI2_DISABLED 316 | + CLK_SAI3_DISABLED 317 | + CLK_SAI4_DISABLED 318 | + CLK_RNG1_LSI 319 | + CLK_LPTIM1_DISABLED 320 | + CLK_LPTIM23_DISABLED 321 | + CLK_LPTIM45_DISABLED 322 | + >; 323 | + pll2:st,pll@1 { 324 | + compatible = "st,stm32mp1-pll"; 325 | + reg = <1>; 326 | + cfg = < 2 65 1 0 0 PQR(1,1,1) >; 327 | + frac = < 0x1400 >; 328 | + u-boot,dm-pre-reloc; 329 | + }; 330 | + pll3:st,pll@2 { 331 | + compatible = "st,stm32mp1-pll"; 332 | + reg = <2>; 333 | + cfg = < 1 49 2 5 36 PQR(1,1,0) >; 334 | + u-boot,dm-pre-reloc; 335 | + }; 336 | + pll4:st,pll@3 { 337 | + compatible = "st,stm32mp1-pll"; 338 | + reg = <3>; 339 | + cfg = < 3 98 5 17 7 PQR(1,1,0) >; 340 | + u-boot,dm-pre-reloc; 341 | + }; 342 | + 343 | + /* USER CODE BEGIN rcc */ 344 | + /* USER CODE END rcc */ 345 | +}; 346 | + 347 | +&i2c4{ 348 | + u-boot,dm-pre-reloc; 349 | + 350 | + /* USER CODE BEGIN i2c4 */ 351 | + /* USER CODE END i2c4 */ 352 | +}; 353 | + 354 | +&qspi{ 355 | + u-boot,dm-pre-reloc; 356 | + 357 | + /* USER CODE BEGIN qspi */ 358 | + /* USER CODE END qspi */ 359 | +}; 360 | + 361 | +&sdmmc1{ 362 | + u-boot,dm-pre-reloc; 363 | + 364 | + /* USER CODE BEGIN sdmmc1 */ 365 | + /* USER CODE END sdmmc1 */ 366 | +}; 367 | + 368 | +&sdmmc2{ 369 | + u-boot,dm-pre-reloc; 370 | + 371 | + /* USER CODE BEGIN sdmmc2 */ 372 | + /* USER CODE END sdmmc2 */ 373 | +}; 374 | + 375 | +#endif /*CONFIG_TFABOOT*/ 376 | + 377 | +&hash1{ 378 | + u-boot,dm-pre-reloc; 379 | + 380 | + /* USER CODE BEGIN hash1 */ 381 | + /* USER CODE END hash1 */ 382 | +}; 383 | + 384 | +&iwdg2{ 385 | + u-boot,dm-pre-reloc; 386 | + 387 | + /* USER CODE BEGIN iwdg2 */ 388 | + /* USER CODE END iwdg2 */ 389 | +}; 390 | + 391 | +&uart4{ 392 | + u-boot,dm-pre-reloc; 393 | + 394 | + /* USER CODE BEGIN uart4 */ 395 | + /* USER CODE END uart4 */ 396 | +}; 397 | + 398 | +&usbotg_hs{ 399 | + u-boot,dm-pre-reloc; 400 | + 401 | + /* USER CODE BEGIN usbotg_hs */ 402 | + /* USER CODE END usbotg_hs */ 403 | +}; 404 | + 405 | +&usbphyc{ 406 | + u-boot,dm-pre-reloc; 407 | + 408 | + /* USER CODE BEGIN usbphyc */ 409 | + /* USER CODE END usbphyc */ 410 | +}; 411 | + 412 | +&usbphyc_port0{ 413 | + u-boot,dm-pre-reloc; 414 | + 415 | + /* USER CODE BEGIN usbphyc_port0 */ 416 | + /* USER CODE END usbphyc_port0 */ 417 | +}; 418 | + 419 | +&usbphyc_port1{ 420 | + u-boot,dm-pre-reloc; 421 | + 422 | + /* USER CODE BEGIN usbphyc_port1 */ 423 | + /* USER CODE END usbphyc_port1 */ 424 | +}; 425 | + 426 | +/* USER CODE BEGIN addons */ 427 | + 428 | +#ifndef CONFIG_TFABOOT 429 | + 430 | +&flash0{ 431 | + u-boot,dm-spl; 432 | +}; 433 | + 434 | +&pmic{ 435 | + u-boot,dm-pre-reloc; 436 | +}; 437 | + 438 | +#endif /*CONFIG_TFABOOT*/ 439 | + 440 | +&uart4_pins_mx { 441 | + pins1 { /* UART4_RX */ 442 | + /* pull-up on rx to avoid floating level */ 443 | + bias-pull-up; 444 | + }; 445 | +}; 446 | +/* USER CODE END addons */ 447 | diff --git a/arch/arm/dts/stm32mp157a-sodimm2-mx.dts b/arch/arm/dts/stm32mp157a-sodimm2-mx.dts 448 | new file mode 100644 449 | index 0000000000..e8b04a2697 450 | --- /dev/null 451 | +++ b/arch/arm/dts/stm32mp157a-sodimm2-mx.dts 452 | @@ -0,0 +1,1510 @@ 453 | +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 454 | +/* 455 | + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 456 | + * Author: STM32CubeMX code generation for STMicroelectronics. 457 | + */ 458 | + 459 | +/* For more information on Device Tree configuration, please refer to 460 | + * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration 461 | + */ 462 | + 463 | +/dts-v1/; 464 | +#include 465 | + 466 | +#include "stm32mp157.dtsi" 467 | +#include "stm32mp15xa.dtsi" 468 | +#include "stm32mp15xxaa-pinctrl.dtsi" 469 | +#include "stm32mp15-m4-srm.dtsi" 470 | + 471 | +/* USER CODE BEGIN includes */ 472 | +#include 473 | +#include 474 | +#include 475 | +#include 476 | +/* USER CODE END includes */ 477 | + 478 | +/ { 479 | + model = "STMicroelectronics STM32MP157AAA3 SODIMM module"; 480 | + compatible = "st,stm32mp157a-sodimm2-mx", "st,stm32mp157"; 481 | + 482 | + memory@c0000000 { 483 | + device_type = "memory"; 484 | + reg = <0xc0000000 0x40000000>; 485 | + 486 | + /* USER CODE BEGIN memory */ 487 | + /* USER CODE END memory */ 488 | + }; 489 | + 490 | + reserved-memory { 491 | + #address-cells = <1>; 492 | + #size-cells = <1>; 493 | + ranges; 494 | + 495 | + /* USER CODE BEGIN reserved-memory */ 496 | + 497 | + mcuram2:mcuram2@10000000{ 498 | + compatible = "shared-dma-pool"; 499 | + reg = <0x10000000 0x40000>; 500 | + no-map; 501 | + }; 502 | + 503 | + vdev0vring0:vdev0vring0@10040000{ 504 | + compatible = "shared-dma-pool"; 505 | + reg = <0x10040000 0x1000>; 506 | + no-map; 507 | + }; 508 | + 509 | + vdev0vring1:vdev0vring1@10041000{ 510 | + compatible = "shared-dma-pool"; 511 | + reg = <0x10041000 0x1000>; 512 | + no-map; 513 | + }; 514 | + 515 | + vdev0buffer:vdev0buffer@10042000{ 516 | + compatible = "shared-dma-pool"; 517 | + reg = <0x10042000 0x4000>; 518 | + no-map; 519 | + }; 520 | + 521 | + mcu_rsc_table:mcu_rsc_table@10048000{ 522 | + compatible = "shared-dma-pool"; 523 | + reg = <0x10048000 0x8000>; 524 | + no-map; 525 | + }; 526 | + 527 | + mcuram:mcuram@30000000{ 528 | + compatible = "shared-dma-pool"; 529 | + reg = <0x30000000 0x40000>; 530 | + no-map; 531 | + }; 532 | + 533 | + retram:retram@38000000{ 534 | + compatible = "shared-dma-pool"; 535 | + reg = <0x38000000 0x10000>; 536 | + no-map; 537 | + }; 538 | + 539 | + gpu_reserved:gpu@f6000000{ 540 | + reg = <0xf6000000 0x8000000>; 541 | + no-map; 542 | + }; 543 | + /* USER CODE END reserved-memory */ 544 | + }; 545 | + 546 | + /* USER CODE BEGIN root */ 547 | + 548 | + aliases{ 549 | + serial0 = &uart4; 550 | + ethernet0 = ðernet0; 551 | + spi0 = &qspi; 552 | + display0 = &lcd0; 553 | + //serial1 = &usart3; 554 | + }; 555 | + 556 | + reg_5v_host: reg-5v-host { 557 | + compatible = "regulator-fixed"; 558 | + regulator-name = "5v-host"; 559 | + regulator-min-microvolt = <5000000>; 560 | + regulator-max-microvolt = <5000000>; 561 | + pinctrl-names = "default", "sleep"; 562 | + pinctrl-0 = <&usb_5v_power_pins_mx>; 563 | + pinctrl-1 = <&usb_5v_power_sleep_pins_mx>; 564 | + //gpio = <&gpioi 11 GPIO_ACTIVE_HIGH>; //power USB port 565 | + enable-active-high; 566 | + default-on; 567 | + status = "okay"; 568 | + }; 569 | + 570 | + reg_5v_otg: reg-5v-otg { 571 | + compatible = "regulator-fixed"; 572 | + regulator-name = "5v-otg"; 573 | + regulator-min-microvolt = <5000000>; 574 | + regulator-max-microvolt = <5000000>; 575 | + pinctrl-names = "default", "sleep"; 576 | + pinctrl-0 = <&usb_otg_5v_power_pins_mx>; 577 | + pinctrl-1 = <&usb_otg_5v_power_sleep_pins_mx>; 578 | + //gpio = <&gpioc 13 GPIO_ACTIVE_HIGH>; //power for second port 579 | + enable-active-high; 580 | + default-on; 581 | + status = "okay"; 582 | + }; 583 | + 584 | + reg_3v3_rgb: regulator-3v3-rgb { 585 | + compatible = "regulator-fixed"; 586 | + regulator-name = "3v3-rgb"; 587 | + regulator-min-microvolt = <3300000>; 588 | + regulator-max-microvolt = <3300000>; 589 | + gpio = <&gpiog 2 GPIO_ACTIVE_HIGH>; 590 | + enable-active-high; 591 | + status = "okay"; 592 | + }; 593 | + 594 | + rgb_panel_backlight: rgb-panel-backlight { 595 | + compatible = "gpio-backlight"; 596 | + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; 597 | + enable-active-high; 598 | + //default-on; 599 | + linux,default-trigger = "backlight"; 600 | + status = "okay"; 601 | + }; 602 | + 603 | + lcd0: display { 604 | + compatible = "ampire,am800480r3tmqwa1h", "panel-dpi"; 605 | + //compatible = "bananapi,s070wv20-ct16", "panel-dpi"; 606 | + //compatible = "panel-dpi"; 607 | + //compatible = "startek,startek-kd050c", "panel-dpi"; 608 | + label = "display"; 609 | + power-supply = <®_3v3_rgb>; 610 | + backlight = <&rgb_panel_backlight>; 611 | + //bits-per-pixel = <32>; 612 | + //bus-width = <24>; 613 | + //connector-type = <17>; 614 | + 615 | + status = "okay"; 616 | + 617 | + port { 618 | + dsi_in: endpoint { 619 | + remote-endpoint = <<dc_ep0_out>; 620 | + }; 621 | + }; 622 | + 623 | + // panel-timing { 624 | + // clock-frequency = <33000000>; 625 | + // hactive = <800>; 626 | + // vactive = <480>; 627 | + // hfront-porch = <40>; 628 | + // hback-porch = <40>; 629 | + // hsync-len = <43>; 630 | + // vback-porch = <29>; 631 | + // vfront-porch = <13>; 632 | + // vsync-len = <3>; 633 | + // hsync-active = <0>; 634 | + // vsync-active = <0>; 635 | + // de-active = <1>; 636 | + // pixelclk-active = <1>; 637 | + // }; 638 | + 639 | + }; 640 | + 641 | + led { 642 | + compatible = "gpio-leds"; 643 | + status = "okay"; 644 | + 645 | + green1 { 646 | + label = "heartbeat"; 647 | + gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>; 648 | + linux,default-trigger = "heartbeat"; 649 | + default-state = "on"; 650 | + }; 651 | + 652 | + green2 { 653 | + label = "network"; 654 | + gpios = <&pcf8574a 7 GPIO_ACTIVE_LOW>; 655 | + linux,default-trigger = "netdev"; 656 | + default-state = "off"; 657 | + }; 658 | + }; 659 | + 660 | + vin:vin{ 661 | + compatible = "regulator-fixed"; 662 | + regulator-name = "vin"; 663 | + regulator-min-microvolt = <5000000>; 664 | + regulator-max-microvolt = <5000000>; 665 | + regulator-always-on; 666 | + }; 667 | + 668 | + chosen{ 669 | + stdout-path = "serial0:115200n8"; 670 | + }; 671 | + 672 | + usb_phy_tuning:usb-phy-tuning{ 673 | + st,hs-dc-level = <2>; 674 | + st,fs-rftime-tuning; 675 | + st,hs-rftime-reduction; 676 | + st,hs-current-trim = <15>; 677 | + st,hs-impedance-trim = <1>; 678 | + st,squelch-level = <3>; 679 | + st,hs-rx-offset = <2>; 680 | + st,no-lsfs-sc; 681 | + }; 682 | + /* USER CODE END root */ 683 | + 684 | + clocks { 685 | + /* USER CODE BEGIN clocks */ 686 | + 687 | + clk_ext_camera:clk-ext-camera{ 688 | + #clock-cells = <0>; 689 | + compatible = "fixed-clock"; 690 | + clock-frequency = <24000000>; 691 | + }; 692 | + /* USER CODE END clocks */ 693 | + 694 | +#ifndef CONFIG_TFABOOT 695 | + clk_lsi: clk-lsi { 696 | + clock-frequency = <32000>; 697 | + }; 698 | + clk_hsi: clk-hsi { 699 | + clock-frequency = <64000000>; 700 | + }; 701 | + clk_csi: clk-csi { 702 | + clock-frequency = <4000000>; 703 | + }; 704 | + clk_lse: clk-lse { 705 | + clock-frequency = <32768>; 706 | + }; 707 | + clk_hse: clk-hse { 708 | + clock-frequency = <24000000>; 709 | + }; 710 | +#endif /*CONFIG_TFABOOT*/ 711 | + }; 712 | + 713 | +}; /*root*/ 714 | + 715 | +&pinctrl { 716 | + u-boot,dm-pre-reloc; 717 | + 718 | + dcmi_pins_mx: dcmi_mx-0 { 719 | + pins { 720 | + pinmux = , /* DCMI_PIXCLK */ 721 | + , /* DCMI_VSYNC */ 722 | + , /* DCMI_D6 */ 723 | + , /* DCMI_D7 */ 724 | + , /* DCMI_HSYNC */ 725 | + , /* DCMI_D0 */ 726 | + , /* DCMI_D1 */ 727 | + , /* DCMI_D2 */ 728 | + , /* DCMI_D3 */ 729 | + , /* DCMI_D4 */ 730 | + ; /* DCMI_D5 */ 731 | + bias-disable; 732 | + }; 733 | + }; 734 | + 735 | + dcmi_sleep_pins_mx: dcmi_sleep_mx-0 { 736 | + pins { 737 | + pinmux = , /* DCMI_PIXCLK */ 738 | + , /* DCMI_VSYNC */ 739 | + , /* DCMI_D6 */ 740 | + , /* DCMI_D7 */ 741 | + , /* DCMI_HSYNC */ 742 | + , /* DCMI_D0 */ 743 | + , /* DCMI_D1 */ 744 | + , /* DCMI_D2 */ 745 | + , /* DCMI_D3 */ 746 | + , /* DCMI_D4 */ 747 | + ; /* DCMI_D5 */ 748 | + }; 749 | + }; 750 | + 751 | + eth1_pins_mx: eth1_mx-0 { 752 | + pins1 { 753 | + pinmux = , /* ETH1_RX_CLK */ 754 | + , /* ETH1_RX_CTL */ 755 | + , /* ETH1_RXD2 */ 756 | + , /* ETH1_RXD3 */ 757 | + , /* ETH1_RXD0 */ 758 | + ; /* ETH1_RXD1 */ 759 | + bias-disable; 760 | + }; 761 | + pins2 { 762 | + pinmux = ; /* ETH1_MDIO */ 763 | + bias-disable; 764 | + drive-push-pull; 765 | + slew-rate = <0>; 766 | + }; 767 | + pins3 { 768 | + pinmux = , /* ETH1_TX_CTL */ 769 | + , /* ETH1_MDC */ 770 | + , /* ETH1_TXD2 */ 771 | + , /* ETH1_TXD3 */ 772 | + , /* ETH1_GTX_CLK */ 773 | + , /* ETH1_CLK125 */ 774 | + , /* ETH1_TXD0 */ 775 | + ; /* ETH1_TXD1 */ 776 | + bias-disable; 777 | + drive-push-pull; 778 | + slew-rate = <2>; 779 | + }; 780 | + }; 781 | + 782 | + eth1_sleep_pins_mx: eth1_sleep_mx-0 { 783 | + pins { 784 | + pinmux = , /* ETH1_RX_CLK */ 785 | + , /* ETH1_MDIO */ 786 | + , /* ETH1_RX_CTL */ 787 | + , /* ETH1_RXD2 */ 788 | + , /* ETH1_RXD3 */ 789 | + , /* ETH1_TX_CTL */ 790 | + , /* ETH1_MDC */ 791 | + , /* ETH1_TXD2 */ 792 | + , /* ETH1_RXD0 */ 793 | + , /* ETH1_RXD1 */ 794 | + , /* ETH1_TXD3 */ 795 | + , /* ETH1_GTX_CLK */ 796 | + , /* ETH1_CLK125 */ 797 | + , /* ETH1_TXD0 */ 798 | + ; /* ETH1_TXD1 */ 799 | + }; 800 | + }; 801 | + 802 | + fdcan1_pins_mx: fdcan1_mx-0 { 803 | + pins1 { 804 | + pinmux = ; /* FDCAN1_TX */ 805 | + bias-pull-up; 806 | + drive-push-pull; 807 | + slew-rate = <0>; 808 | + }; 809 | + pins2 { 810 | + pinmux = ; /* FDCAN1_RX */ 811 | + bias-pull-up; 812 | + }; 813 | + }; 814 | + 815 | + fdcan1_sleep_pins_mx: fdcan1_sleep_mx-0 { 816 | + pins { 817 | + pinmux = , /* FDCAN1_TX */ 818 | + ; /* FDCAN1_RX */ 819 | + }; 820 | + }; 821 | + 822 | + fdcan2_pins_mx: fdcan2_mx-0 { 823 | + pins1 { 824 | + pinmux = ; /* FDCAN2_TX */ 825 | + bias-pull-up; 826 | + drive-push-pull; 827 | + slew-rate = <0>; 828 | + }; 829 | + pins2 { 830 | + pinmux = ; /* FDCAN2_RX */ 831 | + bias-pull-up; 832 | + }; 833 | + }; 834 | + 835 | + fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 { 836 | + pins { 837 | + pinmux = , /* FDCAN2_RX */ 838 | + ; /* FDCAN2_TX */ 839 | + }; 840 | + }; 841 | + 842 | + i2c2_pins_mx: i2c2_mx-0 { 843 | + pins { 844 | + pinmux = , /* I2C2_SCL */ 845 | + ; /* I2C2_SDA */ 846 | + bias-disable; 847 | + drive-open-drain; 848 | + slew-rate = <0>; 849 | + }; 850 | + }; 851 | + 852 | + i2c2_sleep_pins_mx: i2c2_sleep_mx-0 { 853 | + pins { 854 | + pinmux = , /* I2C2_SCL */ 855 | + ; /* I2C2_SDA */ 856 | + }; 857 | + }; 858 | + 859 | + i2c5_pins_mx: i2c5_mx-0 { 860 | + pins { 861 | + pinmux = , /* I2C5_SDA */ 862 | + ; /* I2C5_SCL */ 863 | + bias-disable; 864 | + drive-open-drain; 865 | + slew-rate = <0>; 866 | + }; 867 | + }; 868 | + 869 | + i2c5_sleep_pins_mx: i2c5_sleep_mx-0 { 870 | + pins { 871 | + pinmux = , /* I2C5_SDA */ 872 | + ; /* I2C5_SCL */ 873 | + }; 874 | + }; 875 | + 876 | + ltdc_pins_mx: ltdc_mx-0 { 877 | + pins1 { 878 | + pinmux = , /* LTDC_HSYNC */ 879 | + , /* LTDC_VSYNC */ 880 | + , /* LTDC_R0 */ 881 | + , /* LTDC_R1 */ 882 | + , /* LTDC_R2 */ 883 | + , /* LTDC_R3 */ 884 | + , /* LTDC_R4 */ 885 | + , /* LTDC_R5 */ 886 | + , /* LTDC_R6 */ 887 | + , /* LTDC_R7 */ 888 | + , /* LTDC_G0 */ 889 | + , /* LTDC_G1 */ 890 | + , /* LTDC_G2 */ 891 | + , /* LTDC_G3 */ 892 | + , /* LTDC_G4 */ 893 | + , /* LTDC_B0 */ 894 | + , /* LTDC_B1 */ 895 | + , /* LTDC_B2 */ 896 | + , /* LTDC_B3 */ 897 | + , /* LTDC_G5 */ 898 | + , /* LTDC_G6 */ 899 | + , /* LTDC_G7 */ 900 | + , /* LTDC_B4 */ 901 | + , /* LTDC_B5 */ 902 | + , /* LTDC_B6 */ 903 | + , /* LTDC_B7 */ 904 | + ; /* LTDC_DE */ 905 | + bias-disable; 906 | + drive-push-pull; 907 | + slew-rate = <0>; 908 | + }; 909 | + pins2 { 910 | + pinmux = ; /* LTDC_CLK */ 911 | + bias-disable; 912 | + drive-push-pull; 913 | + slew-rate = <1>; 914 | + }; 915 | + }; 916 | + 917 | + ltdc_sleep_pins_mx: ltdc_sleep_mx-0 { 918 | + pins { 919 | + pinmux = , /* LTDC_HSYNC */ 920 | + , /* LTDC_VSYNC */ 921 | + , /* LTDC_CLK */ 922 | + , /* LTDC_R0 */ 923 | + , /* LTDC_R1 */ 924 | + , /* LTDC_R2 */ 925 | + , /* LTDC_R3 */ 926 | + , /* LTDC_R4 */ 927 | + , /* LTDC_R5 */ 928 | + , /* LTDC_R6 */ 929 | + , /* LTDC_R7 */ 930 | + , /* LTDC_G0 */ 931 | + , /* LTDC_G1 */ 932 | + , /* LTDC_G2 */ 933 | + , /* LTDC_G3 */ 934 | + , /* LTDC_G4 */ 935 | + , /* LTDC_B0 */ 936 | + , /* LTDC_B1 */ 937 | + , /* LTDC_B2 */ 938 | + , /* LTDC_B3 */ 939 | + , /* LTDC_G5 */ 940 | + , /* LTDC_G6 */ 941 | + , /* LTDC_G7 */ 942 | + , /* LTDC_B4 */ 943 | + , /* LTDC_B5 */ 944 | + , /* LTDC_B6 */ 945 | + , /* LTDC_B7 */ 946 | + ; /* LTDC_DE */ 947 | + }; 948 | + }; 949 | + 950 | + quadspi_pins_mx: quadspi_mx-0 { 951 | + u-boot,dm-pre-reloc; 952 | + pins1 { 953 | + u-boot,dm-pre-reloc; 954 | + pinmux = , /* QUADSPI_BK1_NCS */ 955 | + ; /* QUADSPI_BK2_NCS */ 956 | + bias-pull-up; 957 | + drive-push-pull; 958 | + slew-rate = <1>; 959 | + }; 960 | + pins2 { 961 | + u-boot,dm-pre-reloc; 962 | + pinmux = ; /* QUADSPI_CLK */ 963 | + bias-disable; 964 | + drive-push-pull; 965 | + slew-rate = <3>; 966 | + }; 967 | + pins3 { 968 | + u-boot,dm-pre-reloc; 969 | + pinmux = , /* QUADSPI_BK1_IO3 */ 970 | + , /* QUADSPI_BK1_IO2 */ 971 | + , /* QUADSPI_BK1_IO0 */ 972 | + , /* QUADSPI_BK1_IO1 */ 973 | + , /* QUADSPI_BK2_IO3 */ 974 | + , /* QUADSPI_BK2_IO2 */ 975 | + , /* QUADSPI_BK2_IO0 */ 976 | + ; /* QUADSPI_BK2_IO1 */ 977 | + bias-disable; 978 | + drive-push-pull; 979 | + slew-rate = <1>; 980 | + }; 981 | + }; 982 | + 983 | + quadspi_sleep_pins_mx: quadspi_sleep_mx-0 { 984 | + u-boot,dm-pre-reloc; 985 | + pins { 986 | + u-boot,dm-pre-reloc; 987 | + pinmux = , /* QUADSPI_BK1_NCS */ 988 | + , /* QUADSPI_BK2_NCS */ 989 | + , /* QUADSPI_BK1_IO3 */ 990 | + , /* QUADSPI_BK1_IO2 */ 991 | + , /* QUADSPI_BK1_IO0 */ 992 | + , /* QUADSPI_BK1_IO1 */ 993 | + , /* QUADSPI_CLK */ 994 | + , /* QUADSPI_BK2_IO3 */ 995 | + , /* QUADSPI_BK2_IO2 */ 996 | + , /* QUADSPI_BK2_IO0 */ 997 | + ; /* QUADSPI_BK2_IO1 */ 998 | + }; 999 | + }; 1000 | + 1001 | + sdmmc1_pins_mx: sdmmc1_mx-0 { 1002 | + u-boot,dm-pre-reloc; 1003 | + pins1 { 1004 | + u-boot,dm-pre-reloc; 1005 | + pinmux = , /* SDMMC1_D0 */ 1006 | + , /* SDMMC1_D1 */ 1007 | + , /* SDMMC1_D2 */ 1008 | + , /* SDMMC1_D3 */ 1009 | + ; /* SDMMC1_CMD */ 1010 | + bias-pull-up; 1011 | + drive-push-pull; 1012 | + slew-rate = <1>; 1013 | + }; 1014 | + pins2 { 1015 | + u-boot,dm-pre-reloc; 1016 | + pinmux = ; /* SDMMC1_CK */ 1017 | + bias-pull-up; 1018 | + drive-push-pull; 1019 | + slew-rate = <2>; 1020 | + }; 1021 | + }; 1022 | + 1023 | + sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { 1024 | + u-boot,dm-pre-reloc; 1025 | + pins1 { 1026 | + u-boot,dm-pre-reloc; 1027 | + pinmux = , /* SDMMC1_D0 */ 1028 | + , /* SDMMC1_D1 */ 1029 | + , /* SDMMC1_D2 */ 1030 | + ; /* SDMMC1_D3 */ 1031 | + bias-pull-up; 1032 | + drive-push-pull; 1033 | + slew-rate = <1>; 1034 | + }; 1035 | + pins2 { 1036 | + u-boot,dm-pre-reloc; 1037 | + pinmux = ; /* SDMMC1_CK */ 1038 | + bias-pull-up; 1039 | + drive-push-pull; 1040 | + slew-rate = <2>; 1041 | + }; 1042 | + pins3 { 1043 | + u-boot,dm-pre-reloc; 1044 | + pinmux = ; /* SDMMC1_CMD */ 1045 | + bias-pull-up; 1046 | + drive-open-drain; 1047 | + slew-rate = <1>; 1048 | + }; 1049 | + }; 1050 | + 1051 | + sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { 1052 | + u-boot,dm-pre-reloc; 1053 | + pins { 1054 | + u-boot,dm-pre-reloc; 1055 | + pinmux = , /* SDMMC1_D0 */ 1056 | + , /* SDMMC1_D1 */ 1057 | + , /* SDMMC1_D2 */ 1058 | + , /* SDMMC1_D3 */ 1059 | + , /* SDMMC1_CK */ 1060 | + ; /* SDMMC1_CMD */ 1061 | + }; 1062 | + }; 1063 | + 1064 | + sdmmc2_pins_mx: sdmmc2_mx-0 { 1065 | + u-boot,dm-pre-reloc; 1066 | + pins1 { 1067 | + u-boot,dm-pre-reloc; 1068 | + pinmux = , /* SDMMC2_D4 */ 1069 | + , /* SDMMC2_D5 */ 1070 | + , /* SDMMC2_D2 */ 1071 | + , /* SDMMC2_D3 */ 1072 | + , /* SDMMC2_D0 */ 1073 | + , /* SDMMC2_D1 */ 1074 | + , /* SDMMC2_D7 */ 1075 | + , /* SDMMC2_D6 */ 1076 | + ; /* SDMMC2_CMD */ 1077 | + bias-pull-up; 1078 | + drive-push-pull; 1079 | + slew-rate = <1>; 1080 | + }; 1081 | + pins2 { 1082 | + u-boot,dm-pre-reloc; 1083 | + pinmux = ; /* SDMMC2_CK */ 1084 | + bias-pull-up; 1085 | + drive-push-pull; 1086 | + slew-rate = <2>; 1087 | + }; 1088 | + }; 1089 | + 1090 | + sdmmc2_opendrain_pins_mx: sdmmc2_opendrain_mx-0 { 1091 | + u-boot,dm-pre-reloc; 1092 | + pins1 { 1093 | + u-boot,dm-pre-reloc; 1094 | + pinmux = , /* SDMMC2_D4 */ 1095 | + , /* SDMMC2_D5 */ 1096 | + , /* SDMMC2_D2 */ 1097 | + , /* SDMMC2_D3 */ 1098 | + , /* SDMMC2_D0 */ 1099 | + , /* SDMMC2_D1 */ 1100 | + , /* SDMMC2_D7 */ 1101 | + ; /* SDMMC2_D6 */ 1102 | + bias-pull-up; 1103 | + drive-push-pull; 1104 | + slew-rate = <1>; 1105 | + }; 1106 | + pins2 { 1107 | + u-boot,dm-pre-reloc; 1108 | + pinmux = ; /* SDMMC2_CK */ 1109 | + bias-pull-up; 1110 | + drive-push-pull; 1111 | + slew-rate = <2>; 1112 | + }; 1113 | + pins3 { 1114 | + u-boot,dm-pre-reloc; 1115 | + pinmux = ; /* SDMMC2_CMD */ 1116 | + bias-pull-up; 1117 | + drive-open-drain; 1118 | + slew-rate = <1>; 1119 | + }; 1120 | + }; 1121 | + 1122 | + sdmmc2_sleep_pins_mx: sdmmc2_sleep_mx-0 { 1123 | + u-boot,dm-pre-reloc; 1124 | + pins { 1125 | + u-boot,dm-pre-reloc; 1126 | + pinmux = , /* SDMMC2_D4 */ 1127 | + , /* SDMMC2_D5 */ 1128 | + , /* SDMMC2_D2 */ 1129 | + , /* SDMMC2_D3 */ 1130 | + , /* SDMMC2_D0 */ 1131 | + , /* SDMMC2_D1 */ 1132 | + , /* SDMMC2_D7 */ 1133 | + , /* SDMMC2_CK */ 1134 | + , /* SDMMC2_D6 */ 1135 | + ; /* SDMMC2_CMD */ 1136 | + }; 1137 | + }; 1138 | + 1139 | + uart4_pins_mx: uart4_mx-0 { 1140 | + u-boot,dm-pre-reloc; 1141 | + pins1 { 1142 | + u-boot,dm-pre-reloc; 1143 | + pinmux = ; /* UART4_RX */ 1144 | + bias-disable; 1145 | + }; 1146 | + pins2 { 1147 | + u-boot,dm-pre-reloc; 1148 | + pinmux = ; /* UART4_TX */ 1149 | + bias-disable; 1150 | + drive-push-pull; 1151 | + slew-rate = <0>; 1152 | + }; 1153 | + }; 1154 | + 1155 | + uart4_sleep_pins_mx: uart4_sleep_mx-0 { 1156 | + u-boot,dm-pre-reloc; 1157 | + pins { 1158 | + u-boot,dm-pre-reloc; 1159 | + pinmux = , /* UART4_RX */ 1160 | + ; /* UART4_TX */ 1161 | + }; 1162 | + }; 1163 | + 1164 | + usb_otg_hs_pins_mx: usb_otg_hs_mx-0 { 1165 | + u-boot,dm-pre-reloc; 1166 | + pins { 1167 | + u-boot,dm-pre-reloc; 1168 | + pinmux = ; /* USB_OTG_HS_ID */ 1169 | + }; 1170 | + }; 1171 | + 1172 | + usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 { 1173 | + u-boot,dm-pre-reloc; 1174 | + pins { 1175 | + u-boot,dm-pre-reloc; 1176 | + pinmux = ; /* USB_OTG_HS_ID */ 1177 | + }; 1178 | + }; 1179 | + 1180 | + /* USER CODE BEGIN pinctrl */ 1181 | + usb_5v_power_pins_mx: usb_5v_power_mx-0 { 1182 | + u-boot,dm-pre-reloc; 1183 | + pins { 1184 | + u-boot,dm-pre-reloc; 1185 | + pinmux = , /* USB_POWER_EN */ 1186 | + ; /* USB_POWER_EN */ 1187 | + bias-disable; 1188 | + output-high; 1189 | + }; 1190 | + }; 1191 | + 1192 | + usb_5v_power_sleep_pins_mx: usb_5v_power_sleep_mx-0 { 1193 | + u-boot,dm-pre-reloc; 1194 | + pins { 1195 | + u-boot,dm-pre-reloc; 1196 | + pinmux = , /* USB_POWER_EN */ 1197 | + ; /* USB_POWER_EN */ 1198 | + bias-disable; 1199 | + output-low; 1200 | + }; 1201 | + }; 1202 | + 1203 | + usb_otg_5v_power_pins_mx: usb_otg_5v_power_mx-0 { 1204 | + u-boot,dm-pre-reloc; 1205 | + pins { 1206 | + u-boot,dm-pre-reloc; 1207 | + pinmux = ; /* USB_POWER_EN */ 1208 | + bias-disable; 1209 | + output-high; 1210 | + }; 1211 | + }; 1212 | + 1213 | + usb_otg_5v_power_sleep_pins_mx: usb_otg_5v_power_sleep_mx-0 { 1214 | + u-boot,dm-pre-reloc; 1215 | + pins { 1216 | + u-boot,dm-pre-reloc; 1217 | + pinmux = ; /* USB_POWER_EN */ 1218 | + bias-disable; 1219 | + output-low; 1220 | + }; 1221 | + }; 1222 | + 1223 | + /* USER CODE END pinctrl */ 1224 | +}; 1225 | + 1226 | +&pinctrl_z { 1227 | + u-boot,dm-pre-reloc; 1228 | + 1229 | + i2c4_pins_z_mx: i2c4_mx-0 { 1230 | + u-boot,dm-pre-reloc; 1231 | + pins { 1232 | + u-boot,dm-pre-reloc; 1233 | + pinmux = , /* I2C4_SCL */ 1234 | + ; /* I2C4_SDA */ 1235 | + bias-disable; 1236 | + drive-open-drain; 1237 | + slew-rate = <0>; 1238 | + }; 1239 | + }; 1240 | + 1241 | + i2c4_sleep_pins_z_mx: i2c4_sleep_mx-0 { 1242 | + u-boot,dm-pre-reloc; 1243 | + pins { 1244 | + u-boot,dm-pre-reloc; 1245 | + pinmux = , /* I2C4_SCL */ 1246 | + ; /* I2C4_SDA */ 1247 | + }; 1248 | + }; 1249 | + 1250 | + /* USER CODE BEGIN pinctrl_z */ 1251 | + /* USER CODE END pinctrl_z */ 1252 | +}; 1253 | + 1254 | +&m4_rproc{ 1255 | + /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/ 1256 | + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; 1257 | + mbox-names = "vq0", "vq1", "shutdown"; 1258 | + status = "okay"; 1259 | + 1260 | + /* USER CODE BEGIN m4_rproc */ 1261 | + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, 1262 | + <&vdev0vring1>, <&vdev0buffer>, <&mcu_rsc_table>; 1263 | + interrupt-parent = <&exti>; 1264 | + interrupts = <68 1>; 1265 | + wakeup-source; 1266 | + /* USER CODE END m4_rproc */ 1267 | +}; 1268 | + 1269 | +&adc{ 1270 | + status = "okay"; 1271 | + 1272 | + /* USER CODE BEGIN adc */ 1273 | + /* USER CODE END adc */ 1274 | +}; 1275 | + 1276 | +&bsec{ 1277 | + status = "okay"; 1278 | + 1279 | + /* USER CODE BEGIN bsec */ 1280 | + /* USER CODE END bsec */ 1281 | +}; 1282 | + 1283 | +&crc1{ 1284 | + status = "okay"; 1285 | + 1286 | + /* USER CODE BEGIN crc1 */ 1287 | + /* USER CODE END crc1 */ 1288 | +}; 1289 | + 1290 | +&dcmi{ 1291 | + pinctrl-names = "default", "sleep"; 1292 | + pinctrl-0 = <&dcmi_pins_mx>; 1293 | + pinctrl-1 = <&dcmi_sleep_pins_mx>; 1294 | + status = "okay"; 1295 | + 1296 | + /* USER CODE BEGIN dcmi */ 1297 | + 1298 | + port{ 1299 | + 1300 | + dcmi_0:endpoint{ 1301 | + remote-endpoint = <&ov5640_0>; 1302 | + bus-type = <5>; 1303 | + bus-width = <8>; 1304 | + hsync-active = <0>; 1305 | + vsync-active = <0>; 1306 | + pclk-sample = <1>; 1307 | + pclk-max-frequency = <77000000>; 1308 | + }; 1309 | + }; 1310 | + /* USER CODE END dcmi */ 1311 | +}; 1312 | + 1313 | +&dma1{ 1314 | + status = "okay"; 1315 | + 1316 | + /* USER CODE BEGIN dma1 */ 1317 | + sram = <&dma_pool>; 1318 | + /* USER CODE END dma1 */ 1319 | +}; 1320 | + 1321 | +&dma2{ 1322 | + status = "okay"; 1323 | + 1324 | + /* USER CODE BEGIN dma2 */ 1325 | + sram = <&dma_pool>; 1326 | + /* USER CODE END dma2 */ 1327 | +}; 1328 | + 1329 | +&dmamux1{ 1330 | + status = "okay"; 1331 | + 1332 | + dma-masters = <&dma1 &dma2>; 1333 | + dma-channels = <16>; 1334 | + 1335 | + /* USER CODE BEGIN dmamux1 */ 1336 | + /* USER CODE END dmamux1 */ 1337 | +}; 1338 | + 1339 | +&dts{ 1340 | + status = "okay"; 1341 | + 1342 | + /* USER CODE BEGIN dts */ 1343 | + /* USER CODE END dts */ 1344 | +}; 1345 | + 1346 | +ðernet0{ 1347 | + pinctrl-names = "default", "sleep"; 1348 | + pinctrl-0 = <ð1_pins_mx>; 1349 | + pinctrl-1 = <ð1_sleep_pins_mx>; 1350 | + status = "okay"; 1351 | + 1352 | + /* USER CODE BEGIN ethernet0 */ 1353 | + phy-mode = "rgmii-id"; 1354 | + max-speed = <1000>; 1355 | + phy-handle = <&phy0>; 1356 | + nvmem-cells = <ðernet_mac_address>; 1357 | + nvmem-cell-names = "mac-address"; 1358 | + 1359 | + mdio0{ 1360 | + #address-cells = <1>; 1361 | + #size-cells = <0>; 1362 | + compatible = "snps,dwmac-mdio"; 1363 | + 1364 | + phy0:ethernet-phy@0{ 1365 | + reg = <0>; 1366 | + }; 1367 | + }; 1368 | + /* USER CODE END ethernet0 */ 1369 | +}; 1370 | + 1371 | +&gpu{ 1372 | + status = "okay"; 1373 | + 1374 | + /* USER CODE BEGIN gpu */ 1375 | + contiguous-area = <&gpu_reserved>; 1376 | + /* USER CODE END gpu */ 1377 | +}; 1378 | + 1379 | +&hash1{ 1380 | + u-boot,dm-pre-reloc; 1381 | + status = "okay"; 1382 | + 1383 | + /* USER CODE BEGIN hash1 */ 1384 | + /* USER CODE END hash1 */ 1385 | +}; 1386 | + 1387 | +&hsem{ 1388 | + status = "okay"; 1389 | + 1390 | + /* USER CODE BEGIN hsem */ 1391 | + /* USER CODE END hsem */ 1392 | +}; 1393 | + 1394 | +&i2c2{ 1395 | + pinctrl-names = "default", "sleep"; 1396 | + pinctrl-0 = <&i2c2_pins_mx>; 1397 | + pinctrl-1 = <&i2c2_sleep_pins_mx>; 1398 | + status = "okay"; 1399 | + 1400 | + /* USER CODE BEGIN i2c2 */ 1401 | + i2c-scl-rising-time-ns = <185>; 1402 | + i2c-scl-falling-time-ns = <20>; 1403 | + /delete-property/ dmas; 1404 | + /delete-property/ dma-names; 1405 | + 1406 | + 1407 | + ov5640:camera@3c{ 1408 | + compatible = "ovti,ov5640"; 1409 | + reg = <0x3c>; 1410 | + clocks = <&clk_ext_camera>; 1411 | + clock-names = "xclk"; 1412 | + DOVDD-supply = <&v2v8>; 1413 | + powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>; 1414 | + reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; 1415 | + rotation = <180>; 1416 | + status = "okay"; 1417 | + 1418 | + port{ 1419 | + 1420 | + ov5640_0:endpoint{ 1421 | + remote-endpoint = <&dcmi_0>; 1422 | + bus-width = <8>; 1423 | + data-shift = <2>; 1424 | + hsync-active = <0>; 1425 | + vsync-active = <0>; 1426 | + pclk-sample = <1>; 1427 | + pclk-max-frequency = <77000000>; 1428 | + }; 1429 | + }; 1430 | + }; 1431 | + 1432 | + stmfx:stmfx@42{ 1433 | + compatible = "st,stmfx-0300"; 1434 | + reg = <0x42>; 1435 | + interrupts = <8 IRQ_TYPE_EDGE_RISING>; 1436 | + interrupt-parent = <&gpioi>; 1437 | + vdd-supply = <&v3v3>; 1438 | + 1439 | + stmfx_pinctrl:pinctrl{ 1440 | + compatible = "st,stmfx-0300-pinctrl"; 1441 | + gpio-controller; 1442 | + #gpio-cells = <2>; 1443 | + interrupt-controller; 1444 | + #interrupt-cells = <2>; 1445 | + gpio-ranges = <&stmfx_pinctrl 0 0 24>; 1446 | + 1447 | + goodix_pins:goodix{ 1448 | + pins = "gpio14"; 1449 | + bias-pull-down; 1450 | + }; 1451 | + 1452 | + }; 1453 | + }; 1454 | + 1455 | + /* 1456 | + gt9147:goodix_ts@5d{ 1457 | + compatible = "goodix,gt9147"; 1458 | + reg = <0x5d>; 1459 | + panel = <&panel_dsi>; 1460 | + pinctrl-0 = <&goodix_pins>; 1461 | + pinctrl-names = "default"; 1462 | + status = "okay"; 1463 | + interrupts = <14 IRQ_TYPE_EDGE_RISING>; 1464 | + interrupt-parent = <&stmfx_pinctrl>; 1465 | + }; 1466 | + */ 1467 | + gt911_rgb: touchscreen@14 { 1468 | + compatible = "goodix,gt911"; 1469 | + //reg = <0x5d>; 1470 | + reg = <0x14>; 1471 | + interrupt-parent = <&gpiog>; 1472 | + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 1473 | + irq-flags = ; 1474 | + irq-gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; 1475 | + reset-gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; 1476 | + panel = <&lcd0>; 1477 | + status = "okay"; 1478 | + }; 1479 | + 1480 | + pcf8574a: gpio@38 { 1481 | + compatible = "nxp,pcf8574a"; 1482 | + reg = <0x38>; 1483 | + gpio-controller; 1484 | + #gpio-cells = <2>; 1485 | + lines-initial-states = <0>; 1486 | + status = "okay"; 1487 | + }; 1488 | + 1489 | + pcf8574a_ext: gpio@3f { 1490 | + compatible = "nxp,pcf8574a"; 1491 | + reg = <0x3f>; 1492 | + gpio-controller; 1493 | + #gpio-cells = <2>; 1494 | + lines-initial-states = <0>; 1495 | + status = "okay"; 1496 | + }; 1497 | + 1498 | + /* USER CODE END i2c2 */ 1499 | +}; 1500 | + 1501 | +&i2c4{ 1502 | + u-boot,dm-pre-reloc; 1503 | + pinctrl-names = "default", "sleep"; 1504 | + pinctrl-0 = <&i2c4_pins_z_mx>; 1505 | + pinctrl-1 = <&i2c4_sleep_pins_z_mx>; 1506 | + status = "okay"; 1507 | + 1508 | + /* USER CODE BEGIN i2c4 */ 1509 | + i2c-scl-rising-time-ns = <185>; 1510 | + i2c-scl-falling-time-ns = <20>; 1511 | + clock-frequency = <400000>; 1512 | + /delete-property/ dmas; 1513 | + /delete-property/ dma-names; 1514 | + 1515 | + pmic:stpmic@33{ 1516 | + compatible = "st,stpmic1"; 1517 | + reg = <0x33>; 1518 | + interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 1519 | + interrupt-controller; 1520 | + #interrupt-cells = <2>; 1521 | + status = "okay"; 1522 | + 1523 | + regulators{ 1524 | + compatible = "st,stpmic1-regulators"; 1525 | + buck1-supply = <&vin>; 1526 | + buck2-supply = <&vin>; 1527 | + buck3-supply = <&vin>; 1528 | + buck4-supply = <&vin>; 1529 | + ldo1-supply = <&v3v3>; 1530 | + ldo2-supply = <&v3v3>; 1531 | + ldo3-supply = <&vdd_ddr>; 1532 | + ldo4-supply = <&vin>; 1533 | + ldo5-supply = <&v3v3>; 1534 | + ldo6-supply = <&v3v3>; 1535 | + vref_ddr-supply = <&vin>; 1536 | + boost-supply = <&vin>; 1537 | + pwr_sw1-supply = <&bst_out>; 1538 | + pwr_sw2-supply = <&bst_out>; 1539 | + 1540 | + vddcore:buck1{ 1541 | + regulator-name = "vddcore"; 1542 | + regulator-min-microvolt = <1200000>; 1543 | + regulator-max-microvolt = <1350000>; 1544 | + regulator-always-on; 1545 | + regulator-initial-mode = <0>; 1546 | + regulator-over-current-protection; 1547 | + }; 1548 | + 1549 | + vdd_ddr:buck2{ 1550 | + regulator-name = "vdd_ddr"; 1551 | + regulator-min-microvolt = <1350000>; 1552 | + regulator-max-microvolt = <1350000>; 1553 | + regulator-always-on; 1554 | + regulator-initial-mode = <0>; 1555 | + regulator-over-current-protection; 1556 | + }; 1557 | + 1558 | + vdd:buck3{ 1559 | + regulator-name = "vdd"; 1560 | + regulator-min-microvolt = <3300000>; 1561 | + regulator-max-microvolt = <3300000>; 1562 | + regulator-always-on; 1563 | + st,mask-reset; 1564 | + regulator-initial-mode = <0>; 1565 | + regulator-over-current-protection; 1566 | + }; 1567 | + 1568 | + v3v3:buck4{ 1569 | + regulator-name = "v3v3"; 1570 | + regulator-min-microvolt = <3300000>; 1571 | + regulator-max-microvolt = <3300000>; 1572 | + regulator-always-on; 1573 | + regulator-over-current-protection; 1574 | + regulator-initial-mode = <0>; 1575 | + }; 1576 | + 1577 | + vdda:ldo1{ 1578 | + regulator-name = "vdda"; 1579 | + regulator-min-microvolt = <2900000>; 1580 | + regulator-max-microvolt = <2900000>; 1581 | + interrupts = ; 1582 | + }; 1583 | + 1584 | + v2v8:ldo2{ 1585 | + regulator-name = "v2v8"; 1586 | + regulator-min-microvolt = <2800000>; 1587 | + regulator-max-microvolt = <2800000>; 1588 | + interrupts = ; 1589 | + }; 1590 | + 1591 | + vtt_ddr:ldo3{ 1592 | + regulator-name = "vtt_ddr"; 1593 | + regulator-min-microvolt = <500000>; 1594 | + regulator-max-microvolt = <750000>; 1595 | + regulator-always-on; 1596 | + regulator-over-current-protection; 1597 | + }; 1598 | + 1599 | + vdd_usb:ldo4{ 1600 | + regulator-name = "vdd_usb"; 1601 | + regulator-min-microvolt = <3300000>; 1602 | + regulator-max-microvolt = <3300000>; 1603 | + interrupts = ; 1604 | + }; 1605 | + 1606 | + vdd_sd:ldo5{ 1607 | + regulator-name = "vdd_sd"; 1608 | + regulator-min-microvolt = <2900000>; 1609 | + regulator-max-microvolt = <2900000>; 1610 | + interrupts = ; 1611 | + regulator-boot-on; 1612 | + }; 1613 | + 1614 | + v1v8:ldo6{ 1615 | + regulator-name = "v1v8"; 1616 | + regulator-min-microvolt = <1800000>; 1617 | + regulator-max-microvolt = <1800000>; 1618 | + interrupts = ; 1619 | + regulator-enable-ramp-delay = <300000>; 1620 | + }; 1621 | + 1622 | + vref_ddr:vref_ddr{ 1623 | + regulator-name = "vref_ddr"; 1624 | + regulator-always-on; 1625 | + regulator-over-current-protection; 1626 | + }; 1627 | + 1628 | + bst_out:boost{ 1629 | + regulator-name = "bst_out"; 1630 | + interrupts = ; 1631 | + }; 1632 | + 1633 | + vbus_otg:pwr_sw1{ 1634 | + regulator-name = "vbus_otg"; 1635 | + interrupts = ; 1636 | + }; 1637 | + 1638 | + vbus_sw:pwr_sw2{ 1639 | + regulator-name = "vbus_sw"; 1640 | + interrupts = ; 1641 | + regulator-active-discharge = <1>; 1642 | + }; 1643 | + }; 1644 | + 1645 | + onkey{ 1646 | + compatible = "st,stpmic1-onkey"; 1647 | + interrupts = , ; 1648 | + interrupt-names = "onkey-falling", "onkey-rising"; 1649 | + power-off-time-sec = <10>; 1650 | + status = "okay"; 1651 | + }; 1652 | + 1653 | + watchdog{ 1654 | + compatible = "st,stpmic1-wdt"; 1655 | + status = "disabled"; 1656 | + }; 1657 | + }; 1658 | + /* USER CODE END i2c4 */ 1659 | +}; 1660 | + 1661 | +&i2c5{ 1662 | + pinctrl-names = "default", "sleep"; 1663 | + pinctrl-0 = <&i2c5_pins_mx>; 1664 | + pinctrl-1 = <&i2c5_sleep_pins_mx>; 1665 | + status = "okay"; 1666 | + 1667 | + /* USER CODE BEGIN i2c5 */ 1668 | + i2c-scl-rising-time-ns = <185>; 1669 | + i2c-scl-falling-time-ns = <20>; 1670 | + /delete-property/ dmas; 1671 | + /delete-property/ dma-names; 1672 | + /* USER CODE END i2c5 */ 1673 | +}; 1674 | + 1675 | +&ipcc{ 1676 | + status = "okay"; 1677 | + 1678 | + /* USER CODE BEGIN ipcc */ 1679 | + /* USER CODE END ipcc */ 1680 | +}; 1681 | + 1682 | +&iwdg2{ 1683 | + u-boot,dm-pre-reloc; 1684 | + status = "okay"; 1685 | + 1686 | + /* USER CODE BEGIN iwdg2 */ 1687 | + timeout-sec = <32>; 1688 | + /* USER CODE END iwdg2 */ 1689 | +}; 1690 | + 1691 | +<dc{ 1692 | + pinctrl-names = "default", "sleep"; 1693 | + pinctrl-0 = <<dc_pins_mx>; 1694 | + pinctrl-1 = <<dc_sleep_pins_mx>; 1695 | + status = "okay"; 1696 | + 1697 | + /* USER CODE BEGIN ltdc */ 1698 | + 1699 | + port{ 1700 | + 1701 | + ltdc_ep0_out:endpoint@0{ 1702 | + reg = <0>; 1703 | + remote-endpoint = <&dsi_in>; 1704 | + }; 1705 | + }; 1706 | + /* USER CODE END ltdc */ 1707 | +}; 1708 | + 1709 | +&m_can1{ 1710 | + pinctrl-names = "default", "sleep"; 1711 | + pinctrl-0 = <&fdcan1_pins_mx>; 1712 | + pinctrl-1 = <&fdcan1_sleep_pins_mx>; 1713 | + status = "okay"; 1714 | + 1715 | + /* USER CODE BEGIN m_can1 */ 1716 | + /* USER CODE END m_can1 */ 1717 | +}; 1718 | + 1719 | +&m_can2{ 1720 | + pinctrl-names = "default", "sleep"; 1721 | + pinctrl-0 = <&fdcan2_pins_mx>; 1722 | + pinctrl-1 = <&fdcan2_sleep_pins_mx>; 1723 | + status = "okay"; 1724 | + 1725 | + /* USER CODE BEGIN m_can2 */ 1726 | + /* USER CODE END m_can2 */ 1727 | +}; 1728 | + 1729 | +&mdma1{ 1730 | + status = "okay"; 1731 | + 1732 | + /* USER CODE BEGIN mdma1 */ 1733 | + /* USER CODE END mdma1 */ 1734 | +}; 1735 | + 1736 | +&pwr_regulators{ 1737 | + status = "okay"; 1738 | + 1739 | + /* USER CODE BEGIN pwr_regulators */ 1740 | + vdd-supply = <&vdd>; 1741 | + vdd_3v3_usbfs-supply = <&vdd_usb>; 1742 | + vbus-supply = <®_5v_host>; 1743 | + /* USER CODE END pwr_regulators */ 1744 | +}; 1745 | + 1746 | +&qspi{ 1747 | + u-boot,dm-pre-reloc; 1748 | + pinctrl-names = "default", "sleep"; 1749 | + pinctrl-0 = <&quadspi_pins_mx>; 1750 | + pinctrl-1 = <&quadspi_sleep_pins_mx>; 1751 | + status = "okay"; 1752 | + 1753 | + /* USER CODE BEGIN qspi */ 1754 | + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; 1755 | + #address-cells = <1>; 1756 | + #size-cells = <0>; 1757 | + 1758 | + flash0:mx66l51235l@0{ 1759 | + compatible = "jedec,spi-nor"; 1760 | + reg = <0>; 1761 | + spi-rx-bus-width = <4>; 1762 | + spi-max-frequency = <108000000>; 1763 | + #address-cells = <1>; 1764 | + #size-cells = <1>; 1765 | + }; 1766 | + 1767 | + flash1:mx66l51235l@1{ 1768 | + compatible = "jedec,spi-nor"; 1769 | + reg = <1>; 1770 | + spi-rx-bus-width = <4>; 1771 | + spi-max-frequency = <108000000>; 1772 | + #address-cells = <1>; 1773 | + #size-cells = <1>; 1774 | + }; 1775 | + /* USER CODE END qspi */ 1776 | +}; 1777 | + 1778 | +&rcc{ 1779 | + u-boot,dm-pre-reloc; 1780 | + status = "okay"; 1781 | + 1782 | + /* USER CODE BEGIN rcc */ 1783 | + /* USER CODE END rcc */ 1784 | +}; 1785 | + 1786 | +&rng1{ 1787 | + status = "okay"; 1788 | + 1789 | + /* USER CODE BEGIN rng1 */ 1790 | + /* USER CODE END rng1 */ 1791 | +}; 1792 | + 1793 | +&rtc{ 1794 | + status = "okay"; 1795 | + 1796 | + /* USER CODE BEGIN rtc */ 1797 | + /* USER CODE END rtc */ 1798 | +}; 1799 | + 1800 | +&sdmmc1{ 1801 | + u-boot,dm-pre-reloc; 1802 | + pinctrl-names = "default", "opendrain", "sleep"; 1803 | + pinctrl-0 = <&sdmmc1_pins_mx>; 1804 | + pinctrl-1 = <&sdmmc1_opendrain_pins_mx>; 1805 | + pinctrl-2 = <&sdmmc1_sleep_pins_mx>; 1806 | + status = "okay"; 1807 | + 1808 | + /* USER CODE BEGIN sdmmc1 */ 1809 | + broken-cd; 1810 | + st,neg-edge; 1811 | + bus-width = <4>; 1812 | + vmmc-supply = <&vdd_sd>; 1813 | + /* USER CODE END sdmmc1 */ 1814 | +}; 1815 | + 1816 | +&sdmmc2{ 1817 | + u-boot,dm-pre-reloc; 1818 | + pinctrl-names = "default", "opendrain", "sleep"; 1819 | + pinctrl-0 = <&sdmmc2_pins_mx>; 1820 | + pinctrl-1 = <&sdmmc2_opendrain_pins_mx>; 1821 | + pinctrl-2 = <&sdmmc2_sleep_pins_mx>; 1822 | + status = "okay"; 1823 | + 1824 | + /* USER CODE BEGIN sdmmc2 */ 1825 | + non-removable; 1826 | + no-sd; 1827 | + no-sdio; 1828 | + st,neg-edge; 1829 | + bus-width = <8>; 1830 | + vmmc-supply = <&v3v3>; 1831 | + vqmmc-supply = <&vdd>; 1832 | + mmc-ddr-3_3v; 1833 | + /* USER CODE END sdmmc2 */ 1834 | +}; 1835 | + 1836 | +&tamp{ 1837 | + status = "okay"; 1838 | + 1839 | + /* USER CODE BEGIN tamp */ 1840 | + /* USER CODE END tamp */ 1841 | +}; 1842 | + 1843 | +&timers6{ 1844 | + status = "okay"; 1845 | + 1846 | + /* USER CODE BEGIN timers6 */ 1847 | + /delete-property/ dmas; 1848 | + /delete-property/ dma-names; 1849 | + 1850 | + timer@5{ 1851 | + status = "okay"; 1852 | + }; 1853 | + /* USER CODE END timers6 */ 1854 | +}; 1855 | + 1856 | +&uart4{ 1857 | + u-boot,dm-pre-reloc; 1858 | + pinctrl-names = "default", "sleep"; 1859 | + pinctrl-0 = <&uart4_pins_mx>; 1860 | + pinctrl-1 = <&uart4_sleep_pins_mx>; 1861 | + status = "okay"; 1862 | + 1863 | + /* USER CODE BEGIN uart4 */ 1864 | + /delete-property/ dmas; 1865 | + /delete-property/ dma-names; 1866 | + /* USER CODE END uart4 */ 1867 | +}; 1868 | + 1869 | +&usbh_ehci{ 1870 | + status = "okay"; 1871 | + 1872 | + /* USER CODE BEGIN usbh_ehci */ 1873 | + phys = <&usbphyc_port0>; 1874 | + phy-names = "usb"; 1875 | + vbus-supply = <®_5v_host>; 1876 | + /* USER CODE END usbh_ehci */ 1877 | +}; 1878 | + 1879 | +&usbh_ohci{ 1880 | + status = "okay"; 1881 | + 1882 | + /* USER CODE BEGIN usbh_ohci */ 1883 | + vbus-supply = <®_5v_host>; 1884 | + /* USER CODE END usbh_ohci */ 1885 | +}; 1886 | + 1887 | +&usbotg_hs{ 1888 | + u-boot,dm-pre-reloc; 1889 | + pinctrl-names = "default", "sleep"; 1890 | + pinctrl-0 = <&usb_otg_hs_pins_mx>; 1891 | + pinctrl-1 = <&usb_otg_hs_sleep_pins_mx>; 1892 | + status = "okay"; 1893 | + 1894 | + /* USER CODE BEGIN usbotg_hs */ 1895 | + //vbus-supply = <&vbus_otg>; 1896 | + vbus-supply = <®_5v_otg>; 1897 | + phys = <&usbphyc_port1 0>; 1898 | + phy-names = "usb2-phy"; 1899 | + /* USER CODE END usbotg_hs */ 1900 | +}; 1901 | + 1902 | +&usbphyc{ 1903 | + u-boot,dm-pre-reloc; 1904 | + status = "okay"; 1905 | + 1906 | + /* USER CODE BEGIN usbphyc */ 1907 | + /* USER CODE END usbphyc */ 1908 | +}; 1909 | + 1910 | +&usbphyc_port0{ 1911 | + u-boot,dm-pre-reloc; 1912 | + status = "okay"; 1913 | + 1914 | + /* USER CODE BEGIN usbphyc_port0 */ 1915 | + phy-supply = <&vdd_usb>; 1916 | + st,phy-tuning = <&usb_phy_tuning>; 1917 | + vbus-supply = <®_5v_host>; 1918 | + 1919 | + connector{ 1920 | + compatible = "usb-a-connector"; 1921 | + vbus-supply = <&v3v3>; 1922 | + }; 1923 | + /* USER CODE END usbphyc_port0 */ 1924 | +}; 1925 | + 1926 | +&usbphyc_port1{ 1927 | + u-boot,dm-pre-reloc; 1928 | + status = "okay"; 1929 | + 1930 | + /* USER CODE BEGIN usbphyc_port1 */ 1931 | + phy-supply = <&vdd_usb>; 1932 | + st,phy-tuning = <&usb_phy_tuning>; 1933 | + vbus-supply = <®_5v_host>; 1934 | + /* USER CODE END usbphyc_port1 */ 1935 | +}; 1936 | + 1937 | +/* USER CODE BEGIN addons */ 1938 | + 1939 | +&cpu0{ 1940 | + cpu-supply = <&vddcore>; 1941 | + clock-frequency = <650000000>; 1942 | +}; 1943 | + 1944 | +&cpu1{ 1945 | + cpu-supply = <&vddcore>; 1946 | + clock-frequency = <650000000>; 1947 | +}; 1948 | + 1949 | +&sram{ 1950 | + 1951 | + dma_pool:dma_pool@0{ 1952 | + reg = <0x50000 0x10000>; 1953 | + pool; 1954 | + }; 1955 | +}; 1956 | + 1957 | +&usbh_ohci { 1958 | + phys = <&usbphyc_port0>; 1959 | + phy-names = "usb"; 1960 | + vbus-supply = <&vbus_sw>; 1961 | +}; 1962 | +/* USER CODE END addons */ 1963 | --------------------------------------------------------------------------------