├── DVI.v ├── DVI_tb.v ├── LICENSE.txt ├── Pano.ucf ├── Pano.v └── README.md /DVI.v: -------------------------------------------------------------------------------- 1 | module dvi_top( 2 | input SYSCLK, 3 | 4 | input PANO_BUTTON, 5 | 6 | inout V_SPD, 7 | output V_SPC, 8 | 9 | output [11:0] V1_D, 10 | output V1_XCLK_P, 11 | output V1_XCLK_N, 12 | output reg V1_HSYNC, 13 | output reg V1_VSYNC, 14 | output reg V1_DE, 15 | output V1_RESET_N 16 | ); 17 | 18 | // Video timing parameters 19 | parameter X_RESOLUTION = 640; 20 | parameter X_FRONT_PORCH = 16; 21 | parameter X_SYNC_PULSE = 96; 22 | parameter X_BACK_PORCH = 48; 23 | parameter Y_RESOLUTION = 480; 24 | parameter Y_FRONT_PORCH = 12; 25 | parameter Y_SYNC_PULSE = 2; 26 | parameter Y_BACK_PORCH = 31; 27 | 28 | // Global reset signal 29 | wire reset_n = PANO_BUTTON; 30 | 31 | // Buffer I/O 32 | wire sysclk_ibuf; 33 | wire dcm_clk0; 34 | wire dcm_clk0_bufg; 35 | wire dcm_clk90; 36 | wire dcm_locked; 37 | 38 | // Buffers 39 | IBUFG IBUFG0(.I(SYSCLK), .O(sysclk_ibuf)); 40 | BUFG BUFG0(.I(dcm_clk0), .O(dcm_clk0_bufg)); 41 | 42 | // Clock generator 43 | DCM_SP #( 44 | .CLKDV_DIVIDE (2.0), 45 | .CLKFX_MULTIPLY (2), 46 | .CLKFX_DIVIDE (1), 47 | .CLKIN_PERIOD (40.0) 48 | ) 49 | dcm0 ( 50 | .CLKIN (sysclk_ibuf), 51 | .CLKFB (dcm_clk0_bufg), 52 | .DSSEN (1'b0), 53 | .PSINCDEC (1'b0), 54 | .PSEN (1'b0), 55 | .PSCLK (1'b0), 56 | .RST (!reset_n), 57 | .CLK0 (dcm_clk0), 58 | .CLK90 (dcm_clk90), 59 | .CLK180 (), 60 | .CLK270 (), 61 | .CLK2X (), 62 | .CLK2X180 (), 63 | .CLKDV (), 64 | .CLKFX (), 65 | .CLKFX180 (), 66 | .LOCKED (dcm_locked), 67 | .PSDONE () 68 | ); 69 | 70 | // Positive pixel clock output 71 | ODDR2 #( 72 | .DDR_ALIGNMENT ("C0"), 73 | .SRTYPE ("ASYNC") 74 | ) 75 | clkout_oddr_p( 76 | .Q (V1_XCLK_P), 77 | .C0 (dcm_clk90), 78 | .C1 (!dcm_clk90), 79 | .CE (1'b1), 80 | .D0 (1'b1), 81 | .D1 (1'b0), 82 | .R (!reset_n), 83 | .S (1'b0) 84 | ); 85 | 86 | // Negative pixel clock output 87 | ODDR2 #( 88 | .DDR_ALIGNMENT ("C0"), 89 | .SRTYPE ("ASYNC") 90 | ) 91 | clkout_oddr_n( 92 | .Q (V1_XCLK_N), 93 | .C0 (dcm_clk90), 94 | .C1 (!dcm_clk90), 95 | .CE (1'b1), 96 | .D0 (1'b0), 97 | .D1 (1'b1), 98 | .R (!reset_n), 99 | .S (1'b0) 100 | ); 101 | 102 | // TODO: Implement I2C 103 | assign V_SPD = 1'b1; 104 | assign V_SPC = 1'b1; 105 | 106 | // Video signals 107 | reg [31:0] x_counter; 108 | reg [31:0] y_counter; 109 | wire hsync = (x_counter < X_RESOLUTION + X_FRONT_PORCH) || (x_counter >= X_RESOLUTION + X_FRONT_PORCH + X_SYNC_PULSE); 110 | wire vsync = (y_counter < Y_RESOLUTION + Y_FRONT_PORCH) || (y_counter >= Y_RESOLUTION + Y_FRONT_PORCH + Y_SYNC_PULSE); 111 | wire data_enable = (x_counter < X_RESOLUTION) && (y_counter < Y_RESOLUTION); 112 | 113 | // Chrontel reset 114 | assign V1_RESET_N = reset_n && dcm_locked; 115 | 116 | // Static pixel data 117 | wire [7:0] pixel_red = 8'hff; 118 | wire [7:0] pixel_green = 8'hf0; 119 | wire [7:0] pixel_blue = 8'h0f; 120 | 121 | // Main block 122 | always @(posedge dcm_clk0, negedge reset_n, negedge dcm_locked) begin 123 | if (!reset_n || !dcm_locked) begin 124 | x_counter <= 0; 125 | y_counter <= 0; 126 | V1_HSYNC <= 1; 127 | V1_VSYNC <= 1; 128 | V1_DE <= 0; 129 | end else begin 130 | V1_HSYNC <= hsync; 131 | V1_VSYNC <= vsync; 132 | V1_DE <= data_enable; 133 | if (x_counter==X_RESOLUTION + X_FRONT_PORCH + X_SYNC_PULSE + X_BACK_PORCH - 1) begin 134 | x_counter <= 0; 135 | if (y_counter==Y_RESOLUTION + Y_FRONT_PORCH + Y_SYNC_PULSE + Y_BACK_PORCH - 1) 136 | y_counter <= 0; 137 | else 138 | y_counter <= y_counter + 1; 139 | end else begin 140 | x_counter <= x_counter + 1; 141 | end 142 | end 143 | end 144 | 145 | // Pixel data DDR blocks 146 | ODDR2 #( 147 | .DDR_ALIGNMENT ("C0"), 148 | .SRTYPE ("ASYNC") 149 | ) 150 | v1_d_11( 151 | .Q (V1_D[11]), 152 | .C0 (dcm_clk0), 153 | .C1 (!dcm_clk0), 154 | .CE (1'b1), 155 | .D0 (pixel_green[3]), 156 | .D1 (pixel_red[7]), 157 | .R (!reset_n), 158 | .S (1'b0) 159 | ); 160 | ODDR2 #( 161 | .DDR_ALIGNMENT ("C0"), 162 | .SRTYPE ("ASYNC") 163 | ) 164 | v1_d_10( 165 | .Q (V1_D[10]), 166 | .C0 (dcm_clk0), 167 | .C1 (!dcm_clk0), 168 | .CE (1'b1), 169 | .D0 (pixel_green[2]), 170 | .D1 (pixel_red[6]), 171 | .R (!reset_n), 172 | .S (1'b0) 173 | ); 174 | ODDR2 #( 175 | .DDR_ALIGNMENT ("C0"), 176 | .SRTYPE ("ASYNC") 177 | ) 178 | v1_d_9( 179 | .Q (V1_D[9]), 180 | .C0 (dcm_clk0), 181 | .C1 (!dcm_clk0), 182 | .CE (1'b1), 183 | .D0 (pixel_green[1]), 184 | .D1 (pixel_red[5]), 185 | .R (!reset_n), 186 | .S (1'b0) 187 | ); 188 | ODDR2 #( 189 | .DDR_ALIGNMENT ("C0"), 190 | .SRTYPE ("ASYNC") 191 | ) 192 | v1_d_8( 193 | .Q (V1_D[8]), 194 | .C0 (dcm_clk0), 195 | .C1 (!dcm_clk0), 196 | .CE (1'b1), 197 | .D0 (pixel_green[0]), 198 | .D1 (pixel_red[4]), 199 | .R (!reset_n), 200 | .S (1'b0) 201 | ); 202 | ODDR2 #( 203 | .DDR_ALIGNMENT ("C0"), 204 | .SRTYPE ("ASYNC") 205 | ) 206 | v1_d_7( 207 | .Q (V1_D[7]), 208 | .C0 (dcm_clk0), 209 | .C1 (!dcm_clk0), 210 | .CE (1'b1), 211 | .D0 (pixel_blue[7]), 212 | .D1 (pixel_red[3]), 213 | .R (!reset_n), 214 | .S (1'b0) 215 | ); 216 | ODDR2 #( 217 | .DDR_ALIGNMENT ("C0"), 218 | .SRTYPE ("ASYNC") 219 | ) 220 | v1_d_6( 221 | .Q (V1_D[6]), 222 | .C0 (dcm_clk0), 223 | .C1 (!dcm_clk0), 224 | .CE (1'b1), 225 | .D0 (pixel_blue[6]), 226 | .D1 (pixel_red[2]), 227 | .R (!reset_n), 228 | .S (1'b0) 229 | ); 230 | ODDR2 #( 231 | .DDR_ALIGNMENT ("C0"), 232 | .SRTYPE ("ASYNC") 233 | ) 234 | v1_d_5( 235 | .Q (V1_D[5]), 236 | .C0 (dcm_clk0), 237 | .C1 (!dcm_clk0), 238 | .CE (1'b1), 239 | .D0 (pixel_blue[5]), 240 | .D1 (pixel_red[1]), 241 | .R (!reset_n), 242 | .S (1'b0) 243 | ); 244 | ODDR2 #( 245 | .DDR_ALIGNMENT ("C0"), 246 | .SRTYPE ("ASYNC") 247 | ) 248 | v1_d_4( 249 | .Q (V1_D[4]), 250 | .C0 (dcm_clk0), 251 | .C1 (!dcm_clk0), 252 | .CE (1'b1), 253 | .D0 (pixel_blue[4]), 254 | .D1 (pixel_red[0]), 255 | .R (!reset_n), 256 | .S (1'b0) 257 | ); 258 | ODDR2 #( 259 | .DDR_ALIGNMENT ("C0"), 260 | .SRTYPE ("ASYNC") 261 | ) 262 | v1_d_3( 263 | .Q (V1_D[3]), 264 | .C0 (dcm_clk0), 265 | .C1 (!dcm_clk0), 266 | .CE (1'b1), 267 | .D0 (pixel_blue[3]), 268 | .D1 (pixel_green[7]), 269 | .R (!reset_n), 270 | .S (1'b0) 271 | ); 272 | ODDR2 #( 273 | .DDR_ALIGNMENT ("C0"), 274 | .SRTYPE ("ASYNC") 275 | ) 276 | v1_d_2( 277 | .Q (V1_D[2]), 278 | .C0 (dcm_clk0), 279 | .C1 (!dcm_clk0), 280 | .CE (1'b1), 281 | .D0 (pixel_blue[2]), 282 | .D1 (pixel_green[6]), 283 | .R (!reset_n), 284 | .S (1'b0) 285 | ); 286 | ODDR2 #( 287 | .DDR_ALIGNMENT ("C0"), 288 | .SRTYPE ("ASYNC") 289 | ) 290 | v1_d_1( 291 | .Q (V1_D[1]), 292 | .C0 (dcm_clk0), 293 | .C1 (!dcm_clk0), 294 | .CE (1'b1), 295 | .D0 (pixel_blue[1]), 296 | .D1 (pixel_green[5]), 297 | .R (!reset_n), 298 | .S (1'b0) 299 | ); 300 | ODDR2 #( 301 | .DDR_ALIGNMENT ("C0"), 302 | .SRTYPE ("ASYNC") 303 | ) 304 | v1_d_0( 305 | .Q (V1_D[0]), 306 | .C0 (dcm_clk0), 307 | .C1 (!dcm_clk0), 308 | .CE (1'b1), 309 | .D0 (pixel_blue[0]), 310 | .D1 (pixel_green[4]), 311 | .R (!reset_n), 312 | .S (1'b0) 313 | ); 314 | endmodule 315 | -------------------------------------------------------------------------------- /DVI_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 10 ns/1 ps 2 | 3 | module test; 4 | reg tb_clk; 5 | reg tb_button; 6 | 7 | wire tb_spd; 8 | wire tb_spc; 9 | 10 | wire [11:0] tb_d; 11 | wire tb_xclk_p; 12 | wire tb_xclk_n; 13 | wire tb_hsync; 14 | wire tb_vsync; 15 | wire tb_de; 16 | wire tb_reset_n; 17 | 18 | parameter CLK_HALF_PERIOD = 2; 19 | parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; 20 | 21 | dvi_top DUT( 22 | .SYSCLK(tb_clk), 23 | .PANO_BUTTON(tb_button), 24 | 25 | .V_SPD(tb_spd), 26 | .V_SPC(tb_spc), 27 | 28 | .V1_D(tb_d), 29 | .V1_XCLK_P(tb_xclk_p), 30 | .V1_XCLK_N(tb_xclk_n), 31 | .V1_HSYNC(tb_hsync), 32 | .V1_VSYNC(tb_vsync), 33 | .V1_DE(tb_de), 34 | .V1_RESET_N(tb_reset_n) 35 | ); 36 | 37 | always #CLK_HALF_PERIOD tb_clk = !tb_clk; 38 | 39 | task reset(); 40 | begin 41 | tb_button <= 0; 42 | #(10 * CLK_PERIOD); // DCM_SP needs at least 3 clock periods 43 | tb_button <= 1; 44 | end 45 | endtask 46 | 47 | initial begin 48 | tb_clk <= 0; 49 | tb_button <= 1; 50 | 51 | #CLK_PERIOD; 52 | 53 | reset(); 54 | 55 | #(640*480*5 * CLK_PERIOD); 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | 2 | Apache License 3 | Version 2.0, January 2004 4 | http://www.apache.org/licenses/ 5 | 6 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 7 | 8 | 1. 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We also recommend that a 186 | file or class name and description of purpose be included on the 187 | same "printed page" as the copyright notice for easier 188 | identification within third-party archives. 189 | 190 | Copyright [yyyy] [name of copyright owner] 191 | 192 | Licensed under the Apache License, Version 2.0 (the "License"); 193 | you may not use this file except in compliance with the License. 194 | You may obtain a copy of the License at 195 | 196 | http://www.apache.org/licenses/LICENSE-2.0 197 | 198 | Unless required by applicable law or agreed to in writing, software 199 | distributed under the License is distributed on an "AS IS" BASIS, 200 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 201 | See the License for the specific language governing permissions and 202 | limitations under the License. 203 | -------------------------------------------------------------------------------- /Pano.ucf: -------------------------------------------------------------------------------- 1 | # Pano Logic Zero Client G2 Constraints File 2 | 3 | # VCCAUX is 2.5 Volts 4 | CONFIG VCCAUX = "2.5"; 5 | 6 | # 25 MHz System Clock 7 | NET "SYSCLK" LOC = Y13 | IOSTANDARD = LVCMOS33; 8 | TIMESPEC TS_CLK = PERIOD "SYSCLK" 25 MHz HIGH 50%; 9 | NET "SYSCLK" TNM_NET = SYSCLK; 10 | 11 | # Reset Signals 12 | #NET "SYSRST_N" LOC = AB14 | IOSTANDARD = LVCMOS33; 13 | #NET "RESET_OUT_N" LOC = AA6 | IOSTANDARD = LVCMOS33; 14 | 15 | # Power Management 16 | #NET "SLEEP_REQ" LOC = C13 | IOSTANDARD = LVCMOS33; 17 | #NET "POWER_SLEEP" LOC = C10 | IOSTANDARD = LVCMOS33; 18 | 19 | # USB Clock Generation 20 | #NET "USB_RST_N" LOC = W11 | IOSTANDARD = LVCMOS33; 21 | #NET "USB_CLK" LOC = W12 | IOSTANDARD = LVCMOS33; 22 | 23 | # Pano Button LED Output, Active High 24 | NET "LED_RED" LOC = E12 | IOSTANDARD = LVCMOS33; 25 | NET "LED_BLUE" LOC = H13 | IOSTANDARD = LVCMOS33; 26 | NET "LED_GREEN" LOC = F13 | IOSTANDARD = LVCMOS33; 27 | 28 | # Pano Button Input, Active Low 29 | #NET "PANO_BUTTON" LOC = H12 | IOSTANDARD = LVCMOS33; 30 | 31 | # DVI Common 32 | #NET "V_SPD" LOC = D9 | IOSTANDARD = LVCMOS33; 33 | #NET "V_SPC" LOC = E8 | IOSTANDARD = LVCMOS33; 34 | 35 | # DVI Interface 1 (DVI) 36 | #NET "V1_D[0]" LOC = D17 | IOSTANDARD = LVCMOS33; 37 | #NET "V1_D[1]" LOC = A14 | IOSTANDARD = LVCMOS33; 38 | #NET "V1_D[2]" LOC = A15 | IOSTANDARD = LVCMOS33; 39 | #NET "V1_D[3]" LOC = A16 | IOSTANDARD = LVCMOS33; 40 | #NET "V1_D[4]" LOC = A17 | IOSTANDARD = LVCMOS33; 41 | #NET "V1_D[5]" LOC = A18 | IOSTANDARD = LVCMOS33; 42 | #NET "V1_D[6]" LOC = D14 | IOSTANDARD = LVCMOS33; 43 | #NET "V1_D[7]" LOC = B14 | IOSTANDARD = LVCMOS33; 44 | #NET "V1_D[8]" LOC = B16 | IOSTANDARD = LVCMOS33; 45 | #NET "V1_D[9]" LOC = B18 | IOSTANDARD = LVCMOS33; 46 | #NET "V1_D[10]" LOC = E16 | IOSTANDARD = LVCMOS33; 47 | #NET "V1_D[11]" LOC = D15 | IOSTANDARD = LVCMOS33; 48 | #NET "V1_XCLK_P" LOC = E14 | IOSTANDARD = LVCMOS33; 49 | #NET "V1_XCLK_N" LOC = F15 | IOSTANDARD = LVCMOS33; 50 | #NET "V1_HSYNC" LOC = F12 | IOSTANDARD = LVCMOS33; 51 | #NET "V1_VSYNC" LOC = C16 | IOSTANDARD = LVCMOS33; 52 | #NET "V1_DE" LOC = F14 | IOSTANDARD = LVCMOS33; 53 | #NET "V1_RESET_N" LOC = C15 | IOSTANDARD = LVCMOS33; 54 | #NET "DDC1_SCK" LOC = C14 | IOSTANDARD = LVCMOS33; 55 | #NET "DDC1_SDA" LOC = C17 | IOSTANDARD = LVCMOS33; 56 | #NET "V1_HPINT" LOC = D13 | IOSTANDARD = LVCMOS33; # Hot-plug detect interrupt input, active low 57 | 58 | # DVI Interface 2 (micro-HDMI) 59 | #NET "V2_D[0]" LOC = T18 | IOSTANDARD = LVCMOS33; 60 | #NET "V2_D[1]" LOC = U16 | IOSTANDARD = LVCMOS33; 61 | #NET "V2_D[2]" LOC = V17 | IOSTANDARD = LVCMOS33; 62 | #NET "V2_D[3]" LOC = V19 | IOSTANDARD = LVCMOS33; 63 | #NET "V2_D[4]" LOC = V18 | IOSTANDARD = LVCMOS33; 64 | #NET "V2_D[5]" LOC = W17 | IOSTANDARD = LVCMOS33; 65 | #NET "V2_D[6]" LOC = Y17 | IOSTANDARD = LVCMOS33; 66 | #NET "V2_D[7]" LOC = Y15 | IOSTANDARD = LVCMOS33; 67 | #NET "V2_D[8]" LOC = Y18 | IOSTANDARD = LVCMOS33; 68 | #NET "V2_D[9]" LOC = Y19 | IOSTANDARD = LVCMOS33; 69 | #NET "V2_D[10]" LOC = AB21 | IOSTANDARD = LVCMOS33; 70 | #NET "V2_D[11]" LOC = T17 | IOSTANDARD = LVCMOS33; 71 | #NET "V2_XCLK_P" LOC = T15 | IOSTANDARD = LVCMOS33; # Clock output 72 | #NET "V2_HSYNC" LOC = AB15 | IOSTANDARD = LVCMOS33; # H-sync output 73 | #NET "V2_VSYNC" LOC = T16 | IOSTANDARD = LVCMOS33; # V-sync output 74 | #NET "V2_DE" LOC = AB16 | IOSTANDARD = LVCMOS33; # Data enable output 75 | #NET "V2_RESET_N" LOC = W18 | IOSTANDARD = LVCMOS33; # Reset output, active low 76 | #NET "DDC2_SCK" LOC = AA21 | IOSTANDARD = LVCMOS33; # Display data channel clock 77 | #NET "DDC2_SDA" LOC = AB19 | IOSTANDARD = LVCMOS33; # Display data channel data 78 | #NET "V2_HPINT" LOC = AB18 | IOSTANDARD = LVCMOS33; # Hot-plug detect interrupt input, active low 79 | 80 | # USB PHY 81 | #NET "ULPI_DATA[7]" LOC = A4 | IOSTANDARD = LVCMOS33; 82 | #NET "ULPI_DATA[6]" LOC = A6 | IOSTANDARD = LVCMOS33; 83 | #NET "ULPI_DATA[5]" LOC = B6 | IOSTANDARD = LVCMOS33; 84 | #NET "ULPI_DATA[4]" LOC = C6 | IOSTANDARD = LVCMOS33; 85 | #NET "ULPI_DATA[3]" LOC = D6 | IOSTANDARD = LVCMOS33; 86 | #NET "ULPI_DATA[2]" LOC = A8 | IOSTANDARD = LVCMOS33; 87 | #NET "ULPI_DATA[1]" LOC = B8 | IOSTANDARD = LVCMOS33; 88 | #NET "ULPI_DATA[0]" LOC = A7 | IOSTANDARD = LVCMOS33; 89 | #NET "ULPI_NXT" LOC = C5 | IOSTANDARD = LVCMOS33; 90 | #NET "ULPI_DIR" LOC = C7 | IOSTANDARD = LVCMOS33; 91 | #NET "ULPI_STP" LOC = A5 | IOSTANDARD = LVCMOS33; 92 | #NET "ULPI_60M_CLK" LOC = C12 | IOSTANDARD = LVCMOS33; 93 | #NET "USB3300_RESET" LOC = C9 | IOSTANDARD = LVCMOS33; 94 | 95 | # Audio interface 96 | #NET "ADC_BCLK" LOC = AB13 | IOSTANDARD = LVCMOS33; 97 | #NET "ADC_ADCLRC" LOC = W9 | IOSTANDARD = LVCMOS33; 98 | #NET "ADC_ADCDAT" LOC = R13 | IOSTANDARD = LVCMOS33; 99 | #NET "ADC_DACLRC" LOC = U6 | IOSTANDARD = LVCMOS33; 100 | #NET "ADC_DACDAT" LOC = Y14 | IOSTANDARD = LVCMOS33; 101 | #NET "ADC_MCLK" LOC = W14 | IOSTANDARD = LVCMOS33; 102 | #NET "ADC_SCLK" LOC = U17 | IOSTANDARD = LVCMOS33; 103 | #NET "ADC_SDIN" LOC = AB17 | IOSTANDARD = LVCMOS33; 104 | 105 | # Ethernet PHY 106 | #NET "GMII_TX_DATA[7]" LOC = Y10 | IOSTANDARD = LVCMOS33; 107 | #NET "GMII_TX_DATA[6]" LOC = T7 | IOSTANDARD = LVCMOS33; 108 | #NET "GMII_TX_DATA[5]" LOC = AB10 | IOSTANDARD = LVCMOS33; 109 | #NET "GMII_TX_DATA[4]" LOC = AB9 | IOSTANDARD = LVCMOS33; 110 | #NET "GMII_TX_DATA[3]" LOC = AB7 | IOSTANDARD = LVCMOS33; 111 | #NET "GMII_TX_DATA[2]" LOC = AB4 | IOSTANDARD = LVCMOS33; 112 | #NET "GMII_TX_DATA[1]" LOC = AB3 | IOSTANDARD = LVCMOS33; 113 | #NET "GMII_TX_DATA[0]" LOC = AB2 | IOSTANDARD = LVCMOS33; 114 | #NET "GMII_TX_CLK" LOC = Y11 | IOSTANDARD = LVCMOS33; 115 | #NET "GMII_TX_ER" LOC = AB8 | IOSTANDARD = LVCMOS33; # NC 116 | #NET "GMII_TX_EN" LOC = AA8 | IOSTANDARD = LVCMOS33; 117 | #NET "MII_GMII_MDIO" LOC = AA2 | IOSTANDARD = LVCMOS33; 118 | #NET "MII_GMII_MDC" LOC = AB6 | IOSTANDARD = LVCMOS33; 119 | #NET "GMII_RST_N" LOC = R11 | IOSTANDARD = LVCMOS33; 120 | #NET "GTX_CLK" LOC = AA12 | IOSTANDARD = LVCMOS33; 121 | #NET "GMII_RX_DATA[7]" LOC = Y9 | IOSTANDARD = LVCMOS33; 122 | #NET "GMII_RX_DATA[6]" LOC = U9 | IOSTANDARD = LVCMOS33; 123 | #NET "GMII_RX_DATA[5]" LOC = R8 | IOSTANDARD = LVCMOS33; 124 | #NET "GMII_RX_DATA[4]" LOC = V9 | IOSTANDARD = LVCMOS33; 125 | #NET "GMII_RX_DATA[3]" LOC = R7 | IOSTANDARD = LVCMOS33; 126 | #NET "GMII_RX_DATA[2]" LOC = R9 | IOSTANDARD = LVCMOS33; 127 | #NET "GMII_RX_DATA[1]" LOC = Y4 | IOSTANDARD = LVCMOS33; 128 | #NET "GMII_RX_DATA[0]" LOC = Y3 | IOSTANDARD = LVCMOS33; 129 | #NET "GMII_RX_ER" LOC = Y8 | IOSTANDARD = LVCMOS33; 130 | #NET "GMII_RX_DV" LOC = Y7 | IOSTANDARD = LVCMOS33; 131 | #NET "GMII_RX_CLK" LOC = AB11 | IOSTANDARD = LVCMOS33; 132 | #NET "GMII_COL" LOC = V7 | IOSTANDARD = LVCMOS33; 133 | #NET "GMII_CRS" LOC = W4 | IOSTANDARD = LVCMOS33; 134 | #NET "ENET_LINK_ACTIVE_N" LOC = AA4 | IOSTANDARD = LVCMOS33; 135 | 136 | # DDR2 SDRAM Interface A 137 | #NET "DDR2A_D[0]" LOC = N20 | IOSTANDARD = LVCMOS18; 138 | #NET "DDR2A_D[1]" LOC = N22 | IOSTANDARD = LVCMOS18; 139 | #NET "DDR2A_D[2]" LOC = M21 | IOSTANDARD = LVCMOS18; 140 | #NET "DDR2A_D[3]" LOC = M22 | IOSTANDARD = LVCMOS18; 141 | #NET "DDR2A_D[4]" LOC = J20 | IOSTANDARD = LVCMOS18; 142 | #NET "DDR2A_D[5]" LOC = J22 | IOSTANDARD = LVCMOS18; 143 | #NET "DDR2A_D[6]" LOC = K21 | IOSTANDARD = LVCMOS18; 144 | #NET "DDR2A_D[7]" LOC = K22 | IOSTANDARD = LVCMOS18; 145 | #NET "DDR2A_D[8]" LOC = P21 | IOSTANDARD = LVCMOS18; 146 | #NET "DDR2A_D[9]" LOC = P22 | IOSTANDARD = LVCMOS18; 147 | #NET "DDR2A_D[10]" LOC = R20 | IOSTANDARD = LVCMOS18; 148 | #NET "DDR2A_D[11]" LOC = R22 | IOSTANDARD = LVCMOS18; 149 | #NET "DDR2A_D[12]" LOC = U20 | IOSTANDARD = LVCMOS18; 150 | #NET "DDR2A_D[13]" LOC = U22 | IOSTANDARD = LVCMOS18; 151 | #NET "DDR2A_D[14]" LOC = V21 | IOSTANDARD = LVCMOS18; 152 | #NET "DDR2A_D[15]" LOC = V22 | IOSTANDARD = LVCMOS18; 153 | #NET "DDR2A_CKE" LOC = D21 | IOSTANDARD = LVCMOS18; 154 | #NET "DDR2A_A[12]" LOC = D22 | IOSTANDARD = LVCMOS18; 155 | #NET "DDR2A_A[11]" LOC = F19 | IOSTANDARD = LVCMOS18; 156 | #NET "DDR2A_A[10]" LOC = G19 | IOSTANDARD = LVCMOS18; 157 | #NET "DDR2A_A[9]" LOC = C22 | IOSTANDARD = LVCMOS18; 158 | #NET "DDR2A_A[8]" LOC = C20 | IOSTANDARD = LVCMOS18; 159 | #NET "DDR2A_A[7]" LOC = E20 | IOSTANDARD = LVCMOS18; 160 | #NET "DDR2A_A[6]" LOC = K19 | IOSTANDARD = LVCMOS18; 161 | #NET "DDR2A_A[5]" LOC = K20 | IOSTANDARD = LVCMOS18; 162 | #NET "DDR2A_A[4]" LOC = F20 | IOSTANDARD = LVCMOS18; 163 | #NET "DDR2A_A[3]" LOC = G20 | IOSTANDARD = LVCMOS18; 164 | #NET "DDR2A_A[2]" LOC = E22 | IOSTANDARD = LVCMOS18; 165 | #NET "DDR2A_A[1]" LOC = F22 | IOSTANDARD = LVCMOS18; 166 | #NET "DDR2A_A[0]" LOC = F21 | IOSTANDARD = LVCMOS18; 167 | #NET "DDR2A_BA[2]" LOC = H18 | IOSTANDARD = LVCMOS18; 168 | #NET "DDR2A_BA[1]" LOC = K17 | IOSTANDARD = LVCMOS18; 169 | #NET "DDR2A_BA[0]" LOC = J17 | IOSTANDARD = LVCMOS18; 170 | #NET "DDR2A_RAS_L" LOC = H21 | IOSTANDARD = LVCMOS18; 171 | #NET "DDR2A_CAS_L" LOC = H22 | IOSTANDARD = LVCMOS18; 172 | #NET "DDR2A_WE_L" LOC = H19 | IOSTANDARD = LVCMOS18; 173 | #NET "DDR2A_CK_P" LOC = H20 | IOSTANDARD = LVCMOS18; 174 | #NET "DDR2A_CK_N" LOC = J19 | IOSTANDARD = LVCMOS18; 175 | #NET "DDR2A_ODT" LOC = G22 | IOSTANDARD = LVCMOS18; 176 | #NET "DDR2A_UDM" LOC = M20 | IOSTANDARD = LVCMOS18; 177 | #NET "DDR2A_LDM" LOC = L19 | IOSTANDARD = LVCMOS18; 178 | #NET "DDR2A_LDQS_P" LOC = L20 | IOSTANDARD = LVCMOS18; 179 | #NET "DDR2A_LDQS_N" LOC = L22 | IOSTANDARD = LVCMOS18; 180 | #NET "DDR2A_UDQS_P" LOC = T21 | IOSTANDARD = LVCMOS18; 181 | #NET "DDR2A_UDQS_N" LOC = T22 | IOSTANDARD = LVCMOS18; 182 | 183 | # DDR2 SDRAM Interface B 184 | #NET "DDR2B_D[15]" LOC = V1 | IOSTANDARD = LVCMOS18; 185 | #NET "DDR2B_D[14]" LOC = V2 | IOSTANDARD = LVCMOS18; 186 | #NET "DDR2B_D[13]" LOC = U1 | IOSTANDARD = LVCMOS18; 187 | #NET "DDR2B_D[12]" LOC = U3 | IOSTANDARD = LVCMOS18; 188 | #NET "DDR2B_D[11]" LOC = R1 | IOSTANDARD = LVCMOS18; 189 | #NET "DDR2B_D[10]" LOC = R3 | IOSTANDARD = LVCMOS18; 190 | #NET "DDR2B_D[9]" LOC = P1 | IOSTANDARD = LVCMOS18; 191 | #NET "DDR2B_D[8]" LOC = P2 | IOSTANDARD = LVCMOS18; 192 | #NET "DDR2B_D[7]" LOC = K1 | IOSTANDARD = LVCMOS18; 193 | #NET "DDR2B_D[6]" LOC = K2 | IOSTANDARD = LVCMOS18; 194 | #NET "DDR2B_D[5]" LOC = J1 | IOSTANDARD = LVCMOS18; 195 | #NET "DDR2B_D[4]" LOC = J3 | IOSTANDARD = LVCMOS18; 196 | #NET "DDR2B_D[3]" LOC = M1 | IOSTANDARD = LVCMOS18; 197 | #NET "DDR2B_D[2]" LOC = M2 | IOSTANDARD = LVCMOS18; 198 | #NET "DDR2B_D[1]" LOC = N1 | IOSTANDARD = LVCMOS18; 199 | #NET "DDR2B_D[0]" LOC = N3 | IOSTANDARD = LVCMOS18; 200 | #NET "DDR2B_CKE" LOC = D2 | IOSTANDARD = LVCMOS18; 201 | #NET "DDR2B_A[12]" LOC = D1 | IOSTANDARD = LVCMOS18; 202 | #NET "DDR2B_A[11]" LOC = C1 | IOSTANDARD = LVCMOS18; 203 | #NET "DDR2B_A[10]" LOC = G4 | IOSTANDARD = LVCMOS18; 204 | #NET "DDR2B_A[9]" LOC = E1 | IOSTANDARD = LVCMOS18; 205 | #NET "DDR2B_A[8]" LOC = E3 | IOSTANDARD = LVCMOS18; 206 | #NET "DDR2B_A[7]" LOC = H6 | IOSTANDARD = LVCMOS18; 207 | #NET "DDR2B_A[6]" LOC = J4 | IOSTANDARD = LVCMOS18; 208 | #NET "DDR2B_A[5]" LOC = K3 | IOSTANDARD = LVCMOS18; 209 | #NET "DDR2B_A[4]" LOC = F3 | IOSTANDARD = LVCMOS18; 210 | #NET "DDR2B_A[3]" LOC = K6 | IOSTANDARD = LVCMOS18; 211 | #NET "DDR2B_A[2]" LOC = H5 | IOSTANDARD = LVCMOS18; 212 | #NET "DDR2B_A[1]" LOC = H1 | IOSTANDARD = LVCMOS18; 213 | #NET "DDR2B_A[0]" LOC = H2 | IOSTANDARD = LVCMOS18; 214 | #NET "DDR2B_BA[2]" LOC = F1 | IOSTANDARD = LVCMOS18; 215 | #NET "DDR2B_BA[1]" LOC = G1 | IOSTANDARD = LVCMOS18; 216 | #NET "DDR2B_BA[0]" LOC = G3 | IOSTANDARD = LVCMOS18; 217 | #NET "DDR2B_RAS_L" LOC = K5 | IOSTANDARD = LVCMOS18; 218 | #NET "DDR2B_CAS_L" LOC = K4 | IOSTANDARD = LVCMOS18; 219 | #NET "DDR2B_WE_L" LOC = F2 | IOSTANDARD = LVCMOS18; 220 | #NET "DDR2B_CK_P" LOC = H4 | IOSTANDARD = LVCMOS18; 221 | #NET "DDR2B_CK_N" LOC = H3 | IOSTANDARD = LVCMOS18; 222 | #NET "DDR2B_ODT" LOC = J6 | IOSTANDARD = LVCMOS18; 223 | #NET "DDR2B_UDM" LOC = M3 | IOSTANDARD = LVCMOS18; 224 | #NET "DDR2B_LDM" LOC = L4 | IOSTANDARD = LVCMOS18; 225 | #NET "DDR2B_LDQS_P" LOC = L3 | IOSTANDARD = LVCMOS18; 226 | #NET "DDR2B_LDQS_N" LOC = L1 | IOSTANDARD = LVCMOS18; 227 | #NET "DDR2B_UDQS_P" LOC = T2 | IOSTANDARD = LVCMOS18; 228 | #NET "DDR2B_UDQS_N" LOC = T1 | IOSTANDARD = LVCMOS18; 229 | -------------------------------------------------------------------------------- /Pano.v: -------------------------------------------------------------------------------- 1 | module top( 2 | input SYSCLK, 3 | output LED_RED, 4 | output LED_BLUE, 5 | output LED_GREEN 6 | ); 7 | 8 | reg [2:0] led_reg; 9 | reg [32:0] counter; 10 | 11 | assign LED_RED = led_reg[0]; 12 | assign LED_BLUE = led_reg[1]; 13 | assign LED_GREEN = led_reg[2]; 14 | 15 | always @(posedge SYSCLK) begin 16 | if (counter < 25000000) 17 | counter <= counter + 1; 18 | else begin 19 | counter <= 0; 20 | led_reg <= led_reg + 1; 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Pano-Logic-Zero-Client-G2-FPGA-Demo 2 | --------------------------------------------------------------------------------