├── Boards ├── Bittware_CVP13 │ ├── CVP13_DIMM0.xdc │ ├── CVP13_DIMM1.xdc │ ├── bitstream │ │ ├── example.bit │ │ └── example.ltx │ └── create_project.tcl ├── Xilinx_BCU1525 │ ├── BCU1525_DIMM0.xdc │ ├── BCU1525_DIMM1.xdc │ ├── BCU1525_DIMM2.xdc │ ├── BCU1525_DIMM3.xdc │ ├── BCU1525_QSFP.xdc │ ├── bitstream │ │ ├── example.bit │ │ └── example.ltx │ └── create_project.tcl ├── Xilinx_VCU1525 │ ├── VCU1525_DIMM0.xdc │ ├── VCU1525_DIMM1.xdc │ ├── VCU1525_DIMM2.xdc │ ├── VCU1525_DIMM3.xdc │ ├── bitstream │ │ ├── pcie_x16_2400MT.bit │ │ ├── pcie_x16_2400MT.ltx │ │ ├── pcie_x1_2400MT.bit │ │ └── pcie_x1_2400MT.ltx │ └── create_project.tcl └── Xilinx_ZCU104 │ ├── ZCU104_SODIMM.xdc │ ├── ZCU104_TESTSTAND.xdc │ ├── create_project.tcl │ ├── create_project_teststand.tcl │ └── teststand_pmu_io.v ├── Images ├── BCU1525_Quad_DDR4_BlockDiagram.PNG ├── BCU1525_Quad_DDR4_Calibration.PNG ├── BCU1525_Quad_DDR4_MemoryMap.PNG ├── BCU1525_SourceScript.PNG ├── vu9p_bank48.PNG └── zcu104_ioplanner.PNG ├── Interfaces ├── PMU_IO.xml └── PMU_IO_rtl.xml ├── LICENSE ├── Memory ├── Crutial_Ballistix_Sport │ ├── BLS4G4D240FSB.csv │ ├── BLS4G4S26BFSD.csv │ ├── BLS8G4D240FSB.csv │ └── specs │ │ └── 4gb_auto_ddr4_sdram.pdf └── Micron_MTA8ATF1G64HZ │ ├── MTA8ATF1G64HZ.csv │ └── specs │ ├── 8Gb_DDR4_SDRAM.pdf │ └── atf8c1gx64hz.pdf ├── Patches └── xilinx_mig │ └── time_periods.patch ├── README.md └── Scripts └── jtag2axi.tcl /Boards/Bittware_CVP13/bitstream/example.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Boards/Bittware_CVP13/bitstream/example.bit -------------------------------------------------------------------------------- /Boards/Bittware_CVP13/bitstream/example.ltx: -------------------------------------------------------------------------------- 1 | { 2 | "ltx_root": { 3 | "version": 4, 4 | "minor": 0, 5 | "ltx_data": [ 6 | { 7 | "name": "EDA_PROBESET", 8 | "active": true, 9 | "debug_cores": [ 10 | { 11 | "type": "XSDB_V3", 12 | "name": "dbg_hub", 13 | "spec": "labtools_xsdbm_v3", 14 | "clk_input_freq_hz": "75030006" 15 | }, 16 | { 17 | "type": "XSDBS_V2", 18 | "name": "design_1_i/ddr4_0", 19 | "spec": "labtools_xsdbslavelib_v2", 20 | "ipName": "DDR4_SDRAM", 21 | "core_location": { 22 | "user_chain": 1, 23 | "slave_index": 0, 24 | "bscan_switch_index": 0 25 | }, 26 | "uuid": "5055CCF3AB285F28A88899587C896C7C" 27 | }, 28 | { 29 | "type": "XSDBS_V2", 30 | "name": "design_1_i/ddr4_1", 31 | "spec": "labtools_xsdbslavelib_v2", 32 | "ipName": "DDR4_SDRAM", 33 | "core_location": { 34 | "user_chain": 1, 35 | "slave_index": 1, 36 | "bscan_switch_index": 0 37 | }, 38 | "uuid": "B4629568096B5679BC0585F3EF7C1106" 39 | } 40 | ] 41 | } 42 | ] 43 | } 44 | } -------------------------------------------------------------------------------- /Boards/Bittware_CVP13/create_project.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | #Need apply patch to Xilinx MIG before can enable DDR4-2666 speed for DIMM/UDIMM. 22 | set MEM_SPEED 2400 23 | 24 | set ProjectName cvp13_ballistix 25 | 26 | if {$MEM_SPEED == 2666} { 27 | append ProjectName $MEM_SPEED 28 | } 29 | 30 | set ProjectFolder ./$ProjectName 31 | 32 | #Remove unnecessary files. 33 | set file_list [glob -nocomplain webtalk*.*] 34 | foreach name $file_list { 35 | file delete $name 36 | } 37 | 38 | #Delete old project if folder already exists. 39 | if {[file exists .Xil]} { 40 | file delete -force .Xil 41 | } 42 | 43 | #Delete old project if folder already exists. 44 | if {[file exists "$ProjectFolder"]} { 45 | file delete -force $ProjectFolder 46 | } 47 | 48 | set scriptPath [file dirname [file normalize [info script]]] 49 | set sourceRoot [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 50 | 51 | if {[string compare [version -short] 2023.2] != 0} { 52 | return -code error [format "This script is for Vivado version 2023.2!"] 53 | } 54 | 55 | create_project $ProjectName $ProjectFolder -part xcvu13p-figd2104-2-e 56 | 57 | create_bd_design "bd" 58 | 59 | set_param synth.maxThreads 8 60 | set_param general.maxThreads 12 61 | 62 | import_files -norecurse $sourceRoot/Memory/Crutial_Ballistix_Sport/BLS4G4D240FSB.csv 63 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Bittware_CVP13/CVP13_DIMM0.xdc 64 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Bittware_CVP13/CVP13_DIMM1.xdc 65 | 66 | #Uncomment to create local copy of files. 67 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Bittware_CVP13/CVP13_DIMM0.xdc 68 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Bittware_CVP13/CVP13_DIMM1.xdc 69 | 70 | 71 | startgroup 72 | create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 73 | endgroup 74 | 75 | startgroup 76 | make_bd_intf_pins_external [get_bd_intf_pins xdma_0/pcie_mgt] 77 | set_property name pci_express_x1 [get_bd_intf_ports pcie_mgt_0] 78 | make_bd_pins_external [get_bd_pins xdma_0/sys_rst_n] 79 | set_property name pcie_perstn [get_bd_ports sys_rst_n_0] 80 | endgroup 81 | 82 | startgroup 83 | set_property -dict [list CONFIG.mode_selection {Basic}] [get_bd_cells xdma_0] 84 | set_property -dict [list CONFIG.xdma_pcie_64bit_en {true} CONFIG.pf0_msix_cap_table_bir {BAR_1:0} CONFIG.pf0_msix_cap_pba_bir {BAR_1:0}] [get_bd_cells xdma_0] 85 | endgroup 86 | 87 | startgroup 88 | create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 89 | endgroup 90 | 91 | startgroup 92 | set_property -dict [list CONFIG.C_BUF_TYPE {IBUFDSGTE}] [get_bd_cells util_ds_buf_0] 93 | #set_property -dict [list CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk}] [get_bd_cells util_ds_buf_0] 94 | make_bd_intf_pins_external [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] 95 | set_property name pcie_refclk [get_bd_intf_ports CLK_IN_D_0] 96 | connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] 97 | connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] 98 | endgroup 99 | 100 | startgroup 101 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 102 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_1 103 | 104 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_DDR4] 105 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_1/C0_DDR4] 106 | 107 | set_property name C1_DDR4_0 [get_bd_intf_ports C0_DDR4_1] 108 | endgroup 109 | 110 | if {$MEM_SPEED == 2666} { 111 | startgroup 112 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {9996} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_0] 113 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {9996} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_1] 114 | 115 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 116 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_1] 117 | 118 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_0] 119 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_1] 120 | endgroup 121 | } else { 122 | startgroup 123 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {9996} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_0] 124 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {9996} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_1] 125 | 126 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 127 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_1] 128 | 129 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_0] 130 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_1] 131 | endgroup 132 | } 133 | 134 | startgroup 135 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_0] 136 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_1] 137 | endgroup 138 | 139 | startgroup 140 | create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 141 | set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not} CONFIG.LOGO_FILE {data/sym_notgate.png}] [get_bd_cells util_vector_logic_0] 142 | connect_bd_net [get_bd_ports pcie_perstn] [get_bd_pins util_vector_logic_0/Op1] 143 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_0/sys_rst] 144 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_1/sys_rst] 145 | endgroup 146 | 147 | startgroup 148 | create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc 149 | endgroup 150 | 151 | startgroup 152 | set_property -dict [list CONFIG.NUM_MI {2} CONFIG.NUM_SI {1} CONFIG.NUM_CLKS {3}] [get_bd_cells axi_smc] 153 | connect_bd_intf_net [get_bd_intf_pins xdma_0/M_AXI] [get_bd_intf_pins axi_smc/S00_AXI] 154 | connect_bd_net [get_bd_pins xdma_0/axi_aclk] [get_bd_pins axi_smc/aclk] 155 | connect_bd_net [get_bd_pins xdma_0/axi_aresetn] [get_bd_pins axi_smc/aresetn] 156 | endgroup 157 | 158 | startgroup 159 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c0_reset 160 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c1_reset 161 | endgroup 162 | 163 | startgroup 164 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c0_reset] 165 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c0_reset] 166 | 167 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c1_reset] 168 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c1_reset] 169 | 170 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins ddr4_c0_reset/slowest_sync_clk] 171 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c0_reset/ext_reset_in] 172 | connect_bd_net [get_bd_pins ddr4_c0_reset/peripheral_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] 173 | 174 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk] [get_bd_pins ddr4_c1_reset/slowest_sync_clk] 175 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c1_reset/ext_reset_in] 176 | connect_bd_net [get_bd_pins ddr4_c1_reset/peripheral_aresetn] [get_bd_pins ddr4_1/c0_ddr4_aresetn] 177 | endgroup 178 | 179 | startgroup 180 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk1] 181 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk2] 182 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] 183 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M01_AXI] [get_bd_intf_pins ddr4_1/C0_DDR4_S_AXI] 184 | 185 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_SYS_CLK] 186 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_1/C0_SYS_CLK] 187 | 188 | set_property name dimm0_refclk [get_bd_intf_ports C0_SYS_CLK_0] 189 | set_property name dimm1_refclk [get_bd_intf_ports C0_SYS_CLK_1] 190 | 191 | set_property CONFIG.FREQ_HZ 100000000 [get_bd_intf_ports /dimm0_refclk] 192 | set_property CONFIG.FREQ_HZ 100000000 [get_bd_intf_ports /dimm1_refclk] 193 | endgroup 194 | 195 | 196 | assign_bd_address 197 | 198 | make_wrapper -files [get_files ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/bd.bd] -top 199 | add_files -norecurse ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/hdl/bd_wrapper.v 200 | 201 | -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/BCU1525_DIMM1.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | # For BCU1525 Only! DDR4 UDIMM 64-bit, rank 1. 22 | 23 | set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports C1_DDR4_0_reset_n] 24 | 25 | set_property -dict {PACKAGE_PIN AU24 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_ba[0]] 26 | set_property -dict {PACKAGE_PIN AP26 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_ba[1]] 27 | set_property -dict {PACKAGE_PIN BC22 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_bg[0]] 28 | set_property -dict {PACKAGE_PIN AW26 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_bg[1]] 29 | set_property -dict {PACKAGE_PIN BB25 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_cke[0]] 30 | set_property -dict {PACKAGE_PIN AW23 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_odt[0]] 31 | set_property -dict {PACKAGE_PIN AV23 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_cs_n[0]] 32 | set_property -dict {PACKAGE_PIN AU25 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_ck_c[0]] 33 | set_property -dict {PACKAGE_PIN AT25 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_ck_t[0]] 34 | 35 | set_property -dict {PACKAGE_PIN AW25 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_act_n] 36 | set_property -dict {PACKAGE_PIN AN24 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[0]] 37 | set_property -dict {PACKAGE_PIN AT24 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[1]] 38 | set_property -dict {PACKAGE_PIN AW24 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[2]] 39 | set_property -dict {PACKAGE_PIN AN26 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[3]] 40 | set_property -dict {PACKAGE_PIN AY22 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[4]] 41 | set_property -dict {PACKAGE_PIN AY23 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[5]] 42 | set_property -dict {PACKAGE_PIN AV24 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[6]] 43 | set_property -dict {PACKAGE_PIN BA22 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[7]] 44 | set_property -dict {PACKAGE_PIN AY25 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[8]] 45 | set_property -dict {PACKAGE_PIN BA23 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[9]] 46 | set_property -dict {PACKAGE_PIN AM26 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[10]] 47 | set_property -dict {PACKAGE_PIN BA25 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[11]] 48 | set_property -dict {PACKAGE_PIN BB22 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[12]] 49 | set_property -dict {PACKAGE_PIN AL24 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[13]] 50 | set_property -dict {PACKAGE_PIN AL25 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[14]] 51 | set_property -dict {PACKAGE_PIN AM25 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[15]] 52 | set_property -dict {PACKAGE_PIN AN23 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C1_DDR4_0_adr[16]] 53 | 54 | set_property -dict {PACKAGE_PIN BC7 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[0]] 55 | set_property -dict {PACKAGE_PIN BD7 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[1]] 56 | set_property -dict {PACKAGE_PIN BD8 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[2]] 57 | set_property -dict {PACKAGE_PIN BD9 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[3]] 58 | set_property -dict {PACKAGE_PIN BF7 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[4]] 59 | set_property -dict {PACKAGE_PIN BE7 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[5]] 60 | set_property -dict {PACKAGE_PIN BD10 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[6]] 61 | set_property -dict {PACKAGE_PIN BE10 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[7]] 62 | set_property -dict {PACKAGE_PIN BF12 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[8]] 63 | set_property -dict {PACKAGE_PIN BE13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[9]] 64 | set_property -dict {PACKAGE_PIN BD14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[10]] 65 | set_property -dict {PACKAGE_PIN BD13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[11]] 66 | set_property -dict {PACKAGE_PIN BF14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[12]] 67 | set_property -dict {PACKAGE_PIN BF13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[13]] 68 | set_property -dict {PACKAGE_PIN BD16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[14]] 69 | set_property -dict {PACKAGE_PIN BD15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[15]] 70 | set_property -dict {PACKAGE_PIN BF25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[16]] 71 | set_property -dict {PACKAGE_PIN BE25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[17]] 72 | set_property -dict {PACKAGE_PIN BF24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[18]] 73 | set_property -dict {PACKAGE_PIN BD25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[19]] 74 | set_property -dict {PACKAGE_PIN BC23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[20]] 75 | set_property -dict {PACKAGE_PIN BD23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[21]] 76 | set_property -dict {PACKAGE_PIN BF23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[22]] 77 | set_property -dict {PACKAGE_PIN BE23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[23]] 78 | set_property -dict {PACKAGE_PIN BA14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[24]] 79 | set_property -dict {PACKAGE_PIN BA13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[25]] 80 | set_property -dict {PACKAGE_PIN BA12 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[26]] 81 | set_property -dict {PACKAGE_PIN BB12 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[27]] 82 | set_property -dict {PACKAGE_PIN BC9 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[28]] 83 | set_property -dict {PACKAGE_PIN BB9 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[29]] 84 | set_property -dict {PACKAGE_PIN BA7 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[30]] 85 | set_property -dict {PACKAGE_PIN BA8 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[31]] 86 | set_property -dict {PACKAGE_PIN AU13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[32]] 87 | set_property -dict {PACKAGE_PIN AW14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[33]] 88 | set_property -dict {PACKAGE_PIN AW13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[34]] 89 | set_property -dict {PACKAGE_PIN AV13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[35]] 90 | set_property -dict {PACKAGE_PIN AU14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[36]] 91 | set_property -dict {PACKAGE_PIN BA11 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[37]] 92 | set_property -dict {PACKAGE_PIN AY11 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[38]] 93 | set_property -dict {PACKAGE_PIN AV14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[39]] 94 | set_property -dict {PACKAGE_PIN BA18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[40]] 95 | set_property -dict {PACKAGE_PIN BA17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[41]] 96 | set_property -dict {PACKAGE_PIN AY18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[42]] 97 | set_property -dict {PACKAGE_PIN AY17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[43]] 98 | set_property -dict {PACKAGE_PIN BD11 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[44]] 99 | set_property -dict {PACKAGE_PIN BC11 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[45]] 100 | set_property -dict {PACKAGE_PIN BA15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[46]] 101 | set_property -dict {PACKAGE_PIN BB15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[47]] 102 | set_property -dict {PACKAGE_PIN AR13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[48]] 103 | set_property -dict {PACKAGE_PIN AP13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[49]] 104 | set_property -dict {PACKAGE_PIN AN13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[50]] 105 | set_property -dict {PACKAGE_PIN AM13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[51]] 106 | set_property -dict {PACKAGE_PIN AT15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[52]] 107 | set_property -dict {PACKAGE_PIN AR15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[53]] 108 | set_property -dict {PACKAGE_PIN AM14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[54]] 109 | set_property -dict {PACKAGE_PIN AL14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[55]] 110 | set_property -dict {PACKAGE_PIN AV16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[56]] 111 | set_property -dict {PACKAGE_PIN AV17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[57]] 112 | set_property -dict {PACKAGE_PIN AU17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[58]] 113 | set_property -dict {PACKAGE_PIN AU16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[59]] 114 | set_property -dict {PACKAGE_PIN BB17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[60]] 115 | set_property -dict {PACKAGE_PIN BB16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[61]] 116 | set_property -dict {PACKAGE_PIN AT17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[62]] 117 | set_property -dict {PACKAGE_PIN AT18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dq[63]] 118 | 119 | set_property -dict {PACKAGE_PIN BF9 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[0]] 120 | set_property -dict {PACKAGE_PIN BF10 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[0]] 121 | set_property -dict {PACKAGE_PIN BE11 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[1]] 122 | set_property -dict {PACKAGE_PIN BE12 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[1]] 123 | set_property -dict {PACKAGE_PIN BD24 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[2]] 124 | set_property -dict {PACKAGE_PIN BC24 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[2]] 125 | set_property -dict {PACKAGE_PIN BB10 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[3]] 126 | set_property -dict {PACKAGE_PIN BB11 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[3]] 127 | set_property -dict {PACKAGE_PIN AY15 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[4]] 128 | set_property -dict {PACKAGE_PIN AW15 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[4]] 129 | set_property -dict {PACKAGE_PIN BC12 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[5]] 130 | set_property -dict {PACKAGE_PIN BC13 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[5]] 131 | set_property -dict {PACKAGE_PIN AT13 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[6]] 132 | set_property -dict {PACKAGE_PIN AT14 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[6]] 133 | set_property -dict {PACKAGE_PIN AW18 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_c[7]] 134 | set_property -dict {PACKAGE_PIN AV18 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dqs_t[7]] 135 | 136 | set_property -dict {PACKAGE_PIN BE8 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[0]] 137 | set_property -dict {PACKAGE_PIN BE15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[1]] 138 | set_property -dict {PACKAGE_PIN BE22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[2]] 139 | set_property -dict {PACKAGE_PIN BA10 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[3]] 140 | set_property -dict {PACKAGE_PIN AY13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[4]] 141 | set_property -dict {PACKAGE_PIN BB14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[5]] 142 | set_property -dict {PACKAGE_PIN AN14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[6]] 143 | set_property -dict {PACKAGE_PIN AW16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C1_DDR4_0_dm_n[7]] 144 | 145 | #300MHz clock 146 | set_property -dict {PACKAGE_PIN AW20 IOSTANDARD DIFF_SSTL12} [get_ports dimm1_refclk_clk_p] 147 | set_property -dict {PACKAGE_PIN AW19 IOSTANDARD DIFF_SSTL12} [get_ports dimm1_refclk_clk_n] 148 | -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/BCU1525_DIMM2.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | 22 | # For BCU1525 Only! DDR4 UDIMM 64-bit, rank 1. 23 | 24 | set_property -dict {PACKAGE_PIN D36 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports C2_DDR4_0_reset_n] 25 | 26 | set_property -dict {PACKAGE_PIN D33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ba[0]] 27 | set_property -dict {PACKAGE_PIN B36 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ba[1]] 28 | set_property -dict {PACKAGE_PIN C31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_bg[0]] 29 | set_property -dict {PACKAGE_PIN J30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_bg[1]] 30 | set_property -dict {PACKAGE_PIN G30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_cke[0]] 31 | set_property -dict {PACKAGE_PIN E33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_odt[0]] 32 | set_property -dict {PACKAGE_PIN B35 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_cs_n[0]] 33 | set_property -dict {PACKAGE_PIN B34 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ck_c[0]] 34 | set_property -dict {PACKAGE_PIN C34 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ck_t[0]] 35 | 36 | set_property -dict {PACKAGE_PIN B31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_act_n] 37 | set_property -dict {PACKAGE_PIN L29 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[0]] 38 | set_property -dict {PACKAGE_PIN A33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[1]] 39 | set_property -dict {PACKAGE_PIN C33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[2]] 40 | set_property -dict {PACKAGE_PIN J29 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[3]] 41 | set_property -dict {PACKAGE_PIN H31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[4]] 42 | set_property -dict {PACKAGE_PIN G31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[5]] 43 | set_property -dict {PACKAGE_PIN C32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[6]] 44 | set_property -dict {PACKAGE_PIN B32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[7]] 45 | set_property -dict {PACKAGE_PIN A32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[8]] 46 | set_property -dict {PACKAGE_PIN D31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[9]] 47 | set_property -dict {PACKAGE_PIN A34 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[10]] 48 | set_property -dict {PACKAGE_PIN E31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[11]] 49 | set_property -dict {PACKAGE_PIN M30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[12]] 50 | set_property -dict {PACKAGE_PIN F33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[13]] 51 | set_property -dict {PACKAGE_PIN A35 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[14]] 52 | set_property -dict {PACKAGE_PIN G32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[15]] 53 | set_property -dict {PACKAGE_PIN K30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[16]] 54 | 55 | set_property -dict {PACKAGE_PIN P29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[0]] 56 | set_property -dict {PACKAGE_PIN P30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[1]] 57 | set_property -dict {PACKAGE_PIN R30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[2]] 58 | set_property -dict {PACKAGE_PIN N29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[3]] 59 | set_property -dict {PACKAGE_PIN N32 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[4]] 60 | set_property -dict {PACKAGE_PIN M32 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[5]] 61 | set_property -dict {PACKAGE_PIN P31 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[6]] 62 | set_property -dict {PACKAGE_PIN L32 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[7]] 63 | set_property -dict {PACKAGE_PIN H29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[8]] 64 | set_property -dict {PACKAGE_PIN G29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[9]] 65 | set_property -dict {PACKAGE_PIN J28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[10]] 66 | set_property -dict {PACKAGE_PIN H28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[11]] 67 | set_property -dict {PACKAGE_PIN K27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[12]] 68 | set_property -dict {PACKAGE_PIN L27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[13]] 69 | set_property -dict {PACKAGE_PIN K26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[14]] 70 | set_property -dict {PACKAGE_PIN K25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[15]] 71 | set_property -dict {PACKAGE_PIN P25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[16]] 72 | set_property -dict {PACKAGE_PIN R25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[17]] 73 | set_property -dict {PACKAGE_PIN L25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[18]] 74 | set_property -dict {PACKAGE_PIN M25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[19]] 75 | set_property -dict {PACKAGE_PIN P26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[20]] 76 | set_property -dict {PACKAGE_PIN R26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[21]] 77 | set_property -dict {PACKAGE_PIN N27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[22]] 78 | set_property -dict {PACKAGE_PIN N28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[23]] 79 | set_property -dict {PACKAGE_PIN F27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[24]] 80 | set_property -dict {PACKAGE_PIN D28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[25]] 81 | set_property -dict {PACKAGE_PIN E27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[26]] 82 | set_property -dict {PACKAGE_PIN E28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[27]] 83 | set_property -dict {PACKAGE_PIN G26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[28]] 84 | set_property -dict {PACKAGE_PIN F29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[29]] 85 | set_property -dict {PACKAGE_PIN G27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[30]] 86 | set_property -dict {PACKAGE_PIN F28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[31]] 87 | set_property -dict {PACKAGE_PIN A38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[32]] 88 | set_property -dict {PACKAGE_PIN A37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[33]] 89 | set_property -dict {PACKAGE_PIN B37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[34]] 90 | set_property -dict {PACKAGE_PIN C36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[35]] 91 | set_property -dict {PACKAGE_PIN B40 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[36]] 92 | set_property -dict {PACKAGE_PIN C39 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[37]] 93 | set_property -dict {PACKAGE_PIN A40 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[38]] 94 | set_property -dict {PACKAGE_PIN D39 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[39]] 95 | set_property -dict {PACKAGE_PIN G36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[40]] 96 | set_property -dict {PACKAGE_PIN H36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[41]] 97 | set_property -dict {PACKAGE_PIN H37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[42]] 98 | set_property -dict {PACKAGE_PIN J36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[43]] 99 | set_property -dict {PACKAGE_PIN G34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[44]] 100 | set_property -dict {PACKAGE_PIN G35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[45]] 101 | set_property -dict {PACKAGE_PIN K37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[46]] 102 | set_property -dict {PACKAGE_PIN K38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[47]] 103 | set_property -dict {PACKAGE_PIN E38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[48]] 104 | set_property -dict {PACKAGE_PIN D38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[49]] 105 | set_property -dict {PACKAGE_PIN E35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[50]] 106 | set_property -dict {PACKAGE_PIN F35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[51]] 107 | set_property -dict {PACKAGE_PIN E36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[52]] 108 | set_property -dict {PACKAGE_PIN E37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[53]] 109 | set_property -dict {PACKAGE_PIN F38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[54]] 110 | set_property -dict {PACKAGE_PIN G38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[55]] 111 | set_property -dict {PACKAGE_PIN K35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[56]] 112 | set_property -dict {PACKAGE_PIN J35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[57]] 113 | set_property -dict {PACKAGE_PIN K33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[58]] 114 | set_property -dict {PACKAGE_PIN L33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[59]] 115 | set_property -dict {PACKAGE_PIN J33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[60]] 116 | set_property -dict {PACKAGE_PIN J34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[61]] 117 | set_property -dict {PACKAGE_PIN N34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[62]] 118 | set_property -dict {PACKAGE_PIN P34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[63]] 119 | 120 | set_property -dict {PACKAGE_PIN M31 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[0]] 121 | set_property -dict {PACKAGE_PIN N31 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[0]] 122 | set_property -dict {PACKAGE_PIN J26 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[1]] 123 | set_property -dict {PACKAGE_PIN J25 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[1]] 124 | set_property -dict {PACKAGE_PIN M26 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[2]] 125 | set_property -dict {PACKAGE_PIN N26 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[2]] 126 | set_property -dict {PACKAGE_PIN D30 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[3]] 127 | set_property -dict {PACKAGE_PIN D29 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[3]] 128 | set_property -dict {PACKAGE_PIN A39 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[4]] 129 | set_property -dict {PACKAGE_PIN B39 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[4]] 130 | set_property -dict {PACKAGE_PIN H38 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[5]] 131 | set_property -dict {PACKAGE_PIN J38 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[5]] 132 | set_property -dict {PACKAGE_PIN E40 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[6]] 133 | set_property -dict {PACKAGE_PIN E39 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[6]] 134 | set_property -dict {PACKAGE_PIN L36 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[7]] 135 | set_property -dict {PACKAGE_PIN L35 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[7]] 136 | 137 | set_property -dict {PACKAGE_PIN T30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[0]] 138 | set_property -dict {PACKAGE_PIN M27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[1]] 139 | set_property -dict {PACKAGE_PIN R28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[2]] 140 | set_property -dict {PACKAGE_PIN H26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[3]] 141 | set_property -dict {PACKAGE_PIN C37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[4]] 142 | set_property -dict {PACKAGE_PIN H33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[5]] 143 | set_property -dict {PACKAGE_PIN G37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[6]] 144 | set_property -dict {PACKAGE_PIN M34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[7]] 145 | 146 | #300MHz clock 147 | set_property -dict {PACKAGE_PIN F32 IOSTANDARD DIFF_SSTL12} [get_ports dimm2_refclk_clk_p] 148 | set_property -dict {PACKAGE_PIN E32 IOSTANDARD DIFF_SSTL12} [get_ports dimm2_refclk_clk_n] 149 | 150 | -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/BCU1525_DIMM3.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | 22 | # For BCU1525 Only! DDR4 UDIMM 64-bit, rank 1. 23 | 24 | set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports C3_DDR4_0_reset_n] 25 | 26 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ba[0]] 27 | set_property -dict {PACKAGE_PIN H14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ba[1]] 28 | set_property -dict {PACKAGE_PIN D13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_bg[0]] 29 | set_property -dict {PACKAGE_PIN J13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_bg[1]] 30 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_cke[0]] 31 | set_property -dict {PACKAGE_PIN C16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_odt[0]] 32 | set_property -dict {PACKAGE_PIN B16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_cs_n[0]] 33 | set_property -dict {PACKAGE_PIN L13 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ck_c[0]] 34 | set_property -dict {PACKAGE_PIN L14 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ck_t[0]] 35 | 36 | set_property -dict {PACKAGE_PIN H13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_act_n] 37 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[0]] 38 | set_property -dict {PACKAGE_PIN B15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[1]] 39 | set_property -dict {PACKAGE_PIN F14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[2]] 40 | set_property -dict {PACKAGE_PIN A15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[3]] 41 | set_property -dict {PACKAGE_PIN C14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[4]] 42 | set_property -dict {PACKAGE_PIN A14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[5]] 43 | set_property -dict {PACKAGE_PIN B14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[6]] 44 | set_property -dict {PACKAGE_PIN E13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[7]] 45 | set_property -dict {PACKAGE_PIN F13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[8]] 46 | set_property -dict {PACKAGE_PIN A13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[9]] 47 | set_property -dict {PACKAGE_PIN D14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[10]] 48 | set_property -dict {PACKAGE_PIN C13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[11]] 49 | set_property -dict {PACKAGE_PIN B13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[12]] 50 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[13]] 51 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[14]] 52 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[15]] 53 | set_property -dict {PACKAGE_PIN F15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[16]] 54 | 55 | set_property -dict {PACKAGE_PIN M16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[0]] 56 | set_property -dict {PACKAGE_PIN N16 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[1]] 57 | set_property -dict {PACKAGE_PIN N14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[2]] 58 | set_property -dict {PACKAGE_PIN N13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[3]] 59 | set_property -dict {PACKAGE_PIN R15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[4]] 60 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[5]] 61 | set_property -dict {PACKAGE_PIN P13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[6]] 62 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[7]] 63 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[8]] 64 | set_property -dict {PACKAGE_PIN R18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[9]] 65 | set_property -dict {PACKAGE_PIN M20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[10]] 66 | set_property -dict {PACKAGE_PIN M19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[11]] 67 | set_property -dict {PACKAGE_PIN N18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[12]] 68 | set_property -dict {PACKAGE_PIN N19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[13]] 69 | set_property -dict {PACKAGE_PIN R20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[14]] 70 | set_property -dict {PACKAGE_PIN T20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[15]] 71 | set_property -dict {PACKAGE_PIN B24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[16]] 72 | set_property -dict {PACKAGE_PIN A23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[17]] 73 | set_property -dict {PACKAGE_PIN A22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[18]] 74 | set_property -dict {PACKAGE_PIN B25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[19]] 75 | set_property -dict {PACKAGE_PIN C24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[20]] 76 | set_property -dict {PACKAGE_PIN C23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[21]] 77 | set_property -dict {PACKAGE_PIN C22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[22]] 78 | set_property -dict {PACKAGE_PIN B22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[23]] 79 | set_property -dict {PACKAGE_PIN C18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[24]] 80 | set_property -dict {PACKAGE_PIN C19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[25]] 81 | set_property -dict {PACKAGE_PIN C21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[26]] 82 | set_property -dict {PACKAGE_PIN B21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[27]] 83 | set_property -dict {PACKAGE_PIN A17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[28]] 84 | set_property -dict {PACKAGE_PIN A18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[29]] 85 | set_property -dict {PACKAGE_PIN B20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[30]] 86 | set_property -dict {PACKAGE_PIN A20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[31]] 87 | set_property -dict {PACKAGE_PIN E18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[32]] 88 | set_property -dict {PACKAGE_PIN E17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[33]] 89 | set_property -dict {PACKAGE_PIN E20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[34]] 90 | set_property -dict {PACKAGE_PIN F20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[35]] 91 | set_property -dict {PACKAGE_PIN D19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[36]] 92 | set_property -dict {PACKAGE_PIN H18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[37]] 93 | set_property -dict {PACKAGE_PIN D20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[38]] 94 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[39]] 95 | set_property -dict {PACKAGE_PIN G21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[40]] 96 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[41]] 97 | set_property -dict {PACKAGE_PIN G22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[42]] 98 | set_property -dict {PACKAGE_PIN F22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[43]] 99 | set_property -dict {PACKAGE_PIN G25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[44]] 100 | set_property -dict {PACKAGE_PIN F24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[45]] 101 | set_property -dict {PACKAGE_PIN E25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[46]] 102 | set_property -dict {PACKAGE_PIN F25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[47]] 103 | set_property -dict {PACKAGE_PIN J24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[48]] 104 | set_property -dict {PACKAGE_PIN G24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[49]] 105 | set_property -dict {PACKAGE_PIN J23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[50]] 106 | set_property -dict {PACKAGE_PIN H24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[51]] 107 | set_property -dict {PACKAGE_PIN L23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[52]] 108 | set_property -dict {PACKAGE_PIN K21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[53]] 109 | set_property -dict {PACKAGE_PIN L24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[54]] 110 | set_property -dict {PACKAGE_PIN K22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[55]] 111 | set_property -dict {PACKAGE_PIN P24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[56]] 112 | set_property -dict {PACKAGE_PIN N24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[57]] 113 | set_property -dict {PACKAGE_PIN R23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[58]] 114 | set_property -dict {PACKAGE_PIN T24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[59]] 115 | set_property -dict {PACKAGE_PIN N23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[60]] 116 | set_property -dict {PACKAGE_PIN P21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[61]] 117 | set_property -dict {PACKAGE_PIN P23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[62]] 118 | set_property -dict {PACKAGE_PIN R21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[63]] 119 | 120 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[0]] 121 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[0]] 122 | set_property -dict {PACKAGE_PIN P18 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[1]] 123 | set_property -dict {PACKAGE_PIN P19 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[1]] 124 | set_property -dict {PACKAGE_PIN A24 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[2]] 125 | set_property -dict {PACKAGE_PIN A25 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[2]] 126 | set_property -dict {PACKAGE_PIN B17 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[3]] 127 | set_property -dict {PACKAGE_PIN C17 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[3]] 128 | set_property -dict {PACKAGE_PIN F17 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[4]] 129 | set_property -dict {PACKAGE_PIN F18 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[4]] 130 | set_property -dict {PACKAGE_PIN E23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[5]] 131 | set_property -dict {PACKAGE_PIN F23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[5]] 132 | set_property -dict {PACKAGE_PIN H21 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[6]] 133 | set_property -dict {PACKAGE_PIN J21 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[6]] 134 | set_property -dict {PACKAGE_PIN R22 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[7]] 135 | set_property -dict {PACKAGE_PIN T22 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[7]] 136 | 137 | set_property -dict {PACKAGE_PIN T13 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[0]] 138 | set_property -dict {PACKAGE_PIN N17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[1]] 139 | set_property -dict {PACKAGE_PIN D24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[2]] 140 | set_property -dict {PACKAGE_PIN B19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[3]] 141 | set_property -dict {PACKAGE_PIN H19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[4]] 142 | set_property -dict {PACKAGE_PIN H23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[5]] 143 | set_property -dict {PACKAGE_PIN M22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[6]] 144 | set_property -dict {PACKAGE_PIN N22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[7]] 145 | 146 | #300MHz clock 147 | set_property -dict {PACKAGE_PIN J16 IOSTANDARD DIFF_SSTL12} [get_ports dimm3_refclk_clk_p] 148 | set_property -dict {PACKAGE_PIN H16 IOSTANDARD DIFF_SSTL12} [get_ports dimm3_refclk_clk_n] 149 | -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/BCU1525_QSFP.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | 22 | # BCU1525 QSFP I2C connected thru I2C Mux with address 0x74. Mux HiSide (3.3V): 23 | # - Channel0: QSFP0 I2C 24 | # - Channel1: QSFP1 I2C 25 | # - Channel2: USER Si750 Clock I2C 26 | # - Channel3: SYSMon I2C 27 | set_property -dict {PACKAGE_PIN BF19 IOSTANDARD LVCMOS12 } [get_ports I2C_FPGA_SDA_RESET] 28 | set_property -dict {PACKAGE_PIN BF20 IOSTANDARD LVCMOS12 } [get_ports I2C_FPGA_SCL_LS] 29 | set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS12 } [get_ports I2C_FPGA_SDA_LS] 30 | 31 | # BCU1525 QSFP clocks 32 | # FS[1:0] = 01 -> CLK1A/1B: 156.25 MHz 1.8V LVDS 33 | # FS[1:0] = 1X -> CLK1A/1B: 161.1328125 MHz 1.8V LVDS 34 | set_property -dict {PACKAGE_PIN AU19 IOSTANDARD LVCMOS12 } [get_ports USER_SI570_CLOCK_N] 35 | set_property -dict {PACKAGE_PIN AV19 IOSTANDARD LVCMOS12 } [get_ports USER_SI570_CLOCK_N] 36 | set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS12 } [get_ports MGT_SI570_CLOCK0_C_P] 37 | set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS12 } [get_ports MGT_SI570_CLOCK0_C_N] 38 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS12 } [get_ports MGT_SI570_CLOCK1_C_P] 39 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS12 } [get_ports MGT_SI570_CLOCK1_C_N] 40 | # 41 | set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS12 } [get_ports QSFP0_CLOCK_P] 42 | set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS12 } [get_ports QSFP0_CLOCK_N] 43 | set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS12 } [get_ports QSFP1_CLOCK_P] 44 | set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS12 } [get_ports QSFP1_CLOCK_N] 45 | 46 | # BCU1525 QSFP0 47 | set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVCMOS12 } [get_ports QSFP0_REFCLK_RESET] 48 | set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS12 } [get_ports QSFP0_MODSKLL] 49 | set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RESETL] 50 | set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS12 } [get_ports QSFP0_MODPRSL] 51 | set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS12 } [get_ports QSFP0_INTL] 52 | set_property -dict {PACKAGE_PIN BD18 IOSTANDARD LVCMOS12 } [get_ports QSFP0_LPMODE] 53 | set_property -dict {PACKAGE_PIN AT20 IOSTANDARD LVCMOS12 } [get_ports QSFP0_FS0] 54 | set_property -dict {PACKAGE_PIN AU22 IOSTANDARD LVCMOS12 } [get_ports QSFP0_FS1] 55 | set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX1_P] 56 | set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX1_N] 57 | set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX1_P] 58 | set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX1_N] 59 | set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX2_P] 60 | set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX2_N] 61 | set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX2_P] 62 | set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX2_N] 63 | set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX3_P] 64 | set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX3_N] 65 | set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX3_P] 66 | set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX3_N] 67 | set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX4_P] 68 | set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS12 } [get_ports QSFP0_TX4_N] 69 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX4_P] 70 | set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RX4_N] 71 | 72 | 73 | 74 | # BCU1525 QSFP1 Bank231 75 | set_property -dict {PACKAGE_PIN AU20 IOSTANDARD LVCMOS12 } [get_ports QSFP1_REFCLK_RESET] 76 | set_property -dict {PACKAGE_PIN AY20 IOSTANDARD LVCMOS12 } [get_ports QSFP1_MODSKLL] 77 | set_property -dict {PACKAGE_PIN BC18 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RESETL] 78 | set_property -dict {PACKAGE_PIN BC19 IOSTANDARD LVCMOS12 } [get_ports QSFP1_MODPRSL] 79 | set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS12 } [get_ports QSFP1_INTL] 80 | set_property -dict {PACKAGE_PIN AV22 IOSTANDARD LVCMOS12 } [get_ports QSFP1_LPMODE] 81 | set_property -dict {PACKAGE_PIN AR21 IOSTANDARD LVCMOS12 } [get_ports QSFP1_FS0] 82 | set_property -dict {PACKAGE_PIN AR22 IOSTANDARD LVCMOS12 } [get_ports QSFP1_FS1] 83 | set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX1_P] 84 | set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX1_N] 85 | set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX1_P] 86 | set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX1_N] 87 | set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX2_P] 88 | set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX2_N] 89 | set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX2_P] 90 | set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX2_N] 91 | set_property -dict {PACKAGE_PIN R9 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX3_P] 92 | set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX3_N] 93 | set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX3_P] 94 | set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX3_N] 95 | set_property -dict {PACKAGE_PIN P7 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX4_P] 96 | set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS12 } [get_ports QSFP1_TX4_N] 97 | set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX4_P] 98 | set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RX4_N] 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/bitstream/example.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Boards/Xilinx_BCU1525/bitstream/example.bit -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/bitstream/example.ltx: -------------------------------------------------------------------------------- 1 | { 2 | "ltx_root": { 3 | "version": 4, 4 | "minor": 0, 5 | "ltx_data": [ 6 | { 7 | "name": "EDA_PROBESET", 8 | "active": true, 9 | "debug_cores": [ 10 | { 11 | "type": "XSDB_V3", 12 | "name": "dbg_hub", 13 | "spec": "labtools_xsdbm_v3", 14 | "clk_input_freq_hz": "75030011" 15 | }, 16 | { 17 | "type": "XSDBS_V2", 18 | "name": "design_1_i/ddr4_0", 19 | "spec": "labtools_xsdbslavelib_v2", 20 | "ipName": "DDR4_SDRAM", 21 | "core_location": { 22 | "user_chain": 1, 23 | "slave_index": 0, 24 | "bscan_switch_index": 0 25 | }, 26 | "uuid": "5055CCF3AB285F28A88899587C896C7C" 27 | }, 28 | { 29 | "type": "XSDBS_V2", 30 | "name": "design_1_i/ddr4_1", 31 | "spec": "labtools_xsdbslavelib_v2", 32 | "ipName": "DDR4_SDRAM", 33 | "core_location": { 34 | "user_chain": 1, 35 | "slave_index": 1, 36 | "bscan_switch_index": 0 37 | }, 38 | "uuid": "B4629568096B5679BC0585F3EF7C1106" 39 | }, 40 | { 41 | "type": "XSDBS_V2", 42 | "name": "design_1_i/ddr4_2", 43 | "spec": "labtools_xsdbslavelib_v2", 44 | "ipName": "DDR4_SDRAM", 45 | "core_location": { 46 | "user_chain": 1, 47 | "slave_index": 2, 48 | "bscan_switch_index": 0 49 | }, 50 | "uuid": "3D96250BECFC5ADB97FEE84C97874B51" 51 | }, 52 | { 53 | "type": "XSDBS_V2", 54 | "name": "design_1_i/ddr4_3", 55 | "spec": "labtools_xsdbslavelib_v2", 56 | "ipName": "DDR4_SDRAM", 57 | "core_location": { 58 | "user_chain": 1, 59 | "slave_index": 3, 60 | "bscan_switch_index": 0 61 | }, 62 | "uuid": "4105F08787FB5BCAB185230AF393F7F7" 63 | } 64 | ] 65 | } 66 | ] 67 | } 68 | } -------------------------------------------------------------------------------- /Boards/Xilinx_BCU1525/create_project.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | 22 | #Need apply patch to Xilinx MIG before can enable DDR4-2666 speed for DIMM/UDIMM. 23 | set MEM_SPEED 2400 24 | 25 | set ProjectName bcu1525_ballistix 26 | 27 | if {$MEM_SPEED == 2666} { 28 | append ProjectName $MEM_SPEED 29 | } 30 | 31 | set ProjectFolder ./$ProjectName 32 | 33 | #Remove unnecessary files. 34 | set file_list [glob -nocomplain webtalk*.*] 35 | foreach name $file_list { 36 | file delete $name 37 | } 38 | 39 | #Delete old project if folder already exists. 40 | if {[file exists .Xil]} { 41 | file delete -force .Xil 42 | } 43 | 44 | #Delete old project if folder already exists. 45 | if {[file exists "$ProjectFolder"]} { 46 | file delete -force $ProjectFolder 47 | } 48 | 49 | set scriptPath [file dirname [file normalize [info script]]] 50 | set sourceRoot [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 51 | 52 | if {[string compare [version -short] 2023.2] != 0} { 53 | return -code error [format "This script is for Vivado version 2023.2!"] 54 | } 55 | 56 | create_project $ProjectName $ProjectFolder -part xcvu9p-fsgd2104-2L-e 57 | 58 | create_bd_design "bd" 59 | 60 | set_param synth.maxThreads 8 61 | set_param general.maxThreads 12 62 | 63 | import_files -norecurse $sourceRoot/Memory/Crutial_Ballistix_Sport/BLS4G4D240FSB.csv 64 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc 65 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM1.xdc 66 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM2.xdc 67 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM3.xdc 68 | 69 | #Uncomment to create local copy of files. 70 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc 71 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM1.xdc 72 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM2.xdc 73 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_BCU1525/BCU1525_DIMM3.xdc 74 | 75 | startgroup 76 | create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 77 | endgroup 78 | 79 | startgroup 80 | make_bd_intf_pins_external [get_bd_intf_pins xdma_0/pcie_mgt] 81 | set_property name pci_express_x1 [get_bd_intf_ports pcie_mgt_0] 82 | make_bd_pins_external [get_bd_pins xdma_0/sys_rst_n] 83 | set_property name pcie_perstn [get_bd_ports sys_rst_n_0] 84 | endgroup 85 | 86 | startgroup 87 | set_property -dict [list CONFIG.mode_selection {Basic}] [get_bd_cells xdma_0] 88 | set_property -dict [list CONFIG.xdma_pcie_64bit_en {true} CONFIG.pf0_msix_cap_table_bir {BAR_1:0} CONFIG.pf0_msix_cap_pba_bir {BAR_1:0}] [get_bd_cells xdma_0] 89 | endgroup 90 | 91 | startgroup 92 | create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 93 | endgroup 94 | 95 | startgroup 96 | set_property -dict [list CONFIG.C_BUF_TYPE {IBUFDSGTE}] [get_bd_cells util_ds_buf_0] 97 | #set_property -dict [list CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk}] [get_bd_cells util_ds_buf_0] 98 | make_bd_intf_pins_external [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] 99 | set_property name pcie_refclk [get_bd_intf_ports CLK_IN_D_0] 100 | connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] 101 | connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] 102 | endgroup 103 | 104 | startgroup 105 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 106 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_1 107 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_2 108 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_3 109 | 110 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_DDR4] 111 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_1/C0_DDR4] 112 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_2/C0_DDR4] 113 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_3/C0_DDR4] 114 | 115 | set_property name C1_DDR4_0 [get_bd_intf_ports C0_DDR4_1] 116 | set_property name C2_DDR4_0 [get_bd_intf_ports C0_DDR4_2] 117 | set_property name C3_DDR4_0 [get_bd_intf_ports C0_DDR4_3] 118 | endgroup 119 | 120 | if {$MEM_SPEED == 2666} { 121 | startgroup 122 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_0] 123 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_1] 124 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_2] 125 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_3] 126 | 127 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 128 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_1] 129 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_2] 130 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_3] 131 | 132 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_0] 133 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_1] 134 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_2] 135 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_3] 136 | endgroup 137 | } else { 138 | startgroup 139 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_0] 140 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_1] 141 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_2] 142 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_3] 143 | 144 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 145 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_1] 146 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_2] 147 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_3] 148 | 149 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_0] 150 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_1] 151 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_2] 152 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_3] 153 | endgroup 154 | } 155 | 156 | startgroup 157 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_0] 158 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_1] 159 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_2] 160 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_3] 161 | endgroup 162 | 163 | startgroup 164 | create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 165 | set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not} CONFIG.LOGO_FILE {data/sym_notgate.png}] [get_bd_cells util_vector_logic_0] 166 | connect_bd_net [get_bd_ports pcie_perstn] [get_bd_pins util_vector_logic_0/Op1] 167 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_0/sys_rst] 168 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_1/sys_rst] 169 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_2/sys_rst] 170 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_3/sys_rst] 171 | endgroup 172 | 173 | startgroup 174 | create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc 175 | set_property -dict [list CONFIG.NUM_MI {4} CONFIG.NUM_SI {1} CONFIG.NUM_CLKS {5}] [get_bd_cells axi_smc] 176 | connect_bd_intf_net [get_bd_intf_pins xdma_0/M_AXI] [get_bd_intf_pins axi_smc/S00_AXI] 177 | connect_bd_net [get_bd_pins xdma_0/axi_aclk] [get_bd_pins axi_smc/aclk] 178 | connect_bd_net [get_bd_pins xdma_0/axi_aresetn] [get_bd_pins axi_smc/aresetn] 179 | endgroup 180 | 181 | startgroup 182 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c0_reset 183 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c1_reset 184 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c2_reset 185 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c3_reset 186 | endgroup 187 | 188 | startgroup 189 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c0_reset] 190 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c0_reset] 191 | 192 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c1_reset] 193 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c1_reset] 194 | 195 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c2_reset] 196 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c2_reset] 197 | 198 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c3_reset] 199 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c3_reset] 200 | 201 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins ddr4_c0_reset/slowest_sync_clk] 202 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c0_reset/ext_reset_in] 203 | connect_bd_net [get_bd_pins ddr4_c0_reset/peripheral_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] 204 | 205 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk] [get_bd_pins ddr4_c1_reset/slowest_sync_clk] 206 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c1_reset/ext_reset_in] 207 | connect_bd_net [get_bd_pins ddr4_c1_reset/peripheral_aresetn] [get_bd_pins ddr4_1/c0_ddr4_aresetn] 208 | 209 | connect_bd_net [get_bd_pins ddr4_2/c0_ddr4_ui_clk] [get_bd_pins ddr4_c2_reset/slowest_sync_clk] 210 | connect_bd_net [get_bd_pins ddr4_2/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c2_reset/ext_reset_in] 211 | connect_bd_net [get_bd_pins ddr4_c2_reset/peripheral_aresetn] [get_bd_pins ddr4_2/c0_ddr4_aresetn] 212 | 213 | connect_bd_net [get_bd_pins ddr4_3/c0_ddr4_ui_clk] [get_bd_pins ddr4_c3_reset/slowest_sync_clk] 214 | connect_bd_net [get_bd_pins ddr4_3/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c3_reset/ext_reset_in] 215 | connect_bd_net [get_bd_pins ddr4_c3_reset/peripheral_aresetn] [get_bd_pins ddr4_3/c0_ddr4_aresetn] 216 | endgroup 217 | 218 | startgroup 219 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk1] 220 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk2] 221 | connect_bd_net [get_bd_pins ddr4_2/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk3] 222 | connect_bd_net [get_bd_pins ddr4_3/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk4] 223 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] 224 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M01_AXI] [get_bd_intf_pins ddr4_1/C0_DDR4_S_AXI] 225 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M02_AXI] [get_bd_intf_pins ddr4_2/C0_DDR4_S_AXI] 226 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M03_AXI] [get_bd_intf_pins ddr4_3/C0_DDR4_S_AXI] 227 | 228 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_SYS_CLK] 229 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_1/C0_SYS_CLK] 230 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_2/C0_SYS_CLK] 231 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_3/C0_SYS_CLK] 232 | 233 | set_property name dimm0_refclk [get_bd_intf_ports C0_SYS_CLK_0] 234 | set_property name dimm1_refclk [get_bd_intf_ports C0_SYS_CLK_1] 235 | set_property name dimm2_refclk [get_bd_intf_ports C0_SYS_CLK_2] 236 | set_property name dimm3_refclk [get_bd_intf_ports C0_SYS_CLK_3] 237 | 238 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm0_refclk] 239 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm1_refclk] 240 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm2_refclk] 241 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm3_refclk] 242 | endgroup 243 | 244 | 245 | assign_bd_address 246 | 247 | make_wrapper -files [get_files ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/bd.bd] -top 248 | add_files -norecurse ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/hdl/bd_wrapper.v 249 | 250 | -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/VCU1525_DIMM2.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | # For VCU1525 Only! DDR4 UDIMM 64-bit, rank 1. 22 | 23 | set_property -dict {PACKAGE_PIN D36 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports C2_DDR4_0_reset_n] 24 | 25 | set_property -dict {PACKAGE_PIN D33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ba[0]] 26 | set_property -dict {PACKAGE_PIN B36 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ba[1]] 27 | set_property -dict {PACKAGE_PIN C31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_bg[0]] 28 | set_property -dict {PACKAGE_PIN J30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_bg[1]] 29 | set_property -dict {PACKAGE_PIN G30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_cke[0]] 30 | set_property -dict {PACKAGE_PIN E33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_odt[0]] 31 | set_property -dict {PACKAGE_PIN B35 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_cs_n[0]] 32 | set_property -dict {PACKAGE_PIN B34 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ck_c[0]] 33 | set_property -dict {PACKAGE_PIN C34 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_ck_t[0]] 34 | 35 | set_property -dict {PACKAGE_PIN B31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_act_n] 36 | set_property -dict {PACKAGE_PIN L29 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[0]] 37 | set_property -dict {PACKAGE_PIN A33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[1]] 38 | set_property -dict {PACKAGE_PIN C33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[2]] 39 | set_property -dict {PACKAGE_PIN J29 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[3]] 40 | set_property -dict {PACKAGE_PIN H31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[4]] 41 | set_property -dict {PACKAGE_PIN G31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[5]] 42 | set_property -dict {PACKAGE_PIN C32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[6]] 43 | set_property -dict {PACKAGE_PIN B32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[7]] 44 | set_property -dict {PACKAGE_PIN A32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[8]] 45 | set_property -dict {PACKAGE_PIN D31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[9]] 46 | set_property -dict {PACKAGE_PIN A34 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[10]] 47 | set_property -dict {PACKAGE_PIN E31 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[11]] 48 | set_property -dict {PACKAGE_PIN M30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[12]] 49 | set_property -dict {PACKAGE_PIN F33 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[13]] 50 | set_property -dict {PACKAGE_PIN A35 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[14]] 51 | set_property -dict {PACKAGE_PIN G32 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[15]] 52 | set_property -dict {PACKAGE_PIN K30 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C2_DDR4_0_adr[16]] 53 | 54 | set_property -dict {PACKAGE_PIN R25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[0]] 55 | set_property -dict {PACKAGE_PIN P25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[1]] 56 | set_property -dict {PACKAGE_PIN M25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[2]] 57 | set_property -dict {PACKAGE_PIN L25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[3]] 58 | set_property -dict {PACKAGE_PIN P26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[4]] 59 | set_property -dict {PACKAGE_PIN R26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[5]] 60 | set_property -dict {PACKAGE_PIN N27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[6]] 61 | set_property -dict {PACKAGE_PIN N28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[7]] 62 | set_property -dict {PACKAGE_PIN J28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[8]] 63 | set_property -dict {PACKAGE_PIN H29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[9]] 64 | set_property -dict {PACKAGE_PIN H28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[10]] 65 | set_property -dict {PACKAGE_PIN G29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[11]] 66 | set_property -dict {PACKAGE_PIN K25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[12]] 67 | set_property -dict {PACKAGE_PIN L27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[13]] 68 | set_property -dict {PACKAGE_PIN K26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[14]] 69 | set_property -dict {PACKAGE_PIN K27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[15]] 70 | set_property -dict {PACKAGE_PIN F27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[16]] 71 | set_property -dict {PACKAGE_PIN E27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[17]] 72 | set_property -dict {PACKAGE_PIN E28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[18]] 73 | set_property -dict {PACKAGE_PIN D28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[19]] 74 | set_property -dict {PACKAGE_PIN G27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[20]] 75 | set_property -dict {PACKAGE_PIN G26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[21]] 76 | set_property -dict {PACKAGE_PIN F28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[22]] 77 | set_property -dict {PACKAGE_PIN F29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[23]] 78 | set_property -dict {PACKAGE_PIN D26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[24]] 79 | set_property -dict {PACKAGE_PIN C26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[25]] 80 | set_property -dict {PACKAGE_PIN B27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[26]] 81 | set_property -dict {PACKAGE_PIN B26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[27]] 82 | set_property -dict {PACKAGE_PIN A29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[28]] 83 | set_property -dict {PACKAGE_PIN A30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[29]] 84 | set_property -dict {PACKAGE_PIN C27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[30]] 85 | set_property -dict {PACKAGE_PIN C28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[31]] 86 | set_property -dict {PACKAGE_PIN F35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[32]] 87 | set_property -dict {PACKAGE_PIN E38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[33]] 88 | set_property -dict {PACKAGE_PIN D38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[34]] 89 | set_property -dict {PACKAGE_PIN E35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[35]] 90 | set_property -dict {PACKAGE_PIN E36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[36]] 91 | set_property -dict {PACKAGE_PIN E37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[37]] 92 | set_property -dict {PACKAGE_PIN F38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[38]] 93 | set_property -dict {PACKAGE_PIN G38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[39]] 94 | set_property -dict {PACKAGE_PIN P30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[40]] 95 | set_property -dict {PACKAGE_PIN R30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[41]] 96 | set_property -dict {PACKAGE_PIN P29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[42]] 97 | set_property -dict {PACKAGE_PIN N29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[43]] 98 | set_property -dict {PACKAGE_PIN L32 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[44]] 99 | set_property -dict {PACKAGE_PIN M32 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[45]] 100 | set_property -dict {PACKAGE_PIN P31 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[46]] 101 | set_property -dict {PACKAGE_PIN N32 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[47]] 102 | set_property -dict {PACKAGE_PIN J35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[48]] 103 | set_property -dict {PACKAGE_PIN K35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[49]] 104 | set_property -dict {PACKAGE_PIN L33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[50]] 105 | set_property -dict {PACKAGE_PIN K33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[51]] 106 | set_property -dict {PACKAGE_PIN J34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[52]] 107 | set_property -dict {PACKAGE_PIN J33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[53]] 108 | set_property -dict {PACKAGE_PIN N34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[54]] 109 | set_property -dict {PACKAGE_PIN P34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[55]] 110 | set_property -dict {PACKAGE_PIN H36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[56]] 111 | set_property -dict {PACKAGE_PIN G36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[57]] 112 | set_property -dict {PACKAGE_PIN H37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[58]] 113 | set_property -dict {PACKAGE_PIN J36 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[59]] 114 | set_property -dict {PACKAGE_PIN K37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[60]] 115 | set_property -dict {PACKAGE_PIN K38 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[61]] 116 | set_property -dict {PACKAGE_PIN G35 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[62]] 117 | set_property -dict {PACKAGE_PIN G34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dq[63]] 118 | 119 | set_property -dict {PACKAGE_PIN M26 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[0]] 120 | set_property -dict {PACKAGE_PIN N26 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[0]] 121 | set_property -dict {PACKAGE_PIN J26 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[1]] 122 | set_property -dict {PACKAGE_PIN J25 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[1]] 123 | set_property -dict {PACKAGE_PIN D30 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[2]] 124 | set_property -dict {PACKAGE_PIN D29 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[2]] 125 | set_property -dict {PACKAGE_PIN A28 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[3]] 126 | set_property -dict {PACKAGE_PIN A27 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[3]] 127 | set_property -dict {PACKAGE_PIN E40 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[4]] 128 | set_property -dict {PACKAGE_PIN E39 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[4]] 129 | set_property -dict {PACKAGE_PIN M31 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[5]] 130 | set_property -dict {PACKAGE_PIN N31 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[5]] 131 | set_property -dict {PACKAGE_PIN L36 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[6]] 132 | set_property -dict {PACKAGE_PIN L35 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[6]] 133 | set_property -dict {PACKAGE_PIN H38 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_c[7]] 134 | set_property -dict {PACKAGE_PIN J38 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dqs_t[7]] 135 | 136 | set_property -dict {PACKAGE_PIN R28 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[0]] 137 | set_property -dict {PACKAGE_PIN M27 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[1]] 138 | set_property -dict {PACKAGE_PIN H26 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[2]] 139 | set_property -dict {PACKAGE_PIN C29 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[3]] 140 | set_property -dict {PACKAGE_PIN G37 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[4]] 141 | set_property -dict {PACKAGE_PIN T30 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[5]] 142 | set_property -dict {PACKAGE_PIN M34 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[6]] 143 | set_property -dict {PACKAGE_PIN H33 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C2_DDR4_0_dm_n[7]] 144 | 145 | #300MHz clock 146 | set_property -dict {PACKAGE_PIN F32 IOSTANDARD DIFF_SSTL12} [get_ports dimm2_refclk_clk_p] 147 | set_property -dict {PACKAGE_PIN E32 IOSTANDARD DIFF_SSTL12} [get_ports dimm2_refclk_clk_n] 148 | -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/VCU1525_DIMM3.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | # For VCU1525 Only! DDR4 UDIMM 64-bit, rank 1. 22 | 23 | set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports C3_DDR4_0_reset_n] 24 | 25 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ba[0]] 26 | set_property -dict {PACKAGE_PIN H14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ba[1]] 27 | set_property -dict {PACKAGE_PIN D13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_bg[0]] 28 | set_property -dict {PACKAGE_PIN J13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_bg[1]] 29 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_cke[0]] 30 | set_property -dict {PACKAGE_PIN C16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_odt[0]] 31 | set_property -dict {PACKAGE_PIN B16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_cs_n[0]] 32 | set_property -dict {PACKAGE_PIN L13 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ck_c[0]] 33 | set_property -dict {PACKAGE_PIN L14 IOSTANDARD DIFF_SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_ck_t[0]] 34 | 35 | set_property -dict {PACKAGE_PIN H13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_act_n] 36 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[0]] 37 | set_property -dict {PACKAGE_PIN B15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[1]] 38 | set_property -dict {PACKAGE_PIN F14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[2]] 39 | set_property -dict {PACKAGE_PIN A15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[3]] 40 | set_property -dict {PACKAGE_PIN C14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[4]] 41 | set_property -dict {PACKAGE_PIN A14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[5]] 42 | set_property -dict {PACKAGE_PIN B14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[6]] 43 | set_property -dict {PACKAGE_PIN E13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[7]] 44 | set_property -dict {PACKAGE_PIN F13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[8]] 45 | set_property -dict {PACKAGE_PIN A13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[9]] 46 | set_property -dict {PACKAGE_PIN D14 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[10]] 47 | set_property -dict {PACKAGE_PIN C13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[11]] 48 | set_property -dict {PACKAGE_PIN B13 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[12]] 49 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[13]] 50 | set_property -dict {PACKAGE_PIN D15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[14]] 51 | set_property -dict {PACKAGE_PIN E15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[15]] 52 | set_property -dict {PACKAGE_PIN F15 IOSTANDARD SSTL12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports C3_DDR4_0_adr[16]] 53 | 54 | set_property -dict {PACKAGE_PIN P24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[0]] 55 | set_property -dict {PACKAGE_PIN N24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[1]] 56 | set_property -dict {PACKAGE_PIN T24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[2]] 57 | set_property -dict {PACKAGE_PIN R23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[3]] 58 | set_property -dict {PACKAGE_PIN N23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[4]] 59 | set_property -dict {PACKAGE_PIN P21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[5]] 60 | set_property -dict {PACKAGE_PIN P23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[6]] 61 | set_property -dict {PACKAGE_PIN R21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[7]] 62 | set_property -dict {PACKAGE_PIN J24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[8]] 63 | set_property -dict {PACKAGE_PIN J23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[9]] 64 | set_property -dict {PACKAGE_PIN H24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[10]] 65 | set_property -dict {PACKAGE_PIN G24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[11]] 66 | set_property -dict {PACKAGE_PIN L24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[12]] 67 | set_property -dict {PACKAGE_PIN L23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[13]] 68 | set_property -dict {PACKAGE_PIN K22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[14]] 69 | set_property -dict {PACKAGE_PIN K21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[15]] 70 | set_property -dict {PACKAGE_PIN G20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[16]] 71 | set_property -dict {PACKAGE_PIN H17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[17]] 72 | set_property -dict {PACKAGE_PIN F19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[18]] 73 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[19]] 74 | set_property -dict {PACKAGE_PIN J20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[20]] 75 | set_property -dict {PACKAGE_PIN L19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[21]] 76 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[22]] 77 | set_property -dict {PACKAGE_PIN J19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[23]] 78 | set_property -dict {PACKAGE_PIN M19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[24]] 79 | set_property -dict {PACKAGE_PIN M20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[25]] 80 | set_property -dict {PACKAGE_PIN R18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[26]] 81 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[27]] 82 | set_property -dict {PACKAGE_PIN R20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[28]] 83 | set_property -dict {PACKAGE_PIN T20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[29]] 84 | set_property -dict {PACKAGE_PIN N18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[30]] 85 | set_property -dict {PACKAGE_PIN N19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[31]] 86 | set_property -dict {PACKAGE_PIN A23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[32]] 87 | set_property -dict {PACKAGE_PIN A22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[33]] 88 | set_property -dict {PACKAGE_PIN B24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[34]] 89 | set_property -dict {PACKAGE_PIN B25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[35]] 90 | set_property -dict {PACKAGE_PIN B22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[36]] 91 | set_property -dict {PACKAGE_PIN C22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[37]] 92 | set_property -dict {PACKAGE_PIN C24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[38]] 93 | set_property -dict {PACKAGE_PIN C23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[39]] 94 | set_property -dict {PACKAGE_PIN C19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[40]] 95 | set_property -dict {PACKAGE_PIN C18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[41]] 96 | set_property -dict {PACKAGE_PIN C21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[42]] 97 | set_property -dict {PACKAGE_PIN B21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[43]] 98 | set_property -dict {PACKAGE_PIN A18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[44]] 99 | set_property -dict {PACKAGE_PIN A17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[45]] 100 | set_property -dict {PACKAGE_PIN A20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[46]] 101 | set_property -dict {PACKAGE_PIN B20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[47]] 102 | set_property -dict {PACKAGE_PIN E17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[48]] 103 | set_property -dict {PACKAGE_PIN F20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[49]] 104 | set_property -dict {PACKAGE_PIN E18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[50]] 105 | set_property -dict {PACKAGE_PIN E20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[51]] 106 | set_property -dict {PACKAGE_PIN D19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[52]] 107 | set_property -dict {PACKAGE_PIN D20 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[53]] 108 | set_property -dict {PACKAGE_PIN H18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[54]] 109 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[55]] 110 | set_property -dict {PACKAGE_PIN F22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[56]] 111 | set_property -dict {PACKAGE_PIN E22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[57]] 112 | set_property -dict {PACKAGE_PIN G22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[58]] 113 | set_property -dict {PACKAGE_PIN G21 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[59]] 114 | set_property -dict {PACKAGE_PIN F24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[60]] 115 | set_property -dict {PACKAGE_PIN E25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[61]] 116 | set_property -dict {PACKAGE_PIN F25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[62]] 117 | set_property -dict {PACKAGE_PIN G25 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dq[63]] 118 | 119 | set_property -dict {PACKAGE_PIN R22 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[0]] 120 | set_property -dict {PACKAGE_PIN T22 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[0]] 121 | set_property -dict {PACKAGE_PIN H21 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[1]] 122 | set_property -dict {PACKAGE_PIN J21 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[1]] 123 | set_property -dict {PACKAGE_PIN K20 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[2]] 124 | set_property -dict {PACKAGE_PIN L20 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[2]] 125 | set_property -dict {PACKAGE_PIN P18 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[3]] 126 | set_property -dict {PACKAGE_PIN P19 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[3]] 127 | set_property -dict {PACKAGE_PIN A24 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[4]] 128 | set_property -dict {PACKAGE_PIN A25 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[4]] 129 | set_property -dict {PACKAGE_PIN B17 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[5]] 130 | set_property -dict {PACKAGE_PIN C17 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[5]] 131 | set_property -dict {PACKAGE_PIN F17 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[6]] 132 | set_property -dict {PACKAGE_PIN F18 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[6]] 133 | set_property -dict {PACKAGE_PIN E23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_c[7]] 134 | set_property -dict {PACKAGE_PIN F23 IOSTANDARD DIFF_POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dqs_t[7]] 135 | 136 | set_property -dict {PACKAGE_PIN N22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[0]] 137 | set_property -dict {PACKAGE_PIN M22 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[1]] 138 | set_property -dict {PACKAGE_PIN K18 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[2]] 139 | set_property -dict {PACKAGE_PIN N17 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[3]] 140 | set_property -dict {PACKAGE_PIN D24 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[4]] 141 | set_property -dict {PACKAGE_PIN B19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[5]] 142 | set_property -dict {PACKAGE_PIN H19 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[6]] 143 | set_property -dict {PACKAGE_PIN H23 IOSTANDARD POD12_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST IBUF_LOW_PWR FALSE ODT RTT_40 EQUALIZATION EQ_LEVEL2 PRE_EMPHASIS RDRV_240} [get_ports C3_DDR4_0_dm_n[7]] 144 | 145 | #300MHz clock 146 | set_property -dict {PACKAGE_PIN J16 IOSTANDARD DIFF_SSTL12} [get_ports dimm3_refclk_clk_p] 147 | set_property -dict {PACKAGE_PIN H16 IOSTANDARD DIFF_SSTL12} [get_ports dimm3_refclk_clk_n] 148 | -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/bitstream/pcie_x16_2400MT.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Boards/Xilinx_VCU1525/bitstream/pcie_x16_2400MT.bit -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/bitstream/pcie_x16_2400MT.ltx: -------------------------------------------------------------------------------- 1 | { 2 | "ltx_root": { 3 | "version": 4, 4 | "minor": 0, 5 | "ltx_data": [ 6 | { 7 | "name": "EDA_PROBESET", 8 | "active": true, 9 | "debug_cores": [ 10 | { 11 | "type": "XSDB_V3", 12 | "name": "dbg_hub", 13 | "spec": "labtools_xsdbm_v3", 14 | "clk_input_freq_hz": "75030011" 15 | }, 16 | { 17 | "type": "XSDBS_V2", 18 | "name": "design_1_i/ddr4_0", 19 | "spec": "labtools_xsdbslavelib_v2", 20 | "ipName": "DDR4_SDRAM", 21 | "core_location": { 22 | "user_chain": 1, 23 | "slave_index": 0, 24 | "bscan_switch_index": 0 25 | }, 26 | "uuid": "5055CCF3AB285F28A88899587C896C7C" 27 | }, 28 | { 29 | "type": "XSDBS_V2", 30 | "name": "design_1_i/ddr4_1", 31 | "spec": "labtools_xsdbslavelib_v2", 32 | "ipName": "DDR4_SDRAM", 33 | "core_location": { 34 | "user_chain": 1, 35 | "slave_index": 1, 36 | "bscan_switch_index": 0 37 | }, 38 | "uuid": "B4629568096B5679BC0585F3EF7C1106" 39 | }, 40 | { 41 | "type": "XSDBS_V2", 42 | "name": "design_1_i/ddr4_2", 43 | "spec": "labtools_xsdbslavelib_v2", 44 | "ipName": "DDR4_SDRAM", 45 | "core_location": { 46 | "user_chain": 1, 47 | "slave_index": 2, 48 | "bscan_switch_index": 0 49 | }, 50 | "uuid": "3D96250BECFC5ADB97FEE84C97874B51" 51 | }, 52 | { 53 | "type": "XSDBS_V2", 54 | "name": "design_1_i/ddr4_3", 55 | "spec": "labtools_xsdbslavelib_v2", 56 | "ipName": "DDR4_SDRAM", 57 | "core_location": { 58 | "user_chain": 1, 59 | "slave_index": 3, 60 | "bscan_switch_index": 0 61 | }, 62 | "uuid": "4105F08787FB5BCAB185230AF393F7F7" 63 | } 64 | ] 65 | } 66 | ] 67 | } 68 | } -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/bitstream/pcie_x1_2400MT.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Boards/Xilinx_VCU1525/bitstream/pcie_x1_2400MT.bit -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/bitstream/pcie_x1_2400MT.ltx: -------------------------------------------------------------------------------- 1 | { 2 | "ltx_root": { 3 | "version": 4, 4 | "minor": 0, 5 | "ltx_data": [ 6 | { 7 | "name": "EDA_PROBESET", 8 | "active": true, 9 | "debug_cores": [ 10 | { 11 | "type": "XSDB_V3", 12 | "name": "dbg_hub", 13 | "spec": "labtools_xsdbm_v3", 14 | "clk_input_freq_hz": "75030011" 15 | }, 16 | { 17 | "type": "XSDBS_V2", 18 | "name": "design_1_i/ddr4_0", 19 | "spec": "labtools_xsdbslavelib_v2", 20 | "ipName": "DDR4_SDRAM", 21 | "core_location": { 22 | "user_chain": 1, 23 | "slave_index": 0, 24 | "bscan_switch_index": 0 25 | }, 26 | "uuid": "5055CCF3AB285F28A88899587C896C7C" 27 | }, 28 | { 29 | "type": "XSDBS_V2", 30 | "name": "design_1_i/ddr4_1", 31 | "spec": "labtools_xsdbslavelib_v2", 32 | "ipName": "DDR4_SDRAM", 33 | "core_location": { 34 | "user_chain": 1, 35 | "slave_index": 1, 36 | "bscan_switch_index": 0 37 | }, 38 | "uuid": "B4629568096B5679BC0585F3EF7C1106" 39 | }, 40 | { 41 | "type": "XSDBS_V2", 42 | "name": "design_1_i/ddr4_2", 43 | "spec": "labtools_xsdbslavelib_v2", 44 | "ipName": "DDR4_SDRAM", 45 | "core_location": { 46 | "user_chain": 1, 47 | "slave_index": 2, 48 | "bscan_switch_index": 0 49 | }, 50 | "uuid": "3D96250BECFC5ADB97FEE84C97874B51" 51 | }, 52 | { 53 | "type": "XSDBS_V2", 54 | "name": "design_1_i/ddr4_3", 55 | "spec": "labtools_xsdbslavelib_v2", 56 | "ipName": "DDR4_SDRAM", 57 | "core_location": { 58 | "user_chain": 1, 59 | "slave_index": 3, 60 | "bscan_switch_index": 0 61 | }, 62 | "uuid": "4105F08787FB5BCAB185230AF393F7F7" 63 | } 64 | ] 65 | } 66 | ] 67 | } 68 | } -------------------------------------------------------------------------------- /Boards/Xilinx_VCU1525/create_project.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | 22 | #Need apply patch to Xilinx MIG before can enable DDR4-2666 speed for DIMM/UDIMM. 23 | set MEM_SPEED 2400 24 | 25 | set ProjectName vcu1525_ballistix 26 | 27 | if {$MEM_SPEED == 2666} { 28 | append ProjectName $MEM_SPEED 29 | } 30 | 31 | set ProjectFolder ./$ProjectName 32 | 33 | #Remove unnecessary files. 34 | set file_list [glob -nocomplain webtalk*.*] 35 | foreach name $file_list { 36 | file delete $name 37 | } 38 | 39 | #Delete old project if folder already exists. 40 | if {[file exists .Xil]} { 41 | file delete -force .Xil 42 | } 43 | 44 | #Delete old project if folder already exists. 45 | if {[file exists "$ProjectFolder"]} { 46 | file delete -force $ProjectFolder 47 | } 48 | 49 | set scriptPath [file dirname [file normalize [info script]]] 50 | set sourceRoot [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 51 | 52 | if {[string compare [version -short] 2023.2] != 0} { 53 | return -code error [format "This script is for Vivado version 2023.2!"] 54 | } 55 | 56 | create_project $ProjectName $ProjectFolder -part xcvu9p-fsgd2104-2L-e 57 | create_bd_design "bd" 58 | 59 | set_param synth.maxThreads 8 60 | set_param general.maxThreads 12 61 | 62 | import_files -norecurse $sourceRoot/Memory/Crutial_Ballistix_Sport/BLS4G4D240FSB.csv 63 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM0.xdc 64 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM1.xdc 65 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM2.xdc 66 | import_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM3.xdc 67 | 68 | #Uncomment to create local copy of files. 69 | #add_files -norecurse $sourceRoot/Memory/Crutial_Ballistix_Sport/BLS4G4D240FSB.csv 70 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM0.xdc 71 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM1.xdc 72 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM2.xdc 73 | #add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_VCU1525/VCU1525_DIMM3.xdc 74 | 75 | startgroup 76 | create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 77 | endgroup 78 | 79 | startgroup 80 | make_bd_intf_pins_external [get_bd_intf_pins xdma_0/pcie_mgt] 81 | set_property name pci_express_x1 [get_bd_intf_ports pcie_mgt_0] 82 | make_bd_pins_external [get_bd_pins xdma_0/sys_rst_n] 83 | set_property name pcie_perstn [get_bd_ports sys_rst_n_0] 84 | endgroup 85 | 86 | startgroup 87 | set_property -dict [list CONFIG.mode_selection {Basic}] [get_bd_cells xdma_0] 88 | set_property -dict [list CONFIG.xdma_pcie_64bit_en {true} CONFIG.pf0_msix_cap_table_bir {BAR_1:0} CONFIG.pf0_msix_cap_pba_bir {BAR_1:0}] [get_bd_cells xdma_0] 89 | endgroup 90 | 91 | startgroup 92 | create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 93 | endgroup 94 | 95 | startgroup 96 | set_property -dict [list CONFIG.C_BUF_TYPE {IBUFDSGTE}] [get_bd_cells util_ds_buf_0] 97 | #set_property -dict [list CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk}] [get_bd_cells util_ds_buf_0] 98 | make_bd_intf_pins_external [get_bd_intf_pins util_ds_buf_0/CLK_IN_D] 99 | set_property name pcie_refclk [get_bd_intf_ports CLK_IN_D_0] 100 | connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk] 101 | connect_bd_net [get_bd_pins util_ds_buf_0/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt] 102 | endgroup 103 | 104 | startgroup 105 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 106 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_1 107 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_2 108 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_3 109 | 110 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_DDR4] 111 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_1/C0_DDR4] 112 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_2/C0_DDR4] 113 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_3/C0_DDR4] 114 | 115 | set_property name C1_DDR4_0 [get_bd_intf_ports C0_DDR4_1] 116 | set_property name C2_DDR4_0 [get_bd_intf_ports C0_DDR4_2] 117 | set_property name C3_DDR4_0 [get_bd_intf_ports C0_DDR4_3] 118 | endgroup 119 | 120 | if {$MEM_SPEED == 2666} { 121 | startgroup 122 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_0] 123 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_1] 124 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_2] 125 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750} CONFIG.C0.DDR4_InputClockPeriod {3334} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_3] 126 | 127 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 128 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_1] 129 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_2] 130 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_3] 131 | 132 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_0] 133 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_1] 134 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_2] 135 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2666} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_3] 136 | endgroup 137 | } else { 138 | startgroup 139 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_0] 140 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_1] 141 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_2] 142 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833} CONFIG.C0.DDR4_InputClockPeriod {3332} CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5}] [get_bd_cells ddr4_3] 143 | 144 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 145 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_1] 146 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_2] 147 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4D240FSB.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_3] 148 | 149 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_0] 150 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_1] 151 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_2] 152 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {UDIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4D240FSB-2400} CONFIG.C0.DDR4_DataWidth {64}] [get_bd_cells ddr4_3] 153 | endgroup 154 | } 155 | 156 | startgroup 157 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_0] 158 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_1] 159 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_2] 160 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_3] 161 | endgroup 162 | 163 | startgroup 164 | create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 165 | set_property -dict [list CONFIG.C_SIZE {1} CONFIG.C_OPERATION {not} CONFIG.LOGO_FILE {data/sym_notgate.png}] [get_bd_cells util_vector_logic_0] 166 | connect_bd_net [get_bd_ports pcie_perstn] [get_bd_pins util_vector_logic_0/Op1] 167 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_0/sys_rst] 168 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_1/sys_rst] 169 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_2/sys_rst] 170 | connect_bd_net [get_bd_pins util_vector_logic_0/Res] [get_bd_pins ddr4_3/sys_rst] 171 | endgroup 172 | 173 | startgroup 174 | create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc 175 | set_property -dict [list CONFIG.NUM_MI {4} CONFIG.NUM_SI {1} CONFIG.NUM_CLKS {5}] [get_bd_cells axi_smc] 176 | connect_bd_intf_net [get_bd_intf_pins xdma_0/M_AXI] [get_bd_intf_pins axi_smc/S00_AXI] 177 | connect_bd_net [get_bd_pins xdma_0/axi_aclk] [get_bd_pins axi_smc/aclk] 178 | connect_bd_net [get_bd_pins xdma_0/axi_aresetn] [get_bd_pins axi_smc/aresetn] 179 | endgroup 180 | 181 | startgroup 182 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c0_reset 183 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c1_reset 184 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c2_reset 185 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_c3_reset 186 | endgroup 187 | 188 | startgroup 189 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c0_reset] 190 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c0_reset] 191 | 192 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c1_reset] 193 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c1_reset] 194 | 195 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c2_reset] 196 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c2_reset] 197 | 198 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH.VALUE_SRC USER] [get_bd_cells ddr4_c3_reset] 199 | set_property -dict [list CONFIG.C_AUX_RESET_HIGH {0}] [get_bd_cells ddr4_c3_reset] 200 | 201 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins ddr4_c0_reset/slowest_sync_clk] 202 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c0_reset/ext_reset_in] 203 | connect_bd_net [get_bd_pins ddr4_c0_reset/peripheral_aresetn] [get_bd_pins ddr4_0/c0_ddr4_aresetn] 204 | 205 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk] [get_bd_pins ddr4_c1_reset/slowest_sync_clk] 206 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c1_reset/ext_reset_in] 207 | connect_bd_net [get_bd_pins ddr4_c1_reset/peripheral_aresetn] [get_bd_pins ddr4_1/c0_ddr4_aresetn] 208 | 209 | connect_bd_net [get_bd_pins ddr4_2/c0_ddr4_ui_clk] [get_bd_pins ddr4_c2_reset/slowest_sync_clk] 210 | connect_bd_net [get_bd_pins ddr4_2/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c2_reset/ext_reset_in] 211 | connect_bd_net [get_bd_pins ddr4_c2_reset/peripheral_aresetn] [get_bd_pins ddr4_2/c0_ddr4_aresetn] 212 | 213 | connect_bd_net [get_bd_pins ddr4_3/c0_ddr4_ui_clk] [get_bd_pins ddr4_c3_reset/slowest_sync_clk] 214 | connect_bd_net [get_bd_pins ddr4_3/c0_ddr4_ui_clk_sync_rst] [get_bd_pins ddr4_c3_reset/ext_reset_in] 215 | connect_bd_net [get_bd_pins ddr4_c3_reset/peripheral_aresetn] [get_bd_pins ddr4_3/c0_ddr4_aresetn] 216 | endgroup 217 | 218 | startgroup 219 | connect_bd_net [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk1] 220 | connect_bd_net [get_bd_pins ddr4_1/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk2] 221 | connect_bd_net [get_bd_pins ddr4_2/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk3] 222 | connect_bd_net [get_bd_pins ddr4_3/c0_ddr4_ui_clk] [get_bd_pins axi_smc/aclk4] 223 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] 224 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M01_AXI] [get_bd_intf_pins ddr4_1/C0_DDR4_S_AXI] 225 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M02_AXI] [get_bd_intf_pins ddr4_2/C0_DDR4_S_AXI] 226 | connect_bd_intf_net [get_bd_intf_pins axi_smc/M03_AXI] [get_bd_intf_pins ddr4_3/C0_DDR4_S_AXI] 227 | 228 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_SYS_CLK] 229 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_1/C0_SYS_CLK] 230 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_2/C0_SYS_CLK] 231 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_3/C0_SYS_CLK] 232 | 233 | 234 | set_property name dimm0_refclk [get_bd_intf_ports C0_SYS_CLK_0] 235 | set_property name dimm1_refclk [get_bd_intf_ports C0_SYS_CLK_1] 236 | set_property name dimm2_refclk [get_bd_intf_ports C0_SYS_CLK_2] 237 | set_property name dimm3_refclk [get_bd_intf_ports C0_SYS_CLK_3] 238 | 239 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm0_refclk] 240 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm1_refclk] 241 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm2_refclk] 242 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /dimm3_refclk] 243 | endgroup 244 | 245 | 246 | assign_bd_address 247 | 248 | make_wrapper -files [get_files ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/bd.bd] -top 249 | add_files -norecurse ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/hdl/bd_wrapper.v 250 | 251 | -------------------------------------------------------------------------------- /Boards/Xilinx_ZCU104/ZCU104_TESTSTAND.xdc: -------------------------------------------------------------------------------- 1 | 2 | set_property BITSTREAM.CONFIG.PUDC_B Pulldown [current_design] 3 | 4 | # PMU IO on FMC LPC of ZCU104 5 | set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports PMU_IO_power_int] 6 | set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports PMU_IO_kill_power] 7 | 8 | set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports FMC_IO_EN] 9 | 10 | -------------------------------------------------------------------------------- /Boards/Xilinx_ZCU104/create_project.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | #Need apply patch to Xilinx MIG before can enable DDR4-2666 speed for DIMM/UDIMM. 22 | set MEM_SPEED 2400 23 | 24 | set ProjectName zcu104_ballistix 25 | 26 | if {$MEM_SPEED == 2666} { 27 | append ProjectName $MEM_SPEED 28 | } 29 | 30 | set ProjectFolder ./$ProjectName 31 | 32 | #Remove unnecessary files. 33 | set file_list [glob -nocomplain webtalk*.*] 34 | foreach name $file_list { 35 | file delete $name 36 | } 37 | 38 | #Delete old project if folder already exists. 39 | if {[file exists .Xil]} { 40 | file delete -force .Xil 41 | } 42 | 43 | #Delete old project if folder already exists. 44 | if {[file exists "$ProjectFolder"]} { 45 | file delete -force $ProjectFolder 46 | } 47 | 48 | set scriptPath [file dirname [file normalize [info script]]] 49 | set sourceRoot [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 50 | #puts stdout [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 51 | #return -code 1 52 | 53 | if {[string compare [version -short] 2023.2] != 0} { 54 | return -code error [format "This script is for Vivado version 2023.2!"] 55 | } 56 | 57 | create_project $ProjectName ./$ProjectName -part xczu7ev-ffvc1156-2-e 58 | set_property board_part xilinx.com:zcu104:part0:1.1 [current_project] 59 | 60 | create_bd_design "bd" 61 | 62 | set_param synth.maxThreads 8 63 | set_param general.maxThreads 12 64 | 65 | import_files -norecurse $sourceRoot/Memory/Crutial_Ballistix_Sport/BLS4G4S26BFSD.csv 66 | import_files -norecurse $sourceRoot/Memory/Micron_MTA8ATF1G64HZ/MTA8ATF1G64HZ.csv 67 | 68 | startgroup 69 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 70 | #apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {clk_300mhz ( Programmable Differential Clock (300MHz) ) } Manual_Source {Auto}} [get_bd_intf_pins ddr4_0/C0_SYS_CLK] 71 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_DDR4] 72 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_0/C0_SYS_CLK] 73 | set_property name sodimm_refclk [get_bd_intf_ports C0_SYS_CLK_0] 74 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /sodimm_refclk] 75 | endgroup 76 | 77 | if {$MEM_SPEED == 2666} { 78 | startgroup 79 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750}] [get_bd_cells ddr4_0] 80 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4S26BFSD.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 81 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {SODIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4S26BFSD-2666} CONFIG.C0.DDR4_DataWidth {64} CONFIG.C0.DDR4_AxiDataWidth {512} CONFIG.C0.DDR4_AxiAddressWidth {32}] [get_bd_cells ddr4_0] 82 | set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3334}] [get_bd_cells ddr4_0] 83 | endgroup 84 | } else { 85 | startgroup 86 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] [get_bd_cells ddr4_0] 87 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */BLS4G4S26BFSD.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_0] 88 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {SODIMMs} CONFIG.C0.DDR4_MemoryPart {BLS4G4S26BFSD-2400} CONFIG.C0.DDR4_DataWidth {64} CONFIG.C0.DDR4_AxiDataWidth {512} CONFIG.C0.DDR4_AxiAddressWidth {32}] [get_bd_cells ddr4_0] 89 | set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3332}] [get_bd_cells ddr4_0] 90 | endgroup 91 | } 92 | 93 | startgroup 94 | create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 95 | apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ultra_ps_e_0] 96 | endgroup 97 | 98 | startgroup 99 | set_property -dict [list CONFIG.PSU__USE__M_AXI_GP0 {1} CONFIG.PSU__USE__M_AXI_GP1 {0} CONFIG.PSU__USE__M_AXI_GP2 {0}] [get_bd_cells zynq_ultra_ps_e_0] 100 | apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {reset ( FPGA Reset ) } Manual_Source {New External Port (ACTIVE_HIGH)}} [get_bd_pins ddr4_0/sys_rst] 101 | apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {/ddr4_0/c0_ddr4_ui_clk (333 MHz)} Clk_xbar {Auto} Master {/zynq_ultra_ps_e_0/M_AXI_HPM0_FPD} Slave {/ddr4_0/C0_DDR4_S_AXI} intc_ip {Auto} master_apm {0}} [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] 102 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_0] 103 | endgroup 104 | 105 | assign_bd_address 106 | set_property range 4G [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK}] 107 | 108 | add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_ZCU104/ZCU104_SODIMM.xdc 109 | import_files -fileset constrs_1 $sourceRoot/Boards/Xilinx_ZCU104/ZCU104_SODIMM.xdc 110 | 111 | make_wrapper -files [get_files ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/bd.bd] -top 112 | add_files -norecurse ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/hdl/bd_wrapper.v 113 | update_compile_order -fileset sources_1 114 | 115 | -------------------------------------------------------------------------------- /Boards/Xilinx_ZCU104/create_project_teststand.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | #Need apply patch to Xilinx MIG before can enable DDR4-2666 speed for DIMM/UDIMM. 22 | set MEM_SPEED 2400 23 | set MEM_PARTNUMBER MTA8ATF1G64HZ 24 | #set MEM_PARTNUMBER BLS4G4S26BFSD 25 | set USE_JTAG2AXI 1 26 | set USE_PMU 1 27 | set POWER_BUTTON 1 28 | 29 | set ProjectName ZCU104_TESTSTAND 30 | 31 | if {$MEM_SPEED == 2666} { 32 | append ProjectName $MEM_SPEED 33 | } 34 | 35 | set ProjectFolder ./$ProjectName 36 | 37 | #Remove unnecessary files. 38 | set file_list [glob -nocomplain webtalk*.*] 39 | foreach name $file_list { 40 | file delete $name 41 | } 42 | 43 | #Delete old project if folder already exists. 44 | if {[file exists .Xil]} { 45 | file delete -force .Xil 46 | } 47 | 48 | #Delete old project if folder already exists. 49 | if {[file exists "$ProjectFolder"]} { 50 | file delete -force $ProjectFolder 51 | } 52 | 53 | set scriptPath [file dirname [file normalize [info script]]] 54 | set sourceRoot [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 55 | #puts stdout [join [lrange [file split [file dirname [info script]]] 0 end-2] "/"] 56 | #return -code 1 57 | 58 | create_project $ProjectName ./$ProjectName -part xczu7ev-ffvc1156-2-e 59 | set_property board_part xilinx.com:zcu104:part0:1.1 [current_project] 60 | 61 | create_bd_design "bd" 62 | 63 | set_param synth.maxThreads 8 64 | set_param general.maxThreads 12 65 | 66 | set_property ip_repo_paths $sourceRoot/Interfaces [current_project] 67 | 68 | set MEM_SPEED_STR 2400 69 | set MEM_ADDR_WIDTH 32 70 | if {$::MEM_PARTNUMBER == "BLS4G4S26BFSD"} { 71 | import_files -norecurse $sourceRoot/Memory/Crutial_Ballistix_Sport/BLS4G4S26BFSD.csv 72 | if {$MEM_SPEED == "2666"} { 73 | set MEM_SPEED_STR 2666 74 | } elseif {$MEM_SPEED == "2400"} { 75 | set MEM_SPEED_STR 2400 76 | } 77 | } 78 | 79 | if {$::MEM_PARTNUMBER == "MTA8ATF1G64HZ"} { 80 | import_files -norecurse $sourceRoot/Memory/Micron_MTA8ATF1G64HZ/MTA8ATF1G64HZ.csv 81 | set MEM_ADDR_WIDTH 33 82 | if {$MEM_SPEED == "2666"} { 83 | set MEM_SPEED_STR 2G6 84 | } elseif {$MEM_SPEED == "2400"} { 85 | set MEM_SPEED_STR 2G3 86 | } 87 | } 88 | 89 | update_ip_catalog 90 | update_compile_order -fileset sources_1 91 | 92 | startgroup 93 | create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_pl 94 | #apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {clk_300mhz ( Programmable Differential Clock (300MHz) ) } Manual_Source {Auto}} [get_bd_intf_pins ddr4_pl/C0_SYS_CLK] 95 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_pl/C0_DDR4] 96 | make_bd_intf_pins_external [get_bd_intf_pins ddr4_pl/C0_SYS_CLK] 97 | set_property name sodimm_refclk [get_bd_intf_ports C0_SYS_CLK_0] 98 | set_property CONFIG.FREQ_HZ 300000000 [get_bd_intf_ports /sodimm_refclk] 99 | endgroup 100 | 101 | set SODIMM [format %s-%s $MEM_PARTNUMBER $MEM_SPEED_STR] 102 | if {$MEM_SPEED == 2666} { 103 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {750}] [get_bd_cells ddr4_pl] 104 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */$MEM_PARTNUMBER.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_pl] 105 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {SODIMMs} CONFIG.C0.DDR4_MemoryPart ${SODIMM} CONFIG.C0.DDR4_DataWidth {64} CONFIG.C0.DDR4_AxiDataWidth {512} CONFIG.C0.DDR4_AxiAddressWidth ${MEM_ADDR_WIDTH}] [get_bd_cells ddr4_pl] 106 | set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3334}] [get_bd_cells ddr4_pl] 107 | } else { 108 | set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] [get_bd_cells ddr4_pl] 109 | set_property -dict [list CONFIG.C0.DDR4_CustomParts [lindex [get_files */$MEM_PARTNUMBER.csv] 0] CONFIG.C0.DDR4_isCustom {true}] [get_bd_cells ddr4_pl] 110 | set_property -dict [list CONFIG.C0.DDR4_MemoryType {SODIMMs} CONFIG.C0.DDR4_MemoryPart ${SODIMM} CONFIG.C0.DDR4_DataWidth {64} CONFIG.C0.DDR4_AxiDataWidth {512} CONFIG.C0.DDR4_AxiAddressWidth ${MEM_ADDR_WIDTH}] [get_bd_cells ddr4_pl] 111 | set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3332}] [get_bd_cells ddr4_pl] 112 | } 113 | 114 | startgroup 115 | create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.5 zynq_ultra_ps_e_0 116 | apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ultra_ps_e_0] 117 | endgroup 118 | 119 | startgroup 120 | set_property -dict [list CONFIG.PSU__USE__M_AXI_GP0 {1} CONFIG.PSU__USE__M_AXI_GP1 {0} CONFIG.PSU__USE__M_AXI_GP2 {0}] [get_bd_cells zynq_ultra_ps_e_0] 121 | apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {reset ( FPGA Reset ) } Manual_Source {New External Port (ACTIVE_HIGH)}} [get_bd_pins ddr4_pl/sys_rst] 122 | apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {/ddr4_pl/c0_ddr4_ui_clk (333 MHz)} Clk_xbar {Auto} Master {/zynq_ultra_ps_e_0/M_AXI_HPM0_FPD} Slave {/ddr4_pl/C0_DDR4_S_AXI} intc_ip {Auto} master_apm {0}} [get_bd_intf_pins ddr4_pl/C0_DDR4_S_AXI] 123 | set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] [get_bd_cells ddr4_pl] 124 | endgroup 125 | 126 | set_property -dict [list CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 10 .. 11}] [get_bd_cells zynq_ultra_ps_e_0] 127 | 128 | #HDMI TX 129 | #if {$HDMI == 1} 130 | #{ 131 | # create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 ibufds_gt_odiv2 132 | # set_property -dict [list CONFIG.C_BUF_TYPE {BUFG_GT}] [get_bd_cells ibufds_gt_odiv2] 133 | # 134 | # create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 ibufds_gt 135 | # set_property -dict [list CONFIG.C_BUF_TYPE {IBUFDSGTE}] [get_bd_cells ibufds_gt] 136 | # 137 | # create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_vcc 138 | #} 139 | 140 | if {$USE_JTAG2AXI == 1} { 141 | 142 | set DATA_WIDTH [get_property CONFIG.C0.DDR4_DataWidth [get_bd_cells ddr4_pl]] 143 | #set ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth [get_bd_cells ddr4_pl]] 144 | 145 | create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag2axi 146 | set_property -dict [list CONFIG.M_AXI_DATA_WIDTH $DATA_WIDTH CONFIG.M_AXI_ADDR_WIDTH {64}] [get_bd_cells jtag2axi] 147 | 148 | set N_MI [get_property CONFIG.NUM_SI [get_bd_cells axi_smc]] 149 | set_property -dict [list CONFIG.NUM_SI [expr {$N_MI + 1}]] [get_bd_cells axi_smc] 150 | 151 | connect_bd_net [get_bd_pins ddr4_pl/c0_ddr4_ui_clk] [get_bd_pins jtag2axi/aclk] 152 | connect_bd_net [get_bd_pins rst_ddr4_pl_300M/peripheral_aresetn] [get_bd_pins jtag2axi/aresetn] 153 | connect_bd_intf_net [get_bd_intf_pins jtag2axi/M_AXI] [get_bd_intf_pins axi_smc/S01_AXI] 154 | } 155 | 156 | if {$USE_PMU == 1} { 157 | 158 | set_property -dict [list CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} CONFIG.PSU__PMU__GPI1__ENABLE {0} \ 159 | CONFIG.PSU__PMU__GPI2__ENABLE {0} CONFIG.PSU__PMU__GPI3__ENABLE {0} \ 160 | CONFIG.PSU__PMU__GPI4__ENABLE {0} CONFIG.PSU__PMU__GPI5__ENABLE {0} \ 161 | CONFIG.PSU__PMU__GPO0__ENABLE {0} CONFIG.PSU__PMU__GPO1__ENABLE {0} \ 162 | CONFIG.PSU__PMU__GPO2__ENABLE {0} CONFIG.PSU__PMU__GPO3__ENABLE {0} \ 163 | CONFIG.PSU__PMU__GPO4__ENABLE {0} CONFIG.PSU__PMU__GPO5__ENABLE {0}] [get_bd_cells zynq_ultra_ps_e_0] 164 | 165 | if {$POWER_BUTTON == 1} { 166 | 167 | add_files -norecurse $sourceRoot/Boards/Xilinx_ZCU104/teststand_pmu_io.v 168 | 169 | set_property -dict [list CONFIG.PSU__PMU__GPI0__ENABLE {0} CONFIG.PSU__PMU__GPO2__ENABLE {0}] [get_bd_cells zynq_ultra_ps_e_0] 170 | set_property -dict [list CONFIG.PSU__PMU__EMIO_GPI__ENABLE {1} CONFIG.PSU__PMU__EMIO_GPO__ENABLE {1}] [get_bd_cells zynq_ultra_ps_e_0] 171 | 172 | create_bd_cell -type module -reference pmu_io PMU_IO 173 | connect_bd_net [get_bd_pins ddr4_pl/c0_ddr4_ui_clk] [get_bd_pins PMU_IO/CLOCK] 174 | connect_bd_net [get_bd_pins rst_ddr4_pl_300M/peripheral_aresetn] [get_bd_pins PMU_IO/RESETN] 175 | 176 | connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pmu_pl_gpo] [get_bd_pins PMU_IO/PMU_GPO] 177 | connect_bd_net [get_bd_pins PMU_IO/PMU_GPI] [get_bd_pins zynq_ultra_ps_e_0/pl_pmu_gpi] 178 | 179 | make_bd_intf_pins_external [get_bd_intf_pins PMU_IO/PMU_IO] 180 | set_property name PMU_IO [get_bd_intf_ports PMU_IO_0] 181 | 182 | create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 CONSTANT_FMC 183 | make_bd_pins_external [get_bd_pins CONSTANT_FMC/dout] 184 | set_property name FMC_IO_EN [get_bd_ports dout_0] 185 | } 186 | } 187 | 188 | #Set MicroSD clock to 50MHz 189 | set_property -dict [list CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {50}] [get_bd_cells zynq_ultra_ps_e_0] 190 | 191 | 192 | assign_bd_address 193 | set_property range 8G [get_bd_addr_segs {zynq_ultra_ps_e_0/Data/SEG_ddr4_pl_C0_DDR4_ADDRESS_BLOCK}] 194 | 195 | add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_ZCU104/ZCU104_SODIMM.xdc 196 | import_files -fileset constrs_1 $sourceRoot/Boards/Xilinx_ZCU104/ZCU104_SODIMM.xdc 197 | 198 | add_files -fileset constrs_1 -norecurse $sourceRoot/Boards/Xilinx_ZCU104/ZCU104_TESTSTAND.xdc 199 | import_files -fileset constrs_1 $sourceRoot/Boards/Xilinx_ZCU104/ZCU104_TESTSTAND.xdc 200 | 201 | 202 | make_wrapper -files [get_files ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/bd.bd] -top 203 | add_files -norecurse ./$ProjectName/$ProjectName.srcs/sources_1/bd/bd/hdl/bd_wrapper.v 204 | update_compile_order -fileset sources_1 205 | 206 | -------------------------------------------------------------------------------- /Boards/Xilinx_ZCU104/teststand_pmu_io.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1ps/1ps 3 | 4 | module pmu_io # 5 | ( 6 | parameter CLOCK_FREQUENCE = 300000000, 7 | parameter POWERKILL_DELAY = 300000000 8 | ) 9 | ( 10 | input wire CLOCK, 11 | input wire RESETN, 12 | 13 | (* X_INTERFACE_IGNORE = "true" *) 14 | input wire [31:0] PMU_GPO, 15 | (* X_INTERFACE_IGNORE = "true" *) 16 | output wire [31:0] PMU_GPI, 17 | 18 | (* X_INTERFACE_MODE = "Master" *) 19 | (* X_INTERFACE_INFO = "divashin:user:pmu_io:1.0 PMU_IO POWER_INT" *) 20 | input wire POWER_INT, 21 | (* X_INTERFACE_INFO = "divashin:user:pmu_io:1.0 PMU_IO KILL_POWER" *) 22 | output wire KILL_POWER 23 | ); 24 | 25 | //reg [31:0] kill_counter; 26 | //always @(posedge CLOCK) begin 27 | // if (!RESETN) begin 28 | // kill_counter <= 0; 29 | // KILL_POWER <= 0; 30 | // end else begin 31 | // if (PMU_GPO[0]) begin 32 | // kill_counter <= kill_counter + 1; 33 | // if (kill_counter >= POWERKILL_DELAY) begin 34 | // KILL_POWER <= 1; 35 | // end 36 | // end 37 | // end 38 | //end 39 | 40 | assign PMU_GPI[0] = POWER_INT; 41 | assign KILL_POWER = PMU_GPO[0]; 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /Images/BCU1525_Quad_DDR4_BlockDiagram.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Images/BCU1525_Quad_DDR4_BlockDiagram.PNG -------------------------------------------------------------------------------- /Images/BCU1525_Quad_DDR4_Calibration.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Images/BCU1525_Quad_DDR4_Calibration.PNG -------------------------------------------------------------------------------- /Images/BCU1525_Quad_DDR4_MemoryMap.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Images/BCU1525_Quad_DDR4_MemoryMap.PNG -------------------------------------------------------------------------------- /Images/BCU1525_SourceScript.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Images/BCU1525_SourceScript.PNG -------------------------------------------------------------------------------- /Images/vu9p_bank48.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Images/vu9p_bank48.PNG -------------------------------------------------------------------------------- /Images/zcu104_ioplanner.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Images/zcu104_ioplanner.PNG -------------------------------------------------------------------------------- /Interfaces/PMU_IO.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | divashin 4 | user 5 | pmu_io 6 | 1.0 7 | false 8 | false 9 | 1 10 | 1 11 | 12 | -------------------------------------------------------------------------------- /Interfaces/PMU_IO_rtl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | divashin 4 | user 5 | pmu_io_rtl 6 | 1.0 7 | 8 | 9 | 10 | KILL_POWER 11 | Kill Power 12 | 13 | 14 | true 15 | 16 | 17 | required 18 | 1 19 | out 20 | 21 | 22 | required 23 | 1 24 | in 25 | 26 | 1 27 | 28 | 29 | 30 | 31 | POWER_INT 32 | Power Interrupt 33 | 34 | 35 | true 36 | 37 | 38 | required 39 | 1 40 | in 41 | 42 | 43 | required 44 | 1 45 | out 46 | 47 | 1 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, 10 | and distribution as defined by Sections 1 through 9 of this document. 11 | 12 | "Licensor" shall mean the copyright owner or entity authorized by 13 | the copyright owner that is granting the License. 14 | 15 | "Legal Entity" shall mean the union of the acting entity and all 16 | other entities that control, are controlled by, or are under common 17 | control with that entity. For the purposes of this definition, 18 | "control" means (i) the power, direct or indirect, to cause the 19 | direction or management of such entity, whether by contract or 20 | otherwise, or (ii) ownership of fifty percent (50%) or more of the 21 | outstanding shares, or (iii) beneficial ownership of such entity. 22 | 23 | "You" (or "Your") shall mean an individual or Legal Entity 24 | exercising permissions granted by this License. 25 | 26 | "Source" form shall mean the preferred form for making modifications, 27 | including but not limited to software source code, documentation 28 | source, and configuration files. 29 | 30 | "Object" form shall mean any form resulting from mechanical 31 | transformation or translation of a Source form, including but 32 | not limited to compiled object code, generated documentation, 33 | and conversions to other media types. 34 | 35 | "Work" shall mean the work of authorship, whether in Source or 36 | Object form, made available under the License, as indicated by a 37 | copyright notice that is included in or attached to the work 38 | (an example is provided in the Appendix below). 39 | 40 | "Derivative Works" shall mean any work, whether in Source or Object 41 | form, that is based on (or derived from) the Work and for which the 42 | editorial revisions, annotations, elaborations, or other modifications 43 | represent, as a whole, an original work of authorship. For the purposes 44 | of this License, Derivative Works shall not include works that remain 45 | separable from, or merely link (or bind by name) to the interfaces of, 46 | the Work and Derivative Works thereof. 47 | 48 | "Contribution" shall mean any work of authorship, including 49 | the original version of the Work and any modifications or additions 50 | to that Work or Derivative Works thereof, that is intentionally 51 | submitted to Licensor for inclusion in the Work by the copyright owner 52 | or by an individual or Legal Entity authorized to submit on behalf of 53 | the copyright owner. For the purposes of this definition, "submitted" 54 | means any form of electronic, verbal, or written communication sent 55 | to the Licensor or its representatives, including but not limited to 56 | communication on electronic mailing lists, source code control systems, 57 | and issue tracking systems that are managed by, or on behalf of, the 58 | Licensor for the purpose of discussing and improving the Work, but 59 | excluding communication that is conspicuously marked or otherwise 60 | designated in writing by the copyright owner as "Not a Contribution." 61 | 62 | "Contributor" shall mean Licensor and any individual or Legal Entity 63 | on behalf of whom a Contribution has been received by Licensor and 64 | subsequently incorporated within the Work. 65 | 66 | 2. Grant of Copyright License. Subject to the terms and conditions of 67 | this License, each Contributor hereby grants to You a perpetual, 68 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 69 | copyright license to reproduce, prepare Derivative Works of, 70 | publicly display, publicly perform, sublicense, and distribute the 71 | Work and such Derivative Works in Source or Object form. 72 | 73 | 3. Grant of Patent License. Subject to the terms and conditions of 74 | this License, each Contributor hereby grants to You a perpetual, 75 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 76 | (except as stated in this section) patent license to make, have made, 77 | use, offer to sell, sell, import, and otherwise transfer the Work, 78 | where such license applies only to those patent claims licensable 79 | by such Contributor that are necessarily infringed by their 80 | Contribution(s) alone or by combination of their Contribution(s) 81 | with the Work to which such Contribution(s) was submitted. If You 82 | institute patent litigation against any entity (including a 83 | cross-claim or counterclaim in a lawsuit) alleging that the Work 84 | or a Contribution incorporated within the Work constitutes direct 85 | or contributory patent infringement, then any patent licenses 86 | granted to You under this License for that Work shall terminate 87 | as of the date such litigation is filed. 88 | 89 | 4. Redistribution. You may reproduce and distribute copies of the 90 | Work or Derivative Works thereof in any medium, with or without 91 | modifications, and in Source or Object form, provided that You 92 | meet the following conditions: 93 | 94 | (a) You must give any other recipients of the Work or 95 | Derivative Works a copy of this License; and 96 | 97 | (b) You must cause any modified files to carry prominent notices 98 | stating that You changed the files; and 99 | 100 | (c) You must retain, in the Source form of any Derivative Works 101 | that You distribute, all copyright, patent, trademark, and 102 | attribution notices from the Source form of the Work, 103 | excluding those notices that do not pertain to any part of 104 | the Derivative Works; and 105 | 106 | (d) If the Work includes a "NOTICE" text file as part of its 107 | distribution, then any Derivative Works that You distribute must 108 | include a readable copy of the attribution notices contained 109 | within such NOTICE file, excluding those notices that do not 110 | pertain to any part of the Derivative Works, in at least one 111 | of the following places: within a NOTICE text file distributed 112 | as part of the Derivative Works; within the Source form or 113 | documentation, if provided along with the Derivative Works; or, 114 | within a display generated by the Derivative Works, if and 115 | wherever such third-party notices normally appear. The contents 116 | of the NOTICE file are for informational purposes only and 117 | do not modify the License. You may add Your own attribution 118 | notices within Derivative Works that You distribute, alongside 119 | or as an addendum to the NOTICE text from the Work, provided 120 | that such additional attribution notices cannot be construed 121 | as modifying the License. 122 | 123 | You may add Your own copyright statement to Your modifications and 124 | may provide additional or different license terms and conditions 125 | for use, reproduction, or distribution of Your modifications, or 126 | for any such Derivative Works as a whole, provided Your use, 127 | reproduction, and distribution of the Work otherwise complies with 128 | the conditions stated in this License. 129 | 130 | 5. Submission of Contributions. Unless You explicitly state otherwise, 131 | any Contribution intentionally submitted for inclusion in the Work 132 | by You to the Licensor shall be under the terms and conditions of 133 | this License, without any additional terms or conditions. 134 | Notwithstanding the above, nothing herein shall supersede or modify 135 | the terms of any separate license agreement you may have executed 136 | with Licensor regarding such Contributions. 137 | 138 | 6. Trademarks. This License does not grant permission to use the trade 139 | names, trademarks, service marks, or product names of the Licensor, 140 | except as required for reasonable and customary use in describing the 141 | origin of the Work and reproducing the content of the NOTICE file. 142 | 143 | 7. Disclaimer of Warranty. Unless required by applicable law or 144 | agreed to in writing, Licensor provides the Work (and each 145 | Contributor provides its Contributions) on an "AS IS" BASIS, 146 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 147 | implied, including, without limitation, any warranties or conditions 148 | of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A 149 | PARTICULAR PURPOSE. You are solely responsible for determining the 150 | appropriateness of using or redistributing the Work and assume any 151 | risks associated with Your exercise of permissions under this License. 152 | 153 | 8. Limitation of Liability. In no event and under no legal theory, 154 | whether in tort (including negligence), contract, or otherwise, 155 | unless required by applicable law (such as deliberate and grossly 156 | negligent acts) or agreed to in writing, shall any Contributor be 157 | liable to You for damages, including any direct, indirect, special, 158 | incidental, or consequential damages of any character arising as a 159 | result of this License or out of the use or inability to use the 160 | Work (including but not limited to damages for loss of goodwill, 161 | work stoppage, computer failure or malfunction, or any and all 162 | other commercial damages or losses), even if such Contributor 163 | has been advised of the possibility of such damages. 164 | 165 | 9. Accepting Warranty or Additional Liability. While redistributing 166 | the Work or Derivative Works thereof, You may choose to offer, 167 | and charge a fee for, acceptance of support, warranty, indemnity, 168 | or other liability obligations and/or rights consistent with this 169 | License. However, in accepting such obligations, You may act only 170 | on Your own behalf and on Your sole responsibility, not on behalf 171 | of any other Contributor, and only if You agree to indemnify, 172 | defend, and hold each Contributor harmless for any liability 173 | incurred by, or claims asserted against, such Contributor by reason 174 | of your accepting any such warranty or additional liability. 175 | 176 | END OF TERMS AND CONDITIONS 177 | 178 | APPENDIX: How to apply the Apache License to your work. 179 | 180 | To apply the Apache License to your work, attach the following 181 | boilerplate notice, with the fields enclosed by brackets "[]" 182 | replaced with your own identifying information. (Don't include 183 | the brackets!) The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /Memory/Crutial_Ballistix_Sport/BLS4G4D240FSB.csv: -------------------------------------------------------------------------------- 1 | Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length 2 | UDIMMs,BLS4G4D240FSB-2133,1,1,0,1,17,15,10,2,2,1,1,1,1,2133,4GB,4Gb,64,8,8,1.2V,64,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,14,11,8 3 | UDIMMs,BLS4G4D240FSB-2400,1,1,0,1,17,15,10,2,2,1,1,1,1,2400,4GB,4Gb,64,8,8,1.2V,64,833,1600,5000 ps,13000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,16,12,8 4 | UDIMMs,BLS4G4D240FSB-2666,1,1,0,1,17,15,10,2,2,1,1,1,1,2666,4GB,4Gb,64,8,8,1.2V,64,750,1600,5000 ps,12000 ps,0,8 tck,32000 ps,12500 ps,7800000 ps,260000 ps,0,12500 ps,3000 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,18,14,8 5 | -------------------------------------------------------------------------------- /Memory/Crutial_Ballistix_Sport/BLS4G4S26BFSD.csv: -------------------------------------------------------------------------------- 1 | Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length 2 | SODIMMs,BLS4G4S26BFSD-2133,1,1,0,1,17,15,10,2,2,1,1,1,1,2133,4GB,512Mb,64,8,8,1.2V,64,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,14,11,8 3 | SODIMMs,BLS4G4S26BFSD-2400,1,1,0,1,17,15,10,2,2,1,1,1,1,2400,4GB,512Mb,64,8,8,1.2V,64,833,1600,5000 ps,13000 ps,0,8 tck,32000 ps,12500 ps,7800000 ps,260000 ps,0,12500 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,16,12,8 4 | SODIMMs,BLS4G4S26BFSD-2666,1,1,0,1,17,15,10,2,2,1,1,1,1,2666,4GB,512Mb,64,8,8,1.2V,64,750,1600,5000 ps,12000 ps,0,8 tck,32000 ps,12500 ps,7800000 ps,260000 ps,0,12500 ps,3000 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,18,14,8 5 | -------------------------------------------------------------------------------- /Memory/Crutial_Ballistix_Sport/BLS8G4D240FSB.csv: -------------------------------------------------------------------------------- 1 | Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length 2 | UDIMMs,BLS8G4D240FSB-2133,2,1,1,1,17,15,10,2,2,2,2,2,2,2400,8GB,4Gb,64,8,8,1.2V,64,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,14060 ps,7800000 ps,260000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,14,11,8 3 | UDIMMs,BLS8G4D240FSB-2400,2,1,1,1,17,15,10,2,2,2,2,2,2,2400,8GB,4Gb,64,8,8,1.2V,64,833,1600,5000 ps,13000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,16,12,8 4 | UDIMMs,BLS8G4D240FSB-2666,2,1,1,1,17,15,10,2,2,2,2,2,2,2666,8GB,4Gb,64,8,8,1.2V,64,750,1600,5000 ps,12000 ps,0,8 tck,32000 ps,12500 ps,7800000 ps,260000 ps,0,12500 ps,3000 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,18,14,8 5 | -------------------------------------------------------------------------------- /Memory/Crutial_Ballistix_Sport/specs/4gb_auto_ddr4_sdram.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Memory/Crutial_Ballistix_Sport/specs/4gb_auto_ddr4_sdram.pdf -------------------------------------------------------------------------------- /Memory/Micron_MTA8ATF1G64HZ/MTA8ATF1G64HZ.csv: -------------------------------------------------------------------------------- 1 | Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length 2 | SODIMMs,MTA8ATF1G64HZ-2G1,1,1,0,1,17,16,10,2,2,1,1,1,1,2133,8GB,8Gb,64,8,8,1.2V,64,938,1600,5000 ps,15000 ps,0,8 tck,33000 ps,13130 ps,7800000 ps,260000 ps,0,13130 ps,3700 ps,5300 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,15,11,8 3 | SODIMMs,MTA8ATF1G64HZ-2G3,1,1,0,1,17,16,10,2,2,1,1,1,1,2400,8GB,8Gb,64,8,8,1.2V,64,833,1600,5000 ps,13000 ps,0,8 tck,32000 ps,12500 ps,7800000 ps,260000 ps,0,12500 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,17,12,8 4 | SODIMMs,MTA8ATF1G64HZ-2G6,1,1,0,1,17,16,10,2,2,1,1,1,1,2666,8GB,8Gb,64,8,8,1.2V,64,750,1600,5000 ps,12000 ps,0,8 tck,32000 ps,12500 ps,7800000 ps,260000 ps,0,12500 ps,3000 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,19,14,8 5 | -------------------------------------------------------------------------------- /Memory/Micron_MTA8ATF1G64HZ/specs/8Gb_DDR4_SDRAM.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Memory/Micron_MTA8ATF1G64HZ/specs/8Gb_DDR4_SDRAM.pdf -------------------------------------------------------------------------------- /Memory/Micron_MTA8ATF1G64HZ/specs/atf8c1gx64hz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/d953i/Custom_Part_Data_Files/f6d71115a5b02911670f7fde021a7758bf70a7fc/Memory/Micron_MTA8ATF1G64HZ/specs/atf8c1gx64hz.pdf -------------------------------------------------------------------------------- /Patches/xilinx_mig/time_periods.patch: -------------------------------------------------------------------------------- 1 | --- /tools/Xilinx/Vivado/2019.2/data/ip/xilinx/mem_v1_4/csv/time_periods.csv_orig 2019-11-14 11:02:44.898559945 -0800 2 | +++ /tools/Xilinx/Vivado/2019.2/data/ip/xilinx/mem_v1_4/csv/time_periods.csv 2019-11-14 11:04:42.980860606 -0800 3 | @@ -467,7 +467,7 @@ 4 | DDR4,DIMM,-2,E,Vnom,UltraScale,4,2,2,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,1333.33,1500,1600,,,, 5 | DDR4,DIMM,-2,E,Vnom,UltraScale,4,2,2,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,1333.33,1500,1600,,,, 6 | DDR4,DIMM,-2,E,Vnom,UltraScale,4,2,2,No,On,HP,Group 3,POD12,4:1,,,Full,Internal,No,,Too Slow,NA,1600,,,, 7 | -DDR4,DIMM,-2,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2400.00,833,1600,,,, 8 | +DDR4,DIMM,-2,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2666.67,750,1600,,,, 9 | DDR4,DIMM,-2,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 10 | DDR4,DIMM,-2,E,Vnom,UltraScale+,1,1,1,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 11 | DDR4,DIMM,-2,E,Vnom,UltraScale+,1,1,1,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 12 | @@ -517,7 +517,7 @@ 13 | DDR4,DIMM,-2,I,Vnom,UltraScale,4,2,2,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,1333.33,1500,1600,,,, 14 | DDR4,DIMM,-2,I,Vnom,UltraScale,4,2,2,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,1333.33,1500,1600,,,, 15 | DDR4,DIMM,-2,I,Vnom,UltraScale,4,2,2,No,On,HP,Group 3,POD12,4:1,,,Full,Internal,No,,Too Slow,NA,1600,,,, 16 | -DDR4,DIMM,-2,I,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2400.00,833,1600,,,, 17 | +DDR4,DIMM,-2,I,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2666.67,750,1600,,,, 18 | DDR4,DIMM,-2,I,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 19 | DDR4,DIMM,-2,I,Vnom,UltraScale+,1,1,1,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 20 | DDR4,DIMM,-2,I,Vnom,UltraScale+,1,1,1,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 21 | @@ -537,7 +537,7 @@ 22 | DDR4,DIMM,-2,I,Vnom,UltraScale+,4,2,2,No,Off,HP,Group 2,POD12,4:1,,,Full,Internal,No,,1600.00,1250,1600,,,, 23 | DDR4,DIMM,-2,I,Vnom,UltraScale+,4,2,2,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,1600.00,1250,1600,,,, 24 | DDR4,DIMM,-2,I,Vnom,UltraScale+,4,2,2,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,1600.00,1250,1600,,,, 25 | -DDR4,DIMM,-2L,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2400.00,833,1600,,,, 26 | +DDR4,DIMM,-2L,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2666.67,750,1600,,,, 27 | DDR4,DIMM,-2L,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 28 | DDR4,DIMM,-2L,E,Vnom,UltraScale+,1,1,1,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 29 | DDR4,DIMM,-2L,E,Vnom,UltraScale+,1,1,1,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 30 | @@ -627,7 +627,7 @@ 31 | DDR4,DIMM,-3,E,Vnom,UltraScale,4,2,2,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,1333.33,1500,1600,,,, 32 | DDR4,DIMM,-3,E,Vnom,UltraScale,4,2,2,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,1333.33,1500,1600,,,, 33 | DDR4,DIMM,-3,E,Vnom,UltraScale,4,2,2,No,On,HP,Group 3,POD12,4:1,,,Full,Internal,No,,Too Slow,NA,1600,,,, 34 | -DDR4,DIMM,-3,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2400.00,833,1600,,,, 35 | +DDR4,DIMM,-3,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2666.67,750,1600,,,, 36 | DDR4,DIMM,-3,E,Vnom,UltraScale+,1,1,1,No,Off,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 37 | DDR4,DIMM,-3,E,Vnom,UltraScale+,1,1,1,No,On,HP,Group 1,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 38 | DDR4,DIMM,-3,E,Vnom,UltraScale+,1,1,1,No,On,HP,Group 2,POD12,4:1,,,Full,Internal,No,,2133.33,938,1600,,,, 39 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Xilinx Vivado Custom Part Data Files (in CVS format) 2 | 3 | Collection of memory configuration files for Xilinx Vivado along with example design for a few boards. 4 | 5 | # Xilinx Vivado Custom Part Data Files (in CVS format) 6 | Tested with Vivado version 2019.2 & 2022.1 7 | 8 | # DDR4 Memory 9 | - UDIMM Crutial Ballistix Sport BLS4G4D240FSB (CT40A512M8RH-075E component) - 4GB 10 | - UDIMM Crutial Ballistix Sport BLS8G4D240FSB (CT40A512M8RH-075E component) - 8GB 11 | - UDIMM Crutial Ballistix Sport BLS16G4D26BFSB (CT40A1G8WE-75H:D component) - 16GB 12 | - SODIMM Crutial Ballistix Sport BLS4G4S26BFSD (CT40A512M8WE-75H component) - 4GB 13 | - SODIMM Micron MTA8ATF1G64HZ (MT40A1G8WE-075E component) - 8GB 14 | 15 | # Example design for Ballistix 4GB UDIMM's 16 | - Bittware CVP13 17 | - Xilinx BCU1525 18 | - Xilinx VCU1525 19 | - Xilinx ZCU104 20 | 21 | # BCU1525 quad-channel example usage 22 | 23 | Clone repo, go to your project directory and source TCL script from Vivado. For example:
24 | ```cd ~```
25 | ```git clone https://github.com/D953i/Custom_Part_Data_Files.git``` 26 | 27 | In Vivado TCL console:
28 | ```source ../_github/Custom_Part_Data_Files/Boards/Xilinx_BCU1525/create_project.tcl``` 29 | 30 | # BCU1525 create project by using tcl script 31 | ![Vivado_Source_Script](Images/BCU1525_SourceScript.PNG?raw=true "Vivado Source Script Screenshot") 32 | 33 | # BCU1525 quad-channel ddr4 example block diagram 34 | ![Vivado_Block_Diagram](Images/BCU1525_Quad_DDR4_BlockDiagram.PNG?raw=true "Vivado Block Diagram") 35 | 36 | # BCU1525 quad-channel dd4 example memory map 37 | ![Vivado_Memory_Map](Images/BCU1525_Quad_DDR4_MemoryMap.PNG?raw=true "Vivado Memory Map") 38 | 39 | # BCU1525 quad-channel ddr4 example calibration 40 | ![Vivado_Calibration](Images/BCU1525_Quad_DDR4_Calibration.PNG?raw=true "Vivado Memory Calibration") 41 | 42 | # Useful links 43 | - Micron FBGA and Component Marking Decoder
44 | - UltraScale/UltraScale+ DDR4 IP - Interface Calibration and Hardware Debug Guide
45 | - UltraScale/UltraScale+ DDR4 IP - User addition of pblock might cause skew violations between RIU_CLK and PLL_CLK pins of BITSLICE_CONTROL
46 | -------------------------------------------------------------------------------- /Scripts/jtag2axi.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # 3 | # Copyright (c) 2001-2023 divashin@gmail.com 4 | # 5 | # This program is free software; you can redistribute it and/or modify 6 | # it under the terms of the GNU General Public License as published by 7 | # the Free Software Foundation; either version 2 of the License, or 8 | # (at your option) any later version. 9 | # 10 | # This program is distributed in the hope that it will be useful, 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | # GNU General Public License for more details. 14 | # 15 | # You should have received a copy of the GNU General Public License along 16 | # with this program; if not, write to the Free Software Foundation, Inc., 17 | # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 | # 19 | ################################################################################ 20 | 21 | proc write4B {addr value} { 22 | create_hw_axi_txn -force w0 [get_hw_axis hw_axi_1] -address [format 0x%016lx $addr] -data [format 0x%08lx $value] -type write -len 4 23 | run_hw_axi -quiet w0 24 | } 25 | 26 | proc write256B {} { 27 | set base_addr 0x400000000 28 | for {set i 0} {$i < 64} {incr i} { 29 | set addr [expr $base_addr + 4 * $i] 30 | set value 55 31 | set value [expr $value + [expr $i << 0]] 32 | set value [expr $value + [expr $i << 8]] 33 | set value [expr $value + [expr $i << 16]] 34 | set value [expr $value + [expr $i << 24]] 35 | puts "write to addr: [format 0x%010lx $addr] value: [format 0x%08lx $value]" 36 | write4B $addr $value 37 | } 38 | } 39 | 40 | proc read4B {addr} { 41 | create_hw_axi_txn -force r0 [get_hw_axis hw_axi_1] -address [format 0x%010lx $addr] -type read 42 | run_hw_axi -quiet r0 43 | set res [get_property DATA [get_hw_axi_txn r0]] 44 | puts "read from addr: [format 0x%010lx $addr] value: [format 0x$res]" 45 | } 46 | 47 | proc read256B {} { 48 | set base_addr 0x400000000 49 | set value 0 50 | for {set i 0} {$i < 64} {incr i} { 51 | set addr [expr $base_addr + 4 * $i] 52 | read4B $addr 53 | } 54 | } 55 | --------------------------------------------------------------------------------