├── .gitmodules ├── CMakeLists.txt ├── LICENSE ├── README.md ├── cmake ├── FindTCL.cmake ├── GetGitRevisionDescription.cmake └── GetGitRevisionDescription.cmake.in ├── include └── openroad │ ├── Error.hh │ ├── InitOpenRoad.hh │ ├── OpenRoad.hh │ ├── Version.hh │ └── Version.hh.cmake ├── src ├── ArtNetGen │ ├── CMakeLists.txt │ ├── include │ │ └── artnetgen │ │ │ ├── MakeArtNetGen.h │ │ │ └── artNetGen.h │ └── src │ │ ├── MakeArtNetGen.cpp │ │ ├── artNetGen.cpp │ │ ├── artNetGen.i │ │ ├── artNetGen.tcl │ │ ├── bin.cpp │ │ ├── bin.h │ │ ├── distMatching.cpp │ │ ├── distribution.cpp │ │ ├── logger.cpp │ │ ├── logger.h │ │ ├── netlist.cpp │ │ ├── netlist.h │ │ ├── node.cpp │ │ ├── node.h │ │ ├── techMapping.cpp │ │ └── writeSpec.cpp ├── CMakeLists.txt ├── Error.cc ├── Exception.i ├── Main.cc ├── OpenRoad.cc ├── OpenRoad.i ├── OpenRoad.tcl └── dbSta │ ├── .gitignore │ ├── CMakeLists.txt │ ├── include │ └── db_sta │ │ ├── MakeDbSta.hh │ │ ├── dbNetwork.hh │ │ ├── dbReadVerilog.hh │ │ └── dbSta.hh │ ├── src │ ├── CMakeLists.txt │ ├── dbNetwork.cc │ ├── dbReadVerilog.cc │ ├── dbReadVerilog.tcl │ ├── dbSdcNetwork.cc │ ├── dbSdcNetwork.hh │ ├── dbSta.cc │ └── dbSta.i │ └── test │ ├── Nangate45 │ ├── bidir1.lef │ ├── bidir1.lib │ ├── block_sta1.ok │ ├── block_sta1.tcl │ ├── bus1.def │ ├── bus1.lef │ ├── bus1.lib │ ├── bus1.v │ ├── example1.def │ ├── example1.dspef │ ├── example1.lef │ ├── example1.sdf │ ├── example1.v │ ├── example1_fast.lib │ ├── example1_slow.lib │ ├── example1_typ.lib │ ├── find_clks1.def │ ├── find_clks1.ok │ ├── find_clks1.tcl │ ├── helpers.tcl │ ├── hier1.def │ ├── hier1.v │ ├── liberty1.lef │ ├── liberty1.lib │ ├── network_edit1.defok │ ├── network_edit1.ok │ ├── network_edit1.tcl │ ├── pad.lef │ ├── pad.lib │ ├── read_verilog1.defok │ ├── read_verilog1.ok │ ├── read_verilog1.tcl │ ├── read_verilog2.defok │ ├── read_verilog2.ok │ ├── read_verilog2.tcl │ ├── read_verilog3.ok │ ├── read_verilog3.tcl │ ├── read_verilog4.defok │ ├── read_verilog4.ok │ ├── read_verilog4.tcl │ ├── read_verilog4.v │ ├── read_verilog5.defok │ ├── read_verilog5.ok │ ├── read_verilog5.tcl │ ├── read_verilog5.v │ ├── read_verilog6.lef │ ├── read_verilog6.ok │ ├── read_verilog6.tcl │ ├── read_verilog6.v │ ├── reg.txt │ ├── reg1.def │ ├── reg1.v │ ├── reg3.def │ ├── reg4.def │ ├── reg6.def │ ├── regression │ ├── regression_tests.tcl │ ├── report_json1.ok │ ├── report_json1.tcl │ ├── save_defok │ ├── save_ok │ ├── sdc_get1.ok │ ├── sdc_get1.tcl │ ├── sdc_names1.ok │ ├── sdc_names1.tcl │ ├── sdc_names2.def │ ├── sdc_names2.ok │ ├── sdc_names2.tcl │ ├── sta1.ok │ ├── sta1.tcl │ ├── sta2.ok │ ├── sta2.tcl │ ├── sta3.ok │ ├── sta3.tcl │ ├── sta4.ok │ ├── sta4.tcl │ ├── sta5.ok │ ├── sta5.tcl │ ├── write_verilog1.ok │ ├── write_verilog1.tcl │ ├── write_verilog2.ok │ ├── write_verilog2.tcl │ ├── write_verilog3.ok │ ├── write_verilog3.tcl │ ├── write_verilog4.def │ ├── write_verilog4.ok │ ├── write_verilog4.tcl │ ├── write_verilog5.def │ ├── write_verilog5.ok │ └── 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