├── always ├── apiseq ├── assert ├── case ├── class ├── clocking ├── covergroup ├── do ├── enum ├── for ├── fork_any ├── fork_join ├── fork_none ├── func ├── if ├── interface ├── module ├── repeat ├── struct ├── task ├── test ├── union ├── vfunc ├── virtseq ├── vtask └── while /always: -------------------------------------------------------------------------------- 1 | # name: always @() 2 | # key: always 3 | # group: verilog 4 | # -- 5 | always @(posedge ${1:CLOCK} or negedge ${2:RESETn}) begin 6 | if (~$2) begin 7 | $0 8 | end else begin 9 | 10 | end 11 | end -------------------------------------------------------------------------------- /apiseq: -------------------------------------------------------------------------------- 1 | # name: TBNG API Seqence 2 | # key: tbng 3 | # group: tbng 4 | # -- 5 | /*! \class $1_$2_seq_c 6 | * \brief 7 | * \ingroup $1_sequence 8 | */ 9 | class $1_${2:Seq}_seq_c extends ${1:Agent}_seq_base_c; 10 | 11 | /*! Register class with the factor */ 12 | `uvm_object_utils($1_$2_seq_c) 13 | 14 | /*! Constructs a new $1_$2_seq_c instance. 15 | * 16 | * \param name sequence name 17 | */ 18 | function new(string name = "$1_$2_write_seq_c"); 19 | super.new(name); 20 | endfunction : new 21 | 22 | /*! Body description 23 | */ 24 | task body(); 25 | req = $1_item_c::type_id::create("req"); 26 | 27 | start_item(req); 28 | $0 29 | finish_item(req); 30 | get_response(rsp); 31 | endtask : body 32 | 33 | endclass : $1_$2_seq_c 34 | -------------------------------------------------------------------------------- /assert: -------------------------------------------------------------------------------- 1 | # name: assert 2 | # key: assert 3 | # group: verilog 4 | # -- 5 | property ${1:PropertyName}; 6 | @(posedge ${2:CLK}) $0/* condition |=> value*/ ; 7 | endproperty 8 | 9 | assert_$1: assert property ($1); 10 | -------------------------------------------------------------------------------- /case: -------------------------------------------------------------------------------- 1 | # name: case 2 | # key: case 3 | # group: verilog 4 | # -- 5 | case (${1:Expression}) 6 | ${2:Condition}: 7 | begin 8 | $0 9 | end 10 | default: 11 | begin 12 | end 13 | endcase -------------------------------------------------------------------------------- /class: -------------------------------------------------------------------------------- 1 | # name: class 2 | # key: class 3 | # group: verilog 4 | # -- 5 | class ${1:Name} extends $2; 6 | 7 | function new; 8 | $0 9 | endfunction : new 10 | 11 | endclass : $1 12 | -------------------------------------------------------------------------------- /clocking: -------------------------------------------------------------------------------- 1 | # name: clocking 2 | # key: clocking 3 | # group: verilog 4 | # -- 5 | clocking ${1:name_cb} @(posedge ${2:clock}); 6 | default input #${3:setup_time} output #${4:hold_time}; 7 | $0 8 | // output declarations 9 | // input declarations 10 | endclocking: $1 11 | 12 | -------------------------------------------------------------------------------- /covergroup: -------------------------------------------------------------------------------- 1 | # name: covergroup 2 | # key: covergroup 3 | # group: verilog 4 | # -- 5 | covergroup ${1:CoverGroup}; 6 | coverpoint name { 7 | $0 8 | }; 9 | endgroup 10 | -------------------------------------------------------------------------------- /do: -------------------------------------------------------------------------------- 1 | # name: do 2 | # key: do 3 | # group: verilog 4 | # -- 5 | do begin 6 | $0 7 | end while($1); 8 | 9 | -------------------------------------------------------------------------------- /enum: -------------------------------------------------------------------------------- 1 | # name: enum 2 | # key: enum 3 | # group: verilog 4 | # -- 5 | /*! Description */ 6 | typedef enum ${2:Type} { 7 | ${3:Value} = $0; //!< Value Description 8 | } ${1:Name}; 9 | 10 | -------------------------------------------------------------------------------- /for: -------------------------------------------------------------------------------- 1 | # name: for 2 | # key: for 3 | # group: verilog 4 | # -- 5 | for ($0; ; ) begin 6 | end 7 | -------------------------------------------------------------------------------- /fork_any: -------------------------------------------------------------------------------- 1 | # name: fork/join_any 2 | # key: fork 3 | # group: verilog 4 | # -- 5 | fork 6 | begin : ${1:label_1} 7 | $0 8 | end 9 | begin : ${2:label_2} 10 | end 11 | join_any 12 | -------------------------------------------------------------------------------- /fork_join: -------------------------------------------------------------------------------- 1 | # name: fork/join 2 | # key: fork 3 | # group: verilog 4 | # -- 5 | fork 6 | begin : ${1:label_1} 7 | $0 8 | end 9 | begin : ${2:label_2} 10 | end 11 | join 12 | -------------------------------------------------------------------------------- /fork_none: -------------------------------------------------------------------------------- 1 | # name: fork/join_none 2 | # key: fork 3 | # group: verilog 4 | # -- 5 | fork 6 | begin : ${1:label_1} 7 | $0 8 | end 9 | begin : ${2:label_2} 10 | end 11 | join_none 12 | #0; 13 | -------------------------------------------------------------------------------- /func: -------------------------------------------------------------------------------- 1 | # name: function 2 | # key: func 3 | # group: verilog 4 | # -- 5 | /*! Function Description 6 | * 7 | * \param 8 | * 9 | * \return 10 | */ 11 | function ${2:Type} ${1:Name}(); 12 | $0 13 | endfunction : $1 14 | -------------------------------------------------------------------------------- /if: -------------------------------------------------------------------------------- 1 | # name: if 2 | # key: if 3 | # group: verilog 4 | # -- 5 | if ($1) begin 6 | $0 7 | end else if () begin 8 | 9 | end else begin 10 | 11 | end 12 | -------------------------------------------------------------------------------- /interface: -------------------------------------------------------------------------------- 1 | # name: interface 2 | # key: interface 3 | # group: verilog 4 | # -- 5 | interface ${1:Name} (); 6 | $0 7 | endinterface : $1 8 | 9 | -------------------------------------------------------------------------------- /module: -------------------------------------------------------------------------------- 1 | # name: module 2 | # key: module 3 | # group: verilog 4 | # -- 5 | module ${1:module_name} (/*port details*/); 6 | $0 7 | endmodule: $1 8 | 9 | -------------------------------------------------------------------------------- /repeat: -------------------------------------------------------------------------------- 1 | # name: repeat 2 | # key: repeat 3 | # group: verilog 4 | # -- 5 | repeat (${1:Condition}) begin 6 | $0 7 | end 8 | -------------------------------------------------------------------------------- /struct: -------------------------------------------------------------------------------- 1 | # name: struct 2 | # key: struct 3 | # group: verilog 4 | # -- 5 | /*! Typedef Description */ 6 | typedef struct { 7 | $0; //!< Field Description 8 | } ${1:Name}; 9 | 10 | -------------------------------------------------------------------------------- /task: -------------------------------------------------------------------------------- 1 | # name: task 2 | # key: task 3 | # group: verilog 4 | # -- 5 | /*! Description */ 6 | task ${1:Name}(); 7 | $0 8 | endtask : $1 9 | -------------------------------------------------------------------------------- /test: -------------------------------------------------------------------------------- 1 | # name: TBNG Test 2 | # key: tbng 3 | # group: tbng 4 | # -- 5 | /*! \class ${1:TestName} 6 | * \brief Provide a description of the test here 7 | * 8 | * Provide a more detailed description here 9 | */ 10 | class $1 extends test_base_c; 11 | 12 | const string report_id = "${1:$(upcase text)}_SEQ"; //!< Default id for messaging 13 | 14 | /*! Register class with the factory */ 15 | `uvm_component_utils($1); 16 | 17 | /*! Create a new instance 18 | * 19 | * \param name Name of the test 20 | * \param parent Parent component 21 | */ 22 | function new(string name = "$BASE$", uvm_component parent = null); 23 | super.new(name, parent); 24 | endfunction : new 25 | 26 | /*! Sets the config values 27 | */ 28 | function void set_config_values(); 29 | super.set_config_values(); 30 | 31 | // Set config variables here 32 | // m_ebi_cfg_h.enable_monitor_recording = 0; 33 | // m_ebi_cfg_h.has_scoreboard = 0; 34 | // m_uart_cfg_h.enable_monitor_recording = 0; 35 | 36 | // Set simulation timeout to the 37 | set_global_timeout(200us); 38 | 39 | endfunction : set_config_values 40 | 41 | /*! Run the test 42 | */ 43 | task main_phase(uvm_phase phase); 44 | 45 | phase.raise_objection(this); 46 | 47 | // Write test here 48 | $0 49 | 50 | phase.drop_objection(this); 51 | endtask : run 52 | 53 | endclass : $1 54 | 55 | /*!@}*/ 56 | -------------------------------------------------------------------------------- /union: -------------------------------------------------------------------------------- 1 | # name: union 2 | # key: union 3 | # group: verilog 4 | # -- 5 | typedef union { 6 | $0 7 | } ${1:name_u}; 8 | -------------------------------------------------------------------------------- /vfunc: -------------------------------------------------------------------------------- 1 | # name: virtual function 2 | # key: vfunc 3 | # group: verilog 4 | # -- 5 | /*! Function Description 6 | * 7 | * \param 8 | * 9 | * \return 10 | */ 11 | virtual function ${2:Type} ${1:Name}(); 12 | $0 13 | endfunction : $1 14 | 15 | -------------------------------------------------------------------------------- /virtseq: -------------------------------------------------------------------------------- 1 | # name: TBNG Virtual Sequence 2 | # key: tbng 3 | # group: tbng 4 | # -- 5 | /*! \class $1_seq_c 6 | * \brief 7 | */ 8 | class ${1:SequenceName}_seq_c extends virtual_sequence_c; 9 | 10 | /*! Register class with the factory */ 11 | `uvm_object_utils($1_seq_c); 12 | 13 | const string report_id = "${1:$(upcase text)}_SEQ"; //!< Default id for messaging 14 | 15 | /*! Constructs a new $1_seq_c instance. 16 | * 17 | * \param name sequence name 18 | */ 19 | function new(string name = "$1_seq_c"); 20 | super.new(name); 21 | endfunction : new 22 | 23 | task body(); 24 | $0 25 | endtask : body 26 | 27 | endclass : $1_seq_c 28 | 29 | -------------------------------------------------------------------------------- /vtask: -------------------------------------------------------------------------------- 1 | # name: virtual task 2 | # key: vtask 3 | # group: verilog 4 | # -- 5 | /*! Description */ 6 | virtual task ${1:Name}(); 7 | $0 8 | endtask : $1 9 | -------------------------------------------------------------------------------- /while: -------------------------------------------------------------------------------- 1 | # name: while 2 | # key: while 3 | # group: verilog 4 | # -- 5 | while (${1:condition}) begin 6 | $0 7 | end 8 | --------------------------------------------------------------------------------