├── .gitignore ├── .gitmodules ├── README.md ├── doc ├── pcb1.jpg └── render.png ├── licenses ├── CERN-OHL-W.txt └── MIT.txt ├── pcb ├── .gitignore ├── fp-lib-table ├── lib │ ├── RPi_Pico.lib │ └── RPi_Pico.pretty │ │ ├── CUI_SJ-3523-audio-jack.kicad_mod │ │ ├── DSUB-15-L77HDE15SD1CH4F.kicad_mod │ │ ├── Icon │ │ ├── MBR120_SOD-123.kicad_mod │ │ ├── RPi_Pico_SMD_TH.kicad_mod │ │ └── USB_Micro-B_Amphenol_10103594-0001LF_Horizontal_modified.kicad_mod ├── pico-hx.kicad_pcb ├── pico-hx.pro ├── pico-hx.sch └── sym-lib-table ├── rtl ├── data │ └── picohx.pcf └── demo │ ├── .gitignore │ ├── Makefile │ ├── debouncer.v │ ├── picohx_demo_top.v │ └── video │ ├── dvi-12bit.v │ ├── vga_core.v │ └── vga_timing.v ├── scripts └── picoprog.py └── software ├── .gitignore ├── CMakeLists.txt ├── default_bitstream.h ├── fpga_spi.c ├── fpga_spi.h ├── get_serial.c ├── get_serial.h ├── main.c ├── phx_gpio.h ├── pico_sdk_import.cmake ├── spi.pio ├── tusb_config.h ├── usb_common.h ├── usb_descriptors.c ├── usb_programmer.c ├── usb_programmer.h ├── usb_uart.c └── usb_uart.h /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | 3 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "kicad-lib"] 2 | path = pcb/kicad-lib 3 | url = https://github.com/dan-rodrigues/kicad-lib.git 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PicoHX 2 | 3 | This is an FPGA board that combines an iCE40 HX FPGA with the Raspberry Pi Pico. The Pico can program the FPGA over USB using a script included in this repo and then interact with it using GPIO. 4 | 5 | ## KiCad rendering 6 | 7 | ![PCB rendering](doc/render.png) 8 | 9 | ## DVI Demo 10 | 11 | Pictured is an included DVI demo. First, the RP2040 was programmed with the USB software which then exposes a USB programmer device to the host. Then, the FPGA configuration containing the DVI test pattern config was uploaded from the host to the RP2040, which then programmed the FPGA, which then displayed the test pattern on screen. [This DVI PMOD](https://1bitsquared.com/collections/fpga/products/pmod-digital-video-interface) was used. 12 | 13 | ![PCB DVI demo](doc/pcb1.jpg) 14 | 15 | ## Features 16 | 17 | * iCE40 HX FPGA (TQFP144, 1k pinout assumed) 18 | * 10 Pico GPIOs connected to FPGA 19 | * 2 are connected to `GBIN` inputs 20 | * 4x PMODs in a 2x double-PMOD arrangement 21 | * 8x user LEDs for FPGA 22 | * 1x CDONE LED 23 | * 2x users buttons for FPGA 24 | * 1x user button for Pico 25 | * `RUN` button for Pico 26 | * Headers for Pico SWD and hardware UART 27 | * Footprint for QSPI PSRAM or flash 28 | * Micro SD card slot 29 | 30 | ## Design 31 | 32 | ### Programming 33 | 34 | All iCE40 configuration pins are routed to the RP2040 GPIO so the details of how or when it is programmed are up to the software. The included software in this repo will make the Pico present itself is a USB device with these interfaces: 35 | 36 | * Vendor programmer interface: This is how the user can program the iCE40 at any time over USB, using the included [picoprog.py](scripts/picoprog.py) script. 37 | * CDC UART: This UART is separate to the hardware UART that is available on the dedicated pin header. By default, `stdout` is sent to the CDC UART for convenience. 38 | 39 | ### FPGA clock 40 | 41 | The pico exposes one pin that can directly output a clock from one of its PLLs with an optional divider. In the demo software, the USB PLL (48MHz) is divided by 4 to output a 12MHz clock for the FPGA. On the FPGA side, the `GBIN5` pin is used for clock input so that the `SB_PLL40_2F_PAD` can be used. 42 | 43 | ### Power 44 | 45 | There is only a 1.2v regulator on the board as the Pico provides a 3.3v output. The `2V5_VPP` input is tied to 3.3v as the NVCM isn't used in this project. 46 | 47 | ### PIO support 48 | 49 | The 10 GPIOs connected to the FPGA and 4 GPIOs connected to the SD card slot are in consecutive order, so PIO can be used. 50 | 51 | ## Demo 52 | 53 | A demo that displays several test patterns controlled by BTN-A and blinks the LEDs in succession can be found in [rtl/demo](rtl/demo). 54 | 55 | ``` 56 | cd rtl/demo 57 | make prog 58 | ``` 59 | 60 | ## Usage 61 | 62 | ### Building Pico software 63 | 64 | It's assumed that the [pico-sdk](https://github.com/raspberrypi/pico-sdk) is installed and the required environment variables are set. 65 | 66 | ``` 67 | cd software 68 | mkdir build 69 | cd build 70 | cmake .. 71 | make 72 | ``` 73 | 74 | The software can then be flashed using `picotool` for example. Default behaviour of the software is to immediately flash the iCE40 with an included bitstream that runs a counter with output to the 8 user LEDs. 75 | 76 | ### Programming iCE40 bitstream 77 | 78 | It's assumed that the OSS FPGA toolchain is installed which includes [yosys](https://github.com/YosysHQ/yosys) and [nextpnr-ice40](https://github.com/YosysHQ/nextpnr). 79 | 80 | After the Pico software is flashed, it's ready to program the iCE40 using a custom USB driver script. The script is written in Python3 and requires [pyusb](https://github.com/pyusb/pyusb). 81 | 82 | ``` 83 | pip3 install pyusb 84 | ``` 85 | 86 | It can then be programmed with similar usage to [iceprog](https://github.com/YosysHQ/icestorm/tree/master/iceprog). The programmer script is [picoprog.py](scripts/picoprog.py). 87 | 88 | ``` 89 | ./picoprog.py bitstream.bit 90 | ``` 91 | 92 | -------------------------------------------------------------------------------- /doc/pcb1.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dan-rodrigues/pico-hx/ae957f788e57d77343deb94147a5ee680b52fda6/doc/pcb1.jpg -------------------------------------------------------------------------------- /doc/render.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dan-rodrigues/pico-hx/ae957f788e57d77343deb94147a5ee680b52fda6/doc/render.png -------------------------------------------------------------------------------- /licenses/CERN-OHL-W.txt: -------------------------------------------------------------------------------- 1 | CERN Open Hardware Licence Version 2 - Weakly Reciprocal 2 | 3 | 4 | Preamble 5 | 6 | CERN has developed this licence to promote collaboration among 7 | hardware designers and to provide a legal tool which supports the 8 | freedom to use, study, modify, share and distribute hardware designs 9 | and products based on those designs. Version 2 of the CERN Open 10 | Hardware Licence comes in three variants: CERN-OHL-P (permissive); and 11 | two reciprocal licences: this licence, CERN-OHL-W (weakly reciprocal) 12 | and CERN-OHL-S (strongly reciprocal). 13 | 14 | The CERN-OHL-W is copyright CERN 2020. Anyone is welcome to use it, in 15 | unmodified form only. 16 | 17 | Use of this Licence does not imply any endorsement by CERN of any 18 | Licensor or their designs nor does it imply any involvement by CERN in 19 | their development. 20 | 21 | 22 | 1 Definitions 23 | 24 | 1.1 'Licence' means this CERN-OHL-W. 25 | 26 | 1.2 'Compatible Licence' means 27 | 28 | a) any earlier version of the CERN Open Hardware licence, or 29 | 30 | b) any version of the CERN-OHL-S or the CERN-OHL-W, or 31 | 32 | c) any licence which permits You to treat the Source to which 33 | it applies as licensed under CERN-OHL-S or CERN-OHL-W 34 | provided that on Conveyance of any such Source, or any 35 | associated Product You treat the Source in question as being 36 | licensed under CERN-OHL-S or CERN-OHL-W as appropriate. 37 | 38 | 1.3 'Source' means information such as design materials or digital 39 | code which can be applied to Make or test a Product or to 40 | prepare a Product for use, Conveyance or sale, regardless of its 41 | medium or how it is expressed. It may include Notices. 42 | 43 | 1.4 'Covered Source' means Source that is explicitly made available 44 | under this Licence. 45 | 46 | 1.5 'Product' means any device, component, work or physical object, 47 | whether in finished or intermediate form, arising from the use, 48 | application or processing of Covered Source. 49 | 50 | 1.6 'Make' means to create or configure something, whether by 51 | manufacture, assembly, compiling, loading or applying Covered 52 | Source or another Product or otherwise. 53 | 54 | 1.7 'Available Component' means any part, sub-assembly, library or 55 | code which: 56 | 57 | a) is licensed to You as Complete Source under a Compatible 58 | Licence; or 59 | 60 | b) is available, at the time a Product or the Source containing 61 | it is first Conveyed, to You and any other prospective 62 | licensees 63 | 64 | i) with sufficient rights and information (including any 65 | configuration and programming files and information 66 | about its characteristics and interfaces) to enable it 67 | either to be Made itself, or to be sourced and used to 68 | Make the Product; or 69 | ii) as part of the normal distribution of a tool used to 70 | design or Make the Product. 71 | 72 | 1.8 'External Material' means anything (including Source) which: 73 | 74 | a) is only combined with Covered Source in such a way that it 75 | interfaces with the Covered Source using a documented 76 | interface which is described in the Covered Source; and 77 | 78 | b) is not a derivative of or contains Covered Source, or, if it 79 | is, it is solely to the extent necessary to facilitate such 80 | interfacing. 81 | 82 | 1.9 'Complete Source' means the set of all Source necessary to Make 83 | a Product, in the preferred form for making modifications, 84 | including necessary installation and interfacing information 85 | both for the Product, and for any included Available Components. 86 | If the format is proprietary, it must also be made available in 87 | a format (if the proprietary tool can create it) which is 88 | viewable with a tool available to potential licensees and 89 | licensed under a licence approved by the Free Software 90 | Foundation or the Open Source Initiative. Complete Source need 91 | not include the Source of any Available Component, provided that 92 | You include in the Complete Source sufficient information to 93 | enable a recipient to Make or source and use the Available 94 | Component to Make the Product. 95 | 96 | 1.10 'Source Location' means a location where a Licensor has placed 97 | Covered Source, and which that Licensor reasonably believes will 98 | remain easily accessible for at least three years for anyone to 99 | obtain a digital copy. 100 | 101 | 1.11 'Notice' means copyright, acknowledgement and trademark notices, 102 | Source Location references, modification notices (subsection 103 | 3.3(b)) and all notices that refer to this Licence and to the 104 | disclaimer of warranties that are included in the Covered 105 | Source. 106 | 107 | 1.12 'Licensee' or 'You' means any person exercising rights under 108 | this Licence. 109 | 110 | 1.13 'Licensor' means a natural or legal person who creates or 111 | modifies Covered Source. A person may be a Licensee and a 112 | Licensor at the same time. 113 | 114 | 1.14 'Convey' means to communicate to the public or distribute. 115 | 116 | 117 | 2 Applicability 118 | 119 | 2.1 This Licence governs the use, copying, modification, Conveying 120 | of Covered Source and Products, and the Making of Products. By 121 | exercising any right granted under this Licence, You irrevocably 122 | accept these terms and conditions. 123 | 124 | 2.2 This Licence is granted by the Licensor directly to You, and 125 | shall apply worldwide and without limitation in time. 126 | 127 | 2.3 You shall not attempt to restrict by contract or otherwise the 128 | rights granted under this Licence to other Licensees. 129 | 130 | 2.4 This Licence is not intended to restrict fair use, fair dealing, 131 | or any other similar right. 132 | 133 | 134 | 3 Copying, Modifying and Conveying Covered Source 135 | 136 | 3.1 You may copy and Convey verbatim copies of Covered Source, in 137 | any medium, provided You retain all Notices. 138 | 139 | 3.2 You may modify Covered Source, other than Notices, provided that 140 | You irrevocably undertake to make that modified Covered Source 141 | available from a Source Location should You Convey a Product in 142 | circumstances where the recipient does not otherwise receive a 143 | copy of the modified Covered Source. In each case subsection 3.3 144 | shall apply. 145 | 146 | You may only delete Notices if they are no longer applicable to 147 | the corresponding Covered Source as modified by You and You may 148 | add additional Notices applicable to Your modifications. 149 | 150 | 3.3 You may Convey modified Covered Source (with the effect that You 151 | shall also become a Licensor) provided that You: 152 | 153 | a) retain Notices as required in subsection 3.2; 154 | 155 | b) add a Notice to the modified Covered Source stating that You 156 | have modified it, with the date and brief description of how 157 | You have modified it; 158 | 159 | c) add a Source Location Notice for the modified Covered Source 160 | if You Convey in circumstances where the recipient does not 161 | otherwise receive a copy of the modified Covered Source; and 162 | 163 | d) license the modified Covered Source under the terms and 164 | conditions of this Licence (or, as set out in subsection 165 | 8.3, a later version, if permitted by the licence of the 166 | original Covered Source). Such modified Covered Source must 167 | be licensed as a whole, but excluding Available Components 168 | contained in it or External Material to which it is 169 | interfaced, which remain licensed under their own applicable 170 | licences. 171 | 172 | 173 | 4 Making and Conveying Products 174 | 175 | 4.1 You may Make Products, and/or Convey them, provided that You 176 | either provide each recipient with a copy of the Complete Source 177 | or ensure that each recipient is notified of the Source Location 178 | of the Complete Source. That Complete Source includes Covered 179 | Source and You must accordingly satisfy Your obligations set out 180 | in subsection 3.3. If specified in a Notice, the Product must 181 | visibly and securely display the Source Location on it or its 182 | packaging or documentation in the manner specified in that 183 | Notice. 184 | 185 | 4.2 Where You Convey a Product which incorporates External Material, 186 | the Complete Source for that Product which You are required to 187 | provide under subsection 4.1 need not include any Source for the 188 | External Material. 189 | 190 | 4.3 You may license Products under terms of Your choice, provided 191 | that such terms do not restrict or attempt to restrict any 192 | recipients' rights under this Licence to the Covered Source. 193 | 194 | 195 | 5 Research and Development 196 | 197 | You may Convey Covered Source, modified Covered Source or Products to 198 | a legal entity carrying out development, testing or quality assurance 199 | work on Your behalf provided that the work is performed on terms which 200 | prevent the entity from both using the Source or Products for its own 201 | internal purposes and Conveying the Source or Products or any 202 | modifications to them to any person other than You. Any modifications 203 | made by the entity shall be deemed to be made by You pursuant to 204 | subsection 3.2. 205 | 206 | 207 | 6 DISCLAIMER AND LIABILITY 208 | 209 | 6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products 210 | are provided 'as is' and any express or implied warranties, 211 | including, but not limited to, implied warranties of 212 | merchantability, of satisfactory quality, non-infringement of 213 | third party rights, and fitness for a particular purpose or use 214 | are disclaimed in respect of any Source or Product to the 215 | maximum extent permitted by law. The Licensor makes no 216 | representation that any Source or Product does not or will not 217 | infringe any patent, copyright, trade secret or other 218 | proprietary right. The entire risk as to the use, quality, and 219 | performance of any Source or Product shall be with You and not 220 | the Licensor. This disclaimer of warranty is an essential part 221 | of this Licence and a condition for the grant of any rights 222 | granted under this Licence. 223 | 224 | 6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to 225 | the maximum extent permitted by law, have no liability for 226 | direct, indirect, special, incidental, consequential, exemplary, 227 | punitive or other damages of any character including, without 228 | limitation, procurement of substitute goods or services, loss of 229 | use, data or profits, or business interruption, however caused 230 | and on any theory of contract, warranty, tort (including 231 | negligence), product liability or otherwise, arising in any way 232 | in relation to the Covered Source, modified Covered Source 233 | and/or the Making or Conveyance of a Product, even if advised of 234 | the possibility of such damages, and You shall hold the 235 | Licensor(s) free and harmless from any liability, costs, 236 | damages, fees and expenses, including claims by third parties, 237 | in relation to such use. 238 | 239 | 240 | 7 Patents 241 | 242 | 7.1 Subject to the terms and conditions of this Licence, each 243 | Licensor hereby grants to You a perpetual, worldwide, 244 | non-exclusive, no-charge, royalty-free, irrevocable (except as 245 | stated in subsections 7.2 and 8.4) patent licence to Make, have 246 | Made, use, offer to sell, sell, import, and otherwise transfer 247 | the Covered Source and Products, where such licence applies only 248 | to those patent claims licensable by such Licensor that are 249 | necessarily infringed by exercising rights under the Covered 250 | Source as Conveyed by that Licensor. 251 | 252 | 7.2 If You institute patent litigation against any entity (including 253 | a cross-claim or counterclaim in a lawsuit) alleging that the 254 | Covered Source or a Product constitutes direct or contributory 255 | patent infringement, or You seek any declaration that a patent 256 | licensed to You under this Licence is invalid or unenforceable 257 | then any rights granted to You under this Licence shall 258 | terminate as of the date such process is initiated. 259 | 260 | 261 | 8 General 262 | 263 | 8.1 If any provisions of this Licence are or subsequently become 264 | invalid or unenforceable for any reason, the remaining 265 | provisions shall remain effective. 266 | 267 | 8.2 You shall not use any of the name (including acronyms and 268 | abbreviations), image, or logo by which the Licensor or CERN is 269 | known, except where needed to comply with section 3, or where 270 | the use is otherwise allowed by law. Any such permitted use 271 | shall be factual and shall not be made so as to suggest any kind 272 | of endorsement or implication of involvement by the Licensor or 273 | its personnel. 274 | 275 | 8.3 CERN may publish updated versions and variants of this Licence 276 | which it considers to be in the spirit of this version, but may 277 | differ in detail to address new problems or concerns. New 278 | versions will be published with a unique version number and a 279 | variant identifier specifying the variant. If the Licensor has 280 | specified that a given variant applies to the Covered Source 281 | without specifying a version, You may treat that Covered Source 282 | as being released under any version of the CERN-OHL with that 283 | variant. If no variant is specified, the Covered Source shall be 284 | treated as being released under CERN-OHL-S. The Licensor may 285 | also specify that the Covered Source is subject to a specific 286 | version of the CERN-OHL or any later version in which case You 287 | may apply this or any later version of CERN-OHL with the same 288 | variant identifier published by CERN. 289 | 290 | You may treat Covered Source licensed under CERN-OHL-W as 291 | licensed under CERN-OHL-S if and only if all Available 292 | Components referenced in the Covered Source comply with the 293 | corresponding definition of Available Component for CERN-OHL-S. 294 | 295 | 8.4 This Licence shall terminate with immediate effect if You fail 296 | to comply with any of its terms and conditions. 297 | 298 | 8.5 However, if You cease all breaches of this Licence, then Your 299 | Licence from any Licensor is reinstated unless such Licensor has 300 | terminated this Licence by giving You, while You remain in 301 | breach, a notice specifying the breach and requiring You to cure 302 | it within 30 days, and You have failed to come into compliance 303 | in all material respects by the end of the 30 day period. Should 304 | You repeat the breach after receipt of a cure notice and 305 | subsequent reinstatement, this Licence will terminate 306 | immediately and permanently. Section 6 shall continue to apply 307 | after any termination. 308 | 309 | 8.6 This Licence shall not be enforceable except by a Licensor 310 | acting as such, and third party beneficiary rights are 311 | specifically excluded. 312 | 313 | -------------------------------------------------------------------------------- /licenses/MIT.txt: -------------------------------------------------------------------------------- 1 | Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: 2 | 3 | The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. 4 | 5 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 6 | 7 | -------------------------------------------------------------------------------- /pcb/.gitignore: -------------------------------------------------------------------------------- 1 | # KiCad 2 | 3 | # Temporary files 4 | *.000 5 | *.bak 6 | *.bck 7 | *.kicad_pcb-bak 8 | *.kicad_sch-bak 9 | *.kicad_prl 10 | *.sch-bak 11 | *~ 12 | _autosave-* 13 | *.tmp 14 | *-save.pro 15 | *-save.kicad_pcb 16 | fp-info-cache 17 | *-cache.lib 18 | 19 | # Netlist files (exported from Eeschema) 20 | *.net 21 | 22 | # Autorouter files (exported from Pcbnew) 23 | *.dsn 24 | *.ses 25 | 26 | # Exported BOM files 27 | *.xml 28 | *.csv 29 | 30 | # Artifacts 31 | 32 | /job 33 | 34 | -------------------------------------------------------------------------------- /pcb/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name RPi_Pico)(type KiCad)(uri ${KIPRJMOD}/lib/RPi_Pico.pretty)(options "")(descr "")) 3 | (lib (name PMOD)(type KiCad)(uri ${KIPRJMOD}/kicad-lib/PMOD.pretty)(options "")(descr "")) 4 | ) 5 | -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | # Pico 5 | # 6 | DEF Pico U 0 40 Y Y 1 F N 7 | F0 "U" -550 1100 50 H V C CNN 8 | F1 "Pico" 0 750 50 H V C CNN 9 | F2 "RPi_Pico:RPi_Pico_SMD_TH" 0 0 50 V I C CNN 10 | F3 "" 0 0 50 H I C CNN 11 | DRAW 12 | T 0 0 850 50 0 0 0 "Raspberry Pi" Normal 0 C C 13 | S -600 1050 600 -1050 0 1 0 f 14 | X GPIO0 1 -700 950 100 R 50 50 1 1 B 15 | X GPIO7 10 -700 50 100 R 50 50 1 1 B 16 | X GPIO8 11 -700 -50 100 R 50 50 1 1 B 17 | X GPIO9 12 -700 -150 100 R 50 50 1 1 B 18 | X GND 13 -700 -250 100 R 50 50 1 1 W 19 | X GPIO10 14 -700 -350 100 R 50 50 1 1 B 20 | X GPIO11 15 -700 -450 100 R 50 50 1 1 B 21 | X GPIO12 16 -700 -550 100 R 50 50 1 1 B 22 | X GPIO13 17 -700 -650 100 R 50 50 1 1 B 23 | X GND 18 -700 -750 100 R 50 50 1 1 W 24 | X GPIO14 19 -700 -850 100 R 50 50 1 1 B 25 | X GPIO1 2 -700 850 100 R 50 50 1 1 B 26 | X GPIO15 20 -700 -950 100 R 50 50 1 1 B 27 | X GPIO16 21 700 -950 100 L 50 50 1 1 B 28 | X GPIO17 22 700 -850 100 L 50 50 1 1 B 29 | X GND 23 700 -750 100 L 50 50 1 1 W 30 | X GPIO18 24 700 -650 100 L 50 50 1 1 B 31 | X GPIO19 25 700 -550 100 L 50 50 1 1 B 32 | X GPIO20 26 700 -450 100 L 50 50 1 1 B 33 | X GPIO21 27 700 -350 100 L 50 50 1 1 B 34 | X GND 28 700 -250 100 L 50 50 1 1 W 35 | X GPIO22 29 700 -150 100 L 50 50 1 1 B 36 | X GND 3 -700 750 100 R 50 50 1 1 W 37 | X RUN 30 700 -50 100 L 50 50 1 1 I 38 | X GPIO26_ADC0 31 700 50 100 L 50 50 1 1 B 39 | X GPIO27_ADC1 32 700 150 100 L 50 50 1 1 B 40 | X AGND 33 700 250 100 L 50 50 1 1 W 41 | X GPIO28_ADC2 34 700 350 100 L 50 50 1 1 B 42 | X ADC_VREF 35 700 450 100 L 50 50 1 1 U 43 | X 3V3 36 700 550 100 L 50 50 1 1 w 44 | X 3V3_EN 37 700 650 100 L 50 50 1 1 I 45 | X GND 38 700 750 100 L 50 50 1 1 W 46 | X VSYS 39 700 850 100 L 50 50 1 1 U 47 | X GPIO2 4 -700 650 100 R 50 50 1 1 B 48 | X VBUS 40 700 950 100 L 50 50 1 1 w 49 | X SWCLK 41 -100 -1150 100 U 50 50 1 1 I 50 | X GND 42 0 -1150 100 U 50 50 1 1 W 51 | X SWDIO 43 100 -1150 100 U 50 50 1 1 B 52 | X GPIO3 5 -700 550 100 R 50 50 1 1 B 53 | X GPIO4 6 -700 450 100 R 50 50 1 1 B 54 | X GPIO5 7 -700 350 100 R 50 50 1 1 B 55 | X GND 8 -700 250 100 R 50 50 1 1 W 56 | X GPIO6 9 -700 150 100 R 50 50 1 1 B 57 | ENDDRAW 58 | ENDDEF 59 | # 60 | #End Library 61 | -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.pretty/CUI_SJ-3523-audio-jack.kicad_mod: -------------------------------------------------------------------------------- 1 | (module CUI_SJ-3523-audio-jack (layer F.Cu) (tedit 5F03199E) 2 | (descr "3.5 mm, Stereo, Right Angle, Surface Mount (SMT), Audio Jack Connector (https://www.cui.com/product/resource/sj-352x-smt-series.pdf)") 3 | (tags "3.5mm audio cui horizontal jack stereo") 4 | (attr smd) 5 | (fp_text reference J2 (at 0.1 9.7 -270) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value AudioJack3 (at 0 10.35 -180) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start -3.1 -2.3) (end -5.1 -2.3) (layer F.SilkS) (width 0.12)) 12 | (fp_line (start -3.1 -4.9) (end -5.1 -4.9) (layer F.SilkS) (width 0.12)) 13 | (fp_line (start -3.1 4.2) (end -3.1 -2.3) (layer F.SilkS) (width 0.12)) 14 | (fp_line (start -3.1 8.6) (end -3.1 7.4) (layer F.SilkS) (width 0.12)) 15 | (fp_line (start 3.1 8.6) (end -3.1 8.6) (layer F.SilkS) (width 0.12)) 16 | (fp_line (start 3.1 -0.3) (end 3.1 8.6) (layer F.SilkS) (width 0.12)) 17 | (fp_line (start 3.1 -6.1) (end 3.1 -2.9) (layer F.SilkS) (width 0.12)) 18 | (fp_line (start 2.6 -6.1) (end 3.1 -6.1) (layer F.SilkS) (width 0.12)) 19 | (fp_line (start -3.1 -4.9) (end -3.1 -6.1) (layer F.SilkS) (width 0.12)) 20 | (fp_text user %R (at 0 0 -180) (layer F.Fab) 21 | (effects (font (size 1 1) (thickness 0.15))) 22 | ) 23 | (fp_line (start -5.6 -6.1) (end 5.6 -6.1) (layer F.CrtYd) (width 0.05)) 24 | (fp_line (start -5.6 9) (end -5.6 -6.1) (layer F.CrtYd) (width 0.05)) 25 | (fp_line (start 5.6 9) (end -5.6 9) (layer F.CrtYd) (width 0.05)) 26 | (fp_line (start 5.6 -6.1) (end 5.6 9) (layer F.CrtYd) (width 0.05)) 27 | (fp_line (start 2.5 -6) (end 3 -6) (layer F.Fab) (width 0.1)) 28 | (fp_line (start 2.5 -8.5) (end 2.5 -6) (layer F.Fab) (width 0.1)) 29 | (fp_line (start -2.5 -8.5) (end 2.5 -8.5) (layer F.Fab) (width 0.1)) 30 | (fp_line (start -2.5 -6) (end -2.5 -8.5) (layer F.Fab) (width 0.1)) 31 | (fp_line (start -3 -6) (end -2.5 -6) (layer F.Fab) (width 0.1)) 32 | (fp_line (start -3 8.5) (end -3 -6) (layer F.Fab) (width 0.1)) 33 | (fp_line (start 3 8.5) (end -3 8.5) (layer F.Fab) (width 0.1)) 34 | (fp_line (start 3 -6) (end 3 8.5) (layer F.Fab) (width 0.1)) 35 | (pad "" np_thru_hole circle (at 0 4.5) (size 1.7 1.7) (drill 1.7) (layers *.Cu *.Mask)) 36 | (pad "" np_thru_hole circle (at 0 -2.5) (size 1.7 1.7) (drill 1.7) (layers *.Cu *.Mask)) 37 | (pad 2 smd rect (at -3.7 5.8) (size 2.8 2.8) (layers F.Cu F.Paste F.Mask)) 38 | (pad 1 smd rect (at -3.7 -3.6) (size 2.8 2.2) (layers F.Cu F.Paste F.Mask)) 39 | (pad 3 smd rect (at 3.7 -1.6) (size 2.8 2.2) (layers F.Cu F.Paste F.Mask)) 40 | (model CUI_DEVICES_SJ-3523-SMT-TR.step 41 | (offset (xyz 0 6 0)) 42 | (scale (xyz 1 1 1)) 43 | (rotate (xyz -90 0 90)) 44 | ) 45 | ) 46 | -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.pretty/DSUB-15-L77HDE15SD1CH4F.kicad_mod: -------------------------------------------------------------------------------- 1 | (module DSUB-15-L77HDE15SD1CH4F (layer F.Cu) (tedit 5EFF80D9) 2 | (descr "15-pin D-Sub connector, horizontal/angled (90 deg), THT-mount, female, pitch 2.29x1.98mm, pin-PCB-offset 3.0300000000000002mm, distance of mounting holes 25mm, distance of mounting holes to PCB edge 4.9399999999999995mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf") 3 | (tags "15-pin D-Sub connector horizontal angled 90deg THT female pitch 2.29x1.98mm pin-PCB-offset 3.0300000000000002mm mounting-holes-distance 25mm mounting-hole-offset 25mm") 4 | (fp_text reference REF** (at 10.2 17.43 180) (layer F.SilkS) 5 | (effects (font (size 1 1) (thickness 0.15))) 6 | ) 7 | (fp_text value DSUB-15-L77HDE15SD1CH4F (at -0.01 -7.45 180) (layer F.Fab) 8 | (effects (font (size 1 1) (thickness 0.15))) 9 | ) 10 | (fp_arc (start 12.5 11.43) (end 14.1 11.43) (angle 180) (layer F.Fab) (width 0.1)) 11 | (fp_arc (start -12.5 11.43) (end -10.9 11.43) (angle 180) (layer F.Fab) (width 0.1)) 12 | (fp_line (start 15.415 16.1) (end 15.415 0.45) (layer F.Fab) (width 0.1)) 13 | (fp_line (start 15.415 0.45) (end -15.435 0.45) (layer F.Fab) (width 0.1)) 14 | (fp_line (start -15.435 0.45) (end -15.435 16.1) (layer F.Fab) (width 0.1)) 15 | (fp_line (start -15.435 16.1) (end 15.415 16.1) (layer F.Fab) (width 0.1)) 16 | (fp_line (start 15.415 0.45) (end 15.415 0.05) (layer F.Fab) (width 0.1)) 17 | (fp_line (start 15.415 0.05) (end -15.435 0.05) (layer F.Fab) (width 0.1)) 18 | (fp_line (start -15.435 0.05) (end -15.435 0.45) (layer F.Fab) (width 0.1)) 19 | (fp_line (start -15.435 0.45) (end 15.415 0.45) (layer F.Fab) (width 0.1)) 20 | (fp_line (start 8.14 0.05) (end 8.14 -5.95) (layer F.Fab) (width 0.1)) 21 | (fp_line (start 8.14 -5.95) (end -8.16 -5.95) (layer F.Fab) (width 0.1)) 22 | (fp_line (start -8.16 -5.95) (end -8.16 0.05) (layer F.Fab) (width 0.1)) 23 | (fp_line (start -8.16 0.05) (end 8.14 0.05) (layer F.Fab) (width 0.1)) 24 | (fp_line (start 14.99 0.05) (end 14.99 -4.95) (layer F.Fab) (width 0.1)) 25 | (fp_line (start 14.99 -4.95) (end 9.99 -4.95) (layer F.Fab) (width 0.1)) 26 | (fp_line (start 9.99 -4.95) (end 9.99 0.05) (layer F.Fab) (width 0.1)) 27 | (fp_line (start 9.99 0.05) (end 14.99 0.05) (layer F.Fab) (width 0.1)) 28 | (fp_line (start -10.01 0.05) (end -10.01 -4.95) (layer F.Fab) (width 0.1)) 29 | (fp_line (start -10.01 -4.95) (end -15.01 -4.95) (layer F.Fab) (width 0.1)) 30 | (fp_line (start -15.01 -4.95) (end -15.01 0.05) (layer F.Fab) (width 0.1)) 31 | (fp_line (start -15.01 0.05) (end -10.01 0.05) (layer F.Fab) (width 0.1)) 32 | (fp_line (start 14.09 0.45) (end 14.09 11.43) (layer F.Fab) (width 0.1)) 33 | (fp_line (start 10.89 0.45) (end 10.89 11.43) (layer F.Fab) (width 0.1)) 34 | (fp_line (start -10.91 0.45) (end -10.91 11.43) (layer F.Fab) (width 0.1)) 35 | (fp_line (start -14.11 0.45) (end -14.11 11.43) (layer F.Fab) (width 0.1)) 36 | (fp_line (start -4.115 16.974338) (end -4.615 16.974338) (layer F.SilkS) (width 0.12)) 37 | (fp_line (start -4.615 16.974338) (end -4.365 16.541325) (layer F.SilkS) (width 0.12)) 38 | (fp_line (start -4.365 16.541325) (end -4.115 16.974338) (layer F.SilkS) (width 0.12)) 39 | (fp_line (start 16 16.63) (end 16 0) (layer F.CrtYd) (width 0.05)) 40 | (fp_line (start 16 0) (end -16 0) (layer F.CrtYd) (width 0.05)) 41 | (fp_line (start -16 0) (end -16 16.63) (layer F.CrtYd) (width 0.05)) 42 | (fp_line (start -16 16.63) (end 16 16.63) (layer F.CrtYd) (width 0.05)) 43 | (fp_text user %R (at -0.01 -2.95 180) (layer F.Fab) 44 | (effects (font (size 1 1) (thickness 0.15))) 45 | ) 46 | (fp_line (start 27.48 0) (end -27.48 0) (layer Dwgs.User) (width 0.12)) 47 | (fp_line (start 15.5 0.03) (end 15.5 16.23) (layer F.SilkS) (width 0.12)) 48 | (fp_line (start 15.5 16.23) (end -15.5 16.23) (layer F.SilkS) (width 0.12)) 49 | (fp_line (start -15.5 16.23) (end -15.5 0.03) (layer F.SilkS) (width 0.12)) 50 | (pad 0 thru_hole circle (at 12.495 11.43 180) (size 4 4) (drill 3.2) (layers *.Cu *.Mask)) 51 | (pad 0 thru_hole circle (at -12.495 11.43 180) (size 4 4) (drill 3.2) (layers *.Cu *.Mask)) 52 | (pad 8 thru_hole circle (at -0.895 11.43 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 53 | (pad 7 thru_hole circle (at -3.185 11.43 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 54 | (pad 6 thru_hole circle (at -5.475 11.43 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 55 | (pad 9 thru_hole circle (at 1.395 11.43 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 56 | (pad 10 thru_hole circle (at 3.685 11.43 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 57 | (pad 14 thru_hole circle (at 2.54 8.89 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 58 | (pad 15 thru_hole circle (at 4.83 8.89 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 59 | (pad 12 thru_hole circle (at -2.04 8.89 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 60 | (pad 13 thru_hole circle (at 0.25 8.89 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 61 | (pad 11 thru_hole circle (at -4.33 8.89 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 62 | (pad 5 thru_hole circle (at 4.83 13.97 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 63 | (pad 4 thru_hole circle (at 2.54 13.97 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 64 | (pad 3 thru_hole circle (at 0.25 13.97 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 65 | (pad 2 thru_hole circle (at -2.04 13.97 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 66 | (pad 1 thru_hole rect (at -4.33 13.97 180) (size 1.7 1.7) (drill 1.1) (layers *.Cu *.Mask)) 67 | (model ${KISYS3DMOD}/Connector_Dsub.3dshapes/DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm.wrl 68 | (at (xyz 0 0 0)) 69 | (scale (xyz 1 1 1)) 70 | (rotate (xyz 0 0 0)) 71 | ) 72 | ) 73 | -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.pretty/Icon : -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dan-rodrigues/pico-hx/ae957f788e57d77343deb94147a5ee680b52fda6/pcb/lib/RPi_Pico.pretty/Icon -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.pretty/MBR120_SOD-123.kicad_mod: -------------------------------------------------------------------------------- 1 | (module MBR120_SOD-123 (layer F.Cu) (tedit 5F02E60A) 2 | (descr SOD-123) 3 | (tags SOD-123) 4 | (attr smd) 5 | (fp_text reference REF** (at 0 -2) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value MBR120_SOD-123 (at 0 2.1) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_text user %R (at 0 -2) (layer F.Fab) 12 | (effects (font (size 1 1) (thickness 0.15))) 13 | ) 14 | (fp_line (start -2.3 -1) (end -2.3 1) (layer F.SilkS) (width 0.12)) 15 | (fp_line (start 0.25 0) (end 0.75 0) (layer F.Fab) (width 0.1)) 16 | (fp_line (start 0.25 0.4) (end -0.35 0) (layer F.Fab) (width 0.1)) 17 | (fp_line (start 0.25 -0.4) (end 0.25 0.4) (layer F.Fab) (width 0.1)) 18 | (fp_line (start -0.35 0) (end 0.25 -0.4) (layer F.Fab) (width 0.1)) 19 | (fp_line (start -0.35 0) (end -0.35 0.55) (layer F.Fab) (width 0.1)) 20 | (fp_line (start -0.35 0) (end -0.35 -0.55) (layer F.Fab) (width 0.1)) 21 | (fp_line (start -0.75 0) (end -0.35 0) (layer F.Fab) (width 0.1)) 22 | (fp_line (start -1.4 0.9) (end -1.4 -0.9) (layer F.Fab) (width 0.1)) 23 | (fp_line (start 1.4 0.9) (end -1.4 0.9) (layer F.Fab) (width 0.1)) 24 | (fp_line (start 1.4 -0.9) (end 1.4 0.9) (layer F.Fab) (width 0.1)) 25 | (fp_line (start -1.4 -0.9) (end 1.4 -0.9) (layer F.Fab) (width 0.1)) 26 | (fp_line (start -2.35 -1.15) (end 2.35 -1.15) (layer F.CrtYd) (width 0.05)) 27 | (fp_line (start 2.35 -1.15) (end 2.35 1.15) (layer F.CrtYd) (width 0.05)) 28 | (fp_line (start 2.35 1.15) (end -2.35 1.15) (layer F.CrtYd) (width 0.05)) 29 | (fp_line (start -2.35 -1.15) (end -2.35 1.15) (layer F.CrtYd) (width 0.05)) 30 | (fp_line (start -2.3 1) (end 1.65 1) (layer F.SilkS) (width 0.12)) 31 | (fp_line (start -2.3 -1) (end 1.65 -1) (layer F.SilkS) (width 0.12)) 32 | (pad 1 smd rect (at -1.475 0) (size 1.25 1.22) (layers F.Cu F.Paste F.Mask)) 33 | (pad 2 smd rect (at 1.475 0) (size 1.25 1.22) (layers F.Cu F.Paste F.Mask)) 34 | (model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_SOD-123.wrl 35 | (at (xyz 0 0 0)) 36 | (scale (xyz 1 1 1)) 37 | (rotate (xyz 0 0 0)) 38 | ) 39 | ) 40 | -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.pretty/RPi_Pico_SMD_TH.kicad_mod: -------------------------------------------------------------------------------- 1 | (module RPi_Pico_SMD_TH (layer F.Cu) (tedit 5F638C80) 2 | (descr "Through hole straight pin header, 2x20, 2.54mm pitch, double rows") 3 | (tags "Through hole pin header THT 2x20 2.54mm double row") 4 | (fp_text reference REF** (at 0 0) (layer F.SilkS) 5 | (effects (font (size 1 1) (thickness 0.15))) 6 | ) 7 | (fp_text value RPi_Pico_SMD_TH (at 0 2.159) (layer F.Fab) 8 | (effects (font (size 1 1) (thickness 0.15))) 9 | ) 10 | (fp_line (start 1.1 25.5) (end 1.5 25.5) (layer F.SilkS) (width 0.12)) 11 | (fp_line (start -1.5 25.5) (end -1.1 25.5) (layer F.SilkS) (width 0.12)) 12 | (fp_line (start 10.5 25.5) (end 3.7 25.5) (layer F.SilkS) (width 0.12)) 13 | (fp_line (start 10.5 15.1) (end 10.5 15.5) (layer F.SilkS) (width 0.12)) 14 | (fp_line (start 10.5 7.4) (end 10.5 7.8) (layer F.SilkS) (width 0.12)) 15 | (fp_line (start 10.5 -18) (end 10.5 -17.6) (layer F.SilkS) (width 0.12)) 16 | (fp_line (start 10.5 -25.5) (end 10.5 -25.2) (layer F.SilkS) (width 0.12)) 17 | (fp_line (start 10.5 -2.7) (end 10.5 -2.3) (layer F.SilkS) (width 0.12)) 18 | (fp_line (start 10.5 12.5) (end 10.5 12.9) (layer F.SilkS) (width 0.12)) 19 | (fp_line (start 10.5 -7.8) (end 10.5 -7.4) (layer F.SilkS) (width 0.12)) 20 | (fp_line (start 10.5 -12.9) (end 10.5 -12.5) (layer F.SilkS) (width 0.12)) 21 | (fp_line (start 10.5 -0.2) (end 10.5 0.2) (layer F.SilkS) (width 0.12)) 22 | (fp_line (start 10.5 4.9) (end 10.5 5.3) (layer F.SilkS) (width 0.12)) 23 | (fp_line (start 10.5 20.1) (end 10.5 20.5) (layer F.SilkS) (width 0.12)) 24 | (fp_line (start 10.5 22.7) (end 10.5 23.1) (layer F.SilkS) (width 0.12)) 25 | (fp_line (start 10.5 17.6) (end 10.5 18) (layer F.SilkS) (width 0.12)) 26 | (fp_line (start 10.5 -15.4) (end 10.5 -15) (layer F.SilkS) (width 0.12)) 27 | (fp_line (start 10.5 -23.1) (end 10.5 -22.7) (layer F.SilkS) (width 0.12)) 28 | (fp_line (start 10.5 -20.5) (end 10.5 -20.1) (layer F.SilkS) (width 0.12)) 29 | (fp_line (start 10.5 10) (end 10.5 10.4) (layer F.SilkS) (width 0.12)) 30 | (fp_line (start 10.5 2.3) (end 10.5 2.7) (layer F.SilkS) (width 0.12)) 31 | (fp_line (start 10.5 -5.3) (end 10.5 -4.9) (layer F.SilkS) (width 0.12)) 32 | (fp_line (start 10.5 -10.4) (end 10.5 -10) (layer F.SilkS) (width 0.12)) 33 | (fp_line (start -10.5 22.7) (end -10.5 23.1) (layer F.SilkS) (width 0.12)) 34 | (fp_line (start -10.5 20.1) (end -10.5 20.5) (layer F.SilkS) (width 0.12)) 35 | (fp_line (start -10.5 17.6) (end -10.5 18) (layer F.SilkS) (width 0.12)) 36 | (fp_line (start -10.5 15.1) (end -10.5 15.5) (layer F.SilkS) (width 0.12)) 37 | (fp_line (start -10.5 12.5) (end -10.5 12.9) (layer F.SilkS) (width 0.12)) 38 | (fp_line (start -10.5 10) (end -10.5 10.4) (layer F.SilkS) (width 0.12)) 39 | (fp_line (start -10.5 7.4) (end -10.5 7.8) (layer F.SilkS) (width 0.12)) 40 | (fp_line (start -10.5 4.9) (end -10.5 5.3) (layer F.SilkS) (width 0.12)) 41 | (fp_line (start -10.5 2.3) (end -10.5 2.7) (layer F.SilkS) (width 0.12)) 42 | (fp_line (start -10.5 -0.2) (end -10.5 0.2) (layer F.SilkS) (width 0.12)) 43 | (fp_line (start -10.5 -2.7) (end -10.5 -2.3) (layer F.SilkS) (width 0.12)) 44 | (fp_line (start -10.5 -5.3) (end -10.5 -4.9) (layer F.SilkS) (width 0.12)) 45 | (fp_line (start -10.5 -7.8) (end -10.5 -7.4) (layer F.SilkS) (width 0.12)) 46 | (fp_line (start -10.5 -10.4) (end -10.5 -10) (layer F.SilkS) (width 0.12)) 47 | (fp_line (start -10.5 -12.9) (end -10.5 -12.5) (layer F.SilkS) (width 0.12)) 48 | (fp_line (start -10.5 -15.4) (end -10.5 -15) (layer F.SilkS) (width 0.12)) 49 | (fp_line (start -10.5 -18) (end -10.5 -17.6) (layer F.SilkS) (width 0.12)) 50 | (fp_line (start -10.5 -20.5) (end -10.5 -20.1) (layer F.SilkS) (width 0.12)) 51 | (fp_line (start -10.5 -23.1) (end -10.5 -22.7) (layer F.SilkS) (width 0.12)) 52 | (fp_line (start -10.5 -25.5) (end -10.5 -25.2) (layer F.SilkS) (width 0.12)) 53 | (fp_line (start -7.493 -22.833) (end -7.493 -25.5) (layer F.SilkS) (width 0.12)) 54 | (fp_line (start -10.5 -22.833) (end -7.493 -22.833) (layer F.SilkS) (width 0.12)) 55 | (fp_line (start -3.7 25.5) (end -10.5 25.5) (layer F.SilkS) (width 0.12)) 56 | (fp_line (start -10.5 -25.5) (end 10.5 -25.5) (layer F.SilkS) (width 0.12)) 57 | (fp_line (start -11 26) (end -11 -26) (layer F.CrtYd) (width 0.12)) 58 | (fp_line (start 11 26) (end -11 26) (layer F.CrtYd) (width 0.12)) 59 | (fp_line (start 11 -26) (end 11 26) (layer F.CrtYd) (width 0.12)) 60 | (fp_line (start -11 -26) (end 11 -26) (layer F.CrtYd) (width 0.12)) 61 | (fp_line (start -10.5 -24.2) (end -9.2 -25.5) (layer F.Fab) (width 0.12)) 62 | (fp_line (start -10.5 25.5) (end -10.5 -25.5) (layer F.Fab) (width 0.12)) 63 | (fp_line (start 10.5 25.5) (end -10.5 25.5) (layer F.Fab) (width 0.12)) 64 | (fp_line (start 10.5 -25.5) (end 10.5 25.5) (layer F.Fab) (width 0.12)) 65 | (fp_line (start -10.5 -25.5) (end 10.5 -25.5) (layer F.Fab) (width 0.12)) 66 | (fp_text user %R (at 0 0 180) (layer F.Fab) 67 | (effects (font (size 1 1) (thickness 0.15))) 68 | ) 69 | (fp_text user GP1 (at -12.9 -21.6 45) (layer F.SilkS) 70 | (effects (font (size 0.8 0.8) (thickness 0.15))) 71 | ) 72 | (fp_text user GP2 (at -12.9 -16.51 45) (layer F.SilkS) 73 | (effects (font (size 0.8 0.8) (thickness 0.15))) 74 | ) 75 | (fp_text user GP0 (at -12.8 -24.13 45) (layer F.SilkS) 76 | (effects (font (size 0.8 0.8) (thickness 0.15))) 77 | ) 78 | (fp_text user GP3 (at -12.8 -13.97 45) (layer F.SilkS) 79 | (effects (font (size 0.8 0.8) (thickness 0.15))) 80 | ) 81 | (fp_text user GP4 (at -12.8 -11.43 45) (layer F.SilkS) 82 | (effects (font (size 0.8 0.8) (thickness 0.15))) 83 | ) 84 | (fp_text user GP5 (at -12.8 -8.89 45) (layer F.SilkS) 85 | (effects (font (size 0.8 0.8) (thickness 0.15))) 86 | ) 87 | (fp_text user GP6 (at -12.8 -3.81 45) (layer F.SilkS) 88 | (effects (font (size 0.8 0.8) (thickness 0.15))) 89 | ) 90 | (fp_text user GP7 (at -12.7 -1.3 45) (layer F.SilkS) 91 | (effects (font (size 0.8 0.8) (thickness 0.15))) 92 | ) 93 | (fp_text user GP8 (at -12.8 1.27 45) (layer F.SilkS) 94 | (effects (font (size 0.8 0.8) (thickness 0.15))) 95 | ) 96 | (fp_text user GP9 (at -12.8 3.81 45) (layer F.SilkS) 97 | (effects (font (size 0.8 0.8) (thickness 0.15))) 98 | ) 99 | (fp_text user GP10 (at -13.054 8.89 45) (layer F.SilkS) 100 | (effects (font (size 0.8 0.8) (thickness 0.15))) 101 | ) 102 | (fp_text user GP11 (at -13.2 11.43 45) (layer F.SilkS) 103 | (effects (font (size 0.8 0.8) (thickness 0.15))) 104 | ) 105 | (fp_text user GP12 (at -13.2 13.97 45) (layer F.SilkS) 106 | (effects (font (size 0.8 0.8) (thickness 0.15))) 107 | ) 108 | (fp_text user GP13 (at -13.054 16.51 45) (layer F.SilkS) 109 | (effects (font (size 0.8 0.8) (thickness 0.15))) 110 | ) 111 | (fp_text user GP14 (at -13.1 21.59 45) (layer F.SilkS) 112 | (effects (font (size 0.8 0.8) (thickness 0.15))) 113 | ) 114 | (fp_text user GP15 (at -13.054 24.13 45) (layer F.SilkS) 115 | (effects (font (size 0.8 0.8) (thickness 0.15))) 116 | ) 117 | (fp_text user GP16 (at 13.054 24.13 45) (layer F.SilkS) 118 | (effects (font (size 0.8 0.8) (thickness 0.15))) 119 | ) 120 | (fp_text user GP17 (at 13.054 21.59 45) (layer F.SilkS) 121 | (effects (font (size 0.8 0.8) (thickness 0.15))) 122 | ) 123 | (fp_text user GP18 (at 13.054 16.51 45) (layer F.SilkS) 124 | (effects (font (size 0.8 0.8) (thickness 0.15))) 125 | ) 126 | (fp_text user GP19 (at 13.054 13.97 45) (layer F.SilkS) 127 | (effects (font (size 0.8 0.8) (thickness 0.15))) 128 | ) 129 | (fp_text user GP20 (at 13.054 11.43 45) (layer F.SilkS) 130 | (effects (font (size 0.8 0.8) (thickness 0.15))) 131 | ) 132 | (fp_text user GP21 (at 13.054 8.9 45) (layer F.SilkS) 133 | (effects (font (size 0.8 0.8) (thickness 0.15))) 134 | ) 135 | (fp_text user GP22 (at 13.054 3.81 45) (layer F.SilkS) 136 | (effects (font (size 0.8 0.8) (thickness 0.15))) 137 | ) 138 | (fp_text user RUN (at 13 1.27 45) (layer F.SilkS) 139 | (effects (font (size 0.8 0.8) (thickness 0.15))) 140 | ) 141 | (fp_text user GP26 (at 13.054 -1.27 45) (layer F.SilkS) 142 | (effects (font (size 0.8 0.8) (thickness 0.15))) 143 | ) 144 | (fp_text user GP27 (at 13.054 -3.8 45) (layer F.SilkS) 145 | (effects (font (size 0.8 0.8) (thickness 0.15))) 146 | ) 147 | (fp_text user GP28 (at 13.054 -9.144 45) (layer F.SilkS) 148 | (effects (font (size 0.8 0.8) (thickness 0.15))) 149 | ) 150 | (fp_text user ADC_VREF (at 14 -12.5 45) (layer F.SilkS) 151 | (effects (font (size 0.8 0.8) (thickness 0.15))) 152 | ) 153 | (fp_text user 3V3 (at 12.9 -13.9 45) (layer F.SilkS) 154 | (effects (font (size 0.8 0.8) (thickness 0.15))) 155 | ) 156 | (fp_text user 3V3_EN (at 13.7 -17.2 45) (layer F.SilkS) 157 | (effects (font (size 0.8 0.8) (thickness 0.15))) 158 | ) 159 | (fp_text user VSYS (at 13.2 -21.59 45) (layer F.SilkS) 160 | (effects (font (size 0.8 0.8) (thickness 0.15))) 161 | ) 162 | (fp_text user VBUS (at 13.3 -24.2 45) (layer F.SilkS) 163 | (effects (font (size 0.8 0.8) (thickness 0.15))) 164 | ) 165 | (fp_text user GND (at -12.8 -19.05 45) (layer F.SilkS) 166 | (effects (font (size 0.8 0.8) (thickness 0.15))) 167 | ) 168 | (fp_text user GND (at -12.8 -6.35 45) (layer F.SilkS) 169 | (effects (font (size 0.8 0.8) (thickness 0.15))) 170 | ) 171 | (fp_text user GND (at -12.8 6.35 45) (layer F.SilkS) 172 | (effects (font (size 0.8 0.8) (thickness 0.15))) 173 | ) 174 | (fp_text user GND (at -12.8 19.05 45) (layer F.SilkS) 175 | (effects (font (size 0.8 0.8) (thickness 0.15))) 176 | ) 177 | (fp_text user GND (at 12.8 19.05 45) (layer F.SilkS) 178 | (effects (font (size 0.8 0.8) (thickness 0.15))) 179 | ) 180 | (fp_text user GND (at 12.8 6.35 45) (layer F.SilkS) 181 | (effects (font (size 0.8 0.8) (thickness 0.15))) 182 | ) 183 | (fp_text user GND (at 12.8 -19.05 45) (layer F.SilkS) 184 | (effects (font (size 0.8 0.8) (thickness 0.15))) 185 | ) 186 | (fp_text user AGND (at 13.054 -6.35 45) (layer F.SilkS) 187 | (effects (font (size 0.8 0.8) (thickness 0.15))) 188 | ) 189 | (fp_text user SWCLK (at -5.7 26.2) (layer F.SilkS) 190 | (effects (font (size 0.8 0.8) (thickness 0.15))) 191 | ) 192 | (fp_text user SWDIO (at 5.6 26.2) (layer F.SilkS) 193 | (effects (font (size 0.8 0.8) (thickness 0.15))) 194 | ) 195 | (fp_poly (pts (xy -1.5 -16.5) (xy -3.5 -16.5) (xy -3.5 -18.5) (xy -1.5 -18.5)) (layer Dwgs.User) (width 0.1)) 196 | (fp_poly (pts (xy -1.5 -14) (xy -3.5 -14) (xy -3.5 -16) (xy -1.5 -16)) (layer Dwgs.User) (width 0.1)) 197 | (fp_poly (pts (xy -1.5 -11.5) (xy -3.5 -11.5) (xy -3.5 -13.5) (xy -1.5 -13.5)) (layer Dwgs.User) (width 0.1)) 198 | (fp_poly (pts (xy 3.7 -20.2) (xy -3.7 -20.2) (xy -3.7 -24.9) (xy 3.7 -24.9)) (layer Dwgs.User) (width 0.1)) 199 | (fp_text user "Copper Keepouts shown on Dwgs layer" (at 0.1 -30.2) (layer Cmts.User) 200 | (effects (font (size 1 1) (thickness 0.15))) 201 | ) 202 | (pad 1 thru_hole oval (at -8.89 -24.13) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 203 | (pad 2 thru_hole oval (at -8.89 -21.59) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 204 | (pad 3 thru_hole rect (at -8.89 -19.05) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 205 | (pad 4 thru_hole oval (at -8.89 -16.51) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 206 | (pad 5 thru_hole oval (at -8.89 -13.97) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 207 | (pad 6 thru_hole oval (at -8.89 -11.43) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 208 | (pad 7 thru_hole oval (at -8.89 -8.89) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 209 | (pad 8 thru_hole rect (at -8.89 -6.35) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 210 | (pad 9 thru_hole oval (at -8.89 -3.81) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 211 | (pad 10 thru_hole oval (at -8.89 -1.27) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 212 | (pad 11 thru_hole oval (at -8.89 1.27) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 213 | (pad 12 thru_hole oval (at -8.89 3.81) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 214 | (pad 13 thru_hole rect (at -8.89 6.35) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 215 | (pad 14 thru_hole oval (at -8.89 8.89) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 216 | (pad 15 thru_hole oval (at -8.89 11.43) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 217 | (pad 16 thru_hole oval (at -8.89 13.97) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 218 | (pad 17 thru_hole oval (at -8.89 16.51) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 219 | (pad 18 thru_hole rect (at -8.89 19.05) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 220 | (pad 19 thru_hole oval (at -8.89 21.59) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 221 | (pad 20 thru_hole oval (at -8.89 24.13) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 222 | (pad 21 thru_hole oval (at 8.89 24.13) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 223 | (pad 22 thru_hole oval (at 8.89 21.59) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 224 | (pad 23 thru_hole rect (at 8.89 19.05) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 225 | (pad 24 thru_hole oval (at 8.89 16.51) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 226 | (pad 25 thru_hole oval (at 8.89 13.97) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 227 | (pad 26 thru_hole oval (at 8.89 11.43) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 228 | (pad 27 thru_hole oval (at 8.89 8.89) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 229 | (pad 28 thru_hole rect (at 8.89 6.35) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 230 | (pad 29 thru_hole oval (at 8.89 3.81) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 231 | (pad 30 thru_hole oval (at 8.89 1.27) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 232 | (pad 31 thru_hole oval (at 8.89 -1.27) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 233 | (pad 32 thru_hole oval (at 8.89 -3.81) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 234 | (pad 33 thru_hole rect (at 8.89 -6.35) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 235 | (pad 34 thru_hole oval (at 8.89 -8.89) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 236 | (pad 35 thru_hole oval (at 8.89 -11.43) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 237 | (pad 36 thru_hole oval (at 8.89 -13.97) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 238 | (pad 37 thru_hole oval (at 8.89 -16.51) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 239 | (pad 38 thru_hole rect (at 8.89 -19.05) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 240 | (pad 39 thru_hole oval (at 8.89 -21.59) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 241 | (pad 40 thru_hole oval (at 8.89 -24.13) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 242 | (pad 1 smd rect (at -8.89 -24.13) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 243 | (pad 2 smd rect (at -8.89 -21.59) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 244 | (pad 3 smd rect (at -8.89 -19.05) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 245 | (pad 4 smd rect (at -8.89 -16.51) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 246 | (pad 5 smd rect (at -8.89 -13.97) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 247 | (pad 6 smd rect (at -8.89 -11.43) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 248 | (pad 7 smd rect (at -8.89 -8.89) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 249 | (pad 8 smd rect (at -8.89 -6.35) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 250 | (pad 9 smd rect (at -8.89 -3.81) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 251 | (pad 10 smd rect (at -8.89 -1.27) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 252 | (pad 11 smd rect (at -8.89 1.27) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 253 | (pad 12 smd rect (at -8.89 3.81) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 254 | (pad 13 smd rect (at -8.89 6.35) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 255 | (pad 14 smd rect (at -8.89 8.89) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 256 | (pad 15 smd rect (at -8.89 11.43) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 257 | (pad 16 smd rect (at -8.89 13.97) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 258 | (pad 17 smd rect (at -8.89 16.51) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 259 | (pad 18 smd rect (at -8.89 19.05) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 260 | (pad 19 smd rect (at -8.89 21.59) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 261 | (pad 20 smd rect (at -8.89 24.13) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 262 | (pad 40 smd rect (at 8.89 -24.13) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 263 | (pad 39 smd rect (at 8.89 -21.59) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 264 | (pad 38 smd rect (at 8.89 -19.05) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 265 | (pad 37 smd rect (at 8.89 -16.51) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 266 | (pad 36 smd rect (at 8.89 -13.97) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 267 | (pad 35 smd rect (at 8.89 -11.43) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 268 | (pad 34 smd rect (at 8.89 -8.89) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 269 | (pad 33 smd rect (at 8.89 -6.35) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 270 | (pad 32 smd rect (at 8.89 -3.81) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 271 | (pad 31 smd rect (at 8.89 -1.27) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 272 | (pad 30 smd rect (at 8.89 1.27) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 273 | (pad 29 smd rect (at 8.89 3.81) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 274 | (pad 28 smd rect (at 8.89 6.35) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 275 | (pad 27 smd rect (at 8.89 8.89) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 276 | (pad 26 smd rect (at 8.89 11.43) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 277 | (pad 25 smd rect (at 8.89 13.97) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 278 | (pad 24 smd rect (at 8.89 16.51) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 279 | (pad 23 smd rect (at 8.89 19.05) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 280 | (pad 22 smd rect (at 8.89 21.59) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 281 | (pad 21 smd rect (at 8.89 24.13) (size 3.5 1.7) (drill (offset 0.9 0)) (layers F.Cu F.Mask)) 282 | (pad "" np_thru_hole oval (at -2.725 -24) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)) 283 | (pad "" np_thru_hole oval (at 2.725 -24) (size 1.8 1.8) (drill 1.8) (layers *.Cu *.Mask)) 284 | (pad "" np_thru_hole oval (at -2.425 -20.97) (size 1.5 1.5) (drill 1.5) (layers *.Cu *.Mask)) 285 | (pad "" np_thru_hole oval (at 2.425 -20.97) (size 1.5 1.5) (drill 1.5) (layers *.Cu *.Mask)) 286 | (pad 41 smd rect (at -2.54 23.9 90) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 287 | (pad 41 thru_hole oval (at -2.54 23.9) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 288 | (pad 42 smd rect (at 0 23.9 90) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 289 | (pad 42 thru_hole rect (at 0 23.9) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 290 | (pad 43 smd rect (at 2.54 23.9 90) (size 3.5 1.7) (drill (offset -0.9 0)) (layers F.Cu F.Mask)) 291 | (pad 43 thru_hole oval (at 2.54 23.9) (size 1.7 1.7) (drill 1.02) (layers *.Cu *.Mask)) 292 | ) 293 | -------------------------------------------------------------------------------- /pcb/lib/RPi_Pico.pretty/USB_Micro-B_Amphenol_10103594-0001LF_Horizontal_modified.kicad_mod: -------------------------------------------------------------------------------- 1 | (module USB_Micro-B_Amphenol_10103594-0001LF_Horizontal_modified (layer F.Cu) (tedit 5F0317C2) 2 | (descr "Micro USB Type B 10103594-0001LF, http://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/10103594.pdf") 3 | (tags "USB USB_B USB_micro USB_OTG") 4 | (attr smd) 5 | (fp_text reference J5 (at -5.365 -2.58 -180) (layer F.SilkS) 6 | (effects (font (size 1 1) (thickness 0.15))) 7 | ) 8 | (fp_text value USB_B_Micro (at -0.025 3.32 -180) (layer F.Fab) 9 | (effects (font (size 1 1) (thickness 0.15))) 10 | ) 11 | (fp_line (start 4.14 1.7) (end -4.13 1.7) (layer F.CrtYd) (width 0.05)) 12 | (fp_line (start 4.14 1.7) (end 4.14 -3.995) (layer F.CrtYd) (width 0.05)) 13 | (fp_line (start -4.13 -3.995) (end -4.13 1.7) (layer F.CrtYd) (width 0.05)) 14 | (fp_line (start -4.13 -3.995) (end 4.14 -3.995) (layer F.CrtYd) (width 0.05)) 15 | (fp_line (start -4.02 1.7) (end 4.02 1.7) (layer Dwgs.User) (width 0.1)) 16 | (fp_line (start -3.775 2.22) (end -3.775 -1.98) (layer F.Fab) (width 0.12)) 17 | (fp_line (start -2.975 -2.73) (end 3.725 -2.73) (layer F.Fab) (width 0.12)) 18 | (fp_line (start 3.725 -2.73) (end 3.725 2.22) (layer F.Fab) (width 0.12)) 19 | (fp_line (start 3.725 2.22) (end -3.775 2.22) (layer F.Fab) (width 0.12)) 20 | (fp_line (start -3.775 -1.98) (end -2.975 -2.73) (layer F.Fab) (width 0.12)) 21 | (fp_line (start -1.325 -3.98) (end -1.725 -4.43) (layer F.SilkS) (width 0.12)) 22 | (fp_line (start -1.725 -4.43) (end -0.925 -4.43) (layer F.SilkS) (width 0.12)) 23 | (fp_line (start -0.925 -4.43) (end -1.325 -3.98) (layer F.SilkS) (width 0.12)) 24 | (fp_line (start 3.825 1.62) (end 3.825 -1.18) (layer F.SilkS) (width 0.12)) 25 | (fp_line (start 3.825 -1.18) (end 4.125 -1.18) (layer F.SilkS) (width 0.12)) 26 | (fp_line (start 4.125 -1.18) (end 4.125 -2.73) (layer F.SilkS) (width 0.12)) 27 | (fp_line (start -3.875 1.62) (end -3.875 -1.18) (layer F.SilkS) (width 0.12)) 28 | (fp_line (start -4.175 -1.18) (end -3.875 -1.18) (layer F.SilkS) (width 0.12)) 29 | (fp_line (start -4.175 -1.18) (end -4.175 -2.73) (layer F.SilkS) (width 0.12)) 30 | (fp_text user %R (at -0.025 -1.13 -180) (layer F.Fab) 31 | (effects (font (size 1 1) (thickness 0.15))) 32 | ) 33 | (fp_text user "PCB edge" (at -0.025 1.12 -180) (layer Dwgs.User) 34 | (effects (font (size 0.5 0.5) (thickness 0.075))) 35 | ) 36 | (pad 6 smd rect (at 0.9625 0.25 90) (size 2.5 1.425) (layers F.Cu F.Paste F.Mask)) 37 | (pad 6 smd rect (at -0.9625 0.25 90) (size 2.5 1.425) (layers F.Cu F.Paste F.Mask)) 38 | (pad 6 thru_hole oval (at 2.725 0 90) (size 1.8 1.3) (drill oval 1.2 0.7) (layers *.Cu *.Mask)) 39 | (pad 6 thru_hole oval (at -2.725 0 90) (size 1.8 1.3) (drill oval 1.2 0.7) (layers *.Cu *.Mask)) 40 | (pad 6 thru_hole oval (at -2.425 -3.03 90) (size 1.45 1.05) (drill oval 1.05 0.65) (layers *.Cu *.Mask)) 41 | (pad 5 smd rect (at 1.3 -2.825 90) (size 1.75 0.4) (layers F.Cu F.Paste F.Mask)) 42 | (pad 4 smd rect (at 0.65 -2.825 90) (size 1.75 0.4) (layers F.Cu F.Paste F.Mask)) 43 | (pad 3 smd rect (at 0 -2.825 90) (size 1.75 0.4) (layers F.Cu F.Paste F.Mask)) 44 | (pad 2 smd rect (at -0.65 -2.825 90) (size 1.75 0.4) (layers F.Cu F.Paste F.Mask)) 45 | (pad 1 smd rect (at -1.3 -2.825 90) (size 1.75 0.4) (layers F.Cu F.Paste F.Mask)) 46 | (pad 6 smd rect (at 2.9 -3.03) (size 2 1.46) (layers F.Cu F.Paste F.Mask)) 47 | (pad 6 smd rect (at -2.9 -3.03) (size 2 1.46) (layers F.Cu F.Paste F.Mask)) 48 | (pad 6 smd rect (at -2.9875 -1.7) (size 1.825 0.7) (layers F.Cu F.Paste F.Mask)) 49 | (pad 6 smd roundrect (at -2.725 -0.425) (size 1.3 3.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.296)) 50 | (pad 6 smd roundrect (at 2.725 -0.425) (size 1.3 3.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.296)) 51 | (pad 6 smd rect (at 2.9875 -1.7) (size 1.825 0.7) (layers F.Cu F.Paste F.Mask)) 52 | (pad 6 thru_hole oval (at 2.425 -3.03 90) (size 1.45 1.05) (drill oval 1.05 0.65) (layers *.Cu *.Mask)) 53 | (model 10103594.stp 54 | (offset (xyz 0 0.2 2.2)) 55 | (scale (xyz 1 1 1)) 56 | (rotate (xyz 90 0 180)) 57 | ) 58 | ) 59 | -------------------------------------------------------------------------------- /pcb/pico-hx.pro: -------------------------------------------------------------------------------- 1 | update=Wednesday, 31 March 2021 at 06:15:29 pm 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [pcbnew] 16 | version=1 17 | PageLayoutDescrFile= 18 | LastNetListRead= 19 | CopperLayerCount=4 20 | BoardThickness=1.6002 21 | AllowMicroVias=0 22 | AllowBlindVias=0 23 | RequireCourtyardDefinitions=1 24 | ProhibitOverlappingCourtyards=1 25 | MinTrackWidth=0.185 26 | MinViaDiameter=0.45 27 | MinViaDrill=0.2 28 | MinMicroViaDiameter=0.2 29 | MinMicroViaDrill=0.09999999999999999 30 | MinHoleToHole=0.254 31 | TrackWidth1=0.185 32 | TrackWidth2=0.185 33 | TrackWidth3=0.254 34 | TrackWidth4=0.5 35 | TrackWidth5=0.508 36 | TrackWidth6=0.762 37 | TrackWidth7=1 38 | ViaDiameter1=0.6858 39 | ViaDrill1=0.3302 40 | ViaDiameter2=0.6858 41 | ViaDrill2=0.3302 42 | ViaDiameter3=0.889 43 | ViaDrill3=0.381 44 | dPairWidth1=0.185 45 | dPairGap1=0.254 46 | dPairViaGap1=0.25 47 | SilkLineWidth=0.1524 48 | SilkTextSizeV=0.8128 49 | SilkTextSizeH=0.8128 50 | SilkTextSizeThickness=0.1524 51 | SilkTextItalic=0 52 | SilkTextUpright=1 53 | CopperLineWidth=0.254 54 | CopperTextSizeV=1.524 55 | CopperTextSizeH=1.524 56 | CopperTextThickness=0.3048 57 | CopperTextItalic=0 58 | CopperTextUpright=1 59 | EdgeCutLineWidth=0.03809999999999999 60 | CourtyardLineWidth=0.05 61 | OthersLineWidth=0.1524 62 | OthersTextSizeV=1.016 63 | OthersTextSizeH=1.016 64 | OthersTextSizeThickness=0.1524 65 | OthersTextItalic=0 66 | OthersTextUpright=1 67 | SolderMaskClearance=0 68 | SolderMaskMinWidth=0 69 | SolderPasteClearance=0 70 | SolderPasteRatio=-0 71 | [pcbnew/Layer.F.Cu] 72 | Name=F.Cu 73 | Type=0 74 | Enabled=1 75 | [pcbnew/Layer.In1.Cu] 76 | Name=In1.Cu 77 | Type=1 78 | Enabled=1 79 | [pcbnew/Layer.In2.Cu] 80 | Name=In2.Cu 81 | Type=1 82 | Enabled=1 83 | [pcbnew/Layer.In3.Cu] 84 | Name=In3.Cu 85 | Type=0 86 | Enabled=0 87 | [pcbnew/Layer.In4.Cu] 88 | Name=In4.Cu 89 | Type=0 90 | Enabled=0 91 | [pcbnew/Layer.In5.Cu] 92 | Name=In5.Cu 93 | Type=0 94 | Enabled=0 95 | [pcbnew/Layer.In6.Cu] 96 | Name=In6.Cu 97 | Type=0 98 | Enabled=0 99 | [pcbnew/Layer.In7.Cu] 100 | Name=In7.Cu 101 | Type=0 102 | Enabled=0 103 | [pcbnew/Layer.In8.Cu] 104 | Name=In8.Cu 105 | Type=0 106 | Enabled=0 107 | [pcbnew/Layer.In9.Cu] 108 | Name=In9.Cu 109 | Type=0 110 | Enabled=0 111 | [pcbnew/Layer.In10.Cu] 112 | Name=In10.Cu 113 | Type=0 114 | Enabled=0 115 | [pcbnew/Layer.In11.Cu] 116 | Name=In11.Cu 117 | Type=0 118 | Enabled=0 119 | [pcbnew/Layer.In12.Cu] 120 | Name=In12.Cu 121 | Type=0 122 | Enabled=0 123 | [pcbnew/Layer.In13.Cu] 124 | Name=In13.Cu 125 | Type=0 126 | Enabled=0 127 | [pcbnew/Layer.In14.Cu] 128 | Name=In14.Cu 129 | Type=0 130 | Enabled=0 131 | [pcbnew/Layer.In15.Cu] 132 | Name=In15.Cu 133 | Type=0 134 | Enabled=0 135 | [pcbnew/Layer.In16.Cu] 136 | Name=In16.Cu 137 | Type=0 138 | Enabled=0 139 | [pcbnew/Layer.In17.Cu] 140 | Name=In17.Cu 141 | Type=0 142 | Enabled=0 143 | [pcbnew/Layer.In18.Cu] 144 | Name=In18.Cu 145 | Type=0 146 | Enabled=0 147 | [pcbnew/Layer.In19.Cu] 148 | Name=In19.Cu 149 | Type=0 150 | Enabled=0 151 | [pcbnew/Layer.In20.Cu] 152 | Name=In20.Cu 153 | Type=0 154 | Enabled=0 155 | [pcbnew/Layer.In21.Cu] 156 | Name=In21.Cu 157 | Type=0 158 | Enabled=0 159 | [pcbnew/Layer.In22.Cu] 160 | Name=In22.Cu 161 | Type=0 162 | Enabled=0 163 | [pcbnew/Layer.In23.Cu] 164 | Name=In23.Cu 165 | Type=0 166 | Enabled=0 167 | [pcbnew/Layer.In24.Cu] 168 | Name=In24.Cu 169 | Type=0 170 | Enabled=0 171 | [pcbnew/Layer.In25.Cu] 172 | Name=In25.Cu 173 | Type=0 174 | Enabled=0 175 | [pcbnew/Layer.In26.Cu] 176 | Name=In26.Cu 177 | Type=0 178 | Enabled=0 179 | [pcbnew/Layer.In27.Cu] 180 | Name=In27.Cu 181 | Type=0 182 | Enabled=0 183 | [pcbnew/Layer.In28.Cu] 184 | Name=In28.Cu 185 | Type=0 186 | Enabled=0 187 | [pcbnew/Layer.In29.Cu] 188 | Name=In29.Cu 189 | Type=0 190 | Enabled=0 191 | [pcbnew/Layer.In30.Cu] 192 | Name=In30.Cu 193 | Type=0 194 | Enabled=0 195 | [pcbnew/Layer.B.Cu] 196 | Name=B.Cu 197 | Type=0 198 | Enabled=1 199 | [pcbnew/Layer.B.Adhes] 200 | Enabled=0 201 | [pcbnew/Layer.F.Adhes] 202 | Enabled=0 203 | [pcbnew/Layer.B.Paste] 204 | Enabled=1 205 | [pcbnew/Layer.F.Paste] 206 | Enabled=1 207 | [pcbnew/Layer.B.SilkS] 208 | Enabled=1 209 | [pcbnew/Layer.F.SilkS] 210 | Enabled=1 211 | [pcbnew/Layer.B.Mask] 212 | Enabled=1 213 | [pcbnew/Layer.F.Mask] 214 | Enabled=1 215 | [pcbnew/Layer.Dwgs.User] 216 | Enabled=1 217 | [pcbnew/Layer.Cmts.User] 218 | Enabled=0 219 | [pcbnew/Layer.Eco1.User] 220 | Enabled=0 221 | [pcbnew/Layer.Eco2.User] 222 | Enabled=0 223 | [pcbnew/Layer.Edge.Cuts] 224 | Enabled=1 225 | [pcbnew/Layer.Margin] 226 | Enabled=1 227 | [pcbnew/Layer.B.CrtYd] 228 | Enabled=1 229 | [pcbnew/Layer.F.CrtYd] 230 | Enabled=1 231 | [pcbnew/Layer.B.Fab] 232 | Enabled=0 233 | [pcbnew/Layer.F.Fab] 234 | Enabled=1 235 | [pcbnew/Layer.Rescue] 236 | Enabled=0 237 | [pcbnew/Netclasses] 238 | [pcbnew/Netclasses/Default] 239 | Name=Default 240 | Clearance=0.15 241 | TrackWidth=0.185 242 | ViaDiameter=0.6858 243 | ViaDrill=0.3302 244 | uViaDiameter=0.6858 245 | uViaDrill=0.3302 246 | dPairWidth=0.185 247 | dPairGap=0.254 248 | dPairViaGap=0.25 249 | -------------------------------------------------------------------------------- /pcb/pico-hx.sch: -------------------------------------------------------------------------------- 1 | EESchema Schematic File Version 4 2 | EELAYER 30 0 3 | EELAYER END 4 | $Descr A3 16535 11693 5 | encoding utf-8 6 | Sheet 1 1 7 | Title "" 8 | Date "" 9 | Rev "" 10 | Comp "" 11 | Comment1 "" 12 | Comment2 "" 13 | Comment3 "" 14 | Comment4 "" 15 | $EndDescr 16 | $Comp 17 | L RPi_Pico:Pico U1 18 | U 1 1 606423DC 19 | P 13000 4050 20 | F 0 "U1" H 13000 5265 50 0000 C CNN 21 | F 1 "Pico" H 13000 5174 50 0000 C CNN 22 | F 2 "RPi_Pico:RPi_Pico_SMD_TH" V 13000 4050 50 0001 C CNN 23 | F 3 "" H 13000 4050 50 0001 C CNN 24 | 1 13000 4050 25 | 1 0 0 -1 26 | $EndComp 27 | $Comp 28 | L FPGA_Lattice:ICE40HX1K-TQ144 U2 29 | U 1 1 606476E2 30 | P 2200 2250 31 | F 0 "U2" H 2580 2378 50 0000 L CNN 32 | F 1 "ICE40HX1K-TQ144" H 2580 2287 50 0000 L CNN 33 | F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 2200 800 50 0001 C CNN 34 | F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40" H 1350 3650 50 0001 C CNN 35 | 1 2200 2250 36 | 1 0 0 -1 37 | $EndComp 38 | $Comp 39 | L FPGA_Lattice:ICE40HX1K-TQ144 U2 40 | U 2 1 6064E759 41 | P 2200 5650 42 | F 0 "U2" H 2580 5778 50 0000 L CNN 43 | F 1 "ICE40HX1K-TQ144" H 2580 5687 50 0000 L CNN 44 | F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 2200 4200 50 0001 C CNN 45 | F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40" H 1350 7050 50 0001 C CNN 46 | 2 2200 5650 47 | 1 0 0 -1 48 | $EndComp 49 | $Comp 50 | L FPGA_Lattice:ICE40HX1K-TQ144 U2 51 | U 3 1 6065612E 52 | P 4550 2150 53 | F 0 "U2" H 4930 2278 50 0000 L CNN 54 | F 1 "ICE40HX1K-TQ144" H 4930 2187 50 0000 L CNN 55 | F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 4550 700 50 0001 C CNN 56 | F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40" H 3700 3550 50 0001 C CNN 57 | 3 4550 2150 58 | 1 0 0 -1 59 | $EndComp 60 | $Comp 61 | L FPGA_Lattice:ICE40HX1K-TQ144 U2 62 | U 4 1 6065C7EE 63 | P 4550 5650 64 | F 0 "U2" H 4930 5778 50 0000 L CNN 65 | F 1 "ICE40HX1K-TQ144" H 4930 5687 50 0000 L CNN 66 | F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 4550 4200 50 0001 C CNN 67 | F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40" H 3700 7050 50 0001 C CNN 68 | 4 4550 5650 69 | 1 0 0 -1 70 | $EndComp 71 | $Comp 72 | L FPGA_Lattice:ICE40HX1K-TQ144 U2 73 | U 5 1 6066C16E 74 | P 7200 2850 75 | F 0 "U2" H 8000 3550 50 0000 L CNN 76 | F 1 "ICE40HX1K-TQ144" H 7700 3450 50 0000 L CNN 77 | F 2 "Package_QFP:TQFP-144_20x20mm_P0.5mm" H 7200 1400 50 0001 C CNN 78 | F 3 "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40" H 6350 4250 50 0001 C CNN 79 | 5 7200 2850 80 | 1 0 0 -1 81 | $EndComp 82 | NoConn ~ 13700 3400 83 | Wire Wire Line 84 | 13700 3500 14000 3500 85 | $Comp 86 | L power:+3V3 #PWR0101 87 | U 1 1 6067F816 88 | P 14000 2900 89 | F 0 "#PWR0101" H 14000 2750 50 0001 C CNN 90 | F 1 "+3V3" H 14015 3073 50 0000 C CNN 91 | F 2 "" H 14000 2900 50 0001 C CNN 92 | F 3 "" H 14000 2900 50 0001 C CNN 93 | 1 14000 2900 94 | 1 0 0 -1 95 | $EndComp 96 | $Comp 97 | L power:+5V #PWR0102 98 | U 1 1 60645814 99 | P 13750 2900 100 | F 0 "#PWR0102" H 13750 2750 50 0001 C CNN 101 | F 1 "+5V" H 13765 3073 50 0000 C CNN 102 | F 2 "" H 13750 2900 50 0001 C CNN 103 | F 3 "" H 13750 2900 50 0001 C CNN 104 | 1 13750 2900 105 | 1 0 0 -1 106 | $EndComp 107 | NoConn ~ 13700 3200 108 | $Comp 109 | L power:GND #PWR0103 110 | U 1 1 60646696 111 | P 13750 5150 112 | F 0 "#PWR0103" H 13750 4900 50 0001 C CNN 113 | F 1 "GND" H 13755 4977 50 0000 C CNN 114 | F 2 "" H 13750 5150 50 0001 C CNN 115 | F 3 "" H 13750 5150 50 0001 C CNN 116 | 1 13750 5150 117 | 1 0 0 -1 118 | $EndComp 119 | Wire Wire Line 120 | 13700 3300 13750 3300 121 | Wire Wire Line 122 | 13750 3300 13750 3800 123 | Wire Wire Line 124 | 13700 3800 13750 3800 125 | Connection ~ 13750 3800 126 | Wire Wire Line 127 | 13750 3800 13750 4300 128 | Wire Wire Line 129 | 13700 4300 13750 4300 130 | Connection ~ 13750 4300 131 | Wire Wire Line 132 | 13750 4300 13750 4800 133 | Wire Wire Line 134 | 13700 4800 13750 4800 135 | Connection ~ 13750 4800 136 | Wire Wire Line 137 | 13750 4800 13750 5150 138 | Wire Wire Line 139 | 12300 3300 12250 3300 140 | Wire Wire Line 141 | 12250 3300 12250 3800 142 | $Comp 143 | L power:GND #PWR0104 144 | U 1 1 6064B5FC 145 | P 12250 5250 146 | F 0 "#PWR0104" H 12250 5000 50 0001 C CNN 147 | F 1 "GND" H 12255 5077 50 0000 C CNN 148 | F 2 "" H 12250 5250 50 0001 C CNN 149 | F 3 "" H 12250 5250 50 0001 C CNN 150 | 1 12250 5250 151 | 1 0 0 -1 152 | $EndComp 153 | Wire Wire Line 154 | 12300 4800 12250 4800 155 | Connection ~ 12250 4800 156 | Wire Wire Line 157 | 12250 4800 12250 5150 158 | Wire Wire Line 159 | 12300 4300 12250 4300 160 | Connection ~ 12250 4300 161 | Wire Wire Line 162 | 12250 4300 12250 4800 163 | Wire Wire Line 164 | 12300 3800 12250 3800 165 | Connection ~ 12250 3800 166 | Wire Wire Line 167 | 12250 3800 12250 4300 168 | Wire Wire Line 169 | 13000 5200 13000 5500 170 | $Comp 171 | L power:GND #PWR0105 172 | U 1 1 6064E7C0 173 | P 13000 5500 174 | F 0 "#PWR0105" H 13000 5250 50 0001 C CNN 175 | F 1 "GND" V 13000 5300 50 0000 C CNN 176 | F 2 "" H 13000 5500 50 0001 C CNN 177 | F 3 "" H 13000 5500 50 0001 C CNN 178 | 1 13000 5500 179 | 1 0 0 -1 180 | $EndComp 181 | $Comp 182 | L Connector:Micro_SD_Card J3 183 | U 1 1 606531A0 184 | P 14850 6600 185 | F 0 "J3" H 14800 7317 50 0000 C CNN 186 | F 1 "Micro_SD" H 14800 7226 50 0000 C CNN 187 | F 2 "Connector_Card:microSD_HC_Hirose_DM3D-SF" H 16000 6900 50 0001 C CNN 188 | F 3 "https://www.hirose.com/product/document?clcode=CL0609-0033-6-00&productname=DM3AT-SF-PEJ2M5&series=DM3&documenttype=Catalog&lang=en&documentid=D49662_en" H 14850 6600 50 0001 C CNN 189 | 1 14850 6600 190 | 1 0 0 -1 191 | $EndComp 192 | Wire Wire Line 193 | 13700 4100 14300 4100 194 | $Comp 195 | L Switch:SW_SPST SW1 196 | U 1 1 6066A3B1 197 | P 14500 4100 198 | F 0 "SW1" H 14500 4335 50 0000 C CNN 199 | F 1 "RUN" H 14500 4244 50 0000 C CNN 200 | F 2 "Button_Switch_SMD:SW_SPST_PTS645" H 14500 4100 50 0001 C CNN 201 | F 3 "~" H 14500 4100 50 0001 C CNN 202 | 1 14500 4100 203 | 1 0 0 -1 204 | $EndComp 205 | $Comp 206 | L power:GND #PWR0106 207 | U 1 1 6066BD8A 208 | P 14800 4200 209 | F 0 "#PWR0106" H 14800 3950 50 0001 C CNN 210 | F 1 "GND" H 14805 4027 50 0000 C CNN 211 | F 2 "" H 14800 4200 50 0001 C CNN 212 | F 3 "" H 14800 4200 50 0001 C CNN 213 | 1 14800 4200 214 | 1 0 0 -1 215 | $EndComp 216 | Wire Wire Line 217 | 14800 4200 14800 4100 218 | Wire Wire Line 219 | 14800 4100 14700 4100 220 | Text Label 6550 3050 2 50 ~ 0 221 | FPGA_SS 222 | Wire Wire Line 223 | 6550 3050 6600 3050 224 | Text Label 6550 2950 2 50 ~ 0 225 | FPGA_SCK 226 | Wire Wire Line 227 | 6550 2950 6600 2950 228 | Text Label 6550 2850 2 50 ~ 0 229 | FPGA_SDI 230 | Wire Wire Line 231 | 6550 2850 6600 2850 232 | Text Label 6550 2750 2 50 ~ 0 233 | FPGA_SDO 234 | Wire Wire Line 235 | 6550 2750 6600 2750 236 | Text Label 6550 3250 2 50 ~ 0 237 | ~FPGA_CRESET 238 | Wire Wire Line 239 | 6550 3250 6600 3250 240 | $Comp 241 | L power:GND #PWR0107 242 | U 1 1 60677D36 243 | P 7200 3600 244 | F 0 "#PWR0107" H 7200 3350 50 0001 C CNN 245 | F 1 "GND" H 7205 3427 50 0000 C CNN 246 | F 2 "" H 7200 3600 50 0001 C CNN 247 | F 3 "" H 7200 3600 50 0001 C CNN 248 | 1 7200 3600 249 | 1 0 0 -1 250 | $EndComp 251 | Text Label 7850 2850 0 50 ~ 0 252 | FPGA_CDONE 253 | Wire Wire Line 254 | 7850 2850 7800 2850 255 | Wire Wire Line 256 | 7200 3550 7200 3600 257 | Wire Wire Line 258 | 12300 3100 12200 3100 259 | Wire Wire Line 260 | 12200 3200 12300 3200 261 | Text Label 12200 3100 2 50 ~ 0 262 | UART_TX 263 | Text Label 12200 3200 2 50 ~ 0 264 | UART_RX 265 | Text Label 12200 4700 2 50 ~ 0 266 | FPGA_SDO 267 | Wire Wire Line 268 | 12200 3400 12300 3400 269 | Text Label 13800 4000 0 50 ~ 0 270 | FPGA_SS 271 | Text Label 13800 3900 0 50 ~ 0 272 | FPGA_SCK 273 | Text Label 12200 4600 2 50 ~ 0 274 | FPGA_SDI 275 | Text Label 13800 4700 0 50 ~ 0 276 | ~FPGA_CRESET 277 | Wire Wire Line 278 | 12200 3500 12300 3500 279 | Wire Wire Line 280 | 12200 3600 12300 3600 281 | Wire Wire Line 282 | 12200 3700 12300 3700 283 | Wire Wire Line 284 | 12200 3900 12300 3900 285 | Text Label 13800 4600 0 50 ~ 0 286 | FPGA_CDONE 287 | Wire Wire Line 288 | 12200 4000 12300 4000 289 | Text Label 1700 6850 2 50 ~ 0 290 | FPGA_RPIO_0 291 | Text Label 1700 6150 2 50 ~ 0 292 | FPGA_RPIO_7 293 | Text Label 1650 5750 2 50 ~ 0 294 | FPGA_RPIO_S0 295 | Wire Wire Line 296 | 12200 4100 12300 4100 297 | Text Label 4000 2250 2 50 ~ 0 298 | FPGA_CLK 299 | Text Label 12200 3400 2 50 ~ 0 300 | FPGA_RPIO_0 301 | Text Label 12200 4200 2 50 ~ 0 302 | FPGA_RPIO_7 303 | Wire Wire Line 304 | 13800 4900 13700 4900 305 | Wire Wire Line 306 | 13950 6600 13900 6600 307 | $Comp 308 | L power:+3V3 #PWR0108 309 | U 1 1 60692490 310 | P 13900 6000 311 | F 0 "#PWR0108" H 13900 5850 50 0001 C CNN 312 | F 1 "+3V3" H 13915 6173 50 0000 C CNN 313 | F 2 "" H 13900 6000 50 0001 C CNN 314 | F 3 "" H 13900 6000 50 0001 C CNN 315 | 1 13900 6000 316 | 1 0 0 -1 317 | $EndComp 318 | $Comp 319 | L power:GND #PWR0109 320 | U 1 1 60693716 321 | P 13900 7350 322 | F 0 "#PWR0109" H 13900 7100 50 0001 C CNN 323 | F 1 "GND" H 13905 7177 50 0000 C CNN 324 | F 2 "" H 13900 7350 50 0001 C CNN 325 | F 3 "" H 13900 7350 50 0001 C CNN 326 | 1 13900 7350 327 | 1 0 0 -1 328 | $EndComp 329 | Wire Wire Line 330 | 13900 7350 13900 6800 331 | Wire Wire Line 332 | 13900 6800 13950 6800 333 | Wire Wire Line 334 | 15650 7200 15700 7200 335 | Wire Wire Line 336 | 15700 7200 15700 7350 337 | $Comp 338 | L power:GND #PWR0110 339 | U 1 1 60696935 340 | P 15700 7350 341 | F 0 "#PWR0110" H 15700 7100 50 0001 C CNN 342 | F 1 "GND" H 15705 7177 50 0000 C CNN 343 | F 2 "" H 15700 7350 50 0001 C CNN 344 | F 3 "" H 15700 7350 50 0001 C CNN 345 | 1 15700 7350 346 | 1 0 0 -1 347 | $EndComp 348 | Text Label 13850 6700 2 50 ~ 0 349 | SD_CLK 350 | Wire Wire Line 351 | 13850 6700 13950 6700 352 | Text Label 13850 6300 2 50 ~ 0 353 | SD_DAT2 354 | Wire Wire Line 355 | 13850 6300 13950 6300 356 | Text Label 13850 6400 2 50 ~ 0 357 | SD_DAT3 358 | Wire Wire Line 359 | 13850 6400 13950 6400 360 | Text Label 13850 6500 2 50 ~ 0 361 | SD_CMD 362 | Wire Wire Line 363 | 13900 6600 13900 6050 364 | Wire Wire Line 365 | 13850 6500 13950 6500 366 | Text Label 13850 6900 2 50 ~ 0 367 | SD_DAT0 368 | Wire Wire Line 369 | 13850 6900 13950 6900 370 | Text Label 13850 7000 2 50 ~ 0 371 | SD_DAT1 372 | Wire Wire Line 373 | 13850 7000 13950 7000 374 | Text Label 13800 4500 0 50 ~ 0 375 | SD_CLK 376 | Text Label 13800 5000 0 50 ~ 0 377 | SD_DAT2 378 | Text Label 13800 4900 0 50 ~ 0 379 | SD_DAT3 380 | Text Label 12200 4900 2 50 ~ 0 381 | SD_DAT0 382 | Text Label 12200 5000 2 50 ~ 0 383 | SD_DAT1 384 | Wire Wire Line 385 | 13800 4400 13700 4400 386 | Wire Wire Line 387 | 13700 4700 13800 4700 388 | Wire Wire Line 389 | 13800 4200 13700 4200 390 | Text Label 13800 4200 0 50 ~ 0 391 | SD_CMD 392 | Wire Wire Line 393 | 13800 4000 13700 4000 394 | Text Label 12200 4400 2 50 ~ 0 395 | FPGA_RPIO_S0 396 | Wire Wire Line 397 | 13800 4600 13700 4600 398 | Wire Wire Line 399 | 13800 3900 13700 3900 400 | Wire Wire Line 401 | 13800 4500 13700 4500 402 | Wire Wire Line 403 | 12300 4200 12200 4200 404 | NoConn ~ 13700 3600 405 | Wire Wire Line 406 | 13700 3700 13800 3700 407 | Wire Wire Line 408 | 13800 5000 13700 5000 409 | Text Label 12200 4500 2 50 ~ 0 410 | FPGA_RPIO_S1 411 | Text Label 1650 5650 2 50 ~ 0 412 | FPGA_RPIO_S1 413 | Wire Wire Line 414 | 1650 5650 1700 5650 415 | Wire Wire Line 416 | 1700 5750 1650 5750 417 | Wire Wire Line 418 | 1650 2250 1700 2250 419 | Text Label 1700 6750 2 50 ~ 0 420 | FPGA_RPIO_1 421 | Text Label 1700 6650 2 50 ~ 0 422 | FPGA_RPIO_2 423 | Text Label 1700 6550 2 50 ~ 0 424 | FPGA_RPIO_3 425 | Text Label 1700 6450 2 50 ~ 0 426 | FPGA_RPIO_4 427 | Text Label 1700 6350 2 50 ~ 0 428 | FPGA_RPIO_5 429 | Text Label 1700 6250 2 50 ~ 0 430 | FPGA_RPIO_6 431 | Text Label 12200 3500 2 50 ~ 0 432 | FPGA_RPIO_1 433 | Text Label 12200 3600 2 50 ~ 0 434 | FPGA_RPIO_2 435 | Text Label 12200 3700 2 50 ~ 0 436 | FPGA_RPIO_3 437 | Text Label 12200 3900 2 50 ~ 0 438 | FPGA_RPIO_4 439 | Text Label 12200 4000 2 50 ~ 0 440 | FPGA_RPIO_5 441 | Text Label 12200 4100 2 50 ~ 0 442 | FPGA_RPIO_6 443 | Wire Wire Line 444 | 12200 4400 12300 4400 445 | Wire Wire Line 446 | 12200 4500 12300 4500 447 | Wire Wire Line 448 | 12200 4600 12300 4600 449 | Wire Wire Line 450 | 12200 4700 12300 4700 451 | Wire Wire Line 452 | 12200 4900 12300 4900 453 | Wire Wire Line 454 | 12200 5000 12300 5000 455 | Text Label 4000 4550 2 50 ~ 0 456 | PMOD_A4 457 | Text Label 4000 4650 2 50 ~ 0 458 | PMOD_A10 459 | Wire Wire Line 460 | 4000 4550 4050 4550 461 | Wire Wire Line 462 | 4050 4850 4000 4850 463 | Text Label 4000 6350 2 50 ~ 0 464 | PMOD_B1 465 | Text Label 4000 6150 2 50 ~ 0 466 | PMOD_B2 467 | Text Label 4000 5950 2 50 ~ 0 468 | PMOD_B3 469 | Text Label 4000 5750 2 50 ~ 0 470 | PMOD_B4 471 | Wire Wire Line 472 | 4050 6050 4000 6050 473 | Wire Wire Line 474 | 4000 5950 4050 5950 475 | Wire Wire Line 476 | 4050 5850 4000 5850 477 | Wire Wire Line 478 | 4000 5750 4050 5750 479 | Text Label 4000 4750 2 50 ~ 0 480 | PMOD_A3 481 | Wire Wire Line 482 | 4000 4650 4050 4650 483 | Wire Wire Line 484 | 4050 4750 4000 4750 485 | Text Label 4000 5850 2 50 ~ 0 486 | PMOD_B10 487 | Text Label 4000 6050 2 50 ~ 0 488 | PMOD_B9 489 | Text Label 4000 6250 2 50 ~ 0 490 | PMOD_B8 491 | Text Label 4000 6450 2 50 ~ 0 492 | PMOD_B7 493 | Wire Wire Line 494 | 4000 6150 4050 6150 495 | Wire Wire Line 496 | 4000 6250 4050 6250 497 | Wire Wire Line 498 | 4000 6350 4050 6350 499 | Wire Wire Line 500 | 4000 6450 4050 6450 501 | Text Label 4000 4850 2 50 ~ 0 502 | PMOD_A9 503 | $Comp 504 | L Memory_RAM:ESP-PSRAM32 U3 505 | U 1 1 608806D4 506 | P 7250 9600 507 | F 0 "U3" H 7400 10200 50 0000 R CNN 508 | F 1 "PSRAM" H 7500 10100 50 0000 R CNN 509 | F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 7250 9000 50 0001 C CNN 510 | F 3 "https://datasheet.lcsc.com/szlcsc/1809140531_Lyontek-Inc-LY68L6400SLIT_C261881.pdf" H 6850 10100 50 0001 C CNN 511 | 1 7250 9600 512 | -1 0 0 -1 513 | $EndComp 514 | Text Label 6800 9300 2 50 ~ 0 515 | ~PSRAM_CS 516 | Text Label 6800 9400 2 50 ~ 0 517 | PSRAM_SCK 518 | Wire Wire Line 519 | 6800 9300 6850 9300 520 | Text Label 6800 9800 2 50 ~ 0 521 | PSRAM_SO 522 | Text Label 6800 9700 2 50 ~ 0 523 | PSRAM_SI 524 | Text Label 6800 9600 2 50 ~ 0 525 | PSRAM_SIO2 526 | Text Label 6800 9500 2 50 ~ 0 527 | PSRAM_SIO3 528 | Wire Wire Line 529 | 6800 9500 6850 9500 530 | Wire Wire Line 531 | 6850 9400 6800 9400 532 | Wire Wire Line 533 | 6800 9600 6850 9600 534 | Wire Wire Line 535 | 6850 9700 6800 9700 536 | Wire Wire Line 537 | 6800 9800 6850 9800 538 | Text Label 4000 1750 2 50 ~ 0 539 | ~PSRAM_CS 540 | Text Label 4000 1350 2 50 ~ 0 541 | PSRAM_SCK 542 | Text Label 4000 1650 2 50 ~ 0 543 | PSRAM_SO 544 | Text Label 4000 1250 2 50 ~ 0 545 | PSRAM_SI 546 | Text Label 4000 1550 2 50 ~ 0 547 | PSRAM_SIO2 548 | Text Label 4000 1450 2 50 ~ 0 549 | PSRAM_SIO3 550 | Wire Wire Line 551 | 1700 1550 1650 1550 552 | Wire Wire Line 553 | 1650 1650 1700 1650 554 | $Comp 555 | L Regulator_Linear:MIC5504-1.2YM5 U4 556 | U 1 1 609659A6 557 | P 9900 9450 558 | F 0 "U4" H 9900 9817 50 0000 C CNN 559 | F 1 "MIC5504-1.2YM5" H 9900 9726 50 0000 C CNN 560 | F 2 "Package_TO_SOT_SMD:SOT-23-5" H 9900 9050 50 0001 C CNN 561 | F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/MIC550X.pdf" H 9650 9700 50 0001 C CNN 562 | 1 9900 9450 563 | 1 0 0 -1 564 | $EndComp 565 | $Comp 566 | L power:+5V #PWR01 567 | U 1 1 60967B39 568 | P 9400 9250 569 | F 0 "#PWR01" H 9400 9100 50 0001 C CNN 570 | F 1 "+5V" H 9415 9423 50 0000 C CNN 571 | F 2 "" H 9400 9250 50 0001 C CNN 572 | F 3 "" H 9400 9250 50 0001 C CNN 573 | 1 9400 9250 574 | 1 0 0 -1 575 | $EndComp 576 | Wire Wire Line 577 | 9400 9250 9400 9350 578 | Wire Wire Line 579 | 9400 9350 9500 9350 580 | $Comp 581 | L Device:C C1 582 | U 1 1 60983241 583 | P 9200 9750 584 | F 0 "C1" H 9400 9800 50 0000 C CNN 585 | F 1 "1uF" H 9400 9700 50 0000 C CNN 586 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 9238 9600 50 0001 C CNN 587 | F 3 "~" H 9200 9750 50 0001 C CNN 588 | F 4 "10v" H 9200 9750 50 0001 C CNN "Voltage" 589 | 1 9200 9750 590 | 1 0 0 -1 591 | $EndComp 592 | Connection ~ 9400 9350 593 | Wire Wire Line 594 | 9500 9550 9400 9550 595 | Wire Wire Line 596 | 9400 9550 9400 9350 597 | $Comp 598 | L power:GND #PWR02 599 | U 1 1 609AE6EB 600 | P 9900 10000 601 | F 0 "#PWR02" H 9900 9750 50 0001 C CNN 602 | F 1 "GND" H 9905 9827 50 0000 C CNN 603 | F 2 "" H 9900 10000 50 0001 C CNN 604 | F 3 "" H 9900 10000 50 0001 C CNN 605 | 1 9900 10000 606 | 1 0 0 -1 607 | $EndComp 608 | Wire Wire Line 609 | 9900 9750 9900 9950 610 | Wire Wire Line 611 | 9900 10000 9900 9950 612 | Connection ~ 9900 9950 613 | $Comp 614 | L power:+1V2 #PWR03 615 | U 1 1 60A1E02A 616 | P 10400 9250 617 | F 0 "#PWR03" H 10400 9100 50 0001 C CNN 618 | F 1 "+1V2" H 10415 9423 50 0000 C CNN 619 | F 2 "" H 10400 9250 50 0001 C CNN 620 | F 3 "" H 10400 9250 50 0001 C CNN 621 | 1 10400 9250 622 | 1 0 0 -1 623 | $EndComp 624 | Wire Wire Line 625 | 10400 9250 10400 9350 626 | Wire Wire Line 627 | 10400 9350 10300 9350 628 | $Comp 629 | L Device:C C2 630 | U 1 1 60A3205C 631 | P 10400 9750 632 | F 0 "C2" H 10600 9800 50 0000 C CNN 633 | F 1 "1uF" H 10600 9700 50 0000 C CNN 634 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 10438 9600 50 0001 C CNN 635 | F 3 "~" H 10400 9750 50 0001 C CNN 636 | F 4 "10v" H 10400 9750 50 0001 C CNN "Voltage" 637 | 1 10400 9750 638 | 1 0 0 -1 639 | $EndComp 640 | Wire Wire Line 641 | 10400 9600 10400 9350 642 | Connection ~ 10400 9350 643 | Wire Wire Line 644 | 10400 9950 9900 9950 645 | Wire Wire Line 646 | 7200 2100 7200 2150 647 | $Comp 648 | L Device:C C11 649 | U 1 1 60A91F45 650 | P 6700 1100 651 | F 0 "C11" H 6750 1200 50 0000 L CNN 652 | F 1 "100nF" H 6750 1000 50 0000 L CNN 653 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 6738 950 50 0001 C CNN 654 | F 3 "~" H 6700 1100 50 0001 C CNN 655 | 1 6700 1100 656 | 1 0 0 -1 657 | $EndComp 658 | $Comp 659 | L power:+1V2 #PWR012 660 | U 1 1 60A94448 661 | P 6700 850 662 | F 0 "#PWR012" H 6700 700 50 0001 C CNN 663 | F 1 "+1V2" H 6715 1023 50 0000 C CNN 664 | F 2 "" H 6700 850 50 0001 C CNN 665 | F 3 "" H 6700 850 50 0001 C CNN 666 | 1 6700 850 667 | 1 0 0 -1 668 | $EndComp 669 | $Comp 670 | L Device:C C12 671 | U 1 1 60A94FEF 672 | P 7050 1100 673 | F 0 "C12" H 7100 1200 50 0000 L CNN 674 | F 1 "100nF" H 7100 1000 50 0000 L CNN 675 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 7088 950 50 0001 C CNN 676 | F 3 "~" H 7050 1100 50 0001 C CNN 677 | 1 7050 1100 678 | 1 0 0 -1 679 | $EndComp 680 | $Comp 681 | L Device:C C13 682 | U 1 1 60AB0849 683 | P 7400 1100 684 | F 0 "C13" H 7450 1200 50 0000 L CNN 685 | F 1 "100nF" H 7450 1000 50 0000 L CNN 686 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 7438 950 50 0001 C CNN 687 | F 3 "~" H 7400 1100 50 0001 C CNN 688 | 1 7400 1100 689 | 1 0 0 -1 690 | $EndComp 691 | $Comp 692 | L Device:C C14 693 | U 1 1 60AB0C88 694 | P 7750 1100 695 | F 0 "C14" H 7800 1200 50 0000 L CNN 696 | F 1 "100nF" H 7800 1000 50 0000 L CNN 697 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 7788 950 50 0001 C CNN 698 | F 3 "~" H 7750 1100 50 0001 C CNN 699 | 1 7750 1100 700 | 1 0 0 -1 701 | $EndComp 702 | Wire Wire Line 703 | 6700 850 6700 900 704 | $Comp 705 | L power:GND #PWR013 706 | U 1 1 60ADC1D7 707 | P 6700 1350 708 | F 0 "#PWR013" H 6700 1100 50 0001 C CNN 709 | F 1 "GND" H 6705 1177 50 0000 C CNN 710 | F 2 "" H 6700 1350 50 0001 C CNN 711 | F 3 "" H 6700 1350 50 0001 C CNN 712 | 1 6700 1350 713 | 1 0 0 -1 714 | $EndComp 715 | Wire Wire Line 716 | 6700 1350 6700 1300 717 | Wire Wire Line 718 | 6700 900 7050 900 719 | Wire Wire Line 720 | 7050 900 7050 950 721 | Connection ~ 6700 900 722 | Wire Wire Line 723 | 6700 900 6700 950 724 | Wire Wire Line 725 | 7050 900 7400 900 726 | Wire Wire Line 727 | 7400 900 7400 950 728 | Connection ~ 7050 900 729 | Wire Wire Line 730 | 7400 900 7750 900 731 | Wire Wire Line 732 | 7750 900 7750 950 733 | Connection ~ 7400 900 734 | Wire Wire Line 735 | 6700 1300 7050 1300 736 | Wire Wire Line 737 | 7050 1300 7050 1250 738 | Connection ~ 6700 1300 739 | Wire Wire Line 740 | 6700 1300 6700 1250 741 | Wire Wire Line 742 | 7050 1300 7400 1300 743 | Wire Wire Line 744 | 7400 1300 7400 1250 745 | Connection ~ 7050 1300 746 | Wire Wire Line 747 | 7400 1300 7750 1300 748 | Wire Wire Line 749 | 7750 1300 7750 1250 750 | Connection ~ 7400 1300 751 | $Comp 752 | L Device:C C4 753 | U 1 1 60B841A9 754 | P 2750 1000 755 | F 0 "C4" H 2800 1100 50 0000 L CNN 756 | F 1 "100nF" H 2800 900 50 0000 L CNN 757 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 2788 850 50 0001 C CNN 758 | F 3 "~" H 2750 1000 50 0001 C CNN 759 | 1 2750 1000 760 | 1 0 0 -1 761 | $EndComp 762 | $Comp 763 | L Device:C C6 764 | U 1 1 60B864E1 765 | P 3100 1000 766 | F 0 "C6" H 3150 1100 50 0000 L CNN 767 | F 1 "100nF" H 3150 900 50 0000 L CNN 768 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 3138 850 50 0001 C CNN 769 | F 3 "~" H 3100 1000 50 0001 C CNN 770 | 1 3100 1000 771 | 1 0 0 -1 772 | $EndComp 773 | $Comp 774 | L power:+3V3 #PWR05 775 | U 1 1 60B96AE3 776 | P 2200 750 777 | F 0 "#PWR05" H 2200 600 50 0001 C CNN 778 | F 1 "+3V3" H 2215 923 50 0000 C CNN 779 | F 2 "" H 2200 750 50 0001 C CNN 780 | F 3 "" H 2200 750 50 0001 C CNN 781 | 1 2200 750 782 | 1 0 0 -1 783 | $EndComp 784 | Wire Wire Line 785 | 2200 750 2200 800 786 | Wire Wire Line 787 | 2200 800 2750 800 788 | Wire Wire Line 789 | 2750 800 2750 850 790 | Connection ~ 2200 800 791 | Wire Wire Line 792 | 2200 800 2200 850 793 | Wire Wire Line 794 | 2750 800 3100 800 795 | Wire Wire Line 796 | 3100 800 3100 850 797 | Connection ~ 2750 800 798 | $Comp 799 | L power:GND #PWR07 800 | U 1 1 60BC6D14 801 | P 3100 1250 802 | F 0 "#PWR07" H 3100 1000 50 0001 C CNN 803 | F 1 "GND" H 3105 1077 50 0000 C CNN 804 | F 2 "" H 3100 1250 50 0001 C CNN 805 | F 3 "" H 3100 1250 50 0001 C CNN 806 | 1 3100 1250 807 | 1 0 0 -1 808 | $EndComp 809 | Wire Wire Line 810 | 3100 1150 3100 1200 811 | Wire Wire Line 812 | 3100 1200 2750 1200 813 | Wire Wire Line 814 | 2750 1200 2750 1150 815 | Connection ~ 3100 1200 816 | Wire Wire Line 817 | 3100 1200 3100 1250 818 | $Comp 819 | L Device:C C8 820 | U 1 1 60BE9288 821 | P 5100 1000 822 | F 0 "C8" H 5150 1100 50 0000 L CNN 823 | F 1 "100nF" H 5150 900 50 0000 L CNN 824 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 5138 850 50 0001 C CNN 825 | F 3 "~" H 5100 1000 50 0001 C CNN 826 | 1 5100 1000 827 | 1 0 0 -1 828 | $EndComp 829 | $Comp 830 | L Device:C C10 831 | U 1 1 60BE928E 832 | P 5450 1000 833 | F 0 "C10" H 5500 1100 50 0000 L CNN 834 | F 1 "100nF" H 5500 900 50 0000 L CNN 835 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 5488 850 50 0001 C CNN 836 | F 3 "~" H 5450 1000 50 0001 C CNN 837 | 1 5450 1000 838 | 1 0 0 -1 839 | $EndComp 840 | Wire Wire Line 841 | 4550 800 5100 800 842 | Wire Wire Line 843 | 5100 800 5100 850 844 | Wire Wire Line 845 | 5100 800 5450 800 846 | Wire Wire Line 847 | 5450 800 5450 850 848 | Connection ~ 5100 800 849 | $Comp 850 | L power:GND #PWR011 851 | U 1 1 60BE9299 852 | P 5450 1250 853 | F 0 "#PWR011" H 5450 1000 50 0001 C CNN 854 | F 1 "GND" H 5455 1077 50 0000 C CNN 855 | F 2 "" H 5450 1250 50 0001 C CNN 856 | F 3 "" H 5450 1250 50 0001 C CNN 857 | 1 5450 1250 858 | 1 0 0 -1 859 | $EndComp 860 | Wire Wire Line 861 | 5450 1150 5450 1200 862 | Wire Wire Line 863 | 5450 1200 5100 1200 864 | Wire Wire Line 865 | 5100 1200 5100 1150 866 | Connection ~ 5450 1200 867 | Wire Wire Line 868 | 5450 1200 5450 1250 869 | $Comp 870 | L power:+3V3 #PWR09 871 | U 1 1 60BFAB0C 872 | P 4550 750 873 | F 0 "#PWR09" H 4550 600 50 0001 C CNN 874 | F 1 "+3V3" H 4565 923 50 0000 C CNN 875 | F 2 "" H 4550 750 50 0001 C CNN 876 | F 3 "" H 4550 750 50 0001 C CNN 877 | 1 4550 750 878 | 1 0 0 -1 879 | $EndComp 880 | Wire Wire Line 881 | 4550 750 4550 800 882 | Connection ~ 4550 800 883 | Wire Wire Line 884 | 4550 800 4550 850 885 | $Comp 886 | L power:+3V3 #PWR04 887 | U 1 1 60C1F025 888 | P 2200 4050 889 | F 0 "#PWR04" H 2200 3900 50 0001 C CNN 890 | F 1 "+3V3" H 2215 4223 50 0000 C CNN 891 | F 2 "" H 2200 4050 50 0001 C CNN 892 | F 3 "" H 2200 4050 50 0001 C CNN 893 | 1 2200 4050 894 | 1 0 0 -1 895 | $EndComp 896 | Wire Wire Line 897 | 2200 4050 2200 4100 898 | $Comp 899 | L Device:C C3 900 | U 1 1 60C32A4C 901 | P 2750 4300 902 | F 0 "C3" H 2800 4400 50 0000 L CNN 903 | F 1 "100nF" H 2800 4200 50 0000 L CNN 904 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 2788 4150 50 0001 C CNN 905 | F 3 "~" H 2750 4300 50 0001 C CNN 906 | 1 2750 4300 907 | 1 0 0 -1 908 | $EndComp 909 | $Comp 910 | L Device:C C5 911 | U 1 1 60C32A52 912 | P 3100 4300 913 | F 0 "C5" H 3150 4400 50 0000 L CNN 914 | F 1 "100nF" H 3150 4200 50 0000 L CNN 915 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 3138 4150 50 0001 C CNN 916 | F 3 "~" H 3100 4300 50 0001 C CNN 917 | 1 3100 4300 918 | 1 0 0 -1 919 | $EndComp 920 | Wire Wire Line 921 | 2200 4100 2750 4100 922 | Wire Wire Line 923 | 2750 4100 2750 4150 924 | Wire Wire Line 925 | 2750 4100 3100 4100 926 | Wire Wire Line 927 | 3100 4100 3100 4150 928 | Connection ~ 2750 4100 929 | $Comp 930 | L power:GND #PWR06 931 | U 1 1 60C32A5D 932 | P 3100 4550 933 | F 0 "#PWR06" H 3100 4300 50 0001 C CNN 934 | F 1 "GND" H 3105 4377 50 0000 C CNN 935 | F 2 "" H 3100 4550 50 0001 C CNN 936 | F 3 "" H 3100 4550 50 0001 C CNN 937 | 1 3100 4550 938 | 1 0 0 -1 939 | $EndComp 940 | Wire Wire Line 941 | 3100 4450 3100 4500 942 | Wire Wire Line 943 | 3100 4500 2750 4500 944 | Wire Wire Line 945 | 2750 4500 2750 4450 946 | Connection ~ 3100 4500 947 | Wire Wire Line 948 | 3100 4500 3100 4550 949 | $Comp 950 | L power:+3V3 #PWR08 951 | U 1 1 60C44E0A 952 | P 4550 4050 953 | F 0 "#PWR08" H 4550 3900 50 0001 C CNN 954 | F 1 "+3V3" H 4565 4223 50 0000 C CNN 955 | F 2 "" H 4550 4050 50 0001 C CNN 956 | F 3 "" H 4550 4050 50 0001 C CNN 957 | 1 4550 4050 958 | 1 0 0 -1 959 | $EndComp 960 | Wire Wire Line 961 | 4550 4050 4550 4100 962 | $Comp 963 | L Device:C C7 964 | U 1 1 60C58E23 965 | P 5100 4300 966 | F 0 "C7" H 5150 4400 50 0000 L CNN 967 | F 1 "100nF" H 5150 4200 50 0000 L CNN 968 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 5138 4150 50 0001 C CNN 969 | F 3 "~" H 5100 4300 50 0001 C CNN 970 | 1 5100 4300 971 | 1 0 0 -1 972 | $EndComp 973 | $Comp 974 | L Device:C C9 975 | U 1 1 60C58E29 976 | P 5450 4300 977 | F 0 "C9" H 5500 4400 50 0000 L CNN 978 | F 1 "100nF" H 5500 4200 50 0000 L CNN 979 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 5488 4150 50 0001 C CNN 980 | F 3 "~" H 5450 4300 50 0001 C CNN 981 | 1 5450 4300 982 | 1 0 0 -1 983 | $EndComp 984 | Wire Wire Line 985 | 4550 4100 5100 4100 986 | Wire Wire Line 987 | 5100 4100 5100 4150 988 | Wire Wire Line 989 | 5100 4100 5450 4100 990 | Wire Wire Line 991 | 5450 4100 5450 4150 992 | Connection ~ 5100 4100 993 | $Comp 994 | L power:GND #PWR010 995 | U 1 1 60C58E34 996 | P 5450 4550 997 | F 0 "#PWR010" H 5450 4300 50 0001 C CNN 998 | F 1 "GND" H 5455 4377 50 0000 C CNN 999 | F 2 "" H 5450 4550 50 0001 C CNN 1000 | F 3 "" H 5450 4550 50 0001 C CNN 1001 | 1 5450 4550 1002 | 1 0 0 -1 1003 | $EndComp 1004 | Wire Wire Line 1005 | 5450 4450 5450 4500 1006 | Wire Wire Line 1007 | 5450 4500 5100 4500 1008 | Wire Wire Line 1009 | 5100 4500 5100 4450 1010 | Connection ~ 5450 4500 1011 | Wire Wire Line 1012 | 5450 4500 5450 4550 1013 | $Comp 1014 | L Device:R R1 1015 | U 1 1 60C6CE21 1016 | P 9000 1100 1017 | F 0 "R1" H 9070 1146 50 0000 L CNN 1018 | F 1 "100R" H 9070 1055 50 0000 L CNN 1019 | F 2 "Resistor_SMD:R_0603_1608Metric" V 8930 1100 50 0001 C CNN 1020 | F 3 "~" H 9000 1100 50 0001 C CNN 1021 | 1 9000 1100 1022 | 1 0 0 -1 1023 | $EndComp 1024 | $Comp 1025 | L Device:C C15 1026 | U 1 1 60C6D561 1027 | P 9000 1500 1028 | F 0 "C15" H 9050 1600 50 0000 L CNN 1029 | F 1 "100nF" H 9050 1400 50 0000 L CNN 1030 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 9038 1350 50 0001 C CNN 1031 | F 3 "~" H 9000 1500 50 0001 C CNN 1032 | 1 9000 1500 1033 | 1 0 0 -1 1034 | $EndComp 1035 | $Comp 1036 | L Device:C C16 1037 | U 1 1 60C6ED1F 1038 | P 9350 1500 1039 | F 0 "C16" H 9400 1600 50 0000 L CNN 1040 | F 1 "10uF" H 9400 1400 50 0000 L CNN 1041 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 9388 1350 50 0001 C CNN 1042 | F 3 "~" H 9350 1500 50 0001 C CNN 1043 | 1 9350 1500 1044 | 1 0 0 -1 1045 | $EndComp 1046 | $Comp 1047 | L power:+1V2 #PWR014 1048 | U 1 1 60C702A4 1049 | P 9000 900 1050 | F 0 "#PWR014" H 9000 750 50 0001 C CNN 1051 | F 1 "+1V2" H 9015 1073 50 0000 C CNN 1052 | F 2 "" H 9000 900 50 0001 C CNN 1053 | F 3 "" H 9000 900 50 0001 C CNN 1054 | 1 9000 900 1055 | 1 0 0 -1 1056 | $EndComp 1057 | Wire Wire Line 1058 | 9000 900 9000 950 1059 | Wire Wire Line 1060 | 9000 1250 9000 1300 1061 | Connection ~ 9000 1300 1062 | Wire Wire Line 1063 | 9000 1300 9000 1350 1064 | Text Label 9600 1100 0 50 ~ 0 1065 | FPGA_VCCPLL 1066 | Wire Wire Line 1067 | 9350 1700 9350 1650 1068 | Text Label 7550 2000 0 50 ~ 0 1069 | FPGA_VCCPLL 1070 | $Comp 1071 | L power:+1V2 #PWR0115 1072 | U 1 1 60A63877 1073 | P 7200 2100 1074 | F 0 "#PWR0115" H 7200 1950 50 0001 C CNN 1075 | F 1 "+1V2" V 7200 2300 50 0000 C CNN 1076 | F 2 "" H 7200 2100 50 0001 C CNN 1077 | F 3 "" H 7200 2100 50 0001 C CNN 1078 | 1 7200 2100 1079 | 1 0 0 -1 1080 | $EndComp 1081 | Wire Wire Line 1082 | 9000 1300 9350 1300 1083 | Wire Wire Line 1084 | 9350 1350 9350 1300 1085 | Connection ~ 9350 1300 1086 | Wire Wire Line 1087 | 9350 1300 9550 1300 1088 | Wire Wire Line 1089 | 7300 2100 7300 2150 1090 | NoConn ~ 7100 2150 1091 | $Comp 1092 | L power:+3V3 #PWR0119 1093 | U 1 1 60E3B2AA 1094 | P 6900 1950 1095 | F 0 "#PWR0119" H 6900 1800 50 0001 C CNN 1096 | F 1 "+3V3" V 6900 2150 50 0000 C CNN 1097 | F 2 "" H 6900 1950 50 0001 C CNN 1098 | F 3 "" H 6900 1950 50 0001 C CNN 1099 | 1 6900 1950 1100 | 1 0 0 -1 1101 | $EndComp 1102 | Wire Wire Line 1103 | 6900 1950 6900 2000 1104 | Text Label 7600 3650 0 50 ~ 0 1105 | FPGA_GNDPLL 1106 | Wire Wire Line 1107 | 7500 3550 7500 3650 1108 | Text Label 8850 1700 2 50 ~ 0 1109 | FPGA_GNDPLL 1110 | Wire Wire Line 1111 | 8850 1700 9000 1700 1112 | Wire Wire Line 1113 | 9000 1650 9000 1700 1114 | Connection ~ 9000 1700 1115 | Wire Wire Line 1116 | 9000 1700 9350 1700 1117 | $Comp 1118 | L Device:C C17 1119 | U 1 1 60EC3E61 1120 | P 6450 2150 1121 | F 0 "C17" H 6200 2150 50 0000 L CNN 1122 | F 1 "100nF" H 6150 2050 50 0000 L CNN 1123 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 6488 2000 50 0001 C CNN 1124 | F 3 "~" H 6450 2150 50 0001 C CNN 1125 | 1 6450 2150 1126 | 1 0 0 -1 1127 | $EndComp 1128 | Wire Wire Line 1129 | 6450 2000 6900 2000 1130 | Connection ~ 6900 2000 1131 | Wire Wire Line 1132 | 6900 2000 6900 2150 1133 | $Comp 1134 | L power:GND #PWR0120 1135 | U 1 1 60EDADF6 1136 | P 6450 2300 1137 | F 0 "#PWR0120" H 6450 2050 50 0001 C CNN 1138 | F 1 "GND" H 6455 2127 50 0000 C CNN 1139 | F 2 "" H 6450 2300 50 0001 C CNN 1140 | F 3 "" H 6450 2300 50 0001 C CNN 1141 | 1 6450 2300 1142 | 1 0 0 -1 1143 | $EndComp 1144 | $Comp 1145 | L power:GND #PWR0121 1146 | U 1 1 60F9D2EA 1147 | P 7350 10150 1148 | F 0 "#PWR0121" H 7350 9900 50 0001 C CNN 1149 | F 1 "GND" H 7355 9977 50 0000 C CNN 1150 | F 2 "" H 7350 10150 50 0001 C CNN 1151 | F 3 "" H 7350 10150 50 0001 C CNN 1152 | 1 7350 10150 1153 | 1 0 0 -1 1154 | $EndComp 1155 | Wire Wire Line 1156 | 7350 10100 7350 10150 1157 | $Comp 1158 | L power:+3V3 #PWR0122 1159 | U 1 1 60FB42BE 1160 | P 7350 9000 1161 | F 0 "#PWR0122" H 7350 8850 50 0001 C CNN 1162 | F 1 "+3V3" H 7365 9173 50 0000 C CNN 1163 | F 2 "" H 7350 9000 50 0001 C CNN 1164 | F 3 "" H 7350 9000 50 0001 C CNN 1165 | 1 7350 9000 1166 | 1 0 0 -1 1167 | $EndComp 1168 | Wire Wire Line 1169 | 7350 9000 7350 9050 1170 | $Comp 1171 | L Device:C C18 1172 | U 1 1 60FF4CA9 1173 | P 7750 9200 1174 | F 0 "C18" H 7900 9250 50 0000 L CNN 1175 | F 1 "100nF" H 7850 9150 50 0000 L CNN 1176 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 7788 9050 50 0001 C CNN 1177 | F 3 "~" H 7750 9200 50 0001 C CNN 1178 | 1 7750 9200 1179 | 1 0 0 -1 1180 | $EndComp 1181 | Wire Wire Line 1182 | 7350 9050 7750 9050 1183 | Connection ~ 7350 9050 1184 | Wire Wire Line 1185 | 7350 9050 7350 9100 1186 | $Comp 1187 | L power:GND #PWR0123 1188 | U 1 1 61022944 1189 | P 7750 9350 1190 | F 0 "#PWR0123" H 7750 9100 50 0001 C CNN 1191 | F 1 "GND" H 7755 9177 50 0000 C CNN 1192 | F 2 "" H 7750 9350 50 0001 C CNN 1193 | F 3 "" H 7750 9350 50 0001 C CNN 1194 | 1 7750 9350 1195 | 1 0 0 -1 1196 | $EndComp 1197 | $Comp 1198 | L Device:C C19 1199 | U 1 1 610655C8 1200 | P 13300 6250 1201 | F 0 "C19" H 13000 6300 50 0000 L CNN 1202 | F 1 "10uF" H 12950 6200 50 0000 L CNN 1203 | F 2 "Capacitor_SMD:C_0603_1608Metric" H 13338 6100 50 0001 C CNN 1204 | F 3 "~" H 13300 6250 50 0001 C CNN 1205 | 1 13300 6250 1206 | 1 0 0 -1 1207 | $EndComp 1208 | Wire Wire Line 1209 | 13300 6100 13300 6050 1210 | Wire Wire Line 1211 | 13300 6050 13900 6050 1212 | Connection ~ 13900 6050 1213 | Wire Wire Line 1214 | 13900 6050 13900 6000 1215 | $Comp 1216 | L power:GND #PWR0124 1217 | U 1 1 61093DBE 1218 | P 13300 6400 1219 | F 0 "#PWR0124" H 13300 6150 50 0001 C CNN 1220 | F 1 "GND" H 13305 6227 50 0000 C CNN 1221 | F 2 "" H 13300 6400 50 0001 C CNN 1222 | F 3 "" H 13300 6400 50 0001 C CNN 1223 | 1 13300 6400 1224 | 1 0 0 -1 1225 | $EndComp 1226 | Connection ~ 2200 4100 1227 | Wire Wire Line 1228 | 2200 4100 2200 4150 1229 | Connection ~ 4550 4100 1230 | Wire Wire Line 1231 | 4550 4100 4550 4150 1232 | $Comp 1233 | L power:GND #PWR0125 1234 | U 1 1 6116368E 1235 | P 1950 10550 1236 | F 0 "#PWR0125" H 1950 10300 50 0001 C CNN 1237 | F 1 "GND" H 1955 10377 50 0000 C CNN 1238 | F 2 "" H 1950 10550 50 0001 C CNN 1239 | F 3 "" H 1950 10550 50 0001 C CNN 1240 | 1 1950 10550 1241 | 1 0 0 -1 1242 | $EndComp 1243 | Connection ~ 1950 10500 1244 | Wire Wire Line 1245 | 1950 10550 1950 10500 1246 | $Comp 1247 | L power:+3V3 #PWR0126 1248 | U 1 1 61163696 1249 | P 1950 9450 1250 | F 0 "#PWR0126" H 1950 9300 50 0001 C CNN 1251 | F 1 "+3V3" H 1965 9623 50 0000 C CNN 1252 | F 2 "" H 1950 9450 50 0001 C CNN 1253 | F 3 "" H 1950 9450 50 0001 C CNN 1254 | 1 1950 9450 1255 | 1 0 0 -1 1256 | $EndComp 1257 | Wire Wire Line 1258 | 1950 9500 1650 9500 1259 | Wire Wire Line 1260 | 1650 9500 1650 10300 1261 | Connection ~ 1950 9500 1262 | Wire Wire Line 1263 | 1950 9450 1950 9500 1264 | Wire Wire Line 1265 | 2250 10300 2250 9500 1266 | Wire Wire Line 1267 | 1950 9500 2250 9500 1268 | Wire Wire Line 1269 | 1600 10500 1950 10500 1270 | Text Label 1150 9800 2 50 ~ 0 1271 | PMOD_C1 1272 | Wire Wire Line 1273 | 1550 9800 1700 9800 1274 | Text Label 1150 9900 2 50 ~ 0 1275 | PMOD_C2 1276 | Text Label 1150 10000 2 50 ~ 0 1277 | PMOD_C3 1278 | Text Label 1150 10100 2 50 ~ 0 1279 | PMOD_C4 1280 | Text Label 2750 10100 0 50 ~ 0 1281 | PMOD_C10 1282 | Text Label 2750 10000 0 50 ~ 0 1283 | PMOD_C9 1284 | Text Label 2750 9900 0 50 ~ 0 1285 | PMOD_C8 1286 | Text Label 2750 9800 0 50 ~ 0 1287 | PMOD_C7 1288 | Wire Wire Line 1289 | 2350 9800 2200 9800 1290 | Wire Wire Line 1291 | 2200 9900 2350 9900 1292 | Wire Wire Line 1293 | 2350 10000 2200 10000 1294 | Wire Wire Line 1295 | 2200 10100 2350 10100 1296 | Wire Wire Line 1297 | 1700 10100 1550 10100 1298 | Wire Wire Line 1299 | 1550 10000 1700 10000 1300 | Wire Wire Line 1301 | 1700 9900 1550 9900 1302 | Wire Wire Line 1303 | 2750 9800 2650 9800 1304 | Wire Wire Line 1305 | 2650 9900 2750 9900 1306 | Wire Wire Line 1307 | 2750 10000 2650 10000 1308 | Wire Wire Line 1309 | 2650 10100 2750 10100 1310 | $Comp 1311 | L Device:R_Pack04_Split RN5 1312 | U 1 1 611636C4 1313 | P 1400 10100 1314 | F 0 "RN5" V 1400 10100 50 0000 C CNN 1315 | F 1 "33R" V 1000 10100 50 0000 C CNN 1316 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 1675 10100 50 0001 C CNN 1317 | F 3 "~" H 1400 10100 50 0001 C CNN 1318 | 1 1400 10100 1319 | 0 -1 1 0 1320 | $EndComp 1321 | Wire Wire Line 1322 | 1150 10100 1250 10100 1323 | Wire Wire Line 1324 | 1250 10000 1150 10000 1325 | Wire Wire Line 1326 | 1150 9900 1250 9900 1327 | Wire Wire Line 1328 | 1250 9800 1150 9800 1329 | $Comp 1330 | L Connector_Generic:Conn_02x06_Top_Bottom J5 1331 | U 1 1 611636CE 1332 | P 4450 10000 1333 | F 0 "J5" H 4500 10417 50 0000 C CNN 1334 | F 1 "PMOD_D" H 4500 10326 50 0000 C CNN 1335 | F 2 "PMOD:PMOD_Double_Mirrored" H 4450 10000 50 0001 C CNN 1336 | F 3 "~" H 4450 10000 50 0001 C CNN 1337 | 1 4450 10000 1338 | 1 0 0 -1 1339 | $EndComp 1340 | $Comp 1341 | L power:GND #PWR0127 1342 | U 1 1 611636D4 1343 | P 4500 10550 1344 | F 0 "#PWR0127" H 4500 10300 50 0001 C CNN 1345 | F 1 "GND" H 4505 10377 50 0000 C CNN 1346 | F 2 "" H 4500 10550 50 0001 C CNN 1347 | F 3 "" H 4500 10550 50 0001 C CNN 1348 | 1 4500 10550 1349 | 1 0 0 -1 1350 | $EndComp 1351 | Connection ~ 4500 10500 1352 | Wire Wire Line 1353 | 4500 10550 4500 10500 1354 | $Comp 1355 | L power:+3V3 #PWR0128 1356 | U 1 1 611636DC 1357 | P 4500 9450 1358 | F 0 "#PWR0128" H 4500 9300 50 0001 C CNN 1359 | F 1 "+3V3" H 4515 9623 50 0000 C CNN 1360 | F 2 "" H 4500 9450 50 0001 C CNN 1361 | F 3 "" H 4500 9450 50 0001 C CNN 1362 | 1 4500 9450 1363 | 1 0 0 -1 1364 | $EndComp 1365 | Wire Wire Line 1366 | 4500 9500 4200 9500 1367 | Wire Wire Line 1368 | 4200 9500 4200 10300 1369 | Connection ~ 4500 9500 1370 | Wire Wire Line 1371 | 4500 9450 4500 9500 1372 | Wire Wire Line 1373 | 4800 10300 4800 9500 1374 | Wire Wire Line 1375 | 4500 9500 4800 9500 1376 | Wire Wire Line 1377 | 4500 10500 4850 10500 1378 | Text Label 3700 9800 2 50 ~ 0 1379 | PMOD_D1 1380 | Text Label 3700 9900 2 50 ~ 0 1381 | PMOD_D2 1382 | Text Label 3700 10000 2 50 ~ 0 1383 | PMOD_D3 1384 | Text Label 3700 10100 2 50 ~ 0 1385 | PMOD_D4 1386 | Text Label 5300 10100 0 50 ~ 0 1387 | PMOD_D10 1388 | Text Label 5300 10000 0 50 ~ 0 1389 | PMOD_D9 1390 | Text Label 5300 9900 0 50 ~ 0 1391 | PMOD_D8 1392 | Wire Wire Line 1393 | 4900 9800 4750 9800 1394 | Wire Wire Line 1395 | 4750 9900 4900 9900 1396 | Wire Wire Line 1397 | 4900 10000 4750 10000 1398 | Wire Wire Line 1399 | 4750 10100 4900 10100 1400 | Wire Wire Line 1401 | 4250 10100 4100 10100 1402 | Wire Wire Line 1403 | 4100 10000 4250 10000 1404 | Wire Wire Line 1405 | 4250 9900 4100 9900 1406 | Wire Wire Line 1407 | 5300 9800 5200 9800 1408 | Wire Wire Line 1409 | 5200 9900 5300 9900 1410 | Wire Wire Line 1411 | 5300 10000 5200 10000 1412 | Wire Wire Line 1413 | 5200 10100 5300 10100 1414 | Wire Wire Line 1415 | 3700 10100 3800 10100 1416 | Wire Wire Line 1417 | 3800 10000 3700 10000 1418 | Wire Wire Line 1419 | 3700 9900 3800 9900 1420 | Wire Wire Line 1421 | 1650 2150 1700 2150 1422 | Wire Wire Line 1423 | 1650 2050 1700 2050 1424 | Wire Wire Line 1425 | 1650 1950 1700 1950 1426 | Wire Wire Line 1427 | 1650 1850 1700 1850 1428 | Wire Wire Line 1429 | 1700 1750 1650 1750 1430 | Wire Wire Line 1431 | 1650 3050 1700 3050 1432 | Wire Wire Line 1433 | 1700 2950 1650 2950 1434 | Wire Wire Line 1435 | 1650 2850 1700 2850 1436 | Wire Wire Line 1437 | 1700 2750 1650 2750 1438 | $Comp 1439 | L power:GND #PWR0129 1440 | U 1 1 614D4582 1441 | P 12200 2100 1442 | F 0 "#PWR0129" H 12200 1850 50 0001 C CNN 1443 | F 1 "GND" H 12205 1927 50 0000 C CNN 1444 | F 2 "" H 12200 2100 50 0001 C CNN 1445 | F 3 "" H 12200 2100 50 0001 C CNN 1446 | 1 12200 2100 1447 | 1 0 0 -1 1448 | $EndComp 1449 | Wire Wire Line 1450 | 12200 2100 12200 2050 1451 | Wire Wire Line 1452 | 12200 2050 12250 2050 1453 | Text Label 12200 1950 2 50 ~ 0 1454 | UART_RX 1455 | Text Label 12200 1850 2 50 ~ 0 1456 | UART_TX 1457 | Wire Wire Line 1458 | 12200 1850 12250 1850 1459 | Wire Wire Line 1460 | 12250 1950 12200 1950 1461 | $Comp 1462 | L Connector:Conn_01x03_Male J6 1463 | U 1 1 61483541 1464 | P 12450 1950 1465 | F 0 "J6" H 12600 1600 50 0000 R CNN 1466 | F 1 "UART" H 12650 1700 50 0000 R CNN 1467 | F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 12450 1950 50 0001 C CNN 1468 | F 3 "~" H 12450 1950 50 0001 C CNN 1469 | 1 12450 1950 1470 | -1 0 0 1 1471 | $EndComp 1472 | $Comp 1473 | L Connector:Conn_01x03_Male J7 1474 | U 1 1 615A7301 1475 | P 13700 1950 1476 | F 0 "J7" H 13900 1600 50 0000 R CNN 1477 | F 1 "RP_SWD" H 14000 1700 50 0000 R CNN 1478 | F 2 "Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical" H 13700 1950 50 0001 C CNN 1479 | F 3 "~" H 13700 1950 50 0001 C CNN 1480 | 1 13700 1950 1481 | -1 0 0 1 1482 | $EndComp 1483 | $Comp 1484 | L power:GND #PWR0130 1485 | U 1 1 615A813E 1486 | P 13450 2100 1487 | F 0 "#PWR0130" H 13450 1850 50 0001 C CNN 1488 | F 1 "GND" H 13455 1927 50 0000 C CNN 1489 | F 2 "" H 13450 2100 50 0001 C CNN 1490 | F 3 "" H 13450 2100 50 0001 C CNN 1491 | 1 13450 2100 1492 | 1 0 0 -1 1493 | $EndComp 1494 | Wire Wire Line 1495 | 13450 2100 13450 2050 1496 | Wire Wire Line 1497 | 13450 2050 13500 2050 1498 | Text Label 13200 5250 0 50 ~ 0 1499 | RP_SWDIO 1500 | Text Label 13200 5350 0 50 ~ 0 1501 | RP_SWCLK 1502 | Wire Wire Line 1503 | 13200 5350 12900 5350 1504 | Wire Wire Line 1505 | 12900 5200 12900 5350 1506 | Wire Wire Line 1507 | 13100 5200 13100 5250 1508 | Wire Wire Line 1509 | 13100 5250 13200 5250 1510 | Text Label 13450 1850 2 50 ~ 0 1511 | RP_SWCLK 1512 | Text Label 13450 1950 2 50 ~ 0 1513 | RP_SWDIO 1514 | Wire Wire Line 1515 | 13450 1950 13500 1950 1516 | Wire Wire Line 1517 | 13500 1850 13450 1850 1518 | $Comp 1519 | L Switch:SW_SPST SW2 1520 | U 1 1 6180F3D6 1521 | P 7750 5100 1522 | F 0 "SW2" H 7750 5335 50 0000 C CNN 1523 | F 1 "BTN_A" H 7750 5244 50 0000 C CNN 1524 | F 2 "Button_Switch_SMD:SW_SPST_PTS645" H 7750 5100 50 0001 C CNN 1525 | F 3 "~" H 7750 5100 50 0001 C CNN 1526 | 1 7750 5100 1527 | 1 0 0 -1 1528 | $EndComp 1529 | $Comp 1530 | L power:GND #PWR0131 1531 | U 1 1 61812C20 1532 | P 8050 5200 1533 | F 0 "#PWR0131" H 8050 4950 50 0001 C CNN 1534 | F 1 "GND" H 8055 5027 50 0000 C CNN 1535 | F 2 "" H 8050 5200 50 0001 C CNN 1536 | F 3 "" H 8050 5200 50 0001 C CNN 1537 | 1 8050 5200 1538 | 1 0 0 -1 1539 | $EndComp 1540 | Wire Wire Line 1541 | 8050 5100 7950 5100 1542 | Text Label 7300 5100 2 50 ~ 0 1543 | BTN_A 1544 | Wire Wire Line 1545 | 7300 5100 7450 5100 1546 | Text Label 4000 6850 2 50 ~ 0 1547 | BTN_A 1548 | Text Label 4000 6750 2 50 ~ 0 1549 | BTN_B 1550 | $Comp 1551 | L Device:R R2 1552 | U 1 1 618BE8BB 1553 | P 7450 4850 1554 | F 0 "R2" H 7250 4900 50 0000 L CNN 1555 | F 1 "10k" H 7250 4800 50 0000 L CNN 1556 | F 2 "Resistor_SMD:R_0603_1608Metric" V 7380 4850 50 0001 C CNN 1557 | F 3 "~" H 7450 4850 50 0001 C CNN 1558 | 1 7450 4850 1559 | 1 0 0 -1 1560 | $EndComp 1561 | Wire Wire Line 1562 | 7450 5000 7450 5100 1563 | Connection ~ 7450 5100 1564 | Wire Wire Line 1565 | 7450 5100 7550 5100 1566 | $Comp 1567 | L power:+3V3 #PWR0132 1568 | U 1 1 619167E8 1569 | P 7450 4700 1570 | F 0 "#PWR0132" H 7450 4550 50 0001 C CNN 1571 | F 1 "+3V3" H 7465 4873 50 0000 C CNN 1572 | F 2 "" H 7450 4700 50 0001 C CNN 1573 | F 3 "" H 7450 4700 50 0001 C CNN 1574 | 1 7450 4700 1575 | 1 0 0 -1 1576 | $EndComp 1577 | Wire Wire Line 1578 | 8050 5100 8050 5200 1579 | $Comp 1580 | L Switch:SW_SPST SW3 1581 | U 1 1 61A3F683 1582 | P 9000 5100 1583 | F 0 "SW3" H 9000 5335 50 0000 C CNN 1584 | F 1 " BTN_B" H 9000 5244 50 0000 C CNN 1585 | F 2 "Button_Switch_SMD:SW_SPST_PTS645" H 9000 5100 50 0001 C CNN 1586 | F 3 "~" H 9000 5100 50 0001 C CNN 1587 | 1 9000 5100 1588 | 1 0 0 -1 1589 | $EndComp 1590 | $Comp 1591 | L power:GND #PWR0133 1592 | U 1 1 61A3F689 1593 | P 9300 5200 1594 | F 0 "#PWR0133" H 9300 4950 50 0001 C CNN 1595 | F 1 "GND" H 9305 5027 50 0000 C CNN 1596 | F 2 "" H 9300 5200 50 0001 C CNN 1597 | F 3 "" H 9300 5200 50 0001 C CNN 1598 | 1 9300 5200 1599 | 1 0 0 -1 1600 | $EndComp 1601 | Wire Wire Line 1602 | 9300 5100 9200 5100 1603 | Text Label 8550 5100 2 50 ~ 0 1604 | BTN_B 1605 | Wire Wire Line 1606 | 8550 5100 8700 5100 1607 | $Comp 1608 | L Device:R R3 1609 | U 1 1 61A3F692 1610 | P 8700 4850 1611 | F 0 "R3" H 8500 4900 50 0000 L CNN 1612 | F 1 "10k" H 8500 4800 50 0000 L CNN 1613 | F 2 "Resistor_SMD:R_0603_1608Metric" V 8630 4850 50 0001 C CNN 1614 | F 3 "~" H 8700 4850 50 0001 C CNN 1615 | 1 8700 4850 1616 | 1 0 0 -1 1617 | $EndComp 1618 | Wire Wire Line 1619 | 8700 5000 8700 5100 1620 | Connection ~ 8700 5100 1621 | Wire Wire Line 1622 | 8700 5100 8800 5100 1623 | $Comp 1624 | L power:+3V3 #PWR0134 1625 | U 1 1 61A3F69B 1626 | P 8700 4700 1627 | F 0 "#PWR0134" H 8700 4550 50 0001 C CNN 1628 | F 1 "+3V3" H 8715 4873 50 0000 C CNN 1629 | F 2 "" H 8700 4700 50 0001 C CNN 1630 | F 3 "" H 8700 4700 50 0001 C CNN 1631 | 1 8700 4700 1632 | 1 0 0 -1 1633 | $EndComp 1634 | Wire Wire Line 1635 | 9300 5100 9300 5200 1636 | Text Notes 12200 10950 0 79 Italic 16 1637 | PicoHX 1638 | $Comp 1639 | L Device:LED D0 1640 | U 1 1 61C1D34A 1641 | P 9800 6400 1642 | F 0 "D0" V 9900 6350 50 0000 R CNN 1643 | F 1 "LED" V 9800 6350 50 0000 R CNN 1644 | F 2 "LED_SMD:LED_0603_1608Metric" H 9800 6400 50 0001 C CNN 1645 | F 3 "~" H 9800 6400 50 0001 C CNN 1646 | 1 9800 6400 1647 | 0 1 -1 0 1648 | $EndComp 1649 | $Comp 1650 | L power:GND #PWR0135 1651 | U 1 1 61C20B18 1652 | P 7000 6600 1653 | F 0 "#PWR0135" H 7000 6350 50 0001 C CNN 1654 | F 1 "GND" H 7005 6427 50 0000 C CNN 1655 | F 2 "" H 7000 6600 50 0001 C CNN 1656 | F 3 "" H 7000 6600 50 0001 C CNN 1657 | 1 7000 6600 1658 | 1 0 0 -1 1659 | $EndComp 1660 | Wire Wire Line 1661 | 7000 6600 7000 6550 1662 | $Comp 1663 | L Device:R R4 1664 | U 1 1 61C7A3BF 1665 | P 7000 6050 1666 | F 0 "R4" H 7070 6096 50 0000 L CNN 1667 | F 1 "2.2k" H 7070 6005 50 0000 L CNN 1668 | F 2 "Resistor_SMD:R_0603_1608Metric" V 6930 6050 50 0001 C CNN 1669 | F 3 "~" H 7000 6050 50 0001 C CNN 1670 | 1 7000 6050 1671 | 1 0 0 -1 1672 | $EndComp 1673 | Wire Wire Line 1674 | 7000 6200 7000 6250 1675 | Text Label 9750 5850 2 50 ~ 0 1676 | LED_0 1677 | Wire Wire Line 1678 | 6950 5850 7000 5850 1679 | Wire Wire Line 1680 | 7000 5850 7000 5900 1681 | $Comp 1682 | L Device:LED D1 1683 | U 1 1 61CD54AE 1684 | P 9400 6400 1685 | F 0 "D1" V 9500 6350 50 0000 R CNN 1686 | F 1 "LED" V 9400 6350 50 0000 R CNN 1687 | F 2 "LED_SMD:LED_0603_1608Metric" H 9400 6400 50 0001 C CNN 1688 | F 3 "~" H 9400 6400 50 0001 C CNN 1689 | 1 9400 6400 1690 | 0 1 -1 0 1691 | $EndComp 1692 | $Comp 1693 | L power:GND #PWR0136 1694 | U 1 1 61CD54B4 1695 | P 7400 6600 1696 | F 0 "#PWR0136" H 7400 6350 50 0001 C CNN 1697 | F 1 "GND" H 7405 6427 50 0000 C CNN 1698 | F 2 "" H 7400 6600 50 0001 C CNN 1699 | F 3 "" H 7400 6600 50 0001 C CNN 1700 | 1 7400 6600 1701 | 1 0 0 -1 1702 | $EndComp 1703 | Wire Wire Line 1704 | 7400 6600 7400 6550 1705 | $Comp 1706 | L Device:R R5 1707 | U 1 1 61CD54BB 1708 | P 7400 6050 1709 | F 0 "R5" H 7470 6096 50 0000 L CNN 1710 | F 1 "2.2k" H 7470 6005 50 0000 L CNN 1711 | F 2 "Resistor_SMD:R_0603_1608Metric" V 7330 6050 50 0001 C CNN 1712 | F 3 "~" H 7400 6050 50 0001 C CNN 1713 | 1 7400 6050 1714 | 1 0 0 -1 1715 | $EndComp 1716 | Wire Wire Line 1717 | 7400 6200 7400 6250 1718 | Text Label 9350 5850 2 50 ~ 0 1719 | LED_1 1720 | Wire Wire Line 1721 | 7350 5850 7400 5850 1722 | Wire Wire Line 1723 | 7400 5850 7400 5900 1724 | $Comp 1725 | L Device:LED D2 1726 | U 1 1 61D028E8 1727 | P 9000 6400 1728 | F 0 "D2" V 9100 6350 50 0000 R CNN 1729 | F 1 "LED" V 9000 6350 50 0000 R CNN 1730 | F 2 "LED_SMD:LED_0603_1608Metric" H 9000 6400 50 0001 C CNN 1731 | F 3 "~" H 9000 6400 50 0001 C CNN 1732 | 1 9000 6400 1733 | 0 1 -1 0 1734 | $EndComp 1735 | $Comp 1736 | L power:GND #PWR0137 1737 | U 1 1 61D028EE 1738 | P 7800 6600 1739 | F 0 "#PWR0137" H 7800 6350 50 0001 C CNN 1740 | F 1 "GND" H 7805 6427 50 0000 C CNN 1741 | F 2 "" H 7800 6600 50 0001 C CNN 1742 | F 3 "" H 7800 6600 50 0001 C CNN 1743 | 1 7800 6600 1744 | 1 0 0 -1 1745 | $EndComp 1746 | Wire Wire Line 1747 | 7800 6600 7800 6550 1748 | $Comp 1749 | L Device:R R6 1750 | U 1 1 61D028F5 1751 | P 7800 6050 1752 | F 0 "R6" H 7870 6096 50 0000 L CNN 1753 | F 1 "2.2k" H 7870 6005 50 0000 L CNN 1754 | F 2 "Resistor_SMD:R_0603_1608Metric" V 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Device:R_Pack04_Split RN6 2257 | U 2 1 64239BD9 2258 | P 2500 9900 2259 | F 0 "RN6" V 2500 9900 50 0000 C CNN 2260 | F 1 "33R" V 2400 9900 50 0001 C CNN 2261 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 9900 50 0001 C CNN 2262 | F 3 "~" H 2500 9900 50 0001 C CNN 2263 | 2 2500 9900 2264 | 0 1 1 0 2265 | $EndComp 2266 | $Comp 2267 | L Device:R_Pack04_Split RN6 2268 | U 4 1 6423A21C 2269 | P 2500 9800 2270 | F 0 "RN6" V 2500 9800 50 0000 C CNN 2271 | F 1 "33R" V 2400 9800 50 0001 C CNN 2272 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 9800 50 0001 C CNN 2273 | F 3 "~" H 2500 9800 50 0001 C CNN 2274 | 4 2500 9800 2275 | 0 1 1 0 2276 | $EndComp 2277 | $Comp 2278 | L Device:R_Pack04_Split RN5 2279 | U 2 1 6423783E 2280 | P 2500 10100 2281 | F 0 "RN5" V 2500 10100 50 0000 C CNN 2282 | F 1 "33R" V 2600 10100 50 0000 C CNN 2283 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 10100 50 0001 C CNN 2284 | F 3 "~" H 2500 10100 50 0001 C CNN 2285 | 2 2500 10100 2286 | 0 1 -1 0 2287 | $EndComp 2288 | $Comp 2289 | L Device:R_Pack04_Split RN5 2290 | U 4 1 64238E27 2291 | P 2500 10000 2292 | F 0 "RN5" V 2500 10000 50 0000 C CNN 2293 | F 1 "33R" V 2384 10000 50 0001 C CNN 2294 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 10000 50 0001 C CNN 2295 | F 3 "~" H 2500 10000 50 0001 C CNN 2296 | 4 2500 10000 2297 | 0 1 -1 0 2298 | $EndComp 2299 | $Comp 2300 | L power:GND #PWR0111 2301 | U 1 1 6481F612 2302 | P 1950 8800 2303 | F 0 "#PWR0111" H 1950 8550 50 0001 C CNN 2304 | F 1 "GND" H 1955 8627 50 0000 C CNN 2305 | F 2 "" H 1950 8800 50 0001 C CNN 2306 | F 3 "" H 1950 8800 50 0001 C CNN 2307 | 1 1950 8800 2308 | 1 0 0 -1 2309 | $EndComp 2310 | Connection ~ 1950 8750 2311 | Wire Wire Line 2312 | 1950 8800 1950 8750 2313 | $Comp 2314 | L power:+3V3 #PWR0112 2315 | U 1 1 6481F61A 2316 | P 1950 7700 2317 | F 0 "#PWR0112" H 1950 7550 50 0001 C CNN 2318 | F 1 "+3V3" H 1965 7873 50 0000 C CNN 2319 | F 2 "" H 1950 7700 50 0001 C CNN 2320 | F 3 "" H 1950 7700 50 0001 C CNN 2321 | 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Line 2362 | 2200 8350 2350 8350 2363 | Wire Wire Line 2364 | 1700 8350 1550 8350 2365 | Wire Wire Line 2366 | 1550 8250 1700 8250 2367 | Wire Wire Line 2368 | 1700 8150 1550 8150 2369 | Wire Wire Line 2370 | 2750 8050 2650 8050 2371 | Wire Wire Line 2372 | 2650 8150 2750 8150 2373 | Wire Wire Line 2374 | 2750 8250 2650 8250 2375 | Wire Wire Line 2376 | 2650 8350 2750 8350 2377 | $Comp 2378 | L Device:R_Pack04_Split RN2 2379 | U 1 1 6481F63B 2380 | P 1400 8350 2381 | F 0 "RN2" V 1400 8350 50 0000 C CNN 2382 | F 1 "33R" V 1000 8350 50 0000 C CNN 2383 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 1675 8350 50 0001 C CNN 2384 | F 3 "~" H 1400 8350 50 0001 C CNN 2385 | 1 1400 8350 2386 | 0 -1 1 0 2387 | $EndComp 2388 | Wire Wire Line 2389 | 1150 8350 1250 8350 2390 | Wire Wire Line 2391 | 1250 8250 1150 8250 2392 | Wire Wire Line 2393 | 1150 8150 1250 8150 2394 | Wire Wire Line 2395 | 1250 8050 1150 8050 2396 | Wire Wire Line 2397 | 1650 8550 1700 8550 2398 | $Comp 2399 | L Connector_Generic:Conn_02x06_Top_Bottom J1 2400 | U 1 1 6481F646 2401 | P 1900 8250 2402 | F 0 "J1" H 1950 8667 50 0000 C CNN 2403 | F 1 "PMOD_A" H 1950 8576 50 0000 C CNN 2404 | F 2 "PMOD:PMOD_Double_Mirrored" H 1900 8250 50 0001 C CNN 2405 | F 3 "~" H 1900 8250 50 0001 C CNN 2406 | 1 1900 8250 2407 | 1 0 0 -1 2408 | $EndComp 2409 | Wire Wire Line 2410 | 2250 8550 2200 8550 2411 | Wire Wire Line 2412 | 2200 8450 2300 8450 2413 | Wire Wire Line 2414 | 2300 8450 2300 8750 2415 | Wire Wire Line 2416 | 1950 8750 2300 8750 2417 | Wire Wire Line 2418 | 1600 8750 1600 8450 2419 | Wire Wire Line 2420 | 1600 8450 1700 8450 2421 | $Comp 2422 | L Device:R_Pack04_Split RN2 2423 | U 3 1 6481F652 2424 | P 1400 8250 2425 | F 0 "RN2" V 1400 8250 50 0000 C CNN 2426 | F 1 "33R" V 1284 8250 50 0001 C CNN 2427 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 1675 8250 50 0001 C CNN 2428 | F 3 "~" H 1400 8250 50 0001 C CNN 2429 | 3 1400 8250 2430 | 0 -1 1 0 2431 | $EndComp 2432 | $Comp 2433 | L Device:R_Pack04_Split RN1 2434 | U 1 1 6481F658 2435 | P 1400 8150 2436 | F 0 "RN1" V 1400 8150 50 0000 C CNN 2437 | F 1 "33R" V 1300 8150 50 0001 C CNN 2438 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 1675 8150 50 0001 C CNN 2439 | F 3 "~" H 1400 8150 50 0001 C CNN 2440 | 1 1400 8150 2441 | 0 -1 -1 0 2442 | $EndComp 2443 | $Comp 2444 | L Device:R_Pack04_Split RN1 2445 | U 3 1 6481F65E 2446 | P 1400 8050 2447 | F 0 "RN1" V 1400 8050 50 0000 C CNN 2448 | F 1 "33R" V 1300 8050 50 0001 C CNN 2449 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 1675 8050 50 0001 C CNN 2450 | F 3 "~" H 1400 8050 50 0001 C CNN 2451 | 3 1400 8050 2452 | 0 -1 -1 0 2453 | $EndComp 2454 | $Comp 2455 | L Device:R_Pack04_Split RN1 2456 | U 2 1 6481F664 2457 | P 2500 8150 2458 | F 0 "RN1" V 2500 8150 50 0000 C CNN 2459 | F 1 "33R" V 2400 8150 50 0001 C CNN 2460 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 8150 50 0001 C CNN 2461 | F 3 "~" H 2500 8150 50 0001 C CNN 2462 | 2 2500 8150 2463 | 0 1 1 0 2464 | $EndComp 2465 | $Comp 2466 | L Device:R_Pack04_Split RN1 2467 | U 4 1 6481F66A 2468 | P 2500 8050 2469 | F 0 "RN1" V 2500 8050 50 0000 C CNN 2470 | F 1 "33R" V 2400 8050 50 0001 C CNN 2471 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 8050 50 0001 C CNN 2472 | F 3 "~" H 2500 8050 50 0001 C CNN 2473 | 4 2500 8050 2474 | 0 1 1 0 2475 | $EndComp 2476 | $Comp 2477 | L Device:R_Pack04_Split RN2 2478 | U 2 1 6481F670 2479 | P 2500 8350 2480 | F 0 "RN2" V 2500 8350 50 0000 C CNN 2481 | F 1 "33R" V 2900 8350 50 0000 C CNN 2482 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 8350 50 0001 C CNN 2483 | F 3 "~" H 2500 8350 50 0001 C CNN 2484 | 2 2500 8350 2485 | 0 1 -1 0 2486 | $EndComp 2487 | $Comp 2488 | L Device:R_Pack04_Split RN2 2489 | U 4 1 6481F676 2490 | P 2500 8250 2491 | F 0 "RN2" V 2500 8250 50 0000 C CNN 2492 | F 1 "33R" V 2384 8250 50 0001 C CNN 2493 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 2775 8250 50 0001 C CNN 2494 | F 3 "~" H 2500 8250 50 0001 C CNN 2495 | 4 2500 8250 2496 | 0 1 -1 0 2497 | $EndComp 2498 | $Comp 2499 | L power:GND #PWR0113 2500 | U 1 1 648E07B1 2501 | P 4500 8800 2502 | F 0 "#PWR0113" H 4500 8550 50 0001 C CNN 2503 | F 1 "GND" H 4505 8627 50 0000 C CNN 2504 | F 2 "" H 4500 8800 50 0001 C CNN 2505 | F 3 "" H 4500 8800 50 0001 C CNN 2506 | 1 4500 8800 2507 | 1 0 0 -1 2508 | $EndComp 2509 | Connection ~ 4500 8750 2510 | Wire Wire Line 2511 | 4500 8800 4500 8750 2512 | $Comp 2513 | L power:+3V3 #PWR0114 2514 | U 1 1 648E07B9 2515 | P 4500 7700 2516 | F 0 "#PWR0114" H 4500 7550 50 0001 C CNN 2517 | F 1 "+3V3" H 4515 7873 50 0000 C CNN 2518 | F 2 "" H 4500 7700 50 0001 C CNN 2519 | F 3 "" H 4500 7700 50 0001 C CNN 2520 | 1 4500 7700 2521 | 1 0 0 -1 2522 | $EndComp 2523 | Wire Wire Line 2524 | 4500 7750 4200 7750 2525 | Wire Wire Line 2526 | 4200 7750 4200 8550 2527 | Connection ~ 4500 7750 2528 | Wire Wire Line 2529 | 4500 7700 4500 7750 2530 | Wire Wire Line 2531 | 4800 8550 4800 7750 2532 | Wire Wire Line 2533 | 4500 7750 4800 7750 2534 | Wire Wire Line 2535 | 4150 8750 4500 8750 2536 | Text Label 3700 8050 2 50 ~ 0 2537 | PMOD_B1 2538 | Wire Wire Line 2539 | 4100 8050 4250 8050 2540 | Text Label 3700 8150 2 50 ~ 0 2541 | PMOD_B2 2542 | Text Label 3700 8250 2 50 ~ 0 2543 | PMOD_B3 2544 | Text Label 3700 8350 2 50 ~ 0 2545 | PMOD_B4 2546 | Text Label 5300 8350 0 50 ~ 0 2547 | PMOD_B10 2548 | Text Label 5300 8250 0 50 ~ 0 2549 | PMOD_B9 2550 | Text Label 5300 8150 0 50 ~ 0 2551 | PMOD_B8 2552 | Text Label 5300 8050 0 50 ~ 0 2553 | PMOD_B7 2554 | Wire Wire Line 2555 | 4900 8050 4750 8050 2556 | Wire Wire Line 2557 | 4750 8150 4900 8150 2558 | Wire Wire Line 2559 | 4900 8250 4750 8250 2560 | Wire Wire Line 2561 | 4750 8350 4900 8350 2562 | Wire Wire Line 2563 | 4250 8350 4100 8350 2564 | Wire Wire Line 2565 | 4100 8250 4250 8250 2566 | Wire Wire Line 2567 | 4250 8150 4100 8150 2568 | Wire Wire Line 2569 | 5300 8050 5200 8050 2570 | Wire Wire Line 2571 | 5200 8150 5300 8150 2572 | Wire Wire Line 2573 | 5300 8250 5200 8250 2574 | Wire Wire Line 2575 | 5200 8350 5300 8350 2576 | $Comp 2577 | L Device:R_Pack04_Split RN4 2578 | U 1 1 648E07DA 2579 | P 3950 8350 2580 | F 0 "RN4" V 3950 8350 50 0000 C CNN 2581 | F 1 "33R" V 3550 8350 50 0000 C CNN 2582 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 4225 8350 50 0001 C CNN 2583 | F 3 "~" H 3950 8350 50 0001 C CNN 2584 | 1 3950 8350 2585 | 0 -1 1 0 2586 | $EndComp 2587 | Wire Wire Line 2588 | 3700 8350 3800 8350 2589 | Wire Wire Line 2590 | 3800 8250 3700 8250 2591 | Wire Wire Line 2592 | 3700 8150 3800 8150 2593 | Wire Wire Line 2594 | 3800 8050 3700 8050 2595 | Wire Wire Line 2596 | 4200 8550 4250 8550 2597 | $Comp 2598 | L Connector_Generic:Conn_02x06_Top_Bottom J2 2599 | U 1 1 648E07E5 2600 | P 4450 8250 2601 | F 0 "J2" H 4500 8667 50 0000 C CNN 2602 | F 1 "PMOD_B" H 4500 8576 50 0000 C CNN 2603 | F 2 "PMOD:PMOD_Double_Mirrored" H 4450 8250 50 0001 C CNN 2604 | F 3 "~" H 4450 8250 50 0001 C CNN 2605 | 1 4450 8250 2606 | 1 0 0 -1 2607 | $EndComp 2608 | Wire Wire Line 2609 | 4800 8550 4750 8550 2610 | Wire Wire Line 2611 | 4750 8450 4850 8450 2612 | Wire Wire Line 2613 | 4850 8450 4850 8750 2614 | Wire Wire Line 2615 | 4500 8750 4850 8750 2616 | Wire Wire Line 2617 | 4150 8750 4150 8450 2618 | Wire Wire Line 2619 | 4150 8450 4250 8450 2620 | $Comp 2621 | L Device:R_Pack04_Split RN4 2622 | U 3 1 648E07F1 2623 | P 3950 8250 2624 | F 0 "RN4" V 3950 8250 50 0000 C CNN 2625 | F 1 "33R" V 3834 8250 50 0001 C CNN 2626 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 4225 8250 50 0001 C CNN 2627 | F 3 "~" H 3950 8250 50 0001 C CNN 2628 | 3 3950 8250 2629 | 0 -1 1 0 2630 | $EndComp 2631 | $Comp 2632 | L Device:R_Pack04_Split RN3 2633 | U 1 1 648E07F7 2634 | P 3950 8150 2635 | F 0 "RN3" V 3950 8150 50 0000 C CNN 2636 | F 1 "33R" V 3850 8150 50 0001 C CNN 2637 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 4225 8150 50 0001 C CNN 2638 | F 3 "~" H 3950 8150 50 0001 C CNN 2639 | 1 3950 8150 2640 | 0 -1 -1 0 2641 | $EndComp 2642 | $Comp 2643 | L Device:R_Pack04_Split RN3 2644 | U 3 1 648E07FD 2645 | P 3950 8050 2646 | F 0 "RN3" V 3950 8050 50 0000 C CNN 2647 | F 1 "33R" V 3850 8050 50 0001 C CNN 2648 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 4225 8050 50 0001 C CNN 2649 | F 3 "~" H 3950 8050 50 0001 C CNN 2650 | 3 3950 8050 2651 | 0 -1 -1 0 2652 | $EndComp 2653 | $Comp 2654 | L Device:R_Pack04_Split RN3 2655 | U 2 1 648E0803 2656 | P 5050 8150 2657 | F 0 "RN3" V 5050 8150 50 0000 C CNN 2658 | F 1 "33R" V 4950 8150 50 0001 C CNN 2659 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 8150 50 0001 C CNN 2660 | F 3 "~" H 5050 8150 50 0001 C CNN 2661 | 2 5050 8150 2662 | 0 1 1 0 2663 | $EndComp 2664 | $Comp 2665 | L Device:R_Pack04_Split RN3 2666 | U 4 1 648E0809 2667 | P 5050 8050 2668 | F 0 "RN3" V 5050 8050 50 0000 C CNN 2669 | F 1 "33R" V 4950 8050 50 0001 C CNN 2670 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 8050 50 0001 C CNN 2671 | F 3 "~" H 5050 8050 50 0001 C CNN 2672 | 4 5050 8050 2673 | 0 1 1 0 2674 | $EndComp 2675 | $Comp 2676 | L Device:R_Pack04_Split RN4 2677 | U 2 1 648E080F 2678 | P 5050 8350 2679 | F 0 "RN4" V 5050 8350 50 0000 C CNN 2680 | F 1 "33R" V 5450 8350 50 0000 C CNN 2681 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 8350 50 0001 C CNN 2682 | F 3 "~" H 5050 8350 50 0001 C CNN 2683 | 2 5050 8350 2684 | 0 1 -1 0 2685 | $EndComp 2686 | $Comp 2687 | L Device:R_Pack04_Split RN4 2688 | U 4 1 648E0815 2689 | P 5050 8250 2690 | F 0 "RN4" V 5050 8250 50 0000 C CNN 2691 | F 1 "33R" V 4934 8250 50 0001 C CNN 2692 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 8250 50 0001 C CNN 2693 | F 3 "~" H 5050 8250 50 0001 C CNN 2694 | 4 5050 8250 2695 | 0 1 -1 0 2696 | $EndComp 2697 | Wire Wire Line 2698 | 4000 1750 4050 1750 2699 | Wire Wire Line 2700 | 4050 1650 4000 1650 2701 | Wire Wire Line 2702 | 4000 1550 4050 1550 2703 | Wire Wire Line 2704 | 4050 1450 4000 1450 2705 | Wire Wire Line 2706 | 4000 1350 4050 1350 2707 | Wire Wire Line 2708 | 4050 1250 4000 1250 2709 | Wire Wire Line 2710 | 4000 2150 4050 2150 2711 | Wire Wire Line 2712 | 4050 2050 4000 2050 2713 | Wire Wire Line 2714 | 4000 1950 4050 1950 2715 | Wire Wire Line 2716 | 4050 1850 4000 1850 2717 | NoConn ~ 4050 2350 2718 | NoConn ~ 4050 3050 2719 | NoConn ~ 4050 3150 2720 | NoConn ~ 1700 4750 2721 | NoConn ~ 1700 4650 2722 | NoConn ~ 1700 4550 2723 | NoConn ~ 1700 4450 2724 | NoConn ~ 4050 6550 2725 | NoConn ~ 4050 6650 2726 | $Comp 2727 | L power:PWR_FLAG #FLG0104 2728 | U 1 1 65522141 2729 | P 12150 5150 2730 | F 0 "#FLG0104" H 12150 5225 50 0001 C CNN 2731 | F 1 "PWR_FLAG" V 12150 5277 50 0000 L CNN 2732 | F 2 "" H 12150 5150 50 0001 C CNN 2733 | F 3 "~" H 12150 5150 50 0001 C CNN 2734 | 1 12150 5150 2735 | 0 -1 -1 0 2736 | $EndComp 2737 | Wire Wire Line 2738 | 12150 5150 12250 5150 2739 | Connection ~ 12250 5150 2740 | Wire Wire Line 2741 | 12250 5150 12250 5250 2742 | Wire Wire Line 2743 | 8700 9550 8700 9600 2744 | Wire Wire Line 2745 | 13750 3100 13700 3100 2746 | $Comp 2747 | L power:PWR_FLAG #FLG0101 2748 | U 1 1 6569FE82 2749 | P 9500 1700 2750 | F 0 "#FLG0101" H 9500 1775 50 0001 C CNN 2751 | F 1 "PWR_FLAG" V 9500 1828 50 0000 L CNN 2752 | F 2 "" H 9500 1700 50 0001 C CNN 2753 | F 3 "~" H 9500 1700 50 0001 C CNN 2754 | 1 9500 1700 2755 | 0 1 1 0 2756 | $EndComp 2757 | Wire Wire Line 2758 | 9500 1700 9350 1700 2759 | Connection ~ 9350 1700 2760 | $Comp 2761 | L power:PWR_FLAG #FLG0106 2762 | U 1 1 6571C8AF 2763 | P 9550 1300 2764 | F 0 "#FLG0106" H 9550 1375 50 0001 C CNN 2765 | F 1 "PWR_FLAG" V 9550 1428 50 0000 L CNN 2766 | F 2 "" H 9550 1300 50 0001 C CNN 2767 | F 3 "~" H 9550 1300 50 0001 C CNN 2768 | 1 9550 1300 2769 | 0 1 1 0 2770 | $EndComp 2771 | Wire Wire Line 2772 | 9350 1300 9350 1100 2773 | Wire Wire Line 2774 | 9350 1100 9600 1100 2775 | Wire Wire Line 2776 | 13750 2900 13750 3100 2777 | Wire Wire Line 2778 | 14000 2900 14000 3500 2779 | Wire Wire Line 2780 | 4000 6750 4050 6750 2781 | Wire Wire Line 2782 | 4050 6850 4000 6850 2783 | $Comp 2784 | L Mechanical:MountingHole H1 2785 | U 1 1 65A0C3D4 2786 | P 15400 650 2787 | F 0 "H1" H 15500 696 50 0000 L CNN 2788 | F 1 "MountingHole" H 15500 605 50 0000 L CNN 2789 | F 2 "MountingHole:MountingHole_3.2mm_M3_DIN965" H 15400 650 50 0001 C CNN 2790 | F 3 "~" H 15400 650 50 0001 C CNN 2791 | 1 15400 650 2792 | 1 0 0 -1 2793 | $EndComp 2794 | $Comp 2795 | L Mechanical:MountingHole H2 2796 | U 1 1 65A0C845 2797 | P 15400 850 2798 | F 0 "H2" H 15500 896 50 0000 L CNN 2799 | F 1 "MountingHole" H 15500 805 50 0000 L CNN 2800 | F 2 "MountingHole:MountingHole_3.2mm_M3_DIN965" H 15400 850 50 0001 C CNN 2801 | F 3 "~" H 15400 850 50 0001 C CNN 2802 | 1 15400 850 2803 | 1 0 0 -1 2804 | $EndComp 2805 | $Comp 2806 | L Mechanical:MountingHole H3 2807 | U 1 1 65A0CB75 2808 | P 15400 1050 2809 | F 0 "H3" H 15500 1096 50 0000 L CNN 2810 | F 1 "MountingHole" H 15500 1005 50 0000 L CNN 2811 | F 2 "MountingHole:MountingHole_3.2mm_M3_DIN965" H 15400 1050 50 0001 C CNN 2812 | F 3 "~" H 15400 1050 50 0001 C CNN 2813 | 1 15400 1050 2814 | 1 0 0 -1 2815 | $EndComp 2816 | $Comp 2817 | L Mechanical:MountingHole H4 2818 | U 1 1 65A0CDA6 2819 | P 15400 1250 2820 | F 0 "H4" H 15500 1296 50 0000 L CNN 2821 | F 1 "MountingHole" H 15500 1205 50 0000 L CNN 2822 | F 2 "MountingHole:MountingHole_3.2mm_M3_DIN965" H 15400 1250 50 0001 C CNN 2823 | F 3 "~" H 15400 1250 50 0001 C CNN 2824 | 1 15400 1250 2825 | 1 0 0 -1 2826 | $EndComp 2827 | NoConn ~ 4050 2950 2828 | NoConn ~ 4050 2850 2829 | NoConn ~ 1700 5550 2830 | NoConn ~ 1700 5450 2831 | NoConn ~ 1700 5350 2832 | NoConn ~ 1700 5250 2833 | NoConn ~ 1700 5150 2834 | NoConn ~ 1700 5050 2835 | NoConn ~ 1700 4950 2836 | NoConn ~ 1700 4850 2837 | NoConn ~ 1700 5850 2838 | NoConn ~ 1700 5950 2839 | NoConn ~ 1700 6050 2840 | $Comp 2841 | L Connector:Conn_01x02_Male J9 2842 | U 1 1 6603F849 2843 | P 11150 9250 2844 | F 0 "J9" H 11122 9132 50 0000 R CNN 2845 | F 1 "5V_CD" H 11122 9223 50 0000 R CNN 2846 | F 2 "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" H 11150 9250 50 0001 C CNN 2847 | F 3 "~" H 11150 9250 50 0001 C CNN 2848 | 1 11150 9250 2849 | -1 0 0 1 2850 | $EndComp 2851 | $Comp 2852 | L power:GND #PWR0147 2853 | U 1 1 6603F84F 2854 | P 10900 9300 2855 | F 0 "#PWR0147" H 10900 9050 50 0001 C CNN 2856 | F 1 "GND" H 10905 9127 50 0000 C CNN 2857 | F 2 "" H 10900 9300 50 0001 C CNN 2858 | F 3 "" H 10900 9300 50 0001 C CNN 2859 | 1 10900 9300 2860 | 1 0 0 -1 2861 | $EndComp 2862 | Wire Wire Line 2863 | 10900 9300 10900 9250 2864 | Wire Wire Line 2865 | 10900 9250 10950 9250 2866 | $Comp 2867 | L power:+5V #PWR0148 2868 | U 1 1 6603F857 2869 | P 10900 9100 2870 | F 0 "#PWR0148" H 10900 8950 50 0001 C CNN 2871 | F 1 "+5V" H 10915 9273 50 0000 C CNN 2872 | F 2 "" H 10900 9100 50 0001 C CNN 2873 | F 3 "" H 10900 9100 50 0001 C CNN 2874 | 1 10900 9100 2875 | 1 0 0 -1 2876 | $EndComp 2877 | Wire Wire Line 2878 | 10900 9100 10900 9150 2879 | Wire Wire Line 2880 | 10900 9150 10950 9150 2881 | $Comp 2882 | L Connector:Conn_01x02_Male J8 2883 | U 1 1 62C4CD8F 2884 | P 11150 10050 2885 | F 0 "J8" H 11122 9932 50 0000 R CNN 2886 | F 1 "5V_AB" H 11122 10023 50 0000 R CNN 2887 | F 2 "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" H 11150 10050 50 0001 C CNN 2888 | F 3 "~" H 11150 10050 50 0001 C CNN 2889 | 1 11150 10050 2890 | -1 0 0 1 2891 | $EndComp 2892 | Text Label 4000 5050 2 50 ~ 0 2893 | PMOD_A8 2894 | Text Label 4000 4950 2 50 ~ 0 2895 | PMOD_A2 2896 | Text Label 4050 5650 2 50 ~ 0 2897 | PMOD_A7 2898 | Text Label 4050 5550 2 50 ~ 0 2899 | PMOD_A1 2900 | Wire Wire Line 2901 | 7550 2000 7500 2000 2902 | Wire Wire Line 2903 | 7500 2000 7500 2150 2904 | Wire Wire Line 2905 | 7600 3650 7500 3650 2906 | $Comp 2907 | L Connector:TestPoint TP1 2908 | U 1 1 607F6883 2909 | P 14250 8100 2910 | F 0 "TP1" V 14204 8288 50 0000 L CNN 2911 | F 1 "TP_1V2" V 14295 8288 50 0000 L CNN 2912 | F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 14450 8100 50 0001 C CNN 2913 | F 3 "~" H 14450 8100 50 0001 C CNN 2914 | 1 14250 8100 2915 | 0 1 1 0 2916 | $EndComp 2917 | $Comp 2918 | L power:+1V2 #PWR0149 2919 | U 1 1 607F83DA 2920 | P 14250 8100 2921 | F 0 "#PWR0149" H 14250 7950 50 0001 C CNN 2922 | F 1 "+1V2" V 14265 8228 50 0000 L CNN 2923 | F 2 "" H 14250 8100 50 0001 C CNN 2924 | F 3 "" H 14250 8100 50 0001 C CNN 2925 | 1 14250 8100 2926 | 0 -1 -1 0 2927 | $EndComp 2928 | $Comp 2929 | L Connector:TestPoint TP2 2930 | U 1 1 607FF8F3 2931 | P 14250 8350 2932 | F 0 "TP2" V 14204 8538 50 0000 L CNN 2933 | F 1 "TP_3V3" V 14295 8538 50 0000 L CNN 2934 | F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 14450 8350 50 0001 C CNN 2935 | F 3 "~" H 14450 8350 50 0001 C CNN 2936 | 1 14250 8350 2937 | 0 1 1 0 2938 | $EndComp 2939 | $Comp 2940 | L power:+3V3 #PWR0150 2941 | U 1 1 608012EE 2942 | P 14250 8350 2943 | F 0 "#PWR0150" H 14250 8200 50 0001 C CNN 2944 | F 1 "+3V3" V 14265 8478 50 0000 L CNN 2945 | F 2 "" H 14250 8350 50 0001 C CNN 2946 | F 3 "" H 14250 8350 50 0001 C CNN 2947 | 1 14250 8350 2948 | 0 -1 -1 0 2949 | $EndComp 2950 | $Comp 2951 | L Connector:TestPoint TP3 2952 | U 1 1 6080198E 2953 | P 14250 8600 2954 | F 0 "TP3" V 14204 8788 50 0000 L CNN 2955 | F 1 "TP_5V" V 14295 8788 50 0000 L CNN 2956 | F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 14450 8600 50 0001 C CNN 2957 | F 3 "~" H 14450 8600 50 0001 C CNN 2958 | 1 14250 8600 2959 | 0 1 1 0 2960 | $EndComp 2961 | $Comp 2962 | L power:+5V #PWR0151 2963 | U 1 1 60803329 2964 | P 14250 8600 2965 | F 0 "#PWR0151" H 14250 8450 50 0001 C CNN 2966 | F 1 "+5V" V 14265 8728 50 0000 L CNN 2967 | F 2 "" H 14250 8600 50 0001 C CNN 2968 | F 3 "" H 14250 8600 50 0001 C CNN 2969 | 1 14250 8600 2970 | 0 -1 -1 0 2971 | $EndComp 2972 | $Comp 2973 | L Connector:TestPoint TP4 2974 | U 1 1 60867296 2975 | P 14250 8850 2976 | F 0 "TP4" V 14204 9038 50 0000 L CNN 2977 | F 1 "TP_GND" V 14295 9038 50 0000 L CNN 2978 | F 2 "TestPoint:TestPoint_Pad_D2.0mm" H 14450 8850 50 0001 C CNN 2979 | F 3 "~" H 14450 8850 50 0001 C CNN 2980 | 1 14250 8850 2981 | 0 1 1 0 2982 | $EndComp 2983 | $Comp 2984 | L power:GND #PWR0116 2985 | U 1 1 608692CE 2986 | P 14250 8850 2987 | F 0 "#PWR0116" H 14250 8600 50 0001 C CNN 2988 | F 1 "GND" V 14255 8722 50 0000 R CNN 2989 | F 2 "" H 14250 8850 50 0001 C CNN 2990 | F 3 "" H 14250 8850 50 0001 C CNN 2991 | 1 14250 8850 2992 | 0 1 1 0 2993 | $EndComp 2994 | $Comp 2995 | L power:+3V3 #PWR0117 2996 | U 1 1 6079D45F 2997 | P 7300 2100 2998 | F 0 "#PWR0117" H 7300 1950 50 0001 C CNN 2999 | F 1 "+3V3" V 7300 2300 50 0000 C CNN 3000 | F 2 "" H 7300 2100 50 0001 C CNN 3001 | F 3 "" H 7300 2100 50 0001 C CNN 3002 | 1 7300 2100 3003 | 1 0 0 -1 3004 | $EndComp 3005 | $Comp 3006 | L Device:R_Pack04_Split RN7 3007 | U 4 1 63C65F6E 3008 | P 5050 10000 3009 | F 0 "RN7" V 5050 10000 50 0000 C CNN 3010 | F 1 "33R" V 5184 10000 50 0001 C CNN 3011 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 10000 50 0001 C CNN 3012 | F 3 "~" H 5050 10000 50 0001 C CNN 3013 | 4 5050 10000 3014 | 0 1 -1 0 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| 3 3950 9800 3047 | 0 -1 -1 0 3048 | $EndComp 3049 | $Comp 3050 | L Device:R_Pack04_Split RN7 3051 | U 2 1 63B133D3 3052 | P 5050 10100 3053 | F 0 "RN7" V 5050 10100 50 0000 C CNN 3054 | F 1 "33R" V 5450 10100 50 0000 C CNN 3055 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 10100 50 0001 C CNN 3056 | F 3 "~" H 5050 10100 50 0001 C CNN 3057 | 2 5050 10100 3058 | 0 1 -1 0 3059 | $EndComp 3060 | $Comp 3061 | L Device:R_Pack04_Split RN8 3062 | U 4 1 63F9040A 3063 | P 5050 9800 3064 | F 0 "RN8" V 5050 9800 50 0000 C CNN 3065 | F 1 "33R" V 4900 10050 50 0001 C CNN 3066 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 5325 9800 50 0001 C CNN 3067 | F 3 "~" H 5050 9800 50 0001 C CNN 3068 | 4 5050 9800 3069 | 0 1 1 0 3070 | $EndComp 3071 | $Comp 3072 | L Device:R_Pack04_Split RN8 3073 | U 1 1 61163700 3074 | P 3950 9900 3075 | F 0 "RN8" V 3950 9900 50 0000 C CNN 3076 | F 1 "33R" V 3800 10150 50 0001 C CNN 3077 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 4225 9900 50 0001 C CNN 3078 | F 3 "~" H 3950 9900 50 0001 C CNN 3079 | 1 3950 9900 3080 | 0 -1 -1 0 3081 | $EndComp 3082 | $Comp 3083 | L Device:R_Pack04_Split RN7 3084 | U 1 1 6116370A 3085 | P 3950 10100 3086 | F 0 "RN7" V 3950 10100 50 0000 C CNN 3087 | F 1 "33R" V 3550 10100 50 0000 C CNN 3088 | F 2 "Resistor_SMD:R_Array_Convex_4x0603" V 4225 10100 50 0001 C CNN 3089 | F 3 "~" H 3950 10100 50 0001 C CNN 3090 | 1 3950 10100 3091 | 0 -1 1 0 3092 | $EndComp 3093 | Text Label 1650 3050 2 50 ~ 0 3094 | PMOD_C2 3095 | Text Label 1650 2850 2 50 ~ 0 3096 | PMOD_C3 3097 | Text Label 1650 2350 2 50 ~ 0 3098 | PMOD_C4 3099 | Text Label 1650 2750 2 50 ~ 0 3100 | PMOD_C10 3101 | Text Label 1650 2950 2 50 ~ 0 3102 | PMOD_C9 3103 | Text Label 1650 3150 2 50 ~ 0 3104 | PMOD_C8 3105 | Text Label 1650 3350 2 50 ~ 0 3106 | PMOD_C7 3107 | Text Label 1650 3250 2 50 ~ 0 3108 | PMOD_C1 3109 | Text Label 1650 1650 2 50 ~ 0 3110 | PMOD_D10 3111 | Text Label 1650 2250 2 50 ~ 0 3112 | PMOD_D7 3113 | Text Label 1650 2050 2 50 ~ 0 3114 | PMOD_D8 3115 | Text Label 1650 1850 2 50 ~ 0 3116 | PMOD_D9 3117 | Text Label 1650 1550 2 50 ~ 0 3118 | PMOD_D4 3119 | Text Label 1650 1750 2 50 ~ 0 3120 | PMOD_D3 3121 | Text Label 1650 1950 2 50 ~ 0 3122 | PMOD_D2 3123 | Text Label 1650 2150 2 50 ~ 0 3124 | PMOD_D1 3125 | Wire Wire Line 3126 | 1650 3350 1700 3350 3127 | Wire Wire Line 3128 | 1650 3250 1700 3250 3129 | Wire Wire Line 3130 | 1650 3150 1700 3150 3131 | NoConn ~ 1700 2550 3132 | NoConn ~ 1700 2450 3133 | Wire Wire Line 3134 | 4000 4950 4050 4950 3135 | Wire Wire Line 3136 | 4000 5050 4050 5050 3137 | Wire Wire Line 3138 | 1650 2350 1700 2350 3139 | NoConn ~ 1700 2650 3140 | NoConn ~ 4050 5150 3141 | NoConn ~ 4050 5250 3142 | NoConn ~ 4050 5350 3143 | NoConn ~ 4050 5450 3144 | NoConn ~ 1700 1150 3145 | NoConn ~ 1700 1250 3146 | NoConn ~ 1700 1350 3147 | NoConn ~ 1700 1450 3148 | Text Notes 15400 11075 0 59 Italic 12 3149 | v1.0.2 3150 | Text Notes 11850 10250 0 50 ~ 0 3151 | By Dan Rodrigues\n\ngithub.com/dan-rodrigues 3152 | Text Label 4000 1850 2 50 ~ 0 3153 | LED_7 3154 | Text Label 4000 1950 2 50 ~ 0 3155 | LED_6 3156 | Text Label 4000 2050 2 50 ~ 0 3157 | LED_5 3158 | Text Label 4000 2150 2 50 ~ 0 3159 | LED_4 3160 | $EndSCHEMATC 3161 | -------------------------------------------------------------------------------- /pcb/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name RPi_Pico)(type Legacy)(uri ${KIPRJMOD}/lib/RPi_Pico.lib)(options "")(descr "")) 3 | ) 4 | -------------------------------------------------------------------------------- /rtl/data/picohx.pcf: -------------------------------------------------------------------------------- 1 | # Clock from RP2040 2 | 3 | set_io clk_in 49 4 | 5 | # LEDs 6 | 7 | set_io led[0] 60 8 | set_io led[1] 58 9 | set_io led[2] 56 10 | set_io led[3] 52 11 | set_io led[4] 48 12 | set_io led[5] 47 13 | set_io led[6] 45 14 | set_io led[7] 44 15 | 16 | # Buttons 17 | 18 | set_io btn_a 34 19 | set_io btn_b 33 20 | 21 | # PSRAM / Flash 22 | 23 | set_io psram_sck 38 24 | set_io psram_csn 43 25 | set_io psram_io[0] 37 26 | set_io psram_io[1] 42 27 | set_io psram_io[2] 41 28 | set_io psram_io[3] 39 29 | 30 | # RP2040 GPIO 31 | 32 | set_io rp_io[0] 107 33 | set_io rp_io[1] 106 34 | set_io rp_io[2] 105 35 | set_io rp_io[3] 104 36 | set_io rp_io[4] 102 37 | set_io rp_io[5] 101 38 | set_io rp_io[6] 99 39 | set_io rp_io[7] 98 40 | 41 | set_io rp_sio[0] 94 42 | set_io rp_sio[1] 93 43 | 44 | # PMOD-A 45 | 46 | set_io pmod_a1 19 47 | set_io pmod_a2 7 48 | set_io pmod_a3 3 49 | set_io pmod_a4 1 50 | set_io pmod_a7 20 51 | set_io pmod_a8 8 52 | set_io pmod_a9 4 53 | set_io pmod_a10 2 54 | 55 | # PMOD-B 56 | 57 | set_io pmod_b1 28 58 | set_io pmod_b2 25 59 | set_io pmod_b3 23 60 | set_io pmod_b4 21 61 | set_io pmod_b7 29 62 | set_io pmod_b8 26 63 | set_io pmod_b9 24 64 | set_io pmod_b10 22 65 | 66 | # PMOD-C 67 | 68 | set_io pmod_c1 143 69 | set_io pmod_c2 141 70 | set_io pmod_c3 138 71 | set_io pmod_c4 129 72 | set_io pmod_c7 144 73 | set_io pmod_c8 142 74 | set_io pmod_c9 139 75 | set_io pmod_c10 137 76 | 77 | # PMOD-D 78 | 79 | set_io pmod_d1 122 80 | set_io pmod_d2 120 81 | set_io pmod_d3 118 82 | set_io pmod_d4 116 83 | set_io pmod_d7 128 84 | set_io pmod_d8 121 85 | set_io pmod_d9 119 86 | set_io pmod_d10 117 87 | -------------------------------------------------------------------------------- /rtl/demo/.gitignore: -------------------------------------------------------------------------------- 1 | # nextpnr 2 | 3 | /*.bin 4 | /*.json 5 | /*.asc 6 | 7 | # Build artefacts 8 | 9 | /*.h 10 | 11 | -------------------------------------------------------------------------------- /rtl/demo/Makefile: -------------------------------------------------------------------------------- 1 | FPGA_PACKAGE = tq144 2 | FPGA_DEVICE = hx1k 3 | 4 | ### 5 | 6 | PROJ = picohx_demo 7 | TOP = $(PROJ)_top 8 | 9 | ICE40_PIN_DEF = ../data/picohx.pcf 10 | 11 | SOURCES := \ 12 | $(TOP).v \ 13 | debouncer.v 14 | 15 | VIDEO_SOURCES := $(addprefix video/, \ 16 | vga_timing.v \ 17 | vga_core.v \ 18 | dvi-12bit.v \ 19 | ) 20 | 21 | SOURCES += $(VIDEO_SOURCES) 22 | 23 | ### 24 | 25 | main: $(PROJ).bin 26 | header: $(PROJ).h 27 | 28 | count: $(SOURCES) 29 | yosys -p 'synth_ice40 -top $(TOP) -noflatten' $^ 30 | 31 | %.json: $(SOURCES) 32 | yosys -p 'synth_ice40 -top $(TOP) -json $@' $^ 33 | 34 | %.asc: $(ICE40_PIN_DEF) %.json 35 | nextpnr-ice40 --package $(FPGA_PACKAGE) --$(FPGA_DEVICE) --json $(filter-out $<,$^) --placer heap --seed 0 --pcf $< --asc $@ 36 | 37 | %.bin: %.asc 38 | icepack $< $@ 39 | 40 | %.h: %.bin 41 | xxd -i $^ > $@ 42 | 43 | ### 44 | 45 | prog: $(PROJ).bin 46 | ../../scripts/picoprog.py $< 47 | 48 | clean: 49 | rm -f $(PROJ).bin $(PROJ).asc $(PROJ).json $(PROJ).h 50 | 51 | .SECONDARY: 52 | .PHONY: main header clean prog 53 | 54 | -------------------------------------------------------------------------------- /rtl/demo/debouncer.v: -------------------------------------------------------------------------------- 1 | // debouncer.v 2 | // 3 | // Copyright (C) 2020 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: CERN-OHL-W-2.0 6 | 7 | `default_nettype none 8 | 9 | module debouncer #( 10 | parameter integer BTN_COUNT = 8 11 | ) ( 12 | input clk, 13 | input reset, 14 | 15 | input [BTN_COUNT - 1:0] btn, 16 | 17 | output reg [BTN_COUNT - 1:0] level, 18 | output reg [BTN_COUNT - 1:0] trigger, 19 | output reg [BTN_COUNT - 1:0] released 20 | ); 21 | localparam BTN_WIDTH = BTN_COUNT - 1; 22 | 23 | reg [BTN_WIDTH:0] btn_r [0:1]; 24 | 25 | reg [15:0] debounce_counter_common; 26 | wire debounce_counter_common_tick = debounce_counter_common[15]; 27 | 28 | reg [4:0] debounce_counter_button [0:BTN_WIDTH]; 29 | 30 | always @(posedge clk) begin 31 | btn_r[1] <= btn_r[0]; 32 | btn_r[0] <= btn; 33 | end 34 | 35 | reg [BTN_WIDTH:0] level_r; 36 | 37 | always @(posedge clk) begin 38 | if (reset) begin 39 | level <= 0; 40 | trigger <= 0; 41 | released <= 0; 42 | end else begin 43 | for (i = 0; i < BTN_COUNT; i = i + 1) begin 44 | if (debounce_counter_button[i][4]) begin 45 | level[i] <= btn_r[1][i]; 46 | end 47 | 48 | trigger[i] <= level[i] & ~level_r[i]; 49 | released[i] <= ~level[i] & level_r[i]; 50 | level_r[i] <= level[i]; 51 | end 52 | end 53 | end 54 | 55 | always @(posedge clk) begin 56 | if (reset) begin 57 | debounce_counter_common <= 0; 58 | end else begin 59 | debounce_counter_common <= (debounce_counter_common_tick ? 0 : debounce_counter_common + 1); 60 | end 61 | end 62 | 63 | always @(posedge clk) begin 64 | if (reset) begin 65 | for (i = 0; i < BTN_COUNT; i = i + 1) begin 66 | debounce_counter_button[i] <= 0; 67 | end 68 | end else begin 69 | for (i = 0; i < BTN_COUNT; i = i + 1) begin 70 | if ((btn_r[0][i] == btn_r[1][i])) begin 71 | if (debounce_counter_common_tick && !debounce_counter_button[i][4]) begin 72 | debounce_counter_button[i] <= debounce_counter_button[i] + 1; 73 | end 74 | end else begin 75 | debounce_counter_button[i] <= 0; 76 | end 77 | end 78 | end 79 | end 80 | 81 | integer i; 82 | 83 | endmodule 84 | -------------------------------------------------------------------------------- /rtl/demo/picohx_demo_top.v: -------------------------------------------------------------------------------- 1 | // picohx_demo_top.v 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: CERN-OHL-W-2.0 6 | 7 | `default_nettype none 8 | 9 | module picohx_demo_top ( 10 | input clk_in, 11 | 12 | output [7:0] led, 13 | 14 | input btn_a, 15 | input btn_b, 16 | 17 | // PMOD-C 18 | 19 | output pmod_c1, 20 | output pmod_c2, 21 | output pmod_c3, 22 | output pmod_c4, 23 | 24 | output pmod_c7, 25 | output pmod_c8, 26 | output pmod_c9, 27 | output pmod_c10, 28 | 29 | // PMOD-D 30 | 31 | output pmod_d1, 32 | output pmod_d2, 33 | output pmod_d3, 34 | output pmod_d4, 35 | 36 | output pmod_d7, 37 | output pmod_d8, 38 | output pmod_d9, 39 | output pmod_d10 40 | ); 41 | // --- PLL --- 42 | 43 | wire clk_12m = clk_in; 44 | wire clk_20m; 45 | wire clk_40m; 46 | wire pll_locked; 47 | 48 | SB_PLL40_2F_PAD #( 49 | .DIVR(4'b0000), 50 | .DIVF(7'b0110100), 51 | .DIVQ(3'b100), 52 | .FILTER_RANGE(3'b001), 53 | .FEEDBACK_PATH("SIMPLE"), 54 | .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), 55 | .FDA_FEEDBACK(4'b0000), 56 | .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), 57 | .FDA_RELATIVE(4'b0000), 58 | .SHIFTREG_DIV_MODE(2'b00), 59 | .PLLOUT_SELECT_PORTA("GENCLK"), 60 | .PLLOUT_SELECT_PORTB("GENCLK_HALF") 61 | ) pll ( 62 | .PACKAGEPIN(clk_12m), 63 | .PLLOUTGLOBALA(clk_40m), 64 | .PLLOUTGLOBALB(clk_20m), 65 | .LOCK(pll_locked), 66 | .EXTFEEDBACK(), 67 | .DYNAMICDELAY(), 68 | .RESETB(1'b1), 69 | .BYPASS(1'b0), 70 | .LATCHINPUTVALUE() 71 | ); 72 | 73 | wire reset = !reset_counter[3]; 74 | reg [3:0] reset_counter = 0; 75 | 76 | always @(posedge clk_20m) begin 77 | if (!pll_locked) begin 78 | reset_counter <= 0; 79 | end else if (reset) begin 80 | reset_counter <= reset_counter + 1; 81 | end 82 | end 83 | 84 | // --- LED --- 85 | 86 | reg [31:0] counter; 87 | reg count_enabled; 88 | 89 | assign led[7:0] = counter[29:22]; 90 | 91 | always @(posedge clk_20m) begin 92 | if (count_enabled) begin 93 | counter <= counter + 1; 94 | end else if (btn_a_trigger) begin 95 | counter = counter >> 1; 96 | end 97 | end 98 | 99 | always @(posedge clk_20m) begin 100 | if (reset) begin 101 | count_enabled <= 0; 102 | end else if (btn_b_trigger) begin 103 | count_enabled <= !count_enabled; 104 | end 105 | end 106 | 107 | // --- Buttons --- 108 | 109 | wire btn_a_level; 110 | wire btn_b_level; 111 | wire btn_a_trigger; 112 | wire btn_b_trigger; 113 | 114 | debouncer #( 115 | .BTN_COUNT(4) 116 | ) debouncer ( 117 | .clk(clk_20m), 118 | .reset(reset), 119 | 120 | .btn({btn_b, btn_a}), 121 | .level({btn_b_level, btn_a_level}), 122 | .trigger({btn_a_trigger, btn_b_trigger}) 123 | ); 124 | 125 | reg video_mode; 126 | 127 | always @(posedge clk_20m) begin 128 | if (reset) begin 129 | video_mode <= 0; 130 | end else if (btn_a_trigger) begin 131 | video_mode <= !video_mode; 132 | end 133 | end 134 | 135 | // --- Video --- 136 | 137 | wire vga_de; 138 | wire vga_ck; 139 | wire vga_hs; 140 | wire vga_vs; 141 | wire [23:0] vga_rgb; 142 | wire [7:0] r; 143 | wire [7:0] g; 144 | wire [7:0] b; 145 | 146 | vga_core vga_core( 147 | .clk_dot(clk_40m), 148 | .reset(reset), 149 | 150 | .random_num(0 /*random_num[31:0]*/), 151 | .color_3b(1'b0), 152 | .mode_bit(video_mode), 153 | .vga_active(vga_de), 154 | .vga_hsync(vga_hs), 155 | .vga_vsync(vga_vs), 156 | .vga_pixel_rgb(vga_rgb[23:0]) 157 | ); 158 | 159 | assign r = vga_rgb[23:16]; 160 | assign g = vga_rgb[15:8]; 161 | assign b = vga_rgb[7:0]; 162 | 163 | // PMOD assignment: 164 | 165 | assign vga_ck = clk_40m; 166 | 167 | // 12b for dual-PMOD: 168 | 169 | assign { 170 | pmod_c1, pmod_c2, pmod_c3, pmod_c4, pmod_c7, pmod_c8, pmod_c9, pmod_c10 171 | } = {r[7], r[5], g[7], g[5], r[6], r[4], g[6], g[4]}; 172 | 173 | assign { 174 | pmod_d1, pmod_d2, pmod_d3, pmod_d4, pmod_d7, pmod_d8, pmod_d9, pmod_d10 175 | } = {b[7], vga_ck, b[4], vga_hs, b[6], b[5], vga_de, vga_vs}; 176 | 177 | endmodule 178 | -------------------------------------------------------------------------------- /rtl/demo/video/dvi-12bit.v: -------------------------------------------------------------------------------- 1 | /* **************************************************************************** 2 | -- (C) Copyright 2017 Kevin M. Hubbard @ Black Mess Labs - All rights reserved. 3 | -- Source file: top.v 4 | -- Date: December 2017 5 | -- Author: khubbard 6 | -- Description: Spartan3 Test Design 7 | -- Language: Verilog-2001 and VHDL-1993 8 | -- Simulation: Mentor-Modelsim 9 | -- Synthesis: Xilinst-XST 10 | -- License: This project is licensed with the CERN Open Hardware Licence 11 | -- v1.2. You may redistribute and modify this project under the 12 | -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl). 13 | -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED 14 | -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY 15 | -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL 16 | -- v.1.2 for applicable Conditions. 17 | -- 18 | -- 3b Module - Facing module pins 19 | -- ------------------------------- 20 | -- | 1-GRN 3-CLK 5-HS 7-NC GND 3V | 21 | -- | 0-RED 2-BLU 4-DE 6-VS GND 3V | 22 | -- ___|_______________________________|___ 23 | -- | BML HDMI 3b color PMOD board | 24 | -- --------------------------------------- 25 | -- pmod_*_*<0> = red 26 | -- pmod_*_*<1> = green 27 | -- pmod_*_*<2> = blue 28 | -- pmod_*_*<3> = pixel_clock 29 | -- pmod_*_*<4> = data_enable 30 | -- pmod_*_*<5> = hsync 31 | -- pmod_*_*<6> = vsync 32 | -- pmod_*_*<7> = nc 33 | -- 34 | -- 35 | -- 36 | -- 12b Module - Facing module pins 37 | -- ---------------------------- ---------------------------- 38 | -- | 1-R3 3-R1 5-G3 7-G1 GND 3V | | 1-B3 3-ck 5-B0 7-HS GND 3V | 39 | -- | 0-R2 2-R0 4-G2 6-G0 GND 3V | | 0-B2 2-B1 4-DE 6-VS GND 3V | 40 | -- ___|____________________________|______|____________________________|__ 41 | -- | BML HDMI 12b color PMOD board | 42 | -- ----------------------------------------------------------------------- 43 | -- pmod_*_*<0> = r[2] pmod_*_*<0> = b[2] 44 | -- pmod_*_*<1> = r[3] pmod_*_*<1> = b[3] 45 | -- pmod_*_*<2> = r[0] pmod_*_*<2> = b[1] 46 | -- pmod_*_*<3> = r[1] pmod_*_*<3> = ck 47 | -- pmod_*_*<4> = g[2] pmod_*_*<4> = de 48 | -- pmod_*_*<5> = g[3] pmod_*_*<5> = b[0] 49 | -- pmod_*_*<6> = g[0] pmod_*_*<6> = vs 50 | -- pmod_*_*<7> = g[1] pmod_*_*<7> = hs 51 | -- 52 | -- Revision History: 53 | -- Ver# When Who What 54 | -- ---- -------- -------- --------------------------------------------------- 55 | -- 0.1 12.14.17 khubbard Creation 56 | -- ***************************************************************************/ 57 | `default_nettype none // Strictly enforce all nets to be declared 58 | 59 | module top 60 | ( 61 | input CLK, 62 | 63 | output LEDR_N, // on board red 64 | output LEDG_N, // on board green 65 | input BTN_N, // user button aka reset 66 | 67 | output P1A1, P1A2, P1A3, P1A4, P1A7, P1A8, P1A9, P1A10, 68 | output P1B1, P1B2, P1B3, P1B4, P1B7, P1B8, P1B9, P1B10 69 | 70 | 71 | );// module top 72 | 73 | 74 | wire reset_loc; 75 | wire clk_40m_tree; 76 | reg [29:0] led_cnt; 77 | reg [29:0] led_cnt_p1; 78 | wire vga_de; 79 | wire vga_ck; 80 | wire vga_hs; 81 | wire vga_vs; 82 | wire [23:0] vga_rgb; 83 | reg [31:0] random_num; 84 | wire [7:0] r; 85 | wire [7:0] g; 86 | wire [7:0] b; 87 | reg mode_bit; 88 | wire ok_led_loc; 89 | 90 | 91 | assign reset_loc = ~BTN_N; 92 | 93 | //----------------------------------------------------------------------------- 94 | // PLL. 95 | //----------------------------------------------------------------------------- 96 | SB_PLL40_PAD #( 97 | .DIVR(4'b0000), 98 | // 40MHz ish to be exact it is 39.750MHz 99 | //.DIVF(7'b0110111), // 42MHz 100 | .DIVF(7'b0110101), // 39.750MHz 101 | .DIVQ(3'b100), 102 | .FILTER_RANGE(3'b001), 103 | .FEEDBACK_PATH("SIMPLE"), 104 | .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), 105 | .FDA_FEEDBACK(4'b0000), 106 | .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), 107 | .FDA_RELATIVE(4'b0000), 108 | .SHIFTREG_DIV_MODE(2'b00), 109 | .PLLOUT_SELECT("GENCLK"), 110 | .ENABLE_ICEGATE(1'b0) 111 | ) usb_pll_inst ( 112 | .PACKAGEPIN(CLK), 113 | .PLLOUTCORE(clk_40m_tree), 114 | //.PLLOUTGLOBAL(), 115 | .EXTFEEDBACK(), 116 | .DYNAMICDELAY(), 117 | .RESETB(1'b1), 118 | .BYPASS(1'b0), 119 | .LATCHINPUTVALUE(), 120 | //.LOCK(), 121 | //.SDI(), 122 | //.SDO(), 123 | //.SCLK() 124 | ); 125 | 126 | //----------------------------------------------------------------------------- 127 | // Flash an LED. Also control the VGA demos, toggle between color pattern and 128 | // either a bouncing ball or moving lines. 129 | //----------------------------------------------------------------------------- 130 | always @ ( posedge clk_40m_tree or posedge reset_loc ) begin : proc_led 131 | if ( reset_loc == 1 ) begin 132 | random_num <= 32'd0; 133 | led_cnt <= 30'd0; 134 | led_cnt_p1 <= 30'd0; 135 | ok_led_loc <= 0; 136 | mode_bit <= 0; 137 | end else begin 138 | random_num <= random_num + 3; 139 | ok_led_loc <= 0; 140 | led_cnt_p1 <= led_cnt[29:0]; 141 | led_cnt <= led_cnt + 1; 142 | if ( led_cnt[19] == 1 ) begin 143 | ok_led_loc <= 1; 144 | end 145 | if ( led_cnt[29:27] == 3'd0 ) begin 146 | mode_bit <= 0; 147 | end else begin 148 | mode_bit <= 1; 149 | end 150 | 151 | end // clk+reset 152 | end // proc_led 153 | 154 | assign LEDG_N = ok_led_loc; 155 | 156 | // ---------------------------------------------------------------------------- 157 | // VGA Timing Generator 158 | // ---------------------------------------------------------------------------- 159 | vga_core u_vga_core 160 | ( 161 | .reset ( reset_loc ), 162 | .random_num ( random_num[31:0] ), 163 | .color_3b ( 1'b0 ), 164 | .mode_bit ( mode_bit ), 165 | .clk_dot ( clk_40m_tree ), 166 | .vga_active ( vga_de ), 167 | .vga_hsync ( vga_hs ), 168 | .vga_vsync ( vga_vs ), 169 | .vga_pixel_rgb ( vga_rgb[23:0] ) 170 | ); 171 | assign r = vga_rgb[23:16]; 172 | assign g = vga_rgb[15:8]; 173 | assign b = vga_rgb[7:0]; 174 | 175 | 176 | // ---------------------------------------------------------------------------- 177 | // Assign the PMOD(s) for either 3b or 12b HDMI Module from Black Mesa Labs 178 | // DDR Flop to Mirror pixel clock to TFP410 179 | // ---------------------------------------------------------------------------- 180 | //FDDRCPE u1_FDDRCPE 181 | //( 182 | // .C0 ( clk_40m_tree ), .C1 ( ~ clk_40m_tree ), 183 | // .CE ( 1'b1 ), 184 | // .CLR ( 1'b0 ), .PRE ( 1'b0 ), 185 | // .D0 ( 1'b1 ), .D1 ( 1'b0 ), 186 | // .Q ( vga_ck ) 187 | //); 188 | 189 | assign vga_ck = clk_40m_tree; 190 | 191 | // 3b for single-PMOD 192 | //assign {P1A1, P1A2, P1A3, P1A4, P1A7, P1A8, P1A9, P1A10} = 193 | // {g[7], vga_ck, vga_hs, 1'b0, r[7], b[7], vga_de, vga_vs}; 194 | 195 | 196 | // 12b for dual-PMOD 197 | assign {P1A1, P1A2, P1A3, P1A4, P1A7, P1A8, P1A9, P1A10} = 198 | {r[7], r[5], g[7], g[5], r[6], r[4], g[6], g[4]}; 199 | assign {P1B1, P1B2, P1B3, P1B4, P1B7, P1B8, P1B9, P1B10} = 200 | {b[7], vga_ck, b[4], vga_hs, b[6], b[5], vga_de, vga_vs}; 201 | 202 | endmodule // top.v 203 | -------------------------------------------------------------------------------- /rtl/demo/video/vga_core.v: -------------------------------------------------------------------------------- 1 | /* **************************************************************************** 2 | -- (C) Copyright 2017 Kevin M. Hubbard @ Black Mesa Labs - All rights reserved. 3 | -- Source file: vga_core.v 4 | -- Date: 12.14.2017 5 | -- Author: khubbard 6 | -- Description: Test design for VGA core. 7 | -- Language: Verilog-2001 and VHDL-1993 8 | -- Simulation: Mentor-Modelsim 9 | -- Synthesis: Xilinst-XST 10 | -- License: This project is licensed with the CERN Open Hardware Licence 11 | -- v1.2. You may redistribute and modify this project under the 12 | -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl). 13 | -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED 14 | -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY 15 | -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL 16 | -- v.1.2 for applicable Conditions. 17 | -- 18 | -- Revision History: 19 | -- Ver# When Who What 20 | -- ---- -------- -------- --------------------------------------------------- 21 | -- 0.1 12.14.17 khubbard Creation 22 | -- ***************************************************************************/ 23 | `default_nettype none // Strictly enforce all nets to be declared 24 | 25 | module vga_core 26 | ( 27 | input wire reset, 28 | input wire color_3b, // 0 for 12b color, 1 for 3b color 29 | input wire mode_bit, // 0 for test pattern, 1 for demos 30 | input wire clk_dot, // 40 MHz dot clock 31 | input wire [31:0] random_num, // seed for color and direction changes 32 | output wire [23:0] vga_pixel_rgb, // Output pixel in Red,Green,Blue 33 | output wire vga_active, // aka DE 34 | output wire vga_hsync, // aka HS 35 | output wire vga_vsync // aka VS 36 | ); 37 | 38 | reg [15:0] u0_pel_x; 39 | reg [15:0] u0_pel_y; 40 | reg [23:0] vga_rgb_tp; 41 | reg [23:0] vga_rgb_ball; 42 | reg [23:0] vga_rgb_line; 43 | reg [23:0] vga_rgb; 44 | wire [7:0] ramp; 45 | reg [15:0] ball_x_dir; 46 | reg [15:0] ball_y_dir; 47 | reg [23:0] ball_x_pos; 48 | reg [23:0] ball_y_pos; 49 | reg [3:0] dir_chg_sr; 50 | reg [23:0] ball_rgb; 51 | reg [3:0] demo_mode; 52 | reg mode_bit_p1; 53 | reg [15:0] line_x_pos; 54 | reg [15:0] line_y_pos; 55 | reg [23:0] line_rgb; 56 | 57 | 58 | wire u0_vid_new_frame; 59 | wire u0_vid_new_line; 60 | wire u0_vid_active; 61 | wire u0_vga_hsync; 62 | wire u0_vga_vsync; 63 | 64 | assign vga_active = u0_vid_active; 65 | assign vga_hsync = u0_vga_hsync; 66 | assign vga_vsync = u0_vga_vsync; 67 | assign vga_pixel_rgb = vga_rgb[23:0]; 68 | assign ramp = { u0_pel_x[6:0], 1'b0 }; 69 | 70 | 71 | // ---------------------------------------------------------------------------- 72 | // RGB Output Mux: Drive RGB with Either Test Pattern or one of two demos 73 | // ---------------------------------------------------------------------------- 74 | always @ ( posedge clk_dot ) begin : proc_out_mux 75 | begin 76 | mode_bit_p1 <= mode_bit; 77 | if ( color_3b == 0 ) begin 78 | if ( mode_bit == 0 ) begin 79 | vga_rgb <= vga_rgb_tp[23:0]; 80 | end else begin 81 | if ( mode_bit_p1 == 0 ) begin 82 | demo_mode <= ~demo_mode[3:0]; 83 | end 84 | if ( demo_mode[0] == 0 ) begin 85 | vga_rgb <= vga_rgb_ball[23:0]; 86 | end else begin 87 | vga_rgb <= vga_rgb_line[23:0]; 88 | end 89 | end 90 | end else begin 91 | if ( mode_bit == 0 ) begin 92 | vga_rgb[23:16] <= ( vga_rgb_tp[23:16] >= 8'd128 ) ? 8'hFF : 8'h00; 93 | vga_rgb[15:8 ] <= ( vga_rgb_tp[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00; 94 | vga_rgb[7:0 ] <= ( vga_rgb_tp[7:0 ] >= 8'd128 ) ? 8'hFF : 8'h00; 95 | end else begin 96 | if ( mode_bit_p1 == 0 ) begin 97 | demo_mode <= ~demo_mode[3:0]; 98 | end 99 | if ( demo_mode[0] == 0 ) begin 100 | vga_rgb[23:16] <= ( vga_rgb_ball[23:16] >= 8'd128 ) ? 8'hFF : 8'h00; 101 | vga_rgb[15:8 ] <= ( vga_rgb_ball[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00; 102 | vga_rgb[7:0 ] <= ( vga_rgb_ball[7:0 ] >= 8'd128 ) ? 8'hFF : 8'h00; 103 | end else begin 104 | vga_rgb[23:16] <= ( vga_rgb_line[23:16] >= 8'd128 ) ? 8'hFF : 8'h00; 105 | vga_rgb[15:8 ] <= ( vga_rgb_line[15:8 ] >= 8'd128 ) ? 8'hFF : 8'h00; 106 | vga_rgb[7:0 ] <= ( vga_rgb_line[7:0 ] >= 8'd128 ) ? 8'hFF : 8'h00; 107 | end 108 | end 109 | end 110 | end 111 | end // proc_out_mux 112 | 113 | 114 | // ---------------------------------------------------------------------------- 115 | // Moving Lines 116 | // ---------------------------------------------------------------------------- 117 | always @ ( posedge clk_dot ) begin : proc_line 118 | begin 119 | if ( mode_bit == 0 ) begin 120 | line_x_pos <= 16'd400; 121 | line_y_pos <= 16'd300; 122 | line_rgb <= random_num[23:0];// Change color 123 | end else begin 124 | if ( u0_vid_new_frame == 1 ) begin 125 | line_x_pos <= line_x_pos - 1; 126 | line_y_pos <= line_y_pos - 1; 127 | if ( line_x_pos == 16'd0 || line_y_pos == 16'd0 ) begin 128 | line_x_pos <= 16'd400; 129 | line_y_pos <= 16'd300; 130 | line_rgb <= random_num[23:0];// Change color 131 | end 132 | end 133 | vga_rgb_line[23:0] <= { 8'd0, 8'd0, 8'd0 }; 134 | if ( u0_pel_x == 16'd400 - line_x_pos[15:0] || 135 | u0_pel_x == 16'd400 + line_x_pos[15:0] || 136 | u0_pel_y == 16'd300 - line_y_pos[15:0] || 137 | u0_pel_y == 16'd300 + line_y_pos[15:0] ) begin 138 | vga_rgb_line[23:0] <= { 1'b1, line_rgb[22:0] }; 139 | end 140 | end 141 | end // clk+reset 142 | end // proc_line 143 | 144 | 145 | // ---------------------------------------------------------------------------- 146 | // Bouncing Ball 147 | // ---------------------------------------------------------------------------- 148 | always @ ( posedge clk_dot ) begin : proc_ball 149 | begin 150 | if ( mode_bit == 0 ) begin 151 | ball_x_pos <= {8'd0, 8'd400, 8'd0 }; // Start in center of 800x600 152 | ball_y_pos <= {8'd0, 8'd300, 8'd0 }; 153 | ball_rgb <= random_num[23:0]; // Get a random RGB Ball color 154 | ball_x_dir <= { 2'b01, random_num[11:2] };// 4bit int,8bit fract direction 155 | ball_y_dir <= { 2'b01, random_num[23:14] };// 4bit int,8bit fract direction 156 | end else begin 157 | // Move the ball every VSYNC and check for out of bounds. 158 | // If out of bounds this VSYNC, but not previous VSYNC then invert the 159 | // direction vectors. This effectively bounces a ball off perimeter wall 160 | if ( u0_vid_new_frame == 1 ) begin 161 | dir_chg_sr <= { dir_chg_sr[2:0], 1'b0 }; 162 | ball_x_pos <= ball_x_pos + { {12{ball_x_dir[11]}}, ball_x_dir[11:0] }; 163 | ball_y_pos <= ball_y_pos + { {12{ball_y_dir[11]}}, ball_y_dir[11:0] }; 164 | 165 | if ( ball_x_pos[23:8] < 32 && dir_chg_sr == 4'd0 ) begin 166 | ball_x_dir <= ~ ball_x_dir[11:0]; 167 | dir_chg_sr[0] <= 1; 168 | end else if ( ball_x_pos[23:8] > 768 && dir_chg_sr == 4'd0 ) begin 169 | ball_x_dir <= ~ ball_x_dir[11:0]; 170 | dir_chg_sr[0] <= 1; 171 | end 172 | if ( ball_y_pos[23:8] < 32 && dir_chg_sr == 4'd0 ) begin 173 | ball_y_dir <= ~ ball_y_dir[11:0]; 174 | dir_chg_sr[0] <= 1; 175 | end else if ( ball_y_pos[23:8] > 550 && dir_chg_sr == 4'd0 ) begin 176 | ball_y_dir <= ~ ball_y_dir[11:0]; 177 | dir_chg_sr[0] <= 1; 178 | end 179 | if ( dir_chg_sr[0] == 1 ) begin 180 | ball_rgb <= random_num[23:0];// Change ball color every bounce 181 | end 182 | end 183 | 184 | vga_rgb_ball[23:0] <= { 8'h00, 8'h00, 8'h00 }; 185 | // ~Ball~ is actually a 16x16 square centered around the ball x,y 186 | if ( u0_pel_x > ball_x_pos[23:8] - 16'd8 && 187 | u0_pel_x < ball_x_pos[23:8] + 16'd8 && 188 | u0_pel_y > ball_y_pos[23:8] - 16'd8 && 189 | u0_pel_y < ball_y_pos[23:8] + 16'd8 ) begin 190 | vga_rgb_ball[23:0] <= { 1'b1, ball_rgb[22:0] }; 191 | end 192 | end 193 | end // clk+reset 194 | end // proc_ball 195 | 196 | 197 | // ---------------------------------------------------------------------------- 198 | // Test Pattern 199 | // ---------------------------------------------------------------------------- 200 | always @ ( posedge clk_dot ) begin : proc_test_pattern 201 | begin 202 | // Red Green Blue 203 | if ( u0_pel_x[9:7] == 3'd6 ) begin 204 | vga_rgb_tp <= { ramp, ramp, ramp };// White 205 | end else if ( u0_pel_x[9:7] == 3'd5 ) begin 206 | vga_rgb_tp <= { ramp, ramp, 8'd0 };// Yellow 207 | end else if ( u0_pel_x[9:7] == 3'd4 ) begin 208 | vga_rgb_tp <= { 8'd0, ramp, ramp };// Cyan 209 | end else if ( u0_pel_x[9:7] == 3'd3 ) begin 210 | vga_rgb_tp <= { 8'd0, ramp, 8'd0 };// Green 211 | end else if ( u0_pel_x[9:7] == 3'd2 ) begin 212 | vga_rgb_tp <= { ramp, 8'd0, ramp };// Magenta 213 | end else if ( u0_pel_x[9:7] == 3'd1 ) begin 214 | vga_rgb_tp <= { ramp, 8'd0, 8'd0 };// Red 215 | end else if ( u0_pel_x[9:7] == 3'd0 ) begin 216 | vga_rgb_tp <= { 8'd0, 8'd0, ramp };// Blue 217 | end 218 | 219 | end // clk+reset 220 | end // proc_test_pattern 221 | 222 | 223 | // ---------------------------------------------------------------------------- 224 | // Raster Counters. Count the Pixel Location in X and Y 225 | // ---------------------------------------------------------------------------- 226 | always @ ( posedge clk_dot ) begin : proc_u0_raster_cnt 227 | begin 228 | if ( u0_vid_new_frame == 1 ) begin 229 | u0_pel_y <= 16'd0; 230 | end else if ( u0_vid_new_line == 1 ) begin 231 | if ( u0_pel_y == 16'hFFFF ) begin 232 | u0_pel_y <= 16'hFFFF;// Prevent rollover 233 | end else begin 234 | u0_pel_y <= u0_pel_y + 1; 235 | end 236 | end // if ( vid_new_frame == 1 ) begin 237 | 238 | if ( u0_vid_new_line == 1 ) begin 239 | u0_pel_x <= 16'd0; 240 | end else begin 241 | if ( u0_pel_x == 16'hFFFF ) begin 242 | u0_pel_x <= 16'hFFFF;// Prevent rollover 243 | end else begin 244 | u0_pel_x <= u0_pel_x + 1; 245 | end 246 | end // if ( vid_new_line == 1 ) begin 247 | 248 | end // clk+reset 249 | end // proc_u0_raster_cnt 250 | 251 | 252 | // ---------------------------------------------------------------------------- 253 | // VGA Timing Generator 254 | // ---------------------------------------------------------------------------- 255 | vga_timing u0_vga_timing 256 | ( 257 | .reset ( reset ), 258 | .clk_dot ( clk_dot ), 259 | .vid_new_frame ( u0_vid_new_frame ), 260 | .vid_new_line ( u0_vid_new_line ), 261 | .vid_active ( u0_vid_active ), 262 | .vga_hsync ( u0_vga_hsync ), 263 | .vga_vsync ( u0_vga_vsync ) 264 | ); 265 | 266 | 267 | endmodule // vga_core 268 | -------------------------------------------------------------------------------- /rtl/demo/video/vga_timing.v: -------------------------------------------------------------------------------- 1 | /* **************************************************************************** 2 | -- (C) Copyright 2013 Kevin M. Hubbard @ Black Mesa Labs - All rights reserved. 3 | -- Source file: vga_timing.v 4 | -- Date: April 20, 2013 5 | -- Author: khubbard 6 | -- Description: Generate Analog VGA Timing signals 7 | -- Language: Verilog-2001 and VHDL-1993 8 | -- Simulation: Mentor-Modelsim 9 | -- Synthesis: Xilinst-XST 10 | -- License: This project is licensed with the CERN Open Hardware Licence 11 | -- v1.2. You may redistribute and modify this project under the 12 | -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl). 13 | -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED 14 | -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY 15 | -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL 16 | -- v.1.2 for applicable Conditions. 17 | -- 18 | -- Binary 19 | -- -------- 2.5V ---------- 4V Node 20 | -- | FPGA |----->| 74ACT245 |----[220ohm]--+--[100ohm]-GND : Red 0,0.7V 21 | -- | |----->| |----[220ohm]--+--[100ohm]-GND : Grn 0,0.7V 22 | -- | |----->| |----[220ohm]--+--[100ohm]-GND : Blu 0,0.7V 23 | -- | |----->| |------------------------------> HSYNC 24 | -- | |----->| VCC=5V |------------------------------> VSYNC 25 | -- -------- ---------- 26 | -- 27 | -- 2 Shades 28 | -- R(0)----->| 74ACT245 |----[560ohm]--+--[100ohm]-GND : Red at + 29 | -- R(1)----->| |----[560ohm]--+ : Grn at + 30 | -- 31 | -- Note: Monitor has 75 termination for all signals, so the resistor divider 32 | -- was adjusted to get 0.7V Max on the line. Assert R(0) and R(1) for 33 | -- bright Red, or just one for a dimmer Red. 34 | -- 35 | -- Video Timing: 36 | -- |-BP-|Active Video|-FP| 37 | -- SYNC __/ \_____________________/ \_ 38 | -- 39 | -- HSYNC BP H FP Htotal VSYNC BP V FP Vtotal 40 | -- 800x600 40MHz 60Hz 128 88 800 40 1056 4 23 600 1 628 41 | -- 1024x768 65MHz 60Hz 136 160 1024 24 1344 6 29 768 3 806 42 | -- 1280x1024 108MHz 60Hz 112 248 1280 48 1688 3 38 1024 1 1066 43 | -- 640x1024 54MHz 60Hz 56 124 640 24 844 3 38 1024 1 1066 44 | -- 45 | -- Odd - Does this work ?? 46 | -- 800x480 40MHz 45Hz 128 88 800 127 1143 128 32 480 127 767 47 | -- 48 | -- Note: 40 / 10 = 4 x 27 = 108 49 | -- 50 | -- ---------------------------------------------------------------------------- 51 | -- The pinout for a standard 15-pin VGA-out connector Monitor side (male plug): 52 | -- 53 | -- /----------------------------------------------\ 54 | -- \ 1 2 3 4 5 / 55 | -- \ / 56 | -- \ 6 7 8 9 10 / 57 | -- \ / 58 | -- \ 11 12 13 14 15 / 59 | -- \------------------------------------/ 60 | -- 61 | -- 1: Red Video 0 - 0.7V 62 | -- 2: Green Video 0 - 0.7V 63 | -- 3: Blue Video 0 - 0.7V 64 | -- 4: Monitor ID 2 (To video card from monitor) 65 | -- 5: TTL Ground (Monitor self-test, used for testing purposes only) 66 | -- 67 | -- 6: Red Analog Ground 68 | -- 7: Green Analog Ground 69 | -- 8: Blue Analog Ground 70 | -- 9: Key (Plugged hole, not used for electronic signals) 71 | -- 10: Sync Ground (For both sync pins) 72 | -- 73 | -- 11: Monitor ID 0 (To video card from monitor) 74 | -- 12: Monitor ID 1 (To video card from monitor) 75 | -- 13: Horizontal Sync (To monitor from video card) 0 or 5.0V 76 | -- 14: Vertical Sync (To monitor from video card) 0 or 5.0V 77 | -- 15: Monitor ID 3 (To video card from monitor) 78 | -- 79 | -- 80 | -- vid_active ___/ \_____/ \____/ \______/ .... / \___/ \___ 81 | -- vid_new_frame _/ \___________________________________________________/ \___ 82 | -- vid_new_line _/ \________/ \_________/ \_________/ \__ .... / \_____/ \___ 83 | -- 0 1 2 3 1023 84 | -- 85 | -- VGA to HDMI Converter $25 from Amazon 86 | -- IO Crest VGA to HDMI Convertor with Audio support (SY-ADA31025). 87 | -- Supports Resolutions: 88 | -- 800x600 89 | -- 1024x768 1280x720 1280x800 1280x960 1280x1024 90 | -- 1360x768 91 | -- 1600x900 1600x1200 1680x1050 92 | -- 1920x1080 93 | -- 94 | -- Lilliput 7" 669GL LCD Display 95 | -- Native Resolution 800x480. Accepts HDMI 1920x1080 96 | -- 97 | -- Revision History: 98 | -- Ver# When Who What 99 | -- ---- -------- -------- --------------------------------------------------- 100 | -- 0.1 06.20.08 khubbard Creation 101 | -- ***************************************************************************/ 102 | `default_nettype none // Strictly enforce all nets to be declared 103 | 104 | 105 | module vga_timing 106 | ( 107 | input wire reset, 108 | input wire clk_dot, 109 | output reg vid_new_frame, 110 | output reg vid_new_line, 111 | output reg vid_active, 112 | output reg vga_hsync, 113 | output reg vga_vsync 114 | );// module vga_timing 115 | 116 | // 800x600 40MHz 60Hz 117 | `define def_h_sync 16'd128 118 | `define def_h_bp 16'd88 119 | `define def_h_actv 16'd800 120 | `define def_h_fp 16'd40 121 | `define def_h_total 16'd1056 122 | `define def_v_sync 16'd4 123 | `define def_v_bp 16'd23 124 | `define def_v_actv 16'd600 125 | `define def_v_fp 16'd1 126 | `define def_v_total 16'd628 127 | 128 | // 1280x1024 108MHz 60Hz 129 | /* 130 | `define def_h_sync 16'd112 131 | `define def_h_bp 16'd248 132 | `define def_h_actv 16'd1280 133 | `define def_h_fp 16'd48 134 | `define def_h_total 16'd1688 135 | `define def_v_sync 16'd3 136 | `define def_v_bp 16'd38 137 | `define def_v_actv 16'd1024 138 | `define def_v_fp 16'd1 139 | `define def_v_total 16'd1066 140 | */ 141 | 142 | /* Attempt at 480p with 27.7MHz 60 Hz */ 143 | /* From http://www.3dexpress.de/displayconfigx/timings.html */ 144 | /* 145 | `define def_h_sync 16'd40 146 | `define def_h_bp 16'd96 147 | `define def_h_actv 16'd720 148 | `define def_h_fp 16'd24 149 | `define def_h_total 16'd880 150 | 151 | `define def_v_sync 16'd3 152 | `define def_v_bp 16'd32 153 | `define def_v_actv 16'd480 154 | `define def_v_fp 16'd10 155 | `define def_v_total 16'd525 156 | */ 157 | 158 | `define state_h_sync 2'd0 159 | `define state_h_bp 2'd1 160 | `define state_h_actv 2'd2 161 | `define state_h_fp 2'd3 162 | 163 | `define state_v_sync 2'd0 164 | `define state_v_bp 2'd1 165 | `define state_v_actv 2'd2 166 | `define state_v_fp 2'd3 167 | 168 | reg [15:0] cnt_h; 169 | reg [15:0] cnt_v; 170 | reg [1:0] fsm_h; 171 | reg [1:0] fsm_v; 172 | reg hsync_loc; 173 | reg vsync_loc; 174 | reg vsync_loc_p1; 175 | reg h_rollover; 176 | 177 | 178 | //----------------------------------------------------------------------------- 179 | // Flop the outputs 180 | //----------------------------------------------------------------------------- 181 | always @ (posedge clk_dot or posedge reset ) begin : proc_dout 182 | if ( reset == 1 ) begin 183 | vga_hsync <= 1'b0; 184 | vga_vsync <= 1'b0; 185 | vsync_loc_p1 <= 1'b0; 186 | end else begin 187 | vga_hsync <= hsync_loc; 188 | vga_vsync <= vsync_loc; 189 | vsync_loc_p1 <= vsync_loc; 190 | end 191 | end 192 | 193 | 194 | //----------------------------------------------------------------------------- 195 | // VGA State Machine for Horizontal Timing 196 | //----------------------------------------------------------------------------- 197 | always @ (posedge clk_dot or posedge reset ) begin : proc_vga_h 198 | if ( reset == 1 ) begin 199 | hsync_loc <= 1'b0; 200 | vid_new_line <= 1'b0; 201 | vid_new_frame <= 1'b0; 202 | vid_active <= 1'b0; 203 | cnt_h <= 16'd1; 204 | fsm_h <= `state_h_sync; 205 | h_rollover <= 1'b1; 206 | end else begin 207 | h_rollover <= 1'b0; 208 | vid_new_line <= 1'b0; 209 | vid_new_frame <= 1'b0; 210 | vid_active <= 1'b0; 211 | hsync_loc <= 1'b0; // Default to HSYNC OFF 212 | cnt_h <= cnt_h + 16'd1; // Default to counting 213 | 214 | if ( fsm_h == `state_h_sync ) begin 215 | hsync_loc <= 1'b1; 216 | end 217 | if ( fsm_h == `state_h_actv && fsm_v == `state_v_actv ) begin 218 | vid_active <= 1'b1; 219 | end 220 | 221 | if ( fsm_h == `state_h_sync && cnt_h == `def_h_sync ) begin 222 | cnt_h <= 16'd1; 223 | fsm_h <= fsm_h + 2'd1; 224 | end 225 | if ( fsm_h == `state_h_bp && cnt_h == `def_h_bp ) begin 226 | cnt_h <= 16'd1; 227 | fsm_h <= fsm_h + 2'd1; 228 | vid_new_line <= 1'b1; 229 | if ( fsm_v == `state_v_actv && cnt_v == 16'd2 ) begin 230 | vid_new_frame <= 1'b1; 231 | end 232 | end 233 | if ( fsm_h == `state_h_actv && cnt_h == `def_h_actv ) begin 234 | cnt_h <= 16'd1; 235 | fsm_h <= fsm_h + 2'd1; 236 | end 237 | if ( fsm_h == `state_h_fp && cnt_h == `def_h_fp ) begin 238 | cnt_h <= 16'd1; 239 | fsm_h <= fsm_h + 2'd1; 240 | h_rollover <= 1'b1; 241 | end 242 | end 243 | end // proc_vga_h 244 | 245 | 246 | //----------------------------------------------------------------------------- 247 | // VGA State Machine for Vertical Timing 248 | //----------------------------------------------------------------------------- 249 | always @ (posedge clk_dot or posedge reset ) begin : proc_vga_v 250 | if ( reset == 1 ) begin 251 | cnt_v <= 16'd1; 252 | vsync_loc <= 1'b0; 253 | fsm_v <= `state_v_fp; 254 | end else begin 255 | if ( h_rollover == 1'b1 ) begin 256 | cnt_v <= cnt_v + 16'd1; // Default to counting 257 | vsync_loc <= 1'b0; // Default to VSYNC OFF 258 | if ( fsm_v == `state_v_sync && cnt_v == `def_v_sync ) begin 259 | cnt_v <= 16'd1; 260 | fsm_v <= fsm_v + 2'd1; 261 | end 262 | if ( fsm_v == `state_v_bp && cnt_v == `def_v_bp ) begin 263 | cnt_v <= 16'd1; 264 | fsm_v <= fsm_v + 2'd1; 265 | end 266 | if ( fsm_v == `state_v_actv && cnt_v == `def_v_actv ) begin 267 | cnt_v <= 16'd1; 268 | fsm_v <= fsm_v + 2'd1; 269 | end 270 | if ( fsm_v == `state_v_fp && cnt_v == `def_v_fp ) begin 271 | cnt_v <= 16'd1; 272 | fsm_v <= fsm_v + 2'd1; 273 | vsync_loc <= 1'b1; 274 | end 275 | 276 | if ( fsm_v == `state_v_sync && cnt_v != `def_v_sync ) begin 277 | vsync_loc <= 1'b1; 278 | end 279 | end 280 | end 281 | end // proc_vga_v 282 | 283 | 284 | endmodule // vga_timing 285 | -------------------------------------------------------------------------------- /scripts/picoprog.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # picoprog.py 4 | # 5 | # Copyright (C) 2021 Dan Rodrigues 6 | # 7 | # SPDX-License-Identifier: MIT 8 | 9 | import sys 10 | 11 | import usb.core 12 | import usb.util 13 | 14 | # Expecting 1 argument with bitstream to load 15 | if len(sys.argv) != 2: 16 | print("Usage: picoprog.py ") 17 | sys.exit(0) 18 | 19 | # Find Pico programmer device 20 | dev = usb.core.find(idVendor=0x2E8A, idProduct=0x0004) 21 | if dev is None: 22 | raise RuntimeError("Device not found") 23 | 24 | cfg = dev.get_active_configuration() 25 | intf = cfg[(2, 0)] 26 | 27 | outep = usb.util.find_descriptor( 28 | intf, 29 | # First OUT endpoint 30 | custom_match= \ 31 | lambda e: \ 32 | usb.util.endpoint_direction(e.bEndpointAddress) == \ 33 | usb.util.ENDPOINT_OUT) 34 | 35 | inep = usb.util.find_descriptor( 36 | intf, 37 | # First IN endpoint 38 | custom_match= \ 39 | lambda e: \ 40 | usb.util.endpoint_direction(e.bEndpointAddress) == \ 41 | usb.util.ENDPOINT_IN) 42 | 43 | assert inep is not None 44 | assert outep is not None 45 | 46 | # Load bitstream to send 47 | 48 | bitstream_path = sys.argv[1] 49 | bitstream_file = open(bitstream_path, 'rb') 50 | if bitstream_file is None: 51 | raise ValueError("Failed to open bitstream file: {:s}".format(bitstream_path)) 52 | 53 | bitstream = bitstream_file.read() 54 | bitstream_file.close() 55 | 56 | # Send bitstream over USB 57 | 58 | ctrl_request_type = 0x40 59 | 60 | ctrl_request_prepare = 0x01 61 | ctrl_request_finalize = 0x02 62 | 63 | dev.ctrl_transfer(ctrl_request_type, ctrl_request_prepare, 0, 0) 64 | outep.write(bitstream) 65 | dev.ctrl_transfer(ctrl_request_type, ctrl_request_finalize, 0, 0) 66 | -------------------------------------------------------------------------------- /software/.gitignore: -------------------------------------------------------------------------------- 1 | /build 2 | 3 | /ice40bitstream.bin 4 | 5 | -------------------------------------------------------------------------------- /software/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.12) 2 | 3 | include(pico_sdk_import.cmake) 4 | 5 | project(picohx_demo C CXX ASM) 6 | set(CMAKE_C_STANDARD 11) 7 | set(CMAKE_CXX_STANDARD 17) 8 | 9 | pico_sdk_init() 10 | 11 | add_executable(picohx_demo 12 | main.c 13 | usb_descriptors.c 14 | usb_uart.c 15 | usb_programmer.c 16 | fpga_spi.c 17 | get_serial.c 18 | ) 19 | 20 | pico_generate_pio_header(picohx_demo ${CMAKE_CURRENT_LIST_DIR}/spi.pio) 21 | 22 | # Pull in our pico_stdlib which pulls in commonly used features 23 | target_link_libraries(picohx_demo 24 | pico_stdlib 25 | hardware_pio 26 | tinyusb_device 27 | tinyusb_board 28 | pico_unique_id 29 | ) 30 | 31 | target_include_directories(picohx_demo PRIVATE .) 32 | 33 | # create map/bin/hex file etc. 34 | pico_add_extra_outputs(picohx_demo) 35 | 36 | -------------------------------------------------------------------------------- /software/fpga_spi.c: -------------------------------------------------------------------------------- 1 | // fpga_spi.c 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | #include 8 | 9 | #include "pico/stdlib.h" 10 | #include "hardware/pio.h" 11 | 12 | #include "fpga_spi.h" 13 | #include "phx_gpio.h" 14 | 15 | #include "spi.pio.h" 16 | 17 | void __not_in_flash_func(fpga_upload_bitstream)(const uint8_t *bitstream, size_t len) { 18 | uint cdone = PHX_GPIO_FPGA_CDONE; 19 | uint creset = PHX_GPIO_FPGA_CRESET; 20 | uint sck = PHX_GPIO_FPGA_SCK; 21 | uint sdo = PHX_GPIO_FPGA_SDO; 22 | uint sdi = PHX_GPIO_FPGA_SDI; 23 | uint ss = PHX_GPIO_FPGA_SS; 24 | 25 | // Init PIO for bistream sending 26 | PIO pio = pio0; 27 | 28 | // 1 of 4 SMs must be claimed 29 | uint sm = pio_claim_unused_sm(pio, true); 30 | // 25MHz, the max speed specified for iCE40 SPI 31 | float div = 125 / 25.0; 32 | fpga_spi_config_init(pio, sm, sdi, sck, div); 33 | 34 | // CDONE pullup 35 | gpio_init(cdone); 36 | gpio_set_dir(cdone, GPIO_IN); 37 | gpio_pull_up(cdone); 38 | 39 | // Assert SSB 40 | gpio_init(ss); 41 | gpio_put(ss, 0); 42 | gpio_set_dir(ss, GPIO_OUT); 43 | 44 | // Assert CRESETB for at least 200us 45 | gpio_init(creset); 46 | gpio_put(creset, 0); 47 | gpio_set_dir(creset, GPIO_OUT); 48 | busy_wait_us_32(300); 49 | // ..deassert CRESETB 50 | gpio_put(creset, 1); 51 | 52 | // 1200uS wait (CRAM clear) 53 | busy_wait_us_32(2000); 54 | 55 | // Deassert SS, send 8 clocks 56 | gpio_put(ss, 1); 57 | busy_wait_us_32(2); 58 | 59 | fpga_spi_config_put(pio0, 0, 0); 60 | fpga_spi_config_flush_fifo(pio0, 0); 61 | 62 | // ..then reassert 63 | gpio_put(ss, 0); 64 | 65 | // Send bitstream 66 | for (size_t i = 0; i < len; i++) 67 | fpga_spi_config_put(pio0, sm, bitstream[i]); 68 | 69 | // Send at least 100 clocks immediately after bitstream 70 | const uint dummy_bytes = 100 / 8 + 1; 71 | for (int i = 0; i < dummy_bytes; i++) 72 | fpga_spi_config_put(pio0, sm, 0); 73 | 74 | fpga_spi_config_flush_fifo(pio0, sm); 75 | 76 | // All PIO work is done now 77 | pio_sm_unclaim(pio, sm); 78 | 79 | // Check CDONE status to confirm successful config 80 | if (gpio_get(cdone)) { 81 | printf("%s: successfully programmed\n", __FUNCTION__); 82 | 83 | gpio_put(PICO_DEFAULT_LED_PIN, 1); 84 | } else { 85 | printf("%s: failed to program\n", __FUNCTION__); 86 | 87 | while (true) { 88 | gpio_put(PICO_DEFAULT_LED_PIN, 1); 89 | sleep_ms(200); 90 | gpio_put(PICO_DEFAULT_LED_PIN, 0); 91 | sleep_ms(200); 92 | } 93 | } 94 | } 95 | -------------------------------------------------------------------------------- /software/fpga_spi.h: -------------------------------------------------------------------------------- 1 | // fpga_spi.h 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | #include "pico/stdlib.h" 8 | 9 | void __not_in_flash_func(fpga_upload_bitstream)(const uint8_t *bitstream, size_t len); 10 | -------------------------------------------------------------------------------- /software/get_serial.c: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2021 Federico Zuccardi Merli 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | * 24 | */ 25 | 26 | #include 27 | #include "pico/unique_id.h" 28 | #include "get_serial.h" 29 | 30 | /* C string for iSerialNumber in USB Device Descriptor, two chars per byte + terminating NUL */ 31 | char usb_serial[PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2 + 1]; 32 | 33 | /* Why a uint8_t[8] array inside a struct instead of an uint64_t an inquiring mind might wonder */ 34 | static pico_unique_board_id_t uID; 35 | 36 | void usb_serial_init(void) 37 | { 38 | pico_get_unique_board_id(&uID); 39 | 40 | for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2; i++) 41 | { 42 | /* Byte index inside the uid array */ 43 | int bi = i / 2; 44 | /* Use high nibble first to keep memory order (just cosmetics) */ 45 | uint8_t nibble = (uID.id[bi] >> 4) & 0x0F; 46 | uID.id[bi] <<= 4; 47 | /* Binary to hex digit */ 48 | usb_serial[i] = nibble < 10 ? nibble + '0' : nibble + 'A' - 10; 49 | } 50 | } 51 | -------------------------------------------------------------------------------- /software/get_serial.h: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2021 Federico Zuccardi Merli 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | * 24 | */ 25 | 26 | #ifndef GET_SERIAL_H_ 27 | #define GET_SERIAL_H_ 28 | 29 | /* Contains unique serial number string (NUL terminated) after call to init_usb_serial */ 30 | extern char usb_serial[]; 31 | 32 | /* Fills unique_serial with the flash unique id */ 33 | extern void usb_serial_init(void); 34 | 35 | #endif 36 | -------------------------------------------------------------------------------- /software/main.c: -------------------------------------------------------------------------------- 1 | // main.c 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | #include "pico/stdlib.h" 8 | #include "hardware/clocks.h" 9 | 10 | #include "phx_gpio.h" 11 | #include "tusb.h" 12 | #include "get_serial.h" 13 | #include "usb_uart.h" 14 | #include "usb_programmer.h" 15 | #include "fpga_spi.h" 16 | 17 | #include "default_bitstream.h" 18 | 19 | int main() { 20 | #ifndef PICO_DEFAULT_LED_PIN 21 | #warning blink example requires a board with a regular LED 22 | #else 23 | // Default to Pico LED on 24 | const uint LED_PIN = PICO_DEFAULT_LED_PIN; 25 | gpio_init(LED_PIN); 26 | gpio_set_dir(LED_PIN, GPIO_OUT); 27 | gpio_put(LED_PIN, 1); 28 | 29 | // 48MHz / 4 = 12MHz clock output to FPGA 30 | const uint usb_clk = 48; 31 | const uint target_clk = 12; 32 | const uint clk_divisor = usb_clk / target_clk; 33 | clock_gpio_init( 34 | PHX_GPIO_FPGA_CLK_IN, 35 | CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 36 | clk_divisor 37 | ); 38 | 39 | // Program the included default bitstream 40 | // This can be replaced later at any time with the USB programmer script 41 | fpga_upload_bitstream(default_bitstream, default_bitstream_len); 42 | 43 | // USB init before entering main loop 44 | tusb_init(); 45 | stdio_usb_init(); 46 | 47 | while (true) { 48 | tud_task(); 49 | usb_prog_task(); 50 | } 51 | #endif 52 | } 53 | -------------------------------------------------------------------------------- /software/phx_gpio.h: -------------------------------------------------------------------------------- 1 | // phx_gpio.h 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | #define PHX_GPIO_FPGA_SDI 12 8 | #define PHX_GPIO_FPGA_SDO 13 9 | #define PHX_GPIO_FPGA_CRESET 18 10 | #define PHX_GPIO_FPGA_CDONE 19 11 | #define PHX_GPIO_FPGA_CLK_IN 21 12 | #define PHX_GPIO_FPGA_SS 26 13 | #define PHX_GPIO_FPGA_SCK 27 14 | -------------------------------------------------------------------------------- /software/pico_sdk_import.cmake: -------------------------------------------------------------------------------- 1 | # This is a copy of /external/pico_sdk_import.cmake 2 | 3 | # This can be dropped into an external project to help locate this SDK 4 | # It should be include()ed prior to project() 5 | 6 | if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) 7 | set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) 8 | message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") 9 | endif () 10 | 11 | if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) 12 | set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) 13 | message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") 14 | endif () 15 | 16 | if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) 17 | set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) 18 | message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") 19 | endif () 20 | 21 | set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") 22 | set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") 23 | set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") 24 | 25 | if (NOT PICO_SDK_PATH) 26 | if (PICO_SDK_FETCH_FROM_GIT) 27 | include(FetchContent) 28 | set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) 29 | if (PICO_SDK_FETCH_FROM_GIT_PATH) 30 | get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") 31 | endif () 32 | FetchContent_Declare( 33 | pico_sdk 34 | GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk 35 | GIT_TAG master 36 | ) 37 | if (NOT pico_sdk) 38 | message("Downloading Raspberry Pi Pico SDK") 39 | FetchContent_Populate(pico_sdk) 40 | set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) 41 | endif () 42 | set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) 43 | else () 44 | message(FATAL_ERROR 45 | "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." 46 | ) 47 | endif () 48 | endif () 49 | 50 | get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") 51 | if (NOT EXISTS ${PICO_SDK_PATH}) 52 | message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") 53 | endif () 54 | 55 | set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) 56 | if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) 57 | message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") 58 | endif () 59 | 60 | set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) 61 | 62 | include(${PICO_SDK_INIT_CMAKE_FILE}) 63 | -------------------------------------------------------------------------------- /software/spi.pio: -------------------------------------------------------------------------------- 1 | ; 2 | ; Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 | ; 4 | ; SPDX-License-Identifier: BSD-3-Clause 5 | ; 6 | 7 | // Effectively a Mode-3 SPI TX 8 | 9 | .program fpga_spi_config 10 | .side_set 1 11 | 12 | out x, 1 side 1 ; stall here, but still assert clock high 13 | mov pins, x side 0 14 | 15 | % c-sdk { 16 | static inline void fpga_spi_config_init(PIO pio, uint sm, uint data_pin, uint clk_pin, float clk_div) { 17 | uint offset = pio_add_program(pio, &fpga_spi_config_program); 18 | pio_gpio_init(pio, data_pin); 19 | pio_gpio_init(pio, clk_pin); 20 | pio_sm_set_consecutive_pindirs(pio, sm, data_pin, 1, true); 21 | pio_sm_set_consecutive_pindirs(pio, sm, clk_pin, 1, true); 22 | pio_sm_config c = fpga_spi_config_program_get_default_config(offset); 23 | sm_config_set_sideset_pins(&c, clk_pin); 24 | sm_config_set_out_pins(&c, data_pin, 1); 25 | sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX); 26 | sm_config_set_clkdiv(&c, clk_div); 27 | // Shift to left to get MSB-first (requires data to be left-justified, which we do with write replication) 28 | sm_config_set_out_shift(&c, false, true, 8); 29 | pio_sm_init(pio, sm, offset, &c); 30 | pio_sm_set_enabled(pio, sm, true); 31 | } 32 | 33 | // Use a byte write to replicate 8 bits across full 32 bit bus for free. This 34 | // gets the data both left- and right-justified in the FIFO! 35 | static inline void fpga_spi_config_put(PIO pio, uint sm, uint8_t x) { 36 | while (pio_sm_is_tx_fifo_full(pio, sm)) 37 | ; 38 | *(io_rw_8 *)&pio->txf[sm] = x; 39 | } 40 | 41 | static inline void fpga_spi_config_flush_fifo(PIO pio, uint sm) { 42 | uint32_t stall_mask = 1u << (PIO_FDEBUG_TXSTALL_LSB + sm); 43 | pio->fdebug = stall_mask; 44 | while (!(pio->fdebug & stall_mask)) 45 | ; 46 | } 47 | 48 | %} 49 | 50 | -------------------------------------------------------------------------------- /software/tusb_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2019 Ha Thach (tinyusb.org) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | * 24 | */ 25 | 26 | #ifndef _TUSB_CONFIG_H_ 27 | #define _TUSB_CONFIG_H_ 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | //-------------------------------------------------------------------- 34 | // COMMON CONFIGURATION 35 | //-------------------------------------------------------------------- 36 | 37 | // defined by compiler flags for flexibility 38 | #ifndef CFG_TUSB_MCU 39 | #error CFG_TUSB_MCU must be defined 40 | #endif 41 | 42 | #define CFG_TUSB_RHPORT0_MODE OPT_MODE_DEVICE 43 | 44 | #ifndef CFG_TUSB_OS 45 | #define CFG_TUSB_OS OPT_OS_PICO 46 | #endif 47 | 48 | #ifndef CFG_TUSB_MEM_SECTION 49 | #define CFG_TUSB_MEM_SECTION 50 | #endif 51 | 52 | #ifndef CFG_TUSB_MEM_ALIGN 53 | #define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) 54 | #endif 55 | 56 | //-------------------------------------------------------------------- 57 | // DEVICE CONFIGURATION 58 | //-------------------------------------------------------------------- 59 | 60 | #ifndef CFG_TUD_ENDPOINT0_SIZE 61 | #define CFG_TUD_ENDPOINT0_SIZE 64 62 | #endif 63 | 64 | //------------- CLASS -------------// 65 | #define CFG_TUD_HID 0 66 | #define CFG_TUD_CDC 1 67 | #define CFG_TUD_MSC 0 68 | #define CFG_TUD_MIDI 0 69 | #define CFG_TUD_VENDOR 1 70 | 71 | #define CFG_TUD_CDC_RX_BUFSIZE 64 72 | #define CFG_TUD_CDC_TX_BUFSIZE 64 73 | 74 | #define CFG_TUD_VENDOR_RX_BUFSIZE 8192 75 | #define CFG_TUD_VENDOR_TX_BUFSIZE 8192 76 | 77 | #ifdef __cplusplus 78 | } 79 | #endif 80 | 81 | #endif /* _TUSB_CONFIG_H_ */ 82 | -------------------------------------------------------------------------------- /software/usb_common.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. 3 | * 4 | * SPDX-License-Identifier: BSD-3-Clause 5 | */ 6 | 7 | #ifndef _USB_COMMON_H 8 | #define _USB_COMMON_H 9 | 10 | #include "pico/types.h" 11 | #include "hardware/structs/usb.h" 12 | 13 | // bmRequestType bit definitions 14 | #define USB_REQ_TYPE_STANDARD 0x00u 15 | #define USB_REQ_TYPE_TYPE_MASK 0x60u 16 | #define USB_REQ_TYPE_TYPE_CLASS 0x20u 17 | #define USB_REQ_TYPE_TYPE_VENDOR 0x40u 18 | 19 | #define USB_REQ_TYPE_RECIPIENT_MASK 0x1fu 20 | #define USB_REQ_TYPE_RECIPIENT_DEVICE 0x00u 21 | #define USB_REQ_TYPE_RECIPIENT_INTERFACE 0x01u 22 | #define USB_REQ_TYPE_RECIPIENT_ENDPOINT 0x02u 23 | 24 | #define USB_DIR_OUT 0x00u 25 | #define USB_DIR_IN 0x80u 26 | 27 | #define USB_TRANSFER_TYPE_CONTROL 0x0 28 | #define USB_TRANSFER_TYPE_ISOCHRONOUS 0x1 29 | #define USB_TRANSFER_TYPE_BULK 0x2 30 | #define USB_TRANSFER_TYPE_INTERRUPT 0x3 31 | #define USB_TRANSFER_TYPE_BITS 0x3 32 | 33 | // Descriptor types 34 | #define USB_DT_DEVICE 0x01 35 | #define USB_DT_CONFIG 0x02 36 | #define USB_DT_STRING 0x03 37 | #define USB_DT_INTERFACE 0x04 38 | #define USB_DT_ENDPOINT 0x05 39 | 40 | #define USB_REQUEST_GET_STATUS 0x0 41 | #define USB_REQUEST_CLEAR_FEATURE 0x01 42 | #define USB_REQUEST_SET_FEATURE 0x03 43 | #define USB_REQUEST_SET_ADDRESS 0x05 44 | #define USB_REQUEST_GET_DESCRIPTOR 0x06 45 | #define USB_REQUEST_SET_DESCRIPTOR 0x07 46 | #define USB_REQUEST_GET_CONFIGURATION 0x08 47 | #define USB_REQUEST_SET_CONFIGURATION 0x09 48 | #define USB_REQUEST_GET_INTERFACE 0x0a 49 | #define USB_REQUEST_SET_INTERFACE 0x0b 50 | #define USB_REQUEST_SYNC_FRAME 0x0c 51 | 52 | #define USB_REQUEST_MSC_GET_MAX_LUN 0xfe 53 | #define USB_REQUEST_MSC_RESET 0xff 54 | 55 | #define USB_FEAT_ENDPOINT_HALT 0x00 56 | #define USB_FEAT_DEVICE_REMOTE_WAKEUP 0x01 57 | #define USB_FEAT_TEST_MODE 0x02 58 | 59 | #define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05 60 | 61 | struct usb_setup_packet { 62 | uint8_t bmRequestType; 63 | uint8_t bRequest; 64 | uint16_t wValue; 65 | uint16_t wIndex; 66 | uint16_t wLength; 67 | } __packed; 68 | 69 | struct usb_descriptor { 70 | uint8_t bLength; 71 | uint8_t bDescriptorType; 72 | }; 73 | 74 | struct usb_device_descriptor { 75 | uint8_t bLength; 76 | uint8_t bDescriptorType; 77 | uint16_t bcdUSB; 78 | uint8_t bDeviceClass; 79 | uint8_t bDeviceSubClass; 80 | uint8_t bDeviceProtocol; 81 | uint8_t bMaxPacketSize0; 82 | uint16_t idVendor; 83 | uint16_t idProduct; 84 | uint16_t bcdDevice; 85 | uint8_t iManufacturer; 86 | uint8_t iProduct; 87 | uint8_t iSerialNumber; 88 | uint8_t bNumConfigurations; 89 | } __packed; 90 | 91 | struct usb_configuration_descriptor { 92 | uint8_t bLength; 93 | uint8_t bDescriptorType; 94 | uint16_t wTotalLength; 95 | uint8_t bNumInterfaces; 96 | uint8_t bConfigurationValue; 97 | uint8_t iConfiguration; 98 | uint8_t bmAttributes; 99 | uint8_t bMaxPower; 100 | } __packed; 101 | 102 | struct usb_interface_descriptor { 103 | uint8_t bLength; 104 | uint8_t bDescriptorType; 105 | uint8_t bInterfaceNumber; 106 | uint8_t bAlternateSetting; 107 | uint8_t bNumEndpoints; 108 | uint8_t bInterfaceClass; 109 | uint8_t bInterfaceSubClass; 110 | uint8_t bInterfaceProtocol; 111 | uint8_t iInterface; 112 | } __packed; 113 | 114 | struct usb_endpoint_descriptor { 115 | uint8_t bLength; 116 | uint8_t bDescriptorType; 117 | uint8_t bEndpointAddress; 118 | uint8_t bmAttributes; 119 | uint16_t wMaxPacketSize; 120 | uint8_t bInterval; 121 | } __packed; 122 | 123 | struct usb_endpoint_descriptor_long { 124 | uint8_t bLength; 125 | uint8_t bDescriptorType; 126 | uint8_t bEndpointAddress; 127 | uint8_t bmAttributes; 128 | uint16_t wMaxPacketSize; 129 | uint8_t bInterval; 130 | uint8_t bRefresh; 131 | uint8_t bSyncAddr; 132 | } __attribute__((packed)); 133 | 134 | #endif -------------------------------------------------------------------------------- /software/usb_descriptors.c: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2019 Ha Thach (tinyusb.org) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | * 24 | */ 25 | 26 | #include "tusb.h" 27 | #include "get_serial.h" 28 | 29 | //--------------------------------------------------------------------+ 30 | // Device Descriptors 31 | //--------------------------------------------------------------------+ 32 | tusb_desc_device_t const desc_device = { 33 | .bLength = sizeof(tusb_desc_device_t), 34 | .bDescriptorType = TUSB_DESC_DEVICE, 35 | .bcdUSB = 0x0110, // // USB Specification version 1.1 36 | .bDeviceClass = 0x00, // Each interface specifies its own 37 | .bDeviceSubClass = 0x00, // Each interface specifies its own 38 | .bDeviceProtocol = 0x00, 39 | .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, 40 | 41 | // FIXME: proper device IDs 42 | .idVendor = 0x2E8A, // Pi 43 | .idProduct = 0x0004, // Picoprobe 44 | // FIXME: 45 | 46 | .bcdDevice = 0x0100, // Version 01.00 47 | .iManufacturer = 0x01, 48 | .iProduct = 0x02, 49 | .iSerialNumber = 0x03, 50 | .bNumConfigurations = 0x01 51 | }; 52 | 53 | // Invoked when received GET DEVICE DESCRIPTOR 54 | // Application return pointer to descriptor 55 | uint8_t const * tud_descriptor_device_cb(void) { 56 | return (uint8_t const *) &desc_device; 57 | } 58 | 59 | //--------------------------------------------------------------------+ 60 | // Configuration Descriptor 61 | //--------------------------------------------------------------------+ 62 | 63 | enum { 64 | ITF_NUM_CDC_COM, 65 | ITF_NUM_CDC_DATA, 66 | ITF_NUM_PROG, 67 | ITF_NUM_TOTAL 68 | }; 69 | 70 | #define CDC_NOTIFICATION_EP_NUM 0x81 71 | #define CDC_DATA_OUT_EP_NUM 0x02 72 | #define CDC_DATA_IN_EP_NUM 0x83 73 | #define PROG_OUT_EP_NUM 0x04 74 | #define PROG_IN_EP_NUM 0x85 75 | 76 | #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_VENDOR_DESC_LEN) 77 | 78 | uint8_t const desc_configuration[] = { 79 | TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 500), 80 | 81 | // Interface 0 + 1 82 | TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_COM, 0, CDC_NOTIFICATION_EP_NUM, 64, CDC_DATA_OUT_EP_NUM, CDC_DATA_IN_EP_NUM, 64), 83 | 84 | // Interface 2 85 | TUD_VENDOR_DESCRIPTOR(ITF_NUM_PROG, 0, PROG_OUT_EP_NUM, PROG_IN_EP_NUM, 64) 86 | }; 87 | 88 | // Invoked when received GET CONFIGURATION DESCRIPTOR 89 | // Application return pointer to descriptor 90 | // Descriptor contents must exist long enough for transfer to complete 91 | uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { 92 | (void) index; // for multiple configurations 93 | return desc_configuration; 94 | } 95 | 96 | //--------------------------------------------------------------------+ 97 | // String Descriptors 98 | //--------------------------------------------------------------------+ 99 | 100 | // array of pointer to string descriptors 101 | char const* string_desc_arr [] = { 102 | (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) 103 | // Manufacturer 104 | "drr", 105 | // Product name 106 | "PicoHX iCE40 SPI programmer", 107 | // Serial 108 | usb_serial 109 | }; 110 | 111 | static uint16_t _desc_str[32]; 112 | 113 | // Invoked when received GET STRING DESCRIPTOR request 114 | // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete 115 | uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) { 116 | (void) langid; 117 | 118 | uint8_t chr_count; 119 | 120 | if (index == 0) { 121 | memcpy(&_desc_str[1], string_desc_arr[0], 2); 122 | chr_count = 1; 123 | } else { 124 | // Convert ASCII string into UTF-16 125 | if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0]))) { 126 | return NULL; 127 | } 128 | 129 | const char* str = string_desc_arr[index]; 130 | 131 | // Cap at max char 132 | chr_count = strlen(str); 133 | if ( chr_count > 31 ) chr_count = 31; 134 | 135 | for (uint8_t i=0; i 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | #include 8 | 9 | #include "pico/stdlib.h" 10 | #include "tusb.h" 11 | 12 | #include "usb_programmer.h" 13 | #include "fpga_spi.h" 14 | 15 | enum phx_ctrl_req { 16 | PHX_CTRL_REQ_PREPARE_BITSTREAM_LOAD = 0x01, 17 | PHX_CTRL_REQ_FINALIZE_BITSTREAM_LOAD = 0x02 18 | }; 19 | 20 | // Preload bitstream for simplicity 21 | // Could alternatively stream it assuming no interruptions 22 | static uint8_t bitstream[0x8000]; 23 | static size_t bitstream_index; 24 | 25 | void usb_prog_task() { 26 | if (!tud_vendor_available()) { 27 | return; 28 | } 29 | 30 | if (bitstream_index >= sizeof(bitstream)) { 31 | printf("%s: data available but buffer is exhausted\n", __FUNCTION__); 32 | return; 33 | } 34 | 35 | const size_t packet_size = 64; 36 | uint32_t rx_len = tud_vendor_read(&bitstream[bitstream_index], packet_size); 37 | if (rx_len == 0) { 38 | return; 39 | } 40 | 41 | bitstream_index += rx_len; 42 | } 43 | 44 | bool tud_vendor_control_request_cb(uint8_t rhport, tusb_control_request_t const *request) { 45 | // These control requests don't have a data phase so just immediately act on them 46 | switch (request->bRequest) { 47 | case PHX_CTRL_REQ_PREPARE_BITSTREAM_LOAD: 48 | bitstream_index = 0; 49 | return tud_control_status(rhport, request); 50 | case PHX_CTRL_REQ_FINALIZE_BITSTREAM_LOAD: 51 | fpga_upload_bitstream(bitstream, bitstream_index); 52 | return tud_control_status(rhport, request); 53 | default: 54 | printf("%s: unknown ctrl request: %x\n", __FUNCTION__, request->bRequest); 55 | return false; 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /software/usb_programmer.h: -------------------------------------------------------------------------------- 1 | // usb_programmer.h 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | void usb_prog_task(void); 8 | -------------------------------------------------------------------------------- /software/usb_uart.c: -------------------------------------------------------------------------------- 1 | // Mostly coped from the stdio_usb example 2 | 3 | #include "usb_uart.h" 4 | 5 | #include "tusb.h" 6 | 7 | #include "pico/stdio/driver.h" 8 | #include "pico/binary_info.h" 9 | #include "pico/mutex.h" 10 | #include "pico/time.h" 11 | 12 | #define PICO_STDIO_USB_STDOUT_TIMEOUT_US 500000 13 | #define PICO_STDIO_USB_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF 14 | 15 | static mutex_t stdio_usb_mutex; 16 | 17 | static void stdio_usb_out_chars(const char *buf, int length); 18 | static int stdio_usb_in_chars(char *buf, int length); 19 | 20 | stdio_driver_t stdio_usb = { 21 | .out_chars = stdio_usb_out_chars, 22 | .in_chars = stdio_usb_in_chars, 23 | #if PICO_STDIO_ENABLE_CRLF_SUPPORT 24 | .crlf_enabled = PICO_STDIO_USB_DEFAULT_CRLF 25 | #endif 26 | }; 27 | 28 | void stdio_usb_init() { 29 | mutex_init(&stdio_usb_mutex); 30 | stdio_set_driver_enabled(&stdio_usb, true); 31 | } 32 | 33 | static void stdio_usb_out_chars(const char *buf, int length) { 34 | static uint64_t last_avail_time; 35 | uint32_t owner; 36 | if (!mutex_try_enter(&stdio_usb_mutex, &owner)) { 37 | if (owner == get_core_num()) return; // would deadlock otherwise 38 | mutex_enter_blocking(&stdio_usb_mutex); 39 | } 40 | if (tud_cdc_connected()) { 41 | for (int i = 0; i < length;) { 42 | int n = length - i; 43 | int avail = tud_cdc_write_available(); 44 | if (n > avail) n = avail; 45 | if (n) { 46 | int n2 = tud_cdc_write(buf + i, n); 47 | tud_task(); 48 | tud_cdc_write_flush(); 49 | i += n2; 50 | last_avail_time = time_us_64(); 51 | } else { 52 | tud_task(); 53 | tud_cdc_write_flush(); 54 | if (!tud_cdc_connected() || 55 | (!tud_cdc_write_available() && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) { 56 | break; 57 | } 58 | } 59 | } 60 | } else { 61 | // reset our timeout 62 | last_avail_time = 0; 63 | } 64 | mutex_exit(&stdio_usb_mutex); 65 | } 66 | 67 | static int stdio_usb_in_chars(char *buf, int length) { 68 | // (Unsupported for now) 69 | return 0; 70 | } 71 | -------------------------------------------------------------------------------- /software/usb_uart.h: -------------------------------------------------------------------------------- 1 | // usb_uart.h 2 | // 3 | // Copyright (C) 2021 Dan Rodrigues 4 | // 5 | // SPDX-License-Identifier: MIT 6 | 7 | void stdio_usb_init(void); 8 | --------------------------------------------------------------------------------