├── LICENSE ├── README.md ├── build.sh ├── configuration.nix ├── cross-config.nix ├── kernel └── Pine64-PineCube-support.patch ├── sd-image.nix └── uboot ├── Pine64-PineCube-uboot-support.patch ├── default.nix └── spi-installer.nix /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2020 Daniel Fullmer 2 | 3 | Permission is hereby granted, free of charge, to any person obtaining a copy 4 | of this software and associated documentation files (the "Software"), to deal 5 | in the Software without restriction, including without limitation the rights 6 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 | copies of the Software, and to permit persons to whom the Software is 8 | furnished to do so, subject to the following conditions: 9 | 10 | The above copyright notice and this permission notice shall be included in all 11 | copies or substantial portions of the Software. 12 | 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 19 | SOFTWARE. 20 | 21 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # NixOS on Pinecube 2 | 3 | Download / install Nix using the instructions [here](https://nixos.org/download.html). 4 | Then, build an SD card image with `./build.sh`. 5 | Otherwise, a prebuilt image is available [here](https://drive.google.com/file/d/1P1W-cUGVXKch123DayvI1JpxyViJfkTF/view?usp=sharing) (last updated 2021-03-11). 6 | Decompress and flash with (replace `/dev/sdX`): 7 | ```shell 8 | $ cat ./result/sd-image/nixos-sd-image-21.03pre-git-armv7l-linux.img.zst | zstd -d | dd of=/dev/sdX bs=1024 9 | ``` 10 | 11 | It should be accessible over UART2 pins (see pinout on wiki) or SSH. 12 | - Username: `nixos` 13 | - Password: `nixos` 14 | 15 | This repository remains a work-in-progress, with certain features I need still not finished, including hardware accelerated encoding support. 16 | 17 | # Additional Notes 18 | 19 | ## Recording from CSI camera: 20 | - https://linux-sunxi.org/CSI#CSI_on_mainline_Linux_with_v4l2 21 | - https://www.kernel.org/doc/html/latest/userspace-api/media/v4l/subdev-formats.html 22 | 23 | Streaming via rtmp: 24 | 25 | Run a RTMP server on a machine on the network (assuming at 192.168.1.200). 26 | 27 | On pinecube 28 | ```shell 29 | $ media-ctl --set-v4l2 '"ov5640 1-003c":0[fmt:UYVY8_2X8/640x480@1/15]' 30 | $ ffmpeg -s 640x480 -r 15 -i /dev/video0 -vcodec flv -f flv rtmp://192.168.1.200/live/pinecube 31 | ``` 32 | 33 | On receiving machine: 34 | ```shell 35 | $ mpv "rtmp://192.168.1.200/live/pinecube" --profile=low-latency --cache-secs=1 36 | ``` 37 | 38 | To enable audio in the stream: (see section below for further audio details) 39 | ```shell 40 | $ media-ctl --set-v4l2 '"ov5640 1-003c":0[fmt:UYVY8_2X8/320x240@1/15]' 41 | $ ffmpeg -s 320x240 -r 15 -i /dev/video0 -f alsa -ac 1 -ar 22050 -i hw:0,0 -acodec libmp3lame -vcodec flv -f flv rtmp://192.168.1.200/live/pinecube 42 | ``` 43 | (Ensure that Mic1 is active and unmuted using `alsamixer`) 44 | CPU usage while encoding required me to also lower camera resolution and also the audio sampling rate. 45 | Let me know if you find ffmpeg settings that give a good balance between quality, CPU usage, and bitrate. 46 | 47 | ## Activating IR LEDs: 48 | ```shell 49 | $ echo 1 > /sys/class/leds/pine64\:ir\:led1/brightness 50 | $ echo 1 > /sys/class/leds/pine64\:ir\:led2/brightness 51 | ``` 52 | 53 | ## GPIO: 54 | https://linux-sunxi.org/GPIO 55 | ```shell 56 | $ cat /sys/kernel/debug/pinctrl/1c20800.pinctrl/pinmux-pins 57 | ``` 58 | gives information about pin numbering and what pins already claimed for other things 59 | 60 | ### Enabling/disabling IR-cut filter 61 | ```shell 62 | # Export gpio, set direction 63 | $ echo 45 > /sys/class/gpio/export 64 | $ echo out > /sys/class/gpio/gpio45/direction 65 | 66 | # 1 to enable, 0 to disable 67 | $ echo 1 > /sys/class/gpio/gpio45/value 68 | ``` 69 | 70 | ### Passive IR detection 71 | ```shell 72 | # Export gpio, set direction 73 | $ echo 199 > /sys/class/gpio/export 74 | $ echo in > /sys/class/gpio/gpio199/direction 75 | 76 | # Returns 1 for presence, 0 for none 77 | $ cat /sys/class/gpio/gpio199/value 78 | ``` 79 | 80 | ## SPI NOR 81 | The published schematic says it's a `GD5F4GQ4UCYIG`, however the label on the pinecube I have is for an `XT25F128B`. 82 | And this matches the JEDEC bytes reported in Linux. 83 | ```shell 84 | $ sudo modprobe spi-nor 85 | ``` 86 | The device is accessible at `/dev/mtd0`. 87 | 88 | ### SPI Boot 89 | Run `nix-build -A firmware-installer`. Then, 90 | ```shell 91 | $ dd if=result/firmware-installer-image.img of=/dev/sdX bs=1024 92 | ``` 93 | Then, use the menu option available over UART2 to install u-boot to the SPI. 94 | 95 | I initially flashed a bad u-boot, which caused me to be unable to boot from MMC or even FEL. 96 | I was able to force the Pinecube to load into FEL by grounding the `SPI0_MISO` pin. 97 | Then, I could boot into u-boot and erase the SPI, returning the Pinecube to factory condition. 98 | 99 | ## Ethernet 100 | Working fine in linux, and now also u-boot with patch derived from: https://lists.denx.de/pipermail/u-boot/2020-May/413924.html 101 | S3 datasheet says it supports up to 1000Mbit, but we only have a 100Mbit PHY: `H1601CG` 102 | Maybe this is for easier PoE support? 103 | 104 | ## USB 105 | Working in linux, currently not in u-boot. 106 | 107 | ## WIFI 108 | Other individuals have reported WiFi is working for them with exactly the same NixOS configuration. 109 | However, it currently doesn't work for me. 110 | This may be a hardware / power issue on my device. 111 | Sometimes, `iwlist wlan0 scan` works fine. 112 | However, it frequently stopps working after starting `wpa_supplicant`. 113 | Dmesg errors: 114 | ``` 115 | Oct 19 06:11:31 nixos wpa_supplicant[926]: Successfully initialized wpa_supplicant 116 | Oct 19 06:11:32 nixos kernel: sunxi-mmc 1c10000.mmc: data error, sending stop command 117 | Oct 19 06:11:32 nixos kernel: sunxi-mmc 1c10000.mmc: send stop command failed 118 | ``` 119 | 120 | ## Audio 121 | S3 has significant differences when compared with V3s. 122 | It has 4 audio inputs (3 mics, 1 line in), and 2 audio outputs (headphone and line out). 123 | PineCube MainBoard schematic says that the audio amplifier is connected in pin PB5 (PWM1) but in reality it is connected to PG6 (UART1_TX). 124 | Use `alsamixer` to ensure mic is active and unmuted. 125 | ```shell 126 | $ ffmpeg -f alsa -ar 22050 -i hw:0,0 -acodec mp3 -f flv rtmp://192.168.1.200/live/pinecube 127 | ``` 128 | 129 | To test your speaker, first turn up the "Line Out" and "DAC" controls in alsamixer. Next run: 130 | ```shell 131 | $ speaker-test -c2 -t wav 132 | `` 133 | You should be able to hear the audio being played via the speaker. 134 | 135 | ## Power Supply 136 | See `/sys/class/power_supply/axp20x-ac`. 137 | See `/sys/class/power_supply/axp20x-battery/{status,capacity}`. 138 | Green LED if power is on. 139 | Red LED if battery is charging. 140 | -------------------------------------------------------------------------------- /build.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | nix-build "" \ 4 | -I nixpkgs=https://github.com/danielfullmer/nixpkgs/archive/e69838e006a7271006ab834b521187891bf93ff4.tar.gz \ 5 | -I nixos-config=./sd-image.nix \ 6 | -A config.system.build.sdImage 7 | -------------------------------------------------------------------------------- /configuration.nix: -------------------------------------------------------------------------------- 1 | { config, lib, pkgs, ... }: 2 | 3 | { 4 | boot.loader.grub.enable = false; 5 | boot.loader.generic-extlinux-compatible.enable = true; 6 | boot.consoleLogLevel = 7; 7 | 8 | # cma is 64M by default which is waay too much and we can't even unpack initrd 9 | boot.kernelParams = [ "console=ttyS0,115200n8" "cma=32M" ]; 10 | 11 | # See: https://lore.kernel.org/patchwork/project/lkml/list/?submitter=22013&order=name 12 | boot.kernelPackages = pkgs.linuxPackages_5_9; 13 | boot.kernelPatches = [ 14 | { name = "pine64-pinecube"; 15 | patch = ./kernel/Pine64-PineCube-support.patch; 16 | # sunxi_defconfig is missing wireless support 17 | # TODO: Are all of these options needed here? 18 | extraConfig = '' 19 | CFG80211 m 20 | WIRELESS y 21 | WLAN y 22 | RFKILL y 23 | RFKILL_INPUT y 24 | RFKILL_GPIO y 25 | ''; 26 | } 27 | ]; 28 | 29 | boot.kernelModules = [ "spi-nor" ]; # Not sure why this doesn't autoload. Provides SPI NOR at /dev/mtd0 30 | boot.extraModulePackages = [ config.boot.kernelPackages.rtl8189es ]; 31 | 32 | zramSwap.enable = true; # 128MB is not much to work with 33 | 34 | sound.enable = true; 35 | 36 | environment.systemPackages = with pkgs; [ 37 | ffmpeg 38 | (v4l_utils.override { withGUI = false; }) 39 | usbutils 40 | ]; 41 | 42 | ### 43 | 44 | services.openssh.enable = true; 45 | services.openssh.permitRootLogin = "yes"; 46 | users.users.root.initialPassword = "nixos"; # Log in without a password 47 | 48 | users.users.nixos = { 49 | isNormalUser = true; 50 | extraGroups = [ "wheel" "networkmanager" "video" ]; 51 | initialPassword = "nixos"; 52 | }; 53 | services.mingetty.autologinUser = "nixos"; 54 | 55 | networking.wireless.enable = true; 56 | 57 | } 58 | -------------------------------------------------------------------------------- /cross-config.nix: -------------------------------------------------------------------------------- 1 | { config, lib, pkgs, ... }: 2 | 3 | { 4 | nixpkgs.crossSystem = lib.recursiveUpdate lib.systems.examples.armv7l-hf-multiplatform { 5 | platform = { 6 | name = "pinecube"; 7 | kernelBaseConfig = "sunxi_defconfig"; 8 | }; 9 | }; 10 | 11 | nixpkgs.overlays = [ (self: super: { 12 | # Dependency minimization for cross-compiling 13 | cairo = super.cairo.override { glSupport = false; }; 14 | libass = super.libass.override { encaSupport = false; }; 15 | gnutls = super.gnutls.override { guileBindings = false; }; 16 | polkit = super.polkit.override { withIntrospection = false; }; 17 | }) ]; 18 | 19 | # disable more stuff to minimize cross-compilation 20 | # some from: https://github.com/illegalprime/nixos-on-arm/blob/master/images/mini/default.nix 21 | environment.noXlibs = true; 22 | documentation.info.enable = false; 23 | documentation.man.enable = false; 24 | programs.command-not-found.enable = false; 25 | security.polkit.enable = false; 26 | security.audit.enable = false; 27 | services.udisks2.enable = false; 28 | boot.enableContainers = false; 29 | } 30 | -------------------------------------------------------------------------------- /kernel/Pine64-PineCube-support.patch: -------------------------------------------------------------------------------- 1 | From 17bd28ff69e61f881d54cf4c606c04b55a43d478 Mon Sep 17 00:00:00 2001 2 | From: Icenowy Zheng 3 | Date: Wed, 23 Sep 2020 08:57:03 +0800 4 | Subject: [PATCH 01/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support 5 | 6 | The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite 7 | similar to the ones on Allwinner H3, except for V3s the external MII is 8 | not wired out. 9 | 10 | Add ethernet support to V3/V3s/S3/S3L. 11 | 12 | Signed-off-by: Icenowy Zheng 13 | --- 14 | arch/arm/boot/dts/sun8i-v3.dtsi | 13 ++++++++ 15 | arch/arm/boot/dts/sun8i-v3s.dtsi | 52 ++++++++++++++++++++++++++++++++ 16 | 2 files changed, 65 insertions(+) 17 | 18 | diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi 19 | index 6ae8645ade50..ca4672ed2e02 100644 20 | --- a/arch/arm/boot/dts/sun8i-v3.dtsi 21 | +++ b/arch/arm/boot/dts/sun8i-v3.dtsi 22 | @@ -9,6 +9,19 @@ &ccu { 23 | compatible = "allwinner,sun8i-v3-ccu"; 24 | }; 25 | 26 | +&emac { 27 | + /delete-property/ phy-handle; 28 | + /delete-property/ phy-mode; 29 | +}; 30 | + 31 | +&mdio_mux { 32 | + external_mdio: mdio@2 { 33 | + reg = <2>; 34 | + #address-cells = <1>; 35 | + #size-cells = <0>; 36 | + }; 37 | +}; 38 | + 39 | &pio { 40 | compatible = "allwinner,sun8i-v3-pinctrl"; 41 | }; 42 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 43 | index e5312869c0d2..b4069df84d10 100644 44 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 45 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 46 | @@ -138,6 +138,15 @@ mixer0_out_tcon0: endpoint { 47 | }; 48 | }; 49 | 50 | + syscon: system-control@1c00000 { 51 | + compatible = "allwinner,sun8i-v3s-system-control", 52 | + "allwinner,sun8i-h3-system-control"; 53 | + reg = <0x01c00000 0x1000>; 54 | + #address-cells = <1>; 55 | + #size-cells = <1>; 56 | + ranges; 57 | + }; 58 | + 59 | tcon0: lcd-controller@1c0c000 { 60 | compatible = "allwinner,sun8i-v3s-tcon"; 61 | reg = <0x01c0c000 0x1000>; 62 | @@ -404,6 +413,49 @@ i2c1: i2c@1c2b000 { 63 | #size-cells = <0>; 64 | }; 65 | 66 | + emac: ethernet@1c30000 { 67 | + compatible = "allwinner,sun8i-v3s-emac"; 68 | + syscon = <&syscon>; 69 | + reg = <0x01c30000 0x10000>; 70 | + interrupts = ; 71 | + interrupt-names = "macirq"; 72 | + resets = <&ccu RST_BUS_EMAC>; 73 | + reset-names = "stmmaceth"; 74 | + clocks = <&ccu CLK_BUS_EMAC>; 75 | + clock-names = "stmmaceth"; 76 | + phy-handle = <&int_mii_phy>; 77 | + phy-mode = "mii"; 78 | + status = "disabled"; 79 | + 80 | + mdio: mdio { 81 | + #address-cells = <1>; 82 | + #size-cells = <0>; 83 | + compatible = "snps,dwmac-mdio"; 84 | + }; 85 | + 86 | + mdio_mux: mdio-mux { 87 | + compatible = "allwinner,sun8i-h3-mdio-mux"; 88 | + #address-cells = <1>; 89 | + #size-cells = <0>; 90 | + 91 | + mdio-parent-bus = <&mdio>; 92 | + /* Only one MDIO is usable at the time */ 93 | + internal_mdio: mdio@1 { 94 | + compatible = "allwinner,sun8i-h3-mdio-internal"; 95 | + reg = <1>; 96 | + #address-cells = <1>; 97 | + #size-cells = <0>; 98 | + 99 | + int_mii_phy: ethernet-phy@1 { 100 | + compatible = "ethernet-phy-ieee802.3-c22"; 101 | + reg = <1>; 102 | + clocks = <&ccu CLK_BUS_EPHY>; 103 | + resets = <&ccu RST_BUS_EPHY>; 104 | + }; 105 | + }; 106 | + }; 107 | + }; 108 | + 109 | spi0: spi@1c68000 { 110 | compatible = "allwinner,sun8i-h3-spi"; 111 | reg = <0x01c68000 0x1000>; 112 | -- 113 | 2.29.0 114 | 115 | 116 | From c3e603b4fb67bcc5da7361c46c11f6101835d54c Mon Sep 17 00:00:00 2001 117 | From: Icenowy Zheng 118 | Date: Wed, 23 Sep 2020 08:58:53 +0800 119 | Subject: [PATCH 02/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2 120 | RX/TX 121 | 122 | The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used 123 | as debugging UART on some boards. 124 | 125 | Add pinctrl node for them. 126 | 127 | Signed-off-by: Icenowy Zheng 128 | --- 129 | arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++++++ 130 | 1 file changed, 7 insertions(+) 131 | 132 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 133 | index b4069df84d10..3932d227ac1c 100644 134 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 135 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 136 | @@ -311,6 +311,11 @@ uart0_pb_pins: uart0-pb-pins { 137 | function = "uart0"; 138 | }; 139 | 140 | + uart2_pins: uart2-pins { 141 | + pins = "PB0", "PB1"; 142 | + function = "uart2"; 143 | + }; 144 | + 145 | mmc0_pins: mmc0-pins { 146 | pins = "PF0", "PF1", "PF2", "PF3", 147 | "PF4", "PF5"; 148 | @@ -386,6 +391,8 @@ uart2: serial@1c28800 { 149 | reg-io-width = <4>; 150 | clocks = <&ccu CLK_BUS_UART2>; 151 | resets = <&ccu RST_BUS_UART2>; 152 | + pinctrl-0 = <&uart2_pins>; 153 | + pinctrl-names = "default"; 154 | status = "disabled"; 155 | }; 156 | 157 | -- 158 | 2.29.0 159 | 160 | 161 | From ada1e0b448d8fd71eac999adbc3a179c0395002a Mon Sep 17 00:00:00 2001 162 | From: Icenowy Zheng 163 | Date: Wed, 23 Sep 2020 08:58:54 +0800 164 | Subject: [PATCH 03/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node 165 | 166 | The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI. 167 | 168 | Add the device tree node of it. 169 | 170 | Signed-off-by: Icenowy Zheng 171 | --- 172 | arch/arm/boot/dts/sun8i-v3s.dtsi | 12 ++++++++++++ 173 | 1 file changed, 12 insertions(+) 174 | 175 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 176 | index 3932d227ac1c..f221018d7cf3 100644 177 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 178 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 179 | @@ -477,6 +477,18 @@ spi0: spi@1c68000 { 180 | #size-cells = <0>; 181 | }; 182 | 183 | + csi1: camera@1cb4000 { 184 | + compatible = "allwinner,sun8i-v3s-csi"; 185 | + reg = <0x01cb4000 0x3000>; 186 | + interrupts = ; 187 | + clocks = <&ccu CLK_BUS_CSI>, 188 | + <&ccu CLK_CSI1_SCLK>, 189 | + <&ccu CLK_DRAM_CSI>; 190 | + clock-names = "bus", "mod", "ram"; 191 | + resets = <&ccu RST_BUS_CSI>; 192 | + status = "disabled"; 193 | + }; 194 | + 195 | gic: interrupt-controller@1c81000 { 196 | compatible = "arm,gic-400"; 197 | reg = <0x01c81000 0x1000>, 198 | -- 199 | 2.29.0 200 | 201 | 202 | From 48cf51ab9126ea032f464157b2cf2a40f9a49be4 Mon Sep 17 00:00:00 2001 203 | From: Icenowy Zheng 204 | Date: Wed, 23 Sep 2020 09:00:11 +0800 205 | Subject: [PATCH 04/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit 206 | parallel CSI 207 | 208 | The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI. 209 | 210 | As we're going to add support for Pine64 SCC board, which uses 8-bit 211 | parallel CSI (and the MCLK output), add the pinctrl node of 8-bit 212 | CSI and MCLK to the DTSI file. 213 | 214 | Signed-off-by: Icenowy Zheng 215 | --- 216 | arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ 217 | 1 file changed, 14 insertions(+) 218 | 219 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 220 | index f221018d7cf3..2727756bcd91 100644 221 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 222 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 223 | @@ -301,6 +301,20 @@ pio: pinctrl@1c20800 { 224 | interrupt-controller; 225 | #interrupt-cells = <3>; 226 | 227 | + /omit-if-no-ref/ 228 | + csi1_8bit_pins: csi1-8bit-pins { 229 | + pins = "PE0", "PE2", "PE3", "PE8", "PE9", 230 | + "PE10", "PE11", "PE12", "PE13", "PE14", 231 | + "PE15"; 232 | + function = "csi"; 233 | + }; 234 | + 235 | + /omit-if-no-ref/ 236 | + csi1_mclk_pin: csi1-mclk-pin { 237 | + pins = "PE1"; 238 | + function = "csi"; 239 | + }; 240 | + 241 | i2c0_pins: i2c0-pins { 242 | pins = "PB6", "PB7"; 243 | function = "i2c0"; 244 | -- 245 | 2.29.0 246 | 247 | 248 | From e7b7e35f417676ac1e692730c16ab50f9d6e4da4 Mon Sep 17 00:00:00 2001 249 | From: Icenowy Zheng 250 | Date: Wed, 23 Sep 2020 09:00:12 +0800 251 | Subject: [PATCH 05/18] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for I2C1 at 252 | PE bank 253 | 254 | I2C1 controller is available at PE bank, usually used for 255 | connecting an I2C-controlled camera sensor. 256 | 257 | Add pinctrl node for it. 258 | 259 | Signed-off-by: Icenowy Zheng 260 | --- 261 | arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++++++ 262 | 1 file changed, 6 insertions(+) 263 | 264 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 265 | index 2727756bcd91..3cd3b58c2587 100644 266 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 267 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 268 | @@ -320,6 +320,12 @@ i2c0_pins: i2c0-pins { 269 | function = "i2c0"; 270 | }; 271 | 272 | + /omit-if-no-ref/ 273 | + i2c1_pe_pins: i2c1-pe-pins { 274 | + pins = "PE21", "PE22"; 275 | + function = "i2c1"; 276 | + }; 277 | + 278 | uart0_pb_pins: uart0-pb-pins { 279 | pins = "PB8", "PB9"; 280 | function = "uart0"; 281 | -- 282 | 2.29.0 283 | 284 | 285 | From 0ae37e2d02098a198f3d149b2e36b8e862a121ee Mon Sep 17 00:00:00 2001 286 | From: Icenowy Zheng 287 | Date: Wed, 23 Sep 2020 09:02:14 +0800 288 | Subject: [PATCH 06/18] dt-bindings: arm: sunxi: add Pine64 PineCube binding 289 | 290 | Document board compatible names for Pine64 PineCube IP camera. 291 | 292 | Signed-off-by: Icenowy Zheng 293 | --- 294 | Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 295 | 1 file changed, 5 insertions(+) 296 | 297 | diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml 298 | index efc9118233b4..ba4a380ba4a3 100644 299 | --- a/Documentation/devicetree/bindings/arm/sunxi.yaml 300 | +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml 301 | @@ -626,6 +626,11 @@ properties: 302 | - const: pine64,pine64-plus 303 | - const: allwinner,sun50i-a64 304 | 305 | + - description: Pine64 PineCube 306 | + items: 307 | + - const: pine64,pinecube 308 | + - const: allwinner,sun8i-v3 309 | + 310 | - description: Pine64 PineH64 model A 311 | items: 312 | - const: pine64,pine-h64 313 | -- 314 | 2.29.0 315 | 316 | 317 | From 6dca04137361a821df34ef83b6f34fd1aa9fbb73 Mon Sep 17 00:00:00 2001 318 | From: Icenowy Zheng 319 | Date: Wed, 23 Sep 2020 09:02:15 +0800 320 | Subject: [PATCH 07/18] ARM: dts: sun8i: s3l: add support for Pine64 PineCube 321 | IP camera 322 | 323 | The Pine64 PineCube IP camera is an IP camera with SoChip S3 SoC. 324 | 325 | It comes with a main board, an expansion board and a camera. 326 | 327 | The main board features a Micro-USB power-only jack, a USB Type-A port, 328 | an Ethernet port connected to the internal PHY of the SoC and a Realtek 329 | RTL8189ES SDIO Wi-Fi module. A RGB LCD connector is reserved on the 330 | board. 331 | 332 | The expansion board features a TF slot, a microphone, a speaker 333 | connector with on-board amplifier and a few IR LEDs. 334 | 335 | Add support for the kit, with features on the main board and the 336 | expansion board now. 337 | 338 | Signed-off-by: Icenowy Zheng 339 | --- 340 | arch/arm/boot/dts/Makefile | 1 + 341 | arch/arm/boot/dts/sun8i-s3-pinecube.dts | 235 ++++++++++++++++++++++++ 342 | 2 files changed, 236 insertions(+) 343 | create mode 100644 arch/arm/boot/dts/sun8i-s3-pinecube.dts 344 | 345 | diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile 346 | index 4572db3fa5ae..4363ba564bb4 100644 347 | --- a/arch/arm/boot/dts/Makefile 348 | +++ b/arch/arm/boot/dts/Makefile 349 | @@ -1194,6 +1194,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ 350 | sun8i-r16-parrot.dtb \ 351 | sun8i-r40-bananapi-m2-ultra.dtb \ 352 | sun8i-s3-lichee-zero-plus.dtb \ 353 | + sun8i-s3-pinecube.dtb \ 354 | sun8i-t3-cqa3t-bv3.dtb \ 355 | sun8i-v3s-licheepi-zero.dtb \ 356 | sun8i-v3s-licheepi-zero-dock.dtb \ 357 | diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 358 | new file mode 100644 359 | index 000000000000..9bab6b7f4014 360 | --- /dev/null 361 | +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 362 | @@ -0,0 +1,235 @@ 363 | +// SPDX-License-Identifier: (GPL-2.0+ OR X11) 364 | +/* 365 | + * Copyright 2019 Icenowy Zheng 366 | + */ 367 | + 368 | +/dts-v1/; 369 | +#include "sun8i-v3.dtsi" 370 | +#include 371 | +#include 372 | + 373 | +/ { 374 | + model = "PineCube IP Camera"; 375 | + compatible = "pine64,pinecube", "allwinner,sun8i-s3"; 376 | + 377 | + aliases { 378 | + serial0 = &uart2; 379 | + }; 380 | + 381 | + chosen { 382 | + stdout-path = "serial0:115200n8"; 383 | + }; 384 | + 385 | + leds { 386 | + compatible = "gpio-leds"; 387 | + 388 | + led1 { 389 | + label = "pine64:ir:led1"; 390 | + gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ 391 | + }; 392 | + 393 | + led2 { 394 | + label = "pine64:ir:led2"; 395 | + gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ 396 | + }; 397 | + }; 398 | + 399 | + reg_vcc5v0: vcc5v0 { 400 | + compatible = "regulator-fixed"; 401 | + regulator-name = "vcc5v0"; 402 | + regulator-min-microvolt = <5000000>; 403 | + regulator-max-microvolt = <5000000>; 404 | + }; 405 | + 406 | + reg_vcc_wifi: vcc-wifi { 407 | + compatible = "regulator-fixed"; 408 | + regulator-name = "vcc-wifi"; 409 | + regulator-min-microvolt = <3300000>; 410 | + regulator-max-microvolt = <3300000>; 411 | + gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ 412 | + vin-supply = <®_dcdc3>; 413 | + startup-delay-us = <200000>; 414 | + }; 415 | + 416 | + wifi_pwrseq: wifi_pwrseq { 417 | + compatible = "mmc-pwrseq-simple"; 418 | + reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ 419 | + post-power-on-delay-ms = <200>; 420 | + }; 421 | +}; 422 | + 423 | +&csi1 { 424 | + pinctrl-names = "default"; 425 | + pinctrl-0 = <&csi1_8bit_pins>; 426 | + status = "okay"; 427 | + 428 | + port { 429 | + #address-cells = <1>; 430 | + #size-cells = <0>; 431 | + 432 | + csi1_ep: endpoint { 433 | + remote-endpoint = <&ov5640_ep>; 434 | + bus-width = <8>; 435 | + hsync-active = <1>; /* Active high */ 436 | + vsync-active = <0>; /* Active low */ 437 | + data-active = <1>; /* Active high */ 438 | + pclk-sample = <1>; /* Rising */ 439 | + }; 440 | + }; 441 | +}; 442 | + 443 | +&emac { 444 | + phy-handle = <&int_mii_phy>; 445 | + phy-mode = "mii"; 446 | + status = "okay"; 447 | +}; 448 | + 449 | +&i2c0 { 450 | + status = "okay"; 451 | + 452 | + axp209: pmic@34 { 453 | + compatible = "x-powers,axp203", 454 | + "x-powers,axp209"; 455 | + reg = <0x34>; 456 | + interrupt-parent = <&gic>; 457 | + interrupts = ; 458 | + interrupt-controller; 459 | + #interrupt-cells = <1>; 460 | + }; 461 | +}; 462 | + 463 | +&i2c1 { 464 | + pinctrl-names = "default"; 465 | + pinctrl-0 = <&i2c1_pe_pins>; 466 | + status = "okay"; 467 | + 468 | + ov5640: camera@3c { 469 | + compatible = "ovti,ov5640"; 470 | + reg = <0x3c>; 471 | + pinctrl-names = "default"; 472 | + pinctrl-0 = <&csi1_mclk_pin>; 473 | + clocks = <&ccu CLK_CSI1_MCLK>; 474 | + clock-names = "xclk"; 475 | + 476 | + AVDD-supply = <®_ldo3>; 477 | + DOVDD-supply = <®_ldo3>; 478 | + DVDD-supply = <®_ldo4>; 479 | + reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ 480 | + powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ 481 | + 482 | + port { 483 | + ov5640_ep: endpoint { 484 | + remote-endpoint = <&csi1_ep>; 485 | + bus-width = <8>; 486 | + hsync-active = <1>; /* Active high */ 487 | + vsync-active = <0>; /* Active low */ 488 | + data-active = <1>; /* Active high */ 489 | + pclk-sample = <1>; /* Rising */ 490 | + }; 491 | + }; 492 | + }; 493 | +}; 494 | + 495 | +&lradc { 496 | + vref-supply = <®_ldo2>; 497 | + status = "okay"; 498 | + 499 | + button-200 { 500 | + label = "Setup"; 501 | + linux,code = ; 502 | + channel = <0>; 503 | + voltage = <190000>; 504 | + }; 505 | +}; 506 | + 507 | +&mmc0 { 508 | + vmmc-supply = <®_dcdc3>; 509 | + bus-width = <4>; 510 | + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 511 | + status = "okay"; 512 | +}; 513 | + 514 | +&mmc1 { 515 | + vmmc-supply = <®_vcc_wifi>; 516 | + vqmmc-supply = <®_dcdc3>; 517 | + mmc-pwrseq = <&wifi_pwrseq>; 518 | + bus-width = <4>; 519 | + non-removable; 520 | + status = "okay"; 521 | +}; 522 | + 523 | +&pio { 524 | + vcc-pd-supply = <®_dcdc3>; 525 | + vcc-pe-supply = <®_ldo3>; 526 | +}; 527 | + 528 | +#include "axp209.dtsi" 529 | + 530 | +&ac_power_supply { 531 | + status = "okay"; 532 | +}; 533 | + 534 | +®_dcdc2 { 535 | + regulator-always-on; 536 | + regulator-min-microvolt = <1250000>; 537 | + regulator-max-microvolt = <1250000>; 538 | + regulator-name = "vdd-sys-cpu-ephy"; 539 | +}; 540 | + 541 | +®_dcdc3 { 542 | + regulator-always-on; 543 | + regulator-min-microvolt = <3300000>; 544 | + regulator-max-microvolt = <3300000>; 545 | + regulator-name = "vcc-3v3"; 546 | +}; 547 | + 548 | +®_ldo1 { 549 | + regulator-name = "vdd-rtc"; 550 | +}; 551 | + 552 | +®_ldo2 { 553 | + regulator-always-on; 554 | + regulator-min-microvolt = <3000000>; 555 | + regulator-max-microvolt = <3000000>; 556 | + regulator-name = "avcc"; 557 | +}; 558 | + 559 | +®_ldo3 { 560 | + regulator-min-microvolt = <2800000>; 561 | + regulator-max-microvolt = <2800000>; 562 | + regulator-name = "avdd-dovdd-2v8-csi"; 563 | + regulator-soft-start; 564 | + regulator-ramp-delay = <1600>; 565 | +}; 566 | + 567 | +®_ldo4 { 568 | + regulator-min-microvolt = <1800000>; 569 | + regulator-max-microvolt = <1800000>; 570 | + regulator-name = "dvdd-1v8-csi"; 571 | +}; 572 | + 573 | +&spi0 { 574 | + status = "okay"; 575 | + 576 | + flash@0 { 577 | + #address-cells = <1>; 578 | + #size-cells = <1>; 579 | + compatible = "winbond,w25q128", "jedec,spi-nor"; 580 | + reg = <0>; 581 | + spi-max-frequency = <40000000>; 582 | + }; 583 | +}; 584 | + 585 | +&uart2 { 586 | + status = "okay"; 587 | +}; 588 | + 589 | +&usb_otg { 590 | + dr_mode = "host"; 591 | + status = "okay"; 592 | +}; 593 | + 594 | +&usbphy { 595 | + usb0_vbus-supply = <®_vcc5v0>; 596 | + status = "okay"; 597 | +}; 598 | -- 599 | 2.29.0 600 | 601 | 602 | From 7ad2976267f04f3b29327e470c9698bd689775d8 Mon Sep 17 00:00:00 2001 603 | From: Daniel Fullmer 604 | Date: Fri, 23 Oct 2020 16:04:15 -0700 605 | Subject: [PATCH 08/18] ARM: dts: sun8i: s3l: fix Pinecube IR LEDs 606 | 607 | Signed-off-by: Daniel Fullmer 608 | --- 609 | arch/arm/boot/dts/sun8i-s3-pinecube.dts | 4 ++-- 610 | 1 file changed, 2 insertions(+), 2 deletions(-) 611 | 612 | diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 613 | index 9bab6b7f4014..a4adf52ef406 100644 614 | --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts 615 | +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 616 | @@ -25,12 +25,12 @@ leds { 617 | 618 | led1 { 619 | label = "pine64:ir:led1"; 620 | - gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ 621 | + gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */ 622 | }; 623 | 624 | led2 { 625 | label = "pine64:ir:led2"; 626 | - gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ 627 | + gpios = <&pio 1 12 GPIO_ACTIVE_HIGH>; /* PB12 */ 628 | }; 629 | }; 630 | 631 | -- 632 | 2.29.0 633 | 634 | 635 | From 08043145ab7046e85339a9bd3221cc8ee53e64e5 Mon Sep 17 00:00:00 2001 636 | From: Daniel Fullmer 637 | Date: Fri, 23 Oct 2020 16:05:10 -0700 638 | Subject: [PATCH 09/18] ARM: dts: sun8i: s3l: add battery power supply to 639 | pinecube 640 | 641 | Signed-off-by: Daniel Fullmer 642 | --- 643 | arch/arm/boot/dts/sun8i-s3-pinecube.dts | 4 ++++ 644 | 1 file changed, 4 insertions(+) 645 | 646 | diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 647 | index a4adf52ef406..0319327dea3c 100644 648 | --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts 649 | +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 650 | @@ -169,6 +169,10 @@ &ac_power_supply { 651 | status = "okay"; 652 | }; 653 | 654 | +&battery_power_supply { 655 | + status = "okay"; 656 | +}; 657 | + 658 | ®_dcdc2 { 659 | regulator-always-on; 660 | regulator-min-microvolt = <1250000>; 661 | -- 662 | 2.29.0 663 | 664 | 665 | From 009e2c4615d99fcfe4fdaa8c1761afe649302a84 Mon Sep 17 00:00:00 2001 666 | From: Icenowy Zheng 667 | Date: Wed, 24 May 2017 18:06:05 +0800 668 | Subject: [PATCH 10/18] ARM: dts: sun8i: add DMA engine in V3s DTSI 669 | 670 | Allwinner V3s SoC features a DMA engine. 671 | 672 | Add it in the DTSI file. 673 | 674 | Signed-off-by: Icenowy Zheng 675 | Acked-by: Chen-Yu Tsai 676 | --- 677 | arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +++++++++ 678 | 1 file changed, 9 insertions(+) 679 | 680 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 681 | index 3cd3b58c2587..4203a0964864 100644 682 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 683 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 684 | @@ -147,6 +147,15 @@ syscon: system-control@1c00000 { 685 | ranges; 686 | }; 687 | 688 | + dma: dma-controller@01c02000 { 689 | + compatible = "allwinner,sun8i-v3s-dma"; 690 | + reg = <0x01c02000 0x1000>; 691 | + interrupts = ; 692 | + clocks = <&ccu CLK_BUS_DMA>; 693 | + resets = <&ccu RST_BUS_DMA>; 694 | + #dma-cells = <1>; 695 | + }; 696 | + 697 | tcon0: lcd-controller@1c0c000 { 698 | compatible = "allwinner,sun8i-v3s-tcon"; 699 | reg = <0x01c0c000 0x1000>; 700 | -- 701 | 2.29.0 702 | 703 | 704 | From 92cd60e77ba64615a6182f74e9bb23e2cb863100 Mon Sep 17 00:00:00 2001 705 | From: Icenowy Zheng 706 | Date: Wed, 24 May 2017 18:06:06 +0800 707 | Subject: [PATCH 11/18] ARM: dts: sun8i: add audio codec support into V3s DTSI 708 | 709 | Allwinner V3s SoC features an internal audio codec like the one in H3, 710 | and a analog codec like the one in H3/A23 (but much simpler). 711 | 712 | Add them in the DTSI file. 713 | 714 | Signed-off-by: Icenowy Zheng 715 | Acked-by: Chen-Yu Tsai 716 | --- 717 | arch/arm/boot/dts/sun8i-v3s.dtsi | 32 ++++++++++++++++++++++++++++++++ 718 | 1 file changed, 32 insertions(+) 719 | 720 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 721 | index 4203a0964864..0a933c9dc779 100644 722 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 723 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 724 | @@ -383,6 +383,33 @@ wdt0: watchdog@1c20ca0 { 725 | clocks = <&osc24M>; 726 | }; 727 | 728 | + i2s0: i2s@1c22000 { 729 | + #sound-dai-cells = <0>; 730 | + compatible = "allwinner,sun8i-h3-i2s"; 731 | + reg = <0x01c22000 0x400>; 732 | + interrupts = ; 733 | + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 734 | + clock-names = "apb", "mod"; 735 | + dmas = <&dma 3>, <&dma 3>; 736 | + resets = <&ccu RST_BUS_I2S0>; /* TODO: Areset/sun8i-v3s-ccu says this isn't available on V3s */ 737 | + dma-names = "rx", "tx"; 738 | + status = "disabled"; 739 | + }; 740 | + 741 | + codec: codec@01c22c00 { 742 | + #sound-dai-cells = <0>; 743 | + compatible = "allwinner,sun8i-v3s-codec"; 744 | + reg = <0x01c22c00 0x400>; 745 | + interrupts = ; 746 | + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 747 | + clock-names = "apb", "codec"; 748 | + resets = <&ccu RST_BUS_CODEC>; 749 | + dmas = <&dma 15>, <&dma 15>; 750 | + dma-names = "rx", "tx"; 751 | + allwinner,codec-analog-controls = <&codec_analog>; 752 | + status = "disabled"; 753 | + }; 754 | + 755 | lradc: lradc@1c22800 { 756 | compatible = "allwinner,sun4i-a10-lradc-keys"; 757 | reg = <0x01c22800 0x400>; 758 | @@ -390,6 +417,11 @@ lradc: lradc@1c22800 { 759 | status = "disabled"; 760 | }; 761 | 762 | + codec_analog: codec-analog@01c23000 { 763 | + compatible = "allwinner,sun8i-v3s-codec-analog"; 764 | + reg = <0x01c23000 0x4>; 765 | + }; 766 | + 767 | uart0: serial@1c28000 { 768 | compatible = "snps,dw-apb-uart"; 769 | reg = <0x01c28000 0x400>; 770 | -- 771 | 2.29.0 772 | 773 | 774 | From c742763da8b136f1a62043531d5cf6c570732b0f Mon Sep 17 00:00:00 2001 775 | From: Daniel Fullmer 776 | Date: Sat, 24 Oct 2020 15:13:51 -0700 777 | Subject: [PATCH 12/18] ARM: dts: sun8i: s3l: enable audio on Pinecube 778 | 779 | TODO: Do this properly. Maybe add sun8i-s3-codec-analog 780 | --- 781 | arch/arm/boot/dts/sun8i-s3-pinecube.dts | 13 +++++++++++++ 782 | sound/soc/sunxi/sun8i-codec-analog.c | 4 ++++ 783 | 2 files changed, 17 insertions(+) 784 | 785 | diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 786 | index 0319327dea3c..35e501ec8073 100644 787 | --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts 788 | +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 789 | @@ -237,3 +237,16 @@ &usbphy { 790 | usb0_vbus-supply = <®_vcc5v0>; 791 | status = "okay"; 792 | }; 793 | + 794 | +&i2s0 { 795 | + status = "okay"; 796 | +}; 797 | + 798 | +&codec { 799 | + allwinner,pa-gpio = <&pio 6 6 GPIO_ACTIVE_HIGH>; /*PG6*/ 800 | + allwinner,audio-routing = 801 | + "Speaker", "LINEOUT", 802 | + "MIC1", "Mic", 803 | + "Mic", "MBIAS"; 804 | + status = "okay"; 805 | +}; 806 | diff --git a/sound/soc/sunxi/sun8i-codec-analog.c b/sound/soc/sunxi/sun8i-codec-analog.c 807 | index be872eefa61e..b806121abeeb 100644 808 | --- a/sound/soc/sunxi/sun8i-codec-analog.c 809 | +++ b/sound/soc/sunxi/sun8i-codec-analog.c 810 | @@ -731,6 +731,10 @@ static int sun8i_codec_analog_add_mixer(struct snd_soc_component *cmpnt, 811 | static const struct sun8i_codec_analog_quirks sun8i_v3s_quirks = { 812 | .has_headphone = true, 813 | .has_hmic = true, 814 | + .has_linein = true, 815 | + .has_lineout = true, 816 | + .has_mbias = true, 817 | + .has_mic2 = true, 818 | }; 819 | 820 | static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt) 821 | -- 822 | 2.29.0 823 | 824 | 825 | From 154d022acdfa415fbb1969ace6f74a21028fc9af Mon Sep 17 00:00:00 2001 826 | From: microcai 827 | Date: Mon, 29 Jun 2020 23:36:40 +0800 828 | Subject: [PATCH 13/18] spi-nor: Add support for xt25f32b/xt25f128b 829 | 830 | The RockPi4b dev board ship with xt25f32b solded. add these ids so the 831 | board's spi flash can be accessed within linux. 832 | 833 | Signed-off-by: microcai 834 | --- 835 | drivers/mtd/spi-nor/Makefile | 1 + 836 | drivers/mtd/spi-nor/core.c | 1 + 837 | drivers/mtd/spi-nor/core.h | 1 + 838 | drivers/mtd/spi-nor/xtx.c | 21 +++++++++++++++++++++ 839 | 4 files changed, 24 insertions(+) 840 | create mode 100644 drivers/mtd/spi-nor/xtx.c 841 | 842 | diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile 843 | index 653923896205..3f7a52d7fa0b 100644 844 | --- a/drivers/mtd/spi-nor/Makefile 845 | +++ b/drivers/mtd/spi-nor/Makefile 846 | @@ -17,6 +17,7 @@ spi-nor-objs += sst.o 847 | spi-nor-objs += winbond.o 848 | spi-nor-objs += xilinx.o 849 | spi-nor-objs += xmc.o 850 | +spi-nor-objs += xtx.o 851 | obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o 852 | 853 | obj-$(CONFIG_MTD_SPI_NOR) += controllers/ 854 | diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c 855 | index 0369d98b2d12..88e91af97ef3 100644 856 | --- a/drivers/mtd/spi-nor/core.c 857 | +++ b/drivers/mtd/spi-nor/core.c 858 | @@ -2024,6 +2024,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { 859 | &spi_nor_winbond, 860 | &spi_nor_xilinx, 861 | &spi_nor_xmc, 862 | + &spi_nor_xtx, 863 | }; 864 | 865 | static const struct flash_info * 866 | diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h 867 | index 6f2f6b27173f..cea8c0c25c9f 100644 868 | --- a/drivers/mtd/spi-nor/core.h 869 | +++ b/drivers/mtd/spi-nor/core.h 870 | @@ -398,6 +398,7 @@ extern const struct spi_nor_manufacturer spi_nor_sst; 871 | extern const struct spi_nor_manufacturer spi_nor_winbond; 872 | extern const struct spi_nor_manufacturer spi_nor_xilinx; 873 | extern const struct spi_nor_manufacturer spi_nor_xmc; 874 | +extern const struct spi_nor_manufacturer spi_nor_xtx; 875 | 876 | int spi_nor_write_enable(struct spi_nor *nor); 877 | int spi_nor_write_disable(struct spi_nor *nor); 878 | diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c 879 | new file mode 100644 880 | index 000000000000..541fd8e52b79 881 | --- /dev/null 882 | +++ b/drivers/mtd/spi-nor/xtx.c 883 | @@ -0,0 +1,21 @@ 884 | +// SPDX-License-Identifier: GPL-2.0 885 | +/* 886 | + * Copyright (C) 2005, Intec Automation Inc. 887 | + * Copyright (C) 2014, Freescale Semiconductor, Inc. 888 | + */ 889 | + 890 | +#include 891 | + 892 | +#include "core.h" 893 | + 894 | +static const struct flash_info xtx_parts[] = { 895 | + /* XTX (Shenzhen Xin Tian Xia Tech) */ 896 | + { "xt25f32b", INFO(0x0b4016, 0, 64 * 1024, 64, SECT_4K) }, 897 | + { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256, SECT_4K) }, 898 | +}; 899 | + 900 | +const struct spi_nor_manufacturer spi_nor_xtx = { 901 | + .name = "xtx", 902 | + .parts = xtx_parts, 903 | + .nparts = ARRAY_SIZE(xtx_parts), 904 | +}; 905 | -- 906 | 2.29.0 907 | 908 | 909 | From 2c19e5196d862d18e65d990dc5c48d91a5a868d1 Mon Sep 17 00:00:00 2001 910 | From: Daniel Fullmer 911 | Date: Sat, 24 Oct 2020 17:02:30 -0700 912 | Subject: [PATCH 14/18] ARM: dts: sun8i: s3l: use flash for pinecube 913 | 914 | --- 915 | arch/arm/boot/dts/sun8i-s3-pinecube.dts | 2 +- 916 | 1 file changed, 1 insertion(+), 1 deletion(-) 917 | 918 | diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 919 | index 35e501ec8073..edfa6847735c 100644 920 | --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts 921 | +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 922 | @@ -218,7 +218,7 @@ &spi0 { 923 | flash@0 { 924 | #address-cells = <1>; 925 | #size-cells = <1>; 926 | - compatible = "winbond,w25q128", "jedec,spi-nor"; 927 | + compatible = "xtx,xt25f128b", "jedec,spi-nor"; 928 | reg = <0>; 929 | spi-max-frequency = <40000000>; 930 | }; 931 | -- 932 | 2.29.0 933 | 934 | 935 | From 7a7f126557d5d4910b908cb83f39fdb294dbcd05 Mon Sep 17 00:00:00 2001 936 | From: Icenowy Zheng 937 | Date: Fri, 20 Nov 2020 13:08:51 +0800 938 | Subject: [PATCH 15/18] ARM: dts: sun8i: v3s: fix GIC node memory range 939 | 940 | Currently the GIC node in V3s DTSI follows some old DT examples, and 941 | being broken. This leads a warning at boot. 942 | 943 | Fix this. 944 | 945 | Fixes: f989086ccbc6 ("ARM: dts: sunxi: add dtsi file for V3s SoC") 946 | Signed-off-by: Icenowy Zheng 947 | --- 948 | arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +- 949 | 1 file changed, 1 insertion(+), 1 deletion(-) 950 | 951 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 952 | index 0a933c9dc779..fe6339ad52b2 100644 953 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 954 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 955 | @@ -553,7 +553,7 @@ csi1: camera@1cb4000 { 956 | gic: interrupt-controller@1c81000 { 957 | compatible = "arm,gic-400"; 958 | reg = <0x01c81000 0x1000>, 959 | - <0x01c82000 0x1000>, 960 | + <0x01c82000 0x2000>, 961 | <0x01c84000 0x2000>, 962 | <0x01c86000 0x2000>; 963 | interrupt-controller; 964 | -- 965 | 2.29.0 966 | 967 | 968 | From aa361de51f3d0909c8e4c1ee8f9374e98f72ac06 Mon Sep 17 00:00:00 2001 969 | From: Icenowy Zheng 970 | Date: Sun, 22 Nov 2020 08:38:39 +0800 971 | Subject: [PATCH 16/18] ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes 972 | 973 | The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI 974 | controllers. 975 | 976 | Add the device nodes for the controllers. 977 | 978 | Signed-off-by: Icenowy Zheng 979 | --- 980 | arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++ 981 | 1 file changed, 19 insertions(+) 982 | 983 | diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi 984 | index fe6339ad52b2..ea26fef67bfa 100644 985 | --- a/arch/arm/boot/dts/sun8i-v3s.dtsi 986 | +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi 987 | @@ -279,6 +279,25 @@ usbphy: phy@1c19400 { 988 | #phy-cells = <1>; 989 | }; 990 | 991 | + ehci0: usb@1c1a000 { 992 | + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; 993 | + reg = <0x01c1a000 0x100>; 994 | + interrupts = ; 995 | + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 996 | + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 997 | + status = "disabled"; 998 | + }; 999 | + 1000 | + ohci0: usb@1c1a400 { 1001 | + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; 1002 | + reg = <0x01c1a400 0x100>; 1003 | + interrupts = ; 1004 | + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 1005 | + <&ccu CLK_USB_OHCI0>; 1006 | + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 1007 | + status = "disabled"; 1008 | + }; 1009 | + 1010 | ccu: clock@1c20000 { 1011 | compatible = "allwinner,sun8i-v3s-ccu"; 1012 | reg = <0x01c20000 0x400>; 1013 | -- 1014 | 2.29.0 1015 | 1016 | 1017 | From 65d891639488a741c2dfa3cdbeafae9a51634faa Mon Sep 17 00:00:00 2001 1018 | From: Icenowy Zheng 1019 | Date: Sun, 22 Nov 2020 08:40:10 +0800 1020 | Subject: [PATCH 17/18] ARM: dts: sun8i: v3s: enable EHCI/OHCI for Lichee Pi 1021 | Zero 1022 | 1023 | As the USB port on Lichee Pi Zero works in the OTG mode, enable the 1024 | EHCI/OHCI controllers for it. 1025 | 1026 | Signed-off-by: Icenowy Zheng 1027 | --- 1028 | arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++ 1029 | 1 file changed, 8 insertions(+) 1030 | 1031 | diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts 1032 | index 2e4587d26ce5..0cd969194acb 100644 1033 | --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts 1034 | +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts 1035 | @@ -77,6 +77,10 @@ red_led { 1036 | }; 1037 | }; 1038 | 1039 | +&ehci0 { 1040 | + status = "okay"; 1041 | +}; 1042 | + 1043 | &mmc0 { 1044 | broken-cd; 1045 | bus-width = <4>; 1046 | @@ -84,6 +88,10 @@ &mmc0 { 1047 | status = "okay"; 1048 | }; 1049 | 1050 | +&ohci0 { 1051 | + status = "okay"; 1052 | +}; 1053 | + 1054 | &uart0 { 1055 | pinctrl-0 = <&uart0_pb_pins>; 1056 | pinctrl-names = "default"; 1057 | -- 1058 | 2.29.0 1059 | 1060 | 1061 | From ca1700b440f7c4bf6abdc3db8d598b3e8b7d2a31 Mon Sep 17 00:00:00 2001 1062 | From: Icenowy Zheng 1063 | Date: Sun, 22 Nov 2020 08:40:11 +0800 1064 | Subject: [PATCH 18/18] ARM: dts: sun8i: s3: switch PineCube to use OHCI/EHCI 1065 | only 1066 | 1067 | The PineCube board features a USB Type-A connector connected to the 1068 | SoC's USB pins. 1069 | 1070 | As this is not designed for being used as a USB device, disable OTG 1071 | controller and route USB to OHCI/EHCI fixedly. 1072 | 1073 | Signed-off-by: Icenowy Zheng 1074 | --- 1075 | arch/arm/boot/dts/sun8i-s3-pinecube.dts | 17 ++++++++++++----- 1076 | 1 file changed, 12 insertions(+), 5 deletions(-) 1077 | 1078 | diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 1079 | index edfa6847735c..a852608e7666 100644 1080 | --- a/arch/arm/boot/dts/sun8i-s3-pinecube.dts 1081 | +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts 1082 | @@ -78,6 +78,12 @@ csi1_ep: endpoint { 1083 | }; 1084 | }; 1085 | 1086 | +&ehci0 { 1087 | + phys = <&usbphy 0>; 1088 | + phy-names = "usb"; 1089 | + status = "okay"; 1090 | +}; 1091 | + 1092 | &emac { 1093 | phy-handle = <&int_mii_phy>; 1094 | phy-mode = "mii"; 1095 | @@ -158,6 +164,12 @@ &mmc1 { 1096 | status = "okay"; 1097 | }; 1098 | 1099 | +&ohci0 { 1100 | + phys = <&usbphy 0>; 1101 | + phy-names = "usb"; 1102 | + status = "okay"; 1103 | +}; 1104 | + 1105 | &pio { 1106 | vcc-pd-supply = <®_dcdc3>; 1107 | vcc-pe-supply = <®_ldo3>; 1108 | @@ -228,11 +240,6 @@ &uart2 { 1109 | status = "okay"; 1110 | }; 1111 | 1112 | -&usb_otg { 1113 | - dr_mode = "host"; 1114 | - status = "okay"; 1115 | -}; 1116 | - 1117 | &usbphy { 1118 | usb0_vbus-supply = <®_vcc5v0>; 1119 | status = "okay"; 1120 | -- 1121 | 2.29.0 1122 | 1123 | -------------------------------------------------------------------------------- /sd-image.nix: -------------------------------------------------------------------------------- 1 | { config, pkgs, ... }: 2 | 3 | let 4 | uboot = pkgs.callPackage ./uboot {}; 5 | in 6 | { 7 | imports = [ 8 | 9 | ./configuration.nix 10 | ./cross-config.nix 11 | ]; 12 | 13 | sdImage.populateFirmwareCommands = ""; 14 | sdImage.populateRootCommands = '' 15 | mkdir -p ./files/boot 16 | ${config.boot.loader.generic-extlinux-compatible.populateCmd} -c ${config.system.build.toplevel} -d ./files/boot 17 | ''; 18 | sdImage.postBuildCommands = '' 19 | dd if=${uboot}/u-boot-sunxi-with-spl.bin of=$img bs=1024 seek=8 conv=notrunc 20 | ''; 21 | } 22 | -------------------------------------------------------------------------------- /uboot/Pine64-PineCube-uboot-support.patch: -------------------------------------------------------------------------------- 1 | From 8d78ca668de85ffcc6db523e87867475aee2a7a3 Mon Sep 17 00:00:00 2001 2 | From: Icenowy Zheng 3 | Date: Mon, 26 Oct 2020 22:15:59 +0800 4 | Subject: [PATCH 1/9] sunxi: add V3/S3 support 5 | 6 | Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes 7 | with no co-packaged DDR (DDR3 is usually used externally), and S3L comes 8 | with co-packaged DDR3. 9 | 10 | Add support for Allwinner V3/S3 chips by add SoC names to original V3s 11 | choice, and allow to select DDR3. 12 | 13 | Signed-off-by: Icenowy Zheng 14 | --- 15 | arch/arm/mach-sunxi/Kconfig | 3 +-- 16 | 1 file changed, 1 insertion(+), 2 deletions(-) 17 | 18 | diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig 19 | index be0822bfb7..31339ac2a1 100644 20 | --- a/arch/arm/mach-sunxi/Kconfig 21 | +++ b/arch/arm/mach-sunxi/Kconfig 22 | @@ -253,7 +253,7 @@ config MACH_SUN8I_R40 23 | select PHY_SUN4I_USB 24 | 25 | config MACH_SUN8I_V3S 26 | - bool "sun8i (Allwinner V3s)" 27 | + bool "sun8i (Allwinner V3/V3s/S3/S3L)" 28 | select CPU_V7A 29 | select CPU_V7_HAS_NONSEC 30 | select CPU_V7_HAS_VIRT 31 | @@ -363,7 +363,6 @@ choice 32 | config SUNXI_DRAM_DDR3_1333 33 | bool "DDR3 1333" 34 | select SUNXI_DRAM_DDR3 35 | - depends on !MACH_SUN8I_V3S 36 | ---help--- 37 | This option is the original only supported memory type, which suits 38 | many H3/H5/A64 boards available now. 39 | -- 40 | 2.28.0 41 | 42 | 43 | From 11de589ef2bcca811e936b75bb6c28ab1fbfbca1 Mon Sep 17 00:00:00 2001 44 | From: Icenowy Zheng 45 | Date: Mon, 26 Oct 2020 22:18:01 +0800 46 | Subject: [PATCH 2/9] sunxi: gpio: introduce compatible string for V3 GPIO 47 | 48 | A new compatible string is introduced for V3 GPIO, because it has more 49 | pins available than V3s. 50 | 51 | Add the compatible string to the GPIO driver. 52 | 53 | Signed-off-by: Icenowy Zheng 54 | --- 55 | drivers/gpio/sunxi_gpio.c | 1 + 56 | 1 file changed, 1 insertion(+) 57 | 58 | diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c 59 | index 9c3a4428e1..0329efab50 100644 60 | --- a/drivers/gpio/sunxi_gpio.c 61 | +++ b/drivers/gpio/sunxi_gpio.c 62 | @@ -351,6 +351,7 @@ static const struct udevice_id sunxi_gpio_ids[] = { 63 | ID("allwinner,sun8i-a83t-pinctrl", a_all), 64 | ID("allwinner,sun8i-h3-pinctrl", a_all), 65 | ID("allwinner,sun8i-r40-pinctrl", a_all), 66 | + ID("allwinner,sun8i-v3-pinctrl", a_all), 67 | ID("allwinner,sun8i-v3s-pinctrl", a_all), 68 | ID("allwinner,sun9i-a80-pinctrl", a_all), 69 | ID("allwinner,sun50i-a64-pinctrl", a_all), 70 | -- 71 | 2.28.0 72 | 73 | 74 | From 861a94b8a7d6c308d03e24328769da3406f8def8 Mon Sep 17 00:00:00 2001 75 | From: Icenowy Zheng 76 | Date: Mon, 26 Oct 2020 22:18:02 +0800 77 | Subject: [PATCH 3/9] clk: sunxi: add compatible string for V3 78 | 79 | A new compatible string is introduced for V3 CCU, because it has a few 80 | extra features available. 81 | 82 | Add the compatible string to the clock driver. As the extra features are 83 | not touched, just share the description struct now. 84 | 85 | Signed-off-by: Icenowy Zheng 86 | --- 87 | drivers/clk/sunxi/clk_v3s.c | 2 ++ 88 | 1 file changed, 2 insertions(+) 89 | 90 | diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c 91 | index b79446cc4f..f3fc06ab31 100644 92 | --- a/drivers/clk/sunxi/clk_v3s.c 93 | +++ b/drivers/clk/sunxi/clk_v3s.c 94 | @@ -56,6 +56,8 @@ static int v3s_clk_bind(struct udevice *dev) 95 | static const struct udevice_id v3s_clk_ids[] = { 96 | { .compatible = "allwinner,sun8i-v3s-ccu", 97 | .data = (ulong)&v3s_ccu_desc }, 98 | + { .compatible = "allwinner,sun8i-v3-ccu", 99 | + .data = (ulong)&v3s_ccu_desc }, 100 | { } 101 | }; 102 | 103 | -- 104 | 2.28.0 105 | 106 | 107 | From ea527e363442b93e55e129eb89aa4e42691a3aec Mon Sep 17 00:00:00 2001 108 | From: Icenowy Zheng 109 | Date: Mon, 26 Oct 2020 22:19:34 +0800 110 | Subject: [PATCH 4/9] sunxi: allow to use AXP20[39] attached to I2C0 on V3 111 | series 112 | 113 | The reference design of Allwinner V3 series uses an 114 | AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the 115 | first community-available V3s board, Lichee Pi Zero, omitted it. 116 | 117 | Allow to introduce support for the PMIC on boards with it. 118 | 119 | Signed-off-by: Icenowy Zheng 120 | --- 121 | arch/arm/include/asm/arch-sunxi/gpio.h | 1 + 122 | board/sunxi/board.c | 4 ++++ 123 | drivers/power/Kconfig | 4 ++-- 124 | 3 files changed, 7 insertions(+), 2 deletions(-) 125 | 126 | diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h 127 | index a646ea6a3c..f817d328f4 100644 128 | --- a/arch/arm/include/asm/arch-sunxi/gpio.h 129 | +++ b/arch/arm/include/asm/arch-sunxi/gpio.h 130 | @@ -158,6 +158,7 @@ enum sunxi_gpio_number { 131 | #define SUN5I_GPB_TWI1 2 132 | #define SUN4I_GPB_TWI2 2 133 | #define SUN5I_GPB_TWI2 2 134 | +#define SUN8I_V3S_GPB_TWI0 2 135 | #define SUN4I_GPB_UART0 2 136 | #define SUN5I_GPB_UART0 2 137 | #define SUN8I_GPB_UART2 2 138 | diff --git a/board/sunxi/board.c b/board/sunxi/board.c 139 | index f32e8f582f..4b37c9b77a 100644 140 | --- a/board/sunxi/board.c 141 | +++ b/board/sunxi/board.c 142 | @@ -101,6 +101,10 @@ void i2c_init_board(void) 143 | sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 144 | sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 145 | clock_twi_onoff(0, 1); 146 | +#elif defined(CONFIG_MACH_SUN8I_V3S) 147 | + sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0); 148 | + sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0); 149 | + clock_twi_onoff(0, 1); 150 | #elif defined(CONFIG_MACH_SUN8I) 151 | sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 152 | sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 153 | diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig 154 | index 5910926fac..02050f6f35 100644 155 | --- a/drivers/power/Kconfig 156 | +++ b/drivers/power/Kconfig 157 | @@ -14,7 +14,7 @@ choice 158 | default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 159 | default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 160 | default AXP818_POWER if MACH_SUN8I_A83T 161 | - default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I 162 | + default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_V3S 163 | 164 | config SUNXI_NO_PMIC 165 | bool "board without a pmic" 166 | @@ -32,7 +32,7 @@ config AXP152_POWER 167 | 168 | config AXP209_POWER 169 | bool "axp209 pmic support" 170 | - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I 171 | + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S 172 | select AXP_PMIC_BUS 173 | select CMD_POWEROFF 174 | ---help--- 175 | -- 176 | 2.28.0 177 | 178 | 179 | From f229ec30eb2390d204a2e63e140d52a7de9005ea Mon Sep 17 00:00:00 2001 180 | From: Icenowy Zheng 181 | Date: Mon, 26 Oct 2020 22:19:35 +0800 182 | Subject: [PATCH 5/9] sunxi: dts: sync Allwinner V3s-related DTs from Linux 183 | 5.10-rc1 184 | 185 | This commit imports device tree files that are related to Allwinner V3 186 | series from Linux commit 3650b228f83a ("Linux 5.10-rc1"). 187 | 188 | Signed-off-by: Icenowy Zheng 189 | --- 190 | arch/arm/dts/sun8i-s3-lichee-zero-plus.dts | 53 +++ 191 | arch/arm/dts/sun8i-s3-pinecube.dts | 235 +++++++++++++ 192 | arch/arm/dts/sun8i-v3.dtsi | 27 ++ 193 | arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 96 ++++++ 194 | arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 26 +- 195 | arch/arm/dts/sun8i-v3s.dtsi | 318 ++++++++++++++++-- 196 | 6 files changed, 725 insertions(+), 30 deletions(-) 197 | create mode 100644 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts 198 | create mode 100644 arch/arm/dts/sun8i-s3-pinecube.dts 199 | create mode 100644 arch/arm/dts/sun8i-v3.dtsi 200 | create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts 201 | 202 | diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts 203 | new file mode 100644 204 | index 0000000000..d18192d51d 205 | --- /dev/null 206 | +++ b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts 207 | @@ -0,0 +1,53 @@ 208 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 209 | +/* 210 | + * Copyright (C) 2019 Icenowy Zheng 211 | + */ 212 | + 213 | +/dts-v1/; 214 | +#include "sun8i-v3.dtsi" 215 | + 216 | +#include 217 | + 218 | +/ { 219 | + model = "Sipeed Lichee Zero Plus"; 220 | + compatible = "sipeed,lichee-zero-plus", "sochip,s3", 221 | + "allwinner,sun8i-v3"; 222 | + 223 | + aliases { 224 | + serial0 = &uart0; 225 | + }; 226 | + 227 | + chosen { 228 | + stdout-path = "serial0:115200n8"; 229 | + }; 230 | + 231 | + reg_vcc3v3: vcc3v3 { 232 | + compatible = "regulator-fixed"; 233 | + regulator-name = "vcc3v3"; 234 | + regulator-min-microvolt = <3300000>; 235 | + regulator-max-microvolt = <3300000>; 236 | + }; 237 | +}; 238 | + 239 | +&mmc0 { 240 | + broken-cd; 241 | + bus-width = <4>; 242 | + vmmc-supply = <®_vcc3v3>; 243 | + status = "okay"; 244 | +}; 245 | + 246 | +&uart0 { 247 | + pinctrl-0 = <&uart0_pb_pins>; 248 | + pinctrl-names = "default"; 249 | + status = "okay"; 250 | +}; 251 | + 252 | +&usb_otg { 253 | + dr_mode = "peripheral"; 254 | + status = "okay"; 255 | +}; 256 | + 257 | +&usbphy { 258 | + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 259 | + status = "okay"; 260 | +}; 261 | diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts 262 | new file mode 100644 263 | index 0000000000..9bab6b7f40 264 | --- /dev/null 265 | +++ b/arch/arm/dts/sun8i-s3-pinecube.dts 266 | @@ -0,0 +1,235 @@ 267 | +// SPDX-License-Identifier: (GPL-2.0+ OR X11) 268 | +/* 269 | + * Copyright 2019 Icenowy Zheng 270 | + */ 271 | + 272 | +/dts-v1/; 273 | +#include "sun8i-v3.dtsi" 274 | +#include 275 | +#include 276 | + 277 | +/ { 278 | + model = "PineCube IP Camera"; 279 | + compatible = "pine64,pinecube", "allwinner,sun8i-s3"; 280 | + 281 | + aliases { 282 | + serial0 = &uart2; 283 | + }; 284 | + 285 | + chosen { 286 | + stdout-path = "serial0:115200n8"; 287 | + }; 288 | + 289 | + leds { 290 | + compatible = "gpio-leds"; 291 | + 292 | + led1 { 293 | + label = "pine64:ir:led1"; 294 | + gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ 295 | + }; 296 | + 297 | + led2 { 298 | + label = "pine64:ir:led2"; 299 | + gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ 300 | + }; 301 | + }; 302 | + 303 | + reg_vcc5v0: vcc5v0 { 304 | + compatible = "regulator-fixed"; 305 | + regulator-name = "vcc5v0"; 306 | + regulator-min-microvolt = <5000000>; 307 | + regulator-max-microvolt = <5000000>; 308 | + }; 309 | + 310 | + reg_vcc_wifi: vcc-wifi { 311 | + compatible = "regulator-fixed"; 312 | + regulator-name = "vcc-wifi"; 313 | + regulator-min-microvolt = <3300000>; 314 | + regulator-max-microvolt = <3300000>; 315 | + gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ 316 | + vin-supply = <®_dcdc3>; 317 | + startup-delay-us = <200000>; 318 | + }; 319 | + 320 | + wifi_pwrseq: wifi_pwrseq { 321 | + compatible = "mmc-pwrseq-simple"; 322 | + reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ 323 | + post-power-on-delay-ms = <200>; 324 | + }; 325 | +}; 326 | + 327 | +&csi1 { 328 | + pinctrl-names = "default"; 329 | + pinctrl-0 = <&csi1_8bit_pins>; 330 | + status = "okay"; 331 | + 332 | + port { 333 | + #address-cells = <1>; 334 | + #size-cells = <0>; 335 | + 336 | + csi1_ep: endpoint { 337 | + remote-endpoint = <&ov5640_ep>; 338 | + bus-width = <8>; 339 | + hsync-active = <1>; /* Active high */ 340 | + vsync-active = <0>; /* Active low */ 341 | + data-active = <1>; /* Active high */ 342 | + pclk-sample = <1>; /* Rising */ 343 | + }; 344 | + }; 345 | +}; 346 | + 347 | +&emac { 348 | + phy-handle = <&int_mii_phy>; 349 | + phy-mode = "mii"; 350 | + status = "okay"; 351 | +}; 352 | + 353 | +&i2c0 { 354 | + status = "okay"; 355 | + 356 | + axp209: pmic@34 { 357 | + compatible = "x-powers,axp203", 358 | + "x-powers,axp209"; 359 | + reg = <0x34>; 360 | + interrupt-parent = <&gic>; 361 | + interrupts = ; 362 | + interrupt-controller; 363 | + #interrupt-cells = <1>; 364 | + }; 365 | +}; 366 | + 367 | +&i2c1 { 368 | + pinctrl-names = "default"; 369 | + pinctrl-0 = <&i2c1_pe_pins>; 370 | + status = "okay"; 371 | + 372 | + ov5640: camera@3c { 373 | + compatible = "ovti,ov5640"; 374 | + reg = <0x3c>; 375 | + pinctrl-names = "default"; 376 | + pinctrl-0 = <&csi1_mclk_pin>; 377 | + clocks = <&ccu CLK_CSI1_MCLK>; 378 | + clock-names = "xclk"; 379 | + 380 | + AVDD-supply = <®_ldo3>; 381 | + DOVDD-supply = <®_ldo3>; 382 | + DVDD-supply = <®_ldo4>; 383 | + reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ 384 | + powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ 385 | + 386 | + port { 387 | + ov5640_ep: endpoint { 388 | + remote-endpoint = <&csi1_ep>; 389 | + bus-width = <8>; 390 | + hsync-active = <1>; /* Active high */ 391 | + vsync-active = <0>; /* Active low */ 392 | + data-active = <1>; /* Active high */ 393 | + pclk-sample = <1>; /* Rising */ 394 | + }; 395 | + }; 396 | + }; 397 | +}; 398 | + 399 | +&lradc { 400 | + vref-supply = <®_ldo2>; 401 | + status = "okay"; 402 | + 403 | + button-200 { 404 | + label = "Setup"; 405 | + linux,code = ; 406 | + channel = <0>; 407 | + voltage = <190000>; 408 | + }; 409 | +}; 410 | + 411 | +&mmc0 { 412 | + vmmc-supply = <®_dcdc3>; 413 | + bus-width = <4>; 414 | + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; 415 | + status = "okay"; 416 | +}; 417 | + 418 | +&mmc1 { 419 | + vmmc-supply = <®_vcc_wifi>; 420 | + vqmmc-supply = <®_dcdc3>; 421 | + mmc-pwrseq = <&wifi_pwrseq>; 422 | + bus-width = <4>; 423 | + non-removable; 424 | + status = "okay"; 425 | +}; 426 | + 427 | +&pio { 428 | + vcc-pd-supply = <®_dcdc3>; 429 | + vcc-pe-supply = <®_ldo3>; 430 | +}; 431 | + 432 | +#include "axp209.dtsi" 433 | + 434 | +&ac_power_supply { 435 | + status = "okay"; 436 | +}; 437 | + 438 | +®_dcdc2 { 439 | + regulator-always-on; 440 | + regulator-min-microvolt = <1250000>; 441 | + regulator-max-microvolt = <1250000>; 442 | + regulator-name = "vdd-sys-cpu-ephy"; 443 | +}; 444 | + 445 | +®_dcdc3 { 446 | + regulator-always-on; 447 | + regulator-min-microvolt = <3300000>; 448 | + regulator-max-microvolt = <3300000>; 449 | + regulator-name = "vcc-3v3"; 450 | +}; 451 | + 452 | +®_ldo1 { 453 | + regulator-name = "vdd-rtc"; 454 | +}; 455 | + 456 | +®_ldo2 { 457 | + regulator-always-on; 458 | + regulator-min-microvolt = <3000000>; 459 | + regulator-max-microvolt = <3000000>; 460 | + regulator-name = "avcc"; 461 | +}; 462 | + 463 | +®_ldo3 { 464 | + regulator-min-microvolt = <2800000>; 465 | + regulator-max-microvolt = <2800000>; 466 | + regulator-name = "avdd-dovdd-2v8-csi"; 467 | + regulator-soft-start; 468 | + regulator-ramp-delay = <1600>; 469 | +}; 470 | + 471 | +®_ldo4 { 472 | + regulator-min-microvolt = <1800000>; 473 | + regulator-max-microvolt = <1800000>; 474 | + regulator-name = "dvdd-1v8-csi"; 475 | +}; 476 | + 477 | +&spi0 { 478 | + status = "okay"; 479 | + 480 | + flash@0 { 481 | + #address-cells = <1>; 482 | + #size-cells = <1>; 483 | + compatible = "winbond,w25q128", "jedec,spi-nor"; 484 | + reg = <0>; 485 | + spi-max-frequency = <40000000>; 486 | + }; 487 | +}; 488 | + 489 | +&uart2 { 490 | + status = "okay"; 491 | +}; 492 | + 493 | +&usb_otg { 494 | + dr_mode = "host"; 495 | + status = "okay"; 496 | +}; 497 | + 498 | +&usbphy { 499 | + usb0_vbus-supply = <®_vcc5v0>; 500 | + status = "okay"; 501 | +}; 502 | diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi 503 | new file mode 100644 504 | index 0000000000..ca4672ed2e 505 | --- /dev/null 506 | +++ b/arch/arm/dts/sun8i-v3.dtsi 507 | @@ -0,0 +1,27 @@ 508 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 509 | +/* 510 | + * Copyright (C) 2019 Icenowy Zheng 511 | + */ 512 | + 513 | +#include "sun8i-v3s.dtsi" 514 | + 515 | +&ccu { 516 | + compatible = "allwinner,sun8i-v3-ccu"; 517 | +}; 518 | + 519 | +&emac { 520 | + /delete-property/ phy-handle; 521 | + /delete-property/ phy-mode; 522 | +}; 523 | + 524 | +&mdio_mux { 525 | + external_mdio: mdio@2 { 526 | + reg = <2>; 527 | + #address-cells = <1>; 528 | + #size-cells = <0>; 529 | + }; 530 | +}; 531 | + 532 | +&pio { 533 | + compatible = "allwinner,sun8i-v3-pinctrl"; 534 | +}; 535 | diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts 536 | new file mode 100644 537 | index 0000000000..db5cd0b857 538 | --- /dev/null 539 | +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts 540 | @@ -0,0 +1,96 @@ 541 | +/* 542 | + * Copyright (C) 2016 Icenowy Zheng 543 | + * 544 | + * This file is dual-licensed: you can use it either under the terms 545 | + * of the GPL or the X11 license, at your option. Note that this dual 546 | + * licensing only applies to this file, and not this project as a 547 | + * whole. 548 | + * 549 | + * a) This file is free software; you can redistribute it and/or 550 | + * modify it under the terms of the GNU General Public License as 551 | + * published by the Free Software Foundation; either version 2 of the 552 | + * License, or (at your option) any later version. 553 | + * 554 | + * This file is distributed in the hope that it will be useful, 555 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of 556 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 557 | + * GNU General Public License for more details. 558 | + * 559 | + * Or, alternatively, 560 | + * 561 | + * b) Permission is hereby granted, free of charge, to any person 562 | + * obtaining a copy of this software and associated documentation 563 | + * files (the "Software"), to deal in the Software without 564 | + * restriction, including without limitation the rights to use, 565 | + * copy, modify, merge, publish, distribute, sublicense, and/or 566 | + * sell copies of the Software, and to permit persons to whom the 567 | + * Software is furnished to do so, subject to the following 568 | + * conditions: 569 | + * 570 | + * The above copyright notice and this permission notice shall be 571 | + * included in all copies or substantial portions of the Software. 572 | + * 573 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 574 | + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 575 | + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 576 | + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 577 | + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 578 | + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 579 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 580 | + * OTHER DEALINGS IN THE SOFTWARE. 581 | + */ 582 | + 583 | +#include "sun8i-v3s-licheepi-zero.dts" 584 | + 585 | +#include 586 | + 587 | +/ { 588 | + model = "Lichee Pi Zero with Dock"; 589 | + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", 590 | + "allwinner,sun8i-v3s"; 591 | + 592 | + leds { 593 | + /* The LEDs use PG0~2 pins, which conflict with MMC1 */ 594 | + status = "disabled"; 595 | + }; 596 | +}; 597 | + 598 | +&mmc1 { 599 | + broken-cd; 600 | + bus-width = <4>; 601 | + vmmc-supply = <®_vcc3v3>; 602 | + status = "okay"; 603 | +}; 604 | + 605 | +&lradc { 606 | + vref-supply = <®_vcc3v0>; 607 | + status = "okay"; 608 | + 609 | + button-200 { 610 | + label = "Volume Up"; 611 | + linux,code = ; 612 | + channel = <0>; 613 | + voltage = <200000>; 614 | + }; 615 | + 616 | + button-400 { 617 | + label = "Volume Down"; 618 | + linux,code = ; 619 | + channel = <0>; 620 | + voltage = <400000>; 621 | + }; 622 | + 623 | + button-600 { 624 | + label = "Select"; 625 | + linux,code = ; 626 | + channel = <0>; 627 | + voltage = <600000>; 628 | + }; 629 | + 630 | + button-800 { 631 | + label = "Start"; 632 | + linux,code = ; 633 | + channel = <0>; 634 | + voltage = <800000>; 635 | + }; 636 | +}; 637 | diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts 638 | index 3d9168cbae..2e4587d26c 100644 639 | --- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts 640 | +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts 641 | @@ -55,11 +55,29 @@ 642 | chosen { 643 | stdout-path = "serial0:115200n8"; 644 | }; 645 | + 646 | + leds { 647 | + compatible = "gpio-leds"; 648 | + 649 | + blue_led { 650 | + label = "licheepi:blue:usr"; 651 | + gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ 652 | + }; 653 | + 654 | + green_led { 655 | + label = "licheepi:green:usr"; 656 | + gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ 657 | + default-state = "on"; 658 | + }; 659 | + 660 | + red_led { 661 | + label = "licheepi:red:usr"; 662 | + gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ 663 | + }; 664 | + }; 665 | }; 666 | 667 | &mmc0 { 668 | - pinctrl-0 = <&mmc0_pins_a>; 669 | - pinctrl-names = "default"; 670 | broken-cd; 671 | bus-width = <4>; 672 | vmmc-supply = <®_vcc3v3>; 673 | @@ -67,7 +85,7 @@ 674 | }; 675 | 676 | &uart0 { 677 | - pinctrl-0 = <&uart0_pins_a>; 678 | + pinctrl-0 = <&uart0_pb_pins>; 679 | pinctrl-names = "default"; 680 | status = "okay"; 681 | }; 682 | @@ -78,6 +96,6 @@ 683 | }; 684 | 685 | &usbphy { 686 | - usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; 687 | + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 688 | status = "okay"; 689 | }; 690 | diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi 691 | index ebefc0fefe..0c73416769 100644 692 | --- a/arch/arm/dts/sun8i-v3s.dtsi 693 | +++ b/arch/arm/dts/sun8i-v3s.dtsi 694 | @@ -40,16 +40,31 @@ 695 | * OTHER DEALINGS IN THE SOFTWARE. 696 | */ 697 | 698 | +#include 699 | #include 700 | #include 701 | -#include 702 | -#include 703 | +#include 704 | 705 | / { 706 | #address-cells = <1>; 707 | #size-cells = <1>; 708 | interrupt-parent = <&gic>; 709 | 710 | + chosen { 711 | + #address-cells = <1>; 712 | + #size-cells = <1>; 713 | + ranges; 714 | + 715 | + framebuffer-lcd { 716 | + compatible = "allwinner,simple-framebuffer", 717 | + "simple-framebuffer"; 718 | + allwinner,pipeline = "mixer0-lcd0"; 719 | + clocks = <&display_clocks CLK_MIXER0>, 720 | + <&ccu CLK_TCON0>; 721 | + status = "disabled"; 722 | + }; 723 | + }; 724 | + 725 | cpus { 726 | #address-cells = <1>; 727 | #size-cells = <0>; 728 | @@ -62,6 +77,12 @@ 729 | }; 730 | }; 731 | 732 | + de: display-engine { 733 | + compatible = "allwinner,sun8i-v3s-display-engine"; 734 | + allwinner,pipelines = <&mixer0>; 735 | + status = "disabled"; 736 | + }; 737 | + 738 | timer { 739 | compatible = "arm,armv7-timer"; 740 | interrupts = , 741 | @@ -79,6 +100,7 @@ 742 | #clock-cells = <0>; 743 | compatible = "fixed-clock"; 744 | clock-frequency = <24000000>; 745 | + clock-accuracy = <50000>; 746 | clock-output-names = "osc24M"; 747 | }; 748 | 749 | @@ -86,7 +108,8 @@ 750 | #clock-cells = <0>; 751 | compatible = "fixed-clock"; 752 | clock-frequency = <32768>; 753 | - clock-output-names = "osc32k"; 754 | + clock-accuracy = <50000>; 755 | + clock-output-names = "ext-osc32k"; 756 | }; 757 | }; 758 | 759 | @@ -96,7 +119,86 @@ 760 | #size-cells = <1>; 761 | ranges; 762 | 763 | - mmc0: mmc@01c0f000 { 764 | + display_clocks: clock@1000000 { 765 | + compatible = "allwinner,sun8i-v3s-de2-clk"; 766 | + reg = <0x01000000 0x10000>; 767 | + clocks = <&ccu CLK_BUS_DE>, 768 | + <&ccu CLK_DE>; 769 | + clock-names = "bus", 770 | + "mod"; 771 | + resets = <&ccu RST_BUS_DE>; 772 | + #clock-cells = <1>; 773 | + #reset-cells = <1>; 774 | + }; 775 | + 776 | + mixer0: mixer@1100000 { 777 | + compatible = "allwinner,sun8i-v3s-de2-mixer"; 778 | + reg = <0x01100000 0x100000>; 779 | + clocks = <&display_clocks 0>, 780 | + <&display_clocks 6>; 781 | + clock-names = "bus", 782 | + "mod"; 783 | + resets = <&display_clocks 0>; 784 | + 785 | + ports { 786 | + #address-cells = <1>; 787 | + #size-cells = <0>; 788 | + 789 | + mixer0_out: port@1 { 790 | + reg = <1>; 791 | + 792 | + mixer0_out_tcon0: endpoint { 793 | + remote-endpoint = <&tcon0_in_mixer0>; 794 | + }; 795 | + }; 796 | + }; 797 | + }; 798 | + 799 | + syscon: system-control@1c00000 { 800 | + compatible = "allwinner,sun8i-v3s-system-control", 801 | + "allwinner,sun8i-h3-system-control"; 802 | + reg = <0x01c00000 0x1000>; 803 | + #address-cells = <1>; 804 | + #size-cells = <1>; 805 | + ranges; 806 | + }; 807 | + 808 | + tcon0: lcd-controller@1c0c000 { 809 | + compatible = "allwinner,sun8i-v3s-tcon"; 810 | + reg = <0x01c0c000 0x1000>; 811 | + interrupts = ; 812 | + clocks = <&ccu CLK_BUS_TCON0>, 813 | + <&ccu CLK_TCON0>; 814 | + clock-names = "ahb", 815 | + "tcon-ch0"; 816 | + clock-output-names = "tcon-pixel-clock"; 817 | + #clock-cells = <0>; 818 | + resets = <&ccu RST_BUS_TCON0>; 819 | + reset-names = "lcd"; 820 | + status = "disabled"; 821 | + 822 | + ports { 823 | + #address-cells = <1>; 824 | + #size-cells = <0>; 825 | + 826 | + tcon0_in: port@0 { 827 | + reg = <0>; 828 | + 829 | + tcon0_in_mixer0: endpoint { 830 | + remote-endpoint = <&mixer0_out_tcon0>; 831 | + }; 832 | + }; 833 | + 834 | + tcon0_out: port@1 { 835 | + #address-cells = <1>; 836 | + #size-cells = <0>; 837 | + reg = <1>; 838 | + }; 839 | + }; 840 | + }; 841 | + 842 | + 843 | + mmc0: mmc@1c0f000 { 844 | compatible = "allwinner,sun7i-a20-mmc"; 845 | reg = <0x01c0f000 0x1000>; 846 | clocks = <&ccu CLK_BUS_MMC0>, 847 | @@ -110,12 +212,14 @@ 848 | resets = <&ccu RST_BUS_MMC0>; 849 | reset-names = "ahb"; 850 | interrupts = ; 851 | + pinctrl-names = "default"; 852 | + pinctrl-0 = <&mmc0_pins>; 853 | status = "disabled"; 854 | #address-cells = <1>; 855 | #size-cells = <0>; 856 | }; 857 | 858 | - mmc1: mmc@01c10000 { 859 | + mmc1: mmc@1c10000 { 860 | compatible = "allwinner,sun7i-a20-mmc"; 861 | reg = <0x01c10000 0x1000>; 862 | clocks = <&ccu CLK_BUS_MMC1>, 863 | @@ -129,12 +233,14 @@ 864 | resets = <&ccu RST_BUS_MMC1>; 865 | reset-names = "ahb"; 866 | interrupts = ; 867 | + pinctrl-names = "default"; 868 | + pinctrl-0 = <&mmc1_pins>; 869 | status = "disabled"; 870 | #address-cells = <1>; 871 | #size-cells = <0>; 872 | }; 873 | 874 | - mmc2: mmc@01c11000 { 875 | + mmc2: mmc@1c11000 { 876 | compatible = "allwinner,sun7i-a20-mmc"; 877 | reg = <0x01c11000 0x1000>; 878 | clocks = <&ccu CLK_BUS_MMC2>, 879 | @@ -153,7 +259,18 @@ 880 | #size-cells = <0>; 881 | }; 882 | 883 | - usb_otg: usb@01c19000 { 884 | + crypto@1c15000 { 885 | + compatible = "allwinner,sun8i-v3s-crypto", 886 | + "allwinner,sun8i-a33-crypto"; 887 | + reg = <0x01c15000 0x1000>; 888 | + interrupts = ; 889 | + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 890 | + clock-names = "ahb", "mod"; 891 | + resets = <&ccu RST_BUS_CE>; 892 | + reset-names = "ahb"; 893 | + }; 894 | + 895 | + usb_otg: usb@1c19000 { 896 | compatible = "allwinner,sun8i-h3-musb"; 897 | reg = <0x01c19000 0x0400>; 898 | clocks = <&ccu CLK_BUS_OTG>; 899 | @@ -166,7 +283,7 @@ 900 | status = "disabled"; 901 | }; 902 | 903 | - usbphy: phy@01c19400 { 904 | + usbphy: phy@1c19400 { 905 | compatible = "allwinner,sun8i-v3s-usb-phy"; 906 | reg = <0x01c19400 0x2c>, 907 | <0x01c1a800 0x4>; 908 | @@ -180,64 +297,118 @@ 909 | #phy-cells = <1>; 910 | }; 911 | 912 | - ccu: clock@01c20000 { 913 | + ccu: clock@1c20000 { 914 | compatible = "allwinner,sun8i-v3s-ccu"; 915 | reg = <0x01c20000 0x400>; 916 | - clocks = <&osc24M>, <&osc32k>; 917 | + clocks = <&osc24M>, <&rtc 0>; 918 | clock-names = "hosc", "losc"; 919 | #clock-cells = <1>; 920 | #reset-cells = <1>; 921 | }; 922 | 923 | - rtc: rtc@01c20400 { 924 | - compatible = "allwinner,sun6i-a31-rtc"; 925 | + rtc: rtc@1c20400 { 926 | + #clock-cells = <1>; 927 | + compatible = "allwinner,sun8i-v3-rtc"; 928 | reg = <0x01c20400 0x54>; 929 | interrupts = , 930 | ; 931 | + clocks = <&osc32k>; 932 | + clock-output-names = "osc32k", "osc32k-out"; 933 | }; 934 | 935 | - pio: pinctrl@01c20800 { 936 | + pio: pinctrl@1c20800 { 937 | compatible = "allwinner,sun8i-v3s-pinctrl"; 938 | reg = <0x01c20800 0x400>; 939 | interrupts = , 940 | ; 941 | - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 942 | + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 943 | clock-names = "apb", "hosc", "losc"; 944 | gpio-controller; 945 | #gpio-cells = <3>; 946 | interrupt-controller; 947 | #interrupt-cells = <3>; 948 | 949 | - uart0_pins_a: uart0@0 { 950 | + /omit-if-no-ref/ 951 | + csi1_8bit_pins: csi1-8bit-pins { 952 | + pins = "PE0", "PE2", "PE3", "PE8", "PE9", 953 | + "PE10", "PE11", "PE12", "PE13", "PE14", 954 | + "PE15"; 955 | + function = "csi"; 956 | + }; 957 | + 958 | + /omit-if-no-ref/ 959 | + csi1_mclk_pin: csi1-mclk-pin { 960 | + pins = "PE1"; 961 | + function = "csi"; 962 | + }; 963 | + 964 | + i2c0_pins: i2c0-pins { 965 | + pins = "PB6", "PB7"; 966 | + function = "i2c0"; 967 | + }; 968 | + 969 | + /omit-if-no-ref/ 970 | + i2c1_pe_pins: i2c1-pe-pins { 971 | + pins = "PE21", "PE22"; 972 | + function = "i2c1"; 973 | + }; 974 | + 975 | + uart0_pb_pins: uart0-pb-pins { 976 | pins = "PB8", "PB9"; 977 | function = "uart0"; 978 | - bias-pull-up; 979 | }; 980 | 981 | - mmc0_pins_a: mmc0@0 { 982 | + uart2_pins: uart2-pins { 983 | + pins = "PB0", "PB1"; 984 | + function = "uart2"; 985 | + }; 986 | + 987 | + mmc0_pins: mmc0-pins { 988 | pins = "PF0", "PF1", "PF2", "PF3", 989 | "PF4", "PF5"; 990 | function = "mmc0"; 991 | drive-strength = <30>; 992 | bias-pull-up; 993 | }; 994 | + 995 | + mmc1_pins: mmc1-pins { 996 | + pins = "PG0", "PG1", "PG2", "PG3", 997 | + "PG4", "PG5"; 998 | + function = "mmc1"; 999 | + drive-strength = <30>; 1000 | + bias-pull-up; 1001 | + }; 1002 | + 1003 | + spi0_pins: spi0-pins { 1004 | + pins = "PC0", "PC1", "PC2", "PC3"; 1005 | + function = "spi0"; 1006 | + }; 1007 | }; 1008 | 1009 | - timer@01c20c00 { 1010 | - compatible = "allwinner,sun4i-a10-timer"; 1011 | + timer@1c20c00 { 1012 | + compatible = "allwinner,sun8i-v3s-timer"; 1013 | reg = <0x01c20c00 0xa0>; 1014 | interrupts = , 1015 | - ; 1016 | + , 1017 | + ; 1018 | clocks = <&osc24M>; 1019 | }; 1020 | 1021 | - wdt0: watchdog@01c20ca0 { 1022 | + wdt0: watchdog@1c20ca0 { 1023 | compatible = "allwinner,sun6i-a31-wdt"; 1024 | reg = <0x01c20ca0 0x20>; 1025 | interrupts = ; 1026 | + clocks = <&osc24M>; 1027 | + }; 1028 | + 1029 | + lradc: lradc@1c22800 { 1030 | + compatible = "allwinner,sun4i-a10-lradc-keys"; 1031 | + reg = <0x01c22800 0x400>; 1032 | + interrupts = ; 1033 | + status = "disabled"; 1034 | }; 1035 | 1036 | - uart0: serial@01c28000 { 1037 | + uart0: serial@1c28000 { 1038 | compatible = "snps,dw-apb-uart"; 1039 | reg = <0x01c28000 0x400>; 1040 | interrupts = ; 1041 | @@ -248,7 +419,7 @@ 1042 | status = "disabled"; 1043 | }; 1044 | 1045 | - uart1: serial@01c28400 { 1046 | + uart1: serial@1c28400 { 1047 | compatible = "snps,dw-apb-uart"; 1048 | reg = <0x01c28400 0x400>; 1049 | interrupts = ; 1050 | @@ -259,7 +430,7 @@ 1051 | status = "disabled"; 1052 | }; 1053 | 1054 | - uart2: serial@01c28800 { 1055 | + uart2: serial@1c28800 { 1056 | compatible = "snps,dw-apb-uart"; 1057 | reg = <0x01c28800 0x400>; 1058 | interrupts = ; 1059 | @@ -267,11 +438,106 @@ 1060 | reg-io-width = <4>; 1061 | clocks = <&ccu CLK_BUS_UART2>; 1062 | resets = <&ccu RST_BUS_UART2>; 1063 | + pinctrl-0 = <&uart2_pins>; 1064 | + pinctrl-names = "default"; 1065 | + status = "disabled"; 1066 | + }; 1067 | + 1068 | + i2c0: i2c@1c2ac00 { 1069 | + compatible = "allwinner,sun6i-a31-i2c"; 1070 | + reg = <0x01c2ac00 0x400>; 1071 | + interrupts = ; 1072 | + clocks = <&ccu CLK_BUS_I2C0>; 1073 | + resets = <&ccu RST_BUS_I2C0>; 1074 | + pinctrl-names = "default"; 1075 | + pinctrl-0 = <&i2c0_pins>; 1076 | + status = "disabled"; 1077 | + #address-cells = <1>; 1078 | + #size-cells = <0>; 1079 | + }; 1080 | + 1081 | + i2c1: i2c@1c2b000 { 1082 | + compatible = "allwinner,sun6i-a31-i2c"; 1083 | + reg = <0x01c2b000 0x400>; 1084 | + interrupts = ; 1085 | + clocks = <&ccu CLK_BUS_I2C1>; 1086 | + resets = <&ccu RST_BUS_I2C1>; 1087 | + status = "disabled"; 1088 | + #address-cells = <1>; 1089 | + #size-cells = <0>; 1090 | + }; 1091 | + 1092 | + emac: ethernet@1c30000 { 1093 | + compatible = "allwinner,sun8i-v3s-emac"; 1094 | + syscon = <&syscon>; 1095 | + reg = <0x01c30000 0x10000>; 1096 | + interrupts = ; 1097 | + interrupt-names = "macirq"; 1098 | + resets = <&ccu RST_BUS_EMAC>; 1099 | + reset-names = "stmmaceth"; 1100 | + clocks = <&ccu CLK_BUS_EMAC>; 1101 | + clock-names = "stmmaceth"; 1102 | + phy-handle = <&int_mii_phy>; 1103 | + phy-mode = "mii"; 1104 | + status = "disabled"; 1105 | + 1106 | + mdio: mdio { 1107 | + #address-cells = <1>; 1108 | + #size-cells = <0>; 1109 | + compatible = "snps,dwmac-mdio"; 1110 | + }; 1111 | + 1112 | + mdio_mux: mdio-mux { 1113 | + compatible = "allwinner,sun8i-h3-mdio-mux"; 1114 | + #address-cells = <1>; 1115 | + #size-cells = <0>; 1116 | + 1117 | + mdio-parent-bus = <&mdio>; 1118 | + /* Only one MDIO is usable at the time */ 1119 | + internal_mdio: mdio@1 { 1120 | + compatible = "allwinner,sun8i-h3-mdio-internal"; 1121 | + reg = <1>; 1122 | + #address-cells = <1>; 1123 | + #size-cells = <0>; 1124 | + 1125 | + int_mii_phy: ethernet-phy@1 { 1126 | + compatible = "ethernet-phy-ieee802.3-c22"; 1127 | + reg = <1>; 1128 | + clocks = <&ccu CLK_BUS_EPHY>; 1129 | + resets = <&ccu RST_BUS_EPHY>; 1130 | + }; 1131 | + }; 1132 | + }; 1133 | + }; 1134 | + 1135 | + spi0: spi@1c68000 { 1136 | + compatible = "allwinner,sun8i-h3-spi"; 1137 | + reg = <0x01c68000 0x1000>; 1138 | + interrupts = ; 1139 | + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1140 | + clock-names = "ahb", "mod"; 1141 | + pinctrl-names = "default"; 1142 | + pinctrl-0 = <&spi0_pins>; 1143 | + resets = <&ccu RST_BUS_SPI0>; 1144 | + status = "disabled"; 1145 | + #address-cells = <1>; 1146 | + #size-cells = <0>; 1147 | + }; 1148 | + 1149 | + csi1: camera@1cb4000 { 1150 | + compatible = "allwinner,sun8i-v3s-csi"; 1151 | + reg = <0x01cb4000 0x3000>; 1152 | + interrupts = ; 1153 | + clocks = <&ccu CLK_BUS_CSI>, 1154 | + <&ccu CLK_CSI1_SCLK>, 1155 | + <&ccu CLK_DRAM_CSI>; 1156 | + clock-names = "bus", "mod", "ram"; 1157 | + resets = <&ccu RST_BUS_CSI>; 1158 | status = "disabled"; 1159 | }; 1160 | 1161 | - gic: interrupt-controller@01c81000 { 1162 | - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1163 | + gic: interrupt-controller@1c81000 { 1164 | + compatible = "arm,gic-400"; 1165 | reg = <0x01c81000 0x1000>, 1166 | <0x01c82000 0x1000>, 1167 | <0x01c84000 0x2000>, 1168 | -- 1169 | 2.28.0 1170 | 1171 | 1172 | From b3972695f62ccbde205b304e159b3423662cc048 Mon Sep 17 00:00:00 2001 1173 | From: Icenowy Zheng 1174 | Date: Mon, 26 Oct 2020 22:21:00 +0800 1175 | Subject: [PATCH 6/9] sunxi: add PineCube board 1176 | 1177 | PineCube is an IP camera development kit released by Pine64. 1178 | 1179 | It comes with the following compoents: 1180 | 1181 | - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, 1182 | a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps 1183 | Ethernet port and FPC connectors for camera and daughter board. 1184 | - An OV5640-based camera module which is connected to the parallel CSI 1185 | bus of the mainboard. 1186 | - A daughterboard with several buttons, a SD slot, some IR LEDs, a 1187 | microphone and a speaker connector. 1188 | 1189 | As the device tree is synchronized in a previous commit, just add 1190 | MAINTAINER item and a defconfig. 1191 | 1192 | Signed-off-by: Icenowy Zheng 1193 | Acked-by: Maxime Ripard 1194 | --- 1195 | board/sunxi/MAINTAINERS | 5 +++++ 1196 | configs/pinecube_defconfig | 17 +++++++++++++++++ 1197 | 2 files changed, 22 insertions(+) 1198 | create mode 100644 configs/pinecube_defconfig 1199 | 1200 | diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS 1201 | index 1180b86db3..5c53b2c878 100644 1202 | --- a/board/sunxi/MAINTAINERS 1203 | +++ b/board/sunxi/MAINTAINERS 1204 | @@ -440,6 +440,11 @@ M: Vasily Khoruzhick 1205 | S: Maintained 1206 | F: configs/pinebook_defconfig 1207 | 1208 | +PINECUBE BOARD: 1209 | +M: Icenowy Zheng 1210 | +S: Maintained 1211 | +F: configs/pinecube_defconfig 1212 | + 1213 | PINE64 BOARDS 1214 | M: Andre Przywara 1215 | S: Maintained 1216 | diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig 1217 | new file mode 100644 1218 | index 0000000000..107562ee49 1219 | --- /dev/null 1220 | +++ b/configs/pinecube_defconfig 1221 | @@ -0,0 +1,17 @@ 1222 | +CONFIG_ARM=y 1223 | +CONFIG_ARCH_SUNXI=y 1224 | +CONFIG_SPL=y 1225 | +CONFIG_MACH_SUN8I_V3S=y 1226 | +CONFIG_SUNXI_DRAM_DDR3_1333=y 1227 | +CONFIG_DRAM_CLK=504 1228 | +CONFIG_DRAM_ODT_EN=y 1229 | +CONFIG_I2C0_ENABLE=y 1230 | +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" 1231 | +CONFIG_SPL_I2C_SUPPORT=y 1232 | +# CONFIG_NETDEVICES is not set 1233 | +CONFIG_AXP209_POWER=y 1234 | +CONFIG_AXP_DCDC2_VOLT=1250 1235 | +CONFIG_AXP_DCDC3_VOLT=3300 1236 | +CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y 1237 | +CONFIG_AXP_ALDO3_INRUSH_QUIRK=y 1238 | +CONFIG_CONS_INDEX=3 1239 | -- 1240 | 2.28.0 1241 | 1242 | 1243 | From 1d653d30f47f2730bb8039d328271389a120e87d Mon Sep 17 00:00:00 2001 1244 | From: Daniel Fullmer 1245 | Date: Mon, 19 Oct 2020 22:50:57 -0700 1246 | Subject: [PATCH 7/9] sun8i-emac: sun8i-v3s compatibility for sun8i-emac 1247 | 1248 | This patch expands the sun8i-emac driver to support the V3s. 1249 | For this the CLK and RST gates for EMAC and EPHY were added in clk_v3s.c 1250 | 1251 | Based on original patch by Benedikt-Alexander Mokru? 1252 | --- 1253 | drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 1254 | drivers/net/sun8i_emac.c | 15 +++++++++++---- 1255 | 2 files changed, 17 insertions(+), 4 deletions(-) 1256 | 1257 | diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c 1258 | index f3fc06ab31..91ae457e19 100644 1259 | --- a/drivers/clk/sunxi/clk_v3s.c 1260 | +++ b/drivers/clk/sunxi/clk_v3s.c 1261 | @@ -17,6 +17,7 @@ static struct ccu_clk_gate v3s_gates[] = { 1262 | [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 1263 | [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 1264 | [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 1265 | + [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 1266 | [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 1267 | [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 1268 | 1269 | @@ -24,6 +25,8 @@ static struct ccu_clk_gate v3s_gates[] = { 1270 | [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), 1271 | [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), 1272 | 1273 | + [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), 1274 | + 1275 | [CLK_SPI0] = GATE(0x0a0, BIT(31)), 1276 | 1277 | [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), 1278 | @@ -35,12 +38,15 @@ static struct ccu_reset v3s_resets[] = { 1279 | [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), 1280 | [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), 1281 | [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), 1282 | + [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), 1283 | [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), 1284 | [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), 1285 | 1286 | [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), 1287 | [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), 1288 | [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), 1289 | + 1290 | + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), 1291 | }; 1292 | 1293 | static const struct ccu_desc v3s_ccu_desc = { 1294 | diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c 1295 | index e2b05ace8f..29d68d5c2d 100644 1296 | --- a/drivers/net/sun8i_emac.c 1297 | +++ b/drivers/net/sun8i_emac.c 1298 | @@ -56,9 +56,11 @@ 1299 | #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) 1300 | 1301 | #define H3_EPHY_DEFAULT_VALUE 0x58000 1302 | +#define V3S_EPHY_DEFAULT_VALUE 0x38000 1303 | #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) 1304 | #define H3_EPHY_ADDR_SHIFT 20 1305 | #define REG_PHY_ADDR_MASK GENMASK(4, 0) 1306 | +#define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */ 1307 | #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ 1308 | #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ 1309 | #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ 1310 | @@ -112,6 +114,7 @@ enum emac_variant { 1311 | A64_EMAC, 1312 | R40_GMAC, 1313 | H6_EMAC, 1314 | + V3S_EMAC, 1315 | }; 1316 | 1317 | struct emac_dma_desc { 1318 | @@ -279,10 +282,11 @@ static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) 1319 | * needs to be configured and powered up before use 1320 | */ 1321 | *reg &= ~H3_EPHY_DEFAULT_MASK; 1322 | - *reg |= H3_EPHY_DEFAULT_VALUE; 1323 | + *reg |= ((priv->variant == V3S_EMAC) ? V3S_EPHY_DEFAULT_VALUE : H3_EPHY_DEFAULT_VALUE); 1324 | *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; 1325 | *reg &= ~H3_EPHY_SHUTDOWN; 1326 | *reg |= H3_EPHY_SELECT; 1327 | + *reg |= H3_EPHY_CLK_SEL; 1328 | } else 1329 | /* This is to select External Gigabit PHY on 1330 | * the boards with H3 SoC. 1331 | @@ -311,7 +315,7 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, 1332 | 1333 | reg = readl(priv->sysctl_reg + 0x30); 1334 | 1335 | - if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) { 1336 | + if (priv->variant == H3_EMAC || priv->variant == H6_EMAC || priv->variant == V3S_EMAC) { 1337 | ret = sun8i_emac_set_syscon_ephy(priv, ®); 1338 | if (ret) 1339 | return ret; 1340 | @@ -320,7 +324,8 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, 1341 | reg &= ~(SC_ETCS_MASK | SC_EPIT); 1342 | if (priv->variant == H3_EMAC || 1343 | priv->variant == A64_EMAC || 1344 | - priv->variant == H6_EMAC) 1345 | + priv->variant == H6_EMAC || 1346 | + priv->variant == V3S_EMAC) 1347 | reg &= ~SC_RMII_EN; 1348 | 1349 | switch (priv->interface) { 1350 | @@ -985,7 +990,7 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) 1351 | return -EINVAL; 1352 | } 1353 | 1354 | - if (priv->variant == H3_EMAC) { 1355 | + if (priv->variant == H3_EMAC || priv->variant == V3S_EMAC) { 1356 | ret = sun8i_get_ephy_nodes(priv); 1357 | if (ret) 1358 | return ret; 1359 | @@ -1038,6 +1043,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { 1360 | .data = (uintptr_t)R40_GMAC }, 1361 | {.compatible = "allwinner,sun50i-h6-emac", 1362 | .data = (uintptr_t)H6_EMAC }, 1363 | + {.compatible = "allwinner,sun8i-v3s-emac", 1364 | + .data = (uintptr_t)V3S_EMAC }, 1365 | { } 1366 | }; 1367 | 1368 | -- 1369 | 2.28.0 1370 | 1371 | 1372 | From ad232d117506ba382ee766f406ea35b7809bdcac Mon Sep 17 00:00:00 2001 1373 | From: Daniel Fullmer 1374 | Date: Sat, 24 Oct 2020 17:21:51 -0700 1375 | Subject: [PATCH 8/9] mtd: spi-nor-ids: add XTX xt25f32b/xt25f128b flash 1376 | 1377 | --- 1378 | drivers/mtd/spi/Kconfig | 6 ++++++ 1379 | drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1380 | 2 files changed, 11 insertions(+) 1381 | 1382 | diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig 1383 | index 018e8c597e..723485ba79 100644 1384 | --- a/drivers/mtd/spi/Kconfig 1385 | +++ b/drivers/mtd/spi/Kconfig 1386 | @@ -152,6 +152,12 @@ config SPI_FLASH_XMC 1387 | Add support for various XMC (Wuhan Xinxin Semiconductor 1388 | Manufacturing Corp.) SPI flash chips (XM25xxx) 1389 | 1390 | +config SPI_FLASH_XTX 1391 | + bool "XTX SPI flash support" 1392 | + help 1393 | + Add support for various XTX (Shenzhen Xin Tian Xia Tech) SPI flash 1394 | + chips (XTX25FxxxB) 1395 | + 1396 | endif 1397 | 1398 | config SPI_FLASH_USE_4K_SECTORS 1399 | diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c 1400 | index 114ebacde1..e470ba24bd 100644 1401 | --- a/drivers/mtd/spi/spi-nor-ids.c 1402 | +++ b/drivers/mtd/spi/spi-nor-ids.c 1403 | @@ -319,6 +319,11 @@ const struct flash_info spi_nor_ids[] = { 1404 | /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 1405 | { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1406 | { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1407 | +#endif 1408 | +#ifdef CONFIG_SPI_FLASH_XTX 1409 | + /* XTX (Shenzhen Xin Tian Xia Tech) */ 1410 | + { INFO("xt25f32b", 0x0b4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1411 | + { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 1412 | #endif 1413 | { }, 1414 | }; 1415 | -- 1416 | 2.28.0 1417 | 1418 | 1419 | From 443970856fdd30b51a6c59528127262568ac5c7f Mon Sep 17 00:00:00 2001 1420 | From: Daniel Fullmer 1421 | Date: Tue, 27 Oct 2020 18:44:03 -0700 1422 | Subject: [PATCH 9/9] pinecube: enable ethernet, SPI booting/flashing 1423 | 1424 | --- 1425 | arch/arm/dts/Makefile | 3 ++- 1426 | arch/arm/dts/sun8i-s3-pinecube.dts | 4 +++- 1427 | configs/pinecube_defconfig | 10 ++++++++-- 1428 | 3 files changed, 13 insertions(+), 4 deletions(-) 1429 | 1430 | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile 1431 | index 9900b44274..74cee045e6 100644 1432 | --- a/arch/arm/dts/Makefile 1433 | +++ b/arch/arm/dts/Makefile 1434 | @@ -563,7 +563,8 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ 1435 | sun8i-r40-bananapi-m2-ultra.dtb \ 1436 | sun8i-v40-bananapi-m2-berry.dtb 1437 | dtb-$(CONFIG_MACH_SUN8I_V3S) += \ 1438 | - sun8i-v3s-licheepi-zero.dtb 1439 | + sun8i-v3s-licheepi-zero.dtb \ 1440 | + sun8i-s3-pinecube.dtb 1441 | dtb-$(CONFIG_MACH_SUN50I_H5) += \ 1442 | sun50i-h5-bananapi-m2-plus.dtb \ 1443 | sun50i-h5-emlid-neutis-n5-devboard.dtb \ 1444 | diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts 1445 | index 9bab6b7f40..f83f16a83d 100644 1446 | --- a/arch/arm/dts/sun8i-s3-pinecube.dts 1447 | +++ b/arch/arm/dts/sun8i-s3-pinecube.dts 1448 | @@ -13,7 +13,9 @@ 1449 | compatible = "pine64,pinecube", "allwinner,sun8i-s3"; 1450 | 1451 | aliases { 1452 | + ethernet0 = &emac; 1453 | serial0 = &uart2; 1454 | + spi0 = &spi0; 1455 | }; 1456 | 1457 | chosen { 1458 | @@ -214,7 +216,7 @@ 1459 | flash@0 { 1460 | #address-cells = <1>; 1461 | #size-cells = <1>; 1462 | - compatible = "winbond,w25q128", "jedec,spi-nor"; 1463 | + compatible = "xtx,xt25f128b", "jedec,spi-nor"; 1464 | reg = <0>; 1465 | spi-max-frequency = <40000000>; 1466 | }; 1467 | diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig 1468 | index 107562ee49..fec01aeb64 100644 1469 | --- a/configs/pinecube_defconfig 1470 | +++ b/configs/pinecube_defconfig 1471 | @@ -6,12 +6,18 @@ CONFIG_SUNXI_DRAM_DDR3_1333=y 1472 | CONFIG_DRAM_CLK=504 1473 | CONFIG_DRAM_ODT_EN=y 1474 | CONFIG_I2C0_ENABLE=y 1475 | -CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" 1476 | CONFIG_SPL_I2C_SUPPORT=y 1477 | -# CONFIG_NETDEVICES is not set 1478 | +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" 1479 | +CONFIG_DM_MTD=y 1480 | +CONFIG_DM_SPI_FLASH=y 1481 | +CONFIG_SPI_FLASH_SFDP_SUPPORT=y 1482 | +CONFIG_SPI_FLASH_XTX=y 1483 | +CONFIG_SUN8I_EMAC=y 1484 | CONFIG_AXP209_POWER=y 1485 | CONFIG_AXP_DCDC2_VOLT=1250 1486 | CONFIG_AXP_DCDC3_VOLT=3300 1487 | CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y 1488 | CONFIG_AXP_ALDO3_INRUSH_QUIRK=y 1489 | CONFIG_CONS_INDEX=3 1490 | +CONFIG_SPI=y 1491 | +CONFIG_DM_SPI=y 1492 | -- 1493 | 2.28.0 1494 | 1495 | -------------------------------------------------------------------------------- /uboot/default.nix: -------------------------------------------------------------------------------- 1 | { pkgs }: 2 | 3 | pkgs.buildUBoot { 4 | patches = [ ./Pine64-PineCube-uboot-support.patch ]; 5 | 6 | defconfig = "pinecube_defconfig"; 7 | 8 | # Putting this here because it's more a design choice and not generic support 9 | # for hardware. 10 | extraConfig = '' 11 | CONFIG_CMD_BOOTMENU=y 12 | ''; 13 | 14 | extraMeta.platforms = ["armv7l-linux"]; 15 | filesToInstall = ["u-boot-sunxi-with-spl.bin"]; 16 | 17 | } 18 | -------------------------------------------------------------------------------- /uboot/spi-installer.nix: -------------------------------------------------------------------------------- 1 | { pkgs 2 | , e2fsprogs 3 | , runCommandNoCC 4 | , uboot 5 | , utillinux 6 | , ubootTools 7 | }: 8 | 9 | # Adapted from https://github.com/samueldr/wip-pinebook-pro/u-boot/spi-installer.nix 10 | # Thanks to samueldr! 11 | let 12 | board = "sunxi"; # TODO: Can this be pinecube? need to get ${board_name} in uboot to say that 13 | 14 | flashscript = pkgs.writeText "${board}-flash.cmd" '' 15 | echo 16 | echo 17 | echo ${board} firmware installer 18 | echo 19 | echo 20 | 21 | if load ''${devtype} ''${devnum}:''${bootpart} ''${kernel_addr_r} ''${board_name}.spiflash.bin; then 22 | sf probe 23 | sf erase 0 +$filesize 24 | sf write $kernel_addr_r 0 $filesize 25 | echo "Flashing seems to have been successful! Resetting in 5 seconds" 26 | sleep 5 27 | reset 28 | fi 29 | 30 | ''; 31 | 32 | bootcmd = pkgs.writeText "${board}-boot.cmd" '' 33 | setenv bootmenu_0 'Flash firmware to SPI=setenv script flash.scr; run boot_a_script' 34 | setenv bootmenu_1 'Completely erase SPI=sf probe; echo "Currently erasing..."; sf erase 0 +1000000; echo "Done!"; sleep 5; bootmenu -1' 35 | setenv bootmenu_2 'Reboot=reset' 36 | setenv bootmenu_3 37 | bootmenu -1 38 | ''; 39 | 40 | mkScript = file: runCommandNoCC "${board}-boot.scr" { 41 | nativeBuildInputs = [ 42 | ubootTools 43 | ]; 44 | } '' 45 | mkimage -C none -A arm -T script -d ${file} $out 46 | ''; 47 | 48 | rootfsImage = runCommandNoCC "u-boot-installer-fs.img" { 49 | inherit board; 50 | size = "8"; # in MiB 51 | nativeBuildInputs = [ 52 | e2fsprogs.bin 53 | utillinux 54 | ]; 55 | volumeLabel = "FIRMWARE_INSTALL"; 56 | uuid = "666efd84-5c25-48ec-af06-e9dadbaa830f"; 57 | } '' 58 | img="$out" 59 | (PS4=" $ "; set -x 60 | 61 | truncate -s "$size"M $img 62 | 63 | mkdir -p files 64 | (cd ./files 65 | cp -v ${mkScript bootcmd} ./boot.scr 66 | cp -v ${mkScript flashscript} ./flash.scr 67 | cp -v ${uboot}/u-boot-sunxi-with-spl.bin ./"$board".spiflash.bin 68 | ) 69 | 70 | mkfs.ext4 -L $volumeLabel -U $uuid -d ./files $img 71 | ) 72 | ''; 73 | in 74 | 75 | runCommandNoCC "u-boot-installer" { 76 | nativeBuildInputs = [ 77 | utillinux 78 | ]; 79 | # -r--r--r-- 1 root root 1012K Dec 31 1969 u-boot.itb 80 | # Flashed at exactly 8MiB in 81 | gapSize = "10"; # in MiB 82 | } '' 83 | (PS4=" $ "; set -x 84 | mkdir -p $out 85 | 86 | img=$out/firmware-installer-image.img 87 | 88 | # Create the image file sized to fit the gap and /, plus slack. 89 | rootSizeBlocks=$(du -B 512 --apparent-size ${rootfsImage} | awk '{ print $1 }') 90 | gapSizeBlocks=$(($gapSize * 1024 * 1024 / 512)) 91 | imageSize=$((rootSizeBlocks * 512 + gapSizeBlocks * 512)) 92 | truncate -s $imageSize $img 93 | 94 | # type=b is 'W95 FAT32', type=83 is 'Linux'. 95 | # The "bootable" partition is where u-boot will look file for the bootloader 96 | # information (dtbs, extlinux.conf file). 97 | sfdisk $img <