├── .bazelversion ├── .gitattributes ├── .github └── workflows │ └── Linux.yml ├── .gitignore ├── BUILD.bazel ├── LICENSE ├── MODULE.bazel ├── MODULE.bazel.lock ├── Makefile ├── README.md ├── boards ├── Makefile ├── README.md ├── aliexpress_hpc40gbe_k420 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── aliexpress_hpc40gbe_xcku040 │ ├── README.md │ ├── darksocv.xdc │ └── darksocv.xpr ├── avnet_microboard_lx9 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── colorlighti5 │ ├── README.md │ ├── build.sh │ ├── darksocv.lpf │ ├── pll_ref_25MHz.v │ └── upload.sh ├── colorlighti9 │ ├── README.md │ ├── build.sh │ ├── darksocv.lpf │ ├── pll_ref_25MHz.v │ └── upload.sh ├── de10nano_cyclonev_mister │ ├── LICENSE │ ├── README.md │ ├── _darkram.v │ ├── bin2mif.sh │ ├── darkriscv_de10nano.qpf │ ├── darkriscv_de10nano.qsf │ ├── darkriscv_de10nano.sdc │ ├── darkriscv_de10nano.sv │ ├── darksocv.mk │ ├── dut.v │ ├── files.qip │ ├── jtag.cdf │ ├── mem2bin.sh │ ├── rtl │ │ ├── pll.qip │ │ ├── pll.v │ │ ├── pll │ │ │ ├── pll_0002.qip │ │ │ ├── pll_0002.v │ │ │ └── pll_0002_q13.qip │ │ └── vga.v │ └── sys │ │ ├── alsa.sv │ │ ├── arcade_video.v │ │ ├── ascal.vhd │ │ ├── audio_out.v │ │ ├── build_id.tcl │ │ ├── ddr_svc.sv │ │ ├── f2sdram_safe_terminator.sv │ │ ├── gamma_corr.sv │ │ ├── hdmi_config.sv │ │ ├── hps_io.v │ │ ├── hq2x.sv │ │ ├── i2c.v │ │ ├── i2s.v │ │ ├── iir_filter.v │ │ ├── ltc2308.sv │ │ ├── math.sv │ │ ├── mcp23009.sv │ │ ├── mt32pi.sv │ │ ├── osd.v │ │ ├── pll.13.qip │ │ ├── pll_audio.13.qip │ │ ├── pll_audio.qip │ │ ├── pll_audio.v │ │ ├── pll_audio │ │ ├── pll_audio_0002.qip │ │ └── pll_audio_0002.v │ │ ├── pll_cfg.qip │ │ ├── pll_cfg.v │ │ ├── pll_cfg │ │ ├── altera_pll_reconfig_core.v │ │ └── altera_pll_reconfig_top.v │ │ ├── pll_hdmi.13.qip │ │ ├── pll_hdmi.qip │ │ ├── pll_hdmi.v │ │ ├── pll_hdmi │ │ ├── pll_hdmi_0002.qip │ │ └── pll_hdmi_0002.v │ │ ├── pll_hdmi_adj.vhd │ │ ├── pll_q13.qip │ │ ├── pll_q17.qip │ │ ├── scandoubler.v │ │ ├── scanlines.v │ │ ├── sd_card.sv │ │ ├── sigma_delta_dac.v │ │ ├── spdif.v │ │ ├── sys.qip │ │ ├── sys.tcl │ │ ├── sys_analog.tcl │ │ ├── sys_dual_sdram.tcl │ │ ├── sys_top.sdc │ │ ├── sys_top.v │ │ ├── sysmem.sv │ │ ├── vga_out.sv │ │ ├── video_cleaner.sv │ │ ├── video_freak.sv │ │ └── video_mixer.sv ├── digilent_spartan3_s200 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── ice40_breakout_hx8k │ ├── README.md │ ├── build.sh │ ├── darksocv.pcf │ ├── pll.v │ └── upload.sh ├── lattice_brevia2_xp2 │ ├── .gitignore │ ├── README.md │ ├── build.sh │ ├── darksocv.ldf │ ├── darksocv.lpf │ ├── darksocv.mk │ ├── darksocv.tcl │ ├── darksocv1.sty │ └── lattice_brevia2_xp2.xcf ├── max1000_max10 │ ├── README.md │ ├── _darkram.v │ ├── bin2mif.sh │ ├── darksocv.mk │ ├── dut.v │ ├── max1000.cdf │ ├── max1000.qpf │ ├── max1000.qsf │ ├── mem2bin.sh │ ├── pll.ppf │ ├── pll.qip │ ├── pll.v │ ├── pll_bb.v │ ├── pmodbutled.v │ └── top.v ├── openroad │ ├── BUILD.bazel │ ├── README.md │ ├── constraints.sdc │ ├── constraints_darkram.sdc │ ├── darkram.v │ ├── reg2reg-histogram.png │ └── routing-congestion.png ├── papilio_duo_logicstart │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── piswords_ch34x_lx16 │ ├── README.md │ ├── darksocv.ucf │ └── darksocv.xise ├── piswords_rs485_lx9 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── qmtech_artix7_a35 │ ├── README.md │ ├── darksocv.xdc │ └── darksocv.xpr ├── qmtech_cyclone10_cl016 │ ├── darksocv.csv │ ├── darksocv.qpf │ ├── darksocv.qsf │ └── darksocv.sdc ├── qmtech_kintex7_k325 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── qmtech_sdram_lx16 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── qmtech_spartan7_s15 │ ├── darksocv.xdc │ └── darksocv.xpr ├── scarab_minispartan6-plus_lx9 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── ulx3s │ ├── README.md │ ├── build.sh │ ├── darksocv.lpf │ ├── pll_ref_25MHz.v │ └── upload.sh └── xilinx_ac701_a200 │ ├── README.md │ ├── darksocv.imp │ ├── darksocv.mk │ ├── darksocv.prj │ ├── darksocv.ucf │ ├── darksocv.ut │ ├── darksocv.xise │ └── darksocv.xst ├── darkriscv.core ├── doc ├── boot.png ├── darkriscv.png └── darksocv.png ├── rtl ├── README.md ├── config.vh ├── darkbridge.v ├── darkcache.v ├── darkio.v ├── darkpll.v ├── darkram.v ├── darkriscv.v ├── darksocv.v ├── darkspi.v ├── darkuart.v └── lib │ ├── sdram │ └── mt48lc16m16a2_ctrl.v │ └── spi │ ├── LICENSE │ ├── darksocv.gtkw │ ├── lis3dh_stub.v │ ├── spi_master.v │ └── spi_master_bb.v ├── sim ├── Makefile ├── README.md ├── Vdarksocv_gui.cpp ├── cosim.mk ├── darksimv.v └── trace.py ├── src ├── .gitattributes ├── .gitignore ├── Makefile ├── README.md ├── badapple │ ├── Makefile │ ├── badapple.h │ ├── badapple.txt │ └── main.c ├── boot.S ├── config.mk ├── coremark │ ├── Makefile │ ├── README.md │ ├── core_portme.c │ ├── core_portme.h │ ├── coremark.lds │ ├── ee_printf.c │ └── src │ │ ├── core_list_join.c │ │ ├── core_main.c │ │ ├── core_matrix.c │ │ ├── core_state.c │ │ ├── core_util.c │ │ └── coremark.h ├── darklibc │ ├── Makefile │ ├── include │ │ ├── io.h │ │ ├── math.h │ │ ├── stddef.h │ │ ├── stdint.h │ │ ├── stdio.h │ │ ├── string.h │ │ ├── time.h │ │ └── unistd.h │ ├── io.c │ ├── misc.c │ ├── stdio.c │ ├── string.c │ ├── unistd.c │ └── util.S ├── darkshell │ ├── Makefile │ ├── README.md │ └── main.c ├── darksocv.lds ├── darksocv.mem ├── dhrystone │ ├── LICENSE │ ├── Makefile │ ├── README.md │ ├── dhry.h │ ├── dhry_1.c │ └── dhry_2.c ├── donut │ ├── Makefile │ ├── README.md │ └── main.c ├── mandelbrot │ ├── Makefile │ └── main.c ├── primes │ ├── Makefile │ ├── README.md │ └── main.c └── spidemo │ ├── Makefile │ ├── README.md │ ├── SPIBB.md │ ├── main.c │ └── ser.py └── tmp └── .keep /.bazelversion: -------------------------------------------------------------------------------- 1 | 7.4.0 2 | -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | *.mk linguist-detectable=false 2 | *akefile linguist-detectable=false 3 | *.md linguist-detectable=false 4 | *.xise linguist-detectable=false 5 | *.py linguist-detectable=false 6 | -------------------------------------------------------------------------------- /.github/workflows/Linux.yml: -------------------------------------------------------------------------------- 1 | name: Linux 2 | 3 | on: 4 | - push 5 | - pull_request 6 | - workflow_dispatch 7 | 8 | jobs: 9 | build: 10 | runs-on: ubuntu-latest 11 | container: 12 | image: archlinux:latest 13 | steps: 14 | - uses: actions/checkout@v3 15 | - name: Install prerequisites 16 | run: | 17 | pacman -Sy --noconfirm base-devel git wget iverilog 18 | pacman -Sy --noconfirm base-devel git wget xxd 19 | useradd -m builduser 20 | echo 'builduser ALL=(ALL) NOPASSWD: ALL' >> /etc/sudoers 21 | chown -R builduser /home/builduser 22 | 23 | - name: Clone AUR package 24 | run: | 25 | sudo -u builduser git clone https://aur.archlinux.org/riscv32-gnu-toolchain-elf-bin.git /home/builduser/riscv32-toolchain 26 | 27 | - name: Build and install toolchain 28 | run: | 29 | cd /home/builduser/riscv32-toolchain 30 | sudo -u builduser makepkg -si --noconfirm 31 | riscv32-unknown-elf-gcc -v 32 | 33 | - name: Test (darksocv.mem already built) 34 | run: | 35 | make 36 | 37 | - name: Rebuild and test 38 | run: | 39 | export CCPATH=$(dirname `command -v riscv32-unknown-elf-gcc`) 40 | make clean all CROSS=riscv32-unknown-elf CCPATH=$CCPATH ARCH=rv32e_zicsr ABI=ilp32e ENDIAN=big 41 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | tmp/* 2 | sim/darksocv 3 | sim/darksocv.vcd 4 | *~ 5 | */*~ 6 | .DS_Store 7 | */.DS_Store 8 | boards/*/darksocv.cache 9 | boards/*/darksocv.hw 10 | boards/*/darksocv.ip_user_files 11 | boards/*/darksocv.sim 12 | fusesoc.conf 13 | build 14 | iseconfig 15 | *.a 16 | *.bin 17 | bazel-bin 18 | bazel-darkriscv 19 | bazel-out 20 | bazel-testlogs 21 | -------------------------------------------------------------------------------- /BUILD.bazel: -------------------------------------------------------------------------------- 1 | """Top level Bazel module, allows access to files by other modules.""" 2 | 3 | exports_files( 4 | glob([ 5 | "rtl/**/*.v", 6 | "rtl/**/*.vh", 7 | ]), 8 | visibility = [":__subpackages__"], 9 | ) 10 | 11 | filegroup( 12 | name = "verilog", 13 | srcs = glob(["rtl/**/*.v"]), 14 | visibility = [":__subpackages__"], 15 | ) 16 | 17 | filegroup( 18 | name = "verilog_include", 19 | srcs = glob(["rtl/**/*.vh"]), 20 | visibility = [":__subpackages__"], 21 | ) 22 | 23 | filegroup( 24 | name = "verilog_data", 25 | srcs = glob(["src/**/*.mem"]), 26 | visibility = [":__subpackages__"], 27 | ) 28 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2018, Marcelo Samsoniuk 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | * Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | * Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /MODULE.bazel: -------------------------------------------------------------------------------- 1 | """Bazel depedencies""" 2 | 3 | module( 4 | name = "darkriscv", 5 | version = "0.0.1", 6 | compatibility_level = 1, 7 | ) 8 | 9 | bazel_dep(name = "bazel-orfs") 10 | git_override( 11 | module_name = "bazel-orfs", 12 | commit = "b16da67e50032682dc6f01252217bfb71cf89260", 13 | remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git", 14 | ) 15 | 16 | orfs = use_extension("@bazel-orfs//:extension.bzl", "orfs_repositories") 17 | orfs.default( 18 | # To update, find latest at https://hub.docker.com/r/openroad/orfs/tags 19 | image = "docker.io/openroad/orfs:v3.0-2591-g9bca87d7", 20 | sha256 = "673181c3b49235cf5b43e386e4cf478d676b797c8b7736a3ed79fc90f4c8acb7", 21 | ) 22 | use_repo(orfs, "com_github_nixos_patchelf_download") 23 | use_repo(orfs, "docker_orfs") 24 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Marcelo Samsoniuk 3 | # All rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # * Redistributions of source code must retain the above copyright notice, this 9 | # list of conditions and the following disclaimer. 10 | # 11 | # * Redistributions in binary form must reproduce the above copyright notice, 12 | # this list of conditions and the following disclaimer in the documentation 13 | # and/or other materials provided with the distribution. 14 | # 15 | # * Neither the name of the copyright holder nor the names of its 16 | # contributors may be used to endorse or promote products derived from 17 | # this software without specific prior written permission. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # ===8<--------------------------------------------------------- cut here! 31 | # 32 | # This the root makefile and the function of this file is call other 33 | # makefiles. Of course, you need first set the GCC compiler path/name, the 34 | # simulator path/name and the board model in the respective directories: 35 | # 36 | # - src/Makefile 37 | # - sim/Makefile 38 | # - board/Makefile 39 | # 40 | # After configure each Makefile, you can just type 'make' 41 | 42 | default: src/darksocv.mem 43 | make -C sim 44 | 45 | all: 46 | make -C src all 47 | make -C sim all 48 | make -C boards all 49 | 50 | src/darksocv.mem: 51 | make -C src all 52 | 53 | install: 54 | make -C boards install 55 | 56 | clean: 57 | make -C src clean 58 | make -C sim clean 59 | make -C boards clean 60 | -------------------------------------------------------------------------------- /boards/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2018, Marcelo Samsoniuk 3 | # All rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # * Redistributions of source code must retain the above copyright notice, this 9 | # list of conditions and the following disclaimer. 10 | # 11 | # * Redistributions in binary form must reproduce the above copyright notice, 12 | # this list of conditions and the following disclaimer in the documentation 13 | # and/or other materials provided with the distribution. 14 | # 15 | # * Neither the name of the copyright holder nor the names of its 16 | # contributors may be used to endorse or promote products derived from 17 | # this software without specific prior written permission. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | 31 | #BOARD = avnet_microboard_lx9 32 | #BOARD = xilinx_ac701_a200 33 | #BOARD = qmtech_sdram_lx16 34 | #BOARD = lattice_brevia2_xp2 35 | #BOARD = papilio_duo_logicstart 36 | 37 | default: all 38 | 39 | ifdef BOARD 40 | 41 | include $(BOARD)/darksocv.mk 42 | 43 | else 44 | 45 | all: 46 | @echo no board selected to build, done. 47 | 48 | clean: 49 | @echo no board selected to clean, done. 50 | 51 | endif 52 | -------------------------------------------------------------------------------- /boards/README.md: -------------------------------------------------------------------------------- 1 | ## Add your board here! o/ 2 | 3 | Use the AVNET Microboard LX9 as template, since is the best tested board at this 4 | moment, as long I can plug it in the computer and test it in less than five 5 | minutes: 6 | 7 | cp -rp avnet_micrboard_lx9 vendor_board_fpga 8 | 9 | In the case of Vivado, the easy way is use the QMTech Spartan-7 board as 10 | template. In the case of Vivado, there is no automation as found in the 11 | other FPGAs. 12 | 13 | Current supported board/FPGAs: 14 | 15 | avnet_microboard_lx9 16 | qmtech_sdram_lx16 17 | qmtech spartan7 s15 18 | xilinx_ac701_a200 19 | lattice brevia2 lxp2 20 | piswords rs485 lx9 21 | 22 | I am working in a way to make the directory structure better, but it is not 23 | so easy make everything work at the same time! :) 24 | 25 | Proposed structure: 26 | 27 | boards/vendor_boardname_fpga/ top level directory 28 | boards/vendor_boardname_fpga/darksocv.mk top level makefile 29 | boards/vendor_boardname_fpga/darksocv.* other files (board/fpga specific) 30 | 31 | In the current directory is possible set: 32 | 33 | make BOARD=avnet_microboard_lx9 all # build fpga for $BOARD 34 | make install # program fpga 35 | 36 | Of course, the FPGA programming via JTAG depends of some configurations 37 | which are different in different environments. Please check the README file 38 | regarding the board! 39 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_k420/README.md: -------------------------------------------------------------------------------- 1 | ## AliExpress HPC 40GbE K420 (Kintex-7 HPC V2) 2 | 3 | The correct name for this board is "Kintex-7 HPC V2", but is more widely 4 | know as "Aliexpress HPC 40GbE K420" board, since there are lots of HPC 5 | boards in the Aliexpress site. In fact, this board is not manufactured 6 | anymore, instead there is an updated Kintex-7 HPC V3 available. 7 | 8 | The Kintex-7 HPC V2 board includes: 9 | 10 | - a XC7K420 FPGA w/ 910 pins 11 | - lots pf high-speed clocks: 100MHz, 125MHz, 133MHz and 156MHz 12 | - on-board USB/serial (CH340) 13 | - on-board SPI FLASH (N25Q256) 14 | - on-board 2xSFP+ (for up to 2x10Gbps) 15 | - on-board 2xQSFP (for up to 2x40Gbps) 16 | - on-board dual-channel 1033MHz DDR3 17 | - 16 LEDs (they appears to be reversed!) 18 | - 2 swiches 19 | - 4 SMA connectors 20 | - SATA interface 21 | - PCIe 8x 22 | - 3x different JTAG connectors (you need an external JTAG adapter!) 23 | - support for darkriscv running at 240MHz (single-thread) 24 | - multithread support up to 128 threads (120MHz) 25 | 26 | Unfortunately, there is no information yet about the HPC V3, but I guess the 27 | new board is more or less the same as the old board. 28 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_k420/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_k420/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_k420/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | #NET "CLK" TNM_NET = CLK; 30 | 31 | # without cache controller 32 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 33 | 34 | # with cache controller 35 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 36 | 37 | # AliExpress HPC 40GbE K420 board 38 | 39 | NET XCLK LOC = U24 | IOSTANDARD = LVCMOS25 | PERIOD = 100MHz HIGH 50%; 40 | #NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; 41 | #NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; 42 | 43 | NET XRES LOC = A16 | IOSTANDARD = LVCMOS25 | PULLDOWN; 44 | 45 | NET UART_RXD LOC = D17 | IOSTANDARD = LVCMOS25 | PULLUP; 46 | NET UART_TXD LOC = D16 | IOSTANDARD = LVCMOS25; 47 | 48 | NET LED[3] LOC = A27 | IOSTANDARD = LVCMOS15; 49 | NET LED[2] LOC = E24 | IOSTANDARD = LVCMOS15; 50 | NET LED[1] LOC = G24 | IOSTANDARD = LVCMOS15; 51 | NET LED[0] LOC = H21 | IOSTANDARD = LVCMOS15; 52 | 53 | NET DEBUG[3] LOC = G27 | IOSTANDARD = LVCMOS15; # J4-1 54 | NET DEBUG[2] LOC = H26 | IOSTANDARD = LVCMOS15; # J4-2 55 | NET DEBUG[1] LOC = H25 | IOSTANDARD = LVCMOS15; # J4-3 56 | NET DEBUG[0] LOC = H24 | IOSTANDARD = LVCMOS15; # J4-4 57 | 58 | 59 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_k420/darksocv.ut: -------------------------------------------------------------------------------- 1 | -g UnconstrainedPins:Allow 2 | -w 3 | -g DebugBitstream:No 4 | -g Binary:no 5 | -g CRC:Enable 6 | -g ConfigRate:3 7 | -g CclkPin:PullUp 8 | -g M0Pin:PullUp 9 | -g M1Pin:PullUp 10 | -g M2Pin:PullUp 11 | -g ProgPin:PullUp 12 | -g InitPin:Pullup 13 | -g TckPin:PullUp 14 | -g TdiPin:PullUp 15 | -g TdoPin:PullUp 16 | -g TmsPin:PullUp 17 | -g Disable_JTAG:No 18 | -g UnusedPin:PullDown 19 | -g UserID:0xFFFFFFFF 20 | -g ExtMasterCclk_en:Disable 21 | -g ConfigFallback:Disable 22 | -g BPI_page_size:1 23 | -g BPI_sync_mode:Disable 24 | -g SPI_32bit_addr:No 25 | -g SPI_buswidth:1 26 | -g SPI_Fall_Edge:No 27 | -g OverTempPowerDown:Disable 28 | -g USR_ACCESS:None 29 | -g JTAG_XADC:Enable 30 | -g DCIUpdateMode:AsRequired 31 | -g StartUpClk:CClk 32 | -g DONE_cycle:4 33 | -g GTS_cycle:5 34 | -g GWE_cycle:6 35 | -g Match_cycle:Auto 36 | -g Security:None 37 | -g ICAP_select:Auto 38 | -g DonePipe:Yes 39 | -g Encrypt:No 40 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_k420/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/aliexpress_hpc40gbe_k420/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc7k420t-2-ffg901 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 2 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing Yes 46 | -move_first_stage YES 47 | -move_last_stage YES 48 | -optimize_primitives NO 49 | -use_clock_enable Auto 50 | -use_sync_set Auto 51 | -use_sync_reset Auto 52 | -iob Auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -define ALIEXPRESS_HPC40GBE_K420=1 -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_xcku040/README.md: -------------------------------------------------------------------------------- 1 | ## AliExpress HPC 40GbE XCKKU040 (Kintex Ultrascape HPC) 2 | 3 | This board is widely know as "Aliexpress HPC 40GbE XCKU040" board, from the 4 | same source as the K420 board. Although the FPGA is more powerful, the board 5 | is cheaper when compaared to the more complete board and, in fact, is 6 | probable the cheaper ultrascale board. 7 | 8 | The Kintex Ultrascale HPC board includes: 9 | 10 | - a XCKU040 FPGA w/ 1156 pins 11 | - not sure about the speed grade, guessing it is -2! 12 | - high-speed clocks: 100MHz 156MHz 13 | - on-board USB/serial (CH340) 14 | - on-board SPI FLASH (N25QL256) 15 | - on-board 2xQSFP (for up to 2x40Gbps) 16 | - 8 LEDs 17 | - 1 swiches 18 | - PCIe 8x 19 | - TAG connector (you need an external JTAG adapter!) 20 | - support for darkriscv running at 250MHz (single-thread) 21 | - tested up to 300MHz w/ overclock 22 | - 2x I2C setup memories (AT24C04), probably one for each QSFP?! 23 | 24 | Unfortunately, there is no scheatic for this board, just an Excel with the 25 | pins, with some labels in chinese and some small errors, but not bad at all. 26 | 27 | This board appears to work well when overclocked and, in fact, it exceeds 28 | the darkriscv frequency register, so the frequencies above 250MHz will 29 | appears weird! 30 | 31 | For example, when working at 400MHz:: 32 | 33 | boot0: text@0 data@6268 stack@8192 (1924 bytes free) 34 | board: aliexpress hpc/40gbe ku040 (id=10) 35 | build: Mon, 01 Feb 2021 04:06:48 -0300 for rv32e 36 | core0/thread0: darkriscv@144.00MHz rv32e <- frequency reg overflow 37 | uart0: 115200 bps (div=2314) 38 | timr0: frequency=40075Hz (io.timer=399) <-- 400M/(399+1)=1us 39 | 40 | Finally, be careful that the Ultrascale needs TWO boot images, so you need 41 | generate the primary and secondary MCS file (just select in Vivado the 42 | option to generate the FLASH image and the wizard will generate them). 43 | -------------------------------------------------------------------------------- /boards/aliexpress_hpc40gbe_xcku040/darksocv.xdc: -------------------------------------------------------------------------------- 1 | # HPC 2x40GbE XCKU040 board 2 | 3 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 4 | set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design] 5 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] 6 | set_property CONFIG_VOLTAGE 2.5 [current_design] 7 | set_property CFGBVS VCCO [current_design] 8 | set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] 9 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] 10 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 11 | set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] 12 | 13 | set_property -dict { PACKAGE_PIN D23 IOSTANDARD LVCMOS18 } [get_ports { XCLK }]; 14 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { XCLK }]; 15 | 16 | set_property -dict { PACKAGE_PIN AP10 IOSTANDARD LVCMOS33 } [get_ports { XRES }]; 17 | 18 | set_property -dict { PACKAGE_PIN G27 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD }]; 19 | set_property -dict { PACKAGE_PIN H27 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }]; 20 | 21 | set_property -dict { PACKAGE_PIN B25 IOSTANDARD LVCMOS18 } [get_ports { LED[3] }]; 22 | set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS18 } [get_ports { LED[2] }]; 23 | set_property -dict { PACKAGE_PIN B26 IOSTANDARD LVCMOS18 } [get_ports { LED[1] }]; 24 | set_property -dict { PACKAGE_PIN A27 IOSTANDARD LVCMOS18 } [get_ports { LED[0] }]; 25 | 26 | set_property -dict { PACKAGE_PIN B27 IOSTANDARD LVCMOS18 } [get_ports { DEBUG[3] }]; 27 | set_property -dict { PACKAGE_PIN A28 IOSTANDARD LVCMOS18 } [get_ports { DEBUG[2] }]; 28 | set_property -dict { PACKAGE_PIN A29 IOSTANDARD LVCMOS18 } [get_ports { DEBUG[1] }]; 29 | set_property -dict { PACKAGE_PIN B29 IOSTANDARD LVCMOS18 } [get_ports { DEBUG[0] }]; 30 | -------------------------------------------------------------------------------- /boards/avnet_microboard_lx9/README.md: -------------------------------------------------------------------------------- 1 | ## AVNET Microboard LX9 2 | 3 | The old AVNET Microboard LX9 is my preferred development board because is 4 | small, easy to connect to the development environment and very complete, 5 | with integrated JTAG, USB/serial and Ethernet! 6 | 7 | The board includes: 8 | 9 | - a XC6SLX9 FPGA w/ 324 pins (XC6SLX9-2CSG324C) 10 | - lots of clocks: 40MHz, 66MHz and 100MHz 11 | - on-board USB/serial (CP2102) 12 | - on-board JTAG (Atmel AT90USB162) 13 | - on-board SPI FLASH (N25Q128) 14 | - on-board 10/100Mbps ethernet PHY (DP83484J) 15 | - on-board DDR (MT46H32M16LFBF5) 16 | - four LEDs (4xLEDs) 17 | - switchs (4) and uses-button (1) 18 | - some few GPIO pins (2x PMOD) 19 | -------------------------------------------------------------------------------- /boards/avnet_microboard_lx9/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/avnet_microboard_lx9/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/avnet_microboard_lx9/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | #NET "CLK" TNM_NET = CLK; 30 | 31 | # without cache controller 32 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 33 | 34 | # with cache controller 35 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 36 | 37 | # AVNET board LX9 microboard 38 | 39 | NET XCLK LOC = C10 | PERIOD = 100MHz HIGH 50%; 40 | #NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; 41 | #NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; 42 | 43 | NET XRES LOC = V4 | PULLDOWN; 44 | 45 | NET UART_RXD LOC = R7; 46 | NET UART_TXD LOC = T7; 47 | 48 | NET LED[3] LOC = P4; 49 | NET LED[2] LOC = L6; 50 | NET LED[1] LOC = F5; 51 | NET LED[0] LOC = C2; 52 | 53 | NET DEBUG[3] LOC = H12; # J4-1 54 | NET DEBUG[2] LOC = G13; # J4-2 55 | NET DEBUG[1] LOC = E16; # J4-3 56 | NET DEBUG[0] LOC = E18; # J4-4 57 | -------------------------------------------------------------------------------- /boards/avnet_microboard_lx9/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/avnet_microboard_lx9/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/avnet_microboard_lx9/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc6slx9-2-csg324 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -define AVNET_MICROBOARD_LX9=1 -------------------------------------------------------------------------------- /boards/colorlighti5/README.md: -------------------------------------------------------------------------------- 1 | Just use yosys/nextpnr-ecp5 2 | --------------------------- 3 | 4 | download toolchain from https://github.com/YosysHQ/oss-cad-suite-build/releases 5 | You can change the frequency with the pll_ref_25MHz.v (accepted fmax hardwired). 6 | Use config.vh to adjust fmax via BOARD_CK. 7 | -------------------------------------------------------------------------------- /boards/colorlighti5/build.sh: -------------------------------------------------------------------------------- 1 | rm -f darksocv.cfg darksocv.json 2 | yosys -D __YOSYS__ -D LATTICE_ECP5_COLORLIGHTI5 -p "synth_ecp5 -json darksocv.json -top darksocv" ../../rtl/darksocv.v ../../rtl/darkriscv.v ../../rtl/darkuart.v pll_ref_25MHz.v 3 | nextpnr-ecp5 --timing-allow-fail --json darksocv.json --textcfg darksocv.cfg --25k --package CABGA381 --speed 6 --lpf darksocv.lpf 4 | ecppack --compress --input darksocv.cfg --bit darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/colorlighti5/darksocv.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS; 2 | BLOCK ASYNCPATHS; 3 | #i5-v6.0 4 | LOCATE COMP "XCLK" SITE "P3"; 5 | IOBUF PORT "XCLK" PULLMODE=NONE IO_TYPE=LVCMOS33; 6 | FREQUENCY PORT "XCLK" 25 MHZ; 7 | ## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) 8 | # on PCB v1.7 shutdown is not connected to FPGA 9 | LOCATE COMP "XRES" SITE "G16"; # FPGA receives 10 | IOBUF PORT "XRES" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 11 | LOCATE COMP "UART_TXD" SITE "J17"; # FPGA transmits to ftdi 12 | IOBUF PORT "UART_TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 13 | LOCATE COMP "UART_RXD" SITE "H18"; # FPGA received to ftdi 14 | IOBUF PORT "UART_RXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 15 | # 16 | ## upper 17 | LOCATE COMP "LED[0]" SITE "D1"; 18 | LOCATE COMP "LED[1]" SITE "C1"; 19 | LOCATE COMP "LED[2]" SITE "C2"; 20 | LOCATE COMP "LED[3]" SITE "E3"; 21 | 22 | ## bottom 23 | LOCATE COMP "DEBUG[0]" SITE "E2"; 24 | LOCATE COMP "DEBUG[1]" SITE "D2"; 25 | LOCATE COMP "DEBUG[2]" SITE "B1"; 26 | LOCATE COMP "DEBUG[3]" SITE "A3"; 27 | 28 | # if you use spi bitbang, just remove PULLMODE=UP from property 29 | IOBUF PORT "LED[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 30 | IOBUF PORT "LED[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 31 | IOBUF PORT "LED[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 32 | IOBUF PORT "LED[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 33 | IOBUF PORT "DEBUG[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 34 | IOBUF PORT "DEBUG[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 35 | IOBUF PORT "DEBUG[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 36 | IOBUF PORT "DEBUG[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 37 | 38 | 39 | ## PROGRAMN (reload bitstream from FLASH, exit from bootloader) 40 | # PCB v2.0.5 and higher 41 | LOCATE COMP "user_programn" SITE "M4"; 42 | IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 43 | 44 | -------------------------------------------------------------------------------- /boards/colorlighti5/upload.sh: -------------------------------------------------------------------------------- 1 | # sram config 2 | openFPGALoader --board=colorlight-i5 darksocv.bit 3 | # flash config 4 | #openFPGALoader -f --board=colorlight-i5 darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/colorlighti9/README.md: -------------------------------------------------------------------------------- 1 | Just use yosys/nextpnr-ecp5 2 | --------------------------- 3 | 4 | download toolchain from https://github.com/YosysHQ/oss-cad-suite-build/releases 5 | You can change the frequency with the pll_ref_25MHz.v (accepted fmax hardwired). 6 | Use config.vh to adjust fmax via BOARD_CK. 7 | -------------------------------------------------------------------------------- /boards/colorlighti9/build.sh: -------------------------------------------------------------------------------- 1 | rm -f darksocv.cfg darksocv.json 2 | yosys -D __YOSYS__ -D LATTICE_ECP5_COLORLIGHTI9 -p "synth_ecp5 -json darksocv.json -top darksocv" ../../rtl/darksocv.v ../..rtl/darkpll.v ../../rtl/darkriscv.v ../../rtl/darkuart.v pll_ref_25MHz.v 3 | nextpnr-ecp5 --timing-allow-fail --json darksocv.json --textcfg darksocv.cfg --45k --package CABGA381 --speed 6 --lpf darksocv.lpf 4 | ecppack --compress --input darksocv.cfg --bit darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/colorlighti9/darksocv.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS; 2 | BLOCK ASYNCPATHS; 3 | #i5-v6.0 4 | LOCATE COMP "XCLK" SITE "P3"; 5 | IOBUF PORT "XCLK" PULLMODE=NONE IO_TYPE=LVCMOS33; 6 | FREQUENCY PORT "XCLK" 25 MHZ; 7 | ## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) 8 | # on PCB v1.7 shutdown is not connected to FPGA 9 | LOCATE COMP "XRES" SITE "G16"; # FPGA receives 10 | IOBUF PORT "XRES" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 11 | LOCATE COMP "UART_TXD" SITE "J17"; # FPGA transmits to ftdi 12 | IOBUF PORT "UART_TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 13 | LOCATE COMP "UART_RXD" SITE "H18"; # FPGA received to ftdi 14 | IOBUF PORT "UART_RXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 15 | # 16 | ## upper 17 | LOCATE COMP "LED[0]" SITE "D1"; 18 | LOCATE COMP "LED[1]" SITE "C1"; 19 | LOCATE COMP "LED[2]" SITE "C2"; 20 | LOCATE COMP "LED[3]" SITE "E3"; 21 | 22 | ## bottom 23 | LOCATE COMP "DEBUG[0]" SITE "E2"; 24 | LOCATE COMP "DEBUG[1]" SITE "D2"; 25 | LOCATE COMP "DEBUG[2]" SITE "B1"; 26 | LOCATE COMP "DEBUG[3]" SITE "A3"; 27 | 28 | # if you use spi bitbang, just remove PULLMODE=UP from property 29 | IOBUF PORT "LED[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 30 | IOBUF PORT "LED[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 31 | IOBUF PORT "LED[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 32 | IOBUF PORT "LED[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 33 | IOBUF PORT "DEBUG[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 34 | IOBUF PORT "DEBUG[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 35 | IOBUF PORT "DEBUG[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 36 | IOBUF PORT "DEBUG[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 37 | 38 | 39 | ## PROGRAMN (reload bitstream from FLASH, exit from bootloader) 40 | # PCB v2.0.5 and higher 41 | LOCATE COMP "user_programn" SITE "M4"; 42 | IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 43 | 44 | -------------------------------------------------------------------------------- /boards/colorlighti9/upload.sh: -------------------------------------------------------------------------------- 1 | # sram config 2 | openFPGALoader --board=colorlight-i9 darksocv.bit 3 | # flash config 4 | #openFPGALoader -f --board=colorlight-i9 darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/README.md: -------------------------------------------------------------------------------- 1 | # DE10-Nano board (Terasic) / MiSTer 2 | 3 | ## General information 4 | The DE10-Nano board is a robust development board based on Intel/Altera Cyclone V family of FPGAs.\ 5 | It has an Intel Cyclone® V SE 5CSEBA6U23I7 device (110K LEs) and also includes the following peripherals: 6 | * 64/128Mbit Flash Memory (EPCS64/128) 7 | * 800MHz Dual-core ARM Cortex-A9 processor (HPS) 8 | * 1GB DDR3 SDRAM (32-bit data bus, HPS) 9 | * 1 Gigabit Ethernet PHY with RJ45 connector (HPS) 10 | * USB-Blaster II onboard for programming; JTAG Mode 11 | * HDMI TX, compatible with DVI 1.0 and HDCP v1.4 12 | * 8 LEDs + 2 push-buttons 13 | * Three 50 MHz clock sources 14 | * 3-axis accelerometer 15 | * Many headers: 40pins, Arduino R3, JTAG.. 16 | 17 | NOTE: This Darkriscv port targets/integrates the MiSTer framework around the DE10-Nano. 18 | Some of their files are licensed under GPL v2+ (See LICENSE). 19 | 20 | For more detailed information, see here:\ 21 | https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046 22 | 23 | https://github.com/MiSTer-devel/Wiki_MiSTer/wiki 24 | 25 | The DarkRISCV/darksoc builds out-of-the box using Quartus command-line, 26 | taking about ~10% of the on-chip logic for the SoC demo (including Mister resources). 27 | - It uses an altera pll QIP to transform 50MHz into several freqs for MiSTer (TODO: maybe integrate it into darkpll), 28 | - and a simplified darkram based on altsyncram to properly infer BRAM (TODO: maybe integrate it into darkram). 29 | 30 | ## Instructions 31 | Install Quartus with Cyclone V support, `srecord`, `awk`, `xxd`.\ 32 | Read/apply the Terasic docs to enable the cyclone V support (eg: udev rules, ftdi driver etc..)\ 33 | Ensure that `QUARTUS` macro defined in `boards/de10nano_cyclonev_mister/darksocv.mk` points to your Quartus install, then, from darkriscv root directory:\ 34 | Build the bitstream: 35 | ``` 36 | make all BOARD=de10nano_cyclonev_mister 37 | ``` 38 | To program the device, you must transfer the resulting `boards/de10nano_cyclonev_mister/output_files/darkriscv_de10nano.rbf` to your device 39 | and program it using the MiSTer menu. 40 | One way to do this is to copy the RBF to your MiSTer via Ethernet, or using an USB stick. 41 | 42 | Finally to connect to the serial port, first ensure that the VT52 core SerialPort=ConsolePort; 43 | then you can use `screen` on the MiSTer via ssh: 44 | ``` 45 | TERM=linux ssh -t root@mister screen /dev/ttyS1 115200 46 | ``` 47 | (just replace `mister` by ``) 48 | and you should see DarkRISCV booting up: 49 | ``` 50 | ... 51 | board: de10nano cyclonev mister (id=20) 52 | ... 53 | 36253> led aa55 54 | led = aa55 55 | 1> 56 | ``` 57 | You should see 0x55 on the 8 leds. 58 | 59 | To clean the board-related objects: 60 | ``` 61 | make clean BOARD=de10nano_cyclonev_mister 62 | ``` 63 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/_darkram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "../../rtl/config.vh" 3 | 4 | module darkram #(parameter INIT_FILE = "../memory_init.mif") 5 | ( 6 | input CLK, // Clock 7 | input RES, // Reset 8 | input HLT, // Halt 9 | 10 | input IDREQ, // Instruction fetch request 11 | input [31:0] IADDR, // Instruction address 12 | output [31:0] IDATA, // Instruction data output 13 | output IDACK, // Instruction acknowledge 14 | 15 | input XDREQ, // Data request 16 | input XRD, // Read enable 17 | input XWR, // Write enable 18 | input [3:0] XBE, // Byte enable 19 | input [31:0] XADDR, // Data address 20 | input [31:0] XATAI, // Data input 21 | output [31:0] XATAO, // Data output 22 | output XDACK, // Data acknowledge 23 | 24 | output [3:0] DEBUG // Debug signals 25 | ); 26 | 27 | // Internal signals 28 | wire [31:0] ram_q_a, ram_q_b; 29 | wire write_enable; 30 | 31 | 32 | // Instantiate altsyncram 33 | altsyncram #( 34 | .operation_mode("BIDIR_DUAL_PORT"), 35 | .width_a(32), 36 | .widthad_a(13), // Address width for 4KB RAM 37 | .numwords_a(2048), 38 | .width_b(32), 39 | .widthad_b(13), 40 | .numwords_b(2048), 41 | .lpm_type("altsyncram"), 42 | .ram_block_type("AUTO"), 43 | .init_file(INIT_FILE), 44 | .outdata_reg_a("UNREGISTERED"), 45 | .outdata_reg_b("UNREGISTERED"), 46 | .indata_reg_b("CLOCK0"), 47 | .address_reg_b("CLOCK0"), 48 | .wrcontrol_wraddress_reg_b("CLOCK0"), 49 | .byte_size(8), 50 | .width_byteena_a(4), 51 | .width_byteena_b(4), 52 | .byteena_reg_b("CLOCK0") 53 | ) ram_inst ( 54 | .clock0(CLK), 55 | .address_a(IADDR[12:2]), 56 | .q_a(ram_q_a), 57 | .address_b(XADDR[12:2]), 58 | .wren_b(write_enable), 59 | .byteena_b(XBE), 60 | .data_b(XATAI), 61 | .q_b(ram_q_b) 62 | ); 63 | assign write_enable = XWR & XDREQ; 64 | 65 | // Assign instruction fetch outputs 66 | assign IDATA = ram_q_a; 67 | assign IDACK = IDREQ; // Immediate ACK for simplicity 68 | 69 | // Assign data read/write outputs 70 | assign XATAO = ram_q_b; 71 | assign XDACK = DTACK==1 ||(XDREQ&&XWR); 72 | reg [3:0] DTACK = 0; 73 | always@(posedge CLK) // stage #1.0 74 | begin 75 | DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && XRD ? 1 : 0; 76 | end 77 | 78 | // Debug outputs (for observability) 79 | assign DEBUG = { XDREQ,XRD,XWR,XDACK }; 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/bin2mif.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | WORD=4 4 | SRC=memory_init.bin;DST=memory_init.mif 5 | srec_cat $SRC -binary -byte-swap 4 -o $DST -mif $WORD 6 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/darkriscv_de10nano.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition 21 | # Date created = 18:23:56 January 08, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.1" 26 | DATE = "18:23:56 January 08, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "darkriscv_de10nano" 31 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/darkriscv_de10nano.sdc: -------------------------------------------------------------------------------- 1 | derive_pll_clocks 2 | derive_clock_uncertainty 3 | 4 | # core specific constraints 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/dut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "../../rtl/config.vh" 3 | 4 | module dut ( 5 | input rx, 6 | output tx, 7 | output [15:0] leds, 8 | input reset, 9 | input clk 10 | ); 11 | 12 | darksocv soc0 ( 13 | .UART_RXD(rx), // UART receive line 14 | .UART_TXD(tx), // UART transmit line 15 | 16 | .LED(leds), // on-board leds 17 | 18 | .XCLK(clk), // external clock 19 | .XRES(reset) // external reset 20 | ); 21 | endmodule 22 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/files.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE sys/sys.qip 2 | set_global_assignment -name VERILOG_FILE rtl/vga.v 3 | set_global_assignment -name VERILOG_FILE ../../rtl/darksocv.v 4 | set_global_assignment -name VERILOG_FILE ../../rtl/darkio.v 5 | set_global_assignment -name VERILOG_FILE ../../rtl/darkpll.v 6 | set_global_assignment -name VERILOG_FILE ../../rtl/darkuart.v 7 | set_global_assignment -name VERILOG_FILE ../../rtl/darkriscv.v 8 | set_global_assignment -name VERILOG_FILE ../../rtl/darkbridge.v 9 | set_global_assignment -name VERILOG_FILE dut.v 10 | set_global_assignment -name SYSTEMVERILOG_FILE darkriscv_de10nano.sv 11 | set_global_assignment -name VERILOG_FILE _darkram.v 12 | set_global_assignment -name SDC_FILE darkriscv_de10nano.sdc 13 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/jtag.cdf: -------------------------------------------------------------------------------- 1 | JedecChain; 2 | FileRevision(JESD32A); 3 | DefaultMfr(6E); 4 | 5 | P ActionCode(Ign) 6 | Device PartName(SOCVHPS) MfrSpec(OpMask(0)); 7 | P ActionCode(Cfg) 8 | Device PartName(5CSEBA6U23I7) Path("output_files/") File("darkriscv_de10nano.sof") MfrSpec(OpMask(1)); 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/mem2bin.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SRC=memory_init.mem;DST=memory_init.bin 4 | awk '{print substr($0, 7, 2) substr($0, 5, 2) substr($0, 3, 2) substr($0, 1, 2)}' $SRC | xxd -r -p > $DST 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/rtl/pll/pll_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/rtl/pll/pll_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module pll_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked 15 | ); 16 | 17 | altera_pll #( 18 | .fractional_vco_multiplier("false"), 19 | .reference_clock_frequency("50.0 MHz"), 20 | .operation_mode("direct"), 21 | .number_of_clocks(1), 22 | .output_clock_frequency0("25.116279 MHz"), 23 | .phase_shift0("0 ps"), 24 | .duty_cycle0(50), 25 | .output_clock_frequency1("0 MHz"), 26 | .phase_shift1("0 ps"), 27 | .duty_cycle1(50), 28 | .output_clock_frequency2("0 MHz"), 29 | .phase_shift2("0 ps"), 30 | .duty_cycle2(50), 31 | .output_clock_frequency3("0 MHz"), 32 | .phase_shift3("0 ps"), 33 | .duty_cycle3(50), 34 | .output_clock_frequency4("0 MHz"), 35 | .phase_shift4("0 ps"), 36 | .duty_cycle4(50), 37 | .output_clock_frequency5("0 MHz"), 38 | .phase_shift5("0 ps"), 39 | .duty_cycle5(50), 40 | .output_clock_frequency6("0 MHz"), 41 | .phase_shift6("0 ps"), 42 | .duty_cycle6(50), 43 | .output_clock_frequency7("0 MHz"), 44 | .phase_shift7("0 ps"), 45 | .duty_cycle7(50), 46 | .output_clock_frequency8("0 MHz"), 47 | .phase_shift8("0 ps"), 48 | .duty_cycle8(50), 49 | .output_clock_frequency9("0 MHz"), 50 | .phase_shift9("0 ps"), 51 | .duty_cycle9(50), 52 | .output_clock_frequency10("0 MHz"), 53 | .phase_shift10("0 ps"), 54 | .duty_cycle10(50), 55 | .output_clock_frequency11("0 MHz"), 56 | .phase_shift11("0 ps"), 57 | .duty_cycle11(50), 58 | .output_clock_frequency12("0 MHz"), 59 | .phase_shift12("0 ps"), 60 | .duty_cycle12(50), 61 | .output_clock_frequency13("0 MHz"), 62 | .phase_shift13("0 ps"), 63 | .duty_cycle13(50), 64 | .output_clock_frequency14("0 MHz"), 65 | .phase_shift14("0 ps"), 66 | .duty_cycle14(50), 67 | .output_clock_frequency15("0 MHz"), 68 | .phase_shift15("0 ps"), 69 | .duty_cycle15(50), 70 | .output_clock_frequency16("0 MHz"), 71 | .phase_shift16("0 ps"), 72 | .duty_cycle16(50), 73 | .output_clock_frequency17("0 MHz"), 74 | .phase_shift17("0 ps"), 75 | .duty_cycle17(50), 76 | .pll_type("General"), 77 | .pll_subtype("General") 78 | ) altera_pll_i ( 79 | .rst (rst), 80 | .outclk ({outclk_0}), 81 | .locked (locked), 82 | .fboutclk ( ), 83 | .fbclk (1'b0), 84 | .refclk (refclk) 85 | ); 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/rtl/pll/pll_0002_q13.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/build_id.tcl: -------------------------------------------------------------------------------- 1 | 2 | # Build TimeStamp Verilog Module 3 | # Jeff Wiencrot - 8/1/2011 4 | # Sorgelig - 02/11/2019 5 | proc generateBuildID_Verilog {} { 6 | 7 | # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) 8 | set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\"" 9 | 10 | # Create a Verilog file for output 11 | set outputFileName "build_id.v" 12 | 13 | set fileData "" 14 | if { [file exists $outputFileName]} { 15 | set outputFile [open $outputFileName "r"] 16 | set fileData [read $outputFile] 17 | close $outputFile 18 | } 19 | 20 | if {$buildDate ne $fileData} { 21 | set outputFile [open $outputFileName "w"] 22 | puts -nonewline $outputFile $buildDate 23 | close $outputFile 24 | # Send confirmation message to the Messages window 25 | post_message "Generated: [pwd]/$outputFileName: $buildDate" 26 | } 27 | } 28 | 29 | # Build CDF file 30 | # Sorgelig - 17/2/2018 31 | proc generateCDF {revision device outpath} { 32 | 33 | set outputFileName "jtag.cdf" 34 | set outputFile [open $outputFileName "w"] 35 | 36 | puts $outputFile "JedecChain;" 37 | puts $outputFile " FileRevision(JESD32A);" 38 | puts $outputFile " DefaultMfr(6E);" 39 | puts $outputFile "" 40 | puts $outputFile " P ActionCode(Ign)" 41 | puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));" 42 | puts $outputFile " P ActionCode(Cfg)" 43 | puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" 44 | puts $outputFile "ChainEnd;" 45 | puts $outputFile "" 46 | puts $outputFile "AlteraBegin;" 47 | puts $outputFile " ChainType(JTAG);" 48 | puts $outputFile "AlteraEnd;" 49 | } 50 | 51 | set project_name [lindex $quartus(args) 1] 52 | set revision [lindex $quartus(args) 2] 53 | 54 | if {[project_exists $project_name]} { 55 | if {[string equal "" $revision]} { 56 | project_open $project_name -revision [get_current_revision $project_name] 57 | } else { 58 | project_open $project_name -revision $revision 59 | } 60 | } else { 61 | post_message -type error "Project $project_name does not exist" 62 | exit 63 | } 64 | 65 | set device [get_global_assignment -name DEVICE] 66 | set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] 67 | 68 | if [is_project_open] { 69 | project_close 70 | } 71 | 72 | generateBuildID_Verilog 73 | generateCDF $revision $device $outpath 74 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/i2c.v: -------------------------------------------------------------------------------- 1 | 2 | module i2c 3 | ( 4 | input CLK, 5 | 6 | input START, 7 | input READ, 8 | input [6:0] I2C_ADDR, 9 | input I2C_WLEN, // 0 - one byte, 1 - two bytes 10 | input [7:0] I2C_WDATA1, 11 | input [7:0] I2C_WDATA2, 12 | output [7:0] I2C_RDATA, 13 | output reg END = 1, 14 | output reg ACK = 0, 15 | 16 | //I2C bus 17 | output I2C_SCL, 18 | inout I2C_SDA 19 | ); 20 | 21 | 22 | // Clock Setting 23 | parameter CLK_Freq = 50_000_000; // 50 MHz 24 | parameter I2C_Freq = 400_000; // 400 KHz 25 | 26 | localparam I2C_FreqX2 = I2C_Freq*2; 27 | 28 | reg I2C_CLOCK; 29 | reg [31:0] cnt; 30 | wire [31:0] cnt_next = cnt + I2C_FreqX2; 31 | 32 | always @(posedge CLK) begin 33 | cnt <= cnt_next; 34 | if(cnt_next >= CLK_Freq) begin 35 | cnt <= cnt_next - CLK_Freq; 36 | I2C_CLOCK <= ~I2C_CLOCK; 37 | end 38 | end 39 | 40 | assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0; 41 | assign I2C_SDA = SDO[3] ? 1'bz : 1'b0; 42 | 43 | reg SCLK; 44 | reg [3:0] SDO; 45 | reg [0:7] rdata; 46 | 47 | reg [5:0] SD_COUNTER; 48 | reg [0:31] SD; 49 | 50 | initial begin 51 | SD_COUNTER = 'b111111; 52 | SD = 'hFFFF; 53 | SCLK = 1; 54 | SDO = 4'b1111; 55 | end 56 | 57 | assign I2C_RDATA = rdata; 58 | 59 | always @(posedge CLK) begin 60 | reg old_clk; 61 | reg old_st; 62 | reg rd,len; 63 | 64 | old_clk <= I2C_CLOCK; 65 | old_st <= START; 66 | 67 | // delay to make sure SDA changed while SCL is stabilized at low 68 | if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]]; 69 | SDO[3:1] <= SDO[2:0]; 70 | 71 | if(~old_st && START) begin 72 | SCLK <= 1; 73 | SDO <= 4'b1111; 74 | ACK <= 0; 75 | END <= 0; 76 | rd <= READ; 77 | len <= I2C_WLEN; 78 | if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111}; 79 | else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011}; 80 | SD_COUNTER <= 0; 81 | end else begin 82 | if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin 83 | SD_COUNTER <= SD_COUNTER + 6'd1; 84 | case(SD_COUNTER) 85 | 01: SCLK <= 0; 86 | 10: ACK <= ACK | I2C_SDA; 87 | 19: if(~rd) begin 88 | ACK <= ACK | I2C_SDA; 89 | if(~len) SD_COUNTER <= 29; 90 | end 91 | 20: if(rd) SCLK <= 1; 92 | 23: if(rd) END <= 1; 93 | 28: if(~rd) ACK <= ACK | I2C_SDA; 94 | 29: if(~rd) SCLK <= 1; 95 | 32: if(~rd) END <= 1; 96 | endcase 97 | 98 | if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA; 99 | end 100 | end 101 | end 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/i2s.v: -------------------------------------------------------------------------------- 1 | 2 | module i2s 3 | #( 4 | parameter AUDIO_DW = 16 5 | ) 6 | ( 7 | input reset, 8 | input clk, 9 | input ce, 10 | 11 | output reg sclk, 12 | output reg lrclk, 13 | output reg sdata, 14 | 15 | input [AUDIO_DW-1:0] left_chan, 16 | input [AUDIO_DW-1:0] right_chan 17 | ); 18 | 19 | always @(posedge clk) begin 20 | reg [7:0] bit_cnt; 21 | reg msclk; 22 | 23 | reg [AUDIO_DW-1:0] left; 24 | reg [AUDIO_DW-1:0] right; 25 | 26 | if (reset) begin 27 | bit_cnt <= 1; 28 | lrclk <= 1; 29 | sclk <= 1; 30 | msclk <= 1; 31 | end 32 | else begin 33 | sclk <= msclk; 34 | if(ce) begin 35 | msclk <= ~msclk; 36 | if(msclk) begin 37 | if(bit_cnt >= AUDIO_DW) begin 38 | bit_cnt <= 1; 39 | lrclk <= ~lrclk; 40 | if(lrclk) begin 41 | left <= left_chan; 42 | right <= right_chan; 43 | end 44 | end 45 | else begin 46 | bit_cnt <= bit_cnt + 1'd1; 47 | end 48 | sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; 49 | end 50 | end 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/math.sv: -------------------------------------------------------------------------------- 1 | 2 | // result = num/div 3 | module sys_udiv 4 | #( 5 | parameter NB_NUM, 6 | parameter NB_DIV 7 | ) 8 | ( 9 | input clk, 10 | input start, 11 | output busy, 12 | 13 | input [NB_NUM-1:0] num, 14 | input [NB_DIV-1:0] div, 15 | output reg [NB_NUM-1:0] result, 16 | output reg [NB_DIV-1:0] remainder 17 | ); 18 | 19 | reg run; 20 | assign busy = run; 21 | 22 | always @(posedge clk) begin 23 | reg [5:0] cpt; 24 | reg [NB_NUM+NB_DIV+1:0] rem; 25 | 26 | if (start) begin 27 | cpt <= 0; 28 | run <= 1; 29 | rem <= num; 30 | end 31 | else if (run) begin 32 | cpt <= cpt + 1'd1; 33 | run <= (cpt != NB_NUM + 1'd1); 34 | remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1]; 35 | if (!rem[NB_DIV + NB_NUM + 1'd1]) 36 | rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0}; 37 | else 38 | rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0}; 39 | result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]}; 40 | end 41 | end 42 | 43 | endmodule 44 | 45 | // result = mul1*mul2 46 | module sys_umul 47 | #( 48 | parameter NB_MUL1, 49 | parameter NB_MUL2 50 | ) 51 | ( 52 | input clk, 53 | input start, 54 | output busy, 55 | 56 | input [NB_MUL1-1:0] mul1, 57 | input [NB_MUL2-1:0] mul2, 58 | output reg [NB_MUL1+NB_MUL2-1:0] result 59 | ); 60 | 61 | reg run; 62 | assign busy = run; 63 | 64 | always @(posedge clk) begin 65 | reg [NB_MUL1+NB_MUL2-1:0] add; 66 | reg [NB_MUL2-1:0] map; 67 | 68 | if (start) begin 69 | run <= 1; 70 | result <= 0; 71 | add <= mul1; 72 | map <= mul2; 73 | end 74 | else if (run) begin 75 | if(!map) run <= 0; 76 | if(map[0]) result <= result + add; 77 | add <= add << 1; 78 | map <= map >> 1; 79 | end 80 | end 81 | 82 | endmodule 83 | 84 | // result = (mul1*mul2)/div 85 | module sys_umuldiv 86 | #( 87 | parameter NB_MUL1, 88 | parameter NB_MUL2, 89 | parameter NB_DIV 90 | ) 91 | ( 92 | input clk, 93 | input start, 94 | output busy, 95 | 96 | input [NB_MUL1-1:0] mul1, 97 | input [NB_MUL2-1:0] mul2, 98 | input [NB_DIV-1:0] div, 99 | output [NB_MUL1+NB_MUL2-1:0] result, 100 | output [NB_DIV-1:0] remainder 101 | ); 102 | 103 | wire mul_run; 104 | wire [NB_MUL1+NB_MUL2-1:0] mul_res; 105 | sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res); 106 | 107 | sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder); 108 | 109 | endmodule 110 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/mcp23009.sv: -------------------------------------------------------------------------------- 1 | // 2 | // MCP23009 3 | // (C) 2019 Alexey Melnikov 4 | // 5 | module mcp23009 6 | ( 7 | input clk, 8 | 9 | output reg [2:0] btn, 10 | input [2:0] led, 11 | output reg sd_cd, 12 | 13 | output scl, 14 | inout sda 15 | ); 16 | 17 | 18 | reg start = 0; 19 | wire ready; 20 | wire error; 21 | reg rw; 22 | wire [7:0] dout; 23 | reg [15:0] din; 24 | 25 | i2c #(50_000_000, 500_000) i2c 26 | ( 27 | .CLK(clk), 28 | .START(start), 29 | .READ(rw), 30 | .I2C_ADDR('h20), 31 | .I2C_WLEN(1), 32 | .I2C_WDATA1(din[15:8]), 33 | .I2C_WDATA2(din[7:0]), 34 | .I2C_RDATA(dout), 35 | .END(ready), 36 | .ACK(error), 37 | .I2C_SCL(scl), 38 | .I2C_SDA(sda) 39 | ); 40 | 41 | always@(posedge clk) begin 42 | reg [3:0] idx = 0; 43 | reg [1:0] state = 0; 44 | reg [15:0] timeout = 0; 45 | 46 | if(~&timeout) begin 47 | timeout <= timeout + 1'd1; 48 | start <= 0; 49 | state <= 0; 50 | idx <= 0; 51 | btn <= 0; 52 | rw <= 0; 53 | sd_cd <= 1; 54 | end 55 | else begin 56 | if(~&init_data[idx]) begin 57 | case(state) 58 | 0: begin 59 | start <= 1; 60 | state <= 1; 61 | din <= init_data[idx]; 62 | end 63 | 1: if(~ready) state <= 2; 64 | 2: begin 65 | start <= 0; 66 | if(ready) begin 67 | state <= 0; 68 | if(!error) idx <= idx + 1'd1; 69 | end 70 | end 71 | endcase 72 | end 73 | else begin 74 | case(state) 75 | 0: begin 76 | start <= 1; 77 | state <= 1; 78 | din <= {8'h09,5'b00000,led}; 79 | end 80 | 1: if(~ready) state <= 2; 81 | 2: begin 82 | start <= 0; 83 | if(ready) begin 84 | state <= 0; 85 | rw <= 0; 86 | if(!error) begin 87 | if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]}; 88 | rw <= ~rw; 89 | end 90 | end 91 | end 92 | endcase 93 | end 94 | end 95 | end 96 | 97 | wire [15:0] init_data[12] = 98 | '{ 99 | 16'h00F8, 100 | 16'h0138, 101 | 16'h0200, 102 | 16'h0300, 103 | 16'h0400, 104 | 16'h0524, 105 | 16'h06FF, 106 | 16'h0700, 107 | 16'h0800, 108 | 16'h0900, 109 | 16'h0A00, 110 | 16'hFFFF 111 | }; 112 | 113 | endmodule 114 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v 8 | set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_audio.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"] 8 | set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"] 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_audio/pll_audio_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 3 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 4 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*" 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_audio/pll_audio_0002.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/10ps 2 | module pll_audio_0002( 3 | 4 | // interface 'refclk' 5 | input wire refclk, 6 | 7 | // interface 'reset' 8 | input wire rst, 9 | 10 | // interface 'outclk0' 11 | output wire outclk_0, 12 | 13 | // interface 'locked' 14 | output wire locked 15 | ); 16 | 17 | altera_pll #( 18 | .fractional_vco_multiplier("true"), 19 | .reference_clock_frequency("50.0 MHz"), 20 | .operation_mode("direct"), 21 | .number_of_clocks(1), 22 | .output_clock_frequency0("24.576000 MHz"), 23 | .phase_shift0("0 ps"), 24 | .duty_cycle0(50), 25 | .output_clock_frequency1("0 MHz"), 26 | .phase_shift1("0 ps"), 27 | .duty_cycle1(50), 28 | .output_clock_frequency2("0 MHz"), 29 | .phase_shift2("0 ps"), 30 | .duty_cycle2(50), 31 | .output_clock_frequency3("0 MHz"), 32 | .phase_shift3("0 ps"), 33 | .duty_cycle3(50), 34 | .output_clock_frequency4("0 MHz"), 35 | .phase_shift4("0 ps"), 36 | .duty_cycle4(50), 37 | .output_clock_frequency5("0 MHz"), 38 | .phase_shift5("0 ps"), 39 | .duty_cycle5(50), 40 | .output_clock_frequency6("0 MHz"), 41 | .phase_shift6("0 ps"), 42 | .duty_cycle6(50), 43 | .output_clock_frequency7("0 MHz"), 44 | .phase_shift7("0 ps"), 45 | .duty_cycle7(50), 46 | .output_clock_frequency8("0 MHz"), 47 | .phase_shift8("0 ps"), 48 | .duty_cycle8(50), 49 | .output_clock_frequency9("0 MHz"), 50 | .phase_shift9("0 ps"), 51 | .duty_cycle9(50), 52 | .output_clock_frequency10("0 MHz"), 53 | .phase_shift10("0 ps"), 54 | .duty_cycle10(50), 55 | .output_clock_frequency11("0 MHz"), 56 | .phase_shift11("0 ps"), 57 | .duty_cycle11(50), 58 | .output_clock_frequency12("0 MHz"), 59 | .phase_shift12("0 ps"), 60 | .duty_cycle12(50), 61 | .output_clock_frequency13("0 MHz"), 62 | .phase_shift13("0 ps"), 63 | .duty_cycle13(50), 64 | .output_clock_frequency14("0 MHz"), 65 | .phase_shift14("0 ps"), 66 | .duty_cycle14(50), 67 | .output_clock_frequency15("0 MHz"), 68 | .phase_shift15("0 ps"), 69 | .duty_cycle15(50), 70 | .output_clock_frequency16("0 MHz"), 71 | .phase_shift16("0 ps"), 72 | .duty_cycle16(50), 73 | .output_clock_frequency17("0 MHz"), 74 | .phase_shift17("0 ps"), 75 | .duty_cycle17(50), 76 | .pll_type("General"), 77 | .pll_subtype("General") 78 | ) altera_pll_i ( 79 | .rst (rst), 80 | .outclk ({outclk_0}), 81 | .locked (locked), 82 | .fboutclk ( ), 83 | .fbclk (1'b0), 84 | .refclk (refclk) 85 | ); 86 | endmodule 87 | 88 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_hdmi.13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 2 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 3 | set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] 5 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 6 | 7 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] 8 | set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] 9 | 10 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 11 | set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 12 | set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 13 | set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 14 | 15 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" 16 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1" 17 | set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" 18 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_hdmi/pll_hdmi_0002.qip: -------------------------------------------------------------------------------- 1 | set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 2 | set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" 3 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_q13.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] 5 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] 6 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] 7 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/pll_q17.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name QIP_FILE rtl/pll.qip 2 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ] 3 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.qip ] 4 | set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] 5 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/scanlines.v: -------------------------------------------------------------------------------- 1 | module scanlines #(parameter v2=0) 2 | ( 3 | input clk, 4 | 5 | input [1:0] scanlines, 6 | input [23:0] din, 7 | input hs_in,vs_in, 8 | input de_in, 9 | 10 | output reg [23:0] dout, 11 | output reg hs_out,vs_out, 12 | output reg de_out 13 | ); 14 | 15 | reg [1:0] scanline; 16 | always @(posedge clk) begin 17 | reg old_hs, old_vs; 18 | 19 | old_hs <= hs_in; 20 | old_vs <= vs_in; 21 | 22 | if(old_hs && ~hs_in) begin 23 | if(v2) begin 24 | scanline <= scanline + 1'd1; 25 | if (scanline == scanlines) scanline <= 0; 26 | end 27 | else scanline <= scanline ^ scanlines; 28 | end 29 | if(old_vs && ~vs_in) scanline <= 0; 30 | end 31 | 32 | wire [7:0] r,g,b; 33 | assign {r,g,b} = din; 34 | 35 | reg [23:0] d; 36 | always @(*) begin 37 | case(scanline) 38 | 1: // reduce 25% = 1/2 + 1/4 39 | d = {{1'b0, r[7:1]} + {2'b00, r[7:2]}, 40 | {1'b0, g[7:1]} + {2'b00, g[7:2]}, 41 | {1'b0, b[7:1]} + {2'b00, b[7:2]}}; 42 | 43 | 2: // reduce 50% = 1/2 44 | d = {{1'b0, r[7:1]}, 45 | {1'b0, g[7:1]}, 46 | {1'b0, b[7:1]}}; 47 | 48 | 3: // reduce 75% = 1/4 49 | d = {{2'b00, r[7:2]}, 50 | {2'b00, g[7:2]}, 51 | {2'b00, b[7:2]}}; 52 | 53 | default: d = {r,g,b}; 54 | endcase 55 | end 56 | 57 | always @(posedge clk) begin 58 | reg [23:0] dout1, dout2; 59 | reg de1,de2,vs1,vs2,hs1,hs2; 60 | 61 | dout <= dout2; dout2 <= dout1; dout1 <= d; 62 | vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in; 63 | hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in; 64 | de_out <= de2; de2 <= de1; de1 <= de_in; 65 | end 66 | 67 | endmodule 68 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | // 2 | // PWM DAC 3 | // 4 | // MSBI is the highest bit number. NOT amount of bits! 5 | // 6 | module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) 7 | ( 8 | output reg DACout, //Average Output feeding analog lowpass 9 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 10 | input CLK, 11 | input RESET 12 | ); 13 | 14 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 15 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 16 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 17 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 18 | 19 | always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 20 | always @(*) DeltaAdder = DACin + DeltaB; 21 | always @(*) SigmaAdder = DeltaAdder + SigmaLatch; 22 | 23 | always @(posedge CLK or posedge RESET) begin 24 | if(RESET) begin 25 | SigmaLatch <= 1'b1 << (MSBI+1); 26 | DACout <= INV; 27 | end else begin 28 | SigmaLatch <= SigmaAdder; 29 | DACout <= SigmaLatch[MSBI+2] ^ INV; 30 | end 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/sys_dual_sdram.tcl: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Secondary SDRAM 3 | #============================================================ 4 | set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] 5 | set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] 6 | set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] 7 | set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] 8 | set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] 9 | set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] 10 | set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] 11 | set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] 12 | set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] 13 | set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] 14 | 15 | set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] 16 | set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] 17 | set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] 18 | set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] 19 | set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] 20 | set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] 21 | set_location_assignment PIN_AG24 -to SDRAM2_A[12] 22 | set_location_assignment PIN_AH22 -to SDRAM2_CLK 23 | set_location_assignment PIN_AH21 -to SDRAM2_A[9] 24 | set_location_assignment PIN_AG21 -to SDRAM2_A[11] 25 | set_location_assignment PIN_AH23 -to SDRAM2_A[7] 26 | set_location_assignment PIN_AA20 -to SDRAM2_A[8] 27 | set_location_assignment PIN_AF22 -to SDRAM2_A[5] 28 | set_location_assignment PIN_AE22 -to SDRAM2_A[6] 29 | set_location_assignment PIN_AG20 -to SDRAM2_nWE 30 | set_location_assignment PIN_AF21 -to SDRAM2_A[4] 31 | 32 | set_location_assignment PIN_AG19 -to SDRAM2_nCAS 33 | set_location_assignment PIN_AH19 -to SDRAM2_nRAS 34 | set_location_assignment PIN_AG18 -to SDRAM2_nCS 35 | set_location_assignment PIN_AH18 -to SDRAM2_BA[0] 36 | set_location_assignment PIN_AF18 -to SDRAM2_BA[1] 37 | set_location_assignment PIN_AF20 -to SDRAM2_A[10] 38 | set_location_assignment PIN_AG15 -to SDRAM2_A[0] 39 | set_location_assignment PIN_AE20 -to SDRAM2_A[1] 40 | set_location_assignment PIN_AE19 -to SDRAM2_A[2] 41 | set_location_assignment PIN_AE17 -to SDRAM2_A[3] 42 | 43 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* 44 | set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* 45 | set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* 46 | set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] 47 | set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] 48 | set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* 49 | 50 | set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1" 51 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/vga_out.sv: -------------------------------------------------------------------------------- 1 | 2 | module vga_out 3 | ( 4 | input clk, 5 | input ypbpr_en, 6 | 7 | input hsync, 8 | input vsync, 9 | input csync, 10 | 11 | input [23:0] din, 12 | output [23:0] dout, 13 | 14 | output reg hsync_o, 15 | output reg vsync_o, 16 | output reg csync_o 17 | ); 18 | 19 | wire [5:0] red = din[23:18]; 20 | wire [5:0] green = din[15:10]; 21 | wire [5:0] blue = din[7:2]; 22 | 23 | // http://marsee101.blog19.fc2.com/blog-entry-2311.html 24 | // Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) 25 | // Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) 26 | // Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) 27 | 28 | reg [7:0] y, pb, pr; 29 | reg [23:0] rgb; 30 | always @(posedge clk) begin 31 | reg [18:0] y_1r, pb_1r, pr_1r; 32 | reg [18:0] y_1g, pb_1g, pr_1g; 33 | reg [18:0] y_1b, pb_1b, pr_1b; 34 | reg [18:0] y_2, pb_2, pr_2; 35 | reg [23:0] din1, din2; 36 | reg hsync2, vsync2, csync2; 37 | reg hsync1, vsync1, csync1; 38 | 39 | y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0}); 40 | pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}); 41 | pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}); 42 | 43 | y_1g <= {green, 9'd0} + {green, 2'd0}; 44 | pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0}; 45 | pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}; 46 | 47 | y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}; 48 | pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}; 49 | pr_1b <= {blue, 6'd0} + {blue, 3'd0}; 50 | 51 | y_2 <= y_1r + y_1g + y_1b; 52 | pb_2 <= pb_1r - pb_1g + pb_1b; 53 | pr_2 <= pr_1r - pr_1g - pr_1b; 54 | 55 | y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8]; 56 | pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8]; 57 | pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8]; 58 | 59 | hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; 60 | vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; 61 | csync_o <= csync2; csync2 <= csync1; csync1 <= csync; 62 | 63 | rgb <= din2; din2 <= din1; din1 <= din; 64 | end 65 | 66 | assign dout = ypbpr_en ? {pr, y, pb} : rgb; 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /boards/de10nano_cyclonev_mister/sys/video_cleaner.sv: -------------------------------------------------------------------------------- 1 | // 2 | // 3 | // Copyright (c) 2018 Sorgelig 4 | // 5 | // This program is GPL Licensed. See COPYING for the full license. 6 | // 7 | // 8 | //////////////////////////////////////////////////////////////////////////////////////////////////////// 9 | 10 | `timescale 1ns / 1ps 11 | 12 | module video_cleaner 13 | ( 14 | input clk_vid, 15 | input ce_pix, 16 | 17 | input [7:0] R, 18 | input [7:0] G, 19 | input [7:0] B, 20 | 21 | input HSync, 22 | input VSync, 23 | input HBlank, 24 | input VBlank, 25 | 26 | //optional de 27 | input DE_in, 28 | 29 | // video output signals 30 | output reg [7:0] VGA_R, 31 | output reg [7:0] VGA_G, 32 | output reg [7:0] VGA_B, 33 | output reg VGA_VS, 34 | output reg VGA_HS, 35 | output VGA_DE, 36 | 37 | // optional aligned blank 38 | output reg HBlank_out, 39 | output reg VBlank_out, 40 | 41 | // optional aligned de 42 | output reg DE_out 43 | ); 44 | 45 | wire hs, vs; 46 | s_fix sync_v(clk_vid, HSync, hs); 47 | s_fix sync_h(clk_vid, VSync, vs); 48 | 49 | wire hbl = hs | HBlank; 50 | wire vbl = vs | VBlank; 51 | 52 | assign VGA_DE = ~(HBlank_out | VBlank_out); 53 | 54 | always @(posedge clk_vid) begin 55 | if(ce_pix) begin 56 | HBlank_out <= hbl; 57 | 58 | VGA_HS <= hs; 59 | if(~VGA_HS & hs) VGA_VS <= vs; 60 | 61 | VGA_R <= R; 62 | VGA_G <= G; 63 | VGA_B <= B; 64 | DE_out <= DE_in; 65 | 66 | if(HBlank_out & ~hbl) VBlank_out <= vbl; 67 | end 68 | end 69 | 70 | endmodule 71 | 72 | module s_fix 73 | ( 74 | input clk, 75 | 76 | input sync_in, 77 | output sync_out 78 | ); 79 | 80 | assign sync_out = sync_in ^ pol; 81 | 82 | reg pol; 83 | always @(posedge clk) begin 84 | integer pos = 0, neg = 0, cnt = 0; 85 | reg s1,s2; 86 | 87 | s1 <= sync_in; 88 | s2 <= s1; 89 | 90 | if(~s2 & s1) neg <= cnt; 91 | if(s2 & ~s1) pos <= cnt; 92 | 93 | cnt <= cnt + 1; 94 | if(s2 != s1) cnt <= 0; 95 | 96 | pol <= pos > neg; 97 | end 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /boards/digilent_spartan3_s200/README.md: -------------------------------------------------------------------------------- 1 | ## Digilent Spartan3 S200 2 | 3 | The old Digilent Spartan3 S200 is a very popular development board based in 4 | the XC3S200 FPGA, which use the old, but popular LUT4 technology, and 5 | include lots of anscient peripherals, such as: 6 | 7 | - a XC3S200 FPGA w/ 256 pins 8 | - lots of clocks: 50MHz oscillator 9 | - socket for an extra oscillator 10 | - on-board RS232 converter *** 11 | - on-board VGA interface 12 | - on-board PS2 interface 13 | - on-board Xilinx Serial FLASH 14 | - on-board SRAM (static SRAM) 15 | - 4x 8-segment displays 16 | - 8 LEDs 17 | - 8 on/off switches 18 | - 4 switches 19 | - lots of GPIO pins 20 | 21 | *** note: due to the old RS232 nature, it is recommended use 9600bps! 22 | -------------------------------------------------------------------------------- /boards/digilent_spartan3_s200/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/digilent_spartan3_s200/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/digilent_spartan3_s200/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | #NET "CLK" TNM_NET = CLK; 30 | 31 | # without cache controller 32 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 33 | 34 | # with cache controller 35 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 36 | 37 | # Digilent Spartan3 S200 38 | 39 | NET XCLK LOC = T9 | PERIOD = 50MHz HIGH 50%; 40 | #NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; 41 | #NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; 42 | 43 | NET XRES LOC = M13 | PULLDOWN; 44 | 45 | NET UART_RXD LOC = T13 | PULLUP; 46 | NET UART_TXD LOC = R13; 47 | 48 | NET LED[3] LOC = K12; 49 | NET LED[2] LOC = P14; 50 | NET LED[1] LOC = L12; 51 | NET LED[0] LOC = N14; 52 | 53 | NET DEBUG[3] LOC = P13; # J4-1 54 | NET DEBUG[2] LOC = N12; # J4-2 55 | NET DEBUG[1] LOC = P12; # J4-3 56 | NET DEBUG[0] LOC = P11; # J4-4 57 | -------------------------------------------------------------------------------- /boards/digilent_spartan3_s200/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | #-g ExtMasterCclk_en:No 15 | #-g SPI_buswidth:1 16 | #-g TIMER_CFG:0xFFFF 17 | #-g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | #-g en_sw_gsr:No 27 | #-g drive_awake:No 28 | #-g sw_clk:Startupclk 29 | #-g sw_gwe_cycle:5 30 | #-g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/digilent_spartan3_s200/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/digilent_spartan3_s200/darksocv.prj 5 | -ifmt mixed 6 | -ofn darksocv 7 | -ofmt NGC 8 | -p xc3s200-4-ft256 9 | -top darksocv 10 | -opt_mode Speed 11 | -opt_level 1 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -verilog2001 YES 26 | -define { DIGILENT_SPARTAN3_S200=1 } 27 | -fsm_extract YES -fsm_encoding Auto 28 | -safe_implementation No 29 | -fsm_style LUT 30 | -ram_extract Yes 31 | -ram_style Auto 32 | -rom_extract Yes 33 | -mux_style Auto 34 | -decoder_extract YES 35 | -priority_extract Yes 36 | -shreg_extract YES 37 | -shift_extract YES 38 | -xor_collapse YES 39 | -rom_style Auto 40 | -auto_bram_packing NO 41 | -mux_extract Yes 42 | -resource_sharing YES 43 | -async_to_sync NO 44 | -mult_style Auto 45 | -iobuf YES 46 | -max_fanout 100000 47 | -bufg 8 48 | -register_duplication YES 49 | -register_balancing No 50 | -slice_packing YES 51 | -optimize_primitives NO 52 | -use_clock_enable Auto 53 | -use_sync_set Auto 54 | -use_sync_reset Auto 55 | -iob Auto 56 | -equivalent_register_removal YES 57 | -slice_utilization_ratio_maxmargin 5 58 | -------------------------------------------------------------------------------- /boards/ice40_breakout_hx8k/README.md: -------------------------------------------------------------------------------- 1 | Just use yosys/nextpnr-ice40 2 | --------------------------- 3 | 4 | download toolchain from https://github.com/YosysHQ/oss-cad-suite-build/releases 5 | you can change the pll via icepll tool and change config.vh to adjust fmax via BOARD_CK. 6 | -------------------------------------------------------------------------------- /boards/ice40_breakout_hx8k/build.sh: -------------------------------------------------------------------------------- 1 | rm -f darksocv.asc darksocv.json darksocv.asc darksocv.bit 2 | yosys -D __YOSYS__ -D LATTICE_ICE40_BREAKOUT_HX8K -p "synth_ice40 -json darksocv.json -top darksocv" ../../rtl/darksocv.v ../../rtl/darkriscv.v ../../rtl/darkuart.v pll.v 3 | nextpnr-ice40 -r --hx8k --timing-allow-fail --json darksocv.json --asc darksocv.asc --package ct256 --pcf darksocv.pcf 4 | icepack -s darksocv.asc darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/ice40_breakout_hx8k/darksocv.pcf: -------------------------------------------------------------------------------- 1 | 2 | # Pinout for the iCE40-HX8K Breakout Board 3 | 4 | set_io XCLK J3 5 | 6 | set_io UART_TXD B12 7 | set_io UART_RXD B10 8 | 9 | # left on J3 10 | set_io debug_ser_tx T1 11 | set_io debug_ser_rx R3 12 | 13 | set_io -pullup yes XRES C16 14 | 15 | set_io DEBUG[3] B5 # D9 16 | set_io DEBUG[2] B4 # D8 17 | set_io DEBUG[1] A2 # D7 18 | set_io DEBUG[0] A1 # D6 19 | set_io LED[3] C5 # D5 20 | set_io LED[2] C4 # D4 21 | set_io LED[1] B3 # D3 22 | set_io LED[0] C3 # D2 23 | 24 | -------------------------------------------------------------------------------- /boards/ice40_breakout_hx8k/pll.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 12.000 MHz 9 | * Requested output frequency: 65.000 MHz 10 | * Achieved output frequency: 65.250 MHz 11 | */ 12 | 13 | module pll( 14 | input clock_in, 15 | output clock_out, 16 | output locked 17 | ); 18 | 19 | SB_PLL40_CORE #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0000), // DIVR = 0 22 | .DIVF(7'b1010110), // DIVF = 86 23 | .DIVQ(3'b100), // DIVQ = 4 24 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 25 | ) uut ( 26 | .LOCK(locked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .REFERENCECLK(clock_in), 30 | .PLLOUTCORE(clock_out) 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /boards/ice40_breakout_hx8k/upload.sh: -------------------------------------------------------------------------------- 1 | openFPGALoader --board ice40_generic darksocv.bit 2 | 3 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/.gitignore: -------------------------------------------------------------------------------- 1 | .project 2 | .svproject 3 | syn_results 4 | archiv 5 | impl1 6 | .recovery 7 | *_tcr.dir 8 | .*.ini 9 | *.asd 10 | *.asdb 11 | *.awb 12 | *.awc 13 | *.bak 14 | *.bak.* 15 | *.ccl 16 | *.cfg 17 | *.cmd 18 | *.cst 19 | *.htm 20 | *.html 21 | *.log 22 | *.rva 23 | *.rvs 24 | *.trc 25 | *.rvl 26 | *.ngd 27 | *.ngo 28 | *.tcl 29 | *.svf 30 | *.vhm 31 | *.xml 32 | *.zip 33 | *.vhd 34 | *~ 35 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/build.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Simple script to invoke diamondc - the Lattice Diamond TCL console 4 | 5 | 6 | DIAMOND_PATH=/usr/local/diamond/3.11_x64 7 | 8 | export TEMP=/tmp 9 | export LSC_INI_PATH="" 10 | export LSC_DIAMOND=true 11 | export TCL_LIBRARY=$DIAMOND_PATH/tcltk/lib/tcl8.5 12 | export FOUNDRY=$DIAMOND_PATH/ispFPGA 13 | export PATH=$FOUNDRY/bin/lin64:"$PATH" 14 | $DIAMOND_PATH/bin/lin64/diamondc darksocv.tcl 2>&1 | tee darksocv_build.log 15 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/darksocv.ldf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/darksocv.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS ; 2 | BLOCK ASYNCPATHS ; 3 | LOCATE COMP "DEBUG[0]" SITE "37" ; 4 | LOCATE COMP "DEBUG[1]" SITE "38" ; 5 | LOCATE COMP "DEBUG[2]" SITE "39" ; 6 | LOCATE COMP "DEBUG[3]" SITE "40" ; 7 | LOCATE COMP "LED[0]" SITE "43" ; 8 | LOCATE COMP "LED[1]" SITE "44" ; 9 | LOCATE COMP "LED[2]" SITE "45" ; 10 | LOCATE COMP "LED[3]" SITE "46" ; 11 | IOBUF PORT "DEBUG[0]" IO_TYPE=LVCMOS33 DRIVE=12 ; 12 | IOBUF PORT "DEBUG[1]" IO_TYPE=LVCMOS33 ; 13 | IOBUF PORT "DEBUG[2]" IO_TYPE=LVCMOS33 ; 14 | IOBUF PORT "DEBUG[3]" IO_TYPE=LVCMOS33 ; 15 | IOBUF PORT "LED[0]" IO_TYPE=LVCMOS33 ; 16 | IOBUF PORT "LED[1]" IO_TYPE=LVCMOS33 ; 17 | IOBUF PORT "LED[2]" IO_TYPE=LVCMOS33 ; 18 | IOBUF PORT "LED[3]" IO_TYPE=LVCMOS33 ; 19 | IOBUF PORT "UART_TXD" IO_TYPE=LVCMOS33 ; 20 | LOCATE COMP "UART_TXD" SITE "109" ; 21 | LOCATE COMP "UART_RXD" SITE "110" ; 22 | IOBUF PORT "UART_RXD" IO_TYPE=LVCMOS33 ; 23 | LOCATE COMP "XRES" SITE "19" ; 24 | IOBUF PORT "XRES" IO_TYPE=LVCMOS33 ; 25 | LOCATE COMP "XCLK" SITE "21" ; 26 | IOBUF PORT "XCLK" IO_TYPE=LVCMOS33 ; 27 | 28 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/darksocv.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2020, Ivan Vasilev 3 | # All rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # * Redistributions of source code must retain the above copyright notice, this 9 | # list of conditions and the following disclaimer. 10 | # 11 | # * Redistributions in binary form must reproduce the above copyright notice, 12 | # this list of conditions and the following disclaimer in the documentation 13 | # and/or other materials provided with the distribution. 14 | # 15 | # * Neither the name of the copyright holder nor the names of its 16 | # contributors may be used to endorse or promote products derived from 17 | # this software without specific prior written permission. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # ===8<--------------------------------------------------------- cut here! 31 | 32 | # board LatticeXP2 Brevia 2 33 | BOARD = lattice_brevia2_xp2 34 | DEVICE = LFXP2-5E-6TN144C 35 | DIAMOND_PATH=/usr/local/diamond/3.11_x64 36 | IMPL = impl1 37 | TMP = ../tmp 38 | 39 | 40 | # Expected by Lattice Diamond 41 | export TEMP=../tmp 42 | export LSC_INI_PATH="" 43 | export LSC_DIAMOND=true 44 | export TCL_LIBRARY=$(DIAMOND_PATH)/tcltk/lib/tcl8.5 45 | export FOUNDRY=$(DIAMOND_PATH)/ispFPGA 46 | export PATH:=$(FOUNDRY)/bin/lin64:${PATH} 47 | 48 | 49 | RTL = ../rtl 50 | SRC = ../src 51 | BIT = $(TMP)/darksocv.bit 52 | 53 | RTLS = $(RTL)/darksocv.v $(RTL)/darkriscv.v $(RTL)/darkuart.v $(RTL)/config.vh 54 | 55 | ifdef HARVARD 56 | BOOT = $(SRC)/darksocv.rom.mem $(SRC)/darksocv.ram.mem 57 | else 58 | BOOT = $(SRC)/darksocv.mem 59 | endif 60 | 61 | default: build 62 | 63 | $(BIT): $(BOOT) $(RTLS) 64 | echo PATH: $$PATH 65 | cd $(BOARD) && $(DIAMOND_PATH)/bin/lin64/diamondc darksocv.tcl 2>&1 | tee darksocv_build.log 66 | cp $(BOARD)/$(IMPL)/darksocv_impl1.jed $(BIT) 67 | 68 | clean: 69 | -rm -v $(TMP)/* 70 | rm -rf $(BOARD)/$(IMPL) 71 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/darksocv.tcl: -------------------------------------------------------------------------------- 1 | prj_project open "darksocv.ldf" 2 | prj_run Synthesis -impl impl1 3 | prj_run Translate -impl impl1 4 | prj_run Map -impl impl1 5 | prj_run PAR -impl impl1 6 | prj_run PAR -impl impl1 -task PARTrace 7 | prj_run Export -impl impl1 -task Bitgen 8 | prj_project close 9 | -------------------------------------------------------------------------------- /boards/lattice_brevia2_xp2/lattice_brevia2_xp2.xcf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | JTAG 7 | 8 | 9 | 1 10 | Lattice 11 | LatticeXP2 12 | LFXP2-5E 13 | 0x01299043 14 | All 15 | LFXP2-5E 16 | 17 | 8 18 | 11111111 19 | 1 20 | 0 21 | 22 | ./impl1/darksocv_impl1.jed 23 | 05/12/20 14:57:02 24 | 0x7A90 25 | FLASH Erase,Program,Verify 26 | 35 | 36 | 37 | 38 | SEQUENTIAL 39 | ENTIRED CHAIN 40 | No Override 41 | TLR 42 | TLR 43 | 44 | 1 45 | 46 | 47 | USB2 48 | FTUSB-0 49 | LATTICE FTUSB INTERFACE CABLE A Location 0000 Serial LATTICE FTUSB INTERFACE CABLE A 50 | 51 | TRST ABSENT; 52 | ISPEN ABSENT; 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /boards/max1000_max10/README.md: -------------------------------------------------------------------------------- 1 | # MAX1000 board (Trenz Electronic) 2 | 3 | ## General information 4 | The Max1000 board is a small development board based on Intel/Altera Max10 family of FPGAs.\ 5 | It has a 10M08SAU169C8G chip and also includes the following peripherals: 6 | * 64MBit SDRAM (16-bit data bus) 7 | * 64Mbit Flash Memory 8 | * Arrow USB Programmer2 on-board for programming; JTAG + Serial (FT2232H) 9 | * 8 LEDs + 2 push-buttons 10 | * 12 MHz MEMS Oscillator 11 | * 3-axis accelerometer + thermal sensor 12 | * Many headers: PMOD, Arduino MKR, JTAG, I/O.. 13 | 14 | For more detailed information, see here:\ 15 | https://wiki.trenz-electronic.de/display/PD/TEI0001+Getting+Started 16 | 17 | The DarkRISCV/darksoc builds out-of-the box using Quartus command-line, 18 | taking about ~40% of the on-chip logic for the SoC demo. 19 | - It uses an altera pll QIP to transform 12=>32MHz (TODO: maybe integrate it into darkpll), 20 | - and a simplified darkram based on altsyncram to properly infer BRAM (TODO: maybe integrate it into darkram). 21 | 22 | ## Instructions 23 | Install Quartus with Max10 support, `srecord`, `awk`, `xxd`.\ 24 | Read/apply the Trenz Electronics docs to enable the max1000 support (eg: udev rules, ftdi driver etc..)\ 25 | Ensure that `QUARTUS` macro defined in `boards/max1000_max10/darksocv.mk` points to your Quartus install, then, from darkriscv root directory:\ 26 | Build the bitstream: 27 | ``` 28 | make all BOARD=max1000_max10 29 | ``` 30 | Program the device like this: 31 | ``` 32 | make install BOARD=max1000_max10 33 | ``` 34 | Finally connect at baudrate=115200 to the serial port (eg: /dev/ttyUSB0 or /dev/ttyUSB1) with `screen` (or any other terminal like Putty, etc..): 35 | ```shell 36 | screen /dev/ttyUSB? 115200 37 | ``` 38 | and you should see DarkRISCV booting up: 39 | ``` 40 | ... 41 | board: max1000 max10 (id=19) 42 | ... 43 | 36253> led aa55 44 | led = aa55 45 | 1> 46 | ``` 47 | You should see 0x55 on the 8 leds. 48 | 49 | To clean the board-related objects: 50 | ``` 51 | make clean BOARD=max1000_max10 52 | ``` 53 | 54 | # SPI Support 55 | Builtin SPI accelerometer sensor can be accessed by enabling the Verilog macro and selecting the spidemo application. 56 | ```shell 57 | make clean all BOARD=max1000_max10 APPLICATION=spidemo 58 | make install BOARD=max1000_max10 59 | ``` 60 | In putty: 61 | ``` 62 | ... 63 | INSTRUCTION SETS WANT TO BE FREE 64 | 65 | Welcome to DarkRISCV! 66 | 67 | 10335> sensor 68 | out_x=0f10 69 | out_x=0f10 70 | out_x=0ef0 71 | out_x=0ef0 72 | out_x=0ef0 73 | out_x=0f60 74 | out_x=0f60 75 | out_x=0ec0 76 | out_x=0ec0 77 | out_x=0e70 78 | out_x=0e70 79 | out_x=0e70 80 | ... 81 | ``` 82 | The sensor OUT_X reading is output on the serial port and drawn visually on the 8 leds. 83 | -------------------------------------------------------------------------------- /boards/max1000_max10/_darkram.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "../../rtl/config.vh" 3 | 4 | module darkram #(parameter INIT_FILE = "../memory_init.mif") 5 | ( 6 | input CLK, // Clock 7 | input RES, // Reset 8 | input HLT, // Halt 9 | 10 | input IDREQ, // Instruction fetch request 11 | input [31:0] IADDR, // Instruction address 12 | output [31:0] IDATA, // Instruction data output 13 | output IDACK, // Instruction acknowledge 14 | 15 | input XDREQ, // Data request 16 | input XRD, // Read enable 17 | input XWR, // Write enable 18 | input [3:0] XBE, // Byte enable 19 | input [31:0] XADDR, // Data address 20 | input [31:0] XATAI, // Data input 21 | output [31:0] XATAO, // Data output 22 | output XDACK, // Data acknowledge 23 | 24 | output [3:0] DEBUG // Debug signals 25 | ); 26 | 27 | // Internal signals 28 | wire [31:0] ram_q_a, ram_q_b; 29 | wire write_enable; 30 | 31 | 32 | // Instantiate altsyncram 33 | altsyncram #( 34 | .operation_mode("BIDIR_DUAL_PORT"), 35 | .width_a(32), 36 | .widthad_a(13), // Address width for 4KB RAM 37 | .numwords_a(2048), 38 | .width_b(32), 39 | .widthad_b(13), 40 | .numwords_b(2048), 41 | .lpm_type("altsyncram"), 42 | .ram_block_type("AUTO"), 43 | .init_file(INIT_FILE), 44 | .outdata_reg_a("UNREGISTERED"), 45 | .outdata_reg_b("UNREGISTERED"), 46 | .indata_reg_b("CLOCK0"), 47 | .address_reg_b("CLOCK0"), 48 | .wrcontrol_wraddress_reg_b("CLOCK0"), 49 | .byte_size(8), 50 | .width_byteena_a(4), 51 | .width_byteena_b(4), 52 | .byteena_reg_b("CLOCK0") 53 | ) ram_inst ( 54 | .clock0(CLK), 55 | .address_a(IADDR[12:2]), 56 | .q_a(ram_q_a), 57 | .address_b(XADDR[12:2]), 58 | .wren_b(write_enable), 59 | .byteena_b(XBE), 60 | .data_b(XATAI), 61 | .q_b(ram_q_b) 62 | ); 63 | assign write_enable = XWR & XDREQ; 64 | 65 | // Assign instruction fetch outputs 66 | assign IDATA = ram_q_a; 67 | assign IDACK = IDREQ; // Immediate ACK for simplicity 68 | 69 | // Assign data read/write outputs 70 | assign XATAO = ram_q_b; 71 | assign XDACK = DTACK==1 ||(XDREQ&&XWR); 72 | reg [3:0] DTACK = 0; 73 | always@(posedge CLK) // stage #1.0 74 | begin 75 | DTACK <= RES ? 0 : DTACK ? DTACK-1 : XDREQ && XRD ? 1 : 0; 76 | end 77 | 78 | // Debug outputs (for observability) 79 | assign DEBUG = { XDREQ,XRD,XWR,XDACK }; 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /boards/max1000_max10/bin2mif.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | WORD=4 4 | SRC=memory_init.bin;DST=memory_init.mif 5 | srec_cat $SRC -binary -byte-swap 4 -o $DST -mif $WORD 6 | -------------------------------------------------------------------------------- /boards/max1000_max10/darksocv.mk: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright (c) 2025, Nicolas Sauzede 3 | # All rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # * Redistributions of source code must retain the above copyright notice, this 9 | # list of conditions and the following disclaimer. 10 | # 11 | # * Redistributions in binary form must reproduce the above copyright notice, 12 | # this list of conditions and the following disclaimer in the documentation 13 | # and/or other materials provided with the distribution. 14 | # 15 | # * Neither the name of the copyright holder nor the names of its 16 | # contributors may be used to endorse or promote products derived from 17 | # this software without specific prior written permission. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | # 30 | # ===8<--------------------------------------------------------- cut here! 31 | 32 | BOARD:=max1000_max10 33 | 34 | BRD:=../boards/$(BOARD) 35 | RTL:=../rtl 36 | SRC:=../src 37 | 38 | RTLS:= 39 | RTLS+=$(RTL)/darksocv.v 40 | RTLS+=$(RTL)/darkio.v 41 | RTLS+=$(RTL)/darkpll.v 42 | RTLS+=$(RTL)/darkuart.v 43 | RTLS+=$(RTL)/darkriscv.v 44 | RTLS+=$(RTL)/darkbridge.v 45 | RTLS+=$(BRD)/dut.v 46 | RTLS+=$(BRD)/top.v 47 | RTLS+=$(BRD)/_darkram.v 48 | 49 | BOOT:=$(BRD)/memory_init.mif 50 | 51 | BIT:=$(BRD)/output_files/max1000.sof 52 | 53 | QUARTUS:=~/intelFPGA_lite/17.0 54 | QBIN:=$(QUARTUS)/quartus/bin 55 | 56 | default: all 57 | 58 | $(BIT): $(RTLS) $(BOOT) 59 | (cd $(BRD) ; $(QBIN)/quartus_sh --flow compile max1000) 60 | 61 | $(BRD)/memory_init.mem: $(SRC)/darksocv.mem 62 | cp $< $@ 63 | 64 | $(BRD)/memory_init.bin: $(BRD)/memory_init.mem 65 | (cd $(BRD) ; ./mem2bin.sh) 66 | 67 | $(BOOT): $(BRD)/memory_init.bin 68 | (cd $(BRD) ; ./bin2mif.sh) 69 | 70 | all: $(BIT) 71 | 72 | install: $(BIT) 73 | (cd $(BRD) ; $(QBIN)/quartus_pgm -c Arrow-USB-Blaster max1000.cdf) 74 | 75 | clean: 76 | rm -f $(BRD)/memory_init.mif $(BRD)/memory_init.mem $(BRD)/memory_init.bin 77 | rm -rf $(BRD)/db $(BRD)/incremental_db $(BRD)/output_files 78 | -------------------------------------------------------------------------------- /boards/max1000_max10/dut.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "../../rtl/config.vh" 3 | 4 | module dut ( 5 | input rx, 6 | output tx, 7 | `ifdef SPI 8 | output spi_csn, 9 | output spi_sck, 10 | inout spi_mosi, 11 | input spi_miso, 12 | `endif 13 | inout [8:1] pio, 14 | output [31:0] leds, 15 | input reset, 16 | input clk 17 | ); 18 | wire [31:0] oport; 19 | wire [31:0] iport; 20 | darksocv soc0 ( 21 | .UART_RXD(rx), // UART receive line 22 | .UART_TXD(tx), // UART transmit line 23 | `ifdef SPI 24 | .SPI_SCK(spi_sck), // SPI clock output 25 | .SPI_MOSI(spi_mosi), // SPI master data output, slave data input; or SDI/O (3-wire mode) 26 | .SPI_MISO(spi_miso), // SPI master data input, slave data output 27 | .SPI_CSN(spi_csn), // SPI CSN output (active LOW) 28 | `endif 29 | .LED(leds), // on-board leds 30 | .IPORT(iport), 31 | .OPORT(oport), 32 | 33 | .XCLK(clk), // external clock 34 | .XRES(reset) // external reset 35 | ); 36 | `ifndef SPIBB 37 | wire [3:0] pmbuttons; 38 | wire [3:0] pmleds; 39 | assign pmleds = oport[3:0]; 40 | assign iport = {24'b0, pmbuttons}; 41 | pmodbutled pmodbutled1( 42 | .pio(pio), 43 | .buttons(pmbuttons), 44 | .leds(pmleds) 45 | ); 46 | `endif 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /boards/max1000_max10/max1000.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(10M08SAU169) Path("./output_files/") File("max1000.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /boards/max1000_max10/max1000.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2019 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition 22 | # Date created = 20:41:21 abril 16, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "19.1" 27 | DATE = "20:41:21 abril 16, 2020" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "max1000" 32 | -------------------------------------------------------------------------------- /boards/max1000_max10/mem2bin.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | SRC=memory_init.mem;DST=memory_init.bin 4 | awk '{print substr($0, 7, 2) substr($0, 5, 2) substr($0, 3, 2) substr($0, 1, 2)}' $SRC | xxd -r -p > $DST 5 | -------------------------------------------------------------------------------- /boards/max1000_max10/pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /boards/max1000_max10/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "23.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 7 | -------------------------------------------------------------------------------- /boards/max1000_max10/pmodbutled.v: -------------------------------------------------------------------------------- 1 | /* 2 | IMPORTANT: 3 | Must place the Papilio wingbutled only on the rightmost PMOD PIO pins, 4 | ie: avoid all 3.3V/GND pins! 5 | Pmod Wing Out In 6 | PIO_08 GND 0 7 | PIO_07 2V5 z 8 | PIO_06 3V3 1 9 | PIO_05 5V z 10 | PIO_04 LED4 leds[1] 11 | PIO_03 PB4 z buttons[1] 12 | PIO_02 LED3 leds[0] 13 | PIO_01 PB3 z buttons[0] 14 | */ 15 | module pmodbutled ( 16 | inout [8:1] pio, 17 | output [3:0] buttons, 18 | input [3:0] leds 19 | ); 20 | // Assign leds values to specific io pins 21 | assign pio[4] = leds[1]; 22 | assign pio[2] = leds[0]; 23 | 24 | assign pio[8] = 1'b0; // GND 25 | assign pio[6] = 1'b1; // 3V3 26 | 27 | // Set specific io pins to high impedance (Z) 28 | assign pio[7] = 1'bz; // 2V5 29 | assign pio[5] = 1'bz; // 5V 30 | assign pio[3] = 1'bz; 31 | assign pio[1] = 1'bz; 32 | 33 | // Assign io pin values to button outputs 34 | assign buttons[1] = pio[3]; 35 | assign buttons[0] = pio[1]; 36 | endmodule 37 | 38 | -------------------------------------------------------------------------------- /boards/max1000_max10/top.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "../../rtl/config.vh" 3 | 4 | module top ( 5 | input CLK12M, 6 | input USER_BTN, 7 | output [7:0] LED, 8 | `ifdef SPI 9 | inout SEN_SDI, 10 | output SEN_SPC, 11 | output SEN_CS, 12 | input SEN_SDO, 13 | `endif 14 | inout [8:1] PIO, 15 | inout [5:0] BDBUS, 16 | inout [14:0] D 17 | ); 18 | wire clk; 19 | pll pll0 ( 20 | .inclk0(CLK12M), 21 | .c0(clk) 22 | ); 23 | wire [31:0] leds; 24 | assign LED = leds[7:0]; 25 | dut dut1 ( 26 | .rx(BDBUS[0]), // BDBUS[0] is USB UART TX (FPGA RX) 27 | .tx(BDBUS[1]), // BDBUS[1] is USB UART RX (FPGA TX) 28 | .leds(leds), 29 | `ifdef SPI 30 | .spi_mosi(SEN_SDI), 31 | .spi_sck(SEN_SPC), 32 | .spi_csn(SEN_CS), 33 | .spi_miso(SEN_SDO), 34 | `endif 35 | .pio(PIO), 36 | .reset(~USER_BTN), 37 | .clk(clk) 38 | ); 39 | endmodule 40 | -------------------------------------------------------------------------------- /boards/openroad/BUILD.bazel: -------------------------------------------------------------------------------- 1 | load("@bazel-orfs//:openroad.bzl", "orfs_flow") 2 | 3 | FASTER = { 4 | # ignore timing repair for now 5 | "SETUP_SLACK_MARGIN": "-1000", 6 | "SKIP_REPORT_METRICS": "1", 7 | "SKIP_LAST_GASP": "1", 8 | # skip checks for now, faster 9 | "PWR_NETS_VOLTAGES": "", 10 | "GND_NETS_VOLTAGES": "", 11 | } 12 | 13 | # SRAMs are specific to PDK, mock one here by 14 | # creating it from flip flops and use mock_area 15 | # to reduce the size of the SRAM to something that 16 | # is a bit more reasonable. 17 | orfs_flow( 18 | name = "darkram", 19 | abstract_stage = "cts", 20 | arguments = FASTER | { 21 | "CORE_UTILIZATION": "10", 22 | "SYNTH_MEMORY_MAX_BITS": "65536", 23 | "MACRO_BLOCKAGE_HALO": "0", 24 | "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl", 25 | }, 26 | # The width/height of a real SRAM might be, say, 27 | # 25% of that of a flip flop based SRAM. 28 | mock_area = 0.25, 29 | sources = { 30 | "SDC_FILE": [":constraints_darkram.sdc"], 31 | }, 32 | stage_data = { 33 | "synth": [ 34 | "//:verilog_data", 35 | "//:verilog_include", 36 | ], 37 | }, 38 | # OpenROAD version of the darkram.v file 39 | verilog_files = [":darkram.v"], 40 | ) 41 | 42 | orfs_flow( 43 | name = "darksocv", 44 | arguments = FASTER | { 45 | "SYNTH_HIERARCHICAL": "1", 46 | #"SYNTH_MINIMUM_KEEP_SIZE": "1", 47 | "CORE_UTILIZATION": "40", 48 | "MIN_ROUTING_LAYER": "M2", 49 | "MAX_ROUTING_LAYER": "M7", 50 | "CORE_MARGIN": "2", 51 | "MACRO_PLACE_HALO": "2 2", 52 | "PDN_TCL": "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl", 53 | "GDS_ALLOW_EMPTY": "darkram", 54 | }, 55 | macros = ["darkram_generate_abstract"], 56 | sources = { 57 | "SDC_FILE": [":constraints.sdc"], 58 | }, 59 | stage_data = { 60 | "synth": [ 61 | "//:verilog_data", 62 | "//:verilog_include", 63 | ], 64 | }, 65 | verilog_files = [ 66 | "//:verilog", 67 | ], 68 | ) 69 | -------------------------------------------------------------------------------- /boards/openroad/README.md: -------------------------------------------------------------------------------- 1 | OpenROAD ASAP7 PDK configuration 2 | ================================ 3 | 4 | TL;DR Install Bazelisk and run command below to build and view darksocv in the GUI, Bazelisk handles all depedencies. 5 | 6 | Demonstrates how to set up an [bazel-orfs](https://github.com/The-OpenROAD-Project/bazel-orfs) to build darksocv with [OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) 7 | 8 | To build and view [Install Bazelisk](https://bazel.build/install/bazelisk) and run: 9 | 10 | bazelisk run //boards/openroad:darksocv_cts /tmp/cts gui_cts 11 | 12 | Register to register histogram 13 | ------------------------------ 14 | 15 | ![alt text](reg2reg-histogram.png) 16 | 17 | Estimated routing congestion 18 | ---------------------------- 19 | 20 | ![alt text](routing-congestion.png) 21 | 22 | Ideas for future work 23 | ===================== 24 | 25 | - reduce clock period 26 | - darkram.v should consist of serveral SRAMs connected together to be 27 | a more accurate representation 28 | - create a mock SRAM representation with somewhat realistic timing 29 | - add IO constraints to place pins on one edge of the SRAMs and top level 30 | - reduce area 31 | 32 | [MegaBoom](https://github.com/The-OpenROAD-Project/megaboom) demonstrates a number of techniques to study a design and set up mock SRAMs. 33 | -------------------------------------------------------------------------------- /boards/openroad/constraints.sdc: -------------------------------------------------------------------------------- 1 | set clk_name XCLK 2 | set clk_port_name XCLK 3 | set clk_period 2000 4 | 5 | source $::env(PLATFORM_DIR)/constraints.sdc 6 | -------------------------------------------------------------------------------- /boards/openroad/constraints_darkram.sdc: -------------------------------------------------------------------------------- 1 | set sdc_version 2.0 2 | 3 | set clk_name CLK 4 | set clk_port_name CLK 5 | set clk_period 2000 6 | 7 | set clk_port [get_ports $clk_port_name] 8 | create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port 9 | 10 | set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] 11 | set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}] 12 | set_max_delay [expr {[info exists in2reg_max] ? $in2reg_max : 80}] -from $non_clk_inputs -to [all_registers] 13 | set_max_delay [expr {[info exists reg2out_max] ? $reg2out_max : 80}] -from $all_register_outputs -to [all_outputs] 14 | set_max_delay [expr {[info exists in2out_max] ? $in2out_max : 80}] -from $non_clk_inputs -to [all_outputs] 15 | # group_path -name in2reg -from $non_clk_inputs -to [all_registers] 16 | # group_path -name reg2out -from [all_registers] -to [all_outputs] 17 | # group_path -name in2out -from $non_clk_inputs -to [all_outputs] 18 | -------------------------------------------------------------------------------- /boards/openroad/reg2reg-histogram.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/darklife/darkriscv/b5ba4cb6c2c81ab87f025aa7bf27df438d645980/boards/openroad/reg2reg-histogram.png -------------------------------------------------------------------------------- /boards/openroad/routing-congestion.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/darklife/darkriscv/b5ba4cb6c2c81ab87f025aa7bf27df438d645980/boards/openroad/routing-congestion.png -------------------------------------------------------------------------------- /boards/papilio_duo_logicstart/README.md: -------------------------------------------------------------------------------- 1 | Papilio-DUO 2 | ============== 3 | Compact Papilio FPGA board with a Spartan6 Papilio FPGA on the top and an atmega32u4 Arduino derived design on the bottom. 4 | 5 | Features 6 | -------- 7 | * Arduino Mega Footprint 8 | * Spartan 6 FPGA 9 | * SRAM 512K-2MB 10 | * FT2232H USB 11 | * atmega32u4 AVR 12 | 13 | See also: https://github.com/GadgetFactory/Papilio-DUO 14 | -------------------------------------------------------------------------------- /boards/papilio_duo_logicstart/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/papilio_duo_logicstart/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/papilio_duo_logicstart/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/papilio_duo_logicstart/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/avnet_microboard_lx9/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc6slx9-2-csg324 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -define PAPILIO_DUO_LOGICSTART=1 54 | -------------------------------------------------------------------------------- /boards/piswords_ch34x_lx16/README.md: -------------------------------------------------------------------------------- 1 | ## PISWORDS RS485 LX9 2 | 3 | The Piswords ch34x LX16 is a very interesting chinese board that 4 | include lots of interesting features: 5 | 6 | - a XC6SLX16 FPGA w/ 256 pins (BGA) 7 | - 50MHz clock 8 | - USB/serial CH34x 9 | - 16MB SPI FLASH (M25P16) 10 | - 4 LEDs 11 | - 5 keys 12 | - lots of GPIO pins 13 | - 128-byte I2C EEPROM (I guess) 14 | - 32MB SDRAM (HY57V2562GTR) 15 | - SD CARD reader 16 | 17 | -------------------------------------------------------------------------------- /boards/piswords_rs485_lx9/README.md: -------------------------------------------------------------------------------- 1 | ## PISWORDS RS485 LX9 2 | 3 | The Piswords RS485 LX9* is a very interesting chinese board that 4 | include lots of interesting features: 5 | 6 | - a XC6SLX9 FPGA w/ 144 pins (TQFP!) 7 | - 50MHz clock 8 | - RS232 serial 9 | - RS485 serial (of course) 10 | - 16MB SPI FLASH 11 | - eigth LEDs 12 | - four keys 13 | - lots of GPIO pins 14 | - 128-byte I2C EEPROM (I guess) 15 | 16 | As observed, the main board focus in around RS485 applications, where is 17 | possible connect multiple boards in the same network and control lots of 18 | IOs. 19 | 20 | *note: the boad in fact is named "core board" or "demo board", but for some 21 | unknown reason we know this board as "rs485 board" here. 22 | -------------------------------------------------------------------------------- /boards/piswords_rs485_lx9/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/piswords_rs485_lx9/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/piswords_rs485_lx9/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | # Piswords RS485 LX9 30 | 31 | NET XCLK LOC = P55 | PERIOD = 50MHz HIGH 50%; 32 | NET XRES LOC = P44 | PULLDOWN; 33 | 34 | NET UART_RXD LOC = P47; 35 | NET UART_TXD LOC = P48; 36 | 37 | NET LED[3] LOC = P61; # LED8 38 | NET LED[2] LOC = P62; # LED7 39 | NET LED[1] LOC = P66; # LED6 40 | NET LED[0] LOC = P67; # LED5 41 | 42 | NET DEBUG[3] LOC = P112; # P2-39 43 | NET DEBUG[2] LOC = P115; # P2-37 44 | NET DEBUG[1] LOC = P117; # P2-35 45 | NET DEBUG[0] LOC = P119; # P2-33 46 | -------------------------------------------------------------------------------- /boards/piswords_rs485_lx9/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/piswords_rs485_lx9/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/piswords_rs485_lx9/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc6slx9-2-tqg144 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -define PISWORDS_RS485_LX9=1 -------------------------------------------------------------------------------- /boards/qmtech_artix7_a35/README.md: -------------------------------------------------------------------------------- 1 | ## QMTech Artix-7 A35 2 | 3 | The QMTech Artix-7 A35 is a set of carrier and core boards manufactured by 4 | QMTech and available at AliExpress. The core board is compatible with other 5 | core boards, such as the Artix-7 A100 and the Spartan-7 LX16, which is 6 | available both in DDR and SDRAM setups. As in the case of other QMTech 7 | boards, the Artix-7 A35 lacks an on-board JTAG, so a cheap Chinese JTAG 8 | adapter is also required. However, although the core board also lacks an 9 | USB/serial, the carrier board provides a cp2102, so no additional USB/serial 10 | adapter is required. Regarding the software, you will need Vivado for 11 | Windows or Lnux to build and program the FPGA. I am working here with 12 | Vivado version 2018.2 and it requires 18GB of disk space. Newer versions 13 | will probably require more, but it is possible reduce the space when you 14 | avoid the Zynq/ARM support. Although the Vivado is huge, the operation is 15 | less erratic when compared with ISE, in special regarding the USB/JTAG 16 | support. 17 | 18 | Regarding the board features, in the core board we can find: 19 | 20 | - a XC7A35 FPGA w/ 256 pins 21 | - 50MHz clock 22 | - on-board SPI FLASH 23 | - on-board DDR3 24 | - one LED 25 | - one switch (used as RESET) 26 | - lots and lots of GPIO pins that are connected to the carrier board 27 | 28 | You can find more documentation about this board here: http://www.chinaqmtech.com/download_fpga 29 | 30 | In the carrier board we can find: 31 | 32 | - USB/serial (cp2102) 33 | - GMII PHY 34 | - VGA interface w/ 12-bit DAC 35 | - five LEDs 36 | - five switches 37 | - 3-digit x 7-segment disolay 38 | - micro-SD card interface 39 | - 2x PMOD connectors 40 | - 1x digital camera connector 41 | 42 | Currently, only the USB/serial adapter is supported. 43 | 44 | Instructions: 45 | 46 | - open the darksocv.xpr in Vivado (see how to install Vivado [here](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf)) 47 | - build the FPGA bitstream (no need to build the ROM/RAM files) 48 | - open the hardware manager 49 | - connect to FPGA and program it with the generated bitstream 50 | - connect to the UART with the speed of 115200 bps 51 | - when programmed, you must see the darkriscv welcome banner 52 | -------------------------------------------------------------------------------- /boards/qmtech_artix7_a35/darksocv.xdc: -------------------------------------------------------------------------------- 1 | # QMTech Spartan-7 board 2 | 3 | set_property CFGBVS VCCO [current_design] 4 | set_property CONFIG_VOLTAGE 3.3 [current_design] 5 | 6 | set_property -dict { PACKAGE_PIN N11 IOSTANDARD LVCMOS33 } [get_ports { XCLK }]; 7 | create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports { XCLK }]; 8 | 9 | set_property -dict { PACKAGE_PIN K5 IOSTANDARD LVCMOS33 } [get_ports { XRES }]; 10 | 11 | set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD }]; 12 | set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }]; 13 | 14 | set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; 15 | set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; 16 | set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; 17 | set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; 18 | 19 | set_property -dict { PACKAGE_PIN N4 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[3] }]; 20 | set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[2] }]; 21 | set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[1] }]; 22 | set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[0] }]; 23 | -------------------------------------------------------------------------------- /boards/qmtech_cyclone10_cl016/darksocv.csv: -------------------------------------------------------------------------------- 1 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions 3 | # and other software and tools, and any partner logic 4 | # functions, and any output files from any of the foregoing 5 | # (including device programming or simulation files), and any 6 | # associated documentation or information are expressly subject 7 | # to the terms and conditions of the Intel Program License 8 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | # the Intel FPGA IP License Agreement, or other applicable license 10 | # agreement, including, without limitation, that your use is for 11 | # the sole purpose of programming logic devices manufactured by 12 | # Intel and sold by Intel or its authorized distributors. Please 13 | # refer to the applicable agreement for further details, at 14 | # https://fpgasoftware.intel.com/eula. 15 | 16 | # Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 17 | # File: C:\Verilog\darkriscv\CURRENT\boards\qmtech_cyclone10_cl016\darksocv.csv 18 | # Generated on: Mon Aug 07 16:19:15 2023 19 | 20 | # Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software. 21 | 22 | To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation 23 | DEBUG[3],Output,PIN_AA18,4,B4_N0,PIN_E4,,,,,, 24 | DEBUG[2],Output,PIN_AB19,4,B4_N0,PIN_K7,,,,,, 25 | DEBUG[1],Output,PIN_U20,5,B5_N1,PIN_G5,,,,,, 26 | DEBUG[0],Output,PIN_R19,5,B5_N0,PIN_J7,,,,,, 27 | LED[3],Output,PIN_AA19,4,B4_N0,PIN_B1,,,,,, 28 | LED[2],Output,PIN_W19,5,B5_N1,PIN_K8,,,,,, 29 | LED[1],Output,PIN_Y17,4,B4_N0,PIN_B2,,,,,, 30 | LED[0],Output,PIN_W17,4,B4_N0,PIN_L8,,,,,, 31 | UART_RXD,Input,PIN_AA22,5,B5_N1,PIN_D2,,,,,, 32 | UART_TXD,Output,PIN_AA21,5,B5_N1,PIN_H5,,,,,, 33 | XCLK,Input,PIN_G1,1,B1_N1,PIN_G2,,,,,, 34 | XRES,Input,PIN_P3,2,B2_N0,PIN_E3,,,,,, 35 | -------------------------------------------------------------------------------- /boards/qmtech_cyclone10_cl016/darksocv.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition 22 | # Date created = 15:26:43 August 07, 2023 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.1" 27 | DATE = "15:26:43 August 07, 2023" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "darksocv" 32 | -------------------------------------------------------------------------------- /boards/qmtech_kintex7_k325/README.md: -------------------------------------------------------------------------------- 1 | ## QMTech Kintex-7 K325 2 | 3 | The QMTech Kintex-7 K325 is a set of carrier and core boards manufactured by 4 | QMTech and available at AliExpress. The core board is compatible with other 5 | core boards, such as the Kintex-7 A100 and the Spartan-7 LX16, which is 6 | available both in DDR and SDRAM setups. As in the case of other QMTech 7 | boards, the Kintex-7 K325 lacks an on-board JTAG, so a cheap Chinese JTAG 8 | adapter is also required. However, although the core board also lacks an 9 | USB/serial, the carrier board provides a cp2102, so no additional USB/serial 10 | adapter is required. 11 | 12 | Regarding the software, you will need ISE 14.7 or Vivado for Windows or 13 | Linux to build and program the FPGA. Also, you will need a temporary 30-day 14 | licence in order to generate binaries to this FPGA (the default webpack free 15 | versions does not support this device). 16 | 17 | Regarding the board features, in the core board we can find: 18 | 19 | - a XC7K325 FPGA w/ 676 pins 20 | - 50MHz clock 21 | - on-board SPI FLASH 22 | - on-board DDR3 23 | - one LED 24 | - one switch (used as RESET) 25 | - lots and lots of GPIO pins that are connected to the carrier board 26 | 27 | You can find more documentation about this board here: 28 | 29 | - K325T core board: https://github.com/ChinaQMTECH/QMTECH_XC7K325T_CORE_BOARD 30 | - carrier board manual: https://github.com/ChinaQMTECH/QM_XC7A35T_DDR3/blob/master/QMTECH_Artix-7_XC7A35T_User_Manual(DaughterBoard)-V02.pdf 31 | - carrier board schematic: https://github.com/ChinaQMTECH/QM_XC7A35T_DDR3/blob/master/Hardware/DB-FPGA-XC7A35T-DDR3-V03.pdf 32 | 33 | In the carrier board we can find: 34 | 35 | - USB/serial (cp2102) 36 | - GMII PHY 37 | - VGA interface w/ 12-bit DAC 38 | - five LEDs 39 | - five switches 40 | - 3-digit x 7-segment disolay 41 | - micro-SD card interface 42 | - 2x PMOD connectors 43 | - 1x digital camera connector 44 | 45 | Currently, only the USB/serial adapter is supported. 46 | -------------------------------------------------------------------------------- /boards/qmtech_kintex7_k325/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/qmtech_kintex7_k325/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/qmtech_kintex7_k325/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | #NET "CLK" TNM_NET = CLK; 30 | 31 | # without cache controller 32 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 33 | 34 | # with cache controller 35 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 36 | 37 | # QMtech K325 board 38 | 39 | NET XCLK LOC = F22 | IOSTANDARD = LVCMOS33 | PERIOD = 50MHz HIGH 50%; 40 | #NET XCLK LOC = K15 | PERIOD = 66MHz HIGH 50%; 41 | #NET XCLK LOC = V10 | PERIOD = 40MHz HIGH 50%; 42 | 43 | NET XRES LOC = AF9 | IOSTANDARD = LVCMOS18 | PULLDOWN; 44 | 45 | NET UART_RXD LOC = B12 | IOSTANDARD = LVCMOS33 | PULLUP; # DBJ2-16 -> U5-16 B12 46 | NET UART_TXD LOC = B11 | IOSTANDARD = LVCMOS33; # DBJ2-15 -> U5-15 B11 47 | 48 | NET LED[3] LOC = U25 | IOSTANDARD = LVCMOS33; # U4 49 | NET LED[2] LOC = T23 | IOSTANDARD = LVCMOS33; # U4 50 | NET LED[1] LOC = H26 | IOSTANDARD = LVCMOS33; 51 | NET LED[0] LOC = J26 | IOSTANDARD = LVCMOS33; 52 | 53 | NET DEBUG[3] LOC = R23 | IOSTANDARD = LVCMOS33; # U4 54 | NET DEBUG[2] LOC = P25 | IOSTANDARD = LVCMOS33; # U4 55 | NET DEBUG[1] LOC = N23 | IOSTANDARD = LVCMOS33; # U4 56 | NET DEBUG[0] LOC = M26 | IOSTANDARD = LVCMOS33; # U4 57 | 58 | 59 | -------------------------------------------------------------------------------- /boards/qmtech_kintex7_k325/darksocv.ut: -------------------------------------------------------------------------------- 1 | -g UnconstrainedPins:Allow 2 | -w 3 | -g DebugBitstream:No 4 | -g Binary:no 5 | -g CRC:Enable 6 | -g ConfigRate:3 7 | -g CclkPin:PullUp 8 | -g M0Pin:PullUp 9 | -g M1Pin:PullUp 10 | -g M2Pin:PullUp 11 | -g ProgPin:PullUp 12 | -g InitPin:Pullup 13 | -g TckPin:PullUp 14 | -g TdiPin:PullUp 15 | -g TdoPin:PullUp 16 | -g TmsPin:PullUp 17 | -g Disable_JTAG:No 18 | -g UnusedPin:PullDown 19 | -g UserID:0xFFFFFFFF 20 | -g ExtMasterCclk_en:Disable 21 | -g ConfigFallback:Disable 22 | -g BPI_page_size:1 23 | -g BPI_sync_mode:Disable 24 | -g SPI_32bit_addr:No 25 | -g SPI_buswidth:1 26 | -g SPI_Fall_Edge:No 27 | -g OverTempPowerDown:Disable 28 | -g USR_ACCESS:None 29 | -g JTAG_XADC:Enable 30 | -g DCIUpdateMode:AsRequired 31 | -g StartUpClk:CClk 32 | -g DONE_cycle:4 33 | -g GTS_cycle:5 34 | -g GWE_cycle:6 35 | -g Match_cycle:Auto 36 | -g Security:None 37 | -g ICAP_select:Auto 38 | -g DonePipe:Yes 39 | -g Encrypt:No 40 | -------------------------------------------------------------------------------- /boards/qmtech_kintex7_k325/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/qmtech_kintex7_k325/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc7k325t-2-ffg676 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 2 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing Yes 46 | -move_first_stage YES 47 | -move_last_stage YES 48 | -optimize_primitives NO 49 | -use_clock_enable Auto 50 | -use_sync_set Auto 51 | -use_sync_reset Auto 52 | -iob Auto 53 | -equivalent_register_removal YES 54 | -slice_utilization_ratio_maxmargin 5 55 | -define QMTECH_KINTEX7_K325=1 -------------------------------------------------------------------------------- /boards/qmtech_sdram_lx16/README.md: -------------------------------------------------------------------------------- 1 | ## QMTech SDRAM LX16 2 | 3 | Although the QMTech SDRAM LX16 lacks on-board JTAG and USB/serial, it is a 4 | very cheap and interesting board. In fact, is so cheap that is possible buy 5 | lots of boards and connect them via high-speed links! :) 6 | 7 | With an external Xilinx JTAG cable and an external USB/serial converter, the 8 | board works very well and provides lots of IO pins. 9 | 10 | The board includes: 11 | 12 | - a XC6SLX16 FPGA w/ 256 pins 13 | - 50MHz clock 14 | - on-board SPI FLASH 15 | - on-board SDRAM (classical MT48LC16M16A2 16 | - two LEDs 17 | - lots and lots of GPIO pins 18 | 19 | As long the QMTech SDRAM LX16 is compatible with the QMTech development kit 20 | based in the Artix-7, I managed to adapt the board and use the same 21 | peripherals: 22 | 23 | - USB/serial 24 | - GMII PHY 25 | - VGA interface 26 | - more LEDs 27 | - more switchs 28 | - more GPIOs 29 | 30 | Currently, only the USB/serial adapter is supported. 31 | 32 | 33 | -------------------------------------------------------------------------------- /boards/qmtech_sdram_lx16/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/qmtech_sdram_lx16/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/qmtech_sdram_lx16/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | # QMtech SDRAM/LX16 board 30 | 31 | NET XCLK LOC = A10 | PERIOD = 50MHz HIGH 50%; 32 | NET XRES LOC = T8 | PULLUP; 33 | 34 | NET LED[3] LOC = B12; 35 | NET LED[2] LOC = C11; 36 | NET LED[1] LOC = T9; # board led 37 | NET LED[0] LOC = R9; # board led 38 | 39 | # QMtech expansion board -> connector -> SDRAM/LX16 board 40 | 41 | NET UART_RXD LOC = E16; # F22 -> J2-15 -> E15 42 | NET UART_TXD LOC = E15; # G22 -> J2-16 -> E16 43 | 44 | NET DEBUG[3] LOC = L14; # P23 -> J2-40 -> L14 45 | NET DEBUG[2] LOC = L16; # P24 -> J2-39 -> L16 46 | NET DEBUG[1] LOC = K16; # N21 -> J2-38 -> K16 47 | NET DEBUG[0] LOC = K15; # N22 -> J2-37 -> K15 48 | -------------------------------------------------------------------------------- /boards/qmtech_sdram_lx16/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/qmtech_sdram_lx16/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/qmtech_sdram_lx16/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc6slx16-2-ftg256 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -define QMTECH_SDRAM_LX16=1 -------------------------------------------------------------------------------- /boards/qmtech_spartan7_s15/darksocv.xdc: -------------------------------------------------------------------------------- 1 | # QMTech Spartan-7 board 2 | 3 | set_property CFGBVS VCCO [current_design] 4 | set_property CONFIG_VOLTAGE 3.3 [current_design] 5 | 6 | set_property -dict { PACKAGE_PIN H11 IOSTANDARD LVCMOS33 } [get_ports { XCLK }]; 7 | create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports { XCLK }]; 8 | 9 | set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { XRES }]; 10 | 11 | set_property -dict { PACKAGE_PIN N4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD }]; 12 | set_property -dict { PACKAGE_PIN P5 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }]; 13 | 14 | set_property -dict { PACKAGE_PIN E4 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; 15 | set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; 16 | set_property -dict { PACKAGE_PIN L5 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; 17 | set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; 18 | 19 | set_property -dict { PACKAGE_PIN B5 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[3] }]; 20 | set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[2] }]; 21 | set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[1] }]; 22 | set_property -dict { PACKAGE_PIN A2 IOSTANDARD LVCMOS33 } [get_ports { DEBUG[0] }]; 23 | -------------------------------------------------------------------------------- /boards/scarab_minispartan6-plus_lx9/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/scarab_minispartan6-plus_lx9/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/scarab_minispartan6-plus_lx9/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | #NET "CLK" TNM_NET = CLK; 30 | 31 | # without cache controller 32 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 33 | 34 | # with cache controller 35 | #TIMESPEC TS_CLK = PERIOD "CLK" 75MHz HIGH 50%; 36 | 37 | # AVNET board LX9 microboard 38 | 39 | NET XCLK LOC = K3 | PERIOD = 50MHz HIGH 50%; 40 | 41 | NET XRES LOC = P12 | PULLDOWN; # PORTC10 42 | 43 | NET UART_RXD LOC = M7; 44 | NET UART_TXD LOC = N6; 45 | 46 | NET LED[3] LOC = P9; 47 | NET LED[2] LOC = M9; 48 | NET LED[1] LOC = N9; 49 | NET LED[0] LOC = P11; 50 | 51 | NET DEBUG[3] LOC = L14; # PORTC3 52 | NET DEBUG[2] LOC = K14; # PORTC2 53 | NET DEBUG[1] LOC = J12; # PORTC1 54 | NET DEBUG[0] LOC = J13; # PORTC0 55 | -------------------------------------------------------------------------------- /boards/scarab_minispartan6-plus_lx9/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | -g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | -g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | -g en_sw_gsr:No 27 | -g drive_awake:No 28 | -g sw_clk:Startupclk 29 | -g sw_gwe_cycle:5 30 | -g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/scarab_minispartan6-plus_lx9/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/scarab_minispartan6-plus_lx9/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc6slx9-3-ftg256 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -define SCARAB_MINISPARTAN6_PLUS_LX9=1 54 | -------------------------------------------------------------------------------- /boards/ulx3s/README.md: -------------------------------------------------------------------------------- 1 | Just use yosys/nextpnr-ecp5 2 | --------------------------- 3 | 4 | download toolchain from https://github.com/YosysHQ/oss-cad-suite-build/releases 5 | You can change the frequency with the pll_ref_25MHz.v (accepted fmax hardwired). 6 | Use config.vh to adjust fmax via BOARD_CK. 7 | -------------------------------------------------------------------------------- /boards/ulx3s/build.sh: -------------------------------------------------------------------------------- 1 | rm -f darksocv.cfg darksocv.json 2 | yosys -D __YOSYS__ -D LATTICE_ECP5_ULX3S -p "synth_ecp5 -json darksocv.json -top darksocv" ../../rtl/darksocv.v ../../rtl/darkriscv.v ../../rtl/darkuart.v pll_ref_25MHz.v 3 | nextpnr-ecp5 --timing-allow-fail --json darksocv.json --textcfg darksocv.cfg --85k --package CABGA381 --speed 6 --lpf darksocv.lpf 4 | ecppack --compress --input darksocv.cfg --bit darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/ulx3s/darksocv.lpf: -------------------------------------------------------------------------------- 1 | BLOCK RESETPATHS; 2 | BLOCK ASYNCPATHS; 3 | SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE; 4 | #i5-v6.0 5 | LOCATE COMP "XCLK" SITE "G2"; 6 | IOBUF PORT "XCLK" PULLMODE=NONE IO_TYPE=LVCMOS33; 7 | FREQUENCY PORT "XCLK" 25 MHZ; 8 | ## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) 9 | # on PCB v1.7 shutdown is not connected to FPGA 10 | LOCATE COMP "XRES" SITE "D6"; # FPGA receives 11 | IOBUF PORT "XRES" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 12 | LOCATE COMP "UART_TXD" SITE "L4"; # FPGA transmits to ftdi 13 | IOBUF PORT "UART_TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 14 | LOCATE COMP "UART_RXD" SITE "M1"; # FPGA received to ftdi 15 | IOBUF PORT "UART_RXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 16 | # 17 | ## upper 18 | LOCATE COMP "LED[0]" SITE "D2"; 19 | LOCATE COMP "LED[1]" SITE "C1"; 20 | LOCATE COMP "LED[2]" SITE "C2"; 21 | LOCATE COMP "LED[3]" SITE "B2"; 22 | 23 | ## bottom 24 | LOCATE COMP "DEBUG[0]" SITE "D1"; 25 | LOCATE COMP "DEBUG[1]" SITE "E2"; 26 | LOCATE COMP "DEBUG[2]" SITE "E1"; 27 | LOCATE COMP "DEBUG[3]" SITE "H3"; 28 | 29 | # if you use spi bitbang, just remove PULLMODE=UP from property 30 | IOBUF PORT "LED[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 31 | IOBUF PORT "LED[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 32 | IOBUF PORT "LED[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 33 | IOBUF PORT "LED[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 34 | IOBUF PORT "DEBUG[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 35 | IOBUF PORT "DEBUG[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 36 | IOBUF PORT "DEBUG[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 37 | IOBUF PORT "DEBUG[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; 38 | 39 | 40 | ## PROGRAMN (reload bitstream from FLASH, exit from bootloader) 41 | # PCB v2.0.5 and higher 42 | LOCATE COMP "user_programn" SITE "M4"; 43 | IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; 44 | ## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5) 45 | # on PCB v1.7 shutdown is not connected to FPGA 46 | LOCATE COMP "shutdown" SITE "G16"; # FPGA receives 47 | IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; 48 | 49 | -------------------------------------------------------------------------------- /boards/ulx3s/upload.sh: -------------------------------------------------------------------------------- 1 | # sram config 2 | openFPGALoader --board=ulx3s darksocv.bit 3 | # flash config 4 | #openFPGALoader -f --board=ulx3s darksocv.bit 5 | -------------------------------------------------------------------------------- /boards/xilinx_ac701_a200/README.md: -------------------------------------------------------------------------------- 1 | ## Xilinx AC701 A200 2 | 3 | The AC701 from Xilinx is a very complete and expensive board based in the 4 | Artix-7 A200. Unfortunately, the board was not mine and I borrowed from a 5 | friend for a short time only in order to make a quick test, in a way that 6 | the DarkRISCV worked at 90MHz in the board. Later, after the board was 7 | already returned, I made a better clock scheme in order to generate 180MHz 8 | and the image was built w/ a timing score zero, which means that the build 9 | is probably working, althrough there is no way to test it at this moment. 10 | 11 | The board includes: 12 | 13 | - a XC7A200 FPGA w/ 676 pins 14 | - lots of clock references, but I found only the 90MHz clock 15 | - on-board SPI FLASH 16 | - on-board DDR3 17 | - on-board 1Gbps PHY 18 | - lots and lots of other features! 19 | -------------------------------------------------------------------------------- /boards/xilinx_ac701_a200/darksocv.imp: -------------------------------------------------------------------------------- 1 | setMode -bs 2 | setCable -port auto 3 | Identify -inferir 4 | identifyMPM 5 | assignFile -p 1 -file "../tmp/darksocv.bit" 6 | Program -p 1 7 | quit 8 | -------------------------------------------------------------------------------- /boards/xilinx_ac701_a200/darksocv.prj: -------------------------------------------------------------------------------- 1 | verilog work "../rtl/darkriscv.v" 2 | verilog work "../rtl/darksocv.v" 3 | verilog work "../rtl/darkuart.v" 4 | -------------------------------------------------------------------------------- /boards/xilinx_ac701_a200/darksocv.ucf: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | NET XCLK LOC = P16 | IOSTANDARD = LVCMOS33 | PERIOD = 90MHz HIGH 50%; 30 | NET XCLK CLOCK_DEDICATED_ROUTE = FALSE; 31 | 32 | #NET XCLKP LOC = M21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | PERIOD = 156.25MHz HIGH 50%; 33 | #NET XCLKN LOC = M22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | PERIOD = 156.25MHz HIGH 50%; 34 | 35 | NET XRES LOC = U4 | IOSTANDARD = SSTL15 | PULLDOWN; 36 | 37 | NET UART_RXD LOC = T19 | IOSTANDARD = LVCMOS18; 38 | NET UART_TXD LOC = U19 | IOSTANDARD = LVCMOS18; 39 | 40 | NET LED[3] LOC = R26 | IOSTANDARD = LVCMOS33; 41 | NET LED[2] LOC = T25 | IOSTANDARD = LVCMOS33; 42 | NET LED[1] LOC = T24 | IOSTANDARD = LVCMOS33; 43 | NET LED[0] LOC = M26 | IOSTANDARD = LVCMOS33; 44 | 45 | NET DEBUG[3] LOC = T23 | IOSTANDARD = LVCMOS33; # J48-1 46 | NET DEBUG[2] LOC = R22 | IOSTANDARD = LVCMOS33; # J48-2 47 | NET DEBUG[1] LOC = T22 | IOSTANDARD = LVCMOS33; # J48-3 48 | NET DEBUG[0] LOC = P26 | IOSTANDARD = LVCMOS33; # J48-4 49 | -------------------------------------------------------------------------------- /boards/xilinx_ac701_a200/darksocv.ut: -------------------------------------------------------------------------------- 1 | -w 2 | -g DebugBitstream:No 3 | -g Binary:no 4 | -g CRC:Enable 5 | #-g Reset_on_err:No 6 | #-g ConfigRate:2 7 | -g ProgPin:PullUp 8 | -g TckPin:PullUp 9 | -g TdiPin:PullUp 10 | -g TdoPin:PullUp 11 | -g TmsPin:PullUp 12 | -g UnusedPin:PullDown 13 | -g UserID:0xFFFFFFFF 14 | #-g ExtMasterCclk_en:No 15 | -g SPI_buswidth:1 16 | -g TIMER_CFG:0xFFFF 17 | #-g multipin_wakeup:No 18 | -g StartUpClk:CClk 19 | -g DONE_cycle:4 20 | -g GTS_cycle:5 21 | -g GWE_cycle:6 22 | -g LCK_cycle:NoWait 23 | -g Security:None 24 | -g DonePipe:Yes 25 | -g DriveDone:No 26 | #-g en_sw_gsr:No 27 | #-g drive_awake:No 28 | #-g sw_clk:Startupclk 29 | #-g sw_gwe_cycle:5 30 | #-g sw_gts_cycle:4 31 | -------------------------------------------------------------------------------- /boards/xilinx_ac701_a200/darksocv.xst: -------------------------------------------------------------------------------- 1 | set -tmpdir "../tmp" 2 | set -xsthdpdir "../tmp/" 3 | run 4 | -ifn ../boards/xilinx_ac701_a200/darksocv.prj 5 | -ofn darksocv 6 | -ofmt NGC 7 | -p xc7a200t-2-fbg676 8 | -top darksocv 9 | -opt_mode Speed 10 | -opt_level 1 11 | -power NO 12 | -iuc NO 13 | -keep_hierarchy No 14 | -netlist_hierarchy As_Optimized 15 | -rtlview Yes 16 | -glob_opt AllClockNets 17 | -read_cores YES 18 | -write_timing_constraints NO 19 | -cross_clock_analysis NO 20 | -hierarchy_separator / 21 | -bus_delimiter <> 22 | -case Maintain 23 | -slice_utilization_ratio 100 24 | -bram_utilization_ratio 100 25 | -dsp_utilization_ratio 100 26 | -lc Auto 27 | -reduce_control_sets Auto 28 | -fsm_extract YES -fsm_encoding Auto 29 | -safe_implementation No 30 | -fsm_style LUT 31 | -ram_extract Yes 32 | -ram_style Auto 33 | -rom_extract Yes 34 | -shreg_extract YES 35 | -rom_style Auto 36 | -auto_bram_packing NO 37 | -resource_sharing YES 38 | -async_to_sync NO 39 | -shreg_min_size 2 40 | -use_dsp48 Auto 41 | -iobuf YES 42 | -max_fanout 100000 43 | -bufg 16 44 | -register_duplication YES 45 | -register_balancing No 46 | -optimize_primitives NO 47 | -use_clock_enable Auto 48 | -use_sync_set Auto 49 | -use_sync_reset Auto 50 | -iob Auto 51 | -equivalent_register_removal YES 52 | -slice_utilization_ratio_maxmargin 5 53 | -define XILINX_AC701_A200=1 54 | -------------------------------------------------------------------------------- /doc/boot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/darklife/darkriscv/b5ba4cb6c2c81ab87f025aa7bf27df438d645980/doc/boot.png -------------------------------------------------------------------------------- /doc/darkriscv.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/darklife/darkriscv/b5ba4cb6c2c81ab87f025aa7bf27df438d645980/doc/darkriscv.png -------------------------------------------------------------------------------- /doc/darksocv.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/darklife/darkriscv/b5ba4cb6c2c81ab87f025aa7bf27df438d645980/doc/darksocv.png -------------------------------------------------------------------------------- /sim/README.md: -------------------------------------------------------------------------------- 1 | # Simulation 2 | 3 | This directory provides support for simulation tools. 4 | 5 | ## Icarus Verilog / GTKWave 6 | The main simulation tool is the opensource tools `Icarus Verilog` and `GTKWave`.\ 7 | Alternatively, it is possible to use proprietary simulation tools, as 8 | the Xilinx ISIM and ModelSIM. 9 | 10 | TODO: simulation models for external peripherals, such as the DarkUART. 11 | 12 | ## Verilator / Cosimulation 13 | As an alternative to Icarus Verilog, `Verilator` + `ImGui` (and/or gtkwave) can be used, 14 | offering some kind of cosimulation with C/C++ modules, than can be useful 15 | eg: for interactive simulations.\ 16 | Also it is sometimes beneficial to be able to compile RTL with different (open-source) simulators. 17 | 18 | Prerequisites: Install verilator, sdl2, glew, glfw and imgui (built with sdl2 & opengl3 backends). 19 | 20 | The `spidemo` has some preliminary Verilator support: 21 | ```shell 22 | make clean all APPLICATION=spidemo NOBANNER=1 SPIBB=1 COSIM=1 23 | ``` 24 | This runs the spidemo with both HW and Bit-banging SPI master, with Verilator + ImGui.\ 25 | The banner is removed here because serial accesses are really slow in such cosimulation.\ 26 | Note that the overall performance in cosimulation is not as good as expected, for now. 27 | -------------------------------------------------------------------------------- /sim/cosim.mk: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2025, Nicolas Sauzede 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | ## Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | ## Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | ## Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | VLATOR:=verilator 30 | ifneq (0, $(shell command -v $(VALGRIND) > /dev/null 2>&1 ; echo $$?)) 31 | VLATOR:= 32 | endif 33 | 34 | ifdef VLATOR 35 | DUT?=dut 36 | VDUT=V$(DUT) 37 | V_SRC=$(COSIM_SRC) 38 | GUI_C_SRC:=$(VDUT)_gui.cpp 39 | GUI_VCD_FILE:=$(VDUT)_gui.vcd 40 | GUI_CFLAGS:=-I/usr/include/imgui `sdl2-config --cflags` 41 | GUI_LDFLAGS:=`sdl2-config --libs` -lGLEW -lGL -limgui -O3 42 | VOPT+=--trace 43 | #VOPT+=--timing 44 | #VOPT+=--timing 45 | VOPT+=-Wno-PINMISSING 46 | VOPT+=-Wno-WIDTHTRUNC 47 | VOPT+=-Wno-WIDTHEXPAND 48 | VOPT+=-Wno-CASEX 49 | VOPT+=-Wno-CASEINCOMPLETE 50 | VOPT+=-Wno-REALCVT 51 | VOPT+=-O3 -CFLAGS "-O3" --x-assign fast --x-initial fast --noassert --Wno-MULTIDRIVEN 52 | CC_OPT := -O3 53 | TOP_MODULE=--top-module $(DUT) 54 | GUI_DIR=tmp_gui 55 | VOUT:=./$(GUI_DIR)/$(VDUT).cpp 56 | 57 | %.cosim: ./$(GUI_DIR)/$(VDUT) 58 | # echo "COSIM!!!! STEM=$* TGT=$^" 59 | ./$^ 60 | 61 | $(GUI_DIR)/%: $(COSIM_RTLS) 62 | # echo "VLATOR!!!! STEM=$* TGT=$@" 63 | $(VLATOR) -cc $(VOPT) -LDFLAGS "$(GUI_LDFLAGS) " --Mdir $(@D) -exe $(TOP_MODULE) -CFLAGS $(GUI_CFLAGS) $(V_SRC) $(GUI_C_SRC) -O3 64 | 65 | #./$(GUI_DIR)/$(VDUT): $(GUI_C_SRC) 66 | ./$(GUI_DIR)/$(VDUT): $(VOUT) $(GUI_DIR)/$(GUI_C_SRC) 67 | # echo "MAKE!!!! STEM=$* TGT=$@" 68 | (cd $(GUI_DIR); make -f $(VDUT).mk CFLAGS=-O3 LDFLAGS=-O3 CXXFLAGS="-O3 -DVCD_FILE='\"$(GUI_VCD_FILE)\"'") 69 | endif 70 | -------------------------------------------------------------------------------- /src/.gitattributes: -------------------------------------------------------------------------------- 1 | * linguist-detectable=false 2 | -------------------------------------------------------------------------------- /src/.gitignore: -------------------------------------------------------------------------------- 1 | *.s 2 | *.o 3 | darksocv.* 4 | coremark.* -------------------------------------------------------------------------------- /src/README.md: -------------------------------------------------------------------------------- 1 | ## DarkRISCV Application 2 | 3 | - darklibc: DarkRISCV C librarys 4 | - darksocv: DarkRISCV test code 5 | - coremark: CoreMark benchmark in DarkRISCV 6 | 7 | **For different applications, you need to modify the MLEN in `../rtl/config.vh`** -------------------------------------------------------------------------------- /src/badapple/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | PROJ = badapple 32 | OBJS = main.o 33 | ASMS = main.s 34 | SRCS = main.c 35 | 36 | 37 | DEPS = $(SRCS) $(ASMS) $(OBJS) $(LIBS) # $(PROJ).ld $(PROJ).lds $(DARKLIBC)/darklibc.a 38 | 39 | TARGETS = $(PROJ).a 40 | 41 | .PHONY: all 42 | 43 | all: $(TARGETS) $(DEPS) 44 | @echo sources ok for $(TARGETS). 45 | 46 | clean: 47 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} $(PROJ)_uart.bin 48 | 49 | %.o: %.s Makefile 50 | $(AS) $(ASFLAGS) -c $< -o $@ 51 | 52 | %.s: %.c Makefile 53 | $(CC) $(CFLAGS) -S $< -o $@ 54 | 55 | $(PROJ).a: $(OBJS) Makefile 56 | $(AR) $(ARFLAGS) $@ $(OBJS) 57 | $(RL) $@ 58 | 59 | $(PROJ).x86: $(SRCS) 60 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 61 | @echo x86 ok. 62 | -------------------------------------------------------------------------------- /src/coremark/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | DFLAGS_STR = -DFLAGS_STR=\""-O2 -DPERFORMANCE_RUN=1"\" 32 | 33 | CFLAGS += -I. -I./src $(DFLAGS_STR) -DITERATIONS=4000 -DPERFORMANCE_RUN=1 34 | 35 | PROJ = coremark 36 | OBJS = ./src/core_main.o ./src/core_matrix.o ./src/core_list_join.o ./src/core_state.o ./src/core_util.o core_portme.o ee_printf.o 37 | ASMS = ./src/core_main.s ./src/core_matrix.s ./src/core_list_join.s ./src/core_state.s ./src/core_util.s core_portme.s ee_printf.s 38 | SRCS = ./src/core_main.c ./src/core_matrix.c ./src/core_list_join.c ./src/core_state.c ./src/core_util.c core_portme.c ee_printf.c 39 | 40 | DEPS = $(SRCS) $(ASMS) $(OBJS) Makefile 41 | 42 | TARGETS = $(PROJ).a 43 | 44 | .PHONY: all 45 | 46 | all: $(TARGETS) $(DEPS) 47 | @echo sources ok. 48 | 49 | clean: 50 | -rm -f $(ASMS) $(OBJS) $(PROJ).{a,S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,ram.mem,rom.mem} 51 | 52 | %.o: %.s Makefile 53 | $(AS) $(ASFLAGS) -c $< -o $@ 54 | 55 | %.s: %.c Makefile 56 | $(CC) $(CFLAGS) -S $< -o $@ 57 | 58 | $(PROJ).a: $(OBJS) Makefile 59 | $(AR) $(ARFLAGS) $@ $(OBJS) 60 | #$(RL) $@ 61 | 62 | $(PROJ).x86: $(SRCS) 63 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 64 | @echo x86 ok. 65 | -------------------------------------------------------------------------------- /src/darklibc/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | CFLAGS += -Iinclude 32 | 33 | PROJ = darklibc 34 | OBJS = stdio.o io.o string.o misc.o unistd.o util.o #small.o # start.o 35 | ASMS = stdio.s io.s string.s misc.s unistd.s 36 | SRCS = stdio.c io.c string.c misc.c unistd.c util.S #small.s # start.s 37 | 38 | DEPS = $(SRCS) $(ASMS) $(OBJS) 39 | 40 | TARGETS = $(PROJ).a 41 | 42 | .PHONY: all 43 | 44 | all: $(DEPS) $(TARGETS) 45 | @echo sources ok for $(TARGETS). 46 | 47 | clean: 48 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} 49 | 50 | %.o: %.s Makefile 51 | $(AS) $(ASFLAGS) -c $< -o $@ 52 | 53 | %.s: %.c Makefile 54 | $(CC) $(CFLAGS) -S $< -o $@ 55 | 56 | %.a: $(OBJS) Makefile 57 | $(AR) $(ARFLAGS) $@ $(OBJS) 58 | $(RL) $@ 59 | -------------------------------------------------------------------------------- /src/darklibc/include/math.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __MATH__ 32 | #define __MATH__ 33 | 34 | int mac(int,short,short); 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /src/darklibc/include/stddef.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __STDDEF__ 32 | #define __STDDEF__ 33 | 34 | typedef unsigned int size_t; 35 | #define EOF -1 36 | #define NUL 0 37 | #define NULL (void *)0 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /src/darklibc/include/stdint.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __STDINT__ 32 | #define __STDINT__ 33 | 34 | typedef int int32_t; 35 | typedef short int16_t; 36 | typedef char int8_t; 37 | 38 | typedef unsigned int uint32_t; 39 | typedef unsigned short uint16_t; 40 | typedef unsigned char uint8_t; 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /src/darklibc/include/stdio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __STDIO__ 32 | #define __STDIO__ 33 | 34 | #include 35 | 36 | int getchar(void); 37 | int putchar(int c); 38 | char *gets(char *p,int s); 39 | void putstr(char *p); 40 | int puts(char *p); 41 | int printf(char *fmt,...); 42 | void putx(unsigned); 43 | void putd(int); 44 | int atoi(char *); 45 | int xtoi(char *); 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /src/darklibc/include/string.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __STRING__ 32 | #define __STRING__ 33 | 34 | char *strcpy(char *s1, char *s2); 35 | char *strncpy(char *s1, char *s2, int len); 36 | 37 | int strcmp(char *s1, char *s2); 38 | int strncmp(char *s1, char *s2, int len); 39 | int strlen(char *s1); 40 | 41 | char *memcpy(char *dptr,char *sptr,int len); 42 | char *memcmp(char *dptr,char *sptr,int len); 43 | char *memset(char *dptr, int c, int len); 44 | char *strtok(char *str,char *dptr); 45 | 46 | #endif 47 | -------------------------------------------------------------------------------- /src/darklibc/include/time.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __TIMEH__ 32 | #define __TIMEH__ 33 | 34 | #define CLOCKS_PER_SEC 1000000 35 | 36 | typedef unsigned int clock_t; 37 | typedef unsigned int time_t; 38 | 39 | struct timeval 40 | { 41 | time_t tv_sec; 42 | clock_t tv_usec; 43 | }; 44 | 45 | time_t time(time_t *); 46 | clock_t clock(); 47 | 48 | int gettimeofday(struct timeval *); 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /src/darklibc/include/unistd.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #ifndef __UNISTD__ 32 | #define __UNISTD__ 33 | 34 | void usleep(int); 35 | 36 | #endif 37 | -------------------------------------------------------------------------------- /src/darklibc/unistd.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018, Marcelo Samsoniuk 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * * Redistributions of source code must retain the above copyright notice, this 9 | * list of conditions and the following disclaimer. 10 | * 11 | * * Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * * Neither the name of the copyright holder nor the names of its 16 | * contributors may be used to endorse or promote products derived from 17 | * this software without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | #include 32 | #include 33 | 34 | // time management 35 | 36 | void usleep(int delay) 37 | { 38 | clock_t t = clock() + delay; 39 | 40 | while(clock():/) PTR=$2 18 | else 19 | if($0~/:/) DB[PTR]++ 20 | } END { 21 | for(i in DB) print DB[i],i 22 | }' src/darksocv.lst | sort -nr 23 | 24 | The script will calculate how many instructions each funcion needs and will 25 | print and sort it, producing something like this: 26 | 27 | 456
: 28 | 149 : 29 | 95 : 30 | 62 : 31 | 62 : 32 | 59 : 33 | 47 : 34 | 42 : 35 | ... 36 | 37 | So, with those information, is possible try optimize better the large 38 | funcions. 39 | 40 | TODO: 41 | 42 | - add a gdb-stub in order to support UART debug 43 | - add a SREC decoder in order to support application upload via UART 44 | - split the "stdio" in other files 45 | - add more libc features and optimize the existing features 46 | 47 | -------------------------------------------------------------------------------- /src/darksocv.lds: -------------------------------------------------------------------------------- 1 | /* Copyright (c) 2018, Marcelo Samsoniuk 2 | * All rights reserved. 3 | * 4 | * Redistribution and use in source and binary forms, with or without 5 | * modification, are permitted provided that the following conditions are met: 6 | * 7 | * * Redistributions of source code must retain the above copyright notice, this 8 | * list of conditions and the following disclaimer. 9 | * 10 | * * Redistributions in binary form must reproduce the above copyright notice, 11 | * this list of conditions and the following disclaimer in the documentation 12 | * and/or other materials provided with the distribution. 13 | * 14 | * * Neither the name of the copyright holder nor the names of its 15 | * contributors may be used to endorse or promote products derived from 16 | * this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | */ 29 | 30 | MEMORY 31 | { 32 | /* 33 | darkshell 34 | */ 35 | 36 | MEM (rwx) : ORIGIN = 0x00000000, LENGTH = MLEN 37 | } 38 | 39 | SECTIONS 40 | { 41 | .text : 42 | { 43 | *boot*.o(.text) 44 | *boot*.o(.rodata) 45 | 46 | /* enable this in order to use the uart boot! */ 47 | 48 | . = 512; 49 | 50 | _text = .; 51 | *(.text*) 52 | _etext = .; 53 | } > MEM 54 | .data : 55 | { 56 | _data = .; 57 | *(.rodata*) 58 | *(.data*) 59 | _global = . + 0x800; 60 | *(.sbss*) 61 | *(.bss*) 62 | *(.sdata*) 63 | *(.*) 64 | . = ALIGN(4); 65 | _edata = .; 66 | 67 | } > MEM 68 | 69 | PROVIDE ( _stack = ORIGIN(MEM) + LENGTH(MEM) ); 70 | } 71 | -------------------------------------------------------------------------------- /src/dhrystone/LICENSE: -------------------------------------------------------------------------------- 1 | Dhrystone 2 | ------------------------------------------------------------------------------ 3 | There is no explicit license defined. They were originally 4 | written in ADA by Reinhold P. Weicker and translated to C by Rick Richardson . 5 | 6 | The source obtained from the following site: 7 | https://fossies.org/linux/privat/old/dhrystone-2.1.tar.gz 8 | -------------------------------------------------------------------------------- /src/dhrystone/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | CFLAGS += -Wno-implicit -Wno-incompatible-library-redeclaration -Wno-return-type \ 32 | -fno-builtin-printf -fno-common -falign-functions=4 -Wno-builtin-declaration-mismatch \ 33 | -DTIME -DNOEMUM -DDHRY_ITERS=2000000 34 | 35 | PROJ = dhrystone 36 | OBJS = dhry_1.o dhry_2.o 37 | ASMS = dhry_1.s dhry_2.s 38 | SRCS = dhry_1.c dhry_2.c 39 | 40 | DEPS = $(SRCS) $(ASMS) $(OBJS) $(LIBS) # $(PROJ).ld $(PROJ).lds $(DARKLIBC)/darklibc.a 41 | 42 | TARGETS = $(PROJ).a 43 | 44 | .PHONY: all 45 | 46 | all: $(TARGETS) $(DEPS) 47 | @echo sources ok for $(TARGETS). 48 | 49 | clean: 50 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} $(PROJ)_uart.bin 51 | 52 | %.o: %.s Makefile 53 | $(AS) $(ASFLAGS) -c $< -o $@ 54 | 55 | %.s: %.c Makefile 56 | $(CC) $(CFLAGS) -S $< -o $@ 57 | 58 | $(PROJ).a: $(OBJS) Makefile 59 | $(AR) $(ARFLAGS) $@ $(OBJS) 60 | $(RL) $@ 61 | 62 | $(PROJ).x86: $(SRCS) 63 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 64 | @echo x86 ok. 65 | -------------------------------------------------------------------------------- /src/dhrystone/README.md: -------------------------------------------------------------------------------- 1 | ##Dhrystone 2.1 2 | 3 | the result "maches" the expected for DarkRISCV@100MHz w/ 3-stage pipeline: 4 | 5 | - gcc -O3: 22652 bytes 66DMIPS 11% more mem, 0% more speed (relative to -O2) 6 | - gcc -O2: 20244 bytes 66DMIPS 9% more mem, 100% more speed (relative to -Os) 7 | - gcc -Os: 18416 bytes 33DMIPS 8 | 9 | on DarkRISCV@66MHz 2-stage pipeline: 10 | 11 | - gcc -O2: 50DMIPS (aka 75DMIPS@100MHz) 12 | -------------------------------------------------------------------------------- /src/donut/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | # to make it smaller! 32 | # SMALL = 1 33 | 34 | ifdef SMALL 35 | CFLAGS += -DSMALL 36 | endif 37 | 38 | PROJ = donut 39 | OBJS = main.o 40 | ASMS = main.s 41 | SRCS = main.c 42 | 43 | DEPS = $(SRCS) $(ASMS) $(OBJS) $(LIBS) # $(PROJ).ld $(PROJ).lds $(DARKLIBC)/darklibc.a 44 | 45 | TARGETS = $(PROJ).a 46 | 47 | .PHONY: all 48 | 49 | all: $(TARGETS) $(DEPS) 50 | @echo sources ok for $(TARGETS). 51 | 52 | clean: 53 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} $(PROJ)_uart.bin 54 | 55 | %.o: %.s Makefile 56 | $(AS) $(ASFLAGS) -c $< -o $@ 57 | 58 | %.s: %.c Makefile 59 | $(CC) $(CFLAGS) -S $< -o $@ 60 | 61 | $(PROJ).a: $(OBJS) Makefile 62 | $(AR) $(ARFLAGS) $@ $(OBJS) 63 | $(RL) $@ 64 | 65 | $(PROJ).x86: $(SRCS) 66 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 67 | @echo x86 ok. 68 | -------------------------------------------------------------------------------- /src/donut/README.md: -------------------------------------------------------------------------------- 1 | original file from: 2 | 3 | https://gist.github.com/a1k0n/8ea6516b4946ab36348fb61703dc3194 4 | -------------------------------------------------------------------------------- /src/mandelbrot/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | PROJ = mandelbrot 32 | OBJS = main.o 33 | ASMS = main.s 34 | SRCS = main.c 35 | 36 | 37 | DEPS = $(SRCS) $(ASMS) $(OBJS) $(LIBS) # $(PROJ).ld $(PROJ).lds $(DARKLIBC)/darklibc.a 38 | 39 | TARGETS = $(PROJ).a 40 | 41 | .PHONY: all 42 | 43 | all: $(TARGETS) $(DEPS) 44 | @echo sources ok for $(TARGETS). 45 | 46 | clean: 47 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} $(PROJ)_uart.bin 48 | 49 | %.o: %.s Makefile 50 | $(AS) $(ASFLAGS) -c $< -o $@ 51 | 52 | %.s: %.c Makefile 53 | $(CC) $(CFLAGS) -S $< -o $@ 54 | 55 | $(PROJ).a: $(OBJS) Makefile 56 | $(AR) $(ARFLAGS) $@ $(OBJS) 57 | $(RL) $@ 58 | 59 | $(PROJ).x86: $(SRCS) 60 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 61 | @echo x86 ok. 62 | -------------------------------------------------------------------------------- /src/mandelbrot/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Ported to C language by Marcelo Samsoniuk 3 | * based on BASIC code published by Satoshi Okue: 4 | * https://twitter.com/S_Okue/status/1705175021000458592 5 | * which appears to be based on: 6 | * https://twitter.com/okazunori68/status/1629832782280282113 7 | */ 8 | 9 | #include 10 | 11 | int main() 12 | { 13 | int f,c,d,a,b,p,q,s,t,i,x,y; 14 | char *hex="0123456789ABCDEF"; 15 | 16 | f=50; y=-12; 17 | 18 | loop30: 19 | 20 | x=-39; 21 | 22 | loop40: 23 | 24 | c=x*229/100; d=y*416/100; a=c; b=d; i=0; 25 | 26 | loop90: 27 | 28 | q=b/f; s=b-q*f; t=(a*a-b*b)/f+c; b=2*(a*q+a*s/f)+d; a=t; p=a/f; q=b/f; 29 | if((p*p+q*q)>4) goto loop180; 30 | i++; 31 | if(i<=15) goto loop90; 32 | printf(" "); 33 | goto loop250; 34 | 35 | loop180: 36 | 37 | putchar(hex[(int)i]); // this line replace the BASIC lines 180-240 38 | 39 | loop250: 40 | 41 | x++; 42 | if(x<=39) goto loop40; 43 | printf("\n"); y++; 44 | if(y<=12) goto loop30; 45 | printf("ok\n"); 46 | 47 | printf("press to restart..."); 48 | getchar(); 49 | return 0; 50 | } 51 | -------------------------------------------------------------------------------- /src/primes/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2018, Marcelo Samsoniuk 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | # to make it smaller! 32 | # SMALL = 1 33 | 34 | ifdef SMALL 35 | CFLAGS += -DSMALL 36 | endif 37 | 38 | PROJ = primes 39 | OBJS = main.o 40 | ASMS = main.s 41 | SRCS = main.c 42 | 43 | DEPS = $(SRCS) $(ASMS) $(OBJS) $(LIBS) # $(PROJ).ld $(PROJ).lds $(DARKLIBC)/darklibc.a 44 | 45 | TARGETS = $(PROJ).a 46 | 47 | .PHONY: all 48 | 49 | all: $(TARGETS) $(DEPS) 50 | @echo sources ok for $(TARGETS). 51 | 52 | clean: 53 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} $(PROJ)_uart.bin 54 | 55 | %.o: %.s Makefile 56 | $(AS) $(ASFLAGS) -c $< -o $@ 57 | 58 | %.s: %.c Makefile 59 | $(CC) $(CFLAGS) -S $< -o $@ 60 | 61 | $(PROJ).a: $(OBJS) Makefile 62 | $(AR) $(ARFLAGS) $@ $(OBJS) 63 | $(RL) $@ 64 | 65 | $(PROJ).x86: $(SRCS) 66 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 67 | @echo x86 ok. 68 | -------------------------------------------------------------------------------- /src/spidemo/Makefile: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2025, Nicolas Sauzede 2 | # All rights reserved. 3 | # 4 | # Redistribution and use in source and binary forms, with or without 5 | # modification, are permitted provided that the following conditions are met: 6 | # 7 | # * Redistributions of source code must retain the above copyright notice, this 8 | # list of conditions and the following disclaimer. 9 | # 10 | # * Redistributions in binary form must reproduce the above copyright notice, 11 | # this list of conditions and the following disclaimer in the documentation 12 | # and/or other materials provided with the distribution. 13 | # 14 | # * Neither the name of the copyright holder nor the names of its 15 | # contributors may be used to endorse or promote products derived from 16 | # this software without specific prior written permission. 17 | # 18 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | # DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | # FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | # DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | # SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | # CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | 29 | include ../config.mk 30 | 31 | # to make it smaller! 32 | # SMALL = 1 33 | 34 | ifdef SMALL 35 | CFLAGS += -DSMALL 36 | endif 37 | 38 | PROJ = spidemo 39 | OBJS = main.o 40 | ASMS = main.s 41 | SRCS = main.c 42 | 43 | DEPS = $(SRCS) $(ASMS) $(OBJS) $(LIBS) # $(PROJ).ld $(PROJ).lds $(DARKLIBC)/darklibc.a 44 | 45 | TARGETS = $(PROJ).a 46 | 47 | SPIBB := 1 48 | ifdef SPIBB 49 | CFLAGS += -DSPIBB=1 50 | endif 51 | SPI3WIRE:=1 52 | ifdef SPI3WIRE 53 | CFLAGS += -DSPI3WIRE=1 54 | endif 55 | 56 | .PHONY: all 57 | 58 | all: $(TARGETS) $(DEPS) 59 | @echo sources ok for $(TARGETS). 60 | 61 | clean: 62 | -rm -f $(ASMS) $(OBJS) $(PROJ).{S,bin,lst,map,ram,rom,x86,text,data,bin,ld,o,mem,rom.mem,ram.mem,a} $(PROJ)_uart.bin 63 | 64 | %.o: %.s Makefile 65 | $(AS) $(ASFLAGS) -c $< -o $@ 66 | 67 | %.s: %.c Makefile 68 | $(CC) $(CFLAGS) -S $< -o $@ 69 | 70 | $(PROJ).a: $(OBJS) Makefile 71 | $(AR) $(ARFLAGS) $@ $(OBJS) 72 | $(RL) $@ 73 | 74 | $(PROJ).x86: $(SRCS) 75 | $(HOST_CC) $(HOST_CFLAGS) $(SRCS) -o $(PROJ).x86 -DBUILD="\"$(BUILD)\"" -DARCH="\"x86\"" 76 | @echo x86 ok. 77 | -------------------------------------------------------------------------------- /src/spidemo/README.md: -------------------------------------------------------------------------------- 1 | # SPI Demo 2 | This SPI demo was written for the max1000_max10 board and its builtin SPI accelerometer sensor (refer to boards/max1000_max10/README.md). 3 | 4 | Note however that this application can be simulated without any hardware, using a custom accelerometer stub: 5 | ```shell 6 | make clean all APPLICATION=spidemo 7 | gtkwave rtl/lib/spi/darksocv.gtkw & 8 | ``` 9 | 10 | # Python helper 11 | A python helper (tailored for spi/bb stuff) is provided to easily interact with the darkriscv/fpga shell serial port (`/dev/ttyUSB?`). 12 | Following examples assume that APPLICATION=spidemo has been built/installed. 13 | Eg: Set Bit-Banging off, Check WHOAMI then read OUT_X SPI register: 14 | ```shell 15 | $ ./ser.py "set_bb 0" whoami read 16 | Good HW whoami returned expected 33 17 | main: ret=70 18 | ``` 19 | Eg: Set Bit-Banging on, Check WHOAMI then bit-bang-read OUT_X SPI register: 20 | ```shell 21 | $ ./ser.py "set_bb 1" "bb 7 f b 9 b 9 b 9 b 8 a 9 b 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a f 7" 22 | Good BB whoami returned expected 33 23 | val=80 24 | ``` 25 | -------------------------------------------------------------------------------- /src/spidemo/ser.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import serial 4 | import time 5 | import glob 6 | import sys 7 | 8 | def communicate_with_device(device_path, messages, timeout=0.05, baudrate=115200): 9 | """ 10 | Open a serial connection to a device, send messages, 11 | and read the response. 12 | 13 | Args: 14 | device_path (str): device path to open 15 | messages (list[str]): ASCII messages to send 16 | timeout (float): Read timeout in seconds 17 | baudrate (int): Baud rate for serial communication 18 | """ 19 | try: 20 | ser = serial.Serial( 21 | port=device_path, 22 | baudrate=baudrate, 23 | timeout=timeout, 24 | bytesize=serial.EIGHTBITS, 25 | parity=serial.PARITY_NONE, 26 | stopbits=serial.STOPBITS_ONE 27 | ) 28 | # Add a small delay to ensure port is fully open 29 | # time.sleep(0.2) 30 | for message in messages: 31 | message += "\n" 32 | # Convert string to bytes and write to device 33 | ser.write(message.encode('ascii')) 34 | # Skip first response (command echo) 35 | response = ser.readline().decode('ascii').strip() 36 | if response != message.strip(): 37 | print(f"Error: first {response=} != {message=}") 38 | break 39 | while 1: 40 | response = ser.readline().decode('ascii').strip() 41 | if not response: 42 | break 43 | elif response.endswith(">"): 44 | break 45 | elif message.startswith("bb "): 46 | for resp in response.splitlines(): 47 | #print(f"{response=}") 48 | if ':' not in resp: 49 | val = int(resp, 16) & 0xffff 50 | print(f"{val=:x}"); 51 | else: 52 | for resp in response.splitlines(): 53 | print(f"{response}") 54 | ser.close() 55 | except serial.SerialException as e: 56 | print(f"Error communicating with {device_path}: {e}") 57 | if __name__ == "__main__": 58 | device_path = glob.glob('/dev/ttyUSB?')[0] 59 | args = sys.argv 60 | #print(f"{args}") 61 | if len(args) > 1: 62 | messages = args[1:] 63 | #print(f"{messages=}") 64 | else: 65 | messages = [ 66 | "set_bb 1", 67 | #"bb 7 f b 9 b 8 a 8 a 8 a 9 b 9 b 9 b 9 b 9 b 9 b 9 b 9 b 9 b 9 b 9 b 9 b f 7",# WHOAMI 1fff => ff33 68 | "bb 7 f b 9 b 9 b 9 b 8 a 9 b 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a 8 a f 7",# READ OUT_X => ffa007 69 | ] 70 | communicate_with_device(device_path, messages) 71 | -------------------------------------------------------------------------------- /tmp/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/darklife/darkriscv/b5ba4cb6c2c81ab87f025aa7bf27df438d645980/tmp/.keep --------------------------------------------------------------------------------