├── LICENSE
├── README.md
├── doc
    └── udarkrisc.pdf
├── ise
    └── risc.xise
└── src
    ├── asm.awk
    ├── core.ucf
    ├── core.v
    ├── rom.asm
    ├── rom.v
    ├── soc.v
    └── system.v


/LICENSE:
--------------------------------------------------------------------------------
 1 | BSD 3-Clause License
 2 | 
 3 | Copyright (c) 2015, Marcelo Samsoniuk
 4 | 
 5 | Redistribution and use in source and binary forms, with or without
 6 | modification, are permitted provided that the following conditions are met:
 7 | 
 8 | 1. Redistributions of source code must retain the above copyright notice, this
 9 |    list of conditions and the following disclaimer.
10 | 
11 | 2. Redistributions in binary form must reproduce the above copyright notice,
12 |    this list of conditions and the following disclaimer in the documentation
13 |    and/or other materials provided with the distribution.
14 | 
15 | 3. Neither the name of the copyright holder nor the names of its
16 |    contributors may be used to endorse or promote products derived from
17 |    this software without specific prior written permission.
18 | 
19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
23 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
26 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
  1 | # u[Dark]RISC -- micro-DarkRISC
  2 | 
  3 | This is an early 16-bit RISC processor designed years before DarkRISCV. Although never intendend for real use (it was derived from a serie of experimental cores for a presentation in a University), it is very simple and easy to understand.
  4 | 
  5 | # Features
  6 | 
  7 | Designed back in 2015 (years before DarkRISCV), it includes:
  8 | 
  9 | - Two state pipelined RISC
 10 | - Flexible 16x16-bit registers
 11 | - 16-bit Program Counter (PC)
 12 | - Harvard Architecture w/ separate ROM/RAM up to 64Kword each - Memory mapped IO
 13 | - Less than 100 lines of Verilog
 14 | - 1/3 of a XC3S50AN@75MHz
 15 | - Can be easily changed!
 16 | 
 17 | # History & Motivation
 18 | 
 19 | The beginning: 16-bit VLIW DSPs on FPGAs, with high optimized ALUs around DSP blocks (18x18 mul w/ 48-bit accumulators), in a way that multiple MAC operations can be optimized in parallel w/ other operations (load, branch, etc). However, conventional code was hard to port for VLIW DSPs, so a more general purpose processor was needed...
 20 | 
 21 | Lots of different concepts around accumulator-oriented, register bank oriented, parallel data/address, VLIW, SIMD, MIMD, vector, 16/24/32/48-bits, etc most designs were identified just as “core” or “dsp”, but this specific concept was named uRISC for an external presentation on a University. Because there are too much processors called uRISC already, it was renamed to uDarkRISC (micro-DarkRISC).
 22 | 
 23 | Designed as a evaluation processor, it was never designed to be used on real products and never tested with complex applications... however, the more conventional approach was used as base for DarkRISCV, a high-performance processor which implements a RV32I/E 100% compatible with GCC compiler! For more information about DarkRISCV, please check: https://github.com/darklife/darkriscv/tree/master
 24 | 
 25 | # Instruction Decode
 26 | 
 27 | The 16bit instruction word is read from the synchronous BRAM and divided in 3 or 4 fields, depending on the instruction type:
 28 | 
 29 | - bits 15:12 are the instruction opcode
 30 | - bits 11:8 are the destination register (DREG)
 31 | - bits 7:4 are the source register (SREG)
 32 | - bits 3:0 are reserved for instruction options
 33 | 
 34 | Alternatively, the field 7:0 can be used to load a signed extended 8-bit constant.
 35 | 
 36 | # Instruction Execution
 37 | 
 38 | According to the Destination Register, Source Register, Option Data or Immediate Data, all 16 possible instructions are computed in parallel and put in a 16x16-bit array:
 39 | 
 40 | - shift SREG>>>OPTS ROR)
 41 | - shift SREG<<<OPTS (ROL)
 42 | - add DREG+OPTS or DREG+SREG (ADD)
 43 | - sub DREG-OPTS or DREG-SREG (SUB)
 44 | - xor DREG^SREG (XOR)
 45 | - and DREG&SREG (AND)
 46 | - or DREG|SREG (OR)
 47 | - not ~DREG (NOT)
 48 | - load (LOD) 
 49 | - store (STO)
 50 | - immediate (IMM)
 51 | - (DREG*SREG)>>>OPTS (MUL)
 52 | - branch (BRA)
 53 | - branch to sub-routine (BSR)
 54 | - return from sub-routine (RET)
 55 | - test, decrement and branch (LOP)
 56 | 
 57 | Note that there is no conditional branches other than the LOP instruction.
 58 | 
 59 | As far as the instructions are read from the ROM, the opcode is used to index the above array, so the result is written directly to the register bank. Also, the PC is computed, in a way that it can be 0 (RES==0), DREG (RET instruction), PC+IMM (BSR, BRA or LOP instructions) or just PC+1.
 60 | 
 61 | Finnaly, the LOD and STO activate the RD and WR signals for load/store, with DATA active w/ DREG on store or tri-state on load and SREG as pointer in both cases (so, no addressing modes).
 62 | 
 63 | # Pipeline Detail
 64 | 
 65 | The micro-DarkRISC is a high performacne processor that needs a lot of bandwidth on the instructon bus: running at 75MHz, it requires 150MB/s continuously! So the pipeline is optimized in a way that the pipeline is always filled, even in the case of a branch: there is no flush pipeline, so the pre-fetched instruction is executed and the core peaks IPC = 1 all time.
 66 | 
 67 | Since the load/store instructions are not used so often, there is no optimization regarding the load/store. The impact of such decision depends on the application: for applications that are handled only with internal registe, there is no impact. For most case, however, a small LUTRAM may be enough and, again there is no impact. 
 68 | 
 69 | Eventually, in the case of BRAM, wait-states are required, but the core does not foresee a HALT signal, so there is no way to insert wait-states. Instead, it is possible simulate such wait-states by sucessive load/store instructions at the same address, so the memory is read multiple times until it is ready.
 70 | 
 71 | # Instruction Set
 72 | 
 73 | The direct supported instructions are:
 74 | 
 75 | - ROR/ROL: register right or left rotate.
 76 | - ADD/SUB: register add/sub.
 77 | - XOR/AND/OR/NOT: register logic operations.
 78 | - LOD/STO: register to/from memory operations.
 79 | - IMM: immediate data load (8-bit LSB value).
 80 | - MUL: register multiply and right rotate (trying include some DSP support, but without a wide accumulator).
 81 | - BRA/BSR: load PC from PC+immediate data and, optionally, save PC to a register.
 82 | - RET: load PC from register data.
 83 | - LOP: test register, decrement register and set PC to PC+immediate data.
 84 | 
 85 | In addition, there is an Advanced Instruction Set (aka “pseudo-instructions”). 
 86 | 
 87 | The known pseudo-instructions are:
 88 | 
 89 | - MOV: ROR or ROL with shift value = 0.
 90 | - NOP: MOV with same source/destination register.
 91 | - ADDQ/SUBQ: quick add/sub a value between 1 and 15.
 92 | - JMP: move the address to a register and RET from this register - INC/DEC: ADDQ/SUBQ with value 1.
 93 | - CLR: xor in the same register.
 94 | - and much more! 
 95 | 
 96 | Since the design was before my contact with RISC-V technology, some important concepts are just missing and the set is mostly 68k oriented: ADDQ, SUBQ, BSR, BRA, etc. Even LOP is basically a RISC version of DBcc, which is pretty useful for DSP applications, since LOP supports delayed branch. Although there is no accumulator, the theory around a large accumulator is compute sucessive MUL + ADD, in a way that the values are shifted left. Instead, on this core, the MUL result is shifted right, so it can be accumulated in a separate step, resulting in values that fits on 16-bit only and all LSBs are lost.
 97 | 
 98 | # Development System
 99 | 
100 | Limited to an AWK-based assembler that generates a Verilog file w/ the ROM description and waveform inspection of the simulation... I like show the AWK-based assembler because I developed lots and lots of assemblers and converters across my time working on Siemens, both for well-known archs (such as convert 68000 asm to coldfire asm) and obscure and fully proprietary archs (such as multi-way VLIW DSPs), as well all kind of code/data to verilog converters.
101 | 
102 | # Conclusion
103 | 
104 | Although the uDarkRISC was frozen in time and replaced by the DarkRISCV, there are always people trying find a simple processor to study, which means that there is no bad processors, just processors that are better for different applications. So, although DarkRISCV is good because it can actually run complex code generated by GCC, the uDarkRISC may be far better for starters that are just trying understand how design a simple processor.
105 | 


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/doc/udarkrisc.pdf:
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https://raw.githubusercontent.com/darklife/udarkrisc/00e6da173c99a3e5f233f829bc8efd1d3b8bee10/doc/udarkrisc.pdf


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150 |     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
151 |     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
152 |     <property xil_pn:name="Implementation Top" xil_pn:value="Module|core" xil_pn:valueState="non-default"/>
153 |     <property xil_pn:name="Implementation Top File" xil_pn:value="../src/core.v" xil_pn:valueState="non-default"/>
154 |     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/soc/core0" xil_pn:valueState="non-default"/>
155 |     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
156 |     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
157 |     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
158 |     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
159 |     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
160 |     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
161 |     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
162 |     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
163 |     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
164 |     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
165 |     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
166 |     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
167 |     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
168 |     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
169 |     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
170 |     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
171 |     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
172 |     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
173 |     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
174 |     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
175 |     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
176 |     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
177 |     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
178 |     <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
179 |     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
180 |     <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
181 |     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
182 |     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
183 |     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
184 |     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
185 |     <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
186 |     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
187 |     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
188 |     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
189 |     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
190 |     <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
191 |     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
192 |     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
193 |     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
194 |     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
195 |     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
196 |     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
197 |     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
198 |     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
199 |     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
200 |     <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
201 |     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
202 |     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
203 |     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
204 |     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
205 |     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
206 |     <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
207 |     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
208 |     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
209 |     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
210 |     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
211 |     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
212 |     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
213 |     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
214 |     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
215 |     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
216 |     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
217 |     <property xil_pn:name="Output File Name" xil_pn:value="core" xil_pn:valueState="default"/>
218 |     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
219 |     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
220 |     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
221 |     <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
222 |     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
223 |     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
224 |     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
225 |     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
226 |     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
227 |     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
228 |     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
229 |     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
230 |     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="core_map.v" xil_pn:valueState="default"/>
231 |     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="core_timesim.v" xil_pn:valueState="default"/>
232 |     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="core_synthesis.v" xil_pn:valueState="default"/>
233 |     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="core_translate.v" xil_pn:valueState="default"/>
234 |     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
235 |     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
236 |     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
237 |     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
238 |     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
239 |     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
240 |     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
241 |     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
242 |     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
243 |     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
244 |     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
245 |     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
246 |     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
247 |     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
248 |     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
249 |     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
250 |     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
251 |     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
252 |     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
253 |     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
254 |     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
255 |     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
256 |     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
257 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
258 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
259 |     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
260 |     <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
261 |     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
262 |     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
263 |     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
264 |     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
265 |     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
266 |     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
267 |     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
268 |     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
269 |     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
270 |     <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
271 |     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
272 |     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
273 |     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
274 |     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
275 |     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
276 |     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
277 |     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
278 |     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
279 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
280 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
281 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
282 |     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
283 |     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
284 |     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
285 |     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
286 |     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
287 |     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
288 |     <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
289 |     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
290 |     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
291 |     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
292 |     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
293 |     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
294 |     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
295 |     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
296 |     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
297 |     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
298 |     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
299 |     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
300 |     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
301 |     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
302 |     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
303 |     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
304 |     <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
305 |     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
306 |     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
307 |     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
308 |     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
309 |     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
310 |     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
311 |     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
312 |     <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
313 |     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
314 |     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
315 |     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
316 |     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
317 |     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
318 |     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
319 |     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
320 |     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
321 |     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
322 |     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
323 |     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
324 |     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
325 |     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
326 |     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
327 |     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
328 |     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
329 |     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
330 |     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
331 |     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
332 |     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
333 |     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
334 |     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
335 |     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
336 |     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
337 |     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
338 |     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
339 |     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
340 |     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
341 |     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
342 |     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
343 |     <!--                                                                                  -->
344 |     <!-- The following properties are for internal use only. These should not be modified.-->
345 |     <!--                                                                                  -->
346 |     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
347 |     <property xil_pn:name="PROP_DesignName" xil_pn:value="risc" xil_pn:valueState="non-default"/>
348 |     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
349 |     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
350 |     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
351 |     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
352 |     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
353 |     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
354 |     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
355 |     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-03-21T22:39:17" xil_pn:valueState="non-default"/>
356 |     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BA41FF3C9254DBD93EB21D61D0CBF485" xil_pn:valueState="non-default"/>
357 |     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
358 |     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
359 |   </properties>
360 | 
361 |   <bindings>
362 |     <binding xil_pn:location="/soc" xil_pn:name="../src/core.ucf"/>
363 |   </bindings>
364 | 
365 |   <libraries/>
366 | 
367 |   <autoManagedFiles>
368 |     <!-- The following files are identified by `include statements in verilog -->
369 |     <!-- source files and are automatically managed by Project Navigator.     -->
370 |     <!--                                                                      -->
371 |     <!-- Do not hand-edit this section, as it will be overwritten when the    -->
372 |     <!-- project is analyzed based on files automatically identified as       -->
373 |     <!-- include files.                                                       -->
374 |   </autoManagedFiles>
375 | 
376 | </project>
377 | 


--------------------------------------------------------------------------------
/src/asm.awk:
--------------------------------------------------------------------------------
  1 | #!/usr/bin/awk -f
  2 | 
  3 | BEGIN {
  4 | 
  5 |   for(i=0;i!=256;i++) NEG[i]=255-i;
  6 | 
  7 |   for(j=1;j!=ARGC;j++)
  8 |   {
  9 |     print "processing asm file " ARGV[j];
 10 |     
 11 |     FILE=ARGV[j];
 12 |     LINE=0;
 13 |     
 14 |     while(getline $0 < FILE)
 15 |     {
 16 |       if(NF)
 17 |       {
 18 |         if($0~/:/)
 19 |         {
 20 |           print "  label "$1" at line "LINE
 21 |           gsub(":","",$1); LABEL[$1]=LINE; RLABEL[LINE]=$1
 22 |         }
 23 |         else
 24 |         {
 25 |           print "  instr "$0" at line "LINE
 26 |           
 27 |           SRC[LINE]=$0
 28 | 
 29 |           for(i=2;i<=NF;i++)
 30 |           {
 31 |             if($i~/^%d/)
 32 |             {
 33 |               gsub("^%d","",$i); DREG=int($i); print "    DREG = "DREG
 34 |             }
 35 |             else
 36 |             if($i~/^%s/)
 37 |             {
 38 |               gsub("^%s","",$i); SREG=int($i); print "    SREG = "SREG
 39 |             }
 40 |             else
 41 |             {
 42 |               if(LABEL[$i])
 43 |               {
 44 |                 if(LABEL[$i]>LINE) IMMX=(LABEL[$i]-LINE);
 45 |                 else IMMX=NEG[LINE-LABEL[$i]];
 46 |                 
 47 |                 print "    IMMX = "IMMX" "LINE" to "LABEL[$i]
 48 |               }
 49 |               else
 50 |               {
 51 |                 IMMS=int($i); print "    IMMS = "IMMS
 52 |               } 
 53 |             }
 54 |           }
 55 | 
 56 |           if($1=="ror") DST[LINE]=sprintf("%x%x%x%x",0 ,DREG,SREG,IMMS);
 57 |           if($1=="rol") DST[LINE]=sprintf("%x%x%x%x",1 ,DREG,SREG,IMMS);
 58 |           if($1=="add") DST[LINE]=sprintf("%x%x%x%x",2 ,DREG,SREG,IMMS);
 59 |           if($1=="sub") DST[LINE]=sprintf("%x%x%x%x",3 ,DREG,SREG,IMMS);
 60 |           if($1=="and") DST[LINE]=sprintf("%x%x%x%x",4 ,DREG,SREG,0);
 61 |           if($1=="or" ) DST[LINE]=sprintf("%x%x%x%x",5 ,DREG,SREG,0);
 62 |           if($1=="xor") DST[LINE]=sprintf("%x%x%x%x",6 ,DREG,SREG,0);
 63 |           if($1=="not") DST[LINE]=sprintf("%x%x%x%x",7 ,DREG,0,0);
 64 |           if($1=="lod") DST[LINE]=sprintf("%x%x%x%x",8 ,DREG,SREG,0);
 65 |           if($1=="sto") DST[LINE]=sprintf("%x%x%x%x",9 ,DREG,SREG,0);
 66 |           if($1=="imm") DST[LINE]=sprintf("%x%x%02x",10,DREG,IMMS);
 67 |           if($1=="mul") DST[LINE]=sprintf("%x%x%x%x",11,DREG,SREG,IMMS);
 68 |           if($1=="bra") DST[LINE]=sprintf("%x%x%02x",12,DREG,IMMX);
 69 |           if($1=="bsr") DST[LINE]=sprintf("%x%x%02x",13,DREG,IMMX);
 70 |           if($1=="ret") DST[LINE]=sprintf("%x%x%x%x",14,DREG,0,0);
 71 |           if($1=="lop") DST[LINE]=sprintf("%x%x%02x",15,DREG,IMMX);
 72 | 
 73 |           if($1=="nop") DST[LINE]=sprintf("%x%x%x%x",0 ,0,0,0);
 74 |           if($1=="mov") DST[LINE]=sprintf("%x%x%x%x",0 ,DREG,SREG,0);
 75 |           if($1=="inc") DST[LINE]=sprintf("%x%x%x%x",2 ,DREG,0,1);
 76 |           if($1=="dec") DST[LINE]=sprintf("%x%x%x%x",3 ,DREG,0,1);
 77 |           if($1=="clr") DST[LINE]=sprintf("%x%x%x%x",6 ,DREG,DREG,0);
 78 | 
 79 |           print "    CODE = " DST[LINE];
 80 | 
 81 |           LINE++;
 82 |         }
 83 |       }
 84 |     } 
 85 |     close(FILE);
 86 | 
 87 |     VFILE=FILE;
 88 |     gsub(".asm",".v",VFILE);
 89 | 
 90 |     print ""
 91 |     print "  processed code is from "FILE" to "VFILE":"
 92 |     print ""
 93 | 
 94 |     print "module rom(input CLK, input [9:0] ADDR, output reg [15:0] DATA);" > VFILE
 95 |     print "" > VFILE
 96 |     print "  reg [15:0] ROM [0:1023];" > VFILE
 97 |     print "" > VFILE
 98 |     print "  integer i;" > VFILE
 99 |     print "" > VFILE    
100 |     print "  initial" > VFILE
101 |     print "  begin" > VFILE
102 |     print "    for(i=0;i!=1024;i=i+1)" > VFILE
103 |     print "    begin" > VFILE
104 |     print "      ROM[i] = 0;" > VFILE
105 |     print "    end" > VFILE
106 |     print "" > VFILE
107 |     
108 |     for(i=0;i!=1024;i++)
109 |     {
110 |       if(DST[i])
111 |       {
112 |         printf("  %04d:%s %20s %s\n",i,DST[i],RLABEL[i],SRC[i]);
113 |         print "    ROM["i"] = 16'h"DST[i]";" > VFILE
114 |       }
115 |     }
116 |     
117 |     print "  end" > VFILE
118 |     print "" > VFILE
119 |     print "  always@(posedge CLK) DATA <= ROM[ADDR];" > VFILE
120 |     print "endmodule" > VFILE
121 |     
122 |     close(VFILE)
123 | 
124 |     print "done."
125 |   }
126 | }
127 | 


--------------------------------------------------------------------------------
/src/core.ucf:
--------------------------------------------------------------------------------
1 | NET CLK PERIOD = 50MHz;
2 | 


--------------------------------------------------------------------------------
/src/core.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date:    15:23:48 02/14/2015 
 7 | // Design Name: 
 8 | // Module Name:    core 
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool versions: 
12 | // Description: 
13 | //
14 | // Dependencies: 
15 | //
16 | // Revision: 
17 | // Revision 0.01 - File Created
18 | // Additional Comments: 
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | `define ROR 4'd0
23 | `define ROL 4'd1
24 | `define ADD 4'd2
25 | `define SUB 4'd3
26 | `define AND 4'd4
27 | `define OR  4'd5
28 | `define XOR 4'd6
29 | `define NOT 4'd7
30 | `define LOD 4'd8
31 | `define STO 4'd9
32 | `define IMM 4'd10
33 | `define MUL 4'd11
34 | `define BRA 4'd12
35 | `define BSR 4'd13
36 | `define RET 4'd14
37 | `define LOP 4'd15
38 | 
39 | module core(
40 |     input               CLK,
41 |     input               RES,
42 |     output              RD,
43 |     output              WR,
44 |     output      [15:0]  ADDR,
45 |     inout       [15:0]  DATA
46 |     );
47 | 
48 |     wire        [15:0]  IDATA;
49 | 
50 |     wire        [ 3:0]  INST =    IDATA[15:12];
51 |     wire        [ 3:0]  DPTR =    IDATA[11: 8];
52 |     wire        [ 3:0]  SPTR =    IDATA[ 7: 4];
53 |     wire        [ 3:0]  OPTS =    IDATA[ 3: 0];
54 | 
55 |     reg         [15:0]  PC;
56 | 
57 |     reg signed  [15:0]  REG [0:15];
58 | 
59 |     wire signed [15:0]  IMMS = { IDATA[7]?8'hff:8'h00, IDATA[7:0] };
60 |     wire signed [15:0]  DREG = REG[DPTR];
61 |     wire signed [15:0]  SREG = REG[SPTR];
62 |     wire signed [15:0]  DMUX   [0:15]; 
63 | 
64 |     assign DMUX[`ROR] = SREG>>>OPTS;                  // dreg = sreg>>>opts
65 |     assign DMUX[`ROL] = SREG<<<OPTS;                  // dreg = sreg<<<opts
66 |     assign DMUX[`ADD] = (OPTS?DREG+OPTS:DREG+SREG);   // dreg = dreg+opts or dreg+sreg
67 |     assign DMUX[`SUB] = (OPTS?DREG-OPTS:DREG-DREG);   // dreg = dreg-opts or dreg-sreg
68 |     assign DMUX[`XOR] = DREG^SREG;                    // dreg = dreg xor sreg
69 |     assign DMUX[`AND] = DREG&SREG;                    // dreg = dreg and sreg
70 |     assign DMUX[ `OR] = DREG|SREG;                    // dreg = dreg or  sreg
71 |     assign DMUX[`NOT] = ~DREG;                        // dreg = not dreg
72 |     assign DMUX[`LOD] = DATA;                         // dreg = *sreg
73 |     assign DMUX[`STO] = DREG;
74 |     assign DMUX[`IMM] = IMMS;                         // dreg = imms
75 |     assign DMUX[`MUL] = (DREG*SREG)>>>OPTS;           // dreg = (dreg*sreg)>>>opts
76 |     assign DMUX[`BRA] = DREG;
77 |     assign DMUX[`BSR] = PC+1;                         // dreg = pc+1, pc += imms
78 |     assign DMUX[`RET] = DREG;
79 |     assign DMUX[`LOP] = DREG-1;                       // dreg = dreg-1
80 |     
81 |     always@(posedge CLK)
82 |     begin       
83 |         REG[DPTR] <=    DMUX[INST];
84 |         
85 |         PC <=          !RES ? 0 : 
86 |                  INST==`RET ? DREG : 
87 |                               PC+(INST==`BSR||INST==`BRA||(INST==`LOP&&!DREG[15])?IMMS:1);
88 |     end
89 | 
90 |     assign RD    = INST==`LOD;
91 |     assign WR    = INST==`STO;
92 |     assign DATA  = RD ? 16'hzzzz : DREG;
93 |     assign ADDR  = SREG;
94 | 
95 |     rom rom(CLK,PC[9:0],IDATA);
96 | 
97 | endmodule
98 | 


--------------------------------------------------------------------------------
/src/rom.asm:
--------------------------------------------------------------------------------
 1 | start:
 2 | 	nop
 3 | 
 4 | 	imm     0  %d0
 5 | 	imm	1  %d1
 6 | 	imm 	2  %d2
 7 | 	imm 	3  %d3
 8 | 	imm     4  %d4
 9 | 	imm	5  %d5
10 | 	imm 	6  %d6
11 | 	imm 	7  %d7
12 | 	imm     8  %d8
13 | 	imm	9  %d9
14 | 	imm 	10 %d10
15 | 	imm 	11 %d11
16 | 	imm     12 %d12
17 | 	imm	13 %d13
18 | 	imm 	14 %d14
19 | 	imm 	15 %d15
20 | 
21 | 	clr     %d8
22 | 	xor 	%s1 %d0
23 | 	ror	%s2 %d3 13
24 | 	imm 	8 %d4
25 | loop:
26 | 	lod	%p8 %d7
27 | 	not	%d7
28 | 	sto	%p8 %d7
29 | 	lop 	%d4 loop
30 | 	nop	
31 | 
32 | 	xor	%d0 %d0
33 | 
34 | stop:
35 | 	bra stop
36 | 	nop
37 | 	


--------------------------------------------------------------------------------
/src/rom.v:
--------------------------------------------------------------------------------
 1 | module rom(input CLK, input [9:0] ADDR, output reg [15:0] DATA);
 2 | 
 3 |   reg [15:0] ROM [0:1023];
 4 | 
 5 |   integer i;
 6 | 
 7 |   initial
 8 |   begin
 9 |     for(i=0;i!=1024;i=i+1)
10 |     begin
11 |       ROM[i] = 0;
12 |     end
13 | 
14 |     ROM[0] = 16'h0000;
15 |     ROM[1] = 16'ha000;
16 |     ROM[2] = 16'ha101;
17 |     ROM[3] = 16'ha202;
18 |     ROM[4] = 16'ha303;
19 |     ROM[5] = 16'ha404;
20 |     ROM[6] = 16'ha505;
21 |     ROM[7] = 16'ha606;
22 |     ROM[8] = 16'ha707;
23 |     ROM[9] = 16'ha808;
24 |     ROM[10] = 16'ha909;
25 |     ROM[11] = 16'haa0a;
26 |     ROM[12] = 16'hab0b;
27 |     ROM[13] = 16'hac0c;
28 |     ROM[14] = 16'had0d;
29 |     ROM[15] = 16'hae0e;
30 |     ROM[16] = 16'haf0f;
31 |     ROM[17] = 16'h6880;
32 |     ROM[18] = 16'h6010;
33 |     ROM[19] = 16'h032d;
34 |     ROM[20] = 16'ha408;
35 |     ROM[21] = 16'h8720;
36 |     ROM[22] = 16'h7700;
37 |     ROM[23] = 16'h9720;
38 |     ROM[24] = 16'hf4fc;
39 |     ROM[25] = 16'h0000;
40 |     ROM[26] = 16'h6020;
41 |     ROM[27] = 16'hc0ff;
42 |     ROM[28] = 16'h0000;
43 |   end
44 | 
45 |   always@(posedge CLK) DATA <= ROM[ADDR];
46 | endmodule
47 | 


--------------------------------------------------------------------------------
/src/soc.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date:    21:48:56 02/14/2015 
  7 | // Design Name: 
  8 | // Module Name:    soc 
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool versions: 
 12 | // Description: 
 13 | //
 14 | // Dependencies: 
 15 | //
 16 | // Revision: 
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments: 
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module soc(
 23 |     input               CLK,
 24 |     input               RES,
 25 |     input      [11:0]   IN0,
 26 |     input      [11:0]   IN1,
 27 |     input      [11:0]   IN2,
 28 |     input      [11:0]   IN3,
 29 |     output reg [11:0]   OUT0 = 0,
 30 |     output reg [11:0]   OUT1 = 0,
 31 |     output reg [11:0]   OUT2 = 0,
 32 |     output reg [11:0]   OUT3 = 0
 33 |     );
 34 | 
 35 |     wire [15:0] ADDR0;
 36 |     wire [15:0] DATA0;
 37 |     wire RD0,WR0;
 38 | 
 39 |     core core0(
 40 |         .CLK(CLK),
 41 |         .RES(RES),
 42 |         .RD(RD0),
 43 |         .WR(WR0),
 44 |         .ADDR(ADDR0),
 45 |         .DATA(DATA0)
 46 |     );
 47 | 
 48 |     wire [15:0] ADDR1;
 49 |     wire [15:0] DATA1;
 50 |     wire RD1,WR1;
 51 | 
 52 |     core core1(
 53 |         .CLK(CLK),
 54 |         .RES(RES),
 55 |         .RD(RD1),
 56 |         .WR(WR1),
 57 |         .ADDR(ADDR1),
 58 |         .DATA(DATA1)
 59 |     );
 60 | 
 61 |     wire [15:0] ADDR2;
 62 |     wire [15:0] DATA2;
 63 |     wire RD2,WR2;
 64 | 
 65 |     core core2(
 66 |         .CLK(CLK),
 67 |         .RES(RES),
 68 |         .RD(RD2),
 69 |         .WR(WR2),
 70 |         .ADDR(ADDR2),
 71 |         .DATA(DATA2)
 72 |     );
 73 | 
 74 |     wire [15:0] ADDR3;
 75 |     wire [15:0] DATA3;
 76 |     wire RD3,WR3;
 77 | 
 78 |     core core3(
 79 |         .CLK(CLK),
 80 |         .RES(RES),
 81 |         .RD(RD3),
 82 |         .WR(WR3),
 83 |         .ADDR(ADDR3),
 84 |         .DATA(DATA3)
 85 |     );
 86 | 
 87 |     always@(posedge CLK)
 88 |     begin
 89 |         if(WR0) OUT0 = DATA0;
 90 |         if(WR1) OUT1 = DATA1;
 91 |         if(WR2) OUT2 = DATA2;
 92 |         if(WR3) OUT3 = DATA3;
 93 |     end
 94 | 
 95 |     assign DATA0 = RD0 ? IN0 : 16'hzzzz;
 96 |     assign DATA1 = RD1 ? IN1 : 16'hzzzz;
 97 |     assign DATA2 = RD2 ? IN2 : 16'hzzzz;
 98 |     assign DATA3 = RD3 ? IN3 : 16'hzzzz;
 99 | 
100 | endmodule
101 | 


--------------------------------------------------------------------------------
/src/system.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | 
  3 | ////////////////////////////////////////////////////////////////////////////////
  4 | // Company: 
  5 | // Engineer:
  6 | //
  7 | // Create Date:   19:21:40 02/14/2015
  8 | // Design Name:   core
  9 | // Module Name:   Z:/Users/marcelo/Documents/Verilog/RISCv2/src/system.v
 10 | // Project Name:  RISCv2
 11 | // Target Device:  
 12 | // Tool versions:  
 13 | // Description: 
 14 | //
 15 | // Verilog Test Fixture created by ISE for module: core
 16 | //
 17 | // Dependencies:
 18 | // 
 19 | // Revision:
 20 | // Revision 0.01 - File Created
 21 | // Additional Comments:
 22 | // 
 23 | ////////////////////////////////////////////////////////////////////////////////
 24 | 
 25 | module system;
 26 | 
 27 | 	// Inputs
 28 | 	reg CLK;
 29 | 	reg RES;
 30 | 
 31 | 	// Outputs
 32 | 	wire        RD;
 33 | 	wire        WR;
 34 | 	wire [15:0] ADDR;
 35 | 
 36 | 	// Bidirs
 37 | 	wire [15:0] DATA;
 38 | 
 39 | 	// Instantiate the Unit Under Test (UUT)
 40 | 	core uut (
 41 | 		.CLK(CLK), 
 42 | 		.RES(RES), 
 43 | 		.RD(RD), 
 44 | 		.WR(WR), 
 45 | 		.ADDR(ADDR), 
 46 | 		.DATA(DATA)
 47 | 	);
 48 | 
 49 |     reg [15:0] RAM [0:15];
 50 |     
 51 |     reg [15:0] DATAO = 0;
 52 | 
 53 |     integer j;
 54 | 
 55 |     initial
 56 |     begin
 57 |         for(j=0;j!=16;j=j+1)
 58 |         begin
 59 |             RAM[j] = j;
 60 |         end
 61 |     end
 62 | 
 63 |     reg [3:0] RPTR = 0;
 64 |     reg [3:0] XPTR = 0;
 65 | 
 66 |     assign DATA = RD ? DATAO : 16'hzzzz;
 67 | 
 68 |     always@(posedge CLK)
 69 |     begin
 70 |         DATAO <= RAM[RPTR];
 71 |         if(RD)
 72 |         begin
 73 |             RPTR <= RPTR+1;
 74 |         end
 75 |         
 76 |         if(WR)
 77 |         begin
 78 |             RAM[XPTR] <= DATA;
 79 |             XPTR <= XPTR+1;
 80 |         end
 81 |     end
 82 |     
 83 |     integer i;
 84 | 
 85 | 	initial begin
 86 | 		// Initialize Inputs
 87 | 		CLK = 0;
 88 | 		RES = 0;
 89 | 
 90 |         for(i=0;i!=10000;i=i+1)
 91 |         begin
 92 |             #10 CLK = !CLK;
 93 |             if(i>10)
 94 |             begin
 95 |                 RES = 1;
 96 |             end
 97 |         end 
 98 | 	end
 99 |       
100 | endmodule
101 | 


--------------------------------------------------------------------------------