├── README.md ├── bench ├── Makefile ├── orpsoc_tb.v ├── spi_image.S ├── spi_image.vh ├── test-defines.v └── uart_decoder.v ├── data ├── wb_intercon.conf └── wb_intercon_dbg.conf ├── rtl └── verilog │ ├── clkgen.v │ ├── orpsoc_top.v │ ├── timescale.v │ ├── wb_intercon.v │ ├── wb_intercon.vh │ ├── wb_intercon.vh~ │ ├── wb_intercon_dbg.v │ └── wb_intercon_dbg.vh ├── sw ├── Makefile ├── clear_r3_and_jump_to_0x100.vh ├── spi_uimage_loader.S ├── spi_uimage_loader.vh └── wb_rom_gen.py ├── ulx3s.core └── utils ├── boot_linux.sh └── program.sh /README.md: -------------------------------------------------------------------------------- 1 | Bootloader 2 | ---------- 3 | 4 | The Trellis system is set up by default to start executing at address 0xf0000000 where the boot ROM is located. The contents of the bootloader memory can be set by changing the top-level parameter `bootrom_file` to a different file. Two different bootloaders are shipped with the de0_nano files. 5 | 6 | ### SPI Flash bootloader 7 | 8 | spi_loader program starts executing from internal Boot ROM. This reads out a binary image stored in the on-board SPI Flash and writes it to SDRAM. For simulations, the contents of the SPI Flash can be set with the `spi_flash_file` parameter 9 | 10 | When the program is done loading to RAM, spi_loader will jump to address 0x100 where it expects the first instruction of the program that was copied from the SPI Flash 11 | 12 | ### Clear R3 and jump to 0x100 13 | 14 | The boot ROM will clear registers r0 and r3 and then proceeed to start executing a program from address 0x100. This bootloader is intended for simulation purposes where a program can be preloaded to RAM with the --elf-load=/path/to/elf-file parameter, as well as on target HW where the RAM is initialized with a debugger 15 | -------------------------------------------------------------------------------- /bench/Makefile: -------------------------------------------------------------------------------- 1 | BOOTROM_ADDR ?= 0x80000 2 | RESET_VECTOR ?= 0x100 3 | IMAGE ?= spi_image 4 | IMAGE_NAME ?= $(IMAGE) 5 | 6 | all: $(IMAGE).vh 7 | 8 | %.vh: %.ub 9 | or1k-elf-objcopy --change-addresses $(BOOTROM_ADDR) -I binary -O verilog $< $@ 10 | 11 | %.bin: %.elf 12 | or1k-elf-objcopy -O binary $< $@ 13 | 14 | %.ub: %.bin 15 | mkimage \ 16 | -A or1k \ 17 | -C none \ 18 | -T standalone \ 19 | -a 0x100 \ 20 | -e $(RESET_VECTOR) \ 21 | -n '$@' \ 22 | -d $< \ 23 | $@ 24 | 25 | %.elf: %.S 26 | or1k-elf-gcc -nostdlib $< -o $@ 27 | 28 | clean: 29 | rm -f $(IMAGE).vh 30 | -------------------------------------------------------------------------------- /bench/orpsoc_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module orpsoc_tb; 4 | 5 | //////////////////////////////////////////////////////////////////////// 6 | // 7 | // Boot ROM selection 8 | // 9 | //////////////////////////////////////////////////////////////////////// 10 | parameter bootrom_file = "bootrom/clear_r3_and_jump_to_0x100.vh"; 11 | // parameter bootrom_file = "bootrom/spi_uimage_loader.vh"; 12 | 13 | /* 14 | When the SPI uimage loader is used, the following parameter can be 15 | set to provide alternative SPI Flash contents 16 | */ 17 | parameter spi_flash_file = "spi_image.vh"; 18 | 19 | reg clk = 0; 20 | reg rst_n = 0; 21 | 22 | //////////////////////////////////////////////////////////////////////// 23 | // 24 | // Generate clock (50MHz) and external reset 25 | // 26 | //////////////////////////////////////////////////////////////////////// 27 | 28 | always 29 | #10 clk <= ~clk; 30 | 31 | initial begin 32 | #100 rst_n <= 0; 33 | #200 rst_n <= 1; 34 | end 35 | 36 | //////////////////////////////////////////////////////////////////////// 37 | // 38 | // Add --vcd and --timeout options to the simulation 39 | // 40 | //////////////////////////////////////////////////////////////////////// 41 | vlog_tb_utils vlog_tb_utils0(); 42 | 43 | 44 | //////////////////////////////////////////////////////////////////////// 45 | // 46 | // SDRAM 47 | // 48 | //////////////////////////////////////////////////////////////////////// 49 | 50 | wire [1:0] sdram_ba; 51 | wire [12:0] sdram_addr; 52 | wire sdram_cs_n; 53 | wire sdram_ras; 54 | wire sdram_cas; 55 | wire sdram_we; 56 | wire [15:0] sdram_dq; 57 | wire [1:0] sdram_dqm; 58 | wire sdram_cke; 59 | wire sdram_clk; 60 | 61 | mt48lc16m16a2_wrapper 62 | #(.ADDR_BITS (13)) 63 | sdram_wrapper0 64 | (.clk_i (sdram_clk), 65 | .rst_n_i (rst_n), 66 | .dq_io (sdram_dq), 67 | .addr_i (sdram_addr), 68 | .ba_i (sdram_ba), 69 | .cas_i (sdram_cas), 70 | .cke_i (sdram_cke), 71 | .cs_n_i (sdram_cs_n), 72 | .dqm_i (sdram_dqm), 73 | .ras_i (sdram_ras), 74 | .we_i (sdram_we)); 75 | 76 | //////////////////////////////////////////////////////////////////////// 77 | // 78 | // JTAG VPI interface 79 | // 80 | //////////////////////////////////////////////////////////////////////// 81 | 82 | reg enable_jtag_vpi; 83 | initial enable_jtag_vpi = $test$plusargs("enable_jtag_vpi"); 84 | 85 | jtag_vpi jtag_vpi0 86 | ( 87 | .tms (tms), 88 | .tck (tck), 89 | .tdi (tdi), 90 | .tdo (tdo), 91 | .enable (enable_jtag_vpi), 92 | .init_done (orpsoc_tb.dut.wb_rst)); 93 | 94 | //////////////////////////////////////////////////////////////////////// 95 | // 96 | // SPI Flash 97 | // 98 | //////////////////////////////////////////////////////////////////////// 99 | 100 | 101 | 102 | orpsoc_top 103 | #(.bootrom_file (bootrom_file)) 104 | dut 105 | ( 106 | .sys_clk_pad_i (clk), 107 | .btn_pad_i (!rst_n), 108 | .gpio0_io (), 109 | //JTAG interface 110 | .tms_pad_i (tms), 111 | .tck_pad_i (tck), 112 | .tdi_pad_i (tdi), 113 | .tdo_pad_o (tdo), 114 | //SDRAM Interface 115 | .sdram_ba_pad_o (sdram_ba), 116 | .sdram_a_pad_o (sdram_addr), 117 | .sdram_cs_n_pad_o (sdram_cs_n), 118 | .sdram_ras_pad_o (sdram_ras), 119 | .sdram_cas_pad_o (sdram_cas), 120 | .sdram_we_pad_o (sdram_we), 121 | .sdram_dq_pad_io (sdram_dq), 122 | .sdram_dqm_pad_o (sdram_dqm), 123 | .sdram_cke_pad_o (sdram_cke), 124 | .sdram_clk_pad_o (sdram_clk), 125 | //UART interface 126 | .uart0_srx_pad_i (), 127 | .uart0_stx_pad_o (uart_tx) 128 | ); 129 | 130 | mor1kx_monitor #(.LOG_DIR(".")) i_monitor(); 131 | 132 | //////////////////////////////////////////////////////////////////////// 133 | // 134 | // UART decoder 135 | // 136 | //////////////////////////////////////////////////////////////////////// 137 | 138 | //FIXME: Get correct baud rate from parameter 139 | uart_decoder 140 | #(.uart_baudrate_period_ns(8680)) 141 | uart_decoder0 142 | ( 143 | .clk(clk), 144 | .uart_tx(uart_tx) 145 | ); 146 | 147 | endmodule 148 | -------------------------------------------------------------------------------- /bench/spi_image.S: -------------------------------------------------------------------------------- 1 | l.movhi r0, 0 2 | l.movhi r3, hi(0xdeadbeef) 3 | l.ori r3, r3, lo(0xdeadbeef) 4 | l.nop 0x2 5 | l.nop 0x1 6 | l.nop 0x0 7 | 8 | -------------------------------------------------------------------------------- /bench/spi_image.vh: -------------------------------------------------------------------------------- 1 | @00080000 2 | 27 05 19 56 CE 90 18 D1 55 54 8F BC 00 00 00 18 3 | 00 00 01 00 00 00 01 00 68 3B 1D B6 05 15 01 00 4 | 73 70 69 5F 69 6D 61 67 65 2E 75 62 00 00 00 00 5 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6 | 18 00 00 00 18 60 DE AD A8 63 BE EF 15 00 00 02 7 | 15 00 00 01 15 00 00 00 8 | -------------------------------------------------------------------------------- /bench/test-defines.v: -------------------------------------------------------------------------------- 1 | `define TEST_NAME_STRING "mor1kx" 2 | `define MOR1KX_CPU_PIPELINE cappuccino 3 | -------------------------------------------------------------------------------- /bench/uart_decoder.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | //// //// 3 | //// ORPSoC Testbench UART Decoder //// 4 | //// //// 5 | //// Description //// 6 | //// ORPSoC Testbench UART output decoder //// 7 | //// //// 8 | //// To Do: //// 9 | //// //// 10 | //// //// 11 | //// Author(s): //// 12 | //// - jb, jb@orsoc.se //// 13 | //// //// 14 | //// //// 15 | ////////////////////////////////////////////////////////////////////// 16 | //// //// 17 | //// Copyright (C) 2009 Authors and OPENCORES.ORG //// 18 | //// //// 19 | //// This source file may be used and distributed without //// 20 | //// restriction provided that this copyright statement is not //// 21 | //// removed from the file and that any derivative work contains //// 22 | //// the original copyright notice and the associated disclaimer. //// 23 | //// //// 24 | //// This source file is free software; you can redistribute it //// 25 | //// and/or modify it under the terms of the GNU Lesser General //// 26 | //// Public License as published by the Free Software Foundation; //// 27 | //// either version 2.1 of the License, or (at your option) any //// 28 | //// later version. //// 29 | //// //// 30 | //// This source is distributed in the hope that it will be //// 31 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 32 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 33 | //// PURPOSE. See the GNU Lesser General Public License for more //// 34 | //// details. //// 35 | //// //// 36 | //// You should have received a copy of the GNU Lesser General //// 37 | //// Public License along with this source; if not, download it //// 38 | //// from http://www.opencores.org/lgpl.shtml //// 39 | //// //// 40 | ////////////////////////////////////////////////////////////////////// 41 | 42 | // Receieves and decodes 8-bit, 1 stop bit, no parity UART signals. 43 | `timescale 1ns/1ns 44 | module uart_decoder(clk, uart_tx); 45 | 46 | input clk; 47 | input uart_tx; 48 | 49 | // Default baud of 115200, period (ns) 50 | parameter uart_baudrate_period_ns = 8680; 51 | 52 | // Something to trigger the task 53 | always @(posedge clk) 54 | uart_decoder; 55 | 56 | task uart_decoder; 57 | reg [7:0] tx_byte; 58 | begin 59 | while (uart_tx !== 1'b1) 60 | @(uart_tx); 61 | // Wait for start bit 62 | while (uart_tx !== 1'b0) 63 | @(uart_tx); 64 | #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2)); 65 | tx_byte[0] = uart_tx; 66 | #uart_baudrate_period_ns; 67 | tx_byte[1] = uart_tx; 68 | #uart_baudrate_period_ns; 69 | tx_byte[2] = uart_tx; 70 | #uart_baudrate_period_ns; 71 | tx_byte[3] = uart_tx; 72 | #uart_baudrate_period_ns; 73 | tx_byte[4] = uart_tx; 74 | #uart_baudrate_period_ns; 75 | tx_byte[5] = uart_tx; 76 | #uart_baudrate_period_ns; 77 | tx_byte[6] = uart_tx; 78 | #uart_baudrate_period_ns; 79 | tx_byte[7] = uart_tx; 80 | #uart_baudrate_period_ns; 81 | //Check for stop bit 82 | if (uart_tx !== 1'b1) 83 | begin 84 | // Wait for return to idle 85 | while (uart_tx !== 1'b1) 86 | @(uart_tx); 87 | end 88 | // display the char 89 | $write("%c", tx_byte); 90 | end 91 | endtask // user_uart_read_byte 92 | 93 | endmodule // uart_decoder 94 | -------------------------------------------------------------------------------- /data/wb_intercon.conf: -------------------------------------------------------------------------------- 1 | ; or1k instruction bus master 2 | [master or1k_i] 3 | slaves = 4 | sdram_ibus 5 | rom0 6 | 7 | ; or1k data bus master 8 | [master dbus] 9 | slaves = 10 | sdram_dbus 11 | uart0 12 | gpio0 13 | 14 | ; SDRAM 15 | ; Have several ports with buffering features, 16 | ; so we split each port into a seperate slave 17 | [slave sdram_dbus] 18 | offset=0 19 | ; 32 MB 20 | size=0x2000000 21 | [slave sdram_ibus] 22 | offset=0 23 | ; 32 MB 24 | size=0x2000000 25 | 26 | [slave uart0] 27 | datawidth=8 28 | offset=0x90000000 29 | size=32 30 | 31 | [slave gpio0] 32 | datawidth=8 33 | offset=0x91000000 34 | size=2 35 | 36 | [slave rom0] 37 | offset=0xf0000000 38 | size=1024 39 | -------------------------------------------------------------------------------- /data/wb_intercon_dbg.conf: -------------------------------------------------------------------------------- 1 | [master or1k_d] 2 | slaves = 3 | dbus 4 | 5 | [master dbg] 6 | slaves = 7 | dbus 8 | 9 | [slave dbus] 10 | datawidth=32 11 | offset=0x00000000 12 | size=0x100000000 13 | -------------------------------------------------------------------------------- /rtl/verilog/clkgen.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // 3 | // clkgen 4 | // 5 | // Handles clock and reset generation for rest of design 6 | // 7 | // 8 | ////////////////////////////////////////////////////////////////////// 9 | //// //// 10 | //// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG //// 11 | //// //// 12 | //// This source file may be used and distributed without //// 13 | //// restriction provided that this copyright statement is not //// 14 | //// removed from the file and that any derivative work contains //// 15 | //// the original copyright notice and the associated disclaimer. //// 16 | //// //// 17 | //// This source file is free software; you can redistribute it //// 18 | //// and/or modify it under the terms of the GNU Lesser General //// 19 | //// Public License as published by the Free Software Foundation; //// 20 | //// either version 2.1 of the License, or (at your option) any //// 21 | //// later version. //// 22 | //// //// 23 | //// This source is distributed in the hope that it will be //// 24 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// 25 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 26 | //// PURPOSE. See the GNU Lesser General Public License for more //// 27 | //// details. //// 28 | //// //// 29 | //// You should have received a copy of the GNU Lesser General //// 30 | //// Public License along with this source; if not, download it //// 31 | //// from http://www.opencores.org/lgpl.shtml //// 32 | //// //// 33 | ////////////////////////////////////////////////////////////////////// 34 | 35 | module clkgen 36 | ( 37 | // Main clocks in, depending on board 38 | input sys_clk_pad_i, 39 | // Asynchronous, active low reset in 40 | input rst_n_pad_i, 41 | // Input reset - through a buffer, asynchronous 42 | output async_rst_o, 43 | 44 | // Wishbone clock and reset out 45 | output wb_clk_o, 46 | output wb_rst_o, 47 | 48 | // Main memory clocks 49 | output sdram_clk_o, 50 | output sdram_rst_o 51 | ); 52 | 53 | // First, deal with the asychronous reset 54 | wire async_rst; 55 | wire async_rst_n; 56 | 57 | assign async_rst_n = rst_n_pad_i; 58 | assign async_rst = ~async_rst_n; 59 | 60 | // Everyone likes active-high reset signals... 61 | assign async_rst_o = ~async_rst_n; 62 | 63 | // No PLL support - phase shift SDRAM clk using LUTs :vomit: 64 | /* 65 | localparam sdram_shift_count = 5; 66 | wire [sdram_shift_count:0] sdram_clk_shift; 67 | assign sdram_clk_shift[0] = sys_clk_pad_i; 68 | 69 | generate 70 | genvar ii; 71 | for (ii = 0; ii < sdram_shift_count; ii=ii+1) begin 72 | LUT4 #(.INIT(2)) lut4_i (.A(sdram_clk_shift[ii]), .B(1'b0), .C(1'b0), .D(1'b0), .Z(sdram_clk_shift[ii+1])); 73 | end 74 | endgenerate 75 | 76 | assign sdram_clk_o = sdram_clk_shift[sdram_shift_count]; 77 | */ 78 | assign sdram_clk_o = sys_clk_pad_i; 79 | 80 | // 81 | // Declare synchronous reset wires here 82 | // 83 | 84 | // An active-low synchronous reset signal (usually a PLL lock signal) 85 | wire sync_rst_n; 86 | 87 | wire pll_lock; 88 | 89 | assign wb_clk_o = sys_clk_pad_i; 90 | assign pll_lock = 1'b1; 91 | assign sync_rst_n = pll_lock; 92 | 93 | 94 | 95 | // 96 | // Reset generation 97 | // 98 | // 99 | 100 | // Reset generation for wishbone 101 | reg [15:0] wb_rst_shr; 102 | 103 | always @(posedge wb_clk_o or posedge async_rst) 104 | if (async_rst) 105 | wb_rst_shr <= 16'hffff; 106 | else 107 | wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)}; 108 | 109 | assign wb_rst_o = wb_rst_shr[15]; 110 | 111 | 112 | // Reset generation for SDRAM controller 113 | reg [15:0] sdram_rst_shr; 114 | 115 | always @(posedge sdram_clk_o or posedge async_rst) 116 | if (async_rst) 117 | sdram_rst_shr <= 16'hffff; 118 | else 119 | sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)}; 120 | 121 | assign sdram_rst_o = sdram_rst_shr[15]; 122 | 123 | endmodule // clkgen 124 | -------------------------------------------------------------------------------- /rtl/verilog/orpsoc_top.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////// 2 | // 3 | // ORPSoC top for de0_nano board 4 | // 5 | // Instantiates modules, depending on ORPSoC defines file 6 | // 7 | // Copyright (C) 2013 Stefan Kristiansson 8 | // $@ 11 | 12 | %.bin: %.elf 13 | or1k-elf-objcopy -O binary $< $@ 14 | 15 | %.elf: %.S 16 | or1k-elf-gcc -nostdlib $< -o $@ 17 | 18 | clean: 19 | rm spi_uimage_loader.elf $(TARGET).vh 20 | 21 | -------------------------------------------------------------------------------- /sw/clear_r3_and_jump_to_0x100.vh: -------------------------------------------------------------------------------- 1 | @00000000 2 | 18000000 A8200000 A8C00100 44003000 3 | 15000000 00000000 00000000 00000000 4 | -------------------------------------------------------------------------------- /sw/spi_uimage_loader.S: -------------------------------------------------------------------------------- 1 | // Dummy program 2 | 3 | #define GPIO 0x91000000 4 | 5 | boot_init: 6 | l.movhi r0, 0 7 | l.movhi r2, 0 8 | l.movhi r5, 0 9 | 10 | l.movhi r1, hi(GPIO) 11 | l.ori r1, r1, lo(GPIO) 12 | l.movhi r3, 0 13 | loop: 14 | l.sb 0(r1), r3 15 | l.addi r3, r3, 1 16 | l.lwz r4, 20(r5) 17 | l.sw 20(r5), r3 18 | l.j loop 19 | l.nop 20 | -------------------------------------------------------------------------------- /sw/spi_uimage_loader.vh: -------------------------------------------------------------------------------- 1 | @00000000 2 | 18000000 3 | 18400000 4 | 18A00000 5 | 18209100 6 | A8210000 7 | 18600000 8 | D8011800 9 | 9C630001 10 | 84850014 11 | D4051814 12 | 03FFFFFC 13 | 15000000 14 | 15 | -------------------------------------------------------------------------------- /sw/wb_rom_gen.py: -------------------------------------------------------------------------------- 1 | from struct import unpack 2 | import sys 3 | infile = sys.argv[1] 4 | offset = 64 5 | 6 | outfile = sys.stdout 7 | 8 | BLOCK = """@00000000 9 | {rom_contents} 10 | """ 11 | 12 | with open(infile, "rb") as f: 13 | word = f.read(4) 14 | addr = 0 15 | rom_contents = "" 16 | while word: 17 | data = unpack('>I', word)[0] 18 | if not data == 0: 19 | rom_contents += "{data:08X}\n".format(data=data) 20 | word = f.read(4) 21 | addr += 1 22 | outfile.write(BLOCK.format(rom_contents=rom_contents)) 23 | -------------------------------------------------------------------------------- /ulx3s.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | 3 | name : ::ulx3s:0 4 | 5 | filesets: 6 | rtl: 7 | files: 8 | - rtl/verilog/clkgen.v 9 | - rtl/verilog/orpsoc_top.v 10 | - rtl/verilog/wb_intercon.v 11 | - rtl/verilog/wb_intercon.vh : {is_include_file : true} 12 | - rtl/verilog/wb_intercon_dbg.v 13 | - rtl/verilog/wb_intercon_dbg.vh : {is_include_file : true} 14 | - rtl/verilog/timescale.v : {is_include_file : true} 15 | - sw/clear_r3_and_jump_to_0x100.vh : {copyto : bootrom/clear_r3_and_jump_to_0x100.vh, file_type : user} 16 | - sw/spi_uimage_loader.vh : {copyto : bootrom/spi_uimage_loader.vh, file_type : user} 17 | file_type : verilogSource 18 | depend: 19 | - adv_debug_sys 20 | - gpio 21 | - jtag_tap 22 | - mor1kx-4.1 23 | - or1k_bootloaders 24 | - uart16550 25 | - ">=wb_intercon-1.0" 26 | - ">=wb_sdram_ctrl-r4" 27 | 28 | tb: 29 | files: 30 | - bench/orpsoc_tb.v 31 | - bench/uart_decoder.v 32 | - bench/spi_image.vh : {copyto : spi_image.vh, file_type : user} 33 | - bench/test-defines.v : {is_include_file : true} 34 | file_type: verilogSource 35 | depend: 36 | - "yosys:techlibs:ecp5" 37 | - elf-loader 38 | - jtag_vpi-r2 39 | - mt48lc16m16a2 40 | - ">=vlog_tb_utils-1.0" 41 | 42 | targets: 43 | synth: 44 | default_tool : trellis 45 | filesets : [rtl] 46 | parameters : [bootrom_file] 47 | tools: 48 | trellis: 49 | nextpnr_options : 50 | - --45k 51 | - --basecfg 52 | - /usr/local/share/trellis/misc/basecfgs/empty_lfe5u-45f.config 53 | toplevel : orpsoc_top 54 | 55 | sim: 56 | default_tool : icarus 57 | filesets : [rtl, tb] 58 | parameters : [bootrom_file, spi_flash_file, trace_enable] 59 | tools: 60 | icarus: 61 | iverilog_options : [-DICARUS_SIM, -DSIM, -DSPEEDSIM] 62 | modelsim: 63 | vlog_options : [+define+SIM, +define+MODELSIM_SIM, -timescale 1ns/1ps] 64 | toplevel : orpsoc_tb 65 | 66 | parameters: 67 | bootrom_file: 68 | datatype : file 69 | description : Initial boot ROM contents (in Verilog hex format) 70 | paramtype : vlogparam 71 | 72 | spi_flash_file: 73 | datatype : file 74 | description : Initial SPI Flash contents (in Verilog hex format) 75 | paramtype : vlogparam 76 | 77 | trace_enable: 78 | datatype : bool 79 | description : Enable trace 80 | paramtype : plusarg 81 | -------------------------------------------------------------------------------- /utils/boot_linux.sh: -------------------------------------------------------------------------------- 1 | openocd -s /home/david/build/tutorials/tools/openocd/share/openocd/scripts -f /usr/share/openocd/scripts/interface/ftdi/um232h.cfg -c "transport select jtag; adapter_khz 5000; set TAP_TYPE MOHOR" -f board/or1k_generic.cfg -c "load_image /home/david/or-linux/vmlinux; reg npc 0x100; reg r3 0; resume" 2 | -------------------------------------------------------------------------------- /utils/program.sh: -------------------------------------------------------------------------------- 1 | ../prjtrellis/tools/bit_to_svf.py build/ulx3s_0/bld-trellis/ulx3s_0.bit ulx3s_0.svf 2 | /home/david/ulx3s-bin/usb-jtag/linux/openocd -f ../prjtrellis/misc/openocd/ulx3s.cfg -c "transport select jtag; init; svf ulx3s_0.svf; exit" 3 | --------------------------------------------------------------------------------