├── README.md ├── Top.v ├── build.sbt ├── fpga_swd_2 ├── fpga_swd.h └── fpga_swd_2.ino ├── icestick.pcf ├── project ├── build.properties ├── plugins.sbt ├── project │ └── target │ │ └── config-classes │ │ ├── $11933bf543191ceb629c$$anonfun$$sbtdef$1.class │ │ ├── $11933bf543191ceb629c$.class │ │ ├── $11933bf543191ceb629c.cache │ │ └── $11933bf543191ceb629c.class └── target │ ├── config-classes │ ├── $052a44782576165ef6f2$$anonfun$$sbtdef$1.class │ ├── $052a44782576165ef6f2$.class │ ├── $052a44782576165ef6f2.cache │ ├── $052a44782576165ef6f2.class │ ├── $1a69ab55e3e6247115a5$$anonfun$$sbtdef$1.class │ ├── $1a69ab55e3e6247115a5$.class │ ├── $1a69ab55e3e6247115a5.cache │ ├── $1a69ab55e3e6247115a5.class │ ├── $4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1$$anonfun$apply$1.class │ ├── $4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1.class │ ├── $4fbf35c5103c86f5cb40$.class │ ├── $4fbf35c5103c86f5cb40.cache │ ├── $4fbf35c5103c86f5cb40.class │ ├── $81eec9ef00c970e0dbd8$$anonfun$$sbtdef$1.class │ ├── $81eec9ef00c970e0dbd8$.class │ ├── $81eec9ef00c970e0dbd8.cache │ ├── $81eec9ef00c970e0dbd8.class │ ├── $ac15debf6f88ea3e5bfd$$anonfun$$sbtdef$1.class │ ├── $ac15debf6f88ea3e5bfd$.class │ ├── $ac15debf6f88ea3e5bfd.cache │ ├── $ac15debf6f88ea3e5bfd.class │ ├── $bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1$$anonfun$apply$1$$anonfun$apply$2.class │ ├── $bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1$$anonfun$apply$1.class │ ├── $bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1.class │ ├── $bf8e52aab5b52bddfe2e$.class │ ├── $bf8e52aab5b52bddfe2e.cache │ ├── $bf8e52aab5b52bddfe2e.class │ ├── $c992c1ac736499f537bc$$anonfun$$sbtdef$1.class │ ├── $c992c1ac736499f537bc$.class │ ├── $c992c1ac736499f537bc.cache │ ├── $c992c1ac736499f537bc.class │ ├── $d55667a6a7da34c38cfb$.class │ ├── $d55667a6a7da34c38cfb.cache │ ├── $d55667a6a7da34c38cfb.class │ ├── $d698e6ac6a1561aee690$$anonfun$$sbtdef$1.class │ ├── $d698e6ac6a1561aee690$.class │ ├── $d698e6ac6a1561aee690.cache │ └── $d698e6ac6a1561aee690.class │ ├── resolution-cache │ ├── default │ │ └── fpga_swd-build │ │ │ └── scala_2.10 │ │ │ └── sbt_0.13 │ │ │ └── 0.1-SNAPSHOT │ │ │ ├── resolved.xml.properties │ │ │ └── resolved.xml.xml │ └── reports │ │ ├── default-fpga_swd-build-compile-internal.xml │ │ ├── default-fpga_swd-build-compile.xml │ │ ├── default-fpga_swd-build-docs.xml │ │ ├── default-fpga_swd-build-optional.xml │ │ ├── default-fpga_swd-build-plugin.xml │ │ ├── default-fpga_swd-build-pom.xml │ │ ├── default-fpga_swd-build-provided.xml │ │ ├── default-fpga_swd-build-runtime-internal.xml │ │ ├── default-fpga_swd-build-runtime.xml │ │ ├── default-fpga_swd-build-scala-tool.xml │ │ ├── default-fpga_swd-build-sources.xml │ │ ├── default-fpga_swd-build-test-internal.xml │ │ ├── default-fpga_swd-build-test.xml │ │ ├── ivy-report.css │ │ └── ivy-report.xsl │ └── streams │ ├── $global │ ├── $global │ │ └── $global │ │ │ └── streams │ │ │ └── out │ ├── dependencyPositions │ │ └── $global │ │ │ └── streams │ │ │ └── update_cache_2.10 │ │ │ ├── input_dsp │ │ │ └── output_dsp │ ├── ivyConfiguration │ │ └── $global │ │ │ └── streams │ │ │ └── out │ ├── ivySbt │ │ └── $global │ │ │ └── streams │ │ │ └── out │ ├── projectDescriptors │ │ └── $global │ │ │ └── streams │ │ │ └── out │ ├── update │ │ └── $global │ │ │ └── streams │ │ │ ├── out │ │ │ └── update_cache_2.10 │ │ │ ├── inputs │ │ │ └── output │ └── updateSbtClassifiers │ │ └── $global │ │ └── streams │ │ └── out │ ├── compile │ ├── $global │ │ └── $global │ │ │ └── discoveredMainClasses │ │ │ └── data │ ├── compile │ │ └── $global │ │ │ └── streams │ │ │ └── out │ ├── compileIncremental │ │ └── $global │ │ │ └── streams │ │ │ ├── export │ │ │ └── out │ ├── copyResources │ │ └── $global │ │ │ └── streams │ │ │ ├── copy-resources │ │ │ └── out │ ├── dependencyClasspath │ │ └── $global │ │ │ └── streams │ │ │ └── export │ ├── exportedProducts │ │ └── $global │ │ │ └── streams │ │ │ └── export │ ├── externalDependencyClasspath │ │ └── $global │ │ │ └── streams │ │ │ └── export │ ├── internalDependencyClasspath │ │ └── $global │ │ │ └── streams │ │ │ └── export │ ├── managedClasspath │ │ └── $global │ │ │ └── streams │ │ │ └── export │ ├── unmanagedClasspath │ │ └── $global │ │ │ └── streams │ │ │ └── export │ └── unmanagedJars │ │ └── $global │ │ └── streams │ │ └── export │ └── runtime │ ├── dependencyClasspath │ └── $global │ │ └── streams │ │ └── export │ ├── exportedProducts │ └── $global │ │ └── streams │ │ └── export │ ├── externalDependencyClasspath │ └── $global │ │ └── streams │ │ └── export │ ├── fullClasspath │ └── $global │ │ └── streams │ │ └── export │ ├── internalDependencyClasspath │ └── $global │ │ └── streams │ │ └── export │ ├── managedClasspath │ └── $global │ │ └── streams │ │ └── export │ ├── unmanagedClasspath │ └── $global │ │ └── streams │ │ └── export │ └── unmanagedJars │ └── $global │ └── streams │ └── export └── src ├── main └── scala │ └── modules │ ├── BRAM.scala │ ├── DoubleBarrel.scala │ ├── FIFO.scala │ ├── Helpers.scala │ ├── SPIDecode.scala │ ├── SPIFastRead.scala │ ├── SPISlave.scala │ ├── SWD.scala │ └── SWDTop.scala └── test └── scala └── modules ├── CounterUnitTest.scala ├── DoubleBarrelUnitTest.scala ├── EdgeBufferUnitTest.scala ├── FifoUnitTest.scala ├── SPIDecodeUnitTest.scala ├── SPIFastReadUnitTest.scala ├── SPISlaveUnitTest.scala ├── SWDUnitTest.scala ├── TimerUnitTest.scala └── TopUnitTest.scala /README.md: -------------------------------------------------------------------------------- 1 | # FPGA_SWD 2 | fpga based SWD programmer 3 | 4 | This setup works up to above the max of SWD spec (50Mhz) 5 | 6 | currently verified working with at ATSAMD21G18 at 170 kB/sec. Programs the whole 256k in ~1.5sec. 7 | That may be the max for that chip or maybe limited a bit by my hardware setup. I'll try again once I get a proper PCB. 8 | -------------------------------------------------------------------------------- /Top.v: -------------------------------------------------------------------------------- 1 | `ifdef RANDOMIZE_GARBAGE_ASSIGN 2 | `define RANDOMIZE 3 | `endif 4 | `ifdef RANDOMIZE_INVALID_ASSIGN 5 | `define RANDOMIZE 6 | `endif 7 | `ifdef RANDOMIZE_REG_INIT 8 | `define RANDOMIZE 9 | `endif 10 | `ifdef RANDOMIZE_MEM_INIT 11 | `define RANDOMIZE 12 | `endif 13 | 14 | module EdgeBuffer( 15 | input clock, 16 | input io_in, 17 | output io_out, 18 | output io_rising, 19 | output io_falling 20 | ); 21 | reg r0; 22 | reg [31:0] _RAND_0; 23 | reg r1; 24 | reg [31:0] _RAND_1; 25 | reg r2; 26 | reg [31:0] _RAND_2; 27 | wire _T_10; 28 | wire _T_11; 29 | wire _T_13; 30 | wire _T_14; 31 | assign _T_10 = r2 == 1'h0; 32 | assign _T_11 = _T_10 & r1; 33 | assign _T_13 = r1 == 1'h0; 34 | assign _T_14 = r2 & _T_13; 35 | assign io_out = r1; 36 | assign io_rising = _T_11; 37 | assign io_falling = _T_14; 38 | `ifdef RANDOMIZE 39 | integer initvar; 40 | initial begin 41 | `ifndef verilator 42 | #0.002 begin end 43 | `endif 44 | `ifdef RANDOMIZE_REG_INIT 45 | _RAND_0 = {1{$random}}; 46 | r0 = _RAND_0[0:0]; 47 | `endif // RANDOMIZE_REG_INIT 48 | `ifdef RANDOMIZE_REG_INIT 49 | _RAND_1 = {1{$random}}; 50 | r1 = _RAND_1[0:0]; 51 | `endif // RANDOMIZE_REG_INIT 52 | `ifdef RANDOMIZE_REG_INIT 53 | _RAND_2 = {1{$random}}; 54 | r2 = _RAND_2[0:0]; 55 | `endif // RANDOMIZE_REG_INIT 56 | end 57 | `endif // RANDOMIZE 58 | always @(posedge clock) begin 59 | r0 <= io_in; 60 | r1 <= r0; 61 | r2 <= r1; 62 | end 63 | endmodule 64 | module Counter( 65 | input clock, 66 | input reset, 67 | input io_inc, 68 | output [4:0] io_tot 69 | ); 70 | reg [4:0] _T_9; 71 | reg [31:0] _RAND_0; 72 | wire [5:0] _T_10; 73 | wire [4:0] _T_11; 74 | wire [4:0] _GEN_1; 75 | assign _T_10 = _T_9 + 5'h1; 76 | assign _T_11 = _T_10[4:0]; 77 | assign _GEN_1 = io_inc ? _T_11 : _T_9; 78 | assign io_tot = _T_9; 79 | `ifdef RANDOMIZE 80 | integer initvar; 81 | initial begin 82 | `ifndef verilator 83 | #0.002 begin end 84 | `endif 85 | `ifdef RANDOMIZE_REG_INIT 86 | _RAND_0 = {1{$random}}; 87 | _T_9 = _RAND_0[4:0]; 88 | `endif // RANDOMIZE_REG_INIT 89 | end 90 | `endif // RANDOMIZE 91 | always @(posedge clock) begin 92 | if (reset) begin 93 | _T_9 <= 5'h0; 94 | end else begin 95 | if (io_inc) begin 96 | _T_9 <= _T_11; 97 | end 98 | end 99 | end 100 | endmodule 101 | module SPISlave( 102 | input clock, 103 | input reset, 104 | input io_MOSI, 105 | output io_MISO, 106 | input io_SCK, 107 | input io_SSEL, 108 | output io_DATA_READY, 109 | output [31:0] io_DATA, 110 | input [23:0] io_READ_OUT 111 | ); 112 | reg MOSI_DATA; 113 | reg [31:0] _RAND_0; 114 | wire SCKr_clock; 115 | wire SCKr_io_in; 116 | wire SCKr_io_out; 117 | wire SCKr_io_rising; 118 | wire SCKr_io_falling; 119 | wire SSELr_clock; 120 | wire SSELr_io_in; 121 | wire SSELr_io_out; 122 | wire SSELr_io_rising; 123 | wire SSELr_io_falling; 124 | reg [23:0] byte_data_sent; 125 | reg [31:0] _RAND_1; 126 | wire Counter_clock; 127 | wire Counter_reset; 128 | wire Counter_io_inc; 129 | wire [4:0] Counter_io_tot; 130 | wire _T_15; 131 | wire _T_16; 132 | reg _T_18; 133 | reg [31:0] _RAND_2; 134 | wire _T_20; 135 | wire _T_21; 136 | reg [31:0] _T_24; 137 | reg [31:0] _RAND_3; 138 | wire [32:0] _T_25; 139 | wire [32:0] _GEN_1; 140 | wire [22:0] _T_29; 141 | wire [23:0] _T_31; 142 | wire [23:0] _GEN_2; 143 | wire [23:0] _GEN_3; 144 | wire _T_32; 145 | EdgeBuffer SCKr ( 146 | .clock(SCKr_clock), 147 | .io_in(SCKr_io_in), 148 | .io_out(SCKr_io_out), 149 | .io_rising(SCKr_io_rising), 150 | .io_falling(SCKr_io_falling) 151 | ); 152 | EdgeBuffer SSELr ( 153 | .clock(SSELr_clock), 154 | .io_in(SSELr_io_in), 155 | .io_out(SSELr_io_out), 156 | .io_rising(SSELr_io_rising), 157 | .io_falling(SSELr_io_falling) 158 | ); 159 | Counter Counter ( 160 | .clock(Counter_clock), 161 | .reset(Counter_reset), 162 | .io_inc(Counter_io_inc), 163 | .io_tot(Counter_io_tot) 164 | ); 165 | assign _T_15 = Counter_io_tot == 5'h1f; 166 | assign _T_16 = _T_15 & SCKr_io_rising; 167 | assign _T_20 = SSELr_io_out == 1'h0; 168 | assign _T_21 = SCKr_io_rising & _T_20; 169 | assign _T_25 = {_T_24,MOSI_DATA}; 170 | assign _GEN_1 = _T_21 ? _T_25 : {{1'd0}, _T_24}; 171 | assign _T_29 = byte_data_sent[22:0]; 172 | assign _T_31 = {_T_29,1'h0}; 173 | assign _GEN_2 = _T_21 ? _T_31 : byte_data_sent; 174 | assign _GEN_3 = SSELr_io_falling ? io_READ_OUT : _GEN_2; 175 | assign _T_32 = byte_data_sent[23]; 176 | assign io_MISO = _T_32; 177 | assign io_DATA_READY = _T_18; 178 | assign io_DATA = _T_24; 179 | assign SCKr_io_in = io_SCK; 180 | assign SCKr_clock = clock; 181 | assign SSELr_io_in = io_SSEL; 182 | assign SSELr_clock = clock; 183 | assign Counter_io_inc = SCKr_io_rising; 184 | assign Counter_clock = clock; 185 | assign Counter_reset = SSELr_io_out; 186 | `ifdef RANDOMIZE 187 | integer initvar; 188 | initial begin 189 | `ifndef verilator 190 | #0.002 begin end 191 | `endif 192 | `ifdef RANDOMIZE_REG_INIT 193 | _RAND_0 = {1{$random}}; 194 | MOSI_DATA = _RAND_0[0:0]; 195 | `endif // RANDOMIZE_REG_INIT 196 | `ifdef RANDOMIZE_REG_INIT 197 | _RAND_1 = {1{$random}}; 198 | byte_data_sent = _RAND_1[23:0]; 199 | `endif // RANDOMIZE_REG_INIT 200 | `ifdef RANDOMIZE_REG_INIT 201 | _RAND_2 = {1{$random}}; 202 | _T_18 = _RAND_2[0:0]; 203 | `endif // RANDOMIZE_REG_INIT 204 | `ifdef RANDOMIZE_REG_INIT 205 | _RAND_3 = {1{$random}}; 206 | _T_24 = _RAND_3[31:0]; 207 | `endif // RANDOMIZE_REG_INIT 208 | end 209 | `endif // RANDOMIZE 210 | always @(posedge clock) begin 211 | MOSI_DATA <= io_MOSI; 212 | if (reset) begin 213 | byte_data_sent <= 24'h0; 214 | end else begin 215 | if (SSELr_io_falling) begin 216 | byte_data_sent <= io_READ_OUT; 217 | end else begin 218 | if (_T_21) begin 219 | byte_data_sent <= _T_31; 220 | end 221 | end 222 | end 223 | _T_18 <= _T_16; 224 | if (reset) begin 225 | _T_24 <= 32'h0; 226 | end else begin 227 | _T_24 <= _GEN_1[31:0]; 228 | end 229 | end 230 | endmodule 231 | module SPIDecode( 232 | input clock, 233 | input [27:0] io_dataIn, 234 | output [23:0] io_dataOut, 235 | output [2:0] io_addr, 236 | input io_trigger, 237 | output io_wclk 238 | ); 239 | wire [2:0] _T_9; 240 | wire [23:0] _T_10; 241 | wire _T_11; 242 | wire _T_12; 243 | reg _T_14; 244 | reg [31:0] _RAND_0; 245 | assign _T_9 = io_dataIn[26:24]; 246 | assign _T_10 = io_dataIn[23:0]; 247 | assign _T_11 = io_dataIn[27]; 248 | assign _T_12 = _T_11 & io_trigger; 249 | assign io_dataOut = _T_10; 250 | assign io_addr = _T_9; 251 | assign io_wclk = _T_14; 252 | `ifdef RANDOMIZE 253 | integer initvar; 254 | initial begin 255 | `ifndef verilator 256 | #0.002 begin end 257 | `endif 258 | `ifdef RANDOMIZE_REG_INIT 259 | _RAND_0 = {1{$random}}; 260 | _T_14 = _RAND_0[0:0]; 261 | `endif // RANDOMIZE_REG_INIT 262 | end 263 | `endif // RANDOMIZE 264 | always @(posedge clock) begin 265 | _T_14 <= _T_12; 266 | end 267 | endmodule 268 | module StatusReg( 269 | input clock, 270 | input reset, 271 | input io_en, 272 | input io_din, 273 | output [1:0] io_dout, 274 | input io_done, 275 | input io_error 276 | ); 277 | reg x; 278 | reg [31:0] _RAND_0; 279 | wire _GEN_0; 280 | reg [1:0] out; 281 | reg [31:0] _RAND_1; 282 | wire [1:0] _T_11; 283 | wire [2:0] _T_12; 284 | assign _GEN_0 = io_en ? io_din : x; 285 | assign _T_11 = {io_done,x}; 286 | assign _T_12 = {io_error,_T_11}; 287 | assign io_dout = out; 288 | `ifdef RANDOMIZE 289 | integer initvar; 290 | initial begin 291 | `ifndef verilator 292 | #0.002 begin end 293 | `endif 294 | `ifdef RANDOMIZE_REG_INIT 295 | _RAND_0 = {1{$random}}; 296 | x = _RAND_0[0:0]; 297 | `endif // RANDOMIZE_REG_INIT 298 | `ifdef RANDOMIZE_REG_INIT 299 | _RAND_1 = {1{$random}}; 300 | out = _RAND_1[1:0]; 301 | `endif // RANDOMIZE_REG_INIT 302 | end 303 | `endif // RANDOMIZE 304 | always @(posedge clock) begin 305 | if (reset) begin 306 | x <= 1'h0; 307 | end else begin 308 | if (io_en) begin 309 | x <= io_din; 310 | end 311 | end 312 | if (reset) begin 313 | out <= 2'h0; 314 | end else begin 315 | out <= _T_12[1:0]; 316 | end 317 | end 318 | endmodule 319 | module AddrReg( 320 | input clock, 321 | input reset, 322 | input io_en, 323 | input [23:0] io_din, 324 | output [23:0] io_dout 325 | ); 326 | reg [23:0] x; 327 | reg [31:0] _RAND_0; 328 | wire [23:0] _GEN_0; 329 | assign _GEN_0 = io_en ? io_din : x; 330 | assign io_dout = x; 331 | `ifdef RANDOMIZE 332 | integer initvar; 333 | initial begin 334 | `ifndef verilator 335 | #0.002 begin end 336 | `endif 337 | `ifdef RANDOMIZE_REG_INIT 338 | _RAND_0 = {1{$random}}; 339 | x = _RAND_0[23:0]; 340 | `endif // RANDOMIZE_REG_INIT 341 | end 342 | `endif // RANDOMIZE 343 | always @(posedge clock) begin 344 | if (reset) begin 345 | x <= 24'h0; 346 | end else begin 347 | if (io_en) begin 348 | x <= io_din; 349 | end 350 | end 351 | end 352 | endmodule 353 | module LengthReg( 354 | input clock, 355 | input reset, 356 | input io_en, 357 | input io_dec, 358 | input [23:0] io_din, 359 | output [23:0] io_dout 360 | ); 361 | reg [23:0] x; 362 | reg [31:0] _RAND_0; 363 | wire [23:0] _GEN_0; 364 | wire [24:0] _T_9; 365 | wire [24:0] _T_10; 366 | wire [23:0] _T_11; 367 | wire [23:0] _GEN_1; 368 | assign _GEN_0 = io_en ? io_din : x; 369 | assign _T_9 = x - 24'h1; 370 | assign _T_10 = $unsigned(_T_9); 371 | assign _T_11 = _T_10[23:0]; 372 | assign _GEN_1 = io_dec ? _T_11 : _GEN_0; 373 | assign io_dout = x; 374 | `ifdef RANDOMIZE 375 | integer initvar; 376 | initial begin 377 | `ifndef verilator 378 | #0.002 begin end 379 | `endif 380 | `ifdef RANDOMIZE_REG_INIT 381 | _RAND_0 = {1{$random}}; 382 | x = _RAND_0[23:0]; 383 | `endif // RANDOMIZE_REG_INIT 384 | end 385 | `endif // RANDOMIZE 386 | always @(posedge clock) begin 387 | if (reset) begin 388 | x <= 24'h0; 389 | end else begin 390 | if (io_dec) begin 391 | x <= _T_11; 392 | end else begin 393 | if (io_en) begin 394 | x <= io_din; 395 | end 396 | end 397 | end 398 | end 399 | endmodule 400 | module ClkDivReg( 401 | input clock, 402 | input reset, 403 | input io_en, 404 | input [3:0] io_din, 405 | output [3:0] io_dout 406 | ); 407 | reg [3:0] x; 408 | reg [31:0] _RAND_0; 409 | wire [3:0] _GEN_0; 410 | assign _GEN_0 = io_en ? io_din : x; 411 | assign io_dout = x; 412 | `ifdef RANDOMIZE 413 | integer initvar; 414 | initial begin 415 | `ifndef verilator 416 | #0.002 begin end 417 | `endif 418 | `ifdef RANDOMIZE_REG_INIT 419 | _RAND_0 = {1{$random}}; 420 | x = _RAND_0[3:0]; 421 | `endif // RANDOMIZE_REG_INIT 422 | end 423 | `endif // RANDOMIZE 424 | always @(posedge clock) begin 425 | if (reset) begin 426 | x <= 4'h0; 427 | end else begin 428 | if (io_en) begin 429 | x <= io_din; 430 | end 431 | end 432 | end 433 | endmodule 434 | module Counter_1( 435 | input clock, 436 | input reset, 437 | input io_inc, 438 | output [1:0] io_tot 439 | ); 440 | reg [1:0] _T_9; 441 | reg [31:0] _RAND_0; 442 | wire [2:0] _T_10; 443 | wire [1:0] _T_11; 444 | wire _T_12; 445 | wire [1:0] _T_14; 446 | wire [1:0] _GEN_1; 447 | assign _T_10 = _T_9 + 2'h1; 448 | assign _T_11 = _T_10[1:0]; 449 | assign _T_12 = _T_11 > 2'h2; 450 | assign _T_14 = _T_12 ? 2'h0 : _T_11; 451 | assign _GEN_1 = io_inc ? _T_14 : _T_9; 452 | assign io_tot = _T_9; 453 | `ifdef RANDOMIZE 454 | integer initvar; 455 | initial begin 456 | `ifndef verilator 457 | #0.002 begin end 458 | `endif 459 | `ifdef RANDOMIZE_REG_INIT 460 | _RAND_0 = {1{$random}}; 461 | _T_9 = _RAND_0[1:0]; 462 | `endif // RANDOMIZE_REG_INIT 463 | end 464 | `endif // RANDOMIZE 465 | always @(posedge clock) begin 466 | if (reset) begin 467 | _T_9 <= 2'h0; 468 | end else begin 469 | if (io_inc) begin 470 | if (_T_12) begin 471 | _T_9 <= 2'h0; 472 | end else begin 473 | _T_9 <= _T_11; 474 | end 475 | end 476 | end 477 | end 478 | endmodule 479 | module Counter_2( 480 | input clock, 481 | input reset, 482 | input io_inc, 483 | output [5:0] io_tot 484 | ); 485 | reg [5:0] _T_9; 486 | reg [31:0] _RAND_0; 487 | wire [6:0] _T_10; 488 | wire [5:0] _T_11; 489 | wire _T_12; 490 | wire [5:0] _T_14; 491 | wire [5:0] _GEN_1; 492 | assign _T_10 = _T_9 + 6'h1; 493 | assign _T_11 = _T_10[5:0]; 494 | assign _T_12 = _T_11 > 6'h29; 495 | assign _T_14 = _T_12 ? 6'h0 : _T_11; 496 | assign _GEN_1 = io_inc ? _T_14 : _T_9; 497 | assign io_tot = _T_9; 498 | `ifdef RANDOMIZE 499 | integer initvar; 500 | initial begin 501 | `ifndef verilator 502 | #0.002 begin end 503 | `endif 504 | `ifdef RANDOMIZE_REG_INIT 505 | _RAND_0 = {1{$random}}; 506 | _T_9 = _RAND_0[5:0]; 507 | `endif // RANDOMIZE_REG_INIT 508 | end 509 | `endif // RANDOMIZE 510 | always @(posedge clock) begin 511 | if (reset) begin 512 | _T_9 <= 6'h0; 513 | end else begin 514 | if (io_inc) begin 515 | if (_T_12) begin 516 | _T_9 <= 6'h0; 517 | end else begin 518 | _T_9 <= _T_11; 519 | end 520 | end 521 | end 522 | end 523 | endmodule 524 | module SPIFastRead( 525 | input clock, 526 | output io_MOSI, 527 | input io_MISO, 528 | output io_SCK, 529 | output io_DATA_READY, 530 | output [31:0] io_DATA, 531 | input [23:0] io_ADDR, 532 | input io_EN, 533 | input io_enqRdy 534 | ); 535 | wire _T_11; 536 | reg _T_14; 537 | reg [31:0] _RAND_0; 538 | reg _T_18; 539 | reg [31:0] _RAND_1; 540 | reg _T_21; 541 | reg [31:0] _RAND_2; 542 | wire Counter_clock; 543 | wire Counter_reset; 544 | wire Counter_io_inc; 545 | wire [1:0] Counter_io_tot; 546 | wire _T_24; 547 | wire _T_25; 548 | wire _GEN_1; 549 | wire EdgeBuffer_clock; 550 | wire EdgeBuffer_io_in; 551 | wire EdgeBuffer_io_out; 552 | wire EdgeBuffer_io_rising; 553 | wire EdgeBuffer_io_falling; 554 | wire Counter_1_clock; 555 | wire Counter_1_reset; 556 | wire Counter_1_io_inc; 557 | wire [5:0] Counter_1_io_tot; 558 | wire Counter_2_clock; 559 | wire Counter_2_reset; 560 | wire Counter_2_io_inc; 561 | wire [4:0] Counter_2_io_tot; 562 | wire _T_29; 563 | wire _T_30; 564 | reg _T_32; 565 | reg [31:0] _RAND_3; 566 | reg [23:0] _T_35; 567 | reg [31:0] _RAND_4; 568 | wire _T_36; 569 | wire _T_39; 570 | wire [23:0] _GEN_2; 571 | wire [22:0] _T_43; 572 | wire [23:0] _T_45; 573 | wire _T_47; 574 | wire [23:0] _GEN_3; 575 | wire _T_49; 576 | wire _GEN_4; 577 | wire [23:0] _GEN_5; 578 | wire _GEN_6; 579 | wire _T_50; 580 | wire [23:0] _GEN_8; 581 | wire _GEN_9; 582 | reg [31:0] _T_55; 583 | reg [31:0] _RAND_5; 584 | wire [32:0] _T_56; 585 | wire [32:0] _GEN_11; 586 | wire _GEN_12; 587 | wire [31:0] _GEN_13; 588 | wire _GEN_14; 589 | Counter_1 Counter ( 590 | .clock(Counter_clock), 591 | .reset(Counter_reset), 592 | .io_inc(Counter_io_inc), 593 | .io_tot(Counter_io_tot) 594 | ); 595 | EdgeBuffer EdgeBuffer ( 596 | .clock(EdgeBuffer_clock), 597 | .io_in(EdgeBuffer_io_in), 598 | .io_out(EdgeBuffer_io_out), 599 | .io_rising(EdgeBuffer_io_rising), 600 | .io_falling(EdgeBuffer_io_falling) 601 | ); 602 | Counter_2 Counter_1 ( 603 | .clock(Counter_1_clock), 604 | .reset(Counter_1_reset), 605 | .io_inc(Counter_1_io_inc), 606 | .io_tot(Counter_1_io_tot) 607 | ); 608 | Counter Counter_2 ( 609 | .clock(Counter_2_clock), 610 | .reset(Counter_2_reset), 611 | .io_inc(Counter_2_io_inc), 612 | .io_tot(Counter_2_io_tot) 613 | ); 614 | assign _T_11 = ~ io_EN; 615 | assign _T_24 = Counter_io_tot == 2'h2; 616 | assign _T_25 = ~ _T_21; 617 | assign _GEN_1 = _T_24 ? _T_25 : _T_21; 618 | assign _T_29 = Counter_2_io_tot == 5'h1f; 619 | assign _T_30 = _T_29 & EdgeBuffer_io_rising; 620 | assign _T_36 = _T_18 == 1'h0; 621 | assign _T_39 = Counter_1_io_tot == 6'h0; 622 | assign _GEN_2 = _T_39 ? 24'hb0000 : _T_35; 623 | assign _T_43 = _T_35[22:0]; 624 | assign _T_45 = {_T_43,1'h0}; 625 | assign _T_47 = Counter_1_io_tot == 6'h8; 626 | assign _GEN_3 = _T_47 ? io_ADDR : _T_45; 627 | assign _T_49 = Counter_1_io_tot == 6'h28; 628 | assign _GEN_4 = _T_49 ? 1'h1 : _T_18; 629 | assign _GEN_5 = EdgeBuffer_io_falling ? _GEN_3 : _GEN_2; 630 | assign _GEN_6 = EdgeBuffer_io_falling ? _GEN_4 : _T_18; 631 | assign _T_50 = _T_35[23]; 632 | assign _GEN_8 = _T_36 ? _GEN_5 : _T_35; 633 | assign _GEN_9 = _T_36 ? _GEN_6 : _T_18; 634 | assign _T_56 = {_T_55,_T_14}; 635 | assign _GEN_11 = EdgeBuffer_io_rising ? _T_56 : {{1'd0}, _T_55}; 636 | assign _GEN_12 = _T_18 ? EdgeBuffer_io_rising : 1'h0; 637 | assign _GEN_13 = _T_18 ? _T_55 : 32'h0; 638 | assign _GEN_14 = _T_18 ? 1'h0 : _T_50; 639 | assign io_MOSI = _GEN_14; 640 | assign io_SCK = EdgeBuffer_io_out; 641 | assign io_DATA_READY = _T_32; 642 | assign io_DATA = _GEN_13; 643 | assign Counter_io_inc = io_enqRdy; 644 | assign Counter_clock = clock; 645 | assign Counter_reset = _T_11; 646 | assign EdgeBuffer_io_in = _T_21; 647 | assign EdgeBuffer_clock = clock; 648 | assign Counter_1_io_inc = EdgeBuffer_io_rising; 649 | assign Counter_1_clock = clock; 650 | assign Counter_1_reset = _T_11; 651 | assign Counter_2_io_inc = _GEN_12; 652 | assign Counter_2_clock = clock; 653 | assign Counter_2_reset = _T_11; 654 | `ifdef RANDOMIZE 655 | integer initvar; 656 | initial begin 657 | `ifndef verilator 658 | #0.002 begin end 659 | `endif 660 | `ifdef RANDOMIZE_REG_INIT 661 | _RAND_0 = {1{$random}}; 662 | _T_14 = _RAND_0[0:0]; 663 | `endif // RANDOMIZE_REG_INIT 664 | `ifdef RANDOMIZE_REG_INIT 665 | _RAND_1 = {1{$random}}; 666 | _T_18 = _RAND_1[0:0]; 667 | `endif // RANDOMIZE_REG_INIT 668 | `ifdef RANDOMIZE_REG_INIT 669 | _RAND_2 = {1{$random}}; 670 | _T_21 = _RAND_2[0:0]; 671 | `endif // RANDOMIZE_REG_INIT 672 | `ifdef RANDOMIZE_REG_INIT 673 | _RAND_3 = {1{$random}}; 674 | _T_32 = _RAND_3[0:0]; 675 | `endif // RANDOMIZE_REG_INIT 676 | `ifdef RANDOMIZE_REG_INIT 677 | _RAND_4 = {1{$random}}; 678 | _T_35 = _RAND_4[23:0]; 679 | `endif // RANDOMIZE_REG_INIT 680 | `ifdef RANDOMIZE_REG_INIT 681 | _RAND_5 = {1{$random}}; 682 | _T_55 = _RAND_5[31:0]; 683 | `endif // RANDOMIZE_REG_INIT 684 | end 685 | `endif // RANDOMIZE 686 | always @(posedge clock) begin 687 | _T_14 <= io_MISO; 688 | if (_T_11) begin 689 | _T_18 <= 1'h0; 690 | end else begin 691 | if (_T_36) begin 692 | if (EdgeBuffer_io_falling) begin 693 | if (_T_49) begin 694 | _T_18 <= 1'h1; 695 | end 696 | end 697 | end 698 | end 699 | if (_T_11) begin 700 | _T_21 <= 1'h0; 701 | end else begin 702 | if (_T_24) begin 703 | _T_21 <= _T_25; 704 | end 705 | end 706 | _T_32 <= _T_30; 707 | if (_T_11) begin 708 | _T_35 <= 24'h0; 709 | end else begin 710 | if (_T_36) begin 711 | if (EdgeBuffer_io_falling) begin 712 | if (_T_47) begin 713 | _T_35 <= io_ADDR; 714 | end else begin 715 | _T_35 <= _T_45; 716 | end 717 | end else begin 718 | if (_T_39) begin 719 | _T_35 <= 24'hb0000; 720 | end 721 | end 722 | end 723 | end 724 | if (_T_11) begin 725 | _T_55 <= 32'h0; 726 | end else begin 727 | _T_55 <= _GEN_11[31:0]; 728 | end 729 | end 730 | endmodule 731 | module Fifo( 732 | input clock, 733 | input reset, 734 | input io_enqVal, 735 | output io_enqRdy, 736 | output io_deqVal, 737 | input io_deqRdy, 738 | input [31:0] io_enqDat, 739 | output [31:0] io_deqDat 740 | ); 741 | reg [7:0] enqPtr; 742 | reg [31:0] _RAND_0; 743 | reg [7:0] deqPtr; 744 | reg [31:0] _RAND_1; 745 | reg isFull; 746 | reg [31:0] _RAND_2; 747 | wire doEnq; 748 | wire doDeq; 749 | wire _T_15; 750 | wire _T_16; 751 | wire isEmpty; 752 | wire [8:0] _T_18; 753 | wire [7:0] deqPtrInc; 754 | wire [8:0] _T_20; 755 | wire [7:0] enqPtrInc; 756 | wire _T_21; 757 | wire _T_22; 758 | wire _T_23; 759 | wire _T_24; 760 | wire _T_26; 761 | wire _T_28; 762 | wire isFullNext; 763 | wire [7:0] _T_29; 764 | wire [7:0] _T_30; 765 | wire [15:0] SB_RAM40_4K_MASK; 766 | wire SB_RAM40_4K_WE; 767 | wire [15:0] SB_RAM40_4K_WDATA; 768 | wire SB_RAM40_4K_WCLKE; 769 | wire SB_RAM40_4K_WCLK; 770 | wire [7:0] SB_RAM40_4K_WADDR; 771 | wire SB_RAM40_4K_RE; 772 | wire SB_RAM40_4K_RCLKE; 773 | wire SB_RAM40_4K_RCLK; 774 | wire [7:0] SB_RAM40_4K_RADDR; 775 | wire [15:0] SB_RAM40_4K_RDATA; 776 | wire [15:0] SB_RAM40_4K_1_MASK; 777 | wire SB_RAM40_4K_1_WE; 778 | wire [15:0] SB_RAM40_4K_1_WDATA; 779 | wire SB_RAM40_4K_1_WCLKE; 780 | wire SB_RAM40_4K_1_WCLK; 781 | wire [7:0] SB_RAM40_4K_1_WADDR; 782 | wire SB_RAM40_4K_1_RE; 783 | wire SB_RAM40_4K_1_RCLKE; 784 | wire SB_RAM40_4K_1_RCLK; 785 | wire [7:0] SB_RAM40_4K_1_RADDR; 786 | wire [15:0] SB_RAM40_4K_1_RDATA; 787 | wire [15:0] _T_39; 788 | wire [15:0] _T_40; 789 | wire [31:0] _T_41; 790 | wire _T_45; 791 | SB_RAM40_4K #(.READ_MODE(0), .WRITE_MODE(0)) SB_RAM40_4K ( 792 | .MASK(SB_RAM40_4K_MASK), 793 | .WE(SB_RAM40_4K_WE), 794 | .WDATA(SB_RAM40_4K_WDATA), 795 | .WCLKE(SB_RAM40_4K_WCLKE), 796 | .WCLK(SB_RAM40_4K_WCLK), 797 | .WADDR(SB_RAM40_4K_WADDR), 798 | .RE(SB_RAM40_4K_RE), 799 | .RCLKE(SB_RAM40_4K_RCLKE), 800 | .RCLK(SB_RAM40_4K_RCLK), 801 | .RADDR(SB_RAM40_4K_RADDR), 802 | .RDATA(SB_RAM40_4K_RDATA) 803 | ); 804 | SB_RAM40_4K #(.READ_MODE(0), .WRITE_MODE(0)) SB_RAM40_4K_1 ( 805 | .MASK(SB_RAM40_4K_1_MASK), 806 | .WE(SB_RAM40_4K_1_WE), 807 | .WDATA(SB_RAM40_4K_1_WDATA), 808 | .WCLKE(SB_RAM40_4K_1_WCLKE), 809 | .WCLK(SB_RAM40_4K_1_WCLK), 810 | .WADDR(SB_RAM40_4K_1_WADDR), 811 | .RE(SB_RAM40_4K_1_RE), 812 | .RCLKE(SB_RAM40_4K_1_RCLKE), 813 | .RCLK(SB_RAM40_4K_1_RCLK), 814 | .RADDR(SB_RAM40_4K_1_RADDR), 815 | .RDATA(SB_RAM40_4K_1_RDATA) 816 | ); 817 | assign doEnq = io_enqRdy & io_enqVal; 818 | assign doDeq = io_deqRdy & io_deqVal; 819 | assign _T_15 = isFull == 1'h0; 820 | assign _T_16 = enqPtr == deqPtr; 821 | assign isEmpty = _T_15 & _T_16; 822 | assign _T_18 = deqPtr + 8'h1; 823 | assign deqPtrInc = _T_18[7:0]; 824 | assign _T_20 = enqPtr + 8'h1; 825 | assign enqPtrInc = _T_20[7:0]; 826 | assign _T_21 = ~ doDeq; 827 | assign _T_22 = doEnq & _T_21; 828 | assign _T_23 = enqPtrInc == deqPtr; 829 | assign _T_24 = _T_22 & _T_23; 830 | assign _T_26 = doDeq & isFull; 831 | assign _T_28 = _T_26 ? 1'h0 : isFull; 832 | assign isFullNext = _T_24 ? 1'h1 : _T_28; 833 | assign _T_29 = doEnq ? enqPtrInc : enqPtr; 834 | assign _T_30 = doDeq ? deqPtrInc : deqPtr; 835 | assign _T_39 = io_enqDat[31:16]; 836 | assign _T_40 = io_enqDat[15:0]; 837 | assign _T_41 = {SB_RAM40_4K_RDATA,SB_RAM40_4K_1_RDATA}; 838 | assign _T_45 = isEmpty == 1'h0; 839 | assign io_enqRdy = _T_15; 840 | assign io_deqVal = _T_45; 841 | assign io_deqDat = _T_41; 842 | assign SB_RAM40_4K_MASK = 16'h0; 843 | assign SB_RAM40_4K_WE = doEnq; 844 | assign SB_RAM40_4K_WDATA = _T_39; 845 | assign SB_RAM40_4K_WCLKE = 1'h1; 846 | assign SB_RAM40_4K_WCLK = clock; 847 | assign SB_RAM40_4K_WADDR = enqPtr; 848 | assign SB_RAM40_4K_RE = 1'h1; 849 | assign SB_RAM40_4K_RCLKE = 1'h1; 850 | assign SB_RAM40_4K_RCLK = clock; 851 | assign SB_RAM40_4K_RADDR = deqPtr; 852 | assign SB_RAM40_4K_1_MASK = 16'h0; 853 | assign SB_RAM40_4K_1_WE = doEnq; 854 | assign SB_RAM40_4K_1_WDATA = _T_40; 855 | assign SB_RAM40_4K_1_WCLKE = 1'h1; 856 | assign SB_RAM40_4K_1_WCLK = clock; 857 | assign SB_RAM40_4K_1_WADDR = enqPtr; 858 | assign SB_RAM40_4K_1_RE = 1'h1; 859 | assign SB_RAM40_4K_1_RCLKE = 1'h1; 860 | assign SB_RAM40_4K_1_RCLK = clock; 861 | assign SB_RAM40_4K_1_RADDR = deqPtr; 862 | `ifdef RANDOMIZE 863 | integer initvar; 864 | initial begin 865 | `ifndef verilator 866 | #0.002 begin end 867 | `endif 868 | `ifdef RANDOMIZE_REG_INIT 869 | _RAND_0 = {1{$random}}; 870 | enqPtr = _RAND_0[7:0]; 871 | `endif // RANDOMIZE_REG_INIT 872 | `ifdef RANDOMIZE_REG_INIT 873 | _RAND_1 = {1{$random}}; 874 | deqPtr = _RAND_1[7:0]; 875 | `endif // RANDOMIZE_REG_INIT 876 | `ifdef RANDOMIZE_REG_INIT 877 | _RAND_2 = {1{$random}}; 878 | isFull = _RAND_2[0:0]; 879 | `endif // RANDOMIZE_REG_INIT 880 | end 881 | `endif // RANDOMIZE 882 | always @(posedge clock) begin 883 | if (reset) begin 884 | enqPtr <= 8'h0; 885 | end else begin 886 | if (doEnq) begin 887 | enqPtr <= enqPtrInc; 888 | end 889 | end 890 | if (reset) begin 891 | deqPtr <= 8'h0; 892 | end else begin 893 | if (doDeq) begin 894 | deqPtr <= deqPtrInc; 895 | end 896 | end 897 | if (reset) begin 898 | isFull <= 1'h0; 899 | end else begin 900 | if (_T_24) begin 901 | isFull <= 1'h1; 902 | end else begin 903 | if (_T_26) begin 904 | isFull <= 1'h0; 905 | end 906 | end 907 | end 908 | end 909 | endmodule 910 | module Counter_4( 911 | input clock, 912 | input reset, 913 | input io_inc, 914 | output [8:0] io_tot 915 | ); 916 | reg [8:0] _T_9; 917 | reg [31:0] _RAND_0; 918 | wire [9:0] _T_10; 919 | wire [8:0] _T_11; 920 | wire _T_12; 921 | wire [8:0] _T_14; 922 | wire [8:0] _GEN_1; 923 | assign _T_10 = _T_9 + 9'h1; 924 | assign _T_11 = _T_10[8:0]; 925 | assign _T_12 = _T_11 > 9'h100; 926 | assign _T_14 = _T_12 ? 9'h0 : _T_11; 927 | assign _GEN_1 = io_inc ? _T_14 : _T_9; 928 | assign io_tot = _T_9; 929 | `ifdef RANDOMIZE 930 | integer initvar; 931 | initial begin 932 | `ifndef verilator 933 | #0.002 begin end 934 | `endif 935 | `ifdef RANDOMIZE_REG_INIT 936 | _RAND_0 = {1{$random}}; 937 | _T_9 = _RAND_0[8:0]; 938 | `endif // RANDOMIZE_REG_INIT 939 | end 940 | `endif // RANDOMIZE 941 | always @(posedge clock) begin 942 | if (reset) begin 943 | _T_9 <= 9'h0; 944 | end else begin 945 | if (io_inc) begin 946 | if (_T_12) begin 947 | _T_9 <= 9'h0; 948 | end else begin 949 | _T_9 <= _T_11; 950 | end 951 | end 952 | end 953 | end 954 | endmodule 955 | module DoubleBarrel( 956 | input clock, 957 | input reset, 958 | input [31:0] io_ADDR_IN, 959 | input io_ADDR_SET, 960 | input io_DATA_READY, 961 | input [31:0] io_DATA_IN, 962 | output [31:0] io_DATA_OUT, 963 | input io_TRIGGER, 964 | output io_deqRdy, 965 | output io_dataVal, 966 | input io_EN, 967 | output [1:0] io_A 968 | ); 969 | reg [31:0] addr; 970 | reg [31:0] _RAND_0; 971 | wire [31:0] _GEN_0; 972 | reg [1:0] state; 973 | reg [31:0] _RAND_1; 974 | wire rdy_clock; 975 | wire rdy_io_in; 976 | wire rdy_io_out; 977 | wire rdy_io_rising; 978 | wire rdy_io_falling; 979 | wire _T_16; 980 | wire _T_17; 981 | wire _T_18; 982 | wire _T_19; 983 | wire _T_20; 984 | wire _T_21; 985 | wire _T_22; 986 | wire addrCnt_clock; 987 | wire addrCnt_reset; 988 | wire addrCnt_io_inc; 989 | wire [8:0] addrCnt_io_tot; 990 | wire _T_24; 991 | wire _T_26; 992 | wire [1:0] _GEN_1; 993 | wire [1:0] _GEN_3; 994 | wire _T_28; 995 | wire [1:0] _GEN_4; 996 | wire [31:0] _GEN_6; 997 | wire [1:0] _GEN_7; 998 | wire [7:0] _T_31; 999 | wire [7:0] _T_32; 1000 | wire [7:0] _T_33; 1001 | wire [7:0] _T_34; 1002 | wire [15:0] _T_35; 1003 | wire [23:0] _T_36; 1004 | wire [31:0] _T_37; 1005 | wire _T_40; 1006 | wire [1:0] _GEN_8; 1007 | wire [32:0] _T_42; 1008 | wire [31:0] _T_43; 1009 | wire [1:0] _GEN_9; 1010 | wire [31:0] _GEN_10; 1011 | wire [31:0] _GEN_11; 1012 | wire [1:0] _GEN_12; 1013 | wire [1:0] _GEN_13; 1014 | wire [31:0] _GEN_14; 1015 | EdgeBuffer rdy ( 1016 | .clock(rdy_clock), 1017 | .io_in(rdy_io_in), 1018 | .io_out(rdy_io_out), 1019 | .io_rising(rdy_io_rising), 1020 | .io_falling(rdy_io_falling) 1021 | ); 1022 | Counter_4 addrCnt ( 1023 | .clock(addrCnt_clock), 1024 | .reset(addrCnt_reset), 1025 | .io_inc(addrCnt_io_inc), 1026 | .io_tot(addrCnt_io_tot) 1027 | ); 1028 | assign _GEN_0 = io_ADDR_SET ? io_ADDR_IN : addr; 1029 | assign _T_16 = io_DATA_READY & io_TRIGGER; 1030 | assign _T_17 = _T_16 & io_EN; 1031 | assign _T_18 = state == 2'h2; 1032 | assign _T_19 = rdy_io_rising & _T_18; 1033 | assign _T_20 = state != 2'h0; 1034 | assign _T_21 = ~ rdy_io_rising; 1035 | assign _T_22 = _T_20 & _T_21; 1036 | assign _T_24 = rdy_io_rising & _T_20; 1037 | assign _T_26 = state == 2'h0; 1038 | assign _GEN_1 = rdy_io_rising ? 2'h1 : state; 1039 | assign _GEN_3 = _T_26 ? _GEN_1 : state; 1040 | assign _T_28 = state == 2'h1; 1041 | assign _GEN_4 = rdy_io_rising ? 2'h2 : _GEN_3; 1042 | assign _GEN_6 = _T_28 ? addr : 32'h0; 1043 | assign _GEN_7 = _T_28 ? _GEN_4 : _GEN_3; 1044 | assign _T_31 = io_DATA_IN[7:0]; 1045 | assign _T_32 = io_DATA_IN[15:8]; 1046 | assign _T_33 = io_DATA_IN[23:16]; 1047 | assign _T_34 = io_DATA_IN[31:24]; 1048 | assign _T_35 = {_T_33,_T_34}; 1049 | assign _T_36 = {_T_32,_T_35}; 1050 | assign _T_37 = {_T_31,_T_36}; 1051 | assign _T_40 = addrCnt_io_tot == 9'h100; 1052 | assign _GEN_8 = _T_40 ? 2'h1 : _GEN_7; 1053 | assign _T_42 = addr + 32'h4; 1054 | assign _T_43 = _T_42[31:0]; 1055 | assign _GEN_9 = rdy_io_rising ? _GEN_8 : _GEN_7; 1056 | assign _GEN_10 = rdy_io_rising ? _T_43 : _GEN_0; 1057 | assign _GEN_11 = _T_18 ? _T_37 : _GEN_6; 1058 | assign _GEN_12 = _T_18 ? 2'h3 : 2'h1; 1059 | assign _GEN_13 = _T_18 ? _GEN_9 : _GEN_7; 1060 | assign _GEN_14 = _T_18 ? _GEN_10 : _GEN_0; 1061 | assign io_DATA_OUT = _GEN_11; 1062 | assign io_deqRdy = _T_19; 1063 | assign io_dataVal = _T_22; 1064 | assign io_A = _GEN_12; 1065 | assign rdy_io_in = _T_17; 1066 | assign rdy_clock = clock; 1067 | assign addrCnt_io_inc = _T_24; 1068 | assign addrCnt_clock = clock; 1069 | assign addrCnt_reset = reset; 1070 | `ifdef RANDOMIZE 1071 | integer initvar; 1072 | initial begin 1073 | `ifndef verilator 1074 | #0.002 begin end 1075 | `endif 1076 | `ifdef RANDOMIZE_REG_INIT 1077 | _RAND_0 = {1{$random}}; 1078 | addr = _RAND_0[31:0]; 1079 | `endif // RANDOMIZE_REG_INIT 1080 | `ifdef RANDOMIZE_REG_INIT 1081 | _RAND_1 = {1{$random}}; 1082 | state = _RAND_1[1:0]; 1083 | `endif // RANDOMIZE_REG_INIT 1084 | end 1085 | `endif // RANDOMIZE 1086 | always @(posedge clock) begin 1087 | if (reset) begin 1088 | addr <= 32'h0; 1089 | end else begin 1090 | if (_T_18) begin 1091 | if (rdy_io_rising) begin 1092 | addr <= _T_43; 1093 | end else begin 1094 | if (io_ADDR_SET) begin 1095 | addr <= io_ADDR_IN; 1096 | end 1097 | end 1098 | end else begin 1099 | if (io_ADDR_SET) begin 1100 | addr <= io_ADDR_IN; 1101 | end 1102 | end 1103 | end 1104 | if (reset) begin 1105 | state <= 2'h0; 1106 | end else begin 1107 | if (_T_18) begin 1108 | if (rdy_io_rising) begin 1109 | if (_T_40) begin 1110 | state <= 2'h1; 1111 | end else begin 1112 | if (_T_28) begin 1113 | if (rdy_io_rising) begin 1114 | state <= 2'h2; 1115 | end else begin 1116 | if (_T_26) begin 1117 | if (rdy_io_rising) begin 1118 | state <= 2'h1; 1119 | end 1120 | end 1121 | end 1122 | end else begin 1123 | if (_T_26) begin 1124 | if (rdy_io_rising) begin 1125 | state <= 2'h1; 1126 | end 1127 | end 1128 | end 1129 | end 1130 | end else begin 1131 | if (_T_28) begin 1132 | if (rdy_io_rising) begin 1133 | state <= 2'h2; 1134 | end else begin 1135 | if (_T_26) begin 1136 | if (rdy_io_rising) begin 1137 | state <= 2'h1; 1138 | end 1139 | end 1140 | end 1141 | end else begin 1142 | if (_T_26) begin 1143 | if (rdy_io_rising) begin 1144 | state <= 2'h1; 1145 | end 1146 | end 1147 | end 1148 | end 1149 | end else begin 1150 | if (_T_28) begin 1151 | if (rdy_io_rising) begin 1152 | state <= 2'h2; 1153 | end else begin 1154 | state <= _GEN_3; 1155 | end 1156 | end else begin 1157 | state <= _GEN_3; 1158 | end 1159 | end 1160 | end 1161 | end 1162 | endmodule 1163 | module Timer( 1164 | input clock, 1165 | input reset, 1166 | input [3:0] io_period, 1167 | output io_fire 1168 | ); 1169 | reg [3:0] cnt; 1170 | reg [31:0] _RAND_0; 1171 | wire [4:0] _T_9; 1172 | wire [3:0] _T_10; 1173 | wire _T_11; 1174 | wire [3:0] _T_13; 1175 | wire _T_15; 1176 | reg _T_17; 1177 | reg [31:0] _RAND_1; 1178 | assign _T_9 = cnt + 4'h1; 1179 | assign _T_10 = _T_9[3:0]; 1180 | assign _T_11 = _T_10 > io_period; 1181 | assign _T_13 = _T_11 ? 4'h0 : _T_10; 1182 | assign _T_15 = cnt == io_period; 1183 | assign io_fire = _T_17; 1184 | `ifdef RANDOMIZE 1185 | integer initvar; 1186 | initial begin 1187 | `ifndef verilator 1188 | #0.002 begin end 1189 | `endif 1190 | `ifdef RANDOMIZE_REG_INIT 1191 | _RAND_0 = {1{$random}}; 1192 | cnt = _RAND_0[3:0]; 1193 | `endif // RANDOMIZE_REG_INIT 1194 | `ifdef RANDOMIZE_REG_INIT 1195 | _RAND_1 = {1{$random}}; 1196 | _T_17 = _RAND_1[0:0]; 1197 | `endif // RANDOMIZE_REG_INIT 1198 | end 1199 | `endif // RANDOMIZE 1200 | always @(posedge clock) begin 1201 | if (reset) begin 1202 | cnt <= 4'h0; 1203 | end else begin 1204 | if (_T_11) begin 1205 | cnt <= 4'h0; 1206 | end else begin 1207 | cnt <= _T_10; 1208 | end 1209 | end 1210 | _T_17 <= _T_15; 1211 | end 1212 | endmodule 1213 | module Counter_5( 1214 | input clock, 1215 | input reset, 1216 | input io_inc, 1217 | output [5:0] io_tot, 1218 | input io_rst 1219 | ); 1220 | reg [5:0] _T_9; 1221 | reg [31:0] _RAND_0; 1222 | wire [6:0] _T_10; 1223 | wire [5:0] _T_11; 1224 | wire _T_12; 1225 | wire [5:0] _T_14; 1226 | wire [5:0] _GEN_0; 1227 | wire [5:0] _GEN_1; 1228 | assign _T_10 = _T_9 + 6'h1; 1229 | assign _T_11 = _T_10[5:0]; 1230 | assign _T_12 = _T_11 > 6'h35; 1231 | assign _T_14 = _T_12 ? 6'h0 : _T_11; 1232 | assign _GEN_0 = io_rst ? 6'h0 : _T_9; 1233 | assign _GEN_1 = io_inc ? _T_14 : _GEN_0; 1234 | assign io_tot = _T_9; 1235 | `ifdef RANDOMIZE 1236 | integer initvar; 1237 | initial begin 1238 | `ifndef verilator 1239 | #0.002 begin end 1240 | `endif 1241 | `ifdef RANDOMIZE_REG_INIT 1242 | _RAND_0 = {1{$random}}; 1243 | _T_9 = _RAND_0[5:0]; 1244 | `endif // RANDOMIZE_REG_INIT 1245 | end 1246 | `endif // RANDOMIZE 1247 | always @(posedge clock) begin 1248 | if (reset) begin 1249 | _T_9 <= 6'h0; 1250 | end else begin 1251 | if (io_inc) begin 1252 | if (_T_12) begin 1253 | _T_9 <= 6'h0; 1254 | end else begin 1255 | _T_9 <= _T_11; 1256 | end 1257 | end else begin 1258 | if (io_rst) begin 1259 | _T_9 <= 6'h0; 1260 | end 1261 | end 1262 | end 1263 | end 1264 | endmodule 1265 | module SWD( 1266 | input clock, 1267 | input reset, 1268 | output io_SWCLK, 1269 | input [31:0] io_DATA, 1270 | input io_DATA_READY, 1271 | output io_deqRdy, 1272 | input [3:0] io_CLKDIV, 1273 | input [1:0] io_A, 1274 | input io_D_IN_0, 1275 | output io_D_OUT_0, 1276 | output io_OUTPUT_ENABLE, 1277 | output io_ERROR, 1278 | input io_EN 1279 | ); 1280 | reg [31:0] swdio_out_reg; 1281 | reg [31:0] _RAND_0; 1282 | reg [2:0] swdio_response; 1283 | reg [31:0] _RAND_1; 1284 | reg [2:0] state; 1285 | reg [31:0] _RAND_2; 1286 | reg SWCLKReg; 1287 | reg [31:0] _RAND_3; 1288 | wire tmr_clock; 1289 | wire tmr_reset; 1290 | wire [3:0] tmr_io_period; 1291 | wire tmr_io_fire; 1292 | wire SWCLKr_clock; 1293 | wire SWCLKr_io_in; 1294 | wire SWCLKr_io_out; 1295 | wire SWCLKr_io_rising; 1296 | wire SWCLKr_io_falling; 1297 | wire _T_23; 1298 | wire _T_24; 1299 | wire _T_25; 1300 | wire _T_26; 1301 | wire _T_27; 1302 | wire _GEN_0; 1303 | reg deqRdyr; 1304 | reg [31:0] _RAND_4; 1305 | wire _T_30; 1306 | wire _T_31; 1307 | reg parity; 1308 | reg [31:0] _RAND_5; 1309 | reg outbit; 1310 | reg [31:0] _RAND_6; 1311 | reg outen; 1312 | reg [31:0] _RAND_7; 1313 | wire [2:0] _T_42; 1314 | wire [5:0] _T_43; 1315 | wire [7:0] packet; 1316 | wire bitcnt_clock; 1317 | wire bitcnt_reset; 1318 | wire bitcnt_io_inc; 1319 | wire [5:0] bitcnt_io_tot; 1320 | wire bitcnt_io_rst; 1321 | wire _T_48; 1322 | wire _T_49; 1323 | wire _T_50; 1324 | wire [2:0] _GEN_1; 1325 | wire [2:0] _GEN_2; 1326 | wire [31:0] _GEN_3; 1327 | wire _GEN_4; 1328 | wire _GEN_5; 1329 | wire [2:0] _GEN_6; 1330 | wire _GEN_7; 1331 | wire _T_54; 1332 | wire _T_57; 1333 | wire _T_60; 1334 | wire _GEN_8; 1335 | wire [30:0] _T_62; 1336 | wire [31:0] _T_63; 1337 | wire _GEN_9; 1338 | wire [31:0] _GEN_10; 1339 | wire _T_65; 1340 | wire _GEN_11; 1341 | wire _T_68; 1342 | wire [2:0] _GEN_12; 1343 | wire _GEN_14; 1344 | wire _GEN_15; 1345 | wire [31:0] _GEN_16; 1346 | wire _GEN_17; 1347 | wire [2:0] _GEN_18; 1348 | wire _GEN_19; 1349 | wire _T_70; 1350 | wire _T_73; 1351 | wire [2:0] _GEN_20; 1352 | wire _GEN_21; 1353 | wire [2:0] _GEN_22; 1354 | wire _T_74; 1355 | wire _T_76; 1356 | wire [2:0] _GEN_23; 1357 | wire [31:0] _GEN_24; 1358 | wire [1:0] _T_77; 1359 | wire [2:0] _T_78; 1360 | wire [2:0] _GEN_25; 1361 | wire [2:0] _GEN_26; 1362 | wire [31:0] _GEN_27; 1363 | wire [2:0] _GEN_28; 1364 | wire _GEN_29; 1365 | wire _T_80; 1366 | wire _T_82; 1367 | wire _T_83; 1368 | wire _T_85; 1369 | wire _T_92; 1370 | wire _GEN_30; 1371 | wire [2:0] _GEN_32; 1372 | wire [2:0] _GEN_33; 1373 | wire _GEN_34; 1374 | wire _GEN_35; 1375 | wire [31:0] _GEN_36; 1376 | wire _GEN_37; 1377 | wire [2:0] _GEN_38; 1378 | wire _GEN_39; 1379 | wire _GEN_40; 1380 | wire [31:0] _GEN_41; 1381 | wire _GEN_42; 1382 | wire [2:0] _GEN_43; 1383 | wire _GEN_44; 1384 | wire _GEN_45; 1385 | wire [31:0] _GEN_46; 1386 | wire _GEN_47; 1387 | wire _T_95; 1388 | wire _GEN_48; 1389 | wire _T_105; 1390 | wire _GEN_49; 1391 | wire _GEN_50; 1392 | wire [31:0] _GEN_51; 1393 | wire _GEN_52; 1394 | wire _T_108; 1395 | wire [2:0] _GEN_53; 1396 | wire _GEN_54; 1397 | wire _GEN_55; 1398 | wire _GEN_56; 1399 | wire [31:0] _GEN_57; 1400 | wire _GEN_58; 1401 | wire [2:0] _GEN_59; 1402 | wire _GEN_60; 1403 | Timer tmr ( 1404 | .clock(tmr_clock), 1405 | .reset(tmr_reset), 1406 | .io_period(tmr_io_period), 1407 | .io_fire(tmr_io_fire) 1408 | ); 1409 | EdgeBuffer SWCLKr ( 1410 | .clock(SWCLKr_clock), 1411 | .io_in(SWCLKr_io_in), 1412 | .io_out(SWCLKr_io_out), 1413 | .io_rising(SWCLKr_io_rising), 1414 | .io_falling(SWCLKr_io_falling) 1415 | ); 1416 | Counter_5 bitcnt ( 1417 | .clock(bitcnt_clock), 1418 | .reset(bitcnt_reset), 1419 | .io_inc(bitcnt_io_inc), 1420 | .io_tot(bitcnt_io_tot), 1421 | .io_rst(bitcnt_io_rst) 1422 | ); 1423 | assign _T_23 = state != 3'h6; 1424 | assign _T_24 = tmr_io_fire & _T_23; 1425 | assign _T_25 = state != 3'h0; 1426 | assign _T_26 = _T_24 & _T_25; 1427 | assign _T_27 = ~ SWCLKReg; 1428 | assign _GEN_0 = _T_26 ? _T_27 : SWCLKReg; 1429 | assign _T_30 = deqRdyr & io_EN; 1430 | assign _T_31 = state == 3'h6; 1431 | assign _T_42 = {io_A,1'h0}; 1432 | assign _T_43 = {3'h4,_T_42}; 1433 | assign packet = {_T_43,2'h3}; 1434 | assign _T_48 = state == 3'h0; 1435 | assign _T_49 = io_DATA_READY & io_EN; 1436 | assign _T_50 = _T_49 & tmr_io_fire; 1437 | assign _GEN_1 = _T_50 ? 3'h1 : state; 1438 | assign _GEN_2 = _T_48 ? _GEN_1 : state; 1439 | assign _GEN_3 = _T_48 ? {{24'd0}, packet} : swdio_out_reg; 1440 | assign _GEN_4 = _T_48 ? 1'h0 : _GEN_0; 1441 | assign _GEN_5 = _T_48 ? 1'h1 : parity; 1442 | assign _GEN_6 = _T_48 ? 3'h0 : swdio_response; 1443 | assign _GEN_7 = _T_48 ? io_EN : outen; 1444 | assign _T_54 = state == 3'h1; 1445 | assign _T_57 = swdio_out_reg[0]; 1446 | assign _T_60 = ~ parity; 1447 | assign _GEN_8 = _T_57 ? _T_60 : _GEN_5; 1448 | assign _T_62 = swdio_out_reg[31:1]; 1449 | assign _T_63 = {1'h0,_T_62}; 1450 | assign _GEN_9 = SWCLKr_io_falling ? _GEN_8 : _GEN_5; 1451 | assign _GEN_10 = SWCLKr_io_falling ? _T_63 : _GEN_3; 1452 | assign _T_65 = bitcnt_io_tot == 6'h5; 1453 | assign _GEN_11 = _T_65 ? parity : _T_57; 1454 | assign _T_68 = bitcnt_io_tot == 6'h8; 1455 | assign _GEN_12 = _T_68 ? 3'h2 : _GEN_2; 1456 | assign _GEN_14 = _T_54 ? 1'h0 : deqRdyr; 1457 | assign _GEN_15 = _T_54 ? _GEN_9 : _GEN_5; 1458 | assign _GEN_16 = _T_54 ? _GEN_10 : _GEN_3; 1459 | assign _GEN_17 = _T_54 ? _GEN_11 : outbit; 1460 | assign _GEN_18 = _T_54 ? _GEN_12 : _GEN_2; 1461 | assign _GEN_19 = _T_54 ? 1'h1 : _GEN_7; 1462 | assign _T_70 = state == 3'h2; 1463 | assign _T_73 = bitcnt_io_tot == 6'h9; 1464 | assign _GEN_20 = _T_73 ? 3'h3 : _GEN_18; 1465 | assign _GEN_21 = _T_70 ? 1'h0 : _GEN_19; 1466 | assign _GEN_22 = _T_70 ? _GEN_20 : _GEN_18; 1467 | assign _T_74 = state == 3'h3; 1468 | assign _T_76 = bitcnt_io_tot == 6'hc; 1469 | assign _GEN_23 = _T_76 ? 3'h4 : _GEN_22; 1470 | assign _GEN_24 = _T_76 ? io_DATA : _GEN_16; 1471 | assign _T_77 = swdio_response[2:1]; 1472 | assign _T_78 = {io_D_IN_0,_T_77}; 1473 | assign _GEN_25 = SWCLKr_io_rising ? _T_78 : _GEN_6; 1474 | assign _GEN_26 = _T_74 ? _GEN_23 : _GEN_22; 1475 | assign _GEN_27 = _T_74 ? _GEN_24 : _GEN_16; 1476 | assign _GEN_28 = _T_74 ? _GEN_25 : _GEN_6; 1477 | assign _GEN_29 = _T_74 ? 1'h0 : _GEN_21; 1478 | assign _T_80 = state == 3'h4; 1479 | assign _T_82 = bitcnt_io_tot == 6'hd; 1480 | assign _T_83 = _T_82 & SWCLKr_io_falling; 1481 | assign _T_85 = swdio_response == 3'h1; 1482 | assign _T_92 = swdio_response == 3'h2; 1483 | assign _GEN_30 = _T_92 ? 1'h0 : _GEN_17; 1484 | assign _GEN_32 = _T_92 ? 3'h0 : 3'h6; 1485 | assign _GEN_33 = _T_85 ? 3'h5 : _GEN_32; 1486 | assign _GEN_34 = _T_85 ? _T_57 : _GEN_30; 1487 | assign _GEN_35 = _T_85 ? _T_57 : _GEN_15; 1488 | assign _GEN_36 = _T_85 ? _T_63 : _GEN_27; 1489 | assign _GEN_37 = _T_85 ? 1'h0 : _T_92; 1490 | assign _GEN_38 = _T_83 ? _GEN_33 : _GEN_26; 1491 | assign _GEN_39 = _T_83 ? _GEN_34 : _GEN_17; 1492 | assign _GEN_40 = _T_83 ? _GEN_35 : _GEN_15; 1493 | assign _GEN_41 = _T_83 ? _GEN_36 : _GEN_27; 1494 | assign _GEN_42 = _T_83 ? _GEN_37 : 1'h0; 1495 | assign _GEN_43 = _T_80 ? _GEN_38 : _GEN_26; 1496 | assign _GEN_44 = _T_80 ? _GEN_39 : _GEN_17; 1497 | assign _GEN_45 = _T_80 ? _GEN_40 : _GEN_15; 1498 | assign _GEN_46 = _T_80 ? _GEN_41 : _GEN_27; 1499 | assign _GEN_47 = _T_80 ? _GEN_42 : 1'h0; 1500 | assign _T_95 = state == 3'h5; 1501 | assign _GEN_48 = _T_57 ? _T_60 : _GEN_45; 1502 | assign _T_105 = bitcnt_io_tot == 6'h2d; 1503 | assign _GEN_49 = _T_105 ? parity : _T_57; 1504 | assign _GEN_50 = SWCLKr_io_falling ? _GEN_48 : _GEN_45; 1505 | assign _GEN_51 = SWCLKr_io_falling ? _T_63 : _GEN_46; 1506 | assign _GEN_52 = SWCLKr_io_falling ? _GEN_49 : _GEN_44; 1507 | assign _T_108 = bitcnt_io_tot == 6'h0; 1508 | assign _GEN_53 = _T_108 ? 3'h0 : _GEN_43; 1509 | assign _GEN_54 = _T_108 ? 1'h1 : _GEN_14; 1510 | assign _GEN_55 = _T_95 ? 1'h1 : _GEN_29; 1511 | assign _GEN_56 = _T_95 ? _GEN_50 : _GEN_45; 1512 | assign _GEN_57 = _T_95 ? _GEN_51 : _GEN_46; 1513 | assign _GEN_58 = _T_95 ? _GEN_52 : _GEN_44; 1514 | assign _GEN_59 = _T_95 ? _GEN_53 : _GEN_43; 1515 | assign _GEN_60 = _T_95 ? _GEN_54 : _GEN_14; 1516 | assign io_SWCLK = SWCLKr_io_out; 1517 | assign io_deqRdy = _T_30; 1518 | assign io_D_OUT_0 = outbit; 1519 | assign io_OUTPUT_ENABLE = outen; 1520 | assign io_ERROR = _T_31; 1521 | assign tmr_io_period = io_CLKDIV; 1522 | assign tmr_clock = clock; 1523 | assign tmr_reset = reset; 1524 | assign SWCLKr_io_in = SWCLKReg; 1525 | assign SWCLKr_clock = clock; 1526 | assign bitcnt_io_inc = SWCLKr_io_rising; 1527 | assign bitcnt_io_rst = _GEN_47; 1528 | assign bitcnt_clock = clock; 1529 | assign bitcnt_reset = reset; 1530 | `ifdef RANDOMIZE 1531 | integer initvar; 1532 | initial begin 1533 | `ifndef verilator 1534 | #0.002 begin end 1535 | `endif 1536 | `ifdef RANDOMIZE_REG_INIT 1537 | _RAND_0 = {1{$random}}; 1538 | swdio_out_reg = _RAND_0[31:0]; 1539 | `endif // RANDOMIZE_REG_INIT 1540 | `ifdef RANDOMIZE_REG_INIT 1541 | _RAND_1 = {1{$random}}; 1542 | swdio_response = _RAND_1[2:0]; 1543 | `endif // RANDOMIZE_REG_INIT 1544 | `ifdef RANDOMIZE_REG_INIT 1545 | _RAND_2 = {1{$random}}; 1546 | state = _RAND_2[2:0]; 1547 | `endif // RANDOMIZE_REG_INIT 1548 | `ifdef RANDOMIZE_REG_INIT 1549 | _RAND_3 = {1{$random}}; 1550 | SWCLKReg = _RAND_3[0:0]; 1551 | `endif // RANDOMIZE_REG_INIT 1552 | `ifdef RANDOMIZE_REG_INIT 1553 | _RAND_4 = {1{$random}}; 1554 | deqRdyr = _RAND_4[0:0]; 1555 | `endif // RANDOMIZE_REG_INIT 1556 | `ifdef RANDOMIZE_REG_INIT 1557 | _RAND_5 = {1{$random}}; 1558 | parity = _RAND_5[0:0]; 1559 | `endif // RANDOMIZE_REG_INIT 1560 | `ifdef RANDOMIZE_REG_INIT 1561 | _RAND_6 = {1{$random}}; 1562 | outbit = _RAND_6[0:0]; 1563 | `endif // RANDOMIZE_REG_INIT 1564 | `ifdef RANDOMIZE_REG_INIT 1565 | _RAND_7 = {1{$random}}; 1566 | outen = _RAND_7[0:0]; 1567 | `endif // RANDOMIZE_REG_INIT 1568 | end 1569 | `endif // RANDOMIZE 1570 | always @(posedge clock) begin 1571 | if (reset) begin 1572 | swdio_out_reg <= 32'h0; 1573 | end else begin 1574 | if (_T_95) begin 1575 | if (SWCLKr_io_falling) begin 1576 | swdio_out_reg <= _T_63; 1577 | end else begin 1578 | if (_T_80) begin 1579 | if (_T_83) begin 1580 | if (_T_85) begin 1581 | swdio_out_reg <= _T_63; 1582 | end else begin 1583 | if (_T_74) begin 1584 | if (_T_76) begin 1585 | swdio_out_reg <= io_DATA; 1586 | end else begin 1587 | if (_T_54) begin 1588 | if (SWCLKr_io_falling) begin 1589 | swdio_out_reg <= _T_63; 1590 | end else begin 1591 | if (_T_48) begin 1592 | swdio_out_reg <= {{24'd0}, packet}; 1593 | end 1594 | end 1595 | end else begin 1596 | if (_T_48) begin 1597 | swdio_out_reg <= {{24'd0}, packet}; 1598 | end 1599 | end 1600 | end 1601 | end else begin 1602 | if (_T_54) begin 1603 | if (SWCLKr_io_falling) begin 1604 | swdio_out_reg <= _T_63; 1605 | end else begin 1606 | if (_T_48) begin 1607 | swdio_out_reg <= {{24'd0}, packet}; 1608 | end 1609 | end 1610 | end else begin 1611 | if (_T_48) begin 1612 | swdio_out_reg <= {{24'd0}, packet}; 1613 | end 1614 | end 1615 | end 1616 | end 1617 | end else begin 1618 | if (_T_74) begin 1619 | if (_T_76) begin 1620 | swdio_out_reg <= io_DATA; 1621 | end else begin 1622 | if (_T_54) begin 1623 | if (SWCLKr_io_falling) begin 1624 | swdio_out_reg <= _T_63; 1625 | end else begin 1626 | swdio_out_reg <= _GEN_3; 1627 | end 1628 | end else begin 1629 | swdio_out_reg <= _GEN_3; 1630 | end 1631 | end 1632 | end else begin 1633 | if (_T_54) begin 1634 | if (SWCLKr_io_falling) begin 1635 | swdio_out_reg <= _T_63; 1636 | end else begin 1637 | swdio_out_reg <= _GEN_3; 1638 | end 1639 | end else begin 1640 | swdio_out_reg <= _GEN_3; 1641 | end 1642 | end 1643 | end 1644 | end else begin 1645 | if (_T_74) begin 1646 | if (_T_76) begin 1647 | swdio_out_reg <= io_DATA; 1648 | end else begin 1649 | swdio_out_reg <= _GEN_16; 1650 | end 1651 | end else begin 1652 | swdio_out_reg <= _GEN_16; 1653 | end 1654 | end 1655 | end 1656 | end else begin 1657 | if (_T_80) begin 1658 | if (_T_83) begin 1659 | if (_T_85) begin 1660 | swdio_out_reg <= _T_63; 1661 | end else begin 1662 | if (_T_74) begin 1663 | if (_T_76) begin 1664 | swdio_out_reg <= io_DATA; 1665 | end else begin 1666 | swdio_out_reg <= _GEN_16; 1667 | end 1668 | end else begin 1669 | swdio_out_reg <= _GEN_16; 1670 | end 1671 | end 1672 | end else begin 1673 | swdio_out_reg <= _GEN_27; 1674 | end 1675 | end else begin 1676 | swdio_out_reg <= _GEN_27; 1677 | end 1678 | end 1679 | end 1680 | if (reset) begin 1681 | swdio_response <= 3'h0; 1682 | end else begin 1683 | if (_T_74) begin 1684 | if (SWCLKr_io_rising) begin 1685 | swdio_response <= _T_78; 1686 | end else begin 1687 | if (_T_48) begin 1688 | swdio_response <= 3'h0; 1689 | end 1690 | end 1691 | end else begin 1692 | if (_T_48) begin 1693 | swdio_response <= 3'h0; 1694 | end 1695 | end 1696 | end 1697 | if (reset) begin 1698 | state <= 3'h0; 1699 | end else begin 1700 | if (_T_95) begin 1701 | if (_T_108) begin 1702 | state <= 3'h0; 1703 | end else begin 1704 | if (_T_80) begin 1705 | if (_T_83) begin 1706 | if (_T_85) begin 1707 | state <= 3'h5; 1708 | end else begin 1709 | if (_T_92) begin 1710 | state <= 3'h0; 1711 | end else begin 1712 | state <= 3'h6; 1713 | end 1714 | end 1715 | end else begin 1716 | if (_T_74) begin 1717 | if (_T_76) begin 1718 | state <= 3'h4; 1719 | end else begin 1720 | if (_T_70) begin 1721 | if (_T_73) begin 1722 | state <= 3'h3; 1723 | end else begin 1724 | if (_T_54) begin 1725 | if (_T_68) begin 1726 | state <= 3'h2; 1727 | end else begin 1728 | if (_T_48) begin 1729 | if (_T_50) begin 1730 | state <= 3'h1; 1731 | end 1732 | end 1733 | end 1734 | end else begin 1735 | if (_T_48) begin 1736 | if (_T_50) begin 1737 | state <= 3'h1; 1738 | end 1739 | end 1740 | end 1741 | end 1742 | end else begin 1743 | if (_T_54) begin 1744 | if (_T_68) begin 1745 | state <= 3'h2; 1746 | end else begin 1747 | if (_T_48) begin 1748 | if (_T_50) begin 1749 | state <= 3'h1; 1750 | end 1751 | end 1752 | end 1753 | end else begin 1754 | if (_T_48) begin 1755 | if (_T_50) begin 1756 | state <= 3'h1; 1757 | end 1758 | end 1759 | end 1760 | end 1761 | end 1762 | end else begin 1763 | if (_T_70) begin 1764 | if (_T_73) begin 1765 | state <= 3'h3; 1766 | end else begin 1767 | if (_T_54) begin 1768 | if (_T_68) begin 1769 | state <= 3'h2; 1770 | end else begin 1771 | state <= _GEN_2; 1772 | end 1773 | end else begin 1774 | state <= _GEN_2; 1775 | end 1776 | end 1777 | end else begin 1778 | if (_T_54) begin 1779 | if (_T_68) begin 1780 | state <= 3'h2; 1781 | end else begin 1782 | state <= _GEN_2; 1783 | end 1784 | end else begin 1785 | state <= _GEN_2; 1786 | end 1787 | end 1788 | end 1789 | end 1790 | end else begin 1791 | if (_T_74) begin 1792 | if (_T_76) begin 1793 | state <= 3'h4; 1794 | end else begin 1795 | if (_T_70) begin 1796 | if (_T_73) begin 1797 | state <= 3'h3; 1798 | end else begin 1799 | state <= _GEN_18; 1800 | end 1801 | end else begin 1802 | state <= _GEN_18; 1803 | end 1804 | end 1805 | end else begin 1806 | if (_T_70) begin 1807 | if (_T_73) begin 1808 | state <= 3'h3; 1809 | end else begin 1810 | state <= _GEN_18; 1811 | end 1812 | end else begin 1813 | state <= _GEN_18; 1814 | end 1815 | end 1816 | end 1817 | end 1818 | end else begin 1819 | if (_T_80) begin 1820 | if (_T_83) begin 1821 | if (_T_85) begin 1822 | state <= 3'h5; 1823 | end else begin 1824 | if (_T_92) begin 1825 | state <= 3'h0; 1826 | end else begin 1827 | state <= 3'h6; 1828 | end 1829 | end 1830 | end else begin 1831 | if (_T_74) begin 1832 | if (_T_76) begin 1833 | state <= 3'h4; 1834 | end else begin 1835 | state <= _GEN_22; 1836 | end 1837 | end else begin 1838 | state <= _GEN_22; 1839 | end 1840 | end 1841 | end else begin 1842 | if (_T_74) begin 1843 | if (_T_76) begin 1844 | state <= 3'h4; 1845 | end else begin 1846 | state <= _GEN_22; 1847 | end 1848 | end else begin 1849 | state <= _GEN_22; 1850 | end 1851 | end 1852 | end 1853 | end 1854 | if (reset) begin 1855 | SWCLKReg <= 1'h0; 1856 | end else begin 1857 | if (_T_48) begin 1858 | SWCLKReg <= 1'h0; 1859 | end else begin 1860 | if (_T_26) begin 1861 | SWCLKReg <= _T_27; 1862 | end 1863 | end 1864 | end 1865 | if (reset) begin 1866 | deqRdyr <= 1'h1; 1867 | end else begin 1868 | if (_T_95) begin 1869 | if (_T_108) begin 1870 | deqRdyr <= 1'h1; 1871 | end else begin 1872 | if (_T_54) begin 1873 | deqRdyr <= 1'h0; 1874 | end 1875 | end 1876 | end else begin 1877 | if (_T_54) begin 1878 | deqRdyr <= 1'h0; 1879 | end 1880 | end 1881 | end 1882 | if (reset) begin 1883 | parity <= 1'h0; 1884 | end else begin 1885 | if (_T_95) begin 1886 | if (SWCLKr_io_falling) begin 1887 | if (_T_57) begin 1888 | parity <= _T_60; 1889 | end else begin 1890 | if (_T_80) begin 1891 | if (_T_83) begin 1892 | if (_T_85) begin 1893 | parity <= _T_57; 1894 | end else begin 1895 | if (_T_54) begin 1896 | if (SWCLKr_io_falling) begin 1897 | if (_T_57) begin 1898 | parity <= _T_60; 1899 | end else begin 1900 | if (_T_48) begin 1901 | parity <= 1'h1; 1902 | end 1903 | end 1904 | end else begin 1905 | if (_T_48) begin 1906 | parity <= 1'h1; 1907 | end 1908 | end 1909 | end else begin 1910 | if (_T_48) begin 1911 | parity <= 1'h1; 1912 | end 1913 | end 1914 | end 1915 | end else begin 1916 | if (_T_54) begin 1917 | if (SWCLKr_io_falling) begin 1918 | if (_T_57) begin 1919 | parity <= _T_60; 1920 | end else begin 1921 | if (_T_48) begin 1922 | parity <= 1'h1; 1923 | end 1924 | end 1925 | end else begin 1926 | parity <= _GEN_5; 1927 | end 1928 | end else begin 1929 | parity <= _GEN_5; 1930 | end 1931 | end 1932 | end else begin 1933 | if (_T_54) begin 1934 | if (SWCLKr_io_falling) begin 1935 | if (_T_57) begin 1936 | parity <= _T_60; 1937 | end else begin 1938 | parity <= _GEN_5; 1939 | end 1940 | end else begin 1941 | parity <= _GEN_5; 1942 | end 1943 | end else begin 1944 | parity <= _GEN_5; 1945 | end 1946 | end 1947 | end 1948 | end else begin 1949 | if (_T_80) begin 1950 | if (_T_83) begin 1951 | if (_T_85) begin 1952 | parity <= _T_57; 1953 | end else begin 1954 | if (_T_54) begin 1955 | if (SWCLKr_io_falling) begin 1956 | if (_T_57) begin 1957 | parity <= _T_60; 1958 | end else begin 1959 | parity <= _GEN_5; 1960 | end 1961 | end else begin 1962 | parity <= _GEN_5; 1963 | end 1964 | end else begin 1965 | parity <= _GEN_5; 1966 | end 1967 | end 1968 | end else begin 1969 | parity <= _GEN_15; 1970 | end 1971 | end else begin 1972 | parity <= _GEN_15; 1973 | end 1974 | end 1975 | end else begin 1976 | if (_T_80) begin 1977 | if (_T_83) begin 1978 | if (_T_85) begin 1979 | parity <= _T_57; 1980 | end else begin 1981 | parity <= _GEN_15; 1982 | end 1983 | end else begin 1984 | parity <= _GEN_15; 1985 | end 1986 | end else begin 1987 | parity <= _GEN_15; 1988 | end 1989 | end 1990 | end 1991 | if (reset) begin 1992 | outbit <= 1'h0; 1993 | end else begin 1994 | if (_T_95) begin 1995 | if (SWCLKr_io_falling) begin 1996 | if (_T_105) begin 1997 | outbit <= parity; 1998 | end else begin 1999 | outbit <= _T_57; 2000 | end 2001 | end else begin 2002 | if (_T_80) begin 2003 | if (_T_83) begin 2004 | if (_T_85) begin 2005 | outbit <= _T_57; 2006 | end else begin 2007 | if (_T_92) begin 2008 | outbit <= 1'h0; 2009 | end else begin 2010 | if (_T_54) begin 2011 | if (_T_65) begin 2012 | outbit <= parity; 2013 | end else begin 2014 | outbit <= _T_57; 2015 | end 2016 | end 2017 | end 2018 | end 2019 | end else begin 2020 | if (_T_54) begin 2021 | if (_T_65) begin 2022 | outbit <= parity; 2023 | end else begin 2024 | outbit <= _T_57; 2025 | end 2026 | end 2027 | end 2028 | end else begin 2029 | if (_T_54) begin 2030 | if (_T_65) begin 2031 | outbit <= parity; 2032 | end else begin 2033 | outbit <= _T_57; 2034 | end 2035 | end 2036 | end 2037 | end 2038 | end else begin 2039 | if (_T_80) begin 2040 | if (_T_83) begin 2041 | if (_T_85) begin 2042 | outbit <= _T_57; 2043 | end else begin 2044 | if (_T_92) begin 2045 | outbit <= 1'h0; 2046 | end else begin 2047 | if (_T_54) begin 2048 | if (_T_65) begin 2049 | outbit <= parity; 2050 | end else begin 2051 | outbit <= _T_57; 2052 | end 2053 | end 2054 | end 2055 | end 2056 | end else begin 2057 | outbit <= _GEN_17; 2058 | end 2059 | end else begin 2060 | outbit <= _GEN_17; 2061 | end 2062 | end 2063 | end 2064 | if (reset) begin 2065 | outen <= 1'h0; 2066 | end else begin 2067 | if (_T_95) begin 2068 | outen <= 1'h1; 2069 | end else begin 2070 | if (_T_74) begin 2071 | outen <= 1'h0; 2072 | end else begin 2073 | if (_T_70) begin 2074 | outen <= 1'h0; 2075 | end else begin 2076 | if (_T_54) begin 2077 | outen <= 1'h1; 2078 | end else begin 2079 | if (_T_48) begin 2080 | outen <= io_EN; 2081 | end 2082 | end 2083 | end 2084 | end 2085 | end 2086 | end 2087 | end 2088 | endmodule 2089 | module Top( 2090 | input clock, 2091 | input reset, 2092 | input io_MOSI, 2093 | output io_MISO, 2094 | input io_SCK, 2095 | input io_SSEL, 2096 | output io_FLASH_MOSI, 2097 | input io_FLASH_MISO, 2098 | output io_FLASH_SCK, 2099 | output io_FLASH_SSEL, 2100 | output io_SWCLK, 2101 | output io_SWDIO, 2102 | input [31:0] io_SPI_DATA, 2103 | input io_SPI_DATA_READY, 2104 | output [23:0] io_SPI_READ_OUT, 2105 | output io_OUTPUT_ENABLE, 2106 | output io_D_OUT_0, 2107 | input io_D_IN_0, 2108 | input [31:0] io_FAST_READ_DATA, 2109 | output io_FAST_READ_DATA_READY 2110 | ); 2111 | wire SB_PLL40_CORE_PLLOUTCORE; 2112 | wire SB_PLL40_CORE_REFERENCECLK; 2113 | wire SB_PLL40_CORE_BYPASS; 2114 | wire SB_PLL40_CORE_RESETB; 2115 | wire SB_PLL40_CORE_LOCK; 2116 | wire SPISlave_clock; 2117 | wire SPISlave_reset; 2118 | wire SPISlave_io_MOSI; 2119 | wire SPISlave_io_MISO; 2120 | wire SPISlave_io_SCK; 2121 | wire SPISlave_io_SSEL; 2122 | wire SPISlave_io_DATA_READY; 2123 | wire [31:0] SPISlave_io_DATA; 2124 | wire [23:0] SPISlave_io_READ_OUT; 2125 | wire SPIDecode_clock; 2126 | wire [27:0] SPIDecode_io_dataIn; 2127 | wire [23:0] SPIDecode_io_dataOut; 2128 | wire [2:0] SPIDecode_io_addr; 2129 | wire SPIDecode_io_trigger; 2130 | wire SPIDecode_io_wclk; 2131 | wire StatusReg_clock; 2132 | wire StatusReg_reset; 2133 | wire StatusReg_io_en; 2134 | wire StatusReg_io_din; 2135 | wire [1:0] StatusReg_io_dout; 2136 | wire StatusReg_io_done; 2137 | wire StatusReg_io_error; 2138 | wire _T_21; 2139 | wire _T_23; 2140 | wire _T_24; 2141 | wire AddrReg_clock; 2142 | wire AddrReg_reset; 2143 | wire AddrReg_io_en; 2144 | wire [23:0] AddrReg_io_din; 2145 | wire [23:0] AddrReg_io_dout; 2146 | wire _T_26; 2147 | wire _T_27; 2148 | wire LengthReg_clock; 2149 | wire LengthReg_reset; 2150 | wire LengthReg_io_en; 2151 | wire LengthReg_io_dec; 2152 | wire [23:0] LengthReg_io_din; 2153 | wire [23:0] LengthReg_io_dout; 2154 | wire _T_29; 2155 | wire _T_30; 2156 | wire ClkDivReg_clock; 2157 | wire ClkDivReg_reset; 2158 | wire ClkDivReg_io_en; 2159 | wire [3:0] ClkDivReg_io_din; 2160 | wire [3:0] ClkDivReg_io_dout; 2161 | wire _T_32; 2162 | wire _T_33; 2163 | wire AddrReg_1_clock; 2164 | wire AddrReg_1_reset; 2165 | wire AddrReg_1_io_en; 2166 | wire [23:0] AddrReg_1_io_din; 2167 | wire [23:0] AddrReg_1_io_dout; 2168 | wire _T_35; 2169 | wire _T_36; 2170 | wire _T_38; 2171 | wire [23:0] _GEN_0; 2172 | wire [23:0] _GEN_1; 2173 | wire [23:0] _GEN_2; 2174 | wire [23:0] _GEN_3; 2175 | wire [23:0] _GEN_4; 2176 | wire [23:0] _GEN_5; 2177 | wire _T_51; 2178 | wire _T_52; 2179 | wire EdgeBuffer_clock; 2180 | wire EdgeBuffer_io_in; 2181 | wire EdgeBuffer_io_out; 2182 | wire EdgeBuffer_io_rising; 2183 | wire EdgeBuffer_io_falling; 2184 | wire SPIFastRead_clock; 2185 | wire SPIFastRead_io_MOSI; 2186 | wire SPIFastRead_io_MISO; 2187 | wire SPIFastRead_io_SCK; 2188 | wire SPIFastRead_io_DATA_READY; 2189 | wire [31:0] SPIFastRead_io_DATA; 2190 | wire [23:0] SPIFastRead_io_ADDR; 2191 | wire SPIFastRead_io_EN; 2192 | wire SPIFastRead_io_enqRdy; 2193 | wire Fifo_clock; 2194 | wire Fifo_reset; 2195 | wire Fifo_io_enqVal; 2196 | wire Fifo_io_enqRdy; 2197 | wire Fifo_io_deqVal; 2198 | wire Fifo_io_deqRdy; 2199 | wire [31:0] Fifo_io_enqDat; 2200 | wire [31:0] Fifo_io_deqDat; 2201 | wire _T_54; 2202 | wire _T_56; 2203 | wire _T_57; 2204 | wire DoubleBarrel_clock; 2205 | wire DoubleBarrel_reset; 2206 | wire [31:0] DoubleBarrel_io_ADDR_IN; 2207 | wire DoubleBarrel_io_ADDR_SET; 2208 | wire DoubleBarrel_io_DATA_READY; 2209 | wire [31:0] DoubleBarrel_io_DATA_IN; 2210 | wire [31:0] DoubleBarrel_io_DATA_OUT; 2211 | wire DoubleBarrel_io_TRIGGER; 2212 | wire DoubleBarrel_io_deqRdy; 2213 | wire DoubleBarrel_io_dataVal; 2214 | wire DoubleBarrel_io_EN; 2215 | wire [1:0] DoubleBarrel_io_A; 2216 | wire SWD_clock; 2217 | wire SWD_reset; 2218 | wire SWD_io_SWCLK; 2219 | wire [31:0] SWD_io_DATA; 2220 | wire SWD_io_DATA_READY; 2221 | wire SWD_io_deqRdy; 2222 | wire [3:0] SWD_io_CLKDIV; 2223 | wire [1:0] SWD_io_A; 2224 | wire SWD_io_D_IN_0; 2225 | wire SWD_io_D_OUT_0; 2226 | wire SWD_io_OUTPUT_ENABLE; 2227 | wire SWD_io_ERROR; 2228 | wire SWD_io_EN; 2229 | wire _T_58; 2230 | wire SB_IO_D_IN_0; 2231 | wire SB_IO_D_OUT_0; 2232 | wire SB_IO_OUTPUT_ENABLE; 2233 | wire SB_IO_PACKAGE_PIN; 2234 | wire SB_IO_1_D_IN_0; 2235 | wire SB_IO_1_D_OUT_0; 2236 | wire SB_IO_1_OUTPUT_ENABLE; 2237 | wire SB_IO_1_PACKAGE_PIN; 2238 | wire _T_61; 2239 | wire _T_62; 2240 | wire _T_63; 2241 | SB_PLL40_CORE #(.PLLOUT_SELECT("GENCLK"), .DIVR(0), .DIVQ(2), .FEEDBACK_PATH("SIMPLE"), .DIVF(23), .FILTER_RANGE(2)) SB_PLL40_CORE ( 2242 | .PLLOUTCORE(SB_PLL40_CORE_PLLOUTCORE), 2243 | .REFERENCECLK(SB_PLL40_CORE_REFERENCECLK), 2244 | .BYPASS(SB_PLL40_CORE_BYPASS), 2245 | .RESETB(SB_PLL40_CORE_RESETB), 2246 | .LOCK(SB_PLL40_CORE_LOCK) 2247 | ); 2248 | SPISlave SPISlave ( 2249 | .clock(SPISlave_clock), 2250 | .reset(SPISlave_reset), 2251 | .io_MOSI(SPISlave_io_MOSI), 2252 | .io_MISO(SPISlave_io_MISO), 2253 | .io_SCK(SPISlave_io_SCK), 2254 | .io_SSEL(SPISlave_io_SSEL), 2255 | .io_DATA_READY(SPISlave_io_DATA_READY), 2256 | .io_DATA(SPISlave_io_DATA), 2257 | .io_READ_OUT(SPISlave_io_READ_OUT) 2258 | ); 2259 | SPIDecode SPIDecode ( 2260 | .clock(SPIDecode_clock), 2261 | .io_dataIn(SPIDecode_io_dataIn), 2262 | .io_dataOut(SPIDecode_io_dataOut), 2263 | .io_addr(SPIDecode_io_addr), 2264 | .io_trigger(SPIDecode_io_trigger), 2265 | .io_wclk(SPIDecode_io_wclk) 2266 | ); 2267 | StatusReg StatusReg ( 2268 | .clock(StatusReg_clock), 2269 | .reset(StatusReg_reset), 2270 | .io_en(StatusReg_io_en), 2271 | .io_din(StatusReg_io_din), 2272 | .io_dout(StatusReg_io_dout), 2273 | .io_done(StatusReg_io_done), 2274 | .io_error(StatusReg_io_error) 2275 | ); 2276 | AddrReg AddrReg ( 2277 | .clock(AddrReg_clock), 2278 | .reset(AddrReg_reset), 2279 | .io_en(AddrReg_io_en), 2280 | .io_din(AddrReg_io_din), 2281 | .io_dout(AddrReg_io_dout) 2282 | ); 2283 | LengthReg LengthReg ( 2284 | .clock(LengthReg_clock), 2285 | .reset(LengthReg_reset), 2286 | .io_en(LengthReg_io_en), 2287 | .io_dec(LengthReg_io_dec), 2288 | .io_din(LengthReg_io_din), 2289 | .io_dout(LengthReg_io_dout) 2290 | ); 2291 | ClkDivReg ClkDivReg ( 2292 | .clock(ClkDivReg_clock), 2293 | .reset(ClkDivReg_reset), 2294 | .io_en(ClkDivReg_io_en), 2295 | .io_din(ClkDivReg_io_din), 2296 | .io_dout(ClkDivReg_io_dout) 2297 | ); 2298 | AddrReg AddrReg_1 ( 2299 | .clock(AddrReg_1_clock), 2300 | .reset(AddrReg_1_reset), 2301 | .io_en(AddrReg_1_io_en), 2302 | .io_din(AddrReg_1_io_din), 2303 | .io_dout(AddrReg_1_io_dout) 2304 | ); 2305 | EdgeBuffer EdgeBuffer ( 2306 | .clock(EdgeBuffer_clock), 2307 | .io_in(EdgeBuffer_io_in), 2308 | .io_out(EdgeBuffer_io_out), 2309 | .io_rising(EdgeBuffer_io_rising), 2310 | .io_falling(EdgeBuffer_io_falling) 2311 | ); 2312 | SPIFastRead SPIFastRead ( 2313 | .clock(SPIFastRead_clock), 2314 | .io_MOSI(SPIFastRead_io_MOSI), 2315 | .io_MISO(SPIFastRead_io_MISO), 2316 | .io_SCK(SPIFastRead_io_SCK), 2317 | .io_DATA_READY(SPIFastRead_io_DATA_READY), 2318 | .io_DATA(SPIFastRead_io_DATA), 2319 | .io_ADDR(SPIFastRead_io_ADDR), 2320 | .io_EN(SPIFastRead_io_EN), 2321 | .io_enqRdy(SPIFastRead_io_enqRdy) 2322 | ); 2323 | Fifo Fifo ( 2324 | .clock(Fifo_clock), 2325 | .reset(Fifo_reset), 2326 | .io_enqVal(Fifo_io_enqVal), 2327 | .io_enqRdy(Fifo_io_enqRdy), 2328 | .io_deqVal(Fifo_io_deqVal), 2329 | .io_deqRdy(Fifo_io_deqRdy), 2330 | .io_enqDat(Fifo_io_enqDat), 2331 | .io_deqDat(Fifo_io_deqDat) 2332 | ); 2333 | DoubleBarrel DoubleBarrel ( 2334 | .clock(DoubleBarrel_clock), 2335 | .reset(DoubleBarrel_reset), 2336 | .io_ADDR_IN(DoubleBarrel_io_ADDR_IN), 2337 | .io_ADDR_SET(DoubleBarrel_io_ADDR_SET), 2338 | .io_DATA_READY(DoubleBarrel_io_DATA_READY), 2339 | .io_DATA_IN(DoubleBarrel_io_DATA_IN), 2340 | .io_DATA_OUT(DoubleBarrel_io_DATA_OUT), 2341 | .io_TRIGGER(DoubleBarrel_io_TRIGGER), 2342 | .io_deqRdy(DoubleBarrel_io_deqRdy), 2343 | .io_dataVal(DoubleBarrel_io_dataVal), 2344 | .io_EN(DoubleBarrel_io_EN), 2345 | .io_A(DoubleBarrel_io_A) 2346 | ); 2347 | SWD SWD ( 2348 | .clock(SWD_clock), 2349 | .reset(SWD_reset), 2350 | .io_SWCLK(SWD_io_SWCLK), 2351 | .io_DATA(SWD_io_DATA), 2352 | .io_DATA_READY(SWD_io_DATA_READY), 2353 | .io_deqRdy(SWD_io_deqRdy), 2354 | .io_CLKDIV(SWD_io_CLKDIV), 2355 | .io_A(SWD_io_A), 2356 | .io_D_IN_0(SWD_io_D_IN_0), 2357 | .io_D_OUT_0(SWD_io_D_OUT_0), 2358 | .io_OUTPUT_ENABLE(SWD_io_OUTPUT_ENABLE), 2359 | .io_ERROR(SWD_io_ERROR), 2360 | .io_EN(SWD_io_EN) 2361 | ); 2362 | SB_IO #(.PIN_TYPE("6'b101001"), .PULLUP(0)) SB_IO ( 2363 | .D_IN_0(SB_IO_D_IN_0), 2364 | .D_OUT_0(SB_IO_D_OUT_0), 2365 | .OUTPUT_ENABLE(SB_IO_OUTPUT_ENABLE), 2366 | .PACKAGE_PIN(SB_IO_PACKAGE_PIN) 2367 | ); 2368 | SB_IO #(.PIN_TYPE("6'b101001"), .PULLUP(0)) SB_IO_1 ( 2369 | .D_IN_0(SB_IO_1_D_IN_0), 2370 | .D_OUT_0(SB_IO_1_D_OUT_0), 2371 | .OUTPUT_ENABLE(SB_IO_1_OUTPUT_ENABLE), 2372 | .PACKAGE_PIN(SB_IO_1_PACKAGE_PIN) 2373 | ); 2374 | assign _T_21 = SPIDecode_io_dataOut[0]; 2375 | assign _T_23 = SPIDecode_io_addr == 3'h1; 2376 | assign _T_24 = _T_23 & SPIDecode_io_wclk; 2377 | assign _T_26 = SPIDecode_io_addr == 3'h2; 2378 | assign _T_27 = _T_26 & SPIDecode_io_wclk; 2379 | assign _T_29 = SPIDecode_io_addr == 3'h3; 2380 | assign _T_30 = _T_29 & SPIDecode_io_wclk; 2381 | assign _T_32 = SPIDecode_io_addr == 3'h4; 2382 | assign _T_33 = _T_32 & SPIDecode_io_wclk; 2383 | assign _T_35 = SPIDecode_io_addr == 3'h5; 2384 | assign _T_36 = _T_35 & SPIDecode_io_wclk; 2385 | assign _T_38 = SPIDecode_io_addr == 3'h0; 2386 | assign _GEN_0 = _T_35 ? AddrReg_1_io_dout : 24'h0; 2387 | assign _GEN_1 = _T_32 ? {{20'd0}, ClkDivReg_io_dout} : _GEN_0; 2388 | assign _GEN_2 = _T_29 ? LengthReg_io_dout : _GEN_1; 2389 | assign _GEN_3 = _T_26 ? AddrReg_io_dout : _GEN_2; 2390 | assign _GEN_4 = _T_23 ? {{22'd0}, StatusReg_io_dout} : _GEN_3; 2391 | assign _GEN_5 = _T_38 ? 24'h55 : _GEN_4; 2392 | assign _T_51 = StatusReg_io_dout[0]; 2393 | assign _T_52 = ~ _T_51; 2394 | assign _T_54 = SPIFastRead_io_DATA_READY & EdgeBuffer_io_out; 2395 | assign _T_56 = LengthReg_io_dout != 24'h0; 2396 | assign _T_57 = _T_56 & EdgeBuffer_io_out; 2397 | assign _T_58 = DoubleBarrel_io_dataVal & Fifo_io_deqVal; 2398 | assign _T_61 = LengthReg_io_dout == 24'h0; 2399 | assign _T_62 = ~ Fifo_io_deqVal; 2400 | assign _T_63 = _T_61 & _T_62; 2401 | assign io_MISO = SPISlave_io_MISO; 2402 | assign io_FLASH_MOSI = SPIFastRead_io_MOSI; 2403 | assign io_FLASH_SCK = SPIFastRead_io_SCK; 2404 | assign io_FLASH_SSEL = _T_52; 2405 | assign io_SWCLK = SB_IO_PACKAGE_PIN; 2406 | assign io_SWDIO = SB_IO_1_PACKAGE_PIN; 2407 | assign io_SPI_READ_OUT = 24'h0; 2408 | assign io_OUTPUT_ENABLE = 1'h0; 2409 | assign io_D_OUT_0 = 1'h0; 2410 | assign io_FAST_READ_DATA_READY = 1'h0; 2411 | assign SB_PLL40_CORE_REFERENCECLK = clock; 2412 | assign SB_PLL40_CORE_BYPASS = 1'h0; 2413 | assign SB_PLL40_CORE_RESETB = 1'h0; 2414 | assign SPISlave_io_MOSI = io_MOSI; 2415 | assign SPISlave_io_SCK = io_SCK; 2416 | assign SPISlave_io_SSEL = io_SSEL; 2417 | assign SPISlave_io_READ_OUT = _GEN_5; 2418 | assign SPISlave_clock = SB_PLL40_CORE_PLLOUTCORE; 2419 | assign SPISlave_reset = reset; 2420 | assign SPIDecode_io_dataIn = SPISlave_io_DATA[27:0]; 2421 | assign SPIDecode_io_trigger = SPISlave_io_DATA_READY; 2422 | assign SPIDecode_clock = SB_PLL40_CORE_PLLOUTCORE; 2423 | assign StatusReg_io_en = _T_24; 2424 | assign StatusReg_io_din = _T_21; 2425 | assign StatusReg_io_done = _T_63; 2426 | assign StatusReg_io_error = SWD_io_ERROR; 2427 | assign StatusReg_clock = SB_PLL40_CORE_PLLOUTCORE; 2428 | assign StatusReg_reset = reset; 2429 | assign AddrReg_io_en = _T_27; 2430 | assign AddrReg_io_din = SPIDecode_io_dataOut; 2431 | assign AddrReg_clock = SB_PLL40_CORE_PLLOUTCORE; 2432 | assign AddrReg_reset = reset; 2433 | assign LengthReg_io_en = _T_30; 2434 | assign LengthReg_io_dec = SPIFastRead_io_DATA_READY; 2435 | assign LengthReg_io_din = SPIDecode_io_dataOut; 2436 | assign LengthReg_clock = SB_PLL40_CORE_PLLOUTCORE; 2437 | assign LengthReg_reset = reset; 2438 | assign ClkDivReg_io_en = _T_33; 2439 | assign ClkDivReg_io_din = SPIDecode_io_dataOut[3:0]; 2440 | assign ClkDivReg_clock = SB_PLL40_CORE_PLLOUTCORE; 2441 | assign ClkDivReg_reset = reset; 2442 | assign AddrReg_1_io_en = _T_36; 2443 | assign AddrReg_1_io_din = SPIDecode_io_dataOut; 2444 | assign AddrReg_1_clock = SB_PLL40_CORE_PLLOUTCORE; 2445 | assign AddrReg_1_reset = reset; 2446 | assign EdgeBuffer_io_in = _T_51; 2447 | assign EdgeBuffer_clock = SB_PLL40_CORE_PLLOUTCORE; 2448 | assign SPIFastRead_io_MISO = io_FLASH_MISO; 2449 | assign SPIFastRead_io_ADDR = AddrReg_io_dout; 2450 | assign SPIFastRead_io_EN = _T_57; 2451 | assign SPIFastRead_io_enqRdy = Fifo_io_enqRdy; 2452 | assign SPIFastRead_clock = SB_PLL40_CORE_PLLOUTCORE; 2453 | assign Fifo_io_enqVal = _T_54; 2454 | assign Fifo_io_deqRdy = DoubleBarrel_io_deqRdy; 2455 | assign Fifo_io_enqDat = SPIFastRead_io_DATA; 2456 | assign Fifo_clock = SB_PLL40_CORE_PLLOUTCORE; 2457 | assign Fifo_reset = reset; 2458 | assign DoubleBarrel_io_ADDR_IN = {{8'd0}, AddrReg_1_io_dout}; 2459 | assign DoubleBarrel_io_ADDR_SET = EdgeBuffer_io_rising; 2460 | assign DoubleBarrel_io_DATA_READY = Fifo_io_deqVal; 2461 | assign DoubleBarrel_io_DATA_IN = Fifo_io_deqDat; 2462 | assign DoubleBarrel_io_TRIGGER = SWD_io_deqRdy; 2463 | assign DoubleBarrel_io_EN = EdgeBuffer_io_out; 2464 | assign DoubleBarrel_clock = SB_PLL40_CORE_PLLOUTCORE; 2465 | assign DoubleBarrel_reset = reset; 2466 | assign SWD_io_DATA = DoubleBarrel_io_DATA_OUT; 2467 | assign SWD_io_DATA_READY = _T_58; 2468 | assign SWD_io_CLKDIV = ClkDivReg_io_dout; 2469 | assign SWD_io_A = DoubleBarrel_io_A; 2470 | assign SWD_io_D_IN_0 = SB_IO_1_D_IN_0; 2471 | assign SWD_io_EN = EdgeBuffer_io_out; 2472 | assign SWD_clock = SB_PLL40_CORE_PLLOUTCORE; 2473 | assign SWD_reset = reset; 2474 | assign SB_IO_D_OUT_0 = SWD_io_SWCLK; 2475 | assign SB_IO_OUTPUT_ENABLE = EdgeBuffer_io_out; 2476 | assign SB_IO_1_D_OUT_0 = SWD_io_D_OUT_0; 2477 | assign SB_IO_1_OUTPUT_ENABLE = SWD_io_OUTPUT_ENABLE; 2478 | endmodule 2479 | -------------------------------------------------------------------------------- /build.sbt: -------------------------------------------------------------------------------- 1 | name := "chisel-module-template" 2 | 3 | version := "1.0" 4 | 5 | scalaVersion := "2.11.7" 6 | 7 | scalacOptions ++= Seq("-deprecation", "-feature", "-unchecked", "-language:reflectiveCalls") 8 | 9 | testOptions += Tests.Setup(_ => sys.props("testing") = "true") 10 | 11 | resolvers ++= Seq( 12 | Resolver.sonatypeRepo("snapshots"), 13 | Resolver.sonatypeRepo("releases") 14 | ) 15 | 16 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 17 | val defaultVersions = Map( 18 | "chisel3" -> "3.0-SNAPSHOT", 19 | "chisel-iotesters" -> "1.1-SNAPSHOT" 20 | ) 21 | 22 | libraryDependencies ++= (Seq("chisel3","chisel-iotesters").map { 23 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }) 24 | 25 | libraryDependencies ++= Seq( 26 | "org.scalatest" %% "scalatest" % "2.2.5", 27 | "org.scalacheck" %% "scalacheck" % "1.12.4") -------------------------------------------------------------------------------- /fpga_swd_2/fpga_swd.h: -------------------------------------------------------------------------------- 1 | #ifndef LIB_FPGA_SWD_H 2 | #define LIB_FPGA_SWD_H 3 | 4 | #include 5 | 6 | #define ICESWD_DID 0x00 7 | #define ICESWD_STATUS 0x01 8 | #define ICESWD_ADDR_READ 0x02 9 | #define ICESWD_LENGTH 0x03 10 | #define ICESWD_CLKDIV 0x04 11 | #define ICESWD_ADDR_WRITE 0x05 12 | 13 | #define ICESWD_HW_ID_CODE 0x55 14 | 15 | class ICESWD { 16 | public: 17 | ICESWD(uint8_t cs, uint8_t reset) : _cs(cs), _reset(reset) {} 18 | ~ICESWD() {} 19 | 20 | bool begin() 21 | { 22 | pinMode (_reset, OUTPUT); 23 | digitalWrite(_reset, HIGH); //hold in reset 24 | pinMode (_cs, OUTPUT); 25 | digitalWrite(_cs, HIGH); 26 | 27 | // initialize SPI: 28 | SPI.begin(); 29 | 30 | return true; 31 | } 32 | 33 | bool program(uint32_t readAddr, uint32_t writeAddr, uint32_t len, uint8_t clkdiv = 7){ 34 | digitalWrite(_reset, LOW); //start 35 | 36 | if(readReg(ICESWD_DID) != 0x55){ 37 | return false; 38 | } 39 | 40 | writeReg(ICESWD_ADDR_READ, readAddr); 41 | writeReg(ICESWD_ADDR_WRITE, writeAddr); 42 | writeReg(ICESWD_LENGTH, len); 43 | 44 | writeReg(ICESWD_CLKDIV, clkdiv); 45 | 46 | writeReg(ICESWD_STATUS, 1); 47 | 48 | return true; 49 | } 50 | 51 | uint32_t readReg(uint8_t reg) 52 | { 53 | digitalWrite(_cs, LOW); 54 | SPI.transfer(reg); 55 | SPI.transfer(0); 56 | SPI.transfer16(0); 57 | digitalWrite(_cs, HIGH); 58 | 59 | digitalWrite(_cs, LOW); 60 | //gives 24 bit output 61 | uint8_t b3 = SPI.transfer(0x01); 62 | uint8_t b2 = SPI.transfer(0x00); 63 | uint8_t b1 = SPI.transfer(0x00); 64 | digitalWrite(_cs, HIGH); 65 | 66 | uint32_t val = ((uint32_t)b3 << 16) | ((uint32_t)b2 << 8) | b1; 67 | 68 | return val; 69 | } 70 | 71 | void writeReg(uint8_t reg, uint32_t val) 72 | { 73 | uint8_t cmd = (1 << 3) | reg; 74 | 75 | uint8_t dHigh = (val >> 16) & 0xFF; 76 | uint16_t dLow = val & 0xFFFF; 77 | 78 | digitalWrite(_cs, LOW); 79 | SPI.transfer(cmd); 80 | SPI.transfer(dHigh); 81 | SPI.transfer16(dLow); 82 | digitalWrite(_cs, HIGH); 83 | } 84 | 85 | private: 86 | uint8_t _cs, _reset; 87 | }; 88 | 89 | #endif 90 | -------------------------------------------------------------------------------- /fpga_swd_2/fpga_swd_2.ino: -------------------------------------------------------------------------------- 1 | #include "Adafruit_DAP.h" 2 | #include "fpga_swd.h" 3 | 4 | #define SWDIO 8 5 | #define SWCLK 9 6 | #define SWRST 11 7 | 8 | #define ICECS 10 9 | #define ICERST 4 10 | 11 | #define READ_ADDR 140288 12 | #define WRITE_ADDR 0x00 13 | #define LENGTH (186608 / 4) 14 | 15 | //create a DAP for programming Atmel SAM devices 16 | Adafruit_DAP_SAM dap; 17 | 18 | ICESWD ice(10, 4); 19 | 20 | // Function called when there's an SWD error 21 | void error(const char *text) { 22 | Serial.println(text); 23 | while (1); 24 | } 25 | 26 | 27 | void setup() { 28 | pinMode(13, OUTPUT); 29 | Serial.begin(115200); 30 | while(!Serial) { 31 | delay(1); // will pause the chip until it opens serial console 32 | } 33 | 34 | //init the fpga 35 | ice.begin(); 36 | 37 | dap.begin(SWCLK, SWDIO, SWRST, &error); 38 | 39 | Serial.print("Connecting..."); 40 | if (! dap.dap_disconnect()) error(dap.error_message); 41 | 42 | char debuggername[100]; 43 | if (! dap.dap_get_debugger_info(debuggername)) error(dap.error_message); 44 | Serial.print(debuggername); Serial.print("\n\r"); 45 | 46 | if (! dap.dap_connect()) error(dap.error_message); 47 | 48 | if (! dap.dap_transfer_configure(0, 128, 128)) error(dap.error_message); 49 | if (! dap.dap_swd_configure(0)) error(dap.error_message); 50 | if (! dap.dap_reset_link()) error(dap.error_message); 51 | if (! dap.dap_swj_clock(50)) error(dap.error_message); 52 | dap.dap_target_prepare(); 53 | 54 | uint32_t dsu_did; 55 | if (! dap.select(&dsu_did)) { 56 | Serial.print("Unknown device found 0x"); Serial.print(dsu_did, HEX); 57 | error("Unknown device found"); 58 | } 59 | for (device_t *device = dap.devices; device->dsu_did > 0; device++) { 60 | if (device->dsu_did == dsu_did) { 61 | Serial.print("Found Target: "); 62 | Serial.print(device->name); 63 | Serial.print("\tFlash size: "); 64 | Serial.print(device->flash_size); 65 | Serial.print("\tFlash pages: "); 66 | Serial.println(device->n_pages); 67 | //Serial.print("Page size: "); Serial.println(device->flash_size / device->n_pages); 68 | } 69 | } 70 | 71 | Serial.println(" done."); 72 | 73 | Serial.print("Erasing... "); 74 | dap.erase(); 75 | Serial.println(" done."); 76 | 77 | unsigned long t = millis(); 78 | Serial.print("Programming... "); 79 | //program here 80 | pinMode(SWDIO, INPUT); 81 | pinMode(SWCLK, INPUT); 82 | 83 | if(!ice.program(READ_ADDR, WRITE_ADDR, LENGTH)){ 84 | error("failed to communicate with ICESWD!"); 85 | } 86 | 87 | //wait to finish 88 | while(ice.readReg(ICESWD_STATUS) != 0x03){ 89 | delay(1); 90 | } 91 | 92 | ice.writeReg(ICESWD_STATUS, 0); 93 | 94 | pinMode(SWDIO, OUTPUT); 95 | pinMode(SWCLK, OUTPUT); 96 | 97 | Serial.print("\nDone!..."); 98 | Serial.print( (LENGTH * 4) / (millis() - t) * 1000 ); 99 | Serial.println(" b/s"); 100 | dap.dap_set_clock(50); 101 | 102 | dap.deselect(); 103 | dap.dap_disconnect(); 104 | } 105 | 106 | void loop() { 107 | //blink led on the host to show we're done 108 | digitalWrite(13, HIGH); 109 | delay(500); 110 | digitalWrite(13, LOW); 111 | delay(500); 112 | } 113 | -------------------------------------------------------------------------------- /icestick.pcf: -------------------------------------------------------------------------------- 1 | # ############################################################################## 2 | 3 | # iCEstick PCF 4 | 5 | # ############################################################################## 6 | 7 | # Since Arachne doesn't seem to like ignoring unused constraints 8 | # You will have to put ## in front of things you aren't using 9 | # And then remove ## from anything you are using 10 | # (## so you don't accidentally remove # comments) 11 | 12 | # Clock 13 | set_io clock 21 # 12 MHz clock 14 | 15 | # LEDs 16 | ##set_io io_led0 95 # green 17 | ##set_io io_led1 99 # red 18 | ##set_io io_led2 98 # red 19 | ##set_io io_led3 97 # red 20 | #set_io io_led4 96 # red 21 | 22 | # IRDA interface 23 | ##set_io IRRXD 106 24 | ##set_io IRTXD 105 25 | ##set_io IRSD 107 26 | 27 | # SPI (to configuration EEPROM) 28 | set_io io_FLASH_SCK 70 29 | set_io io_FLASH_MISO 68 30 | set_io io_FLASH_MOSI 67 31 | set_io io_FLASH_SSEL 71 32 | 33 | # J1 34 | # set_io J1_1 3.3V 35 | # set_io J1_2 GND 36 | ##set_io J1_3 112 # PIO0_02 37 | ##set_io J1_4 113 # PIO0_03 38 | ##set_io J1_5 114 # PIO0_04 39 | ##set_io J1_6 115 # PIO0_05 40 | ##set_io J1_7 116 # PIO0_06 PMOD pin 7 41 | ##set_io J1_8 117 # PIO0_07 PMOD pin 8 42 | ##set_io J1_9 118 # PIO0_08 PMOD pin 9 43 | ##set_io J1_10 119 # PIO0_09 PMOD pin 10 44 | 45 | # J3 46 | # set_io J3_1 3.3V 47 | # set_io J3_2 GND 48 | set_io io_MOSI 62 # PIO2_17 49 | set_io io_MISO 61 # PIO2_16 50 | set_io io_SCK 60 # PIO2_15 51 | set_io io_SSEL 56 # PIO2_14 52 | ##set_io J3_7 48 # PIO2_13 53 | ##set_io J3_8 47 # PIO2_12 54 | set_io io_SWCLK 45 # PIO2_11 55 | set_io io_SWDIO 44 # PIO2_10 56 | 57 | # PMOD 58 | # Note: pin 5 and 11 are ground, pins 6 and 12 are Vcc 59 | set_io reset 78 # PIO1_02 60 | ##set_io io_SCK 79 # PIO1_03 61 | ##set_io io_pmod3 80 # PIO1_04 62 | ##set_io io_pmod4 81 # PIO1_05 63 | ##set_io PMOD7 87 # PIO1_06 64 | ##set_io PMOD8 88 # PIO1_07 65 | ##set_io PMOD9 90 # PIO1_08 66 | ##set_io PMOD10 91 # PIO1_09 67 | 68 | # FTDI Port B UART 69 | #set_io DCDn 1 70 | #set_io DSRn 2 71 | #set_io DTRn 3 72 | #set_io CTSn 4 73 | #set_io RTSn 7 74 | #set_io RS232_Tx 8 75 | #set_io RS232_Rx 9 76 | 77 | # Config pins 78 | #set_io CDONE 65 79 | #set_io CRESET_B 66 -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 0.13.11 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn -------------------------------------------------------------------------------- /project/project/target/config-classes/$11933bf543191ceb629c$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/project/target/config-classes/$11933bf543191ceb629c$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/project/target/config-classes/$11933bf543191ceb629c$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/project/target/config-classes/$11933bf543191ceb629c$.class -------------------------------------------------------------------------------- /project/project/target/config-classes/$11933bf543191ceb629c.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/project/target/config-classes/$11933bf543191ceb629c.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/project/target/config-classes/$11933bf543191ceb629c.class -------------------------------------------------------------------------------- /project/target/config-classes/$052a44782576165ef6f2$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$052a44782576165ef6f2$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$052a44782576165ef6f2$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$052a44782576165ef6f2$.class -------------------------------------------------------------------------------- /project/target/config-classes/$052a44782576165ef6f2.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$052a44782576165ef6f2.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$052a44782576165ef6f2.class -------------------------------------------------------------------------------- /project/target/config-classes/$1a69ab55e3e6247115a5$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$1a69ab55e3e6247115a5$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$1a69ab55e3e6247115a5$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$1a69ab55e3e6247115a5$.class -------------------------------------------------------------------------------- /project/target/config-classes/$1a69ab55e3e6247115a5.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$1a69ab55e3e6247115a5.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$1a69ab55e3e6247115a5.class -------------------------------------------------------------------------------- /project/target/config-classes/$4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1$$anonfun$apply$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1$$anonfun$apply$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$4fbf35c5103c86f5cb40$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$4fbf35c5103c86f5cb40$.class -------------------------------------------------------------------------------- /project/target/config-classes/$4fbf35c5103c86f5cb40.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$4fbf35c5103c86f5cb40.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$4fbf35c5103c86f5cb40.class -------------------------------------------------------------------------------- /project/target/config-classes/$81eec9ef00c970e0dbd8$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$81eec9ef00c970e0dbd8$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$81eec9ef00c970e0dbd8$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$81eec9ef00c970e0dbd8$.class -------------------------------------------------------------------------------- /project/target/config-classes/$81eec9ef00c970e0dbd8.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$81eec9ef00c970e0dbd8.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$81eec9ef00c970e0dbd8.class -------------------------------------------------------------------------------- /project/target/config-classes/$ac15debf6f88ea3e5bfd$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$ac15debf6f88ea3e5bfd$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$ac15debf6f88ea3e5bfd$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$ac15debf6f88ea3e5bfd$.class -------------------------------------------------------------------------------- /project/target/config-classes/$ac15debf6f88ea3e5bfd.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$ac15debf6f88ea3e5bfd.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$ac15debf6f88ea3e5bfd.class -------------------------------------------------------------------------------- /project/target/config-classes/$bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1$$anonfun$apply$1$$anonfun$apply$2.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1$$anonfun$apply$1$$anonfun$apply$2.class -------------------------------------------------------------------------------- /project/target/config-classes/$bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1$$anonfun$apply$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1$$anonfun$apply$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$bf8e52aab5b52bddfe2e$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$bf8e52aab5b52bddfe2e$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$bf8e52aab5b52bddfe2e$.class -------------------------------------------------------------------------------- /project/target/config-classes/$bf8e52aab5b52bddfe2e.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$bf8e52aab5b52bddfe2e.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$bf8e52aab5b52bddfe2e.class -------------------------------------------------------------------------------- /project/target/config-classes/$c992c1ac736499f537bc$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$c992c1ac736499f537bc$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$c992c1ac736499f537bc$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$c992c1ac736499f537bc$.class -------------------------------------------------------------------------------- /project/target/config-classes/$c992c1ac736499f537bc.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$c992c1ac736499f537bc.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$c992c1ac736499f537bc.class -------------------------------------------------------------------------------- /project/target/config-classes/$d55667a6a7da34c38cfb$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$d55667a6a7da34c38cfb$.class -------------------------------------------------------------------------------- /project/target/config-classes/$d55667a6a7da34c38cfb.cache: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$d55667a6a7da34c38cfb.cache -------------------------------------------------------------------------------- /project/target/config-classes/$d55667a6a7da34c38cfb.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$d55667a6a7da34c38cfb.class -------------------------------------------------------------------------------- /project/target/config-classes/$d698e6ac6a1561aee690$$anonfun$$sbtdef$1.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$d698e6ac6a1561aee690$$anonfun$$sbtdef$1.class -------------------------------------------------------------------------------- /project/target/config-classes/$d698e6ac6a1561aee690$.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$d698e6ac6a1561aee690$.class -------------------------------------------------------------------------------- /project/target/config-classes/$d698e6ac6a1561aee690.cache: -------------------------------------------------------------------------------- 1 | sbt.internals.DslEntry -------------------------------------------------------------------------------- /project/target/config-classes/$d698e6ac6a1561aee690.class: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/config-classes/$d698e6ac6a1561aee690.class -------------------------------------------------------------------------------- /project/target/resolution-cache/default/fpga_swd-build/scala_2.10/sbt_0.13/0.1-SNAPSHOT/resolved.xml.properties: -------------------------------------------------------------------------------- 1 | #default#fpga_swd-build;0.1-SNAPSHOT resolved revisions 2 | #Fri Sep 01 16:05:23 GMT 2017 3 | +organisation\:\#@\#\:+org.scala-lang\:\#@\#\:+branch\:\#@\#\:+@\#\:NULL\:\#@\:\#@\#\:+module\:\#@\#\:+scala-library\:\#@\#\:+revision\:\#@\#\:+2.10.6\:\#@\#\:=2.10.6 ? 2.10.6 null 4 | +organisation\:\#@\#\:+org.scala-sbt\:\#@\#\:+branch\:\#@\#\:+@\#\:NULL\:\#@\:\#@\#\:+module\:\#@\#\:+sbt\:\#@\#\:+revision\:\#@\#\:+0.13.11\:\#@\#\:=0.13.11 release 0.13.11 null 5 | +organisation\:\#@\#\:+org.scala-lang\:\#@\#\:+branch\:\#@\#\:+@\#\:NULL\:\#@\:\#@\#\:+module\:\#@\#\:+scala-compiler\:\#@\#\:+revision\:\#@\#\:+2.10.6\:\#@\#\:=2.10.6 release 2.10.6 null 6 | -------------------------------------------------------------------------------- /project/target/resolution-cache/default/fpga_swd-build/scala_2.10/sbt_0.13/0.1-SNAPSHOT/resolved.xml.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 11 | fpga_swd-build 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-compile.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-docs.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-optional.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-plugin.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-pom.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-runtime-internal.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-runtime.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-scala-tool.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-sources.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/default-fpga_swd-build-test.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/ivy-report.css: -------------------------------------------------------------------------------- 1 | /* 2 | * Licensed to the Apache Software Foundation (ASF) under one or more 3 | * contributor license agreements. See the NOTICE file distributed with 4 | * this work for additional information regarding copyright ownership. 5 | * The ASF licenses this file to You under the Apache License, Version 2.0 6 | * (the "License"); you may not use this file except in compliance with 7 | * the License. You may obtain a copy of the License at 8 | * 9 | * http://www.apache.org/licenses/LICENSE-2.0 10 | * 11 | * Unless required by applicable law or agreed to in writing, software 12 | * distributed under the License is distributed on an "AS IS" BASIS, 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 | * See the License for the specific language governing permissions and 15 | * limitations under the License. 16 | * 17 | */ 18 | 19 | body { 20 | font-family:"Trebuchet MS",Verdana,Geneva,Arial,Helvetica,sans-serif; 21 | font-size:small; 22 | } 23 | 24 | div#logo { 25 | float: right; 26 | padding-left: 10px; 27 | padding-bottom: 10px; 28 | background: white; 29 | text-align: center; 30 | } 31 | 32 | #logo img { 33 | border: 0; 34 | } 35 | 36 | div#date { 37 | font-style: italic; 38 | padding-left: 60px; 39 | padding-bottom: 40px; 40 | } 41 | 42 | 43 | h1 { 44 | margin-bottom:2px; 45 | 46 | border-color:#7A9437; 47 | border-style:solid; 48 | border-width:0 0 3px 0; 49 | } 50 | 51 | span#module { 52 | color:#7A9437; 53 | text-decoration:none; 54 | } 55 | 56 | span#organisation { 57 | color:black; 58 | text-decoration:none; 59 | } 60 | 61 | #confmenu { 62 | color: #000; 63 | border-bottom: 2px solid black; 64 | margin: 12px 0px 0px 0px; 65 | padding: 0px; 66 | z-index: 1; 67 | padding-left: 10px 68 | } 69 | 70 | #confmenu li { 71 | display: inline; 72 | overflow: hidden; 73 | list-style-type: none; 74 | } 75 | 76 | #confmenu a, a.active { 77 | color: #DEDECF; 78 | background: #898B5E; 79 | font: bold 1em "Trebuchet MS", Arial, sans-serif; 80 | border: 2px solid black; 81 | padding: 2px 5px 0px 5px; 82 | text-decoration: none; 83 | } 84 | 85 | /* 86 | background: #ABAD85 #CED4BD 87 | background: #DEE4CD 88 | */ 89 | 90 | #confmenu a.active { 91 | color: #7A9437; 92 | background: #DEE4CD; 93 | border-bottom: 3px solid #DEE4CD; 94 | } 95 | 96 | #confmenu a:hover { 97 | color: #fff; 98 | background: #ADC09F; 99 | } 100 | 101 | #confmenu a:visited { 102 | color: #DEDECF; 103 | } 104 | 105 | #confmenu a.active:visited { 106 | color: #7A9437; 107 | } 108 | 109 | #confmenu a.active:hover { 110 | background: #DEE4CD; 111 | color: #DEDECF; 112 | } 113 | 114 | #content { 115 | background: #DEE4CD; 116 | padding: 20px; 117 | border: 2px solid black; 118 | border-top: none; 119 | z-index: 2; 120 | } 121 | 122 | #content a { 123 | text-decoration: none; 124 | color: #E8E9BE; 125 | } 126 | 127 | #content a:hover { 128 | background: #898B5E; 129 | } 130 | 131 | 132 | h2 { 133 | margin-bottom:2px; 134 | font-size:medium; 135 | 136 | border-color:#7A9437; 137 | border-style:solid; 138 | border-width:0 0 2px 0; 139 | } 140 | 141 | h3 { 142 | margin-top:30px; 143 | margin-bottom:2px; 144 | padding: 5 5 5 0; 145 | font-size: 24px; 146 | border-style:solid; 147 | border-width:0 0 2px 0; 148 | } 149 | 150 | h4 { 151 | margin-bottom:2px; 152 | margin-top:2px; 153 | font-size:medium; 154 | 155 | border-color:#7A9437; 156 | border-style:dashed; 157 | border-width:0 0 1px 0; 158 | } 159 | 160 | h5 { 161 | margin-bottom:2px; 162 | margin-top:2px; 163 | margin-left:20px; 164 | font-size:medium; 165 | } 166 | 167 | span.resolved { 168 | padding-left: 15px; 169 | font-weight: 500; 170 | font-size: small; 171 | } 172 | 173 | 174 | #content table { 175 | border-collapse:collapse; 176 | width:90%; 177 | margin:auto; 178 | margin-top: 5px; 179 | } 180 | #content thead { 181 | background-color:#CED4BD; 182 | border:1px solid #7A9437; 183 | } 184 | #content tbody { 185 | border-collapse:collapse; 186 | background-color:#FFFFFF; 187 | border:1px solid #7A9437; 188 | } 189 | 190 | #content th { 191 | font-family:monospace; 192 | border:1px solid #7A9437; 193 | padding:5px; 194 | } 195 | 196 | #content td { 197 | border:1px dotted #7A9437; 198 | padding:0 3 0 3; 199 | } 200 | 201 | #content table a { 202 | color:#7A9437; 203 | text-decoration:none; 204 | } 205 | 206 | #content table a:hover { 207 | background-color:#CED4BD; 208 | color:#7A9437; 209 | } 210 | 211 | 212 | 213 | table.deps { 214 | border-collapse:collapse; 215 | width:90%; 216 | margin:auto; 217 | margin-top: 5px; 218 | } 219 | 220 | table.deps thead { 221 | background-color:#CED4BD; 222 | border:1px solid #7A9437; 223 | } 224 | table.deps tbody { 225 | border-collapse:collapse; 226 | background-color:#FFFFFF; 227 | border:1px solid #7A9437; 228 | } 229 | 230 | table.deps th { 231 | font-family:monospace; 232 | border:1px solid #7A9437; 233 | padding:2; 234 | } 235 | 236 | table.deps td { 237 | border:1px dotted #7A9437; 238 | padding:0 3 0 3; 239 | } 240 | 241 | 242 | 243 | 244 | 245 | table.header { 246 | border:0; 247 | width:90%; 248 | margin:auto; 249 | margin-top: 5px; 250 | } 251 | 252 | table.header thead { 253 | border:0; 254 | } 255 | table.header tbody { 256 | border:0; 257 | } 258 | table.header tr { 259 | padding:0px; 260 | border:0; 261 | } 262 | table.header td { 263 | padding:0 3 0 3; 264 | border:0; 265 | } 266 | 267 | td.title { 268 | width:150px; 269 | margin-right:15px; 270 | 271 | font-size:small; 272 | font-weight:700; 273 | } 274 | 275 | td.title:first-letter { 276 | color:#7A9437; 277 | background-color:transparent; 278 | } 279 | 280 | -------------------------------------------------------------------------------- /project/target/resolution-cache/reports/ivy-report.xsl: -------------------------------------------------------------------------------- 1 | 2 | 20 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 |
51 | No dependency 52 |
53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 |
ModuleRevisionStatusResolverDefaultLicensesSize
78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | #- 96 | 97 | 98 | by 99 | 100 | 101 | 102 | 103 | 104 | #-- 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | kB 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | searched 165 | 166 | 167 | downloaded 168 | 169 | 170 | 171 | http://ant.apache.org/ivy/images/evicted.gif 172 | evicted 173 | evicted by 174 | 175 | 176 | 177 | 178 | http://ant.apache.org/ivy/images/error.gif 179 | error 180 | error: 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | #- 194 | 195 | by 196 | 197 | 198 | 199 | 200 | 201 | #-- 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 |
  • 233 | 234 | 235 | active 236 | 237 | --. 238 | 239 | 240 |
    • 241 |     242 | 243 | 244 | 245 | 246 | -- 247 | 248 | :: 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | Ivy report :: <xsl:value-of select="info/@module"/> by <xsl:value-of select="info/@organisation"/> :: <xsl:value-of select="info/@conf"/> 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 |

    265 | 266 | - 267 | 268 | 269 | 270 | 271 | by 272 | 273 | 274 | 275 |

    276 |
    277 | resolved on 278 | 279 | 280 | 281 |
    282 |
      283 | 284 | 285 | 286 |
    287 | 288 |
    289 |

    Dependencies Stats

    290 | 291 | 292 | 297 | 300 | 303 |
    Modules
    Revisions 293 | ( searched searched, 294 | downloaded downloaded, 295 | evicted evicted, 296 | errors error)
    Artifacts 298 | ( downloaded, 299 | failed)
    Artifacts size kB 301 | ( kB downloaded, 302 | kB in cache)
    304 | 305 | 306 |

    Errors

    307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 |
    ModuleRevisionError
    326 |     327 | 328 | 329 |

    Conflicts

    330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 349 | 358 | 369 | 370 | 371 | 372 |
    ModuleSelectedEvicted
    342 | 343 | #- 344 | 345 | by 346 | 347 | 348 | 350 | 351 | 352 | #-- 353 | 354 | 355 | 356 | 357 | 359 | 360 | 361 | #-- 362 | 363 | 364 | 365 | 366 | 367 | 368 |
    373 |     374 | 375 |

    Dependencies Overview

    376 | 377 | 378 | 379 | 380 | 381 | 382 |

    Details

    383 | 384 |

    385 | 386 | - 387 | 388 | by 389 |

    390 | 391 |

    392 | 393 | -- 394 | 395 | Revision: 396 | 397 | 398 | 399 | 400 | 401 |

    402 | 403 | 404 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 418 | 419 | 424 | 425 | 426 | 437 | 438 |
    Home Page 405 | 406 | 407 | 408 |
    Status
    Publication
    Resolver
    Configurations
    Artifacts size kB 416 | ( kB downloaded, 417 | kB in cache)
    Licenses 420 | 421 | 422 | 423 |
    Evicted by 427 | 428 | 429 | 430 | 431 | 432 | 433 | 434 | 435 | in conflict manager 436 |
    439 |
    Required by
    440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | 453 | 454 | 460 | 461 | 462 | 463 | 464 | 465 | 466 |
    OrganisationNameRevisionIn ConfigurationsAsked Revision
    455 | 456 | #- 457 | 458 | 459 |
    467 | 468 | 469 |
    Dependencies
    470 | 471 | 472 | 473 | 474 | 475 |
    Artifacts
    476 | 477 |
    478 | No artifact 479 |
    480 |     481 | 482 | 483 | 484 | 485 | 486 | 487 | 488 | 489 | 490 | 491 | 492 | 493 | 494 | 495 | 496 | 497 | 498 | 499 | 500 | 501 | 502 | 503 |
    NameTypeExtDownloadSize
    kB
    504 |     505 | 506 |     507 |     508 |     509 |
    510 | 511 | 512 |     513 | 514 |     515 | -------------------------------------------------------------------------------- /project/target/streams/$global/$global/$global/streams/out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/$global/$global/streams/out -------------------------------------------------------------------------------- /project/target/streams/$global/dependencyPositions/$global/streams/update_cache_2.10/input_dsp: -------------------------------------------------------------------------------- 1 | org.scala-lang scala-library2.10.6provided -------------------------------------------------------------------------------- /project/target/streams/$global/dependencyPositions/$global/streams/update_cache_2.10/output_dsp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/dependencyPositions/$global/streams/update_cache_2.10/output_dsp -------------------------------------------------------------------------------- /project/target/streams/$global/ivyConfiguration/$global/streams/out: -------------------------------------------------------------------------------- 1 | [debug] Other repositories: 2 | [debug] Default repositories: 3 | [debug] Using inline dependencies specified in Scala. 4 | -------------------------------------------------------------------------------- /project/target/streams/$global/ivySbt/$global/streams/out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/ivySbt/$global/streams/out -------------------------------------------------------------------------------- /project/target/streams/$global/projectDescriptors/$global/streams/out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/projectDescriptors/$global/streams/out -------------------------------------------------------------------------------- /project/target/streams/$global/update/$global/streams/update_cache_2.10/inputs: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/update/$global/streams/update_cache_2.10/inputs -------------------------------------------------------------------------------- /project/target/streams/$global/update/$global/streams/update_cache_2.10/output: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/update/$global/streams/update_cache_2.10/output -------------------------------------------------------------------------------- /project/target/streams/$global/updateSbtClassifiers/$global/streams/out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/$global/updateSbtClassifiers/$global/streams/out -------------------------------------------------------------------------------- /project/target/streams/compile/$global/$global/discoveredMainClasses/data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /project/target/streams/compile/compile/$global/streams/out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/compile/compile/$global/streams/out -------------------------------------------------------------------------------- /project/target/streams/compile/compileIncremental/$global/streams/export: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/compile/compileIncremental/$global/streams/export -------------------------------------------------------------------------------- /project/target/streams/compile/compileIncremental/$global/streams/out: -------------------------------------------------------------------------------- 1 | [debug] [naha]  2 | [debug] [naha] Initial source changes:  3 | [debug] [naha] removed:Set() 4 | [debug] [naha] added: Set() 5 | [debug] [naha] modified: Set() 6 | [debug] [naha] Invalidated products: Set() 7 | [debug] [naha] External API changes: API Changes: Set() 8 | [debug] [naha] Modified binary dependencies: Set() 9 | [debug] [naha] Initial directly invalidated sources: Set() 10 | [debug] [naha]  11 | [debug] [naha] Sources indirectly invalidated by: 12 | [debug] [naha] product: Set() 13 | [debug] [naha] binary dep: Set() 14 | [debug] [naha] external source: Set() 15 | [debug] All initially invalidated sources: Set() 16 | -------------------------------------------------------------------------------- /project/target/streams/compile/copyResources/$global/streams/copy-resources: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/deanm1278/FPGA_SWD/940942af1d010bc6b33fb4aa5a6dfe25367f56d4/project/target/streams/compile/copyResources/$global/streams/copy-resources -------------------------------------------------------------------------------- /project/target/streams/compile/copyResources/$global/streams/out: -------------------------------------------------------------------------------- 1 | [debug] Copy resource mappings:  2 | [debug]   3 | -------------------------------------------------------------------------------- /project/target/streams/compile/dependencyClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | /home/dean/.sbt/boot/scala-2.10.6/lib/scala-library.jar:/home/dean/.ivy2/cache/org.scala-sbt/sbt/jars/sbt-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/main/jars/main-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/actions/jars/actions-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/classpath/jars/classpath-0.13.11.jar:/home/dean/.sbt/boot/scala-2.10.6/lib/scala-compiler.jar:/home/dean/.sbt/boot/scala-2.10.6/lib/scala-reflect.jar:/home/dean/.ivy2/cache/org.scala-sbt/interface/jars/interface-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/io/jars/io-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/control/jars/control-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/launcher-interface/jars/launcher-interface-1.0.0-M1.jar:/home/dean/.ivy2/cache/org.scala-sbt/completion/jars/completion-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/collections/jars/collections-0.13.11.jar:/home/dean/.ivy2/cache/jline/jline/jars/jline-2.13.jar:/home/dean/.ivy2/cache/org.fusesource.jansi/jansi/jars/jansi-1.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/api/jars/api-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/classfile/jars/classfile-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/logging/jars/logging-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/process/jars/process-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-integration/jars/compiler-integration-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/incremental-compiler/jars/incremental-compiler-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/relation/jars/relation-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compile/jars/compile-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/persist/jars/persist-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-tools.sbinary/sbinary_2.10/jars/sbinary_2.10-0.4.2.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-ivy-integration/jars/compiler-ivy-integration-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/ivy/jars/ivy-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/cross/jars/cross-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt.ivy/ivy/jars/ivy-2.3.0-sbt-2cc8d2761242b072cedb0a04cb39435c4fa24f9a.jar:/home/dean/.ivy2/cache/com.jcraft/jsch/jars/jsch-0.1.46.jar:/home/dean/.ivy2/cache/org.scala-sbt/serialization_2.10/jars/serialization_2.10-0.1.2.jar:/home/dean/.ivy2/cache/org.scala-lang.modules/scala-pickling_2.10/jars/scala-pickling_2.10-0.10.1.jar:/home/dean/.ivy2/cache/org.scalamacros/quasiquotes_2.10/jars/quasiquotes_2.10-2.0.1.jar:/home/dean/.ivy2/cache/org.json4s/json4s-core_2.10/jars/json4s-core_2.10-3.2.10.jar:/home/dean/.ivy2/cache/org.json4s/json4s-ast_2.10/jars/json4s-ast_2.10-3.2.10.jar:/home/dean/.ivy2/cache/com.thoughtworks.paranamer/paranamer/jars/paranamer-2.6.jar:/home/dean/.ivy2/cache/org.spire-math/jawn-parser_2.10/jars/jawn-parser_2.10-0.6.0.jar:/home/dean/.ivy2/cache/org.spire-math/json4s-support_2.10/jars/json4s-support_2.10-0.6.0.jar:/home/dean/.ivy2/cache/org.scala-sbt/run/jars/run-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/task-system/jars/task-system-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/tasks/jars/tasks-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/tracking/jars/tracking-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/cache/jars/cache-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/testing/jars/testing-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/test-agent/jars/test-agent-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/test-interface/jars/test-interface-1.0.jar:/home/dean/.ivy2/cache/org.scala-sbt/main-settings/jars/main-settings-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/apply-macro/jars/apply-macro-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/command/jars/command-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/logic/jars/logic-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-interface/jars/compiler-interface-0.13.11.jar 2 | -------------------------------------------------------------------------------- /project/target/streams/compile/exportedProducts/$global/streams/export: -------------------------------------------------------------------------------- 1 | /mnt/c/ChiselProjects/FPGA_SWD/project/target/scala-2.10/sbt-0.13/classes 2 | -------------------------------------------------------------------------------- /project/target/streams/compile/externalDependencyClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | /home/dean/.sbt/boot/scala-2.10.6/lib/scala-library.jar:/home/dean/.ivy2/cache/org.scala-sbt/sbt/jars/sbt-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/main/jars/main-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/actions/jars/actions-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/classpath/jars/classpath-0.13.11.jar:/home/dean/.sbt/boot/scala-2.10.6/lib/scala-compiler.jar:/home/dean/.sbt/boot/scala-2.10.6/lib/scala-reflect.jar:/home/dean/.ivy2/cache/org.scala-sbt/interface/jars/interface-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/io/jars/io-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/control/jars/control-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/launcher-interface/jars/launcher-interface-1.0.0-M1.jar:/home/dean/.ivy2/cache/org.scala-sbt/completion/jars/completion-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/collections/jars/collections-0.13.11.jar:/home/dean/.ivy2/cache/jline/jline/jars/jline-2.13.jar:/home/dean/.ivy2/cache/org.fusesource.jansi/jansi/jars/jansi-1.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/api/jars/api-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/classfile/jars/classfile-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/logging/jars/logging-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/process/jars/process-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-integration/jars/compiler-integration-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/incremental-compiler/jars/incremental-compiler-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/relation/jars/relation-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compile/jars/compile-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/persist/jars/persist-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-tools.sbinary/sbinary_2.10/jars/sbinary_2.10-0.4.2.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-ivy-integration/jars/compiler-ivy-integration-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/ivy/jars/ivy-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/cross/jars/cross-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt.ivy/ivy/jars/ivy-2.3.0-sbt-2cc8d2761242b072cedb0a04cb39435c4fa24f9a.jar:/home/dean/.ivy2/cache/com.jcraft/jsch/jars/jsch-0.1.46.jar:/home/dean/.ivy2/cache/org.scala-sbt/serialization_2.10/jars/serialization_2.10-0.1.2.jar:/home/dean/.ivy2/cache/org.scala-lang.modules/scala-pickling_2.10/jars/scala-pickling_2.10-0.10.1.jar:/home/dean/.ivy2/cache/org.scalamacros/quasiquotes_2.10/jars/quasiquotes_2.10-2.0.1.jar:/home/dean/.ivy2/cache/org.json4s/json4s-core_2.10/jars/json4s-core_2.10-3.2.10.jar:/home/dean/.ivy2/cache/org.json4s/json4s-ast_2.10/jars/json4s-ast_2.10-3.2.10.jar:/home/dean/.ivy2/cache/com.thoughtworks.paranamer/paranamer/jars/paranamer-2.6.jar:/home/dean/.ivy2/cache/org.spire-math/jawn-parser_2.10/jars/jawn-parser_2.10-0.6.0.jar:/home/dean/.ivy2/cache/org.spire-math/json4s-support_2.10/jars/json4s-support_2.10-0.6.0.jar:/home/dean/.ivy2/cache/org.scala-sbt/run/jars/run-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/task-system/jars/task-system-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/tasks/jars/tasks-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/tracking/jars/tracking-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/cache/jars/cache-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/testing/jars/testing-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/test-agent/jars/test-agent-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/test-interface/jars/test-interface-1.0.jar:/home/dean/.ivy2/cache/org.scala-sbt/main-settings/jars/main-settings-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/apply-macro/jars/apply-macro-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/command/jars/command-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/logic/jars/logic-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-interface/jars/compiler-interface-0.13.11.jar 2 | -------------------------------------------------------------------------------- /project/target/streams/compile/internalDependencyClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /project/target/streams/compile/managedClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | /home/dean/.sbt/boot/scala-2.10.6/lib/scala-library.jar:/home/dean/.ivy2/cache/org.scala-sbt/sbt/jars/sbt-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/main/jars/main-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/actions/jars/actions-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/classpath/jars/classpath-0.13.11.jar:/home/dean/.sbt/boot/scala-2.10.6/lib/scala-compiler.jar:/home/dean/.sbt/boot/scala-2.10.6/lib/scala-reflect.jar:/home/dean/.ivy2/cache/org.scala-sbt/interface/jars/interface-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/io/jars/io-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/control/jars/control-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/launcher-interface/jars/launcher-interface-1.0.0-M1.jar:/home/dean/.ivy2/cache/org.scala-sbt/completion/jars/completion-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/collections/jars/collections-0.13.11.jar:/home/dean/.ivy2/cache/jline/jline/jars/jline-2.13.jar:/home/dean/.ivy2/cache/org.fusesource.jansi/jansi/jars/jansi-1.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/api/jars/api-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/classfile/jars/classfile-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/logging/jars/logging-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/process/jars/process-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-integration/jars/compiler-integration-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/incremental-compiler/jars/incremental-compiler-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/relation/jars/relation-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compile/jars/compile-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/persist/jars/persist-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-tools.sbinary/sbinary_2.10/jars/sbinary_2.10-0.4.2.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-ivy-integration/jars/compiler-ivy-integration-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/ivy/jars/ivy-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/cross/jars/cross-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt.ivy/ivy/jars/ivy-2.3.0-sbt-2cc8d2761242b072cedb0a04cb39435c4fa24f9a.jar:/home/dean/.ivy2/cache/com.jcraft/jsch/jars/jsch-0.1.46.jar:/home/dean/.ivy2/cache/org.scala-sbt/serialization_2.10/jars/serialization_2.10-0.1.2.jar:/home/dean/.ivy2/cache/org.scala-lang.modules/scala-pickling_2.10/jars/scala-pickling_2.10-0.10.1.jar:/home/dean/.ivy2/cache/org.scalamacros/quasiquotes_2.10/jars/quasiquotes_2.10-2.0.1.jar:/home/dean/.ivy2/cache/org.json4s/json4s-core_2.10/jars/json4s-core_2.10-3.2.10.jar:/home/dean/.ivy2/cache/org.json4s/json4s-ast_2.10/jars/json4s-ast_2.10-3.2.10.jar:/home/dean/.ivy2/cache/com.thoughtworks.paranamer/paranamer/jars/paranamer-2.6.jar:/home/dean/.ivy2/cache/org.spire-math/jawn-parser_2.10/jars/jawn-parser_2.10-0.6.0.jar:/home/dean/.ivy2/cache/org.spire-math/json4s-support_2.10/jars/json4s-support_2.10-0.6.0.jar:/home/dean/.ivy2/cache/org.scala-sbt/run/jars/run-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/task-system/jars/task-system-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/tasks/jars/tasks-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/tracking/jars/tracking-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/cache/jars/cache-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/testing/jars/testing-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/test-agent/jars/test-agent-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/test-interface/jars/test-interface-1.0.jar:/home/dean/.ivy2/cache/org.scala-sbt/main-settings/jars/main-settings-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/apply-macro/jars/apply-macro-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/command/jars/command-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/logic/jars/logic-0.13.11.jar:/home/dean/.ivy2/cache/org.scala-sbt/compiler-interface/jars/compiler-interface-0.13.11.jar 2 | -------------------------------------------------------------------------------- /project/target/streams/compile/unmanagedClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /project/target/streams/compile/unmanagedJars/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/dependencyClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | /mnt/c/ChiselProjects/FPGA_SWD/project/target/scala-2.10/sbt-0.13/classes 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/exportedProducts/$global/streams/export: -------------------------------------------------------------------------------- 1 | /mnt/c/ChiselProjects/FPGA_SWD/project/target/scala-2.10/sbt-0.13/classes 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/externalDependencyClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/fullClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | /mnt/c/ChiselProjects/FPGA_SWD/project/target/scala-2.10/sbt-0.13/classes 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/internalDependencyClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | /mnt/c/ChiselProjects/FPGA_SWD/project/target/scala-2.10/sbt-0.13/classes 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/managedClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/unmanagedClasspath/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /project/target/streams/runtime/unmanagedJars/$global/streams/export: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /src/main/scala/modules/BRAM.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.experimental._ // To enable experimental features 5 | import chisel3.util._ 6 | 7 | 8 | class SB_RAM40_4K extends BlackBox(Map("READ_MODE" -> 0, 9 | "WRITE_MODE" -> 0)) { 10 | 11 | val io = IO(new Bundle { 12 | val RDATA = Output(UInt(16.W)) 13 | val RADDR = Input(UInt(8.W)) 14 | val RCLK = Input(Clock()) 15 | val RCLKE = Input(Bool()) 16 | val RE = Input(Bool()) 17 | val WADDR = Input(UInt(8.W)) 18 | val WCLK = Input(Clock()) 19 | val WCLKE = Input(Bool()) 20 | val WDATA = Input(UInt(16.W)) 21 | val WE = Input(Bool()) 22 | val MASK = Input(UInt(16.W)) 23 | }) 24 | } 25 | 26 | class SB_RAM40_4K_sim extends Module { 27 | 28 | val io = IO(new Bundle { 29 | val RDATA = Output(UInt(16.W)) 30 | val RADDR = Input(UInt(8.W)) 31 | val RCLK = Input(Clock()) 32 | val RCLKE = Input(Bool()) 33 | val RE = Input(Bool()) 34 | val WADDR = Input(UInt(8.W)) 35 | val WCLK = Input(Clock()) 36 | val WCLKE = Input(Bool()) 37 | val WDATA = Input(UInt(16.W)) 38 | val WE = Input(Bool()) 39 | val MASK = Input(UInt(16.W)) 40 | }) 41 | 42 | val bram = Mem(256, UInt(16.W)) 43 | when (io.WE && io.WCLKE) { bram(io.WADDR) := io.WDATA } 44 | when (io.RE && io.RCLKE) { io.RDATA := bram(io.RADDR) } 45 | } -------------------------------------------------------------------------------- /src/main/scala/modules/DoubleBarrel.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chisel3.experimental._ // To enable experimental features 6 | 7 | class DoubleBarrel extends Module { 8 | val io = IO(new Bundle{ 9 | val ADDR_IN = Input(UInt(32.W)) 10 | val ADDR_SET = Input(Bool()) 11 | val ADDR_OUT = Output(UInt(32.W)) 12 | val DATA_READY = Input(Bool()) 13 | val DATA_IN = Input(UInt(32.W)) 14 | val DATA_OUT = Output(UInt(32.W)) 15 | val TRIGGER = Input(Bool()) 16 | val deqRdy = Output(Bool()) 17 | val dataVal = Output(Bool()) 18 | val EN = Input(Bool()) 19 | 20 | val A = Output(UInt(2.W)) 21 | }) 22 | 23 | val addr = RegInit(0.asUInt(32.W)) 24 | when(io.ADDR_SET) { addr := io.ADDR_IN } 25 | 26 | io.ADDR_OUT := addr 27 | 28 | val sStopped :: sAddr :: sData :: Nil = Enum(3) 29 | val state = RegInit(sStopped) 30 | 31 | val rdy = Module(new EdgeBuffer) //producer has available data and consumer is ready to read 32 | rdy.io.in := io.DATA_READY && io.TRIGGER && io.EN 33 | io.deqRdy := rdy.io.rising && state === sData 34 | 35 | io.dataVal := state != sStopped && ~rdy.io.rising //notify the consumer that data is valid 36 | 37 | val addrCnt = Module(new Counter(256)) 38 | addrCnt.io.inc := rdy.io.rising && state != sStopped 39 | addrCnt.io.amt := 1.U 40 | 41 | when(state === sStopped) { 42 | io.DATA_OUT := 0.U 43 | when(rdy.io.rising) { state := sAddr } 44 | } 45 | 46 | when(state === sAddr){ 47 | io.A := 1.U //TAR 48 | io.DATA_OUT := addr 49 | when(rdy.io.rising){ 50 | state := sData 51 | } 52 | } 53 | when(state === sData){ 54 | io.DATA_OUT := Cat(io.DATA_IN(7,0), Cat(io.DATA_IN(15,8), Cat(io.DATA_IN(23,16), io.DATA_IN(31,24)))) 55 | io.A := 3.U //DRW 56 | when(rdy.io.rising){ 57 | when(addrCnt.io.tot === 256.U){ state := sAddr } 58 | addr := addr + 4.U 59 | } 60 | } 61 | } -------------------------------------------------------------------------------- /src/main/scala/modules/FIFO.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | class Fifo(w: Int, n: Int) extends Module { 7 | val io = IO(new Bundle { 8 | val enqVal = Input(Bool()) 9 | val enqRdy = Output(Bool()) 10 | val deqVal = Output(Bool()) 11 | val deqRdy = Input(Bool()) 12 | val enqDat = Input(UInt(w.W)) 13 | val deqDat = Output(UInt(w.W)) 14 | }) 15 | val enqPtr = RegInit(0.asUInt(n.W)) 16 | val deqPtr = RegInit(0.asUInt(n.W)) 17 | val isFull = RegInit(false.B) 18 | val doEnq = io.enqRdy && io.enqVal 19 | val doDeq = io.deqRdy && io.deqVal 20 | val isEmpty = !isFull && (enqPtr === deqPtr) 21 | val deqPtrInc = deqPtr + 1.U 22 | val enqPtrInc = enqPtr + 1.U 23 | val isFullNext = Mux(doEnq && ~doDeq && (enqPtrInc === deqPtr), 24 | true.B, Mux(doDeq && isFull, false.B, 25 | isFull)) 26 | enqPtr := Mux(doEnq, enqPtrInc, enqPtr) 27 | deqPtr := Mux(doDeq, deqPtrInc, deqPtr) 28 | isFull := isFullNext 29 | 30 | //ram banks for the FIFO 31 | sys.props.get("testing") match { 32 | case Some(x) => 33 | val banks = Range(0, 2).map(_ => Module(new SB_RAM40_4K_sim)) 34 | for (k <- 0 until 2) { 35 | banks(k).io.RADDR := deqPtr 36 | banks(k).io.RCLK := this.clock 37 | banks(k).io.RCLKE := true.B 38 | banks(k).io.RE := true.B 39 | banks(k).io.WADDR := enqPtr 40 | banks(k).io.WCLK := this.clock 41 | banks(k).io.WCLKE := true.B 42 | banks(k).io.WE := doEnq 43 | banks(k).io.MASK := 0x0000.U 44 | } 45 | banks(0).io.WDATA := io.enqDat(31, 16) //high bank 46 | banks(1).io.WDATA := io.enqDat(15, 0) //low bank 47 | 48 | io.deqDat := Cat(banks(0).io.RDATA, banks(1).io.RDATA) 49 | 50 | case _ => 51 | val banks = Range(0, 2).map(_ => Module(new SB_RAM40_4K)) 52 | for (k <- 0 until 2) { 53 | banks(k).io.RADDR := deqPtr 54 | banks(k).io.RCLK := this.clock 55 | banks(k).io.RCLKE := true.B 56 | banks(k).io.RE := true.B 57 | banks(k).io.WADDR := enqPtr 58 | banks(k).io.WCLK := this.clock 59 | banks(k).io.WCLKE := true.B 60 | banks(k).io.WE := doEnq 61 | banks(k).io.MASK := 0x0000.U 62 | } 63 | banks(0).io.WDATA := io.enqDat(31, 16) //high bank 64 | banks(1).io.WDATA := io.enqDat(15, 0) //low bank 65 | 66 | io.deqDat := Cat(banks(0).io.RDATA, banks(1).io.RDATA) 67 | } 68 | 69 | io.enqRdy := !isFull 70 | io.deqVal := !isEmpty 71 | } -------------------------------------------------------------------------------- /src/main/scala/modules/Helpers.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.experimental._ // To enable experimental features 5 | import chisel3.util._ 6 | 7 | class EdgeBuffer extends Module { 8 | val io = IO(new Bundle { 9 | val in = Input(Bool()) 10 | val out = Output(Bool()) 11 | val rising = Output(Bool()) 12 | val falling = Output(Bool()) 13 | }) 14 | val r0 = RegNext(io.in) 15 | val r1 = RegNext(r0) 16 | val r2 = RegNext(r1) 17 | io.out := r1 18 | 19 | io.rising := (!r2 && r1) 20 | io.falling := (r2 && !r1) 21 | } 22 | 23 | object ShiftIn { 24 | def shift(w: Int, en: Bool, v: Bool): UInt = { 25 | val x = RegInit(0.U(w.W)) 26 | when (en) { x := Cat(x, v) } 27 | x 28 | } 29 | } 30 | 31 | object Counter { 32 | 33 | def wrapAround(n: UInt, max: UInt) = 34 | Mux(n > max, 0.U, n) 35 | 36 | def counter(max: UInt, en: Bool, amt: UInt = 1.U, rst: Bool = false.B): UInt = { 37 | val x = RegInit(0.U(max.getWidth.W)) 38 | when (en) { x := wrapAround(x + amt, max) } 39 | .elsewhen(rst) { x := 0.U } 40 | x 41 | } 42 | 43 | } 44 | 45 | class Counter(val w: Int) extends Module { 46 | val io = IO(new Bundle { 47 | val inc = Input(Bool()) 48 | val tot = Output(w.U) 49 | val amt = Input(w.U) 50 | val rst = Input(Bool()) 51 | }) 52 | 53 | io.tot := Counter.counter(w.U, io.inc, io.amt, io.rst) 54 | } 55 | 56 | class Timer(val w: Int) extends Module { 57 | val io = IO(new Bundle{ 58 | val period = Input(UInt(w.W)) 59 | val fire = Output(Bool()) 60 | val en = Input(Bool()) 61 | }) 62 | 63 | val cnt = Counter.counter(io.period, io.en, 1.U) 64 | io.fire := RegNext(cnt === io.period) 65 | } 66 | 67 | class SB_IO extends BlackBox(Map("PIN_TYPE" -> "6'b101001", 68 | "PULLUP" -> 0)) { 69 | 70 | val io = IO(new Bundle { 71 | val PACKAGE_PIN = Output(Bool()) 72 | val OUTPUT_ENABLE = Input(Bool()) 73 | val D_OUT_0 = Input(Bool()) 74 | val D_IN_0 = Output(Bool()) 75 | }) 76 | } 77 | 78 | //we need to declare the PLL as a black box since it's got a device-specific implementation 79 | class SB_PLL40_CORE extends BlackBox(Map("FEEDBACK_PATH" -> "SIMPLE", 80 | "PLLOUT_SELECT" -> "GENCLK", 81 | "DIVR" -> 0, 82 | "DIVF" -> 23, 83 | "DIVQ" -> 2, 84 | "FILTER_RANGE" -> 2)) { 85 | 86 | val io = IO(new Bundle { 87 | val LOCK = Output(Bool()) 88 | val RESETB = Input(Bool()) 89 | val BYPASS = Input(Bool()) 90 | val REFERENCECLK = Input(Clock()) 91 | val PLLOUTCORE = Output(Clock()) 92 | }) 93 | } 94 | 95 | class AddrReg extends Module { 96 | val io = IO(new Bundle { 97 | val en = Input(Bool()) 98 | val din = Input(UInt(24.W)) 99 | val dout = Output(UInt(24.W)) 100 | }) 101 | 102 | val x = RegInit(0.U(24.W)) 103 | when(io.en) { x := io.din } 104 | 105 | io.dout := x 106 | } 107 | 108 | class ClkDivReg extends Module { 109 | val io = IO(new Bundle { 110 | val en = Input(Bool()) 111 | val din = Input(UInt(4.W)) 112 | val dout = Output(UInt(4.W)) 113 | }) 114 | 115 | val x = RegInit(0.U(4.W)) 116 | when(io.en) { x := io.din } 117 | 118 | io.dout := x 119 | } 120 | 121 | class LengthReg extends Module { 122 | val io = IO(new Bundle { 123 | val en = Input(Bool()) 124 | val dec = Input(Bool()) 125 | val din = Input(UInt(24.W)) 126 | val dout = Output(UInt(24.W)) 127 | }) 128 | 129 | val x = RegInit(0.U(24.W)) 130 | when(io.en) { x := io.din } 131 | when(io.dec) { x := x - 1.U } 132 | 133 | io.dout := x 134 | } 135 | 136 | class StatusReg extends Module { 137 | val io = IO(new Bundle{ 138 | val en = Input(Bool()) 139 | val din = Input(Bool()) 140 | val dout = Output(UInt(2.W)) 141 | val done = Input(Bool()) 142 | val error = Input(Bool()) 143 | }) 144 | 145 | val x = RegInit(0.U) 146 | when(io.en) { x := io.din } 147 | 148 | val out = RegInit(0.U(2.W)) 149 | out := Cat(io.error, Cat(io.done, x)) 150 | 151 | io.dout := out 152 | } -------------------------------------------------------------------------------- /src/main/scala/modules/SPIDecode.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | 5 | class SPIDecode extends Module { 6 | val io = IO(new Bundle { 7 | val dataIn = Input(UInt(28.W)) 8 | val dataOut = Output(UInt(24.W)) 9 | val addr = Output(UInt(3.W)) 10 | val trigger = Input(Bool()) 11 | val wclk = Output(Bool()) 12 | }) 13 | val addr = RegInit(0.U(24.W)) 14 | 15 | io.addr := io.dataIn(26, 24) 16 | io.dataOut := io.dataIn(23, 0) 17 | 18 | io.wclk := RegNext(io.dataIn(27) && io.trigger) 19 | } -------------------------------------------------------------------------------- /src/main/scala/modules/SPIFastRead.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chisel3.experimental._ // To enable experimental features 6 | 7 | class SPIFastRead(val w: Int = 32, val dummyCycles: Int = 8, val clkDiv: Int = 2, val cmd: Int = 0x0B, val addrWidth: Int = 24) extends Module { 8 | val io = IO(new Bundle { 9 | val MOSI = Output(Bool()) 10 | val MISO = Input(Bool()) 11 | val SCK = Output(Bool()) 12 | val DATA_READY = Output(Bool()) 13 | val DATA = Output(UInt(w.W)) 14 | val ADDR = Input(UInt( addrWidth.W ) ) 15 | val EN = Input(Bool()) 16 | val enqRdy = Input(Bool()) 17 | 18 | //THESE PORTS ARE ONLY USED FOR SIMULATION 19 | val SCK_RISING = Output(Bool()) 20 | }) 21 | 22 | withReset(~io.EN){ 23 | val MISO_DATA = ShiftRegister(io.MISO, 1) 24 | 25 | val sSetup :: sRead :: Nil = Enum(2) 26 | val state = RegInit(sSetup) 27 | 28 | val SCKReg = RegInit(0.U) 29 | 30 | //generate SCK 31 | val cd = Module(new Counter(clkDiv)) 32 | cd.io.amt := 1.U 33 | cd.io.inc := io.enqRdy 34 | when(cd.io.tot === clkDiv.U){ SCKReg := ~SCKReg } 35 | 36 | val SCKr = Module(new EdgeBuffer) 37 | SCKr.io.in := SCKReg 38 | io.SCK_RISING := SCKr.io.rising //SIMULATION ONLY 39 | 40 | val startCnt = Module(new Counter(9 + addrWidth + dummyCycles)) 41 | startCnt.io.amt := 1.U 42 | startCnt.io.inc := SCKr.io.rising 43 | 44 | //bit counter for reading data 45 | val bitcnt = Module(new Counter(w - 1)) 46 | bitcnt.io.amt := 1.U 47 | val byte_received = RegNext(bitcnt.io.tot === (w - 1).U && SCKr.io.rising) 48 | 49 | //read data, set data ready flag when done 50 | io.DATA_READY := byte_received 51 | 52 | val mosi_out = RegInit(0.asUInt(addrWidth.W)) 53 | 54 | when(state === sSetup){ 55 | 56 | bitcnt.io.inc := 0.U 57 | 58 | //send the command 59 | when(startCnt.io.tot === 0.U){ mosi_out := Cat(cmd.U, 0.asUInt( ( addrWidth - 8).W ) ) } 60 | 61 | //clock out data on the falling edge 62 | when(SCKr.io.falling){ 63 | mosi_out := Cat(mosi_out(addrWidth - 2, 0), 0.U) 64 | 65 | //send the address 66 | when(startCnt.io.tot === 8.U){ mosi_out := io.ADDR } 67 | 68 | //send dummy cycles and then start reading data 69 | when(startCnt.io.tot === ( 8 + addrWidth + dummyCycles).U ){ state := sRead } 70 | 71 | } 72 | io.MOSI := mosi_out(addrWidth - 1) 73 | io.DATA := 0.U 74 | } 75 | 76 | when(state === sRead){ 77 | bitcnt.io.inc := SCKr.io.rising 78 | 79 | io.DATA := ShiftIn.shift(w, SCKr.io.rising, MISO_DATA) 80 | io.MOSI := 0.U 81 | } 82 | 83 | io.SCK := SCKr.io.out 84 | } 85 | } -------------------------------------------------------------------------------- /src/main/scala/modules/SPISlave.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chisel3.experimental._ // To enable experimental features 6 | 7 | class SPISlave(val w: Int, val outWidth: Int = 24) extends Module { 8 | val io = IO(new Bundle { 9 | val MOSI = Input(Bool()) 10 | val MISO = Output(Bool()) 11 | val SCK = Input(Bool()) 12 | val SSEL = Input(Bool()) 13 | val DATA_READY = Output(Bool()) 14 | val DATA = Output(UInt(w.W)) 15 | val READ_OUT = Input(UInt(outWidth.W)) 16 | }) 17 | 18 | val MOSI_DATA = ShiftRegister(io.MOSI, 1) 19 | val SCKr = Module(new EdgeBuffer) 20 | SCKr.io.in := io.SCK 21 | 22 | val SSELr = Module(new EdgeBuffer) 23 | SSELr.io.in := io.SSEL 24 | 25 | val byte_data_sent = RegInit(0.U(outWidth.W)) 26 | 27 | withReset(SSELr.io.out){ 28 | val bitcnt = Module(new Counter(w - 1)) 29 | bitcnt.io.inc := SCKr.io.rising 30 | bitcnt.io.amt := 1.U 31 | 32 | val byte_received = RegNext(bitcnt.io.tot === (w - 1).U && SCKr.io.rising) 33 | 34 | io.DATA_READY := byte_received 35 | } 36 | 37 | io.DATA := ShiftIn.shift(w, SCKr.io.rising && !SSELr.io.out, MOSI_DATA) 38 | 39 | //output data to the master on the rising edge of SCK 40 | when(SSELr.io.falling){ 41 | byte_data_sent := io.READ_OUT 42 | } 43 | .elsewhen(SCKr.io.rising && !SSELr.io.out){ 44 | byte_data_sent := Cat(byte_data_sent(outWidth - 2, 0), false.B) 45 | } 46 | io.MISO := byte_data_sent(outWidth - 1) 47 | 48 | } -------------------------------------------------------------------------------- /src/main/scala/modules/SWD.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chisel3.experimental._ // To enable experimental features 6 | 7 | class SWD extends Module { 8 | val io = IO(new Bundle{ 9 | val SWCLK = Output(Bool()) 10 | val DATA = Input(UInt(32.W)) 11 | val DATA_READY = Input(Bool()) 12 | val deqRdy = Output(Bool()) 13 | val CLKDIV = Input(UInt(4.W)) 14 | val APnDP = Input(Bool()) 15 | val A = Input(UInt(2.W)) 16 | 17 | val D_IN_0 = Input(Bool()) 18 | val D_OUT_0 = Output(Bool()) 19 | val OUTPUT_ENABLE = Output(Bool()) 20 | val ERROR = Output(Bool()) 21 | 22 | val EN = Input(Bool()) 23 | 24 | //THESE PORTS ARE ONLY USED FOR SIMULATION 25 | val SWCLK_RISING = Output(Bool()) 26 | }) 27 | 28 | val swdio_out_reg = RegInit(0.asUInt(32.W)) 29 | 30 | val swdio_response = RegInit(0.asUInt(3.W)) 31 | 32 | val sIdle :: sPacket :: sTrn1 :: sAck :: sTrn2 :: sData :: sError :: Nil = Enum(7) 33 | val state = RegInit(sIdle) 34 | 35 | //generate SWCLK 36 | val SWCLKReg = RegInit(0.U) 37 | val tmr = Module(new Timer(4)) 38 | tmr.io.period := io.CLKDIV 39 | tmr.io.en := 1.U 40 | 41 | val SWCLKr = Module(new EdgeBuffer) 42 | SWCLKr.io.in := SWCLKReg 43 | io.SWCLK := SWCLKr.io.out 44 | io.SWCLK_RISING := SWCLKr.io.rising //only used in simulation 45 | 46 | //SWCLK is disabled in ERROR state 47 | when(tmr.io.fire && state != sError && state != sIdle){ SWCLKReg := ~SWCLKReg } 48 | 49 | val deqRdyr = RegInit(true.B) 50 | io.deqRdy := (deqRdyr && io.EN) 51 | io.ERROR := state === sError 52 | 53 | val parity = RegInit(false.B) 54 | val outbit = RegInit(false.B) 55 | val outen = RegInit(false.B) 56 | val packet = Cat(Cat(Cat(2.U, 0.U), Cat(io.A, 0.U)), Cat(io.APnDP, 1.U)) 57 | 58 | val bitcnt = Module(new Counter(46 + 7)) 59 | bitcnt.io.inc := SWCLKr.io.rising 60 | bitcnt.io.amt := 1.U 61 | bitcnt.io.rst := 0.U 62 | 63 | when(state === sIdle){ 64 | when(io.DATA_READY && io.EN && tmr.io.fire){ state := sPacket } 65 | swdio_out_reg := packet 66 | SWCLKReg := 0.U 67 | parity := true.B 68 | swdio_response := 0.U 69 | outen := io.EN 70 | } 71 | when(state === sPacket){ 72 | bitcnt.io.rst := 0.U 73 | deqRdyr := false.B 74 | 75 | //clock out data on the falling edge 76 | when(SWCLKr.io.falling){ 77 | when(swdio_out_reg(0) === 1.U){ parity := ~parity } //count the 1s for the parity bit 78 | swdio_out_reg := Cat(0.U, swdio_out_reg(31, 1)) 79 | } 80 | when(bitcnt.io.tot === 5.U){ outbit := parity } 81 | .otherwise{ outbit := swdio_out_reg(0) } 82 | 83 | when(bitcnt.io.tot === 8.U){ 84 | state := sTrn1 85 | } 86 | 87 | //SWDIO output is enabled 88 | outen := 1.U 89 | } 90 | when(state === sTrn1){ 91 | //tristate SWDIO until data stage 92 | outen := 0.U 93 | when(bitcnt.io.tot === 9.U){ 94 | //go to ACK state 95 | state := sAck 96 | } 97 | } 98 | when(state === sAck){ 99 | when(bitcnt.io.tot === 12.U){ 100 | state := sTrn2 101 | 102 | swdio_out_reg := io.DATA 103 | } 104 | when(SWCLKr.io.rising){ 105 | swdio_response := Cat(io.D_IN_0, swdio_response(2, 1)) 106 | } 107 | //tristate SWDIO until data stage 108 | outen := 0.U 109 | } 110 | when(state === sTrn2){ 111 | 112 | when(bitcnt.io.tot === 13.U && SWCLKr.io.falling){ 113 | when(swdio_response === 1.U) { 114 | state := sData 115 | outbit := swdio_out_reg(0) 116 | parity := swdio_out_reg(0) 117 | swdio_out_reg := Cat(0.U, swdio_out_reg(31, 1)) 118 | } //transmit data if we have received an ACK 119 | .elsewhen(swdio_response === 2.U) { //WAIT 120 | outbit := 0.U 121 | bitcnt.io.rst := 1.U 122 | state := sIdle 123 | } 124 | .otherwise { state := sError } 125 | } 126 | } 127 | when(state === sData){ 128 | //reclaim SWDIO 129 | outen := 1.U 130 | 131 | //clock out data on the falling edge 132 | when(SWCLKr.io.falling){ 133 | when(swdio_out_reg(0) === 1.U){ parity := ~parity } //count the 1s for the parity bit 134 | swdio_out_reg := Cat(0.U, swdio_out_reg(31, 1)) 135 | 136 | when(bitcnt.io.tot === 45.U){ 137 | outbit := parity 138 | } 139 | .otherwise{ 140 | outbit := swdio_out_reg(0) 141 | } 142 | } 143 | 144 | when(bitcnt.io.tot === 0.U){ 145 | state := sIdle 146 | deqRdyr := true.B 147 | } 148 | } 149 | when(state === sError){ 150 | //TODO: do something when ACK is not received 151 | } 152 | 153 | io.D_OUT_0 := outbit 154 | io.OUTPUT_ENABLE := outen 155 | } -------------------------------------------------------------------------------- /src/main/scala/modules/SWDTop.scala: -------------------------------------------------------------------------------- 1 | package modules 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import chisel3.experimental._ // To enable experimental features 6 | 7 | class Top extends Module { 8 | val io = IO(new Bundle { 9 | val MOSI = Input(Bool()) 10 | val MISO = Output(Bool()) 11 | val SCK = Input(Bool()) 12 | val SSEL = Input(Bool()) 13 | 14 | val FLASH_MOSI = Output(Bool()) 15 | val FLASH_MISO = Input(Bool()) 16 | val FLASH_SCK = Output(Bool()) 17 | val FLASH_SSEL = Output(Bool()) 18 | 19 | val SWCLK = Output(Bool()) 20 | 21 | /************************************** 22 | * This sucks, but right now we may need to 23 | * change this port to inout in the generated verilog. 24 | * (depending on how smart your synthesis software is) 25 | * plz friends, add support. 26 | ****************************************/ 27 | val SWDIO = Output(Bool()) 28 | /**************************************/ 29 | 30 | //THESE PORTS ARE ONLY USED FOR SIMULATION 31 | val SPI_DATA = Input(UInt(32.W)) 32 | val SPI_DATA_READY = Input(Bool()) 33 | val SPI_READ_OUT = Output(UInt(24.W)) 34 | 35 | val OUTPUT_ENABLE = Output(Bool()) 36 | val D_OUT_0 = Output(Bool()) 37 | val D_IN_0 = Input(Bool()) 38 | 39 | val FAST_READ_DATA = Input(UInt(32.W)) 40 | val FAST_READ_DATA_READY = Output(Bool()) 41 | }) 42 | 43 | sys.props.get("testing") match { 44 | case Some(x) => 45 | //For top level simulation don't use PLL or spi slave 46 | 47 | //SPI command decoder 48 | val decoder = Module(new SPIDecode) 49 | decoder.io.dataIn := io.SPI_DATA 50 | decoder.io.trigger := io.SPI_DATA_READY 51 | 52 | //create the register map 53 | val status = Module(new StatusReg) 54 | status.io.din := decoder.io.dataOut(0) 55 | status.io.en := (decoder.io.addr === 1.U && decoder.io.wclk) 56 | 57 | val readAddr = Module(new AddrReg) 58 | readAddr.io.din := decoder.io.dataOut 59 | readAddr.io.en := (decoder.io.addr === 2.U && decoder.io.wclk) 60 | 61 | val length = Module(new LengthReg) 62 | length.io.din := decoder.io.dataOut 63 | length.io.en := (decoder.io.addr === 3.U && decoder.io.wclk) 64 | 65 | val ClkDiv = Module(new ClkDivReg) 66 | ClkDiv.io.din := decoder.io.dataOut 67 | ClkDiv.io.en := (decoder.io.addr === 4.U && decoder.io.wclk) 68 | 69 | val writeAddr = Module(new AddrReg) 70 | writeAddr.io.din := decoder.io.dataOut 71 | writeAddr.io.en := (decoder.io.addr === 5.U && decoder.io.wclk) 72 | 73 | when(decoder.io.addr === 0.U){ io.SPI_READ_OUT := 0x55.U } //hardware ID test code 74 | .elsewhen(decoder.io.addr === 1.U){ io.SPI_READ_OUT := status.io.dout } 75 | .elsewhen(decoder.io.addr === 2.U){ io.SPI_READ_OUT := readAddr.io.dout } 76 | .elsewhen(decoder.io.addr === 3.U){ io.SPI_READ_OUT := length.io.dout } 77 | .elsewhen(decoder.io.addr === 4.U){ io.SPI_READ_OUT := ClkDiv.io.dout } 78 | .elsewhen(decoder.io.addr === 5.U){ io.SPI_READ_OUT := writeAddr.io.dout } 79 | .otherwise{ io.SPI_READ_OUT := 0.U } 80 | 81 | io.FLASH_SSEL := ~status.io.dout(0) 82 | 83 | val ENr = Module(new EdgeBuffer) 84 | ENr.io.in := status.io.dout(0) 85 | 86 | val spiMaster = Module(new SPIFastRead()) 87 | length.io.dec := spiMaster.io.DATA_READY //decrement length left to read 88 | spiMaster.io.ADDR := readAddr.io.dout 89 | io.FLASH_MOSI := spiMaster.io.MOSI 90 | spiMaster.io.MISO := io.FLASH_MISO 91 | io.FLASH_SCK := spiMaster.io.SCK 92 | 93 | 94 | val fifo = Module(new Fifo(32, 3)) //very small fifo for simulation 95 | fifo.io.enqDat := io.FAST_READ_DATA //fake the input data 96 | fifo.io.enqVal := spiMaster.io.DATA_READY && ENr.io.out 97 | 98 | //for simulation 99 | io.FAST_READ_DATA_READY := spiMaster.io.DATA_READY 100 | 101 | //stop reading when we hit the specified number of blocks 102 | spiMaster.io.EN := (length.io.dout != 0.U && ENr.io.out) 103 | spiMaster.io.enqRdy := fifo.io.enqRdy 104 | 105 | val db = Module(new DoubleBarrel()) 106 | db.io.EN := ENr.io.out 107 | db.io.ADDR_IN := writeAddr.io.dout 108 | db.io.ADDR_SET := ENr.io.rising 109 | db.io.DATA_READY := fifo.io.deqVal 110 | db.io.DATA_IN := fifo.io.deqDat 111 | 112 | fifo.io.deqRdy := db.io.deqRdy 113 | 114 | val swd = Module(new SWD()) 115 | io.SWCLK := swd.io.SWCLK 116 | swd.io.CLKDIV := ClkDiv.io.dout 117 | swd.io.DATA_READY := (db.io.dataVal && fifo.io.deqVal) 118 | swd.io.DATA := db.io.DATA_OUT 119 | swd.io.APnDP := 1.U 120 | swd.io.A := db.io.A 121 | swd.io.EN := ENr.io.out 122 | 123 | db.io.TRIGGER := swd.io.deqRdy 124 | 125 | io.OUTPUT_ENABLE := swd.io.OUTPUT_ENABLE 126 | io.D_OUT_0 := swd.io.D_OUT_0 127 | swd.io.D_IN_0 := io.D_IN_0 128 | 129 | //set done 130 | status.io.done := (length.io.dout === 0.U && ~fifo.io.deqVal) 131 | status.io.error := swd.io.ERROR 132 | 133 | case _ => 134 | //instantiate the PLL. We need to explicitly define the clock and reset 135 | val pll = Module(new SB_PLL40_CORE) 136 | pll.io.RESETB := 0.U 137 | pll.io.REFERENCECLK := this.clock 138 | 139 | withClock(pll.io.PLLOUTCORE){ 140 | //create the SPI interface 141 | val spi = Module(new SPISlave(32)) 142 | spi.io.MOSI := io.MOSI 143 | io.MISO := spi.io.MISO 144 | spi.io.SCK := io.SCK 145 | spi.io.SSEL := io.SSEL 146 | 147 | //SPI command decoder 148 | val decoder = Module(new SPIDecode) 149 | decoder.io.dataIn := spi.io.DATA 150 | decoder.io.trigger := spi.io.DATA_READY 151 | 152 | //create the register map 153 | val status = Module(new StatusReg) 154 | status.io.din := decoder.io.dataOut(0) 155 | status.io.en := (decoder.io.addr === 1.U && decoder.io.wclk) 156 | 157 | val readAddr = Module(new AddrReg) 158 | readAddr.io.din := decoder.io.dataOut 159 | readAddr.io.en := (decoder.io.addr === 2.U && decoder.io.wclk) 160 | 161 | val length = Module(new LengthReg) 162 | length.io.din := decoder.io.dataOut 163 | length.io.en := (decoder.io.addr === 3.U && decoder.io.wclk) 164 | 165 | val ClkDiv = Module(new ClkDivReg) 166 | ClkDiv.io.din := decoder.io.dataOut 167 | ClkDiv.io.en := (decoder.io.addr === 4.U && decoder.io.wclk) 168 | 169 | val writeAddr = Module(new AddrReg) 170 | writeAddr.io.din := decoder.io.dataOut 171 | writeAddr.io.en := (decoder.io.addr === 5.U && decoder.io.wclk) 172 | 173 | when(decoder.io.addr === 0.U){ spi.io.READ_OUT := 0x55.U } //hardware ID test code 174 | .elsewhen(decoder.io.addr === 1.U){ spi.io.READ_OUT := status.io.dout } 175 | .elsewhen(decoder.io.addr === 2.U){ spi.io.READ_OUT := readAddr.io.dout } 176 | .elsewhen(decoder.io.addr === 3.U){ spi.io.READ_OUT := length.io.dout } 177 | .elsewhen(decoder.io.addr === 4.U){ spi.io.READ_OUT := ClkDiv.io.dout } 178 | .elsewhen(decoder.io.addr === 5.U){ spi.io.READ_OUT := writeAddr.io.dout } 179 | .otherwise{ spi.io.READ_OUT := 0.U } 180 | 181 | io.FLASH_SSEL := ~status.io.dout(0) 182 | 183 | val ENr = Module(new EdgeBuffer) 184 | ENr.io.in := status.io.dout(0) 185 | 186 | val spiMaster = Module(new SPIFastRead()) 187 | length.io.dec := spiMaster.io.DATA_READY //decrement length left to read 188 | spiMaster.io.ADDR := readAddr.io.dout 189 | io.FLASH_MOSI := spiMaster.io.MOSI 190 | spiMaster.io.MISO := io.FLASH_MISO 191 | io.FLASH_SCK := spiMaster.io.SCK 192 | 193 | 194 | val fifo = Module(new Fifo(32, 8)) 195 | fifo.io.enqDat := spiMaster.io.DATA 196 | fifo.io.enqVal := spiMaster.io.DATA_READY && ENr.io.out 197 | 198 | //stop reading when we hit the specified number of blocks or when the FIFO is full 199 | spiMaster.io.EN := (length.io.dout != 0.U && ENr.io.out) 200 | spiMaster.io.enqRdy := fifo.io.enqRdy 201 | 202 | val db = Module(new DoubleBarrel()) 203 | db.io.EN := ENr.io.out 204 | db.io.ADDR_IN := writeAddr.io.dout 205 | db.io.ADDR_SET := ENr.io.rising 206 | db.io.DATA_READY := fifo.io.deqVal 207 | db.io.DATA_IN := fifo.io.deqDat 208 | 209 | fifo.io.deqRdy := db.io.deqRdy 210 | 211 | val swd = Module(new SWD()) 212 | swd.io.CLKDIV := ClkDiv.io.dout 213 | swd.io.DATA_READY := (db.io.dataVal && fifo.io.deqVal) 214 | swd.io.DATA := db.io.DATA_OUT 215 | swd.io.APnDP := 1.U 216 | swd.io.A := db.io.A 217 | swd.io.EN := ENr.io.out 218 | 219 | db.io.TRIGGER := swd.io.deqRdy 220 | 221 | val swclk = Module(new SB_IO) 222 | io.SWCLK := swclk.io.PACKAGE_PIN 223 | swclk.io.OUTPUT_ENABLE := ENr.io.out 224 | swclk.io.D_OUT_0 := swd.io.SWCLK 225 | 226 | val swdio = Module(new SB_IO) 227 | io.SWDIO := swdio.io.PACKAGE_PIN 228 | swdio.io.OUTPUT_ENABLE := swd.io.OUTPUT_ENABLE 229 | swdio.io.D_OUT_0 := swd.io.D_OUT_0 230 | swd.io.D_IN_0 := swdio.io.D_IN_0 231 | 232 | //set done 233 | status.io.done := (length.io.dout === 0.U && ~fifo.io.deqVal) 234 | status.io.error := swd.io.ERROR 235 | } 236 | } 237 | } 238 | 239 | object TopDriver extends App{ 240 | chisel3.Driver.execute(args, () => new Top()) 241 | } -------------------------------------------------------------------------------- /src/test/scala/modules/CounterUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.Counter 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class CounterUnitTester(c: Counter) extends PeekPokeTester(c) { 9 | val maxInt = 16 10 | var curCnt = 0 11 | 12 | def intWrapAround(n: Int, max: Int) = 13 | if(n > max) 0 else n 14 | 15 | poke(c.io.inc, 0) 16 | poke(c.io.amt, 0) 17 | 18 | // let it spin for a bit 19 | for (i <- 0 until 5) { 20 | step(1) 21 | } 22 | 23 | for (i <- 0 until 10) { 24 | val inc = rnd.nextBoolean() 25 | val amt = rnd.nextInt(maxInt) 26 | poke(c.io.inc, if (inc) 1 else 0) 27 | poke(c.io.amt, amt) 28 | step(1) 29 | curCnt = if(inc) intWrapAround(curCnt + amt, 255) else curCnt 30 | expect(c.io.tot, curCnt) 31 | } 32 | } 33 | 34 | class CounterTester extends ChiselFlatSpec with Matchers { 35 | private val backendNames = Array[String]("firrtl", "verilator") 36 | for ( backendName <- backendNames ) { 37 | "Counter" should s"count to passed value (with $backendName)" in { 38 | Driver(() => new Counter(255), backendName) { 39 | c => new CounterUnitTester(c) 40 | } should be (true) 41 | } 42 | } 43 | } -------------------------------------------------------------------------------- /src/test/scala/modules/DoubleBarrelUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.DoubleBarrel 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class DoubleBarrelUnitTester(c: DoubleBarrel) extends PeekPokeTester(c) { 9 | var r = Random 10 | //var addrStart = r.nextInt(1 << 24) 11 | var addrStart = 1024 12 | poke(c.io.ADDR_SET, 0) 13 | poke(c.io.DATA_READY, 0) 14 | poke(c.io.ADDR_IN, addrStart) 15 | poke(c.io.DATA_IN, 0) 16 | poke(c.io.TRIGGER, 0) 17 | 18 | step(5) //spin 19 | expect(c.io.ADDR_OUT, 0) 20 | 21 | poke(c.io.ADDR_SET, 1) 22 | step(1) 23 | poke(c.io.ADDR_SET, 0) 24 | step(1) 25 | expect(c.io.ADDR_OUT, addrStart) 26 | 27 | step(5) 28 | 29 | poke(c.io.DATA_READY, 1) 30 | 31 | step(5) 32 | 33 | var i = 0 34 | 35 | var dat = 0 36 | 37 | for(k <- 0 until 1035){ 38 | if(peek(c.io.dataVal) == 1){ 39 | if(i % 258 == 0 && i > 1){ 40 | expect(c.io.DATA_OUT, addrStart + 1024) 41 | expect(c.io.A, 1) 42 | } 43 | else if(i == 1){ 44 | expect(c.io.DATA_OUT, addrStart) 45 | expect(c.io.A, 1) 46 | } 47 | else { 48 | expect(c.io.DATA_OUT, dat) 49 | expect(c.io.A, 3) 50 | } 51 | } 52 | 53 | if(peek(c.io.deqRdy) == 1){ 54 | dat = r.nextInt(1 << 25) 55 | poke(c.io.DATA_IN, dat) 56 | } 57 | 58 | if(k % 4 == 0){ 59 | poke(c.io.TRIGGER, 1) 60 | i = i + 1 61 | } 62 | else{ 63 | poke(c.io.TRIGGER, 0) 64 | } 65 | 66 | step(1) 67 | } 68 | } 69 | 70 | class DoubleBarrelTester extends ChiselFlatSpec with Matchers { 71 | private val backendNames = Array[String]("firrtl", "verilator") 72 | for ( backendName <- backendNames ) { 73 | "DoubleBarrel" should s"load address then data into DATA_OUT (with $backendName)" in { 74 | Driver(() => new DoubleBarrel(), backendName) { 75 | c => new DoubleBarrelUnitTester(c) 76 | } should be (true) 77 | } 78 | } 79 | } -------------------------------------------------------------------------------- /src/test/scala/modules/EdgeBufferUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.EdgeBuffer 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class EdgeBufferUnitTester(c: EdgeBuffer) extends PeekPokeTester(c) { 9 | 10 | val r = Random 11 | //val spin: Int = r.nextInt(Integer.MAX_VALUE) 12 | 13 | poke(c.io.in, 0) 14 | 15 | // let it spin for a bit 16 | for (i <- 0 until 10) { 17 | step(1) 18 | } 19 | 20 | expect(c.io.rising, 0) 21 | expect(c.io.falling, 0) 22 | expect(c.io.out, 0) 23 | 24 | poke(c.io.in, 1) 25 | 26 | expect(c.io.rising, 0) 27 | expect(c.io.falling, 0) 28 | expect(c.io.out, 0) 29 | 30 | step(2) 31 | expect(c.io.rising, 1) 32 | expect(c.io.falling, 0) 33 | expect(c.io.out, 1) 34 | 35 | // let it spin for a bit 36 | for (i <- 0 until 12) { 37 | step(1) 38 | } 39 | expect(c.io.rising, 0) 40 | expect(c.io.falling, 0) 41 | expect(c.io.out, 1) 42 | 43 | poke(c.io.in, 0) 44 | step(2) 45 | 46 | expect(c.io.rising, 0) 47 | expect(c.io.falling, 1) 48 | expect(c.io.out, 0) 49 | 50 | step(1) 51 | 52 | expect(c.io.rising, 0) 53 | expect(c.io.falling, 0) 54 | expect(c.io.out, 0) 55 | } 56 | 57 | class EdgeBufferTester extends ChiselFlatSpec with Matchers { 58 | private val backendNames = Array[String]("firrtl", "verilator") 59 | for ( backendName <- backendNames ) { 60 | "EdgeBuffer" should s"detect rising and falling edges (with $backendName)" in { 61 | Driver(() => new EdgeBuffer, backendName) { 62 | c => new EdgeBufferUnitTester(c) 63 | } should be (true) 64 | } 65 | } 66 | } -------------------------------------------------------------------------------- /src/test/scala/modules/FifoUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.Fifo 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class FifoUnitTester(c: Fifo) extends PeekPokeTester(c) { 9 | val r = Random 10 | 11 | var data = Seq.fill(257)(r.nextInt(1 << 24 - 1)) 12 | poke(c.io.enqVal, 0) 13 | poke(c.io.deqRdy, 0) 14 | step(5) //spin 15 | 16 | for(k <- 0 until 257){ 17 | if(k < 256){ expect(c.io.enqRdy, 1) } 18 | else { expect(c.io.enqRdy, 0) } 19 | 20 | poke(c.io.enqDat, data(k)) 21 | step(1) 22 | poke(c.io.enqVal, 1) 23 | step(1) 24 | poke(c.io.enqVal, 0) 25 | } 26 | 27 | for(k <- 0 until 257){ 28 | if(k < 256) { 29 | expect(c.io.deqDat, data(k)) 30 | expect(c.io.deqVal, 1) 31 | } 32 | else { 33 | expect(c.io.deqVal, 0) 34 | } 35 | step(1) 36 | poke(c.io.deqRdy, 1) 37 | step(1) 38 | poke(c.io.deqRdy, 0) 39 | } 40 | 41 | step(5); 42 | } 43 | 44 | class FifoTester extends ChiselFlatSpec with Matchers { 45 | private val backendNames = Array[String]("firrtl", "verilator") 46 | for ( backendName <- backendNames ) { 47 | "Fifo" should s"implement a FIFO structure (with $backendName)" in { 48 | Driver(() => new Fifo(32, 8), backendName) { 49 | c => new FifoUnitTester(c) 50 | } should be (true) 51 | } 52 | } 53 | } -------------------------------------------------------------------------------- /src/test/scala/modules/SPIDecodeUnitTest.scala: -------------------------------------------------------------------------------- 1 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 2 | import modules.SPIDecode 3 | import org.scalatest.Matchers 4 | import scala.util.Random 5 | 6 | class SPIDecodeTest(c: SPIDecode) extends PeekPokeTester(c) { 7 | val r = Random 8 | poke(c.io.trigger, 0) 9 | poke(c.io.dataIn, 0) 10 | step(10) 11 | 12 | for(n <- 1 to 10) { 13 | val datain = r.nextInt(1 << 28) 14 | poke(c.io.dataIn, datain) 15 | 16 | expect(c.io.addr, (datain >> 24) & 0x7) 17 | expect(c.io.dataOut, datain & 0xFFFFFF) 18 | 19 | poke(c.io.trigger, 1) 20 | step(1) 21 | poke(c.io.trigger, 0) 22 | 23 | if( ((datain >> 27) & 0x01) == 1){ 24 | expect(c.io.wclk, 1) 25 | } 26 | else { expect(c.io.wclk, 0) } 27 | 28 | step(1) 29 | 30 | } 31 | } 32 | 33 | class SPIDecodeTester extends ChiselFlatSpec { 34 | private val backendNames = Array[String]("firrtl", "verilator") 35 | for ( backendName <- backendNames ) { 36 | "SPIDecode" should s"receive SPI data (with $backendName)" in { 37 | Driver(() => new SPIDecode, backendName) { 38 | c => new SPIDecodeTest(c) 39 | } should be (true) 40 | } 41 | } 42 | } -------------------------------------------------------------------------------- /src/test/scala/modules/SPIFastReadUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.SPIFastRead 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class SPIFastReadUnitTester(c: SPIFastRead) extends PeekPokeTester(c) { 9 | 10 | val r = Random 11 | val addr = r.nextInt(1<<24 - 1) 12 | val data = r.nextInt(1<<24 - 1) //data that will be sent 13 | var miso = data 14 | poke(c.io.EN, 0) 15 | poke(c.io.ADDR, addr) 16 | 17 | step(4) 18 | poke(c.io.EN, 1) 19 | 20 | var i = 0 21 | var received = 0 22 | for(k <- 0 until 500){ 23 | if(peek(c.io.SCK_RISING) == 1){ 24 | //shift in data on the rising edge of SCK 25 | received = (received << 1) | (if (peek(c.io.MOSI) ==1 ) 1 else 0) 26 | i = i + 1 27 | 28 | //first byte should be fast read command 29 | if(i == 8){ expect(received == 0x0B, s"expected cmd 11, received $received") } 30 | 31 | //next 24 bytes should be the address 32 | if(i == 32){ 33 | val a = (received & 0xFFFFFF) 34 | expect(a == addr, s"expected addr $addr, got $a") 35 | } 36 | 37 | //after 8 cycles the flash chip will start shifting out data 38 | if(i > (32 + 8)){ 39 | val miso_bit = ((miso & 0x80000000) >> 31) & 0x01 40 | poke(c.io.MISO, miso_bit) 41 | miso = (miso << 1) 42 | } 43 | 44 | //module asserts DATA_READY when it's received 32 bytes 45 | if(peek(c.io.DATA_READY) == 1){ 46 | expect(c.io.DATA, data) 47 | } 48 | } 49 | 50 | step(1) 51 | } 52 | } 53 | 54 | class SPIFastReadTester extends ChiselFlatSpec with Matchers { 55 | private val backendNames = Array[String]("firrtl", "verilator") 56 | for ( backendName <- backendNames ) { 57 | "SPIFastRead" should s"fast read out from an SPI flash chip (with $backendName)" in { 58 | Driver(() => new SPIFastRead(), backendName) { 59 | c => new SPIFastReadUnitTester(c) 60 | } should be (true) 61 | } 62 | } 63 | } -------------------------------------------------------------------------------- /src/test/scala/modules/SPISlaveUnitTest.scala: -------------------------------------------------------------------------------- 1 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 2 | import modules.SPISlave 3 | import org.scalatest.Matchers 4 | import scala.util.Random 5 | 6 | class SPISlaveTest(c: SPISlave) extends PeekPokeTester(c) { 7 | val r = Random 8 | poke(c.io.SSEL, 1) 9 | poke(c.io.SCK, 0) 10 | 11 | step(10) 12 | 13 | for(n <- 1 to 100) { 14 | val dataIn = r.nextInt(Integer.MAX_VALUE); 15 | val readOut = r.nextInt(1 << 16) 16 | 17 | var mosi = dataIn 18 | 19 | poke(c.io.READ_OUT, readOut) 20 | poke(c.io.SSEL, 0) 21 | 22 | //spin 23 | step(10) 24 | 25 | for(i <- 1 to c.w) { 26 | val mosi_bit = ((mosi & 0x80000000) >> 31) & 0x01 27 | poke(c.io.MOSI, mosi_bit) 28 | 29 | step(2) 30 | poke(c.io.SCK, 1) 31 | step(4) 32 | poke(c.io.SCK, 0) 33 | mosi = mosi << 1 34 | step(3) 35 | } 36 | 37 | //spin 38 | step(5) 39 | expect(c.io.DATA, dataIn) 40 | 41 | poke(c.io.SSEL, 1) 42 | step(5) 43 | } 44 | } 45 | 46 | class SPISlaveTester extends ChiselFlatSpec { 47 | private val backendNames = Array[String]("firrtl", "verilator") 48 | for ( backendName <- backendNames ) { 49 | "SPISlave" should s"receive SPI data (with $backendName)" in { 50 | Driver(() => new SPISlave(32, 16), backendName) { 51 | c => new SPISlaveTest(c) 52 | } should be (true) 53 | } 54 | } 55 | } -------------------------------------------------------------------------------- /src/test/scala/modules/SWDUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.SWD 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class SWDUnitTester(c: SWD) extends PeekPokeTester(c) { 9 | var r = Random 10 | poke(c.io.APnDP, 1) 11 | poke(c.io.A, 2) 12 | poke(c.io.CLKDIV, 0) 13 | poke(c.io.DATA_READY, 0) 14 | poke(c.io.EN, 0) 15 | 16 | step(10) 17 | poke(c.io.DATA_READY, 1) 18 | poke(c.io.EN, 1) 19 | poke(c.io.D_IN_0, 0) 20 | 21 | val data = r.nextInt(1 << 24) 22 | poke(c.io.DATA, data) 23 | 24 | var received = 0 25 | var bitcount = 0 26 | var parity = false 27 | 28 | for(k <- 0 until 120){ 29 | if(peek(c.io.SWCLK_RISING) == 1){ 30 | if(bitcount < 13){ 31 | received = received | ( (if ( peek(c.io.D_OUT_0) == 1 ) 1 else 0) << bitcount ) 32 | if(peek(c.io.D_OUT_0) == 1){ parity = !parity } 33 | if(bitcount == (13 + 32) ){ 34 | //check parity bit 35 | expect(c.io.D_OUT_0, parity) 36 | } 37 | } 38 | else{ 39 | received = received | ( (if ( peek(c.io.D_OUT_0) == 1 ) 1 else 0) << (bitcount - 13) ) 40 | } 41 | bitcount = bitcount + 1 42 | 43 | // 10 0 10 011 44 | if(bitcount == 8){ 45 | expect(received == 0x93, s"packet value expected 0xB1 received: $received") 46 | } 47 | 48 | poke(c.io.D_IN_0, if (bitcount == 10) 1 else 0) 49 | 50 | if(bitcount == 13) { received = 0 } 51 | 52 | if(bitcount == (13 + 32) ){ 53 | expect(received == data, s"data value expected $data received: $received") 54 | received = 0 55 | } 56 | 57 | } 58 | 59 | step(1) 60 | } 61 | } 62 | 63 | class SWDTester extends ChiselFlatSpec with Matchers { 64 | private val backendNames = Array[String]("firrtl", "verilator") 65 | for ( backendName <- backendNames ) { 66 | "SWD" should s"write data over SWD protocol (with $backendName)" in { 67 | Driver(() => new SWD(), backendName) { 68 | c => new SWDUnitTester(c) 69 | } should be (true) 70 | } 71 | } 72 | } -------------------------------------------------------------------------------- /src/test/scala/modules/TimerUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.Timer 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class TimerUnitTester(c: Timer) extends PeekPokeTester(c) { 9 | 10 | poke(c.io.period, 0) 11 | poke(c.io.en, 1) 12 | 13 | // let it spin for a bit 14 | step(5) 15 | 16 | for (i <- 0 until 10) { 17 | val period = rnd.nextInt((1 << 4) - 1) 18 | poke(c.io.period, period) 19 | for(k <- 0 until (period + 1)){ 20 | step(1) 21 | if(k == period){ expect(c.io.fire, 1) } 22 | else { expect(c.io.fire, 0) } 23 | } 24 | } 25 | } 26 | 27 | class TimerTester extends ChiselFlatSpec with Matchers { 28 | private val backendNames = Array[String]("firrtl", "verilator") 29 | for ( backendName <- backendNames ) { 30 | "Timer" should s"count to passed value (with $backendName)" in { 31 | Driver(() => new Timer(4), backendName) { 32 | c => new TimerUnitTester(c) 33 | } should be (true) 34 | } 35 | } 36 | } -------------------------------------------------------------------------------- /src/test/scala/modules/TopUnitTest.scala: -------------------------------------------------------------------------------- 1 | package modules.test 2 | 3 | import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} 4 | import modules.Top 5 | import org.scalatest.Matchers 6 | import scala.util.Random 7 | 8 | class TopUnitTester(c: Top) extends PeekPokeTester(c) { 9 | val r = Random 10 | 11 | def writeReg(reg : Int, value : Int){ 12 | poke(c.io.SPI_DATA, ( (1 << 27) | (reg << 24) | value) ) 13 | poke(c.io.SPI_DATA_READY, 1) 14 | step(1) 15 | poke(c.io.SPI_DATA_READY, 0) 16 | step(1) 17 | } 18 | 19 | poke(c.io.SPI_DATA_READY, 0) 20 | poke(c.io.SPI_DATA, 0) 21 | poke(c.io.D_IN_0, 0) 22 | poke(c.io.FAST_READ_DATA, 0) 23 | 24 | step(3) //spin 25 | 26 | writeReg(1, 0) 27 | writeReg(2, 3) //start reading at address 3 28 | writeReg(3, 8) //write 8 blocks 29 | writeReg(4, 2) //clkdiv 2 30 | writeReg(1, 1) 31 | 32 | var bitcnt = 0 33 | var swclk_state = false 34 | var txn_started = false 35 | 36 | var spi_data = 0 37 | 38 | for(k <- 0 until 4000){ 39 | //test for start condition 40 | if(peek(c.io.SWCLK) == 1 && peek(c.io.D_OUT_0) == 1){ txn_started = true } 41 | 42 | //increment bitcount when we get a rising edge 43 | if(peek(c.io.SWCLK) == 1 && swclk_state == false && txn_started == true){ 44 | bitcnt = bitcnt + 1 45 | } 46 | swclk_state = (if (peek(c.io.SWCLK) == 1) true else false) 47 | 48 | //send ack when we get to the turnaround 49 | poke(c.io.D_IN_0, if (bitcnt == 10) 1 else 0) 50 | 51 | //check for start condition 52 | if( bitcnt > 46 ){ bitcnt = 0; txn_started = false; } 53 | 54 | //do SPI flash stuff 55 | if(peek(c.io.FAST_READ_DATA_READY) == 1){ 56 | spi_data = spi_data + 1 57 | poke(c.io.FAST_READ_DATA, spi_data) 58 | } 59 | 60 | step(1) 61 | } 62 | } 63 | 64 | class TopTester extends ChiselFlatSpec with Matchers { 65 | private val backendNames = Array[String]("firrtl", "verilator") 66 | for ( backendName <- backendNames ) { 67 | "Top" should s"do all the stuff the circuit does (with $backendName)" in { 68 | Driver(() => new Top, backendName) { 69 | c => new TopUnitTester(c) 70 | } should be (true) 71 | } 72 | } 73 | } --------------------------------------------------------------------------------