├── Divider.v ├── MP3.v ├── README.md ├── TRACK_CONTROL.v ├── VGA.v ├── VGA_TOP.v ├── display7.v ├── keyboard.v ├── track0.COE ├── track1.COE ├── track2.COE ├── track3.COE ├── track4.COE ├── track_testbench.v └── vga_testbench.v /Divider.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/Divider.v -------------------------------------------------------------------------------- /MP3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/MP3.v -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/README.md -------------------------------------------------------------------------------- /TRACK_CONTROL.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/TRACK_CONTROL.v -------------------------------------------------------------------------------- /VGA.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/VGA.v -------------------------------------------------------------------------------- /VGA_TOP.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/VGA_TOP.v -------------------------------------------------------------------------------- /display7.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/display7.v -------------------------------------------------------------------------------- /keyboard.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/keyboard.v -------------------------------------------------------------------------------- /track0.COE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/track0.COE -------------------------------------------------------------------------------- /track1.COE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/track1.COE -------------------------------------------------------------------------------- /track2.COE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/track2.COE -------------------------------------------------------------------------------- /track3.COE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/track3.COE -------------------------------------------------------------------------------- /track4.COE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/track4.COE -------------------------------------------------------------------------------- /track_testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/track_testbench.v -------------------------------------------------------------------------------- /vga_testbench.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/def-saizi-baka/Digital_Logic_FPGA_final_hw/HEAD/vga_testbench.v --------------------------------------------------------------------------------