├── .clang-format ├── .gitignore ├── .vscode ├── c_cpp_properties.json ├── extensions.json ├── launch.json └── tasks.json ├── CMakeLists.txt ├── CMakePresets.json ├── Core ├── Inc │ ├── fifo_queue.h │ ├── iferr.h │ ├── instrument_trigger.h │ ├── onboard_user_button.h │ ├── os.h │ ├── schedl_timer.h │ ├── stm32f3xx_hal_conf.h │ ├── stm32f3xx_hal_msp.h │ ├── stm32f3xx_it.h │ └── user_tasks.h ├── Src │ ├── fifo_queue.c │ ├── main.c │ ├── onboard_user_button.c │ ├── os.c │ ├── os_asm.s │ ├── schedl_timer.c │ ├── stm32f3xx_hal_msp.c │ ├── stm32f3xx_it.c │ ├── syscalls.c │ ├── sysmem.c │ ├── system_stm32f3xx.c │ └── user_tasks.c └── Startup │ └── startup_stm32f303vctx.s ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F3xx │ │ │ ├── Include │ │ │ ├── stm32f303xc.h │ │ │ ├── stm32f3xx.h │ │ │ └── system_stm32f3xx.h │ │ │ └── License.md │ ├── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h │ └── LICENSE.txt └── STM32F3xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f3xx_hal.h │ ├── stm32f3xx_hal_cortex.h │ ├── stm32f3xx_hal_def.h │ ├── stm32f3xx_hal_dma.h │ ├── stm32f3xx_hal_dma_ex.h │ ├── stm32f3xx_hal_exti.h │ ├── stm32f3xx_hal_flash.h │ ├── stm32f3xx_hal_flash_ex.h │ ├── stm32f3xx_hal_gpio.h │ ├── stm32f3xx_hal_gpio_ex.h │ ├── stm32f3xx_hal_pwr.h │ ├── stm32f3xx_hal_pwr_ex.h │ ├── stm32f3xx_hal_rcc.h │ ├── stm32f3xx_hal_rcc_ex.h │ ├── stm32f3xx_hal_tim.h │ └── stm32f3xx_hal_tim_ex.h │ ├── License.md │ └── Src │ ├── stm32f3xx_hal.c │ ├── stm32f3xx_hal_cortex.c │ ├── stm32f3xx_hal_dma.c │ ├── stm32f3xx_hal_exti.c │ ├── stm32f3xx_hal_flash.c │ ├── stm32f3xx_hal_flash_ex.c │ ├── stm32f3xx_hal_gpio.c │ ├── stm32f3xx_hal_pwr.c │ ├── stm32f3xx_hal_pwr_ex.c │ ├── stm32f3xx_hal_rcc.c │ ├── stm32f3xx_hal_rcc_ex.c │ ├── stm32f3xx_hal_tim.c │ └── stm32f3xx_hal_tim_ex.c ├── LICENSE.md ├── README.md ├── STM32F303VCTX_FLASH.ld ├── cmake └── gcc-arm-none-eabi.cmake ├── datasheets ├── Description of STM32F3 HAL and LL Drivers.pdf ├── GNU ARM Assembler Quick Reference.pdf ├── STM32 Cortex-M4 Programming Manual.pdf └── STM32F303xC Datasheet.pdf └── readme_assets ├── book-rtos-valvano.jpg ├── project.jpg ├── saleae-logic2-session.sal └── screenshot-logic-analyzer.png /.clang-format: -------------------------------------------------------------------------------- 1 | BasedOnStyle: Microsoft 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .mxproject 2 | *.launch 3 | .settings/* 4 | 5 | build/* 6 | Debug/* 7 | Release/* 8 | 9 | .vscode/* 10 | !.vscode/c_cpp_properties.json 11 | !.vscode/cmake-kits.json 12 | !.vscode/extensions.json 13 | !.vscode/launch.json 14 | !.vscode/tasks.json 15 | -------------------------------------------------------------------------------- /.vscode/c_cpp_properties.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 4, 3 | "configurations": [ 4 | { 5 | /* ms-vscode.cmake-tools plugin sometimes doesn't work well */ 6 | "name": "STM32 Workaround", 7 | "includePath": [ 8 | "${workspaceFolder}/**", 9 | "/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.macos64_2.0.0.202105311346/tools/lib/gcc/arm-none-eabi/9.3.1/include" 10 | ], 11 | "defines": ["STM32F303xC"] 12 | }, 13 | { 14 | /* ms-vscode.cmake-tools plugin shall to be installed, which provides include paths and defines through CMake file */ 15 | "name": "STM32", 16 | "includePath": [], 17 | "defines": [], 18 | "compilerPath": "", 19 | "cStandard": "gnu17", 20 | "cppStandard": "gnu++14", 21 | "intelliSenseMode": "${default}", 22 | 23 | /* Use this and all the include paths will come from CMake configuration instead */ 24 | "configurationProvider": "ms-vscode.cmake-tools" 25 | } 26 | ] 27 | } 28 | -------------------------------------------------------------------------------- /.vscode/extensions.json: -------------------------------------------------------------------------------- 1 | { 2 | "recommendations": [ 3 | "ms-vscode.cpptools", 4 | "ms-vscode.cmake-tools", 5 | "marus25.cortex-debug", 6 | "twxs.cmake", 7 | "dan-c-underwood.arm", 8 | "zixuanwang.linkerscript" 9 | ] 10 | } 11 | -------------------------------------------------------------------------------- /.vscode/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | // Use IntelliSense to learn about possible attributes. 3 | // Hover to view descriptions of existing attributes. 4 | // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 5 | "version": "0.2.0", 6 | "configurations": [ 7 | { 8 | "name": "Debug Microcontroller - ST-Link", 9 | "cwd": "${workspaceFolder}", 10 | "type": "cortex-debug", 11 | "executable": "${command:cmake.launchTargetPath}", // Or fixed file path: build/stm32h735g-dk-led.elf 12 | "request": "launch", // Use "attach" to connect to target w/o elf download 13 | "servertype": "stlink", 14 | "device": "STM32F303xC", // MCU used, ex. "STM32H735IG" 15 | "interface": "swd", 16 | "serialNumber": "", // Set ST-Link ID if you use multiple at the same time 17 | "runToEntryPoint": "main", 18 | "svdFile": "/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.productdb.debug_2.0.200.202201061234/resources/cmsis/STMicroelectronics_CMSIS_SVD/STM32F303.svd", 19 | "v1": false, 20 | "showDevDebugOutput": "none" 21 | 22 | /* Will get automatically detected if STM32CubeIDE is installed to default directory 23 | or it can be manually provided if necessary.. */ 24 | // "serverpath": "c:\\ST\\STM32CubeIDE_1.7.0\\STM32CubeIDE\\plugins\\com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.win32_2.0.100.202109301221\\tools\\bin\\ST-LINK_gdbserver.exe", 25 | // "armToolchainPath": "c:\\ST\\STM32CubeIDE_1.7.0\\STM32CubeIDE\\plugins\\com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_2.0.0.202105311346\\tools\\bin", 26 | // "stm32cubeprogrammer": "c:\\Program Files\\STMicroelectronics\\STM32Cube\\STM32CubeProgrammer\\bin", 27 | 28 | /* If you use external loader, add additional arguments */ 29 | // "serverArgs": ["--extload", "path/to/ext/loader.stldr"], 30 | } 31 | ] 32 | } 33 | -------------------------------------------------------------------------------- /.vscode/tasks.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "2.0.0", 3 | "tasks": [ 4 | { 5 | "type": "cppbuild", 6 | "label": "Build project", 7 | "command": "cmake", 8 | "args": ["--build", "${command:cmake.buildDirectory}", "-j", "8"], 9 | "options": { 10 | "cwd": "${workspaceFolder}" 11 | }, 12 | "problemMatcher": ["$gcc"], 13 | "group": { 14 | "kind": "build", 15 | "isDefault": true 16 | } 17 | }, 18 | { 19 | "type": "shell", 20 | "label": "Re-build project", 21 | "command": "cmake", 22 | "args": [ 23 | "--build", 24 | "${command:cmake.buildDirectory}", 25 | "--clean-first", 26 | "-v", 27 | "-j", 28 | "8" 29 | ], 30 | "options": { 31 | "cwd": "${workspaceFolder}" 32 | }, 33 | "problemMatcher": ["$gcc"] 34 | }, 35 | { 36 | "type": "shell", 37 | "label": "Clean project", 38 | "command": "cmake", 39 | "args": [ 40 | "--build", 41 | "${command:cmake.buildDirectory}", 42 | "--target", 43 | "clean" 44 | ], 45 | "options": { 46 | "cwd": "${workspaceFolder}" 47 | }, 48 | "problemMatcher": [] 49 | }, 50 | { 51 | "type": "shell", 52 | "label": "CubeProg: Flash project (SWD)", 53 | "command": "STM32_Programmer_CLI", 54 | "args": [ 55 | "--connect", 56 | "port=swd", 57 | "--download", 58 | "${command:cmake.launchTargetPath}", 59 | "-hardRst" 60 | ], 61 | "options": { 62 | "cwd": "${workspaceFolder}" 63 | }, 64 | "problemMatcher": [] 65 | }, 66 | { 67 | "type": "shell", 68 | "label": "CubeProg: List all available communication interfaces", 69 | "command": "STM32_Programmer_CLI", 70 | "args": ["--list"], 71 | "options": { 72 | "cwd": "${workspaceFolder}" 73 | }, 74 | "problemMatcher": [] 75 | } 76 | ] 77 | } 78 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | cmake_minimum_required(VERSION 3.22) 2 | 3 | message("Entering ${CMAKE_CURRENT_LIST_DIR}/CMakeLists.txt") 4 | 5 | #################################################################################################### 6 | # 7 | # Core project settings 8 | # 9 | #################################################################################################### 10 | 11 | set(PROJ_PATH ${CMAKE_CURRENT_SOURCE_DIR}) 12 | project(stm32f3-tiny-rtos) 13 | enable_language(C ASM) 14 | message("Build type: " ${CMAKE_BUILD_TYPE}) 15 | 16 | # Setup compiler settings 17 | set(CMAKE_C_STANDARD 23) 18 | set(CMAKE_C_STANDARD_REQUIRED ON) 19 | set(CMAKE_C_EXTENSIONS ON) 20 | 21 | #################################################################################################### 22 | # 23 | # Project's variables 24 | # 25 | #################################################################################################### 26 | 27 | # Core MCU flags, CPU, instruction set and FPU setup 28 | set(CPU_PARAMETERS 29 | -mthumb 30 | -mcpu=cortex-m4 31 | -mfpu=fpv4-sp-d16 32 | -mfloat-abi=hard 33 | ) 34 | 35 | # Symbols definition 36 | set(symbols_c_SYMB 37 | "USE_HAL_DRIVER" 38 | "STM32F303xC" 39 | ) 40 | set(symbols_asm_SYMB ) 41 | 42 | # Set linker script and executable 43 | set(linker_script_SRC ${PROJ_PATH}/STM32F303VCTX_FLASH.ld) 44 | set(EXECUTABLE ${CMAKE_PROJECT_NAME}) 45 | 46 | #################################################################################################### 47 | # 48 | # Project's source files and include directories 49 | # 50 | #################################################################################################### 51 | 52 | # Source files 53 | set(src_core_src_SRCS 54 | ${PROJ_PATH}/Core/Src/fifo_queue.c 55 | ${PROJ_PATH}/Core/Src/main.c 56 | ${PROJ_PATH}/Core/Src/onboard_user_button.c 57 | ${PROJ_PATH}/Core/Src/os.c 58 | ${PROJ_PATH}/Core/Src/os_asm.s 59 | ${PROJ_PATH}/Core/Src/schedl_timer.c 60 | ${PROJ_PATH}/Core/Src/stm32f3xx_it.c 61 | ${PROJ_PATH}/Core/Src/stm32f3xx_hal_msp.c 62 | ${PROJ_PATH}/Core/Src/syscalls.c 63 | ${PROJ_PATH}/Core/Src/system_stm32f3xx.c 64 | ${PROJ_PATH}/Core/Src/sysmem.c 65 | ${PROJ_PATH}/Core/Src/user_tasks.c) 66 | 67 | set(src_core_startup_SRCS 68 | ${PROJ_PATH}/Core/Startup/startup_stm32f303vctx.s) 69 | 70 | set(src_drivers_stm32f3xx_hal_driver_src_SRCS 71 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c 72 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c 73 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c 74 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c 75 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c 76 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c 77 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c 78 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c 79 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c 80 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c 81 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c 82 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c 83 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c) 84 | 85 | # Include directories 86 | set(include_c_DIRS 87 | ${PROJ_PATH}/Core/Inc 88 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Inc 89 | ${PROJ_PATH}/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy 90 | ${PROJ_PATH}/Drivers/CMSIS/Device/ST/STM32F3xx/Include 91 | ${PROJ_PATH}/Drivers/CMSIS/Include 92 | ) 93 | set(include_asm_DIRS ) 94 | 95 | #################################################################################################### 96 | # 97 | # Executable 98 | # 99 | #################################################################################################### 100 | 101 | # Link directories setup; must be done before executable is added 102 | set(link_DIRS ) 103 | link_directories(${EXECUTABLE} ${link_DIRS}) 104 | 105 | # Executable files 106 | add_executable(${EXECUTABLE} 107 | ${src_core_src_SRCS} 108 | ${src_core_startup_SRCS} 109 | ${src_drivers_stm32f3xx_hal_driver_src_SRCS}) 110 | 111 | # Add linked libraries for linker 112 | set(link_LIBS ) 113 | target_link_libraries(${EXECUTABLE} ${link_LIBS}) 114 | 115 | # Project symbols 116 | target_compile_definitions(${EXECUTABLE} PRIVATE 117 | # Language specific only 118 | $<$: ${symbols_c_SYMB}> 119 | $<$: ${symbols_asm_SYMB}> 120 | 121 | # Configuration specific 122 | $<$: DEBUG> 123 | $<$: > 124 | ) 125 | 126 | # Include paths 127 | target_include_directories(${EXECUTABLE} PRIVATE 128 | # Language specific only 129 | $<$: ${include_c_DIRS}> 130 | $<$: ${include_asm_DIRS}> 131 | 132 | # Configuration specific 133 | $<$: > 134 | $<$: > 135 | ) 136 | 137 | # Compiler and linker options 138 | target_compile_options(${EXECUTABLE} PRIVATE 139 | ${CPU_PARAMETERS} 140 | -Wall 141 | -Wextra 142 | -Wpedantic 143 | -Wno-unused-parameter 144 | 145 | # Language specific only 146 | $<$: > 147 | $<$: -x assembler-with-cpp -MMD -MP> 148 | 149 | # Configuration specific 150 | $<$: -Og -g3 -ggdb> 151 | $<$: -Og -g0> 152 | ) 153 | 154 | # Setup linker parameters 155 | target_link_options(${EXECUTABLE} PRIVATE 156 | -T${linker_script_SRC} 157 | ${CPU_PARAMETERS} 158 | -Wl,-Map=${CMAKE_PROJECT_NAME}.map 159 | -u _printf_float # STDIO float formatting support (remove if not used) 160 | --specs=nosys.specs 161 | -Wl,--start-group 162 | -lc 163 | -lm 164 | -lstdc++ 165 | -lsupc++ 166 | -Wl,--end-group 167 | -Wl,--print-memory-usage 168 | ) 169 | 170 | #################################################################################################### 171 | # 172 | # Post Build 173 | # 174 | #################################################################################################### 175 | 176 | # Execute post-build to print size 177 | add_custom_command(TARGET ${EXECUTABLE} POST_BUILD 178 | COMMAND ${CMAKE_SIZE} $ 179 | ) 180 | 181 | # Convert output to hex and binary 182 | add_custom_command(TARGET ${EXECUTABLE} POST_BUILD 183 | COMMAND ${CMAKE_OBJCOPY} -O ihex $ ${EXECUTABLE}.hex 184 | ) 185 | add_custom_command(TARGET ${EXECUTABLE} POST_BUILD 186 | COMMAND ${CMAKE_OBJCOPY} -O binary $ ${EXECUTABLE}.bin 187 | ) 188 | 189 | message("Exiting ${CMAKE_CURRENT_LIST_DIR}/CMakeLists.txt") 190 | -------------------------------------------------------------------------------- /CMakePresets.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 3, 3 | "configurePresets": [ 4 | { 5 | "name": "default", 6 | "hidden": true, 7 | "generator": "Ninja", 8 | "binaryDir": "${sourceDir}/build/${presetName}", 9 | "toolchainFile": "${sourceDir}/cmake/gcc-arm-none-eabi.cmake", 10 | "cacheVariables": { 11 | "CMAKE_EXPORT_COMPILE_COMMANDS": "ON" 12 | } 13 | }, 14 | { 15 | "name": "Debug", 16 | "inherits": "default", 17 | "cacheVariables": { 18 | "CMAKE_BUILD_TYPE": "Debug" 19 | } 20 | }, 21 | { 22 | "name": "RelWithDebInfo", 23 | "inherits": "default", 24 | "cacheVariables": { 25 | "CMAKE_BUILD_TYPE": "RelWithDebInfo" 26 | } 27 | }, 28 | { 29 | "name": "Release", 30 | "inherits": "default", 31 | "cacheVariables": { 32 | "CMAKE_BUILD_TYPE": "Release" 33 | } 34 | }, 35 | { 36 | "name": "MinSizeRel", 37 | "inherits": "default", 38 | "cacheVariables": { 39 | "CMAKE_BUILD_TYPE": "MinSizeRel" 40 | } 41 | } 42 | ] 43 | } 44 | -------------------------------------------------------------------------------- /Core/Inc/fifo_queue.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module fifo_queue shows how to use three semaphores to create a multiple-producer 3 | * multiple-consumer FIFO queue: producer threads will block when the FIFO is full, and 4 | * consumer threads will block when the FIFO is empty. 5 | * 6 | * Example: 7 | * ```c 8 | * #include "fifo_queue.h" 9 | * 10 | * FifoQueue_t fifo; 11 | * FifoQueue_Init(&fifo); 12 | * 13 | * FifoQueue_Put(&fifo, 234); 14 | * FifoQueue_Put(&fifo, 567); 15 | * 16 | * uint32_t item 17 | * item = FifoQueue_Get(&fifo); 18 | * item = FifoQueue_Get(&fifo); 19 | * ``` 20 | */ 21 | 22 | #pragma once 23 | 24 | #include "os.h" 25 | #include 26 | 27 | #define FIFOQUEUE_SIZE 10 28 | 29 | typedef struct 30 | { 31 | uint32_t data[FIFOQUEUE_SIZE]; 32 | uint32_t *put_pt; 33 | uint32_t *get_pt; 34 | Semaphore_t current_size; 35 | Semaphore_t room_left; 36 | Semaphore_t mutex; 37 | } FifoQueue_t; 38 | 39 | void FifoQueue_Init(FifoQueue_t *fifo); 40 | 41 | void FifoQueue_Put(FifoQueue_t *fifo, uint32_t item); 42 | 43 | uint32_t FifoQueue_Get(FifoQueue_t *fifo); 44 | -------------------------------------------------------------------------------- /Core/Inc/iferr.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module iferr provides macros for shortening error-handling. 3 | * The fn panic is implemented by the caller. 4 | * 5 | * Example: 6 | * ```c 7 | * #include "iferr.h" 8 | * 9 | * HAL_StatusTypeDef fn_a(bool arg); 10 | * HAL_StatusTypeDef fn_b(void); 11 | * 12 | * void panic(void) 13 | * { 14 | * __disable_irq(); 15 | * __asm("BKPT 1"); 16 | * } 17 | * 18 | * HAL_StatusTypeDef init_peripheral(uint32_t arg1, bool arg2) 19 | * { 20 | * assert_or_panic(arg1 < 10); 21 | * IFERR_RETE (fn_a(arg2)); 22 | * IFERR_PANIC(fn_b()); 23 | * return HAL_OK; 24 | * } 25 | * ``` 26 | */ 27 | 28 | #pragma once 29 | 30 | #include "stm32f3xx_hal.h" 31 | 32 | /** 33 | * The panic fn is implemented by the caller. 34 | */ 35 | void panic(void); 36 | 37 | /** 38 | * Assert, or panic. 39 | */ 40 | #define assert_or_panic(expr) ((expr) ? (void)0U : panic()) 41 | 42 | /** 43 | * If error, return error. 44 | */ 45 | #define IFERR_RETE(x) \ 46 | do \ 47 | { \ 48 | HAL_StatusTypeDef err = (x); \ 49 | if (err != HAL_OK) \ 50 | { \ 51 | return err; \ 52 | } \ 53 | } while (0) 54 | 55 | /** 56 | * If error, panic. 57 | */ 58 | #define IFERR_PANIC(x) \ 59 | do \ 60 | { \ 61 | HAL_StatusTypeDef err = (x); \ 62 | if (err != HAL_OK) \ 63 | { \ 64 | panic(); \ 65 | } \ 66 | } while (0) 67 | -------------------------------------------------------------------------------- /Core/Inc/instrument_trigger.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module instrument_trigger provides a macro that generates functions to set up and 3 | * use a GPIO pin as push-pull output. 4 | * Those pins are useful for toggling LED and/or triggering a debugging instrument, 5 | * i.e. an oscilloscope or a logic analyzer. 6 | * 7 | * Example: 8 | * ```c 9 | * #include "instrument-trigger.h" 10 | * InstrumentTrigger_Create(E, 13); 11 | * 12 | * InstrumentTriggerPE13_Init(); 13 | * while (1) 14 | * { 15 | * InstrumentTriggerPE13_Toggle(); 16 | * HAL_Delay(1000); 17 | * } 18 | * ``` 19 | * 20 | * Available user LEDs on the STM32F3 Discovery Board: 21 | * - LD3: Red LED connected to the I/O PE9 of the STM32F303VCT6 22 | * - LD4: Blue LED connected to the I/O PE8 of the STM32F303VCT6 23 | * - LD5: Orange LED connected to the I/O PE10 of the STM32F303VCT6 24 | * - LD6: Green LED connected to the I/O PE15 of the STM32F303VCT6 25 | * - LD7: Green LED connected to the I/O PE11 of the STM32F303VCT6 26 | * - LD8: Orange LED connected to the I/O PE14 of the STM32F303VCT6 27 | * - LD9: Blue LED connected to the I/O PE12 of the STM32F303VCT6 28 | * - LD10: Red LED connected to the I/O PE13 of the STM32F303VCT6 29 | */ 30 | 31 | #pragma once 32 | 33 | #include "stm32f3xx_hal.h" 34 | 35 | #define InstrumentTrigger_Create(PORT, PIN) \ 36 | void InstrumentTriggerP##PORT##PIN##_Init(void) \ 37 | { \ 38 | __HAL_RCC_GPIO##PORT##_CLK_ENABLE(); \ 39 | GPIO_InitTypeDef GPIO_InitStruct = {0}; \ 40 | GPIO_InitStruct.Pin = GPIO_PIN_##PIN; \ 41 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; \ 42 | GPIO_InitStruct.Pull = GPIO_NOPULL; \ 43 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; \ 44 | HAL_GPIO_Init(GPIO##PORT, &GPIO_InitStruct); \ 45 | } \ 46 | void InstrumentTriggerP##PORT##PIN##_Set(void) \ 47 | { \ 48 | HAL_GPIO_WritePin(GPIO##PORT, GPIO_PIN_##PIN, GPIO_PIN_SET); \ 49 | } \ 50 | void InstrumentTriggerP##PORT##PIN##_Reset(void) \ 51 | { \ 52 | HAL_GPIO_WritePin(GPIO##PORT, GPIO_PIN_##PIN, GPIO_PIN_RESET); \ 53 | } \ 54 | void InstrumentTriggerP##PORT##PIN##_Toggle(void) \ 55 | { \ 56 | HAL_GPIO_TogglePin(GPIO##PORT, GPIO_PIN_##PIN); \ 57 | } \ 58 | GPIO_PinState InstrumentTriggerP##PORT##PIN##_Read(void) \ 59 | { \ 60 | return HAL_GPIO_ReadPin(GPIO##PORT, GPIO_PIN_##PIN); \ 61 | } \ 62 | _Static_assert(1, "semi-colon required after this macro, see https://stackoverflow.com/a/59153563/7168774") 63 | -------------------------------------------------------------------------------- /Core/Inc/onboard_user_button.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module onboard_user_button shows how to use the semaphore provided by the OS 3 | * to debounce the onboard user button on PA0. 4 | * 5 | * In short: 6 | * - the interrupt handler is registered on rising edges of PA0; 7 | * - the OnboardUserButton_Task is run by the OS, but blocks immediately waiting for SemaphoreButtonPressed; 8 | * - when the interrupt is triggered, SemaphoreButtonPressed is signaled; 9 | * - the task unblocks on SemaphoreButtonPressed, invokes the callback function, and debounces the button; 10 | * - the callback function toggles the onboard LED on PE8; 11 | * - the task blocks again on SemaphoreButtonPressed; 12 | * 13 | * How this module is used in the project: 14 | * 15 | * _stm32f3xx_it.c_ 16 | * ```c 17 | * #include "onboard_user_button.h" 18 | * 19 | * void EXTI0_IRQHandler(void) 20 | * { 21 | * OnboardUserButton_IRQHandler(); 22 | * } 23 | * ``` 24 | * 25 | * _main.c_ 26 | * ```c 27 | * #include "onboard_user_button.h" 28 | * 29 | * #define TASK_PRIORITY 100 30 | * #define TASK_NAME "OnboardUserButton_Task" 31 | * 32 | * int main(void) 33 | * { 34 | * IFERR_PANIC(HAL_Init()); 35 | * SystemClock_Config(); 36 | * 37 | * OnboardUserButton_Init(); 38 | * 39 | * OS_Init(500); 40 | * OS_Thread_CreateFirst(OnboardUserButton_Task, TASK_PRIORITY, TASK_NAME); 41 | * OS_Launch(); 42 | * } 43 | * ``` 44 | * 45 | * IMPORTANT! 46 | * For this module to behave properly, make sure THREADFREQ is at least 500Hz. 47 | * Conversely, if THREADFREQ is 1Hz, for example, OnboardUserButton_Task might as well run 48 | * four seconds after the button has been pressed, making the callback fn very unresponsive. 49 | */ 50 | 51 | #pragma once 52 | 53 | void OnboardUserButton_Init(void); 54 | 55 | void OnboardUserButton_IRQHandler(void); 56 | 57 | void OnboardUserButton_Task(void); 58 | -------------------------------------------------------------------------------- /Core/Inc/os.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module os encapsulates the core functionality of the operating system and 3 | * exposes the functions for interacting with it. 4 | */ 5 | 6 | #pragma once 7 | 8 | #include 9 | 10 | #define MAXNUMTHREADS 10 /* Maximum number of threads, allocated at compile time */ 11 | #define STACKSIZE 100 /* Number of 32-bit words in each TCB's stack */ 12 | #define THREADFREQ 1 /* Maximum time-slice, in Hz, before the scheduler is run */ 13 | 14 | #define OS_SCHEDL_PRIO_MIN UINT8_MAX /* Lowest priority that can be assigned to a thread */ 15 | #define OS_SCHEDL_PRIO_MAX 0 /* Highest priority that can be assigned to a thread */ 16 | #define OS_SCHEDL_PRIO_MAIN_THREAD 200 /* Baseline priority to be assigned to main threads */ 17 | #define OS_SCHEDL_PRIO_EVENT_THREAD 100 /* Baseline priority to be assigned to event threads */ 18 | 19 | /** 20 | * The type Semaphore_t abstracts the semaphore's counter. 21 | * A value of type *Semaphore_t should only be updated through the fn OS_Semaphore_Wait 22 | * and OS_Semaphore_Signal. 23 | */ 24 | typedef int32_t Semaphore_t; 25 | 26 | /** 27 | * Function descriptions are provided in os.c 28 | */ 29 | 30 | void OS_Init(uint32_t scheduler_frequency_hz); 31 | 32 | void OS_Thread_CreateFirst(void (*task)(void), uint8_t priority, const char *name); 33 | 34 | void OS_Thread_Create(void (*task)(void), uint8_t priority, const char *name); 35 | 36 | void OS_Launch(void); 37 | 38 | void OS_Scheduler(void); 39 | 40 | void OS_Thread_Suspend(void); 41 | 42 | void OS_Thread_Sleep(uint32_t sleep_duration_ms); 43 | 44 | void OS_DecrementTCBsSleepDuration(void); 45 | 46 | void OS_Thread_Kill(void); 47 | 48 | void OS_Semaphore_Wait(Semaphore_t *sem); 49 | 50 | void OS_Semaphore_Signal(Semaphore_t *sem); 51 | -------------------------------------------------------------------------------- /Core/Inc/schedl_timer.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module schedl_timer abstract the timer functionality used by the OS scheduler. 3 | */ 4 | 5 | #pragma once 6 | 7 | #include "stm32f3xx_hal.h" 8 | 9 | #define SchedlTimer_Instance TIM2 10 | #define SchedlTimer_ClkEnable __HAL_RCC_TIM2_CLK_ENABLE 11 | #define SchedlTimer_IRQn TIM2_IRQn 12 | #define SchedlTimer_IRQPreemptPriority (TICK_INT_PRIORITY + 1) 13 | #define SchedlTimer_IRQSubPriority 0 14 | #define SchedlTimer_IRQHandler TIM2_IRQHandler 15 | 16 | void SchedlTimer_Init(uint32_t reload_frequency_hz); 17 | 18 | void SchedlTimer_Start(void); 19 | 20 | void SchedlTimer_ClearITFlag(void); 21 | 22 | void SchedlTimer_ResetCounter(void); 23 | 24 | /* Implemented in os_asm.s */ 25 | void SchedlTimer_IRQHandler(void); 26 | -------------------------------------------------------------------------------- /Core/Inc/stm32f3xx_hal_msp.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module stm32f3xx_hal_msp initializes the MSPs (MCU Support Packages). 3 | */ 4 | 5 | #pragma once 6 | 7 | #include "stm32f3xx_hal.h" 8 | 9 | /** 10 | * The fn HAL_MspInit initializes the global MSP. 11 | */ 12 | void HAL_MspInit(void); 13 | 14 | /** 15 | * The fn HAL_TIM_Base_MspInit initializes the TIMs low level resources. 16 | */ 17 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 18 | -------------------------------------------------------------------------------- /Core/Inc/stm32f3xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module stm32f3xx_it provides the interrupt and exception handlers. 3 | */ 4 | 5 | #pragma once 6 | 7 | #include "schedl_timer.h" 8 | 9 | //================================================================================================== 10 | // CORTEX-M4 PROCESSOR INTERRUPTION AND EXCEPTION HANDLERS 11 | //================================================================================================== 12 | 13 | /** 14 | * The function NMI_Handler handles non maskable interrupts. 15 | */ 16 | void NMI_Handler(void); 17 | 18 | /** 19 | * The function HardFault_Handler handles hard fault interrupts. 20 | */ 21 | void HardFault_Handler(void); 22 | 23 | /** 24 | * The function MemManage_Handler handles memory management faults. 25 | */ 26 | void MemManage_Handler(void); 27 | 28 | /** 29 | * The function BusFault_Handler handles pre-fetch faults and memory access faults. 30 | */ 31 | void BusFault_Handler(void); 32 | 33 | /** 34 | * The function UsageFault_Handler handles undefined instructions or illegal states. 35 | */ 36 | void UsageFault_Handler(void); 37 | 38 | /** 39 | * The function SVC_Handler handles system service calls via SWI instruction. 40 | */ 41 | void SVC_Handler(void); 42 | 43 | /** 44 | * The function DebugMon_Handler handles debug monitors. 45 | */ 46 | void DebugMon_Handler(void); 47 | 48 | /** 49 | * The function PendSV_Handler handles pendable requests for system service. 50 | */ 51 | void PendSV_Handler(void); 52 | 53 | /** 54 | * The function SysTick_Handler handles system tick timer interrupts. 55 | */ 56 | void SysTick_Handler(void); 57 | 58 | //================================================================================================== 59 | // STM32F3xx PERIPHERAL INTERRUPT HANDLERS 60 | // For the available peripheral interrupt handler names, 61 | // refer to the startup file (startup_stm32f3xx.s). 62 | //================================================================================================== 63 | 64 | /** 65 | * The function SchedlTimer_IRQHandler handles SchedlTimer interrupts. 66 | * The implementation is in os_asm.s 67 | */ 68 | void SchedlTimer_IRQHandler(void); 69 | 70 | /** 71 | * The function EXTI0_IRQHandler handles EXTI interrupts from Line 0. 72 | */ 73 | void EXTI0_IRQHandler(void); 74 | -------------------------------------------------------------------------------- /Core/Inc/user_tasks.h: -------------------------------------------------------------------------------- 1 | /** 2 | * The module user_tasks provides dummy tasks to be run by the OS. 3 | */ 4 | 5 | #pragma once 6 | 7 | void UserTask_0(void); 8 | void UserTask_1(void); 9 | void UserTask_2(void); 10 | void UserTask_3(void); 11 | -------------------------------------------------------------------------------- /Core/Src/fifo_queue.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "fifo_queue.h" 6 | 7 | #include 8 | 9 | //================================================================================================== 10 | // DEFINES - MACROS 11 | //================================================================================================== 12 | 13 | /* These #defines improve code readability */ 14 | 15 | #define fifo_data (fifo->data) 16 | #define fifo_put_pt (fifo->put_pt) 17 | #define fifo_get_pt (fifo->get_pt) 18 | #define fifo_current_size (fifo->current_size) 19 | #define fifo_room_left (fifo->room_left) 20 | #define fifo_mutex (fifo->mutex) 21 | 22 | //================================================================================================== 23 | // ENUMS - STRUCTS - TYPEDEFS 24 | //================================================================================================== 25 | 26 | //================================================================================================== 27 | // STATIC PROTOTYPES 28 | //================================================================================================== 29 | 30 | //================================================================================================== 31 | // STATIC VARIABLES 32 | //================================================================================================== 33 | 34 | //================================================================================================== 35 | // GLOBAL FUNCTIONS 36 | //================================================================================================== 37 | 38 | void FifoQueue_Init(FifoQueue_t *fifo) 39 | { 40 | memset(fifo_data, 0x00, FIFOQUEUE_SIZE * sizeof(uint32_t)); 41 | fifo_put_pt = fifo_get_pt = &fifo_data[0]; 42 | fifo_current_size = 0; 43 | fifo_room_left = FIFOQUEUE_SIZE; 44 | fifo_mutex = 1; 45 | } 46 | 47 | void FifoQueue_Put(FifoQueue_t *fifo, uint32_t item) 48 | { 49 | OS_Semaphore_Wait(&fifo_room_left); 50 | OS_Semaphore_Wait(&fifo_mutex); 51 | 52 | *fifo_put_pt = item; 53 | fifo_put_pt++; 54 | if (fifo_put_pt == &fifo_data[FIFOQUEUE_SIZE]) 55 | { 56 | /* Wrap */ 57 | fifo_put_pt = &fifo_data[0]; 58 | } 59 | 60 | OS_Semaphore_Signal(&fifo_mutex); 61 | OS_Semaphore_Signal(&fifo_current_size); 62 | } 63 | 64 | uint32_t FifoQueue_Get(FifoQueue_t *fifo) 65 | { 66 | OS_Semaphore_Wait(&fifo_current_size); 67 | OS_Semaphore_Wait(&fifo_mutex); 68 | 69 | uint32_t item = *fifo_get_pt; 70 | fifo_get_pt++; 71 | if (fifo_get_pt == &fifo_data[FIFOQUEUE_SIZE]) 72 | { 73 | /* Wrap */ 74 | fifo_get_pt = &fifo_data[0]; 75 | } 76 | 77 | OS_Semaphore_Signal(&fifo_mutex); 78 | OS_Semaphore_Signal(&fifo_room_left); 79 | return item; 80 | } 81 | 82 | //================================================================================================== 83 | // STATIC FUNCTIONS 84 | //================================================================================================== 85 | -------------------------------------------------------------------------------- /Core/Src/main.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "iferr.h" 6 | #include "onboard_user_button.h" 7 | #include "os.h" 8 | #include "user_tasks.h" 9 | 10 | #include "stm32f3xx_hal.h" 11 | 12 | //================================================================================================== 13 | // DEFINES - MACROS 14 | //================================================================================================== 15 | 16 | //================================================================================================== 17 | // ENUMS - STRUCTS - TYPEDEFS 18 | //================================================================================================== 19 | 20 | //================================================================================================== 21 | // STATIC PROTOTYPES 22 | //================================================================================================== 23 | 24 | static void SystemClock_Config(void); 25 | 26 | //================================================================================================== 27 | // STATIC VARIABLES 28 | //================================================================================================== 29 | 30 | //================================================================================================== 31 | // GLOBAL FUNCTIONS 32 | //================================================================================================== 33 | 34 | int main(void) 35 | { 36 | /* Reset all peripherals, initialize the Systick, configure the system clock */ 37 | IFERR_PANIC(HAL_Init()); 38 | SystemClock_Config(); 39 | OnboardUserButton_Init(); 40 | 41 | /* Set up and start the OS */ 42 | OS_Init(THREADFREQ); 43 | OS_Thread_CreateFirst(UserTask_0, OS_SCHEDL_PRIO_MAIN_THREAD, "UserTask_0"); 44 | OS_Thread_Create(UserTask_1, OS_SCHEDL_PRIO_MAIN_THREAD, "UserTask_1"); 45 | OS_Thread_Create(UserTask_2, OS_SCHEDL_PRIO_MAIN_THREAD, "UserTask_2"); 46 | OS_Thread_Create(OnboardUserButton_Task, OS_SCHEDL_PRIO_EVENT_THREAD, "OnboardUserButton_Task"); 47 | OS_Launch(); 48 | 49 | /* This statement should not be reached */ 50 | panic(); 51 | } 52 | 53 | void panic(void) 54 | { 55 | __disable_irq(); 56 | __asm("BKPT 1"); 57 | } 58 | 59 | //================================================================================================== 60 | // STATIC FUNCTIONS 61 | //================================================================================================== 62 | 63 | static void SystemClock_Config(void) 64 | { 65 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 66 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 67 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 68 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 69 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 70 | IFERR_PANIC(HAL_RCC_OscConfig(&RCC_OscInitStruct)); 71 | 72 | /* As the system clock frequency is just 8MHz (no PLL), it's safe not to reduce the bus clocks */ 73 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 74 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 75 | RCC_ClkInitStruct.SYSCLKSource = RCC_CFGR_SW_HSI; 76 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 77 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* Fmax = 36 MHz */ 78 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* Fmax = 72 MHz */ 79 | IFERR_PANIC(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0)); 80 | 81 | /* Each time HAL_RCC_ClockConfig() is called to configure the system clock frequency, 82 | * the variable SystemCoreClock is updated */ 83 | assert_or_panic(SystemCoreClock == 8000000); 84 | } 85 | -------------------------------------------------------------------------------- /Core/Src/onboard_user_button.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "onboard_user_button.h" 6 | 7 | #include "instrument_trigger.h" 8 | #include "os.h" 9 | 10 | #include "stm32f3xx_hal.h" 11 | 12 | //================================================================================================== 13 | // DEFINES - MACROS 14 | //================================================================================================== 15 | 16 | InstrumentTrigger_Create(E, 8); 17 | 18 | //================================================================================================== 19 | // ENUMS - STRUCTS - TYPEDEFS 20 | //================================================================================================== 21 | 22 | //================================================================================================== 23 | // STATIC PROTOTYPES 24 | //================================================================================================== 25 | 26 | static void OnTouch(void); 27 | 28 | //================================================================================================== 29 | // STATIC VARIABLES 30 | //================================================================================================== 31 | 32 | static Semaphore_t SemaphoreButtonPressed = 0; 33 | 34 | //================================================================================================== 35 | // GLOBAL FUNCTIONS 36 | //================================================================================================== 37 | 38 | void OnboardUserButton_Init(void) 39 | { 40 | __HAL_RCC_GPIOA_CLK_ENABLE(); 41 | GPIO_InitTypeDef GPIO_InitStruct; 42 | GPIO_InitStruct.Pin = GPIO_PIN_0; 43 | GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 44 | GPIO_InitStruct.Pull = GPIO_PULLDOWN; 45 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 46 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 47 | HAL_NVIC_SetPriority(EXTI0_IRQn, 0x0F, 0); /* Minimum pre-emption priority */ 48 | HAL_NVIC_EnableIRQ(EXTI0_IRQn); 49 | InstrumentTriggerPE8_Init(); 50 | } 51 | 52 | void OnboardUserButton_IRQHandler(void) 53 | { 54 | __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_0); 55 | HAL_NVIC_DisableIRQ(EXTI0_IRQn); 56 | OS_Semaphore_Signal(&SemaphoreButtonPressed); 57 | } 58 | 59 | void OnboardUserButton_Task(void) 60 | { 61 | while (1) 62 | { 63 | OS_Semaphore_Wait(&SemaphoreButtonPressed); 64 | OnTouch(); 65 | HAL_Delay(10); 66 | HAL_NVIC_EnableIRQ(EXTI0_IRQn); 67 | } 68 | } 69 | 70 | //================================================================================================== 71 | // STATIC FUNCTIONS 72 | //================================================================================================== 73 | 74 | static void OnTouch(void) 75 | { 76 | InstrumentTriggerPE8_Toggle(); 77 | } 78 | -------------------------------------------------------------------------------- /Core/Src/os.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "os.h" 6 | 7 | #include "iferr.h" 8 | #include "schedl_timer.h" 9 | 10 | #include "stm32f3xx_hal.h" 11 | 12 | //================================================================================================== 13 | // DEFINES - MACROS 14 | //================================================================================================== 15 | 16 | //================================================================================================== 17 | // ENUMS - STRUCTS - TYPEDEFS 18 | //================================================================================================== 19 | 20 | /** 21 | * TCBState indicates whether the TCB can be used by OS_ThreadCreate 22 | * to create a new thread. 23 | */ 24 | typedef enum 25 | { 26 | TCBStateFree, 27 | TCBStateActive 28 | } TCBState_t; 29 | 30 | /** 31 | * Thread Control Block 32 | * 33 | * IMPORTANT! 34 | * The fn OSAsm_Start and OSAsm_ThreadSwitch, implemented in os_asm.s, expect the stack pointer 35 | * to be placed first in the struct. Don't shuffle it! 36 | */ 37 | typedef struct TCB 38 | { 39 | uint32_t *sp; /* Stack pointer, valid for threads not running */ 40 | struct TCB *next; /* Pointer to circular-linked-list of TCBs */ 41 | uint32_t sleep; /* Sleep duration in ms, zero means not sleeping */ 42 | TCBState_t status; /* TCB active or free */ 43 | Semaphore_t *blocked; /* Pointer to semaphore on which the thread is blocked, NULL if not blocked */ 44 | uint8_t priority; /* Thread priority, 0 is highest, 255 is lowest */ 45 | const char *name; /* Descriptive name to facilitate debugging */ 46 | } TCB_t; 47 | 48 | //================================================================================================== 49 | // GLOBAL AND STATIC VARIABLES 50 | //================================================================================================== 51 | 52 | static TCB_t TCBs[MAXNUMTHREADS]; 53 | static uint32_t Stacks[MAXNUMTHREADS][STACKSIZE]; 54 | 55 | /* Pointer to the currently running thread */ 56 | TCB_t *RunPt; 57 | 58 | /* The variable ActiveTCBsCount tracks the number of TCBs in use by the OS */ 59 | static uint32_t ActiveTCBsCount; 60 | 61 | //================================================================================================== 62 | // FUNCTION PROTOTYPES 63 | //================================================================================================== 64 | 65 | /** 66 | * The fn OS_InitTCBsStatus initializes all TCBs' statuses to be free at startup. 67 | */ 68 | static void OS_InitTCBsStatus(void); 69 | 70 | /** 71 | * The fn OS_Init initializes the SchedlTimer and the TCBs. 72 | */ 73 | void OS_Init(uint32_t scheduler_frequency_hz); 74 | 75 | /** 76 | * The fn OS_SetInitialStack sets up the thread's stack as if it had already been running and then suspended. 77 | * Finally, it sets the TCB's SP (stack pointer) to the top of the stack (grows downwards). 78 | * Check the "STM32 Cortex-M4 Programming Manual" on page 18 for the list of processor core registers. 79 | */ 80 | static void OS_SetInitialStack(uint32_t tcb_idx); 81 | 82 | /** 83 | * The fn OS_Thread_CreateFirst establishes the circular linked list of TCBs with one node, 84 | * and points RunPt to that node. The fn must be called before the OS is launched. 85 | */ 86 | void OS_Thread_CreateFirst(void (*task)(void), uint8_t priority, const char *name); 87 | 88 | /** 89 | * The fn OS_Thread_Create adds a new thread to the circular linked list of TCBs, then runs it. 90 | * It fails if all the TCBs are already active. 91 | * 92 | * The fn can be called both: 93 | * - before the OS is launched (but after the first thread is created); 94 | * - after the OS is launched (by a running thread). 95 | * 96 | * The thread that calls this function keeps running until the end of its scheduled time-slice. 97 | * The new thread is run next. 98 | */ 99 | void OS_Thread_Create(void (*task)(void), uint8_t priority, const char *name); 100 | 101 | /** 102 | * The fn OS_Launch enables the SchedlTimer, then calls OSAsm_Start, which launches the first thread. 103 | */ 104 | void OS_Launch(void); 105 | 106 | /** 107 | * The fn OSAsm_Start, implemented in os_asm.s, is called by OS_Launch once. 108 | * It "restores" the first thread's stack on the main stack. 109 | */ 110 | extern void OSAsm_Start(void); 111 | 112 | /** 113 | * The fn OSAsm_ThreadSwitch, implemented in os_asm.s, is periodically called by the SchedlTimer (ISR). 114 | * It preemptively switches to the next thread, that is, it stores the stack of the running 115 | * thread and restores the stack of the next thread. 116 | * It calls OS_Schedule to determine which thread is run next and update RunPt. 117 | */ 118 | extern void OSAsm_ThreadSwitch(void); 119 | 120 | /** 121 | * The fn OS_Scheduler is called by OSAsm_ThreadSwitch and is responsible for determining 122 | * which thread is run next. 123 | */ 124 | void OS_Scheduler(void); 125 | 126 | /** 127 | * The fn OS_Thread_Suspend halts the current thread and switches to the next. 128 | * It's called by the running thread itself. 129 | */ 130 | void OS_Thread_Suspend(void); 131 | 132 | /** 133 | * The fn OS_Thread_Sleep makes the current thread dormant for a specified time. 134 | * It's called by the running thread itself. 135 | * The fn OS_DecrementTCBsSleepDuration is called by the SysTick ISR every ms and decrements the 136 | * the value of sleep on the TCBs. 137 | */ 138 | void OS_Thread_Sleep(uint32_t ms); 139 | void OS_DecrementTCBsSleepDuration(void); 140 | 141 | /** 142 | * The fn OS_Thread_Kill kills the thread that calls it, then starts the thread scheduled next. 143 | * It fails if the last active thread tries to kill itself. 144 | */ 145 | void OS_Thread_Kill(void); 146 | 147 | /** 148 | * The fn OS_Semaphore_Wait decrements the semaphore counter. 149 | * If the new counter's value is < 0, it marks the current thread as blocked and switches 150 | * to the next one. 151 | */ 152 | void OS_Semaphore_Wait(Semaphore_t *sem); 153 | 154 | /** 155 | * The fn OS_Semaphore_Signal increments the semaphore counter. 156 | * If the new counter's value is <= 0, it wakes up the next thread blocked on that semaphore. 157 | */ 158 | void OS_Semaphore_Signal(Semaphore_t *sem); 159 | 160 | //================================================================================================== 161 | // IMPLEMENTATION 162 | //================================================================================================== 163 | 164 | static void OS_InitTCBsStatus(void) 165 | { 166 | for (uint32_t idx = 0; idx < MAXNUMTHREADS; idx++) 167 | { 168 | TCBs[idx].status = TCBStateFree; 169 | } 170 | } 171 | 172 | void OS_Init(uint32_t scheduler_frequency_hz) 173 | { 174 | SchedlTimer_Init(scheduler_frequency_hz); 175 | OS_InitTCBsStatus(); 176 | } 177 | 178 | static void OS_SetInitialStack(uint32_t tcb_idx) 179 | { 180 | /* From the "STM32 Cortex-M4 Programming Manual" on page 23: 181 | * attempting to execute instructions when the T bit is 0 results in a fault or lockup */ 182 | Stacks[tcb_idx][STACKSIZE - 1] = 0x01000000; /* Thumb Bit (PSR) */ 183 | // Stacks[tcb_idx][STACKSIZE - 2] = /* R15 (PC) -> set later in fn OS_AddThreads 184 | Stacks[tcb_idx][STACKSIZE - 3] = 0x14141414; /* R14 (LR) */ 185 | Stacks[tcb_idx][STACKSIZE - 4] = 0x12121212; /* R12 */ 186 | Stacks[tcb_idx][STACKSIZE - 5] = 0x03030303; /* R3 */ 187 | Stacks[tcb_idx][STACKSIZE - 6] = 0x02020202; /* R2 */ 188 | Stacks[tcb_idx][STACKSIZE - 7] = 0x01010101; /* R1 */ 189 | Stacks[tcb_idx][STACKSIZE - 8] = 0x00000000; /* R0 */ 190 | Stacks[tcb_idx][STACKSIZE - 9] = 0x11111111; /* R11 */ 191 | Stacks[tcb_idx][STACKSIZE - 10] = 0x10101010; /* R10 */ 192 | Stacks[tcb_idx][STACKSIZE - 11] = 0x09090909; /* R9 */ 193 | Stacks[tcb_idx][STACKSIZE - 12] = 0x08080808; /* R8 */ 194 | Stacks[tcb_idx][STACKSIZE - 13] = 0x07070707; /* R7 */ 195 | Stacks[tcb_idx][STACKSIZE - 14] = 0x06060606; /* R6 */ 196 | Stacks[tcb_idx][STACKSIZE - 15] = 0x05050505; /* R5 */ 197 | Stacks[tcb_idx][STACKSIZE - 16] = 0x04040404; /* R4 */ 198 | 199 | TCBs[tcb_idx].sp = &Stacks[tcb_idx][STACKSIZE - 16]; /* Thread's stack pointer */ 200 | } 201 | 202 | void OS_Thread_CreateFirst(void (*task)(void), uint8_t priority, const char *name) 203 | { 204 | assert_or_panic(ActiveTCBsCount == 0); 205 | TCBs[0].next = &(TCBs[0]); 206 | TCBs[0].sleep = 0; 207 | TCBs[0].status = TCBStateActive; 208 | TCBs[0].blocked = NULL; 209 | TCBs[0].priority = priority; 210 | TCBs[0].name = name; 211 | 212 | OS_SetInitialStack(0); 213 | Stacks[0][STACKSIZE - 2] = (int32_t)task; /* PC */ 214 | 215 | /* Thread 0 will run first */ 216 | RunPt = &(TCBs[0]); 217 | ActiveTCBsCount++; 218 | } 219 | 220 | void OS_Thread_Create(void (*task)(void), uint8_t priority, const char *name) 221 | { 222 | assert_or_panic(ActiveTCBsCount > 0 && ActiveTCBsCount < MAXNUMTHREADS); 223 | __disable_irq(); 224 | 225 | /* Find next available TCB */ 226 | uint32_t new_tcb_idx; 227 | for (new_tcb_idx = 0; new_tcb_idx < MAXNUMTHREADS; new_tcb_idx++) 228 | { 229 | if (TCBs[new_tcb_idx].status == TCBStateFree) 230 | break; 231 | } 232 | 233 | TCBs[new_tcb_idx].next = RunPt->next; 234 | RunPt->next = &(TCBs[new_tcb_idx]); 235 | TCBs[new_tcb_idx].sleep = 0; 236 | TCBs[new_tcb_idx].status = TCBStateActive; 237 | TCBs[new_tcb_idx].blocked = NULL; 238 | TCBs[new_tcb_idx].priority = priority; 239 | TCBs[new_tcb_idx].name = name; 240 | 241 | OS_SetInitialStack(new_tcb_idx); 242 | Stacks[new_tcb_idx][STACKSIZE - 2] = (int32_t)task; /* PC */ 243 | 244 | ActiveTCBsCount++; 245 | __enable_irq(); 246 | } 247 | 248 | void OS_Launch(void) 249 | { 250 | assert_or_panic(ActiveTCBsCount > 0); 251 | 252 | /* Prevent the timer's ISR from firing before OSAsm_Start is called */ 253 | __disable_irq(); 254 | 255 | SchedlTimer_Start(); 256 | OSAsm_Start(); 257 | 258 | /* This statement should not be reached */ 259 | panic(); 260 | } 261 | 262 | void OS_Scheduler(void) 263 | { 264 | /* If this fn has been invoked by OS_Thread_Kill, the current TCB has been removed from the 265 | * linked list, so it's correct to start iterating from the next TCB */ 266 | TCB_t *next_pt = RunPt->next; 267 | TCB_t *iterating_pt = next_pt; 268 | 269 | /* Search for highest priority thread not sleeping or blocked */ 270 | uint32_t max_priority = UINT8_MAX + 1; 271 | TCB_t *best_pt = next_pt; 272 | do 273 | { 274 | if ((iterating_pt->priority < max_priority) && (iterating_pt->sleep == 0) && (iterating_pt->blocked == NULL)) 275 | { 276 | best_pt = iterating_pt; 277 | max_priority = best_pt->priority; 278 | } 279 | iterating_pt = iterating_pt->next; 280 | } while (iterating_pt != next_pt); 281 | 282 | RunPt = best_pt; 283 | } 284 | 285 | void OS_Thread_Suspend(void) 286 | { 287 | SchedlTimer_ResetCounter(); 288 | } 289 | 290 | void OS_Thread_Sleep(uint32_t sleep_duration_ms) 291 | { 292 | RunPt->sleep = sleep_duration_ms; 293 | OS_Thread_Suspend(); 294 | } 295 | 296 | void OS_DecrementTCBsSleepDuration(void) 297 | { 298 | for (size_t tcb_idx = 0; tcb_idx < MAXNUMTHREADS; tcb_idx++) 299 | { 300 | if (TCBs[tcb_idx].sleep > 0) 301 | { 302 | TCBs[tcb_idx].sleep -= 1; 303 | } 304 | } 305 | } 306 | 307 | void OS_Thread_Kill(void) 308 | { 309 | assert_or_panic(ActiveTCBsCount > 1); 310 | __disable_irq(); 311 | 312 | TCB_t *previous_tcb = RunPt; 313 | while (1) 314 | { 315 | previous_tcb = previous_tcb->next; 316 | if (previous_tcb->next == RunPt) 317 | break; 318 | } 319 | TCB_t *next_tcb = RunPt->next; 320 | 321 | previous_tcb->next = next_tcb; 322 | RunPt->status = TCBStateFree; 323 | 324 | ActiveTCBsCount--; 325 | __enable_irq(); 326 | OS_Thread_Suspend(); 327 | } 328 | 329 | void OS_Semaphore_Wait(Semaphore_t *sem) 330 | { 331 | __disable_irq(); 332 | (*sem) = (*sem) - 1; 333 | if ((*sem) < 0) 334 | { 335 | RunPt->blocked = sem; /* Reason the thread is blocked */ 336 | __enable_irq(); 337 | OS_Thread_Suspend(); 338 | } 339 | __enable_irq(); 340 | } 341 | 342 | void OS_Semaphore_Signal(Semaphore_t *sem) 343 | { 344 | __disable_irq(); 345 | (*sem) = (*sem) + 1; 346 | if ((*sem) <= 0) 347 | { 348 | /* Search for a TCB blocked on this semaphore and wake it up */ 349 | TCB_t *a_tcb = RunPt->next; 350 | while (a_tcb->blocked != sem) 351 | { 352 | a_tcb = a_tcb->next; 353 | } 354 | a_tcb->blocked = 0; 355 | } 356 | __enable_irq(); 357 | } 358 | -------------------------------------------------------------------------------- /Core/Src/os_asm.s: -------------------------------------------------------------------------------- 1 | .syntax unified @ See https://sourceware.org/binutils/docs/as/ARM_002dInstruction_002dSet.html 2 | .cpu cortex-m4 3 | .fpu softvfp 4 | .thumb 5 | 6 | @ The .global directive gives the symbols external linkage. 7 | @ For clarity, the fn OSAsm_ThreadSwitch is exported as TIM2_IRQHandler, so that the vector table 8 | @ in startup.s doesn't need to be modified. 9 | .global OSAsm_Start 10 | .set TIM2_IRQHandler, OSAsm_ThreadSwitch 11 | .global TIM2_IRQHandler 12 | 13 | .extern RunPt 14 | .extern SchedlTimer_ClearITFlag 15 | .extern OS_Scheduler 16 | 17 | .section .text.OSAsm_Start 18 | .type OSAsm_Start, %function 19 | OSAsm_Start: 20 | CPSID I @ disable interrupts 21 | LDR R0, =RunPt @ R0 = &RunPt; // TCB_t** R0 = &RunPt 22 | LDR R1, [R0] @ R1 = *R0; // TCB_t* R1 = RunPt 23 | LDR SP, [R1] @ SP = *R1; // uint32_t SP = *(RunPt.sp) 24 | @ now we switched to the thread's stack, which we populated before 25 | POP {R4-R11} @ pop regs R4-R11 26 | POP {R0-R3} @ pop regs R0-R3 27 | POP {R12} @ pop reg R12 28 | POP {LR} @ discard LR 29 | POP {LR} @ pop PC to the link register (start location) 30 | POP {R1} @ discard PSR 31 | CPSIE I @ enable interrupts 32 | BX LR @ start first thread 33 | 34 | .section .text.OSAsm_ThreadSwitch 35 | .type OSAsm_ThreadSwitch, %function 36 | OSAsm_ThreadSwitch: 37 | @ save R0-R3,R12,LR,PC,PSR 38 | CPSID I @ prevent interrupt during context-switch 39 | PUSH {R4-R11} @ save remaining regs R4-R11 40 | LDR R0, =RunPt @ R0 = &RunPt; // TCB_t** R0 = &RunPt 41 | LDR R1, [R0] @ R1 = *R0; // TCB_t* R1 = RunPt 42 | STR SP, [R1] @ *R1 = SP; // *(RunPt.sp) = SP 43 | 44 | PUSH {R0, LR} @ push R0 and LR, so that fn calls don't loose them 45 | BL SchedlTimer_ClearITFlag @ clear SchedlTimer interrupt flag 46 | BL OS_Scheduler @ call OS_Scheduler, RunPt is updated 47 | POP {R0, LR} @ restore R0 and LR 48 | 49 | LDR R1, [R0] @ R1 = *R0; // TCB_t* R1 = RunPt 50 | LDR SP, [R1] @ SP = *R1; // uint32_t SP = *(RunPt.sp) 51 | @ now we switched to the new thread's stack 52 | POP {R4-R11} @ restore regs R4-R11 53 | CPSIE I @ tasks run with interrupts enabled 54 | BX LR @ restore R0-R3,R12,LR,PC,PSR 55 | -------------------------------------------------------------------------------- /Core/Src/schedl_timer.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "schedl_timer.h" 6 | 7 | #include "iferr.h" 8 | #include "instrument_trigger.h" 9 | 10 | //================================================================================================== 11 | // DEFINES - MACROS 12 | //================================================================================================== 13 | 14 | /* The pin PB0 is used for monitoring the interval between context-switches with the logic analyzer */ 15 | InstrumentTrigger_Create(B, 0); 16 | 17 | //================================================================================================== 18 | // ENUMS - STRUCTS - TYPEDEFS 19 | //================================================================================================== 20 | 21 | //================================================================================================== 22 | // STATIC PROTOTYPES 23 | //================================================================================================== 24 | 25 | //================================================================================================== 26 | // STATIC VARIABLES 27 | //================================================================================================== 28 | 29 | static TIM_HandleTypeDef TIMHandle; 30 | 31 | //================================================================================================== 32 | // GLOBAL FUNCTIONS 33 | //================================================================================================== 34 | 35 | void SchedlTimer_Init(uint32_t reload_frequency_hz) 36 | { 37 | /* Compute the prescaler value to have TIM2 counter clock equal to 1 KHz */ 38 | uint32_t prescaler_divisions = 10000; 39 | uint32_t period = prescaler_divisions / reload_frequency_hz; 40 | assert_or_panic(period > 1); 41 | 42 | TIMHandle.Instance = SchedlTimer_Instance; 43 | TIMHandle.Init.Prescaler = (SystemCoreClock / prescaler_divisions) - 1; /* Off by 1 because it’s 0-based */ 44 | TIMHandle.Init.Period = period - 1; /* Off by 1 because it’s 0-based */ 45 | TIMHandle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 46 | TIMHandle.Init.CounterMode = TIM_COUNTERMODE_DOWN; 47 | IFERR_PANIC(HAL_TIM_Base_Init(&TIMHandle)); 48 | InstrumentTriggerPB0_Init(); 49 | } 50 | 51 | void SchedlTimer_Start(void) 52 | { 53 | IFERR_PANIC(HAL_TIM_Base_Start_IT(&TIMHandle)); 54 | } 55 | 56 | void SchedlTimer_ClearITFlag(void) 57 | { 58 | __HAL_TIM_CLEAR_IT(&TIMHandle, TIM_IT_UPDATE); 59 | InstrumentTriggerPB0_Toggle(); 60 | } 61 | 62 | void SchedlTimer_ResetCounter(void) 63 | { 64 | __HAL_TIM_SET_COUNTER(&TIMHandle, 0); 65 | /* Don't return from this fn before the interrupt triggered */ 66 | HAL_Delay(1); 67 | } 68 | 69 | //================================================================================================== 70 | // STATIC FUNCTIONS 71 | //================================================================================================== 72 | -------------------------------------------------------------------------------- /Core/Src/stm32f3xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "stm32f3xx_hal_msp.h" 6 | 7 | #include "schedl_timer.h" 8 | 9 | //================================================================================================== 10 | // GLOBAL FUNCTIONS 11 | //================================================================================================== 12 | 13 | void HAL_MspInit(void) 14 | { 15 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 16 | __HAL_RCC_PWR_CLK_ENABLE(); 17 | HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); 18 | } 19 | 20 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) 21 | { 22 | SchedlTimer_ClkEnable(); 23 | HAL_NVIC_SetPriority(SchedlTimer_IRQn, SchedlTimer_IRQPreemptPriority, SchedlTimer_IRQSubPriority); 24 | HAL_NVIC_EnableIRQ(SchedlTimer_IRQn); 25 | } 26 | -------------------------------------------------------------------------------- /Core/Src/stm32f3xx_it.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "stm32f3xx_it.h" 6 | 7 | #include "onboard_user_button.h" 8 | #include "os.h" 9 | 10 | #include "core_cm4.h" 11 | #include "stm32f3xx_hal.h" 12 | #include 13 | 14 | //================================================================================================== 15 | // ENUMS - STRUCTS - TYPEDEFS 16 | //================================================================================================== 17 | 18 | typedef struct 19 | { 20 | uint32_t CFSReg; /* Configurable Fault Status Register */ 21 | uint16_t UFSReg; /* Usage Fault Status Registers */ 22 | uint8_t BFSReg; /* Bus Fault Status Registers */ 23 | uint8_t MMFSReg; /* Memory Manage Fault Status Registers */ 24 | uint32_t HFSReg; /* HardFault Status Register */ 25 | 26 | /* Usage Faults */ 27 | bool DIVBYZERO; 28 | bool UNALIGNED; 29 | bool NOCP; 30 | bool INVPC; 31 | bool INVSTATE; 32 | bool UNDEFINSTR; 33 | 34 | /* Bus Faults */ 35 | bool BFARVALID; 36 | bool LSPERR; 37 | bool STKERR; 38 | bool UNSTKERR; 39 | bool IMPRECISERR; 40 | bool PRECISERR; 41 | bool IBUSERR; 42 | 43 | /* MemManage Faults */ 44 | bool MMARVALID; 45 | bool MLSPERR; 46 | bool MSTKERR; 47 | bool MUNSTKERR; 48 | bool DACCVIOL; 49 | bool IACCVIOL; 50 | 51 | /* Hard Faults */ 52 | bool DEBUGEVT; 53 | bool FORCED; 54 | bool VECTTBL; 55 | } HardFaultStatusRegisters_t; 56 | 57 | //================================================================================================== 58 | // STATIC PROTOTYPES 59 | //================================================================================================== 60 | 61 | static void InspectHardFault(void); 62 | 63 | //================================================================================================== 64 | // STATIC VARIABLES 65 | //================================================================================================== 66 | 67 | static __USED HardFaultStatusRegisters_t HardFaultStatusRegs; 68 | 69 | //================================================================================================== 70 | // CORTEX-M4 PROCESSOR INTERRUPTION AND EXCEPTION HANDLERS 71 | //================================================================================================== 72 | 73 | void NMI_Handler(void) 74 | { 75 | while (1) 76 | { 77 | } 78 | } 79 | 80 | void HardFault_Handler(void) 81 | { 82 | /* To determine what caused the fault, inspect the global variable HardFaultStatusRegs. 83 | * Useful article: https://interrupt.memfault.com/blog/cortex-m-fault-debug */ 84 | InspectHardFault(); 85 | while (1) 86 | { 87 | } 88 | } 89 | 90 | void MemManage_Handler(void) 91 | { 92 | while (1) 93 | { 94 | } 95 | } 96 | 97 | void BusFault_Handler(void) 98 | { 99 | while (1) 100 | { 101 | } 102 | } 103 | 104 | void UsageFault_Handler(void) 105 | { 106 | while (1) 107 | { 108 | } 109 | } 110 | 111 | void SVC_Handler(void) 112 | { 113 | } 114 | 115 | void DebugMon_Handler(void) 116 | { 117 | } 118 | 119 | void PendSV_Handler(void) 120 | { 121 | } 122 | 123 | void SysTick_Handler(void) 124 | { 125 | HAL_IncTick(); 126 | OS_DecrementTCBsSleepDuration(); 127 | } 128 | 129 | //================================================================================================== 130 | // STM32F3xx PERIPHERAL INTERRUPT HANDLERS 131 | // For the available peripheral interrupt handler names, 132 | // please refer to the startup file (startup_stm32f3xx.s). 133 | //================================================================================================== 134 | 135 | void EXTI0_IRQHandler(void) 136 | { 137 | OnboardUserButton_IRQHandler(); 138 | } 139 | 140 | //================================================================================================== 141 | // STATIC FUNCTIONS 142 | //================================================================================================== 143 | 144 | static void InspectHardFault(void) 145 | { 146 | uint32_t *cfsr_addr = (uint32_t *)0xE000ED28; 147 | uint32_t cfsr = *cfsr_addr; 148 | 149 | uint32_t *hfsr_addr = (uint32_t *)0xE000ED2C; 150 | uint32_t hfsr = *hfsr_addr; 151 | 152 | HardFaultStatusRegs = (HardFaultStatusRegisters_t){ 153 | .CFSReg = cfsr, 154 | .UFSReg = cfsr >> SCB_CFSR_USGFAULTSR_Pos, 155 | .BFSReg = cfsr >> SCB_CFSR_BUSFAULTSR_Pos, 156 | .MMFSReg = cfsr >> SCB_CFSR_MEMFAULTSR_Pos, 157 | .HFSReg = hfsr, 158 | 159 | /* Usage Faults */ 160 | .DIVBYZERO = cfsr & SCB_CFSR_DIVBYZERO_Msk, 161 | .UNALIGNED = cfsr & SCB_CFSR_UNALIGNED_Msk, 162 | .NOCP = cfsr & SCB_CFSR_NOCP_Msk, 163 | .INVPC = cfsr & SCB_CFSR_INVPC_Msk, 164 | .INVSTATE = cfsr & SCB_CFSR_INVSTATE_Msk, 165 | .UNDEFINSTR = cfsr & SCB_CFSR_UNDEFINSTR_Msk, 166 | 167 | /* Bus Faults */ 168 | .BFARVALID = cfsr & SCB_CFSR_BFARVALID_Msk, 169 | .LSPERR = cfsr & SCB_CFSR_LSPERR_Msk, 170 | .STKERR = cfsr & SCB_CFSR_STKERR_Msk, 171 | .UNSTKERR = cfsr & SCB_CFSR_UNSTKERR_Msk, 172 | .IMPRECISERR = cfsr & SCB_CFSR_IMPRECISERR_Msk, 173 | .PRECISERR = cfsr & SCB_CFSR_PRECISERR_Msk, 174 | .IBUSERR = cfsr & SCB_CFSR_IBUSERR_Msk, 175 | 176 | /* MemManage Faults */ 177 | .MMARVALID = cfsr & SCB_CFSR_MMARVALID_Msk, 178 | .MLSPERR = cfsr & SCB_CFSR_MLSPERR_Msk, 179 | .MSTKERR = cfsr & SCB_CFSR_MSTKERR_Msk, 180 | .MUNSTKERR = cfsr & SCB_CFSR_MUNSTKERR_Msk, 181 | .DACCVIOL = cfsr & SCB_CFSR_DACCVIOL_Msk, 182 | .IACCVIOL = cfsr & SCB_CFSR_IACCVIOL_Msk, 183 | 184 | /* Hard Faults */ 185 | .DEBUGEVT = hfsr & SCB_HFSR_DEBUGEVT_Msk, 186 | .FORCED = hfsr & SCB_HFSR_FORCED_Msk, 187 | .VECTTBL = hfsr & SCB_HFSR_VECTTBL_Msk, 188 | }; 189 | } 190 | -------------------------------------------------------------------------------- /Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | 33 | 34 | /* Variables */ 35 | extern int __io_putchar(int ch) __attribute__((weak)); 36 | extern int __io_getchar(void) __attribute__((weak)); 37 | 38 | 39 | char *__env[1] = { 0 }; 40 | char **environ = __env; 41 | 42 | 43 | /* Functions */ 44 | void initialise_monitor_handles() 45 | { 46 | } 47 | 48 | int _getpid(void) 49 | { 50 | return 1; 51 | } 52 | 53 | int _kill(int pid, int sig) 54 | { 55 | errno = EINVAL; 56 | return -1; 57 | } 58 | 59 | void _exit (int status) 60 | { 61 | _kill(status, -1); 62 | while (1) {} /* Make sure we hang here */ 63 | } 64 | 65 | __attribute__((weak)) int _read(int file, char *ptr, int len) 66 | { 67 | int DataIdx; 68 | 69 | for (DataIdx = 0; DataIdx < len; DataIdx++) 70 | { 71 | *ptr++ = __io_getchar(); 72 | } 73 | 74 | return len; 75 | } 76 | 77 | __attribute__((weak)) int _write(int file, char *ptr, int len) 78 | { 79 | int DataIdx; 80 | 81 | for (DataIdx = 0; DataIdx < len; DataIdx++) 82 | { 83 | __io_putchar(*ptr++); 84 | } 85 | return len; 86 | } 87 | 88 | int _close(int file) 89 | { 90 | return -1; 91 | } 92 | 93 | 94 | int _fstat(int file, struct stat *st) 95 | { 96 | st->st_mode = S_IFCHR; 97 | return 0; 98 | } 99 | 100 | int _isatty(int file) 101 | { 102 | return 1; 103 | } 104 | 105 | int _lseek(int file, int ptr, int dir) 106 | { 107 | return 0; 108 | } 109 | 110 | int _open(char *path, int flags, ...) 111 | { 112 | /* Pretend like we always fail */ 113 | return -1; 114 | } 115 | 116 | int _wait(int *status) 117 | { 118 | errno = ECHILD; 119 | return -1; 120 | } 121 | 122 | int _unlink(char *name) 123 | { 124 | errno = ENOENT; 125 | return -1; 126 | } 127 | 128 | int _times(struct tms *buf) 129 | { 130 | return -1; 131 | } 132 | 133 | int _stat(char *file, struct stat *st) 134 | { 135 | st->st_mode = S_IFCHR; 136 | return 0; 137 | } 138 | 139 | int _link(char *old, char *new) 140 | { 141 | errno = EMLINK; 142 | return -1; 143 | } 144 | 145 | int _fork(void) 146 | { 147 | errno = EAGAIN; 148 | return -1; 149 | } 150 | 151 | int _execve(char *name, char **argv, char **env) 152 | { 153 | errno = ENOMEM; 154 | return -1; 155 | } 156 | -------------------------------------------------------------------------------- /Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * Copyright (c) 2022 STMicroelectronics. 14 | * All rights reserved. 15 | * 16 | * This software is licensed under terms that can be found in the LICENSE file 17 | * in the root directory of this software component. 18 | * If no LICENSE file comes with this software, it is provided AS-IS. 19 | * 20 | ****************************************************************************** 21 | */ 22 | 23 | /* Includes */ 24 | #include 25 | #include 26 | 27 | /** 28 | * Pointer to the current high watermark of the heap usage 29 | */ 30 | static uint8_t *__sbrk_heap_end = NULL; 31 | 32 | /** 33 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 34 | * and others from the C library 35 | * 36 | * @verbatim 37 | * ############################################################################ 38 | * # .data # .bss # newlib heap # MSP stack # 39 | * # # # # Reserved by _Min_Stack_Size # 40 | * ############################################################################ 41 | * ^-- RAM start ^-- _end _estack, RAM end --^ 42 | * @endverbatim 43 | * 44 | * This implementation starts allocating at the '_end' linker symbol 45 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 46 | * The implementation considers '_estack' linker symbol to be RAM end 47 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 48 | * reserved size, please increase the '_Min_Stack_Size'. 49 | * 50 | * @param incr Memory size 51 | * @return Pointer to allocated memory 52 | */ 53 | void *_sbrk(ptrdiff_t incr) 54 | { 55 | extern uint8_t _end; /* Symbol defined in the linker script */ 56 | extern uint8_t _estack; /* Symbol defined in the linker script */ 57 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 58 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 59 | const uint8_t *max_heap = (uint8_t *)stack_limit; 60 | uint8_t *prev_heap_end; 61 | 62 | /* Initialize heap end at first call */ 63 | if (NULL == __sbrk_heap_end) 64 | { 65 | __sbrk_heap_end = &_end; 66 | } 67 | 68 | /* Protect heap from growing into the reserved MSP stack */ 69 | if (__sbrk_heap_end + incr > max_heap) 70 | { 71 | errno = ENOMEM; 72 | return (void *)-1; 73 | } 74 | 75 | prev_heap_end = __sbrk_heap_end; 76 | __sbrk_heap_end += incr; 77 | 78 | return (void *)prev_heap_end; 79 | } 80 | -------------------------------------------------------------------------------- /Core/Src/system_stm32f3xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f3xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. 6 | * 7 | * 1. This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f3xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. 22 | * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to 23 | * configure the system clock before to branch to main program. 24 | * 25 | * 3. This file configures the system clock as follows: 26 | *============================================================================= 27 | * Supported STM32F3xx device 28 | *----------------------------------------------------------------------------- 29 | * System Clock source | HSI 30 | *----------------------------------------------------------------------------- 31 | * SYSCLK(Hz) | 8000000 32 | *----------------------------------------------------------------------------- 33 | * HCLK(Hz) | 8000000 34 | *----------------------------------------------------------------------------- 35 | * AHB Prescaler | 1 36 | *----------------------------------------------------------------------------- 37 | * APB2 Prescaler | 1 38 | *----------------------------------------------------------------------------- 39 | * APB1 Prescaler | 1 40 | *----------------------------------------------------------------------------- 41 | * USB Clock | DISABLE 42 | *----------------------------------------------------------------------------- 43 | *============================================================================= 44 | ****************************************************************************** 45 | * @attention 46 | * 47 | *

© Copyright (c) 2016 STMicroelectronics. 48 | * All rights reserved.

49 | * 50 | * This software component is licensed by ST under BSD 3-Clause license, 51 | * the "License"; You may not use this file except in compliance with the 52 | * License. You may obtain a copy of the License at: 53 | * opensource.org/licenses/BSD-3-Clause 54 | * 55 | ****************************************************************************** 56 | */ 57 | 58 | /** @addtogroup CMSIS 59 | * @{ 60 | */ 61 | 62 | /** @addtogroup stm32f3xx_system 63 | * @{ 64 | */ 65 | 66 | /** @addtogroup STM32F3xx_System_Private_Includes 67 | * @{ 68 | */ 69 | 70 | #include "stm32f3xx.h" 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @addtogroup STM32F3xx_System_Private_TypesDefinitions 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @addtogroup STM32F3xx_System_Private_Defines 85 | * @{ 86 | */ 87 | #if !defined (HSE_VALUE) 88 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. 89 | This value can be provided and adapted by the user application. */ 90 | #endif /* HSE_VALUE */ 91 | 92 | #if !defined (HSI_VALUE) 93 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. 94 | This value can be provided and adapted by the user application. */ 95 | #endif /* HSI_VALUE */ 96 | 97 | /* Note: Following vector table addresses must be defined in line with linker 98 | configuration. */ 99 | /*!< Uncomment the following line if you need to relocate the vector table 100 | anywhere in Flash or Sram, else the vector table is kept at the automatic 101 | remap of boot address selected */ 102 | /* #define USER_VECT_TAB_ADDRESS */ 103 | 104 | #if defined(USER_VECT_TAB_ADDRESS) 105 | /*!< Uncomment the following line if you need to relocate your vector Table 106 | in Sram else user remap will be done in Flash. */ 107 | /* #define VECT_TAB_SRAM */ 108 | #if defined(VECT_TAB_SRAM) 109 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. 110 | This value must be a multiple of 0x200. */ 111 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 112 | This value must be a multiple of 0x200. */ 113 | #else 114 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 115 | This value must be a multiple of 0x200. */ 116 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 117 | This value must be a multiple of 0x200. */ 118 | #endif /* VECT_TAB_SRAM */ 119 | #endif /* USER_VECT_TAB_ADDRESS */ 120 | 121 | /******************************************************************************/ 122 | /** 123 | * @} 124 | */ 125 | 126 | /** @addtogroup STM32F3xx_System_Private_Macros 127 | * @{ 128 | */ 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /** @addtogroup STM32F3xx_System_Private_Variables 135 | * @{ 136 | */ 137 | /* This variable is updated in three ways: 138 | 1) by calling CMSIS function SystemCoreClockUpdate() 139 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 140 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 141 | Note: If you use this function to configure the system clock there is no need to 142 | call the 2 first functions listed above, since SystemCoreClock variable is 143 | updated automatically. 144 | */ 145 | uint32_t SystemCoreClock = 8000000; 146 | 147 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 148 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 149 | 150 | /** 151 | * @} 152 | */ 153 | 154 | /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes 155 | * @{ 156 | */ 157 | 158 | /** 159 | * @} 160 | */ 161 | 162 | /** @addtogroup STM32F3xx_System_Private_Functions 163 | * @{ 164 | */ 165 | 166 | /** 167 | * @brief Setup the microcontroller system 168 | * @param None 169 | * @retval None 170 | */ 171 | void SystemInit(void) 172 | { 173 | /* FPU settings --------------------------------------------------------------*/ 174 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 175 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 176 | #endif 177 | 178 | /* Configure the Vector Table location -------------------------------------*/ 179 | #if defined(USER_VECT_TAB_ADDRESS) 180 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ 181 | #endif /* USER_VECT_TAB_ADDRESS */ 182 | } 183 | 184 | /** 185 | * @brief Update SystemCoreClock variable according to Clock Register Values. 186 | * The SystemCoreClock variable contains the core clock (HCLK), it can 187 | * be used by the user application to setup the SysTick timer or configure 188 | * other parameters. 189 | * 190 | * @note Each time the core clock (HCLK) changes, this function must be called 191 | * to update SystemCoreClock variable value. Otherwise, any configuration 192 | * based on this variable will be incorrect. 193 | * 194 | * @note - The system frequency computed by this function is not the real 195 | * frequency in the chip. It is calculated based on the predefined 196 | * constant and the selected clock source: 197 | * 198 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 199 | * 200 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 201 | * 202 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 203 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 204 | * 205 | * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value 206 | * 8 MHz) but the real value may vary depending on the variations 207 | * in voltage and temperature. 208 | * 209 | * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value 210 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 211 | * frequency of the crystal used. Otherwise, this function may 212 | * have wrong result. 213 | * 214 | * - The result of this function could be not correct when using fractional 215 | * value for HSE crystal. 216 | * 217 | * @param None 218 | * @retval None 219 | */ 220 | void SystemCoreClockUpdate (void) 221 | { 222 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; 223 | 224 | /* Get SYSCLK source -------------------------------------------------------*/ 225 | tmp = RCC->CFGR & RCC_CFGR_SWS; 226 | 227 | switch (tmp) 228 | { 229 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ 230 | SystemCoreClock = HSI_VALUE; 231 | break; 232 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ 233 | SystemCoreClock = HSE_VALUE; 234 | break; 235 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ 236 | /* Get PLL clock source and multiplication factor ----------------------*/ 237 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; 238 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 239 | pllmull = ( pllmull >> 18) + 2; 240 | 241 | #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) 242 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; 243 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) 244 | { 245 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 246 | SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; 247 | } 248 | else 249 | { 250 | /* HSI oscillator clock selected as PREDIV1 clock entry */ 251 | SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; 252 | } 253 | #else 254 | if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) 255 | { 256 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 257 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 258 | } 259 | else 260 | { 261 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; 262 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 263 | SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; 264 | } 265 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ 266 | break; 267 | default: /* HSI used as system clock */ 268 | SystemCoreClock = HSI_VALUE; 269 | break; 270 | } 271 | /* Compute HCLK clock frequency ----------------*/ 272 | /* Get HCLK prescaler */ 273 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 274 | /* HCLK clock frequency */ 275 | SystemCoreClock >>= tmp; 276 | } 277 | 278 | /** 279 | * @} 280 | */ 281 | 282 | /** 283 | * @} 284 | */ 285 | 286 | /** 287 | * @} 288 | */ 289 | 290 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 291 | -------------------------------------------------------------------------------- /Core/Src/user_tasks.c: -------------------------------------------------------------------------------- 1 | //================================================================================================== 2 | // INCLUDES 3 | //================================================================================================== 4 | 5 | #include "user_tasks.h" 6 | 7 | #include "instrument_trigger.h" 8 | #include "os.h" 9 | 10 | #include "stm32f3xx_hal.h" 11 | #include 12 | 13 | //================================================================================================== 14 | // DEFINES - MACROS 15 | //================================================================================================== 16 | 17 | /* See instrument_trigger.h for the available LEDs on the STM32F3DISCOVERY board */ 18 | InstrumentTrigger_Create(E, 11); /* UserTask_0 */ 19 | InstrumentTrigger_Create(E, 12); /* UserTask_1 */ 20 | InstrumentTrigger_Create(E, 13); /* UserTask_2 */ 21 | InstrumentTrigger_Create(E, 14); /* UserTask_3 */ 22 | 23 | //================================================================================================== 24 | // ENUMS - STRUCTS - TYPEDEFS 25 | //================================================================================================== 26 | 27 | //================================================================================================== 28 | // STATIC PROTOTYPES 29 | //================================================================================================== 30 | 31 | //================================================================================================== 32 | // STATIC VARIABLES 33 | //================================================================================================== 34 | 35 | //================================================================================================== 36 | // GLOBAL FUNCTIONS 37 | //================================================================================================== 38 | 39 | void UserTask_0(void) 40 | { 41 | InstrumentTriggerPE11_Init(); 42 | uint32_t count = 0; 43 | while (1) 44 | { 45 | InstrumentTriggerPE11_Toggle(); 46 | HAL_Delay(60); 47 | count++; 48 | if (count == 100) 49 | { 50 | OS_Thread_Create(UserTask_3, OS_SCHEDL_PRIO_MAIN_THREAD, "UserTask_3"); 51 | } 52 | if (count == 200) 53 | { 54 | InstrumentTriggerPE11_Reset(); 55 | OS_Thread_Kill(); 56 | } 57 | } 58 | } 59 | 60 | void UserTask_1(void) 61 | { 62 | InstrumentTriggerPE12_Init(); 63 | while (1) 64 | { 65 | for (uint32_t i = 0; i <= 12; i++) 66 | { 67 | InstrumentTriggerPE12_Toggle(); 68 | HAL_Delay(50); 69 | } 70 | OS_Thread_Suspend(); 71 | } 72 | } 73 | 74 | void UserTask_2(void) 75 | { 76 | InstrumentTriggerPE13_Init(); 77 | uint32_t count = 0; 78 | while (1) 79 | { 80 | InstrumentTriggerPE13_Toggle(); 81 | count++; 82 | if (count % 35 == 0) 83 | OS_Thread_Sleep(4500); 84 | else 85 | HAL_Delay(70); 86 | } 87 | } 88 | 89 | void UserTask_3(void) 90 | { 91 | InstrumentTriggerPE14_Init(); 92 | while (1) 93 | { 94 | InstrumentTriggerPE14_Toggle(); 95 | HAL_Delay(60); 96 | } 97 | } 98 | 99 | //================================================================================================== 100 | // STATIC FUNCTIONS 101 | //================================================================================================== 102 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f3xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32f3xx_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32F3XX_H 32 | #define __SYSTEM_STM32F3XX_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32F3xx_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32F3xx_System_Exported_types 48 | * @{ 49 | */ 50 | /* This variable is updated in three ways: 51 | 1) by calling CMSIS function SystemCoreClockUpdate() 52 | 3) by calling HAL API function HAL_RCC_GetHCLKFreq() 53 | 3) by calling HAL API function HAL_RCC_ClockConfig() 54 | Note: If you use this function to configure the system clock; then there 55 | is no need to call the 2 first functions listed above, since SystemCoreClock 56 | variable is updated automatically. 57 | */ 58 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 59 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 60 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 61 | 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F3xx_System_Exported_Constants 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F3xx_System_Exported_Macros 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @addtogroup STM32F3xx_System_Exported_Functions 84 | * @{ 85 | */ 86 | 87 | extern void SystemInit(void); 88 | extern void SystemCoreClockUpdate(void); 89 | /** 90 | * @} 91 | */ 92 | 93 | #ifdef __cplusplus 94 | } 95 | #endif 96 | 97 | #endif /*__SYSTEM_STM32F3XX_H */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 107 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Device/ST/STM32F3xx/License.md: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. 10 | 11 | "Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. 12 | 13 | "Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. 14 | 15 | "You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License. 16 | 17 | "Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files. 18 | 19 | "Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types. 20 | 21 | "Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below). 22 | 23 | "Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof. 24 | 25 | "Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution." 26 | 27 | "Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work. 28 | 29 | 2. Grant of Copyright License. 30 | 31 | Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form. 32 | 33 | 3. Grant of Patent License. 34 | 35 | Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed. 36 | 37 | 4. Redistribution. 38 | 39 | You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions: 40 | 1.You must give any other recipients of the Work or Derivative Works a copy of this License; and 41 | 2.You must cause any modified files to carry prominent notices stating that You changed the files; and 42 | 3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and 43 | 4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License. 44 | 45 | You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License. 46 | 47 | 5. Submission of Contributions. 48 | 49 | Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions. 50 | 51 | 6. Trademarks. 52 | 53 | This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file. 54 | 55 | 7. Disclaimer of Warranty. 56 | 57 | Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License. 58 | 59 | 8. Limitation of Liability. 60 | 61 | In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages. 62 | 63 | 9. Accepting Warranty or Additional Liability. 64 | 65 | While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. 66 | 67 | END OF TERMS AND CONDITIONS 68 | 69 | APPENDIX: 70 | 71 | Copyright [2019] [STMicroelectronics] 72 | 73 | Licensed under the Apache License, Version 2.0 (the "License"); 74 | you may not use this file except in compliance with the License. 75 | You may obtain a copy of the License at 76 | 77 | http://www.apache.org/licenses/LICENSE-2.0 78 | 79 | Unless required by applicable law or agreed to in writing, software 80 | distributed under the License is distributed on an "AS IS" BASIS, 81 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 82 | See the License for the specific language governing permissions and 83 | limitations under the License. 84 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Drivers/CMSIS/LICENSE.txt: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, 10 | and distribution as defined by Sections 1 through 9 of this document. 11 | 12 | "Licensor" shall mean the copyright owner or entity authorized by 13 | the copyright owner that is granting the License. 14 | 15 | "Legal Entity" shall mean the union of the acting entity and all 16 | other entities that control, are controlled by, or are under common 17 | control with that entity. For the purposes of this definition, 18 | "control" means (i) the power, direct or indirect, to cause the 19 | direction or management of such entity, whether by contract or 20 | otherwise, or (ii) ownership of fifty percent (50%) or more of the 21 | outstanding shares, or (iii) beneficial ownership of such entity. 22 | 23 | "You" (or "Your") shall mean an individual or Legal Entity 24 | exercising permissions granted by this License. 25 | 26 | "Source" form shall mean the preferred form for making modifications, 27 | including but not limited to software source code, documentation 28 | source, and configuration files. 29 | 30 | "Object" form shall mean any form resulting from mechanical 31 | transformation or translation of a Source form, including but 32 | not limited to compiled object code, generated documentation, 33 | and conversions to other media types. 34 | 35 | "Work" shall mean the work of authorship, whether in Source or 36 | Object form, made available under the License, as indicated by a 37 | copyright notice that is included in or attached to the work 38 | (an example is provided in the Appendix below). 39 | 40 | "Derivative Works" shall mean any work, whether in Source or Object 41 | form, that is based on (or derived from) the Work and for which the 42 | editorial revisions, annotations, elaborations, or other modifications 43 | represent, as a whole, an original work of authorship. For the purposes 44 | of this License, Derivative Works shall not include works that remain 45 | separable from, or merely link (or bind by name) to the interfaces of, 46 | the Work and Derivative Works thereof. 47 | 48 | "Contribution" shall mean any work of authorship, including 49 | the original version of the Work and any modifications or additions 50 | to that Work or Derivative Works thereof, that is intentionally 51 | submitted to Licensor for inclusion in the Work by the copyright owner 52 | or by an individual or Legal Entity authorized to submit on behalf of 53 | the copyright owner. For the purposes of this definition, "submitted" 54 | means any form of electronic, verbal, or written communication sent 55 | to the Licensor or its representatives, including but not limited to 56 | communication on electronic mailing lists, source code control systems, 57 | and issue tracking systems that are managed by, or on behalf of, the 58 | Licensor for the purpose of discussing and improving the Work, but 59 | excluding communication that is conspicuously marked or otherwise 60 | designated in writing by the copyright owner as "Not a Contribution." 61 | 62 | "Contributor" shall mean Licensor and any individual or Legal Entity 63 | on behalf of whom a Contribution has been received by Licensor and 64 | subsequently incorporated within the Work. 65 | 66 | 2. Grant of Copyright License. Subject to the terms and conditions of 67 | this License, each Contributor hereby grants to You a perpetual, 68 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 69 | copyright license to reproduce, prepare Derivative Works of, 70 | publicly display, publicly perform, sublicense, and distribute the 71 | Work and such Derivative Works in Source or Object form. 72 | 73 | 3. Grant of Patent License. Subject to the terms and conditions of 74 | this License, each Contributor hereby grants to You a perpetual, 75 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 76 | (except as stated in this section) patent license to make, have made, 77 | use, offer to sell, sell, import, and otherwise transfer the Work, 78 | where such license applies only to those patent claims licensable 79 | by such Contributor that are necessarily infringed by their 80 | Contribution(s) alone or by combination of their Contribution(s) 81 | with the Work to which such Contribution(s) was submitted. If You 82 | institute patent litigation against any entity (including a 83 | cross-claim or counterclaim in a lawsuit) alleging that the Work 84 | or a Contribution incorporated within the Work constitutes direct 85 | or contributory patent infringement, then any patent licenses 86 | granted to You under this License for that Work shall terminate 87 | as of the date such litigation is filed. 88 | 89 | 4. Redistribution. You may reproduce and distribute copies of the 90 | Work or Derivative Works thereof in any medium, with or without 91 | modifications, and in Source or Object form, provided that You 92 | meet the following conditions: 93 | 94 | (a) You must give any other recipients of the Work or 95 | Derivative Works a copy of this License; and 96 | 97 | (b) You must cause any modified files to carry prominent notices 98 | stating that You changed the files; and 99 | 100 | (c) You must retain, in the Source form of any Derivative Works 101 | that You distribute, all copyright, patent, trademark, and 102 | attribution notices from the Source form of the Work, 103 | excluding those notices that do not pertain to any part of 104 | the Derivative Works; and 105 | 106 | (d) If the Work includes a "NOTICE" text file as part of its 107 | distribution, then any Derivative Works that You distribute must 108 | include a readable copy of the attribution notices contained 109 | within such NOTICE file, excluding those notices that do not 110 | pertain to any part of the Derivative Works, in at least one 111 | of the following places: within a NOTICE text file distributed 112 | as part of the Derivative Works; within the Source form or 113 | documentation, if provided along with the Derivative Works; or, 114 | within a display generated by the Derivative Works, if and 115 | wherever such third-party notices normally appear. The contents 116 | of the NOTICE file are for informational purposes only and 117 | do not modify the License. You may add Your own attribution 118 | notices within Derivative Works that You distribute, alongside 119 | or as an addendum to the NOTICE text from the Work, provided 120 | that such additional attribution notices cannot be construed 121 | as modifying the License. 122 | 123 | You may add Your own copyright statement to Your modifications and 124 | may provide additional or different license terms and conditions 125 | for use, reproduction, or distribution of Your modifications, or 126 | for any such Derivative Works as a whole, provided Your use, 127 | reproduction, and distribution of the Work otherwise complies with 128 | the conditions stated in this License. 129 | 130 | 5. Submission of Contributions. Unless You explicitly state otherwise, 131 | any Contribution intentionally submitted for inclusion in the Work 132 | by You to the Licensor shall be under the terms and conditions of 133 | this License, without any additional terms or conditions. 134 | Notwithstanding the above, nothing herein shall supersede or modify 135 | the terms of any separate license agreement you may have executed 136 | with Licensor regarding such Contributions. 137 | 138 | 6. Trademarks. This License does not grant permission to use the trade 139 | names, trademarks, service marks, or product names of the Licensor, 140 | except as required for reasonable and customary use in describing the 141 | origin of the Work and reproducing the content of the NOTICE file. 142 | 143 | 7. Disclaimer of Warranty. Unless required by applicable law or 144 | agreed to in writing, Licensor provides the Work (and each 145 | Contributor provides its Contributions) on an "AS IS" BASIS, 146 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 147 | implied, including, without limitation, any warranties or conditions 148 | of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A 149 | PARTICULAR PURPOSE. You are solely responsible for determining the 150 | appropriateness of using or redistributing the Work and assume any 151 | risks associated with Your exercise of permissions under this License. 152 | 153 | 8. Limitation of Liability. In no event and under no legal theory, 154 | whether in tort (including negligence), contract, or otherwise, 155 | unless required by applicable law (such as deliberate and grossly 156 | negligent acts) or agreed to in writing, shall any Contributor be 157 | liable to You for damages, including any direct, indirect, special, 158 | incidental, or consequential damages of any character arising as a 159 | result of this License or out of the use or inability to use the 160 | Work (including but not limited to damages for loss of goodwill, 161 | work stoppage, computer failure or malfunction, or any and all 162 | other commercial damages or losses), even if such Contributor 163 | has been advised of the possibility of such damages. 164 | 165 | 9. Accepting Warranty or Additional Liability. While redistributing 166 | the Work or Derivative Works thereof, You may choose to offer, 167 | and charge a fee for, acceptance of support, warranty, indemnity, 168 | or other liability obligations and/or rights consistent with this 169 | License. However, in accepting such obligations, You may act only 170 | on Your own behalf and on Your sole responsibility, not on behalf 171 | of any other Contributor, and only if You agree to indemnify, 172 | defend, and hold each Contributor harmless for any liability 173 | incurred by, or claims asserted against, such Contributor by reason 174 | of your accepting any such warranty or additional liability. 175 | 176 | END OF TERMS AND CONDITIONS 177 | 178 | APPENDIX: How to apply the Apache License to your work. 179 | 180 | To apply the Apache License to your work, attach the following 181 | boilerplate notice, with the fields enclosed by brackets "{}" 182 | replaced with your own identifying information. (Don't include 183 | the brackets!) The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright {yyyy} {name of copyright owner} 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2016 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F3xx_HAL_DEF 23 | #define __STM32F3xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f3xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00U, 42 | HAL_ERROR = 0x01U, 43 | HAL_BUSY = 0x02U, 44 | HAL_TIMEOUT = 0x03 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00U, 53 | HAL_LOCKED = 0x01 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macro ------------------------------------------------------------*/ 57 | 58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 59 | 60 | #define HAL_MAX_DELAY 0xFFFFFFFFU 61 | 62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT) 63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 64 | 65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ 66 | do{ \ 67 | (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ 68 | (__DMA_HANDLE_).Parent = (__HANDLE__); \ 69 | } while(0U) 70 | 71 | /** @brief Reset the Handle's State field. 72 | * @param __HANDLE__ specifies the Peripheral Handle. 73 | * @note This macro can be used for the following purpose: 74 | * - When the Handle is declared as local variable; before passing it as parameter 75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 76 | * to set to 0 the Handle's "State" field. 77 | * Otherwise, "State" field may have any random value and the first time the function 78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 79 | * (i.e. HAL_PPP_MspInit() will not be executed). 80 | * - When there is a need to reconfigure the low level hardware: instead of calling 81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 84 | * @retval None 85 | */ 86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 87 | 88 | #if (USE_RTOS == 1U) 89 | #error " USE_RTOS should be 0 in the current HAL release " 90 | #else 91 | #define __HAL_LOCK(__HANDLE__) \ 92 | do{ \ 93 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 94 | { \ 95 | return HAL_BUSY; \ 96 | } \ 97 | else \ 98 | { \ 99 | (__HANDLE__)->Lock = HAL_LOCKED; \ 100 | } \ 101 | }while (0U) 102 | 103 | #define __HAL_UNLOCK(__HANDLE__) \ 104 | do{ \ 105 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 106 | }while (0U) 107 | #endif /* USE_RTOS */ 108 | 109 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 110 | #ifndef __weak 111 | #define __weak __attribute__((weak)) 112 | #endif 113 | #ifndef __packed 114 | #define __packed __attribute__((packed)) 115 | #endif 116 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 117 | #ifndef __weak 118 | #define __weak __attribute__((weak)) 119 | #endif /* __weak */ 120 | #ifndef __packed 121 | #define __packed __attribute__((__packed__)) 122 | #endif /* __packed */ 123 | #endif /* __GNUC__ */ 124 | 125 | 126 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 127 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 128 | #ifndef __ALIGN_BEGIN 129 | #define __ALIGN_BEGIN 130 | #endif 131 | #ifndef __ALIGN_END 132 | #define __ALIGN_END __attribute__ ((aligned (4))) 133 | #endif 134 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 135 | #ifndef __ALIGN_END 136 | #define __ALIGN_END __attribute__ ((aligned (4))) 137 | #endif /* __ALIGN_END */ 138 | #ifndef __ALIGN_BEGIN 139 | #define __ALIGN_BEGIN 140 | #endif /* __ALIGN_BEGIN */ 141 | #else 142 | #ifndef __ALIGN_END 143 | #define __ALIGN_END 144 | #endif /* __ALIGN_END */ 145 | #ifndef __ALIGN_BEGIN 146 | #if defined (__CC_ARM) /* ARM Compiler V5*/ 147 | #define __ALIGN_BEGIN __align(4) 148 | #elif defined (__ICCARM__) /* IAR Compiler */ 149 | #define __ALIGN_BEGIN 150 | #endif /* __CC_ARM */ 151 | #endif /* __ALIGN_BEGIN */ 152 | #endif /* __GNUC__ */ 153 | 154 | /** 155 | * @brief __NOINLINE definition 156 | */ 157 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 158 | /* ARM V4/V5 and V6 & GNU Compiler 159 | ------------------------------- 160 | */ 161 | #define __NOINLINE __attribute__ ( (noinline) ) 162 | 163 | #elif defined ( __ICCARM__ ) 164 | /* ICCARM Compiler 165 | --------------- 166 | */ 167 | #define __NOINLINE _Pragma("optimize = no_inline") 168 | 169 | #endif 170 | 171 | #ifdef __cplusplus 172 | } 173 | #endif 174 | 175 | #endif /* ___STM32F3xx_HAL_DEF */ 176 | 177 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 178 | -------------------------------------------------------------------------------- /Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of Flash HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_FLASH_H 22 | #define __STM32F3xx_HAL_FLASH_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASH 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup FLASH_Private_Constants 40 | * @{ 41 | */ 42 | #define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ 43 | /** 44 | * @} 45 | */ 46 | 47 | /** @addtogroup FLASH_Private_Macros 48 | * @{ 49 | */ 50 | 51 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ 52 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ 53 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 54 | 55 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ 56 | ((__LATENCY__) == FLASH_LATENCY_1) || \ 57 | ((__LATENCY__) == FLASH_LATENCY_2)) 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /* Exported types ------------------------------------------------------------*/ 64 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @brief FLASH Procedure structure definition 70 | */ 71 | typedef enum 72 | { 73 | FLASH_PROC_NONE = 0U, 74 | FLASH_PROC_PAGEERASE = 1U, 75 | FLASH_PROC_MASSERASE = 2U, 76 | FLASH_PROC_PROGRAMHALFWORD = 3U, 77 | FLASH_PROC_PROGRAMWORD = 4U, 78 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U 79 | } FLASH_ProcedureTypeDef; 80 | 81 | /** 82 | * @brief FLASH handle Structure definition 83 | */ 84 | typedef struct 85 | { 86 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 87 | 88 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ 89 | 90 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ 91 | 92 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ 93 | 94 | HAL_LockTypeDef Lock; /*!< FLASH locking object */ 95 | 96 | __IO uint32_t ErrorCode; /*!< FLASH error code 97 | This parameter can be a value of @ref FLASH_Error_Codes */ 98 | } FLASH_ProcessTypeDef; 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /* Exported constants --------------------------------------------------------*/ 105 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 106 | * @{ 107 | */ 108 | 109 | /** @defgroup FLASH_Error_Codes FLASH Error Codes 110 | * @{ 111 | */ 112 | 113 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ 114 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ 115 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @defgroup FLASH_Type_Program FLASH Type Program 122 | * @{ 123 | */ 124 | #define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR |= FLASH_ACR_HLFCYA) 185 | 186 | /** 187 | * @brief Disable the FLASH half cycle access. 188 | * @retval None 189 | */ 190 | #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) 191 | 192 | /** 193 | * @} 194 | */ 195 | 196 | /** @defgroup FLASH_EM_Latency FLASH Latency 197 | * @brief macros to handle FLASH Latency 198 | * @{ 199 | */ 200 | 201 | /** 202 | * @brief Set the FLASH Latency. 203 | * @param __LATENCY__ FLASH Latency 204 | * This parameter can be one of the following values: 205 | * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle 206 | * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle 207 | * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles 208 | * @retval None 209 | */ 210 | #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) 211 | 212 | 213 | /** 214 | * @brief Get the FLASH Latency. 215 | * @retval FLASH Latency 216 | * This parameter can be one of the following values: 217 | * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle 218 | * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle 219 | * @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles 220 | */ 221 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 222 | 223 | /** 224 | * @} 225 | */ 226 | 227 | /** @defgroup FLASH_Prefetch FLASH Prefetch 228 | * @brief macros to handle FLASH Prefetch buffer 229 | * @{ 230 | */ 231 | /** 232 | * @brief Enable the FLASH prefetch buffer. 233 | * @retval None 234 | */ 235 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) 236 | 237 | /** 238 | * @brief Disable the FLASH prefetch buffer. 239 | * @retval None 240 | */ 241 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) 242 | 243 | /** 244 | * @} 245 | */ 246 | 247 | /** @defgroup FLASH_Interrupt FLASH Interrupts 248 | * @brief macros to handle FLASH interrupts 249 | * @{ 250 | */ 251 | 252 | /** 253 | * @brief Enable the specified FLASH interrupt. 254 | * @param __INTERRUPT__ FLASH interrupt 255 | * This parameter can be any combination of the following values: 256 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 257 | * @arg @ref FLASH_IT_ERR Error Interrupt 258 | * @retval none 259 | */ 260 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) 261 | 262 | /** 263 | * @brief Disable the specified FLASH interrupt. 264 | * @param __INTERRUPT__ FLASH interrupt 265 | * This parameter can be any combination of the following values: 266 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 267 | * @arg @ref FLASH_IT_ERR Error Interrupt 268 | * @retval none 269 | */ 270 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) 271 | 272 | /** 273 | * @brief Get the specified FLASH flag status. 274 | * @param __FLAG__ specifies the FLASH flag to check. 275 | * This parameter can be one of the following values: 276 | * @arg @ref FLASH_FLAG_BSY FLASH Busy flag 277 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 278 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 279 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag 280 | * @retval The new state of __FLAG__ (SET or RESET). 281 | */ 282 | #define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) 283 | 284 | /** 285 | * @brief Clear the specified FLASH flag. 286 | * @param __FLAG__ specifies the FLASH flags to clear. 287 | * This parameter can be any combination of the following values: 288 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 289 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 290 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag 291 | * @retval none 292 | */ 293 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /* Include FLASH HAL Extended module */ 304 | #include "stm32f3xx_hal_flash_ex.h" 305 | 306 | /* Exported functions --------------------------------------------------------*/ 307 | /** @addtogroup FLASH_Exported_Functions 308 | * @{ 309 | */ 310 | 311 | /** @addtogroup FLASH_Exported_Functions_Group1 312 | * @{ 313 | */ 314 | /* IO operation functions *****************************************************/ 315 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 316 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 317 | 318 | /* FLASH IRQ handler function */ 319 | void HAL_FLASH_IRQHandler(void); 320 | /* Callbacks in non blocking modes */ 321 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 322 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 323 | 324 | /** 325 | * @} 326 | */ 327 | 328 | /** @addtogroup FLASH_Exported_Functions_Group2 329 | * @{ 330 | */ 331 | /* Peripheral Control functions ***********************************************/ 332 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 333 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 334 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 335 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 336 | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 337 | 338 | /** 339 | * @} 340 | */ 341 | 342 | /** @addtogroup FLASH_Exported_Functions_Group3 343 | * @{ 344 | */ 345 | /* Peripheral State and Error functions ***************************************/ 346 | uint32_t HAL_FLASH_GetError(void); 347 | 348 | /** 349 | * @} 350 | */ 351 | 352 | /** 353 | * @} 354 | */ 355 | 356 | /* Private function -------------------------------------------------*/ 357 | /** @addtogroup FLASH_Private_Functions 358 | * @{ 359 | */ 360 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 361 | 362 | /** 363 | * @} 364 | */ 365 | 366 | /** 367 | * @} 368 | */ 369 | 370 | /** 371 | * @} 372 | */ 373 | 374 | #ifdef __cplusplus 375 | } 376 | #endif 377 | 378 | #endif /* __STM32F3xx_HAL_FLASH_H */ 379 | 380 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 381 | 382 | -------------------------------------------------------------------------------- /Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_pwr.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_PWR_H 22 | #define __STM32F3xx_HAL_PWR_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PWR PWR 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /** @defgroup PWR_Exported_Constants PWR Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins 46 | * @{ 47 | */ 48 | 49 | #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */ 50 | #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */ 51 | #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */ 52 | /** 53 | * @} 54 | */ 55 | 56 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode 57 | * @{ 58 | */ 59 | #define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */ 60 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */ 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 66 | * @{ 67 | */ 68 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */ 69 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */ 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 75 | * @{ 76 | */ 77 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */ 78 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */ 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @defgroup PWR_Flag PWR Flag 84 | * @{ 85 | */ 86 | #define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */ 87 | #define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */ 88 | #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */ 89 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */ 90 | /** 91 | * @} 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /* Exported macro ------------------------------------------------------------*/ 99 | /** @defgroup PWR_Exported_Macro PWR Exported Macro 100 | * @{ 101 | */ 102 | 103 | /** @brief Check PWR flag is set or not. 104 | * @param __FLAG__ specifies the flag to check. 105 | * This parameter can be one of the following values: 106 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 107 | * was received from the WKUP pin or from the RTC alarm (Alarm A 108 | * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. 109 | * An additional wakeup event is detected if the WKUP pin is enabled 110 | * (by setting the EWUP bit) when the WKUP pin level is already high. 111 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 112 | * resumed from StandBy mode. 113 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 114 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 115 | * For this reason, this bit is equal to 0 after Standby or reset 116 | * until the PVDE bit is set. 117 | * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference 118 | * voltage VREFINT is ready. 119 | * @retval The new state of __FLAG__ (TRUE or FALSE). 120 | */ 121 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 122 | 123 | /** @brief Clear the PWR's pending flags. 124 | * @param __FLAG__ specifies the flag to clear. 125 | * This parameter can be one of the following values: 126 | * @arg PWR_FLAG_WU: Wake Up flag 127 | * @arg PWR_FLAG_SB: StandBy flag 128 | */ 129 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) 130 | 131 | /** 132 | * @} 133 | */ 134 | 135 | /* Private macros --------------------------------------------------------*/ 136 | /** @addtogroup PWR_Private_Macros PWR Private Macros 137 | * @{ 138 | */ 139 | 140 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 141 | ((PIN) == PWR_WAKEUP_PIN2) || \ 142 | ((PIN) == PWR_WAKEUP_PIN3)) 143 | 144 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 145 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 146 | 147 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 148 | 149 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /* Include PWR HAL Extended module */ 156 | #include "stm32f3xx_hal_pwr_ex.h" 157 | 158 | /* Exported functions --------------------------------------------------------*/ 159 | 160 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions 161 | * @{ 162 | */ 163 | 164 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 165 | * @{ 166 | */ 167 | 168 | /* Initialization and de-initialization functions *****************************/ 169 | void HAL_PWR_DeInit(void); 170 | 171 | /** 172 | * @} 173 | */ 174 | 175 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 176 | * @{ 177 | */ 178 | 179 | /* Peripheral Control functions **********************************************/ 180 | void HAL_PWR_EnableBkUpAccess(void); 181 | void HAL_PWR_DisableBkUpAccess(void); 182 | 183 | /* WakeUp pins configuration functions ****************************************/ 184 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 185 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 186 | 187 | /* Low Power modes configuration functions ************************************/ 188 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 189 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 190 | void HAL_PWR_EnterSTANDBYMode(void); 191 | 192 | void HAL_PWR_EnableSleepOnExit(void); 193 | void HAL_PWR_DisableSleepOnExit(void); 194 | void HAL_PWR_EnableSEVOnPend(void); 195 | void HAL_PWR_DisableSEVOnPend(void); 196 | /** 197 | * @} 198 | */ 199 | 200 | /** 201 | * @} 202 | */ 203 | 204 | /** 205 | * @} 206 | */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | #ifdef __cplusplus 213 | } 214 | #endif 215 | 216 | 217 | #endif /* __STM32F3xx_HAL_PWR_H */ 218 | 219 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 220 | -------------------------------------------------------------------------------- /Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_pwr_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F3xx_HAL_PWR_EX_H 22 | #define __STM32F3xx_HAL_PWR_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f3xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F3xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PWREx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | 41 | /** @defgroup PWREx_Exported_Types PWR Extended Exported Types 42 | * @{ 43 | */ 44 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 45 | defined(STM32F302xC) || defined(STM32F303xC) || \ 46 | defined(STM32F303x8) || defined(STM32F334x8) || \ 47 | defined(STM32F301x8) || defined(STM32F302x8) || \ 48 | defined(STM32F373xC) 49 | /** 50 | * @brief PWR PVD configuration structure definition 51 | */ 52 | typedef struct 53 | { 54 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level 55 | This parameter can be a value of @ref PWREx_PVD_detection_level */ 56 | 57 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 58 | This parameter can be a value of @ref PWREx_PVD_Mode */ 59 | }PWR_PVDTypeDef; 60 | #endif /* STM32F302xE || STM32F303xE || */ 61 | /* STM32F302xC || STM32F303xC || */ 62 | /* STM32F303x8 || STM32F334x8 || */ 63 | /* STM32F301x8 || STM32F302x8 || */ 64 | /* STM32F373xC */ 65 | 66 | /** 67 | * @} 68 | */ 69 | 70 | /* Exported constants --------------------------------------------------------*/ 71 | /** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants 72 | * @{ 73 | */ 74 | 75 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 76 | defined(STM32F302xC) || defined(STM32F303xC) || \ 77 | defined(STM32F303x8) || defined(STM32F334x8) || \ 78 | defined(STM32F301x8) || defined(STM32F302x8) || \ 79 | defined(STM32F373xC) 80 | 81 | /** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level 82 | * @{ 83 | */ 84 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */ 85 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */ 86 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */ 87 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */ 88 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */ 89 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */ 90 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */ 91 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */ 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode 97 | * @{ 98 | */ 99 | #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 100 | #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 101 | #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 102 | #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 103 | #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 104 | #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 105 | #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 106 | /** 107 | * @} 108 | */ 109 | 110 | #define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ 111 | 112 | #endif /* STM32F302xE || STM32F303xE || */ 113 | /* STM32F302xC || STM32F303xC || */ 114 | /* STM32F303x8 || STM32F334x8 || */ 115 | /* STM32F301x8 || STM32F302x8 || */ 116 | /* STM32F373xC */ 117 | 118 | #if defined(STM32F373xC) || defined(STM32F378xx) 119 | /** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx 120 | * @{ 121 | */ 122 | #define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */ 123 | #define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */ 124 | #define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */ 125 | /** 126 | * @} 127 | */ 128 | #endif /* STM32F373xC || STM32F378xx */ 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /* Exported macro ------------------------------------------------------------*/ 135 | /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros 136 | * @{ 137 | */ 138 | 139 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 140 | defined(STM32F302xC) || defined(STM32F303xC) || \ 141 | defined(STM32F303x8) || defined(STM32F334x8) || \ 142 | defined(STM32F301x8) || defined(STM32F302x8) || \ 143 | defined(STM32F373xC) 144 | 145 | /** 146 | * @brief Enable interrupt on PVD Exti Line 16. 147 | * @retval None. 148 | */ 149 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) 150 | 151 | /** 152 | * @brief Disable interrupt on PVD Exti Line 16. 153 | * @retval None. 154 | */ 155 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) 156 | 157 | /** 158 | * @brief Generate a Software interrupt on selected EXTI line. 159 | * @retval None. 160 | */ 161 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) 162 | 163 | /** 164 | * @brief Enable event on PVD Exti Line 16. 165 | * @retval None. 166 | */ 167 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) 168 | 169 | /** 170 | * @brief Disable event on PVD Exti Line 16. 171 | * @retval None. 172 | */ 173 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) 174 | 175 | /** 176 | * @brief Disable the PVD Extended Interrupt Rising Trigger. 177 | * @retval None. 178 | */ 179 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 180 | 181 | /** 182 | * @brief Disable the PVD Extended Interrupt Falling Trigger. 183 | * @retval None. 184 | */ 185 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 186 | 187 | /** 188 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 189 | * @retval None 190 | */ 191 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 192 | 193 | /** 194 | * @brief PVD EXTI line configuration: set falling edge trigger. 195 | * @retval None. 196 | */ 197 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) 198 | 199 | /** 200 | * @brief PVD EXTI line configuration: set rising edge trigger. 201 | * @retval None. 202 | */ 203 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) 204 | 205 | /** 206 | * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. 207 | * @retval None 208 | */ 209 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 210 | 211 | /** 212 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 213 | * @retval EXTI PVD Line Status. 214 | */ 215 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 216 | 217 | /** 218 | * @brief Clear the PVD EXTI flag. 219 | * @retval None. 220 | */ 221 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 222 | 223 | #endif /* STM32F302xE || STM32F303xE || */ 224 | /* STM32F302xC || STM32F303xC || */ 225 | /* STM32F303x8 || STM32F334x8 || */ 226 | /* STM32F301x8 || STM32F302x8 || */ 227 | /* STM32F373xC */ 228 | 229 | /** 230 | * @} 231 | */ 232 | 233 | /* Private macros --------------------------------------------------------*/ 234 | /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros 235 | * @{ 236 | */ 237 | 238 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 239 | defined(STM32F302xC) || defined(STM32F303xC) || \ 240 | defined(STM32F303x8) || defined(STM32F334x8) || \ 241 | defined(STM32F301x8) || defined(STM32F302x8) || \ 242 | defined(STM32F373xC) 243 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ 244 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ 245 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ 246 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 247 | 248 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ 249 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ 250 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ 251 | ((MODE) == PWR_PVD_MODE_NORMAL)) 252 | #endif /* STM32F302xE || STM32F303xE || */ 253 | /* STM32F302xC || STM32F303xC || */ 254 | /* STM32F303x8 || STM32F334x8 || */ 255 | /* STM32F301x8 || STM32F302x8 || */ 256 | /* STM32F373xC */ 257 | 258 | #if defined(STM32F373xC) || defined(STM32F378xx) 259 | #define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \ 260 | ((SDADC) == PWR_SDADC_ANALOG2) || \ 261 | ((SDADC) == PWR_SDADC_ANALOG3)) 262 | #endif /* STM32F373xC || STM32F378xx */ 263 | 264 | 265 | /** 266 | * @} 267 | */ 268 | 269 | /* Exported functions --------------------------------------------------------*/ 270 | 271 | /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions 272 | * @{ 273 | */ 274 | 275 | /** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions 276 | * @{ 277 | */ 278 | /* Peripheral Extended control functions **************************************/ 279 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 280 | defined(STM32F302xC) || defined(STM32F303xC) || \ 281 | defined(STM32F303x8) || defined(STM32F334x8) || \ 282 | defined(STM32F301x8) || defined(STM32F302x8) || \ 283 | defined(STM32F373xC) 284 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 285 | void HAL_PWR_EnablePVD(void); 286 | void HAL_PWR_DisablePVD(void); 287 | void HAL_PWR_PVD_IRQHandler(void); 288 | void HAL_PWR_PVDCallback(void); 289 | #endif /* STM32F302xE || STM32F303xE || */ 290 | /* STM32F302xC || STM32F303xC || */ 291 | /* STM32F303x8 || STM32F334x8 || */ 292 | /* STM32F301x8 || STM32F302x8 || */ 293 | /* STM32F373xC */ 294 | 295 | #if defined(STM32F373xC) || defined(STM32F378xx) 296 | void HAL_PWREx_EnableSDADC(uint32_t Analogx); 297 | void HAL_PWREx_DisableSDADC(uint32_t Analogx); 298 | #endif /* STM32F373xC || STM32F378xx */ 299 | 300 | /** 301 | * @} 302 | */ 303 | 304 | /** 305 | * @} 306 | */ 307 | 308 | /** 309 | * @} 310 | */ 311 | 312 | /** 313 | * @} 314 | */ 315 | 316 | #ifdef __cplusplus 317 | } 318 | #endif 319 | 320 | #endif /* __STM32F3xx_HAL_PWR_EX_H */ 321 | 322 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 323 | -------------------------------------------------------------------------------- /Drivers/STM32F3xx_HAL_Driver/License.md: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 STMicroelectronics 2 | 3 | This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). -------------------------------------------------------------------------------- /Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f3xx_hal_pwr_ex.c 4 | * @author MCD Application Team 5 | * @brief Extended PWR HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the Power Controller (PWR) peripheral: 8 | * + Extended Initialization and de-initialization functions 9 | * + Extended Peripheral Control functions 10 | * 11 | ****************************************************************************** 12 | * @attention 13 | * 14 | *

© Copyright (c) 2016 STMicroelectronics. 15 | * All rights reserved.

16 | * 17 | * This software component is licensed by ST under BSD 3-Clause license, 18 | * the "License"; You may not use this file except in compliance with the 19 | * License. You may obtain a copy of the License at: 20 | * opensource.org/licenses/BSD-3-Clause 21 | * 22 | ****************************************************************************** 23 | */ 24 | 25 | /* Includes ------------------------------------------------------------------*/ 26 | #include "stm32f3xx_hal.h" 27 | 28 | /** @addtogroup STM32F3xx_HAL_Driver 29 | * @{ 30 | */ 31 | 32 | /** @defgroup PWREx PWREx 33 | * @brief PWREx HAL module driver 34 | * @{ 35 | */ 36 | 37 | #ifdef HAL_PWR_MODULE_ENABLED 38 | 39 | /* Private typedef -----------------------------------------------------------*/ 40 | /* Private define ------------------------------------------------------------*/ 41 | /** @defgroup PWREx_Private_Constants PWR Extended Private Constants 42 | * @{ 43 | */ 44 | #define PVD_MODE_IT (0x00010000U) 45 | #define PVD_MODE_EVT (0x00020000U) 46 | #define PVD_RISING_EDGE (0x00000001U) 47 | #define PVD_FALLING_EDGE (0x00000002U) 48 | /** 49 | * @} 50 | */ 51 | 52 | /* Private macro -------------------------------------------------------------*/ 53 | /* Private variables ---------------------------------------------------------*/ 54 | /* Private function prototypes -----------------------------------------------*/ 55 | /* Exported functions ---------------------------------------------------------*/ 56 | 57 | /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions 58 | * @{ 59 | */ 60 | 61 | /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions 62 | * @brief Extended Peripheral Control functions 63 | * 64 | @verbatim 65 | 66 | =============================================================================== 67 | ##### Peripheral Extended control functions ##### 68 | =============================================================================== 69 | *** PVD configuration (present on all other devices than STM32F3x8 devices) *** 70 | ========================= 71 | [..] 72 | (+) The PVD is used to monitor the VDD power supply by comparing it to a 73 | threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 74 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 75 | than the PVD threshold. This event is internally connected to the EXTI 76 | line16 and can generate an interrupt if enabled. This is done through 77 | __HAL_PWR_PVD_EXTI_ENABLE_IT() macro 78 | (+) The PVD is stopped in Standby mode. 79 | -@- PVD is not available on STM32F3x8 Product Line 80 | 81 | 82 | *** Voltage regulator *** 83 | ========================= 84 | [..] 85 | (+) The voltage regulator is always enabled after Reset. It works in three different 86 | modes. 87 | In Run mode, the regulator supplies full power to the 1.8V domain (core, memories 88 | and digital peripherals). 89 | In Stop mode, the regulator supplies low power to the 1.8V domain, preserving 90 | contents of registers and SRAM. 91 | In Stop mode, the regulator is powered off. The contents of the registers and SRAM 92 | are lost except for the Standby circuitry and the Backup Domain. 93 | Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the 94 | microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. 95 | 96 | 97 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 98 | than the PVD threshold. This event is internally connected to the EXTI 99 | line16 and can generate an interrupt if enabled. This is done through 100 | __HAL_PWR_PVD_EXTI_ENABLE_IT() macro 101 | (+) The PVD is stopped in Standby mode. 102 | 103 | 104 | *** SDADC power configuration *** 105 | ================================ 106 | [..] 107 | (+) On STM32F373xC/STM32F378xx devices, there are up to 108 | 3 SDADC instances that can be enabled/disabled. 109 | 110 | @endverbatim 111 | * @{ 112 | */ 113 | 114 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ 115 | defined(STM32F302xC) || defined(STM32F303xC) || \ 116 | defined(STM32F303x8) || defined(STM32F334x8) || \ 117 | defined(STM32F301x8) || defined(STM32F302x8) || \ 118 | defined(STM32F373xC) 119 | 120 | /** 121 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 122 | * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 123 | * information for the PVD. 124 | * @note Refer to the electrical characteristics of your device datasheet for 125 | * more details about the voltage threshold corresponding to each 126 | * detection level. 127 | * @retval None 128 | */ 129 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 130 | { 131 | /* Check the parameters */ 132 | assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 133 | assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 134 | 135 | /* Set PLS[7:5] bits according to PVDLevel value */ 136 | MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 137 | 138 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 139 | __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 140 | __HAL_PWR_PVD_EXTI_DISABLE_IT(); 141 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 142 | 143 | /* Configure interrupt mode */ 144 | if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 145 | { 146 | __HAL_PWR_PVD_EXTI_ENABLE_IT(); 147 | } 148 | 149 | /* Configure event mode */ 150 | if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 151 | { 152 | __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 153 | } 154 | 155 | /* Configure the edge */ 156 | if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 157 | { 158 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 159 | } 160 | 161 | if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 162 | { 163 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 164 | } 165 | } 166 | 167 | /** 168 | * @brief Enables the Power Voltage Detector(PVD). 169 | * @retval None 170 | */ 171 | void HAL_PWR_EnablePVD(void) 172 | { 173 | SET_BIT(PWR->CR, PWR_CR_PVDE); 174 | } 175 | 176 | /** 177 | * @brief Disables the Power Voltage Detector(PVD). 178 | * @retval None 179 | */ 180 | void HAL_PWR_DisablePVD(void) 181 | { 182 | CLEAR_BIT(PWR->CR, PWR_CR_PVDE); 183 | } 184 | 185 | /** 186 | * @brief This function handles the PWR PVD interrupt request. 187 | * @note This API should be called under the PVD_IRQHandler(). 188 | * @retval None 189 | */ 190 | void HAL_PWR_PVD_IRQHandler(void) 191 | { 192 | /* Check PWR exti flag */ 193 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 194 | { 195 | /* PWR PVD interrupt user callback */ 196 | HAL_PWR_PVDCallback(); 197 | 198 | /* Clear PWR Exti pending bit */ 199 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 200 | } 201 | } 202 | 203 | /** 204 | * @brief PWR PVD interrupt callback 205 | * @retval None 206 | */ 207 | __weak void HAL_PWR_PVDCallback(void) 208 | { 209 | /* NOTE : This function Should not be modified, when the callback is needed, 210 | the HAL_PWR_PVDCallback could be implemented in the user file 211 | */ 212 | } 213 | 214 | #endif /* STM32F302xE || STM32F303xE || */ 215 | /* STM32F302xC || STM32F303xC || */ 216 | /* STM32F303x8 || STM32F334x8 || */ 217 | /* STM32F301x8 || STM32F302x8 || */ 218 | /* STM32F373xC */ 219 | 220 | #if defined(STM32F373xC) || defined(STM32F378xx) 221 | 222 | /** 223 | * @brief Enables the SDADC peripheral functionaliy 224 | * @param Analogx specifies the SDADC peripheral instance. 225 | * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. 226 | * @retval None 227 | */ 228 | void HAL_PWREx_EnableSDADC(uint32_t Analogx) 229 | { 230 | /* Check the parameters */ 231 | assert_param(IS_PWR_SDADC_ANALOG(Analogx)); 232 | 233 | /* Enable PWR clock interface for SDADC use */ 234 | __HAL_RCC_PWR_CLK_ENABLE(); 235 | 236 | PWR->CR |= Analogx; 237 | } 238 | 239 | /** 240 | * @brief Disables the SDADC peripheral functionaliy 241 | * @param Analogx specifies the SDADC peripheral instance. 242 | * This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3. 243 | * @retval None 244 | */ 245 | void HAL_PWREx_DisableSDADC(uint32_t Analogx) 246 | { 247 | /* Check the parameters */ 248 | assert_param(IS_PWR_SDADC_ANALOG(Analogx)); 249 | 250 | PWR->CR &= ~Analogx; 251 | } 252 | 253 | #endif /* STM32F373xC || STM32F378xx */ 254 | 255 | /** 256 | * @} 257 | */ 258 | 259 | /** 260 | * @} 261 | */ 262 | 263 | #endif /* HAL_PWR_MODULE_ENABLED */ 264 | /** 265 | * @} 266 | */ 267 | 268 | /** 269 | * @} 270 | */ 271 | 272 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 273 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Loris Guerra 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /STM32F303VCTX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** @file : LinkerScript.ld 5 | ** 6 | ** @author : Auto-generated by STM32CubeIDE 7 | ** 8 | ** Abstract : Linker script for STM32F3DISCOVERY Board embedding STM32F303VCTx Device from stm32f3 series 9 | ** 256Kbytes FLASH 10 | ** 8Kbytes CCMRAM 11 | ** 40Kbytes RAM 12 | ** 13 | ** Set heap size, stack size and stack location according 14 | ** to application requirements. 15 | ** 16 | ** Set memory bank area and size if external memory is used 17 | ** 18 | ** Target : STMicroelectronics STM32 19 | ** 20 | ** Distribution: The file is distributed as is, without any warranty 21 | ** of any kind. 22 | ** 23 | ****************************************************************************** 24 | ** @attention 25 | ** 26 | ** Copyright (c) 2022 STMicroelectronics. 27 | ** All rights reserved. 28 | ** 29 | ** This software is licensed under terms that can be found in the LICENSE file 30 | ** in the root directory of this software component. 31 | ** If no LICENSE file comes with this software, it is provided AS-IS. 32 | ** 33 | ****************************************************************************** 34 | */ 35 | 36 | /* Entry Point */ 37 | ENTRY(Reset_Handler) 38 | 39 | /* Highest address of the user mode stack */ 40 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ 41 | 42 | _Min_Heap_Size = 0x200; /* required amount of heap */ 43 | _Min_Stack_Size = 0x400; /* required amount of stack */ 44 | 45 | /* Memories definition */ 46 | MEMORY 47 | { 48 | CCMRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 8K 49 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 40K 50 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K 51 | } 52 | 53 | /* Sections */ 54 | SECTIONS 55 | { 56 | /* The startup code into "FLASH" Rom type memory */ 57 | .isr_vector : 58 | { 59 | . = ALIGN(4); 60 | KEEP(*(.isr_vector)) /* Startup code */ 61 | . = ALIGN(4); 62 | } >FLASH 63 | 64 | /* The program code and other data into "FLASH" Rom type memory */ 65 | .text : 66 | { 67 | . = ALIGN(4); 68 | *(.text) /* .text sections (code) */ 69 | *(.text*) /* .text* sections (code) */ 70 | *(.glue_7) /* glue arm to thumb code */ 71 | *(.glue_7t) /* glue thumb to arm code */ 72 | *(.eh_frame) 73 | 74 | KEEP (*(.init)) 75 | KEEP (*(.fini)) 76 | 77 | . = ALIGN(4); 78 | _etext = .; /* define a global symbols at end of code */ 79 | } >FLASH 80 | 81 | /* Constant data into "FLASH" Rom type memory */ 82 | .rodata : 83 | { 84 | . = ALIGN(4); 85 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 86 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 87 | . = ALIGN(4); 88 | } >FLASH 89 | 90 | .ARM.extab : { 91 | . = ALIGN(4); 92 | *(.ARM.extab* .gnu.linkonce.armextab.*) 93 | . = ALIGN(4); 94 | } >FLASH 95 | 96 | .ARM : { 97 | . = ALIGN(4); 98 | __exidx_start = .; 99 | *(.ARM.exidx*) 100 | __exidx_end = .; 101 | . = ALIGN(4); 102 | } >FLASH 103 | 104 | .preinit_array : 105 | { 106 | . = ALIGN(4); 107 | PROVIDE_HIDDEN (__preinit_array_start = .); 108 | KEEP (*(.preinit_array*)) 109 | PROVIDE_HIDDEN (__preinit_array_end = .); 110 | . = ALIGN(4); 111 | } >FLASH 112 | 113 | .init_array : 114 | { 115 | . = ALIGN(4); 116 | PROVIDE_HIDDEN (__init_array_start = .); 117 | KEEP (*(SORT(.init_array.*))) 118 | KEEP (*(.init_array*)) 119 | PROVIDE_HIDDEN (__init_array_end = .); 120 | . = ALIGN(4); 121 | } >FLASH 122 | 123 | .fini_array : 124 | { 125 | . = ALIGN(4); 126 | PROVIDE_HIDDEN (__fini_array_start = .); 127 | KEEP (*(SORT(.fini_array.*))) 128 | KEEP (*(.fini_array*)) 129 | PROVIDE_HIDDEN (__fini_array_end = .); 130 | . = ALIGN(4); 131 | } >FLASH 132 | 133 | /* Used by the startup to initialize data */ 134 | _sidata = LOADADDR(.data); 135 | 136 | /* Initialized data sections into "RAM" Ram type memory */ 137 | .data : 138 | { 139 | . = ALIGN(4); 140 | _sdata = .; /* create a global symbol at data start */ 141 | *(.data) /* .data sections */ 142 | *(.data*) /* .data* sections */ 143 | *(.RamFunc) /* .RamFunc sections */ 144 | *(.RamFunc*) /* .RamFunc* sections */ 145 | 146 | . = ALIGN(4); 147 | _edata = .; /* define a global symbol at data end */ 148 | 149 | } >RAM AT> FLASH 150 | 151 | _siccmram = LOADADDR(.ccmram); 152 | 153 | /* CCM-RAM section 154 | * 155 | * IMPORTANT NOTE! 156 | * If initialized variables will be placed in this section, 157 | * the startup code needs to be modified to copy the init-values. 158 | */ 159 | .ccmram : 160 | { 161 | . = ALIGN(4); 162 | _sccmram = .; /* create a global symbol at ccmram start */ 163 | *(.ccmram) 164 | *(.ccmram*) 165 | 166 | . = ALIGN(4); 167 | _eccmram = .; /* create a global symbol at ccmram end */ 168 | } >CCMRAM AT> FLASH 169 | 170 | /* Uninitialized data section into "RAM" Ram type memory */ 171 | . = ALIGN(4); 172 | .bss : 173 | { 174 | /* This is used by the startup in order to initialize the .bss section */ 175 | _sbss = .; /* define a global symbol at bss start */ 176 | __bss_start__ = _sbss; 177 | *(.bss) 178 | *(.bss*) 179 | *(COMMON) 180 | 181 | . = ALIGN(4); 182 | _ebss = .; /* define a global symbol at bss end */ 183 | __bss_end__ = _ebss; 184 | } >RAM 185 | 186 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ 187 | ._user_heap_stack : 188 | { 189 | . = ALIGN(8); 190 | PROVIDE ( end = . ); 191 | PROVIDE ( _end = . ); 192 | . = . + _Min_Heap_Size; 193 | . = . + _Min_Stack_Size; 194 | . = ALIGN(8); 195 | } >RAM 196 | 197 | /* Remove information from the compiler libraries */ 198 | /DISCARD/ : 199 | { 200 | libc.a ( * ) 201 | libm.a ( * ) 202 | libgcc.a ( * ) 203 | } 204 | 205 | .ARM.attributes 0 : { *(.ARM.attributes) } 206 | } 207 | -------------------------------------------------------------------------------- /cmake/gcc-arm-none-eabi.cmake: -------------------------------------------------------------------------------- 1 | set(CMAKE_SYSTEM_NAME Generic) 2 | set(CMAKE_SYSTEM_PROCESSOR arm) 3 | 4 | # Some default GCC settings 5 | # arm-none-eabi- must be part of path environment 6 | set(TOOLCHAIN_PREFIX arm-none-eabi-) 7 | set(FLAGS "-fdata-sections -ffunction-sections --specs=nano.specs -Wl,--gc-sections") 8 | set(CPP_FLAGS "-fno-rtti -fno-exceptions -fno-threadsafe-statics") 9 | 10 | set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc ${FLAGS}) 11 | set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) 12 | set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++ ${FLAGS} ${CPP_FLAGS}) 13 | set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy) 14 | set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size) 15 | 16 | set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf") 17 | set(CMAKE_EXECUTABLE_SUFFIX_C ".elf") 18 | set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf") 19 | 20 | set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) 21 | -------------------------------------------------------------------------------- /datasheets/Description of STM32F3 HAL and LL Drivers.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/datasheets/Description of STM32F3 HAL and LL Drivers.pdf -------------------------------------------------------------------------------- /datasheets/GNU ARM Assembler Quick Reference.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/datasheets/GNU ARM Assembler Quick Reference.pdf -------------------------------------------------------------------------------- /datasheets/STM32 Cortex-M4 Programming Manual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/datasheets/STM32 Cortex-M4 Programming Manual.pdf -------------------------------------------------------------------------------- /datasheets/STM32F303xC Datasheet.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/datasheets/STM32F303xC Datasheet.pdf -------------------------------------------------------------------------------- /readme_assets/book-rtos-valvano.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/readme_assets/book-rtos-valvano.jpg -------------------------------------------------------------------------------- /readme_assets/project.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/readme_assets/project.jpg -------------------------------------------------------------------------------- /readme_assets/saleae-logic2-session.sal: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/readme_assets/saleae-logic2-session.sal -------------------------------------------------------------------------------- /readme_assets/screenshot-logic-analyzer.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dehre/stm32f3-tiny-rtos/98bb33bd887719cbd47bed650c1c5ef6ea5ef7ff/readme_assets/screenshot-logic-analyzer.png --------------------------------------------------------------------------------