├── LICENSE ├── README.md ├── devicetree_overlays ├── axp20x.dts ├── cwu50_panel.dts ├── displaystuff.dts └── dt-bindings │ ├── gpio │ ├── aspeed-gpio.h │ ├── gpio.h │ ├── meson-a1-gpio.h │ ├── meson-axg-gpio.h │ ├── meson-g12a-gpio.h │ ├── meson-gxbb-gpio.h │ ├── meson-gxl-gpio.h │ ├── meson-s4-gpio.h │ ├── meson8-gpio.h │ ├── meson8b-gpio.h │ ├── msc313-gpio.h │ ├── tegra-gpio.h │ ├── tegra186-gpio.h │ ├── tegra194-gpio.h │ ├── tegra234-gpio.h │ ├── tegra241-gpio.h │ └── uniphier-gpio.h │ ├── interrupt-controller │ ├── apple-aic.h │ ├── arm-gic.h │ ├── aspeed-scu-ic.h │ ├── irq-st.h │ ├── irq.h │ ├── irqc-rzg2l.h │ ├── mips-gic.h │ └── mvebu-icu.h │ └── pinctrl │ ├── am33xx.h │ ├── am43xx.h │ ├── apple.h │ ├── at91.h │ ├── bcm2835.h │ ├── brcm,pinctrl-stingray.h │ ├── dm814x.h │ ├── dra.h │ ├── hisi.h │ ├── k210-fpioa.h │ ├── k3.h │ ├── keystone.h │ ├── lochnagar.h │ ├── mediatek,mt8188-pinfunc.h │ ├── mt6397-pinfunc.h │ ├── mt65xx.h │ ├── mt6779-pinfunc.h │ ├── mt6795-pinfunc.h │ ├── mt6797-pinfunc.h │ ├── mt7623-pinfunc.h │ ├── mt8135-pinfunc.h │ ├── mt8183-pinfunc.h │ ├── mt8186-pinfunc.h │ ├── mt8192-pinfunc.h │ ├── mt8195-pinfunc.h │ ├── mt8365-pinfunc.h │ ├── nomadik.h │ ├── omap.h │ ├── pads-imx8dxl.h │ ├── pads-imx8qm.h │ ├── pads-imx8qxp.h │ ├── pinctrl-starfive-jh7100.h │ ├── pinctrl-tegra-io-pad.h │ ├── pinctrl-tegra-xusb.h │ ├── pinctrl-tegra.h │ ├── pinctrl-zynq.h │ ├── pinctrl-zynqmp.h │ ├── qcom,pmic-gpio.h │ ├── qcom,pmic-mpp.h │ ├── r7s72100-pinctrl.h │ ├── r7s9210-pinctrl.h │ ├── rockchip.h │ ├── rzg2l-pinctrl.h │ ├── rzn1-pinctrl.h │ ├── rzv2m-pinctrl.h │ ├── samsung.h │ ├── sppctl-sp7021.h │ ├── sppctl.h │ ├── stm32-pinfunc.h │ └── sun4i-a10.h └── kernel ├── linux-headers-6.1.43-105-rockchip_6.1.43-105-rockchip_arm64.deb └── linux-image-6.1.43-105-rockchip_6.1.43-105-rockchip_arm64.deb /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The licenses for most software are designed to take away your 12 | freedom to share and change it. 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See the 304 | GNU General Public License for more details. 305 | 306 | You should have received a copy of the GNU General Public License along 307 | with this program; if not, write to the Free Software Foundation, Inc., 308 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 309 | 310 | Also add information on how to contact you by electronic and paper mail. 311 | 312 | If the program is interactive, make it output a short notice like this 313 | when it starts in an interactive mode: 314 | 315 | Gnomovision version 69, Copyright (C) year name of author 316 | Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 317 | This is free software, and you are welcome to redistribute it 318 | under certain conditions; type `show c' for details. 319 | 320 | The hypothetical commands `show w' and `show c' should show the appropriate 321 | parts of the General Public License. Of course, the commands you use may 322 | be called something other than `show w' and `show c'; they could even be 323 | mouse-clicks or menu items--whatever suits your program. 324 | 325 | You should also get your employer (if you work as a programmer) or your 326 | school, if any, to sign a "copyright disclaimer" for the program, if 327 | necessary. Here is a sample; alter the names: 328 | 329 | Yoyodyne, Inc., hereby disclaims all copyright interest in the program 330 | `Gnomovision' (which makes passes at compilers) written by James Hacker. 331 | 332 | , 1 April 1989 333 | Ty Coon, President of Vice 334 | 335 | This General Public License does not permit incorporating your program into 336 | proprietary programs. If your program is a subroutine library, you may 337 | consider it more useful to permit linking proprietary applications with the 338 | library. If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # radxa-cm5-uconsole 2 | Radxa CM5 in the Clockworkpi uConsole. 3 |
4 |
5 | What does work:
6 | -Display
7 | -Keyboard
8 | -USB
9 | -Power management
10 | -4G module
11 | -microSD card
12 |
13 | What doesnt work, and will never work:
14 | -Internal Wifi/Bt (the Radxa CM5 has no Wifi/Bt on board)
15 |
16 | What does work with Hardware modifications:
17 | -HDMI out
18 |
19 | What does maybe work:
20 | -Audio (mono only)
21 |
22 |
23 | Currently you need to flash the "Radxa CM5 Lite on RPI CM4 IO Image" (https://github.com/radxa-build/radxa-cm5-rpi-cm4-io/releases/download/rsdk-b3/radxa-cm5-rpi-cm4-io_bookworm_cli_b3.output.img.xz) on a microSD and put the CM5 into a Rpi CM4 IO board. 24 |

25 | Boot it up, install my kernel and apply the devicetree overlays with rsetup. Then put the CM5 back into your uConsole. 26 |

27 | I will try to build an image based on the Radxa CLI Image so you can put the CM5 directly into the uConsole without IO Board ... 28 | -------------------------------------------------------------------------------- /devicetree_overlays/axp20x.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | #include 4 | #include 5 | #include 6 | / { 7 | 8 | metadata { 9 | title = "Enable AXP228"; 10 | compatible = "radxa,cm5-rpi-cm4-io"; 11 | description = "Enable AXP228"; 12 | }; 13 | 14 | fragment@0 { 15 | target = <&i2c8>; 16 | __overlay__ { 17 | #address-cells = <1>; 18 | #size-cells = <0>; 19 | pinctrl-0 = <&i2c8m2_xfer>; 20 | pinctrl-names = "default"; 21 | status = "okay"; 22 | axp22x: pmic@34 { 23 | interrupt-controller; 24 | #interrupt-cells = <1>; 25 | compatible = "x-powers,axp221"; 26 | reg = <0x34>; /* i2c address */ 27 | interrupt-parent = <&gpio0>; 28 | interrupts = ; 29 | 30 | regulators { 31 | x-powers,dcdc-freq = <3000>; 32 | reg_aldo1: aldo1 { 33 | regulator-always-on; 34 | regulator-min-microvolt = <3300000>; 35 | regulator-max-microvolt = <3300000>; 36 | regulator-name = "audio-vdd"; 37 | }; 38 | reg_aldo2: aldo2 { 39 | regulator-always-on; 40 | regulator-min-microvolt = <3300000>; 41 | regulator-max-microvolt = <3300000>; 42 | regulator-name = "display-vcc"; 43 | }; 44 | reg_dldo2: dldo2 { 45 | regulator-always-on; 46 | regulator-min-microvolt = <3300000>; 47 | regulator-max-microvolt = <3300000>; 48 | regulator-name = "dldo2"; 49 | }; 50 | reg_dldo3: dldo3 { 51 | regulator-always-on; 52 | regulator-min-microvolt = <3300000>; 53 | regulator-max-microvolt = <3300000>; 54 | regulator-name = "dldo3"; 55 | }; 56 | reg_dldo4: dldo4 { 57 | regulator-always-on; 58 | regulator-min-microvolt = <3300000>; 59 | regulator-max-microvolt = <3300000>; 60 | regulator-name = "dldo4"; 61 | }; 62 | }; 63 | battery_power_supply: battery-power-supply { 64 | compatible = "x-powers,axp221-battery-power-supply"; 65 | monitored-battery = <&battery>; 66 | }; 67 | ac_power_supply: ac_power_supply { 68 | compatible = "x-powers,axp221-ac-power-supply"; 69 | }; 70 | }; 71 | }; 72 | }; 73 | fragment@1 { 74 | target-path = "/"; 75 | __overlay__ { 76 | battery: battery@0 { 77 | compatible = "simple-battery"; 78 | device-chemistry = "lithium-ion"; 79 | constant-charge-current-max-microamp = <2100000>; 80 | voltage-max-design-microvolt = <4200000>; 81 | re-charge-voltage-microvolt = <4000000>; 82 | // adjust the following params according to your battery specs 83 | voltage-min-design-microvolt = <3300000>; 84 | energy-full-design-microwatt-hours = <24790000>; // 2x3350mAh * 3.7v 85 | charge-full-design-microamp-hours = <6700000>; // 2x3350mAh 86 | }; 87 | }; 88 | }; 89 | }; 90 | -------------------------------------------------------------------------------- /devicetree_overlays/cwu50_panel.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | #include 4 | #include 5 | #include 6 | / { 7 | 8 | metadata { 9 | title = "Enable CWU50 display"; 10 | compatible = "radxa,cm5-rpi-cm4-io"; 11 | category = "display"; 12 | exclusive = "dsi1"; 13 | description = "Enable CWU50 display"; 14 | }; 15 | 16 | fragment@0 { 17 | target=<&dsi1>; 18 | __overlay__ { 19 | #address-cells = <1>; 20 | #size-cells = <0>; 21 | status = "okay"; 22 | 23 | ports { 24 | #address-cells = <1>; 25 | #size-cells = <0>; 26 | 27 | port@1 { 28 | reg = <1>; 29 | dsi1_out_panel: endpoint { 30 | remote-endpoint = <&panel_in_dsi1>; 31 | }; 32 | }; 33 | }; 34 | 35 | panel_cwu50: panel@0 { 36 | compatible = "cw,cwu50"; 37 | reg = <0>; 38 | reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 39 | backlight = <&ocp8178_backlight>; 40 | rotation = <90>; 41 | port { 42 | panel_in_dsi1: endpoint { 43 | remote-endpoint = <&dsi1_out_panel>; 44 | }; 45 | }; 46 | }; 47 | 48 | }; 49 | }; 50 | fragment@1 { 51 | target-path = "/"; 52 | __overlay__ { 53 | ocp8178_backlight: backlight@0 { 54 | compatible = "ocp8178-backlight"; 55 | backlight-control-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 56 | default-brightness = <5>; 57 | }; 58 | }; 59 | }; 60 | }; 61 | -------------------------------------------------------------------------------- /devicetree_overlays/displaystuff.dts: -------------------------------------------------------------------------------- 1 | /dts-v1/; 2 | /plugin/; 3 | 4 | #include 5 | #include 6 | #include 7 | 8 | / { 9 | metadata { 10 | title = "uConsole display stuff"; 11 | compatible = "radxa,cm5-rpi-cm4-io"; 12 | category = "display"; 13 | description = "uConsole display stuff"; 14 | }; 15 | }; 16 | 17 | &mipi_dcphy1 { 18 | status = "okay"; 19 | }; 20 | 21 | &route_dsi1 { 22 | status = "okay"; 23 | connect = <&vp3_out_dsi1>; 24 | }; 25 | 26 | &dsi1_in_vp2 { 27 | status = "disabled"; 28 | }; 29 | 30 | &dsi1_in_vp3 { 31 | status = "okay"; 32 | }; 33 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/aspeed-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0+ */ 2 | /* 3 | * This header provides constants for binding aspeed,*-gpio. 4 | * 5 | * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below 6 | * provide names for this. 7 | * 8 | * The second cell contains standard flag values specified in gpio.h. 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H 12 | #define _DT_BINDINGS_GPIO_ASPEED_GPIO_H 13 | 14 | #include 15 | 16 | #define ASPEED_GPIO_PORT_A 0 17 | #define ASPEED_GPIO_PORT_B 1 18 | #define ASPEED_GPIO_PORT_C 2 19 | #define ASPEED_GPIO_PORT_D 3 20 | #define ASPEED_GPIO_PORT_E 4 21 | #define ASPEED_GPIO_PORT_F 5 22 | #define ASPEED_GPIO_PORT_G 6 23 | #define ASPEED_GPIO_PORT_H 7 24 | #define ASPEED_GPIO_PORT_I 8 25 | #define ASPEED_GPIO_PORT_J 9 26 | #define ASPEED_GPIO_PORT_K 10 27 | #define ASPEED_GPIO_PORT_L 11 28 | #define ASPEED_GPIO_PORT_M 12 29 | #define ASPEED_GPIO_PORT_N 13 30 | #define ASPEED_GPIO_PORT_O 14 31 | #define ASPEED_GPIO_PORT_P 15 32 | #define ASPEED_GPIO_PORT_Q 16 33 | #define ASPEED_GPIO_PORT_R 17 34 | #define ASPEED_GPIO_PORT_S 18 35 | #define ASPEED_GPIO_PORT_T 19 36 | #define ASPEED_GPIO_PORT_U 20 37 | #define ASPEED_GPIO_PORT_V 21 38 | #define ASPEED_GPIO_PORT_W 22 39 | #define ASPEED_GPIO_PORT_X 23 40 | #define ASPEED_GPIO_PORT_Y 24 41 | #define ASPEED_GPIO_PORT_Z 25 42 | #define ASPEED_GPIO_PORT_AA 26 43 | #define ASPEED_GPIO_PORT_AB 27 44 | #define ASPEED_GPIO_PORT_AC 28 45 | 46 | #define ASPEED_GPIO(port, offset) \ 47 | ((ASPEED_GPIO_PORT_##port * 8) + offset) 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for most GPIO bindings. 4 | * 5 | * Most GPIO bindings include a flags cell as part of the GPIO specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_GPIO_GPIO_H 11 | #define _DT_BINDINGS_GPIO_GPIO_H 12 | 13 | /* Bit 0 express polarity */ 14 | #define GPIO_ACTIVE_HIGH 0 15 | #define GPIO_ACTIVE_LOW 1 16 | 17 | /* Bit 1 express single-endedness */ 18 | #define GPIO_PUSH_PULL 0 19 | #define GPIO_SINGLE_ENDED 2 20 | 21 | /* Bit 2 express Open drain or open source */ 22 | #define GPIO_LINE_OPEN_SOURCE 0 23 | #define GPIO_LINE_OPEN_DRAIN 4 24 | 25 | /* 26 | * Open Drain/Collector is the combination of single-ended open drain interface. 27 | * Open Source/Emitter is the combination of single-ended open source interface. 28 | */ 29 | #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) 30 | #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) 31 | 32 | /* Bit 3 express GPIO suspend/resume and reset persistence */ 33 | #define GPIO_PERSISTENT 0 34 | #define GPIO_TRANSITORY 8 35 | 36 | /* Bit 4 express pull up */ 37 | #define GPIO_PULL_UP 16 38 | 39 | /* Bit 5 express pull down */ 40 | #define GPIO_PULL_DOWN 32 41 | 42 | /* Bit 6 express pull disable */ 43 | #define GPIO_PULL_DISABLE 64 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson-a1-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 | * Author: Qianggui Song 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_MESON_A1_GPIO_H 8 | #define _DT_BINDINGS_MESON_A1_GPIO_H 9 | 10 | #define GPIOP_0 0 11 | #define GPIOP_1 1 12 | #define GPIOP_2 2 13 | #define GPIOP_3 3 14 | #define GPIOP_4 4 15 | #define GPIOP_5 5 16 | #define GPIOP_6 6 17 | #define GPIOP_7 7 18 | #define GPIOP_8 8 19 | #define GPIOP_9 9 20 | #define GPIOP_10 10 21 | #define GPIOP_11 11 22 | #define GPIOP_12 12 23 | #define GPIOB_0 13 24 | #define GPIOB_1 14 25 | #define GPIOB_2 15 26 | #define GPIOB_3 16 27 | #define GPIOB_4 17 28 | #define GPIOB_5 18 29 | #define GPIOB_6 19 30 | #define GPIOX_0 20 31 | #define GPIOX_1 21 32 | #define GPIOX_2 22 33 | #define GPIOX_3 23 34 | #define GPIOX_4 24 35 | #define GPIOX_5 25 36 | #define GPIOX_6 26 37 | #define GPIOX_7 27 38 | #define GPIOX_8 28 39 | #define GPIOX_9 29 40 | #define GPIOX_10 30 41 | #define GPIOX_11 31 42 | #define GPIOX_12 32 43 | #define GPIOX_13 33 44 | #define GPIOX_14 34 45 | #define GPIOX_15 35 46 | #define GPIOX_16 36 47 | #define GPIOF_0 37 48 | #define GPIOF_1 38 49 | #define GPIOF_2 39 50 | #define GPIOF_3 40 51 | #define GPIOF_4 41 52 | #define GPIOF_5 42 53 | #define GPIOF_6 43 54 | #define GPIOF_7 44 55 | #define GPIOF_8 45 56 | #define GPIOF_9 46 57 | #define GPIOF_10 47 58 | #define GPIOF_11 48 59 | #define GPIOF_12 49 60 | #define GPIOA_0 50 61 | #define GPIOA_1 51 62 | #define GPIOA_2 52 63 | #define GPIOA_3 53 64 | #define GPIOA_4 54 65 | #define GPIOA_5 55 66 | #define GPIOA_6 56 67 | #define GPIOA_7 57 68 | #define GPIOA_8 58 69 | #define GPIOA_9 59 70 | #define GPIOA_10 60 71 | #define GPIOA_11 61 72 | 73 | #endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ 74 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson-axg-gpio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 | * Author: Xingyu Chen 4 | * 5 | * SPDX-License-Identifier: GPL-2.0+ 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_MESON_AXG_GPIO_H 9 | #define _DT_BINDINGS_MESON_AXG_GPIO_H 10 | 11 | /* First GPIO chip */ 12 | #define GPIOAO_0 0 13 | #define GPIOAO_1 1 14 | #define GPIOAO_2 2 15 | #define GPIOAO_3 3 16 | #define GPIOAO_4 4 17 | #define GPIOAO_5 5 18 | #define GPIOAO_6 6 19 | #define GPIOAO_7 7 20 | #define GPIOAO_8 8 21 | #define GPIOAO_9 9 22 | #define GPIOAO_10 10 23 | #define GPIOAO_11 11 24 | #define GPIOAO_12 12 25 | #define GPIOAO_13 13 26 | #define GPIO_TEST_N 14 27 | 28 | /* Second GPIO chip */ 29 | #define GPIOZ_0 0 30 | #define GPIOZ_1 1 31 | #define GPIOZ_2 2 32 | #define GPIOZ_3 3 33 | #define GPIOZ_4 4 34 | #define GPIOZ_5 5 35 | #define GPIOZ_6 6 36 | #define GPIOZ_7 7 37 | #define GPIOZ_8 8 38 | #define GPIOZ_9 9 39 | #define GPIOZ_10 10 40 | #define BOOT_0 11 41 | #define BOOT_1 12 42 | #define BOOT_2 13 43 | #define BOOT_3 14 44 | #define BOOT_4 15 45 | #define BOOT_5 16 46 | #define BOOT_6 17 47 | #define BOOT_7 18 48 | #define BOOT_8 19 49 | #define BOOT_9 20 50 | #define BOOT_10 21 51 | #define BOOT_11 22 52 | #define BOOT_12 23 53 | #define BOOT_13 24 54 | #define BOOT_14 25 55 | #define GPIOA_0 26 56 | #define GPIOA_1 27 57 | #define GPIOA_2 28 58 | #define GPIOA_3 29 59 | #define GPIOA_4 30 60 | #define GPIOA_5 31 61 | #define GPIOA_6 32 62 | #define GPIOA_7 33 63 | #define GPIOA_8 34 64 | #define GPIOA_9 35 65 | #define GPIOA_10 36 66 | #define GPIOA_11 37 67 | #define GPIOA_12 38 68 | #define GPIOA_13 39 69 | #define GPIOA_14 40 70 | #define GPIOA_15 41 71 | #define GPIOA_16 42 72 | #define GPIOA_17 43 73 | #define GPIOA_18 44 74 | #define GPIOA_19 45 75 | #define GPIOA_20 46 76 | #define GPIOX_0 47 77 | #define GPIOX_1 48 78 | #define GPIOX_2 49 79 | #define GPIOX_3 50 80 | #define GPIOX_4 51 81 | #define GPIOX_5 52 82 | #define GPIOX_6 53 83 | #define GPIOX_7 54 84 | #define GPIOX_8 55 85 | #define GPIOX_9 56 86 | #define GPIOX_10 57 87 | #define GPIOX_11 58 88 | #define GPIOX_12 59 89 | #define GPIOX_13 60 90 | #define GPIOX_14 61 91 | #define GPIOX_15 62 92 | #define GPIOX_16 63 93 | #define GPIOX_17 64 94 | #define GPIOX_18 65 95 | #define GPIOX_19 66 96 | #define GPIOX_20 67 97 | #define GPIOX_21 68 98 | #define GPIOX_22 69 99 | #define GPIOY_0 70 100 | #define GPIOY_1 71 101 | #define GPIOY_2 72 102 | #define GPIOY_3 73 103 | #define GPIOY_4 74 104 | #define GPIOY_5 75 105 | #define GPIOY_6 76 106 | #define GPIOY_7 77 107 | #define GPIOY_8 78 108 | #define GPIOY_9 79 109 | #define GPIOY_10 80 110 | #define GPIOY_11 81 111 | #define GPIOY_12 82 112 | #define GPIOY_13 83 113 | #define GPIOY_14 84 114 | #define GPIOY_15 85 115 | 116 | #endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */ 117 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson-g12a-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ 2 | /* 3 | * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 | * Author: Xingyu Chen 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_MESON_G12A_GPIO_H 8 | #define _DT_BINDINGS_MESON_G12A_GPIO_H 9 | 10 | /* First GPIO chip */ 11 | #define GPIOAO_0 0 12 | #define GPIOAO_1 1 13 | #define GPIOAO_2 2 14 | #define GPIOAO_3 3 15 | #define GPIOAO_4 4 16 | #define GPIOAO_5 5 17 | #define GPIOAO_6 6 18 | #define GPIOAO_7 7 19 | #define GPIOAO_8 8 20 | #define GPIOAO_9 9 21 | #define GPIOAO_10 10 22 | #define GPIOAO_11 11 23 | #define GPIOE_0 12 24 | #define GPIOE_1 13 25 | #define GPIOE_2 14 26 | 27 | /* Second GPIO chip */ 28 | #define GPIOZ_0 0 29 | #define GPIOZ_1 1 30 | #define GPIOZ_2 2 31 | #define GPIOZ_3 3 32 | #define GPIOZ_4 4 33 | #define GPIOZ_5 5 34 | #define GPIOZ_6 6 35 | #define GPIOZ_7 7 36 | #define GPIOZ_8 8 37 | #define GPIOZ_9 9 38 | #define GPIOZ_10 10 39 | #define GPIOZ_11 11 40 | #define GPIOZ_12 12 41 | #define GPIOZ_13 13 42 | #define GPIOZ_14 14 43 | #define GPIOZ_15 15 44 | #define GPIOH_0 16 45 | #define GPIOH_1 17 46 | #define GPIOH_2 18 47 | #define GPIOH_3 19 48 | #define GPIOH_4 20 49 | #define GPIOH_5 21 50 | #define GPIOH_6 22 51 | #define GPIOH_7 23 52 | #define GPIOH_8 24 53 | #define BOOT_0 25 54 | #define BOOT_1 26 55 | #define BOOT_2 27 56 | #define BOOT_3 28 57 | #define BOOT_4 29 58 | #define BOOT_5 30 59 | #define BOOT_6 31 60 | #define BOOT_7 32 61 | #define BOOT_8 33 62 | #define BOOT_9 34 63 | #define BOOT_10 35 64 | #define BOOT_11 36 65 | #define BOOT_12 37 66 | #define BOOT_13 38 67 | #define BOOT_14 39 68 | #define BOOT_15 40 69 | #define GPIOC_0 41 70 | #define GPIOC_1 42 71 | #define GPIOC_2 43 72 | #define GPIOC_3 44 73 | #define GPIOC_4 45 74 | #define GPIOC_5 46 75 | #define GPIOC_6 47 76 | #define GPIOC_7 48 77 | #define GPIOA_0 49 78 | #define GPIOA_1 50 79 | #define GPIOA_2 51 80 | #define GPIOA_3 52 81 | #define GPIOA_4 53 82 | #define GPIOA_5 54 83 | #define GPIOA_6 55 84 | #define GPIOA_7 56 85 | #define GPIOA_8 57 86 | #define GPIOA_9 58 87 | #define GPIOA_10 59 88 | #define GPIOA_11 60 89 | #define GPIOA_12 61 90 | #define GPIOA_13 62 91 | #define GPIOA_14 63 92 | #define GPIOA_15 64 93 | #define GPIOX_0 65 94 | #define GPIOX_1 66 95 | #define GPIOX_2 67 96 | #define GPIOX_3 68 97 | #define GPIOX_4 69 98 | #define GPIOX_5 70 99 | #define GPIOX_6 71 100 | #define GPIOX_7 72 101 | #define GPIOX_8 73 102 | #define GPIOX_9 74 103 | #define GPIOX_10 75 104 | #define GPIOX_11 76 105 | #define GPIOX_12 77 106 | #define GPIOX_13 78 107 | #define GPIOX_14 79 108 | #define GPIOX_15 80 109 | #define GPIOX_16 81 110 | #define GPIOX_17 82 111 | #define GPIOX_18 83 112 | #define GPIOX_19 84 113 | 114 | #endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ 115 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson-gxbb-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * GPIO definitions for Amlogic Meson GXBB SoCs 4 | * 5 | * Copyright (C) 2016 Endless Mobile, Inc. 6 | * Author: Carlo Caione 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H 10 | #define _DT_BINDINGS_MESON_GXBB_GPIO_H 11 | 12 | #define GPIOAO_0 0 13 | #define GPIOAO_1 1 14 | #define GPIOAO_2 2 15 | #define GPIOAO_3 3 16 | #define GPIOAO_4 4 17 | #define GPIOAO_5 5 18 | #define GPIOAO_6 6 19 | #define GPIOAO_7 7 20 | #define GPIOAO_8 8 21 | #define GPIOAO_9 9 22 | #define GPIOAO_10 10 23 | #define GPIOAO_11 11 24 | #define GPIOAO_12 12 25 | #define GPIOAO_13 13 26 | #define GPIO_TEST_N 14 27 | 28 | #define GPIOZ_0 0 29 | #define GPIOZ_1 1 30 | #define GPIOZ_2 2 31 | #define GPIOZ_3 3 32 | #define GPIOZ_4 4 33 | #define GPIOZ_5 5 34 | #define GPIOZ_6 6 35 | #define GPIOZ_7 7 36 | #define GPIOZ_8 8 37 | #define GPIOZ_9 9 38 | #define GPIOZ_10 10 39 | #define GPIOZ_11 11 40 | #define GPIOZ_12 12 41 | #define GPIOZ_13 13 42 | #define GPIOZ_14 14 43 | #define GPIOZ_15 15 44 | #define GPIOH_0 16 45 | #define GPIOH_1 17 46 | #define GPIOH_2 18 47 | #define GPIOH_3 19 48 | #define BOOT_0 20 49 | #define BOOT_1 21 50 | #define BOOT_2 22 51 | #define BOOT_3 23 52 | #define BOOT_4 24 53 | #define BOOT_5 25 54 | #define BOOT_6 26 55 | #define BOOT_7 27 56 | #define BOOT_8 28 57 | #define BOOT_9 29 58 | #define BOOT_10 30 59 | #define BOOT_11 31 60 | #define BOOT_12 32 61 | #define BOOT_13 33 62 | #define BOOT_14 34 63 | #define BOOT_15 35 64 | #define BOOT_16 36 65 | #define BOOT_17 37 66 | #define CARD_0 38 67 | #define CARD_1 39 68 | #define CARD_2 40 69 | #define CARD_3 41 70 | #define CARD_4 42 71 | #define CARD_5 43 72 | #define CARD_6 44 73 | #define GPIODV_0 45 74 | #define GPIODV_1 46 75 | #define GPIODV_2 47 76 | #define GPIODV_3 48 77 | #define GPIODV_4 49 78 | #define GPIODV_5 50 79 | #define GPIODV_6 51 80 | #define GPIODV_7 52 81 | #define GPIODV_8 53 82 | #define GPIODV_9 54 83 | #define GPIODV_10 55 84 | #define GPIODV_11 56 85 | #define GPIODV_12 57 86 | #define GPIODV_13 58 87 | #define GPIODV_14 59 88 | #define GPIODV_15 60 89 | #define GPIODV_16 61 90 | #define GPIODV_17 62 91 | #define GPIODV_18 63 92 | #define GPIODV_19 64 93 | #define GPIODV_20 65 94 | #define GPIODV_21 66 95 | #define GPIODV_22 67 96 | #define GPIODV_23 68 97 | #define GPIODV_24 69 98 | #define GPIODV_25 70 99 | #define GPIODV_26 71 100 | #define GPIODV_27 72 101 | #define GPIODV_28 73 102 | #define GPIODV_29 74 103 | #define GPIOY_0 75 104 | #define GPIOY_1 76 105 | #define GPIOY_2 77 106 | #define GPIOY_3 78 107 | #define GPIOY_4 79 108 | #define GPIOY_5 80 109 | #define GPIOY_6 81 110 | #define GPIOY_7 82 111 | #define GPIOY_8 83 112 | #define GPIOY_9 84 113 | #define GPIOY_10 85 114 | #define GPIOY_11 86 115 | #define GPIOY_12 87 116 | #define GPIOY_13 88 117 | #define GPIOY_14 89 118 | #define GPIOY_15 90 119 | #define GPIOY_16 91 120 | #define GPIOX_0 92 121 | #define GPIOX_1 93 122 | #define GPIOX_2 94 123 | #define GPIOX_3 95 124 | #define GPIOX_4 96 125 | #define GPIOX_5 97 126 | #define GPIOX_6 98 127 | #define GPIOX_7 99 128 | #define GPIOX_8 100 129 | #define GPIOX_9 101 130 | #define GPIOX_10 102 131 | #define GPIOX_11 103 132 | #define GPIOX_12 104 133 | #define GPIOX_13 105 134 | #define GPIOX_14 106 135 | #define GPIOX_15 107 136 | #define GPIOX_16 108 137 | #define GPIOX_17 109 138 | #define GPIOX_18 110 139 | #define GPIOX_19 111 140 | #define GPIOX_20 112 141 | #define GPIOX_21 113 142 | #define GPIOX_22 114 143 | #define GPIOCLK_0 115 144 | #define GPIOCLK_1 116 145 | #define GPIOCLK_2 117 146 | #define GPIOCLK_3 118 147 | 148 | #endif 149 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson-gxl-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * GPIO definitions for Amlogic Meson GXL SoCs 4 | * 5 | * Copyright (C) 2016 Endless Mobile, Inc. 6 | * Author: Carlo Caione 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_MESON_GXL_GPIO_H 10 | #define _DT_BINDINGS_MESON_GXL_GPIO_H 11 | 12 | #define GPIOAO_0 0 13 | #define GPIOAO_1 1 14 | #define GPIOAO_2 2 15 | #define GPIOAO_3 3 16 | #define GPIOAO_4 4 17 | #define GPIOAO_5 5 18 | #define GPIOAO_6 6 19 | #define GPIOAO_7 7 20 | #define GPIOAO_8 8 21 | #define GPIOAO_9 9 22 | #define GPIO_TEST_N 10 23 | 24 | #define GPIOZ_0 0 25 | #define GPIOZ_1 1 26 | #define GPIOZ_2 2 27 | #define GPIOZ_3 3 28 | #define GPIOZ_4 4 29 | #define GPIOZ_5 5 30 | #define GPIOZ_6 6 31 | #define GPIOZ_7 7 32 | #define GPIOZ_8 8 33 | #define GPIOZ_9 9 34 | #define GPIOZ_10 10 35 | #define GPIOZ_11 11 36 | #define GPIOZ_12 12 37 | #define GPIOZ_13 13 38 | #define GPIOZ_14 14 39 | #define GPIOZ_15 15 40 | #define GPIOH_0 16 41 | #define GPIOH_1 17 42 | #define GPIOH_2 18 43 | #define GPIOH_3 19 44 | #define GPIOH_4 20 45 | #define GPIOH_5 21 46 | #define GPIOH_6 22 47 | #define GPIOH_7 23 48 | #define GPIOH_8 24 49 | #define GPIOH_9 25 50 | #define BOOT_0 26 51 | #define BOOT_1 27 52 | #define BOOT_2 28 53 | #define BOOT_3 29 54 | #define BOOT_4 30 55 | #define BOOT_5 31 56 | #define BOOT_6 32 57 | #define BOOT_7 33 58 | #define BOOT_8 34 59 | #define BOOT_9 35 60 | #define BOOT_10 36 61 | #define BOOT_11 37 62 | #define BOOT_12 38 63 | #define BOOT_13 39 64 | #define BOOT_14 40 65 | #define BOOT_15 41 66 | #define CARD_0 42 67 | #define CARD_1 43 68 | #define CARD_2 44 69 | #define CARD_3 45 70 | #define CARD_4 46 71 | #define CARD_5 47 72 | #define CARD_6 48 73 | #define GPIODV_0 49 74 | #define GPIODV_1 50 75 | #define GPIODV_2 51 76 | #define GPIODV_3 52 77 | #define GPIODV_4 53 78 | #define GPIODV_5 54 79 | #define GPIODV_6 55 80 | #define GPIODV_7 56 81 | #define GPIODV_8 57 82 | #define GPIODV_9 58 83 | #define GPIODV_10 59 84 | #define GPIODV_11 60 85 | #define GPIODV_12 61 86 | #define GPIODV_13 62 87 | #define GPIODV_14 63 88 | #define GPIODV_15 64 89 | #define GPIODV_16 65 90 | #define GPIODV_17 66 91 | #define GPIODV_18 67 92 | #define GPIODV_19 68 93 | #define GPIODV_20 69 94 | #define GPIODV_21 70 95 | #define GPIODV_22 71 96 | #define GPIODV_23 72 97 | #define GPIODV_24 73 98 | #define GPIODV_25 74 99 | #define GPIODV_26 75 100 | #define GPIODV_27 76 101 | #define GPIODV_28 77 102 | #define GPIODV_29 78 103 | #define GPIOX_0 79 104 | #define GPIOX_1 80 105 | #define GPIOX_2 81 106 | #define GPIOX_3 82 107 | #define GPIOX_4 83 108 | #define GPIOX_5 84 109 | #define GPIOX_6 85 110 | #define GPIOX_7 86 111 | #define GPIOX_8 87 112 | #define GPIOX_9 88 113 | #define GPIOX_10 89 114 | #define GPIOX_11 90 115 | #define GPIOX_12 91 116 | #define GPIOX_13 92 117 | #define GPIOX_14 93 118 | #define GPIOX_15 94 119 | #define GPIOX_16 95 120 | #define GPIOX_17 96 121 | #define GPIOX_18 97 122 | #define GPIOCLK_0 98 123 | #define GPIOCLK_1 99 124 | 125 | #endif 126 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson-s4-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 | /* 3 | * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4 | * Author: Qianggui Song 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_MESON_S4_GPIO_H 8 | #define _DT_BINDINGS_MESON_S4_GPIO_H 9 | 10 | #define GPIOB_0 0 11 | #define GPIOB_1 1 12 | #define GPIOB_2 2 13 | #define GPIOB_3 3 14 | #define GPIOB_4 4 15 | #define GPIOB_5 5 16 | #define GPIOB_6 6 17 | #define GPIOB_7 7 18 | #define GPIOB_8 8 19 | #define GPIOB_9 9 20 | #define GPIOB_10 10 21 | #define GPIOB_11 11 22 | #define GPIOB_12 12 23 | #define GPIOB_13 13 24 | 25 | #define GPIOC_0 14 26 | #define GPIOC_1 15 27 | #define GPIOC_2 16 28 | #define GPIOC_3 17 29 | #define GPIOC_4 18 30 | #define GPIOC_5 19 31 | #define GPIOC_6 20 32 | #define GPIOC_7 21 33 | 34 | #define GPIOE_0 22 35 | #define GPIOE_1 23 36 | 37 | #define GPIOD_0 24 38 | #define GPIOD_1 25 39 | #define GPIOD_2 26 40 | #define GPIOD_3 27 41 | #define GPIOD_4 28 42 | #define GPIOD_5 29 43 | #define GPIOD_6 30 44 | #define GPIOD_7 31 45 | #define GPIOD_8 32 46 | #define GPIOD_9 33 47 | #define GPIOD_10 34 48 | #define GPIOD_11 35 49 | 50 | #define GPIOH_0 36 51 | #define GPIOH_1 37 52 | #define GPIOH_2 38 53 | #define GPIOH_3 39 54 | #define GPIOH_4 40 55 | #define GPIOH_5 41 56 | #define GPIOH_6 42 57 | #define GPIOH_7 43 58 | #define GPIOH_8 44 59 | #define GPIOH_9 45 60 | #define GPIOH_10 46 61 | #define GPIOH_11 47 62 | 63 | #define GPIOX_0 48 64 | #define GPIOX_1 49 65 | #define GPIOX_2 50 66 | #define GPIOX_3 51 67 | #define GPIOX_4 52 68 | #define GPIOX_5 53 69 | #define GPIOX_6 54 70 | #define GPIOX_7 55 71 | #define GPIOX_8 56 72 | #define GPIOX_9 57 73 | #define GPIOX_10 58 74 | #define GPIOX_11 59 75 | #define GPIOX_12 60 76 | #define GPIOX_13 61 77 | #define GPIOX_14 62 78 | #define GPIOX_15 63 79 | #define GPIOX_16 64 80 | #define GPIOX_17 65 81 | #define GPIOX_18 66 82 | #define GPIOX_19 67 83 | 84 | #define GPIOZ_0 68 85 | #define GPIOZ_1 69 86 | #define GPIOZ_2 70 87 | #define GPIOZ_3 71 88 | #define GPIOZ_4 72 89 | #define GPIOZ_5 73 90 | #define GPIOZ_6 74 91 | #define GPIOZ_7 75 92 | #define GPIOZ_8 76 93 | #define GPIOZ_9 77 94 | #define GPIOZ_10 78 95 | #define GPIOZ_11 79 96 | #define GPIOZ_12 80 97 | 98 | #define GPIO_TEST_N 81 99 | #endif /* _DT_BINDINGS_MESON_S4_GPIO_H */ 100 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson8-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * GPIO definitions for Amlogic Meson8 SoCs 4 | * 5 | * Copyright (C) 2014 Beniamino Galvani 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_MESON8_GPIO_H 9 | #define _DT_BINDINGS_MESON8_GPIO_H 10 | 11 | /* First GPIO chip */ 12 | #define GPIOX_0 0 13 | #define GPIOX_1 1 14 | #define GPIOX_2 2 15 | #define GPIOX_3 3 16 | #define GPIOX_4 4 17 | #define GPIOX_5 5 18 | #define GPIOX_6 6 19 | #define GPIOX_7 7 20 | #define GPIOX_8 8 21 | #define GPIOX_9 9 22 | #define GPIOX_10 10 23 | #define GPIOX_11 11 24 | #define GPIOX_12 12 25 | #define GPIOX_13 13 26 | #define GPIOX_14 14 27 | #define GPIOX_15 15 28 | #define GPIOX_16 16 29 | #define GPIOX_17 17 30 | #define GPIOX_18 18 31 | #define GPIOX_19 19 32 | #define GPIOX_20 20 33 | #define GPIOX_21 21 34 | #define GPIOY_0 22 35 | #define GPIOY_1 23 36 | #define GPIOY_2 24 37 | #define GPIOY_3 25 38 | #define GPIOY_4 26 39 | #define GPIOY_5 27 40 | #define GPIOY_6 28 41 | #define GPIOY_7 29 42 | #define GPIOY_8 30 43 | #define GPIOY_9 31 44 | #define GPIOY_10 32 45 | #define GPIOY_11 33 46 | #define GPIOY_12 34 47 | #define GPIOY_13 35 48 | #define GPIOY_14 36 49 | #define GPIOY_15 37 50 | #define GPIOY_16 38 51 | #define GPIODV_0 39 52 | #define GPIODV_1 40 53 | #define GPIODV_2 41 54 | #define GPIODV_3 42 55 | #define GPIODV_4 43 56 | #define GPIODV_5 44 57 | #define GPIODV_6 45 58 | #define GPIODV_7 46 59 | #define GPIODV_8 47 60 | #define GPIODV_9 48 61 | #define GPIODV_10 49 62 | #define GPIODV_11 50 63 | #define GPIODV_12 51 64 | #define GPIODV_13 52 65 | #define GPIODV_14 53 66 | #define GPIODV_15 54 67 | #define GPIODV_16 55 68 | #define GPIODV_17 56 69 | #define GPIODV_18 57 70 | #define GPIODV_19 58 71 | #define GPIODV_20 59 72 | #define GPIODV_21 60 73 | #define GPIODV_22 61 74 | #define GPIODV_23 62 75 | #define GPIODV_24 63 76 | #define GPIODV_25 64 77 | #define GPIODV_26 65 78 | #define GPIODV_27 66 79 | #define GPIODV_28 67 80 | #define GPIODV_29 68 81 | #define GPIOH_0 69 82 | #define GPIOH_1 70 83 | #define GPIOH_2 71 84 | #define GPIOH_3 72 85 | #define GPIOH_4 73 86 | #define GPIOH_5 74 87 | #define GPIOH_6 75 88 | #define GPIOH_7 76 89 | #define GPIOH_8 77 90 | #define GPIOH_9 78 91 | #define GPIOZ_0 79 92 | #define GPIOZ_1 80 93 | #define GPIOZ_2 81 94 | #define GPIOZ_3 82 95 | #define GPIOZ_4 83 96 | #define GPIOZ_5 84 97 | #define GPIOZ_6 85 98 | #define GPIOZ_7 86 99 | #define GPIOZ_8 87 100 | #define GPIOZ_9 88 101 | #define GPIOZ_10 89 102 | #define GPIOZ_11 90 103 | #define GPIOZ_12 91 104 | #define GPIOZ_13 92 105 | #define GPIOZ_14 93 106 | #define CARD_0 94 107 | #define CARD_1 95 108 | #define CARD_2 96 109 | #define CARD_3 97 110 | #define CARD_4 98 111 | #define CARD_5 99 112 | #define CARD_6 100 113 | #define BOOT_0 101 114 | #define BOOT_1 102 115 | #define BOOT_2 103 116 | #define BOOT_3 104 117 | #define BOOT_4 105 118 | #define BOOT_5 106 119 | #define BOOT_6 107 120 | #define BOOT_7 108 121 | #define BOOT_8 109 122 | #define BOOT_9 110 123 | #define BOOT_10 111 124 | #define BOOT_11 112 125 | #define BOOT_12 113 126 | #define BOOT_13 114 127 | #define BOOT_14 115 128 | #define BOOT_15 116 129 | #define BOOT_16 117 130 | #define BOOT_17 118 131 | #define BOOT_18 119 132 | 133 | /* Second GPIO chip */ 134 | #define GPIOAO_0 0 135 | #define GPIOAO_1 1 136 | #define GPIOAO_2 2 137 | #define GPIOAO_3 3 138 | #define GPIOAO_4 4 139 | #define GPIOAO_5 5 140 | #define GPIOAO_6 6 141 | #define GPIOAO_7 7 142 | #define GPIOAO_8 8 143 | #define GPIOAO_9 9 144 | #define GPIOAO_10 10 145 | #define GPIOAO_11 11 146 | #define GPIOAO_12 12 147 | #define GPIOAO_13 13 148 | #define GPIO_BSD_EN 14 149 | #define GPIO_TEST_N 15 150 | 151 | #endif /* _DT_BINDINGS_MESON8_GPIO_H */ 152 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/meson8b-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * GPIO definitions for Amlogic Meson8b SoCs 4 | * 5 | * Copyright (C) 2015 Endless Mobile, Inc. 6 | * Author: Carlo Caione 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_MESON8B_GPIO_H 10 | #define _DT_BINDINGS_MESON8B_GPIO_H 11 | 12 | /* EE (CBUS) GPIO chip */ 13 | #define GPIOX_0 0 14 | #define GPIOX_1 1 15 | #define GPIOX_2 2 16 | #define GPIOX_3 3 17 | #define GPIOX_4 4 18 | #define GPIOX_5 5 19 | #define GPIOX_6 6 20 | #define GPIOX_7 7 21 | #define GPIOX_8 8 22 | #define GPIOX_9 9 23 | #define GPIOX_10 10 24 | #define GPIOX_11 11 25 | #define GPIOX_16 12 26 | #define GPIOX_17 13 27 | #define GPIOX_18 14 28 | #define GPIOX_19 15 29 | #define GPIOX_20 16 30 | #define GPIOX_21 17 31 | 32 | #define GPIOY_0 18 33 | #define GPIOY_1 19 34 | #define GPIOY_3 20 35 | #define GPIOY_6 21 36 | #define GPIOY_7 22 37 | #define GPIOY_8 23 38 | #define GPIOY_9 24 39 | #define GPIOY_10 25 40 | #define GPIOY_11 26 41 | #define GPIOY_12 27 42 | #define GPIOY_13 28 43 | #define GPIOY_14 29 44 | 45 | #define GPIODV_9 30 46 | #define GPIODV_24 31 47 | #define GPIODV_25 32 48 | #define GPIODV_26 33 49 | #define GPIODV_27 34 50 | #define GPIODV_28 35 51 | #define GPIODV_29 36 52 | 53 | #define GPIOH_0 37 54 | #define GPIOH_1 38 55 | #define GPIOH_2 39 56 | #define GPIOH_3 40 57 | #define GPIOH_4 41 58 | #define GPIOH_5 42 59 | #define GPIOH_6 43 60 | #define GPIOH_7 44 61 | #define GPIOH_8 45 62 | #define GPIOH_9 46 63 | 64 | #define CARD_0 47 65 | #define CARD_1 48 66 | #define CARD_2 49 67 | #define CARD_3 50 68 | #define CARD_4 51 69 | #define CARD_5 52 70 | #define CARD_6 53 71 | 72 | #define BOOT_0 54 73 | #define BOOT_1 55 74 | #define BOOT_2 56 75 | #define BOOT_3 57 76 | #define BOOT_4 58 77 | #define BOOT_5 59 78 | #define BOOT_6 60 79 | #define BOOT_7 61 80 | #define BOOT_8 62 81 | #define BOOT_9 63 82 | #define BOOT_10 64 83 | #define BOOT_11 65 84 | #define BOOT_12 66 85 | #define BOOT_13 67 86 | #define BOOT_14 68 87 | #define BOOT_15 69 88 | #define BOOT_16 70 89 | #define BOOT_17 71 90 | #define BOOT_18 72 91 | 92 | #define DIF_0_P 73 93 | #define DIF_0_N 74 94 | #define DIF_1_P 75 95 | #define DIF_1_N 76 96 | #define DIF_2_P 77 97 | #define DIF_2_N 78 98 | #define DIF_3_P 79 99 | #define DIF_3_N 80 100 | #define DIF_4_P 81 101 | #define DIF_4_N 82 102 | 103 | /* AO GPIO chip */ 104 | #define GPIOAO_0 0 105 | #define GPIOAO_1 1 106 | #define GPIOAO_2 2 107 | #define GPIOAO_3 3 108 | #define GPIOAO_4 4 109 | #define GPIOAO_5 5 110 | #define GPIOAO_6 6 111 | #define GPIOAO_7 7 112 | #define GPIOAO_8 8 113 | #define GPIOAO_9 9 114 | #define GPIOAO_10 10 115 | #define GPIOAO_11 11 116 | #define GPIOAO_12 12 117 | #define GPIOAO_13 13 118 | #define GPIO_BSD_EN 14 119 | #define GPIO_TEST_N 15 120 | 121 | #endif /* _DT_BINDINGS_MESON8B_GPIO_H */ 122 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/msc313-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 | /* 3 | * GPIO definitions for MStar/SigmaStar MSC313 and later SoCs 4 | * 5 | * Copyright (C) 2020 Daniel Palmer 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_MSC313_GPIO_H 9 | #define _DT_BINDINGS_MSC313_GPIO_H 10 | 11 | #define MSC313_GPIO_FUART 0 12 | #define MSC313_GPIO_FUART_RX (MSC313_GPIO_FUART + 0) 13 | #define MSC313_GPIO_FUART_TX (MSC313_GPIO_FUART + 1) 14 | #define MSC313_GPIO_FUART_CTS (MSC313_GPIO_FUART + 2) 15 | #define MSC313_GPIO_FUART_RTS (MSC313_GPIO_FUART + 3) 16 | 17 | #define MSC313_GPIO_SR (MSC313_GPIO_FUART_RTS + 1) 18 | #define MSC313_GPIO_SR_IO2 (MSC313_GPIO_SR + 0) 19 | #define MSC313_GPIO_SR_IO3 (MSC313_GPIO_SR + 1) 20 | #define MSC313_GPIO_SR_IO4 (MSC313_GPIO_SR + 2) 21 | #define MSC313_GPIO_SR_IO5 (MSC313_GPIO_SR + 3) 22 | #define MSC313_GPIO_SR_IO6 (MSC313_GPIO_SR + 4) 23 | #define MSC313_GPIO_SR_IO7 (MSC313_GPIO_SR + 5) 24 | #define MSC313_GPIO_SR_IO8 (MSC313_GPIO_SR + 6) 25 | #define MSC313_GPIO_SR_IO9 (MSC313_GPIO_SR + 7) 26 | #define MSC313_GPIO_SR_IO10 (MSC313_GPIO_SR + 8) 27 | #define MSC313_GPIO_SR_IO11 (MSC313_GPIO_SR + 9) 28 | #define MSC313_GPIO_SR_IO12 (MSC313_GPIO_SR + 10) 29 | #define MSC313_GPIO_SR_IO13 (MSC313_GPIO_SR + 11) 30 | #define MSC313_GPIO_SR_IO14 (MSC313_GPIO_SR + 12) 31 | #define MSC313_GPIO_SR_IO15 (MSC313_GPIO_SR + 13) 32 | #define MSC313_GPIO_SR_IO16 (MSC313_GPIO_SR + 14) 33 | #define MSC313_GPIO_SR_IO17 (MSC313_GPIO_SR + 15) 34 | 35 | #define MSC313_GPIO_SD (MSC313_GPIO_SR_IO17 + 1) 36 | #define MSC313_GPIO_SD_CLK (MSC313_GPIO_SD + 0) 37 | #define MSC313_GPIO_SD_CMD (MSC313_GPIO_SD + 1) 38 | #define MSC313_GPIO_SD_D0 (MSC313_GPIO_SD + 2) 39 | #define MSC313_GPIO_SD_D1 (MSC313_GPIO_SD + 3) 40 | #define MSC313_GPIO_SD_D2 (MSC313_GPIO_SD + 4) 41 | #define MSC313_GPIO_SD_D3 (MSC313_GPIO_SD + 5) 42 | 43 | #define MSC313_GPIO_I2C1 (MSC313_GPIO_SD_D3 + 1) 44 | #define MSC313_GPIO_I2C1_SCL (MSC313_GPIO_I2C1 + 0) 45 | #define MSC313_GPIO_I2C1_SDA (MSC313_GPIO_I2C1 + 1) 46 | 47 | #define MSC313_GPIO_SPI0 (MSC313_GPIO_I2C1_SDA + 1) 48 | #define MSC313_GPIO_SPI0_CZ (MSC313_GPIO_SPI0 + 0) 49 | #define MSC313_GPIO_SPI0_CK (MSC313_GPIO_SPI0 + 1) 50 | #define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) 51 | #define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) 52 | 53 | /* SSD20x */ 54 | #define SSD20XD_GPIO_FUART 0 55 | #define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0) 56 | #define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1) 57 | #define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2) 58 | #define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3) 59 | 60 | #define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1) 61 | #define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0) 62 | #define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1) 63 | #define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2) 64 | #define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3) 65 | #define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4) 66 | #define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5) 67 | 68 | #define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1) 69 | #define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0) 70 | #define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1) 71 | 72 | #define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1) 73 | #define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0) 74 | #define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1) 75 | 76 | #define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1) 77 | #define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0) 78 | #define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1) 79 | #define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2) 80 | #define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3) 81 | #define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4) 82 | #define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5) 83 | #define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6) 84 | #define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7) 85 | #define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8) 86 | #define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9) 87 | #define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10) 88 | #define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11) 89 | #define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12) 90 | #define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13) 91 | #define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14) 92 | #define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15) 93 | #define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16) 94 | #define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17) 95 | #define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18) 96 | #define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19) 97 | #define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20) 98 | #define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21) 99 | #define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22) 100 | #define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23) 101 | #define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24) 102 | #define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25) 103 | #define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26) 104 | #define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27) 105 | 106 | #define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1) 107 | #define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0) 108 | #define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1) 109 | #define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2) 110 | #define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3) 111 | #define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4) 112 | #define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5) 113 | #define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6) 114 | #define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7) 115 | #define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8) 116 | #define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9) 117 | #define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10) 118 | #define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11) 119 | #define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12) 120 | #define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13) 121 | #define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14) 122 | #define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15) 123 | 124 | #endif /* _DT_BINDINGS_MSC313_GPIO_H */ 125 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/tegra-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for binding nvidia,tegra*-gpio. 4 | * 5 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 6 | * provide names for this. 7 | * 8 | * The second cell contains standard flag values specified in gpio.h. 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H 12 | #define _DT_BINDINGS_GPIO_TEGRA_GPIO_H 13 | 14 | #include 15 | 16 | #define TEGRA_GPIO_PORT_A 0 17 | #define TEGRA_GPIO_PORT_B 1 18 | #define TEGRA_GPIO_PORT_C 2 19 | #define TEGRA_GPIO_PORT_D 3 20 | #define TEGRA_GPIO_PORT_E 4 21 | #define TEGRA_GPIO_PORT_F 5 22 | #define TEGRA_GPIO_PORT_G 6 23 | #define TEGRA_GPIO_PORT_H 7 24 | #define TEGRA_GPIO_PORT_I 8 25 | #define TEGRA_GPIO_PORT_J 9 26 | #define TEGRA_GPIO_PORT_K 10 27 | #define TEGRA_GPIO_PORT_L 11 28 | #define TEGRA_GPIO_PORT_M 12 29 | #define TEGRA_GPIO_PORT_N 13 30 | #define TEGRA_GPIO_PORT_O 14 31 | #define TEGRA_GPIO_PORT_P 15 32 | #define TEGRA_GPIO_PORT_Q 16 33 | #define TEGRA_GPIO_PORT_R 17 34 | #define TEGRA_GPIO_PORT_S 18 35 | #define TEGRA_GPIO_PORT_T 19 36 | #define TEGRA_GPIO_PORT_U 20 37 | #define TEGRA_GPIO_PORT_V 21 38 | #define TEGRA_GPIO_PORT_W 22 39 | #define TEGRA_GPIO_PORT_X 23 40 | #define TEGRA_GPIO_PORT_Y 24 41 | #define TEGRA_GPIO_PORT_Z 25 42 | #define TEGRA_GPIO_PORT_AA 26 43 | #define TEGRA_GPIO_PORT_BB 27 44 | #define TEGRA_GPIO_PORT_CC 28 45 | #define TEGRA_GPIO_PORT_DD 29 46 | #define TEGRA_GPIO_PORT_EE 30 47 | #define TEGRA_GPIO_PORT_FF 31 48 | 49 | #define TEGRA_GPIO(port, offset) \ 50 | ((TEGRA_GPIO_PORT_##port * 8) + offset) 51 | 52 | #endif 53 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/tegra186-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for binding nvidia,tegra186-gpio*. 4 | * 5 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 6 | * provide names for this. 7 | * 8 | * The second cell contains standard flag values specified in gpio.h. 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H 12 | #define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H 13 | 14 | #include 15 | 16 | /* GPIOs implemented by main GPIO controller */ 17 | #define TEGRA186_MAIN_GPIO_PORT_A 0 18 | #define TEGRA186_MAIN_GPIO_PORT_B 1 19 | #define TEGRA186_MAIN_GPIO_PORT_C 2 20 | #define TEGRA186_MAIN_GPIO_PORT_D 3 21 | #define TEGRA186_MAIN_GPIO_PORT_E 4 22 | #define TEGRA186_MAIN_GPIO_PORT_F 5 23 | #define TEGRA186_MAIN_GPIO_PORT_G 6 24 | #define TEGRA186_MAIN_GPIO_PORT_H 7 25 | #define TEGRA186_MAIN_GPIO_PORT_I 8 26 | #define TEGRA186_MAIN_GPIO_PORT_J 9 27 | #define TEGRA186_MAIN_GPIO_PORT_K 10 28 | #define TEGRA186_MAIN_GPIO_PORT_L 11 29 | #define TEGRA186_MAIN_GPIO_PORT_M 12 30 | #define TEGRA186_MAIN_GPIO_PORT_N 13 31 | #define TEGRA186_MAIN_GPIO_PORT_O 14 32 | #define TEGRA186_MAIN_GPIO_PORT_P 15 33 | #define TEGRA186_MAIN_GPIO_PORT_Q 16 34 | #define TEGRA186_MAIN_GPIO_PORT_R 17 35 | #define TEGRA186_MAIN_GPIO_PORT_T 18 36 | #define TEGRA186_MAIN_GPIO_PORT_X 19 37 | #define TEGRA186_MAIN_GPIO_PORT_Y 20 38 | #define TEGRA186_MAIN_GPIO_PORT_BB 21 39 | #define TEGRA186_MAIN_GPIO_PORT_CC 22 40 | 41 | #define TEGRA186_MAIN_GPIO(port, offset) \ 42 | ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) 43 | 44 | /* GPIOs implemented by AON GPIO controller */ 45 | #define TEGRA186_AON_GPIO_PORT_S 0 46 | #define TEGRA186_AON_GPIO_PORT_U 1 47 | #define TEGRA186_AON_GPIO_PORT_V 2 48 | #define TEGRA186_AON_GPIO_PORT_W 3 49 | #define TEGRA186_AON_GPIO_PORT_Z 4 50 | #define TEGRA186_AON_GPIO_PORT_AA 5 51 | #define TEGRA186_AON_GPIO_PORT_EE 6 52 | #define TEGRA186_AON_GPIO_PORT_FF 7 53 | 54 | #define TEGRA186_AON_GPIO(port, offset) \ 55 | ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) 56 | 57 | #endif 58 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/tegra194-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ 3 | 4 | /* 5 | * This header provides constants for binding nvidia,tegra194-gpio*. 6 | * 7 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8 | * provide names for this. 9 | * 10 | * The second cell contains standard flag values specified in gpio.h. 11 | */ 12 | 13 | #ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 14 | #define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H 15 | 16 | #include 17 | 18 | /* GPIOs implemented by main GPIO controller */ 19 | #define TEGRA194_MAIN_GPIO_PORT_A 0 20 | #define TEGRA194_MAIN_GPIO_PORT_B 1 21 | #define TEGRA194_MAIN_GPIO_PORT_C 2 22 | #define TEGRA194_MAIN_GPIO_PORT_D 3 23 | #define TEGRA194_MAIN_GPIO_PORT_E 4 24 | #define TEGRA194_MAIN_GPIO_PORT_F 5 25 | #define TEGRA194_MAIN_GPIO_PORT_G 6 26 | #define TEGRA194_MAIN_GPIO_PORT_H 7 27 | #define TEGRA194_MAIN_GPIO_PORT_I 8 28 | #define TEGRA194_MAIN_GPIO_PORT_J 9 29 | #define TEGRA194_MAIN_GPIO_PORT_K 10 30 | #define TEGRA194_MAIN_GPIO_PORT_L 11 31 | #define TEGRA194_MAIN_GPIO_PORT_M 12 32 | #define TEGRA194_MAIN_GPIO_PORT_N 13 33 | #define TEGRA194_MAIN_GPIO_PORT_O 14 34 | #define TEGRA194_MAIN_GPIO_PORT_P 15 35 | #define TEGRA194_MAIN_GPIO_PORT_Q 16 36 | #define TEGRA194_MAIN_GPIO_PORT_R 17 37 | #define TEGRA194_MAIN_GPIO_PORT_S 18 38 | #define TEGRA194_MAIN_GPIO_PORT_T 19 39 | #define TEGRA194_MAIN_GPIO_PORT_U 20 40 | #define TEGRA194_MAIN_GPIO_PORT_V 21 41 | #define TEGRA194_MAIN_GPIO_PORT_W 22 42 | #define TEGRA194_MAIN_GPIO_PORT_X 23 43 | #define TEGRA194_MAIN_GPIO_PORT_Y 24 44 | #define TEGRA194_MAIN_GPIO_PORT_Z 25 45 | #define TEGRA194_MAIN_GPIO_PORT_FF 26 46 | #define TEGRA194_MAIN_GPIO_PORT_GG 27 47 | 48 | #define TEGRA194_MAIN_GPIO(port, offset) \ 49 | ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset) 50 | 51 | /* GPIOs implemented by AON GPIO controller */ 52 | #define TEGRA194_AON_GPIO_PORT_AA 0 53 | #define TEGRA194_AON_GPIO_PORT_BB 1 54 | #define TEGRA194_AON_GPIO_PORT_CC 2 55 | #define TEGRA194_AON_GPIO_PORT_DD 3 56 | #define TEGRA194_AON_GPIO_PORT_EE 4 57 | 58 | #define TEGRA194_AON_GPIO(port, offset) \ 59 | ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset) 60 | 61 | #endif 62 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/tegra234-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ 3 | 4 | /* 5 | * This header provides constants for binding nvidia,tegra234-gpio*. 6 | * 7 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8 | * provide names for this. 9 | * 10 | * The second cell contains standard flag values specified in gpio.h. 11 | */ 12 | 13 | #ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 14 | #define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 15 | 16 | #include 17 | 18 | /* GPIOs implemented by main GPIO controller */ 19 | #define TEGRA234_MAIN_GPIO_PORT_A 0 20 | #define TEGRA234_MAIN_GPIO_PORT_B 1 21 | #define TEGRA234_MAIN_GPIO_PORT_C 2 22 | #define TEGRA234_MAIN_GPIO_PORT_D 3 23 | #define TEGRA234_MAIN_GPIO_PORT_E 4 24 | #define TEGRA234_MAIN_GPIO_PORT_F 5 25 | #define TEGRA234_MAIN_GPIO_PORT_G 6 26 | #define TEGRA234_MAIN_GPIO_PORT_H 7 27 | #define TEGRA234_MAIN_GPIO_PORT_I 8 28 | #define TEGRA234_MAIN_GPIO_PORT_J 9 29 | #define TEGRA234_MAIN_GPIO_PORT_K 10 30 | #define TEGRA234_MAIN_GPIO_PORT_L 11 31 | #define TEGRA234_MAIN_GPIO_PORT_M 12 32 | #define TEGRA234_MAIN_GPIO_PORT_N 13 33 | #define TEGRA234_MAIN_GPIO_PORT_P 14 34 | #define TEGRA234_MAIN_GPIO_PORT_Q 15 35 | #define TEGRA234_MAIN_GPIO_PORT_R 16 36 | #define TEGRA234_MAIN_GPIO_PORT_S 17 37 | #define TEGRA234_MAIN_GPIO_PORT_T 18 38 | #define TEGRA234_MAIN_GPIO_PORT_U 19 39 | #define TEGRA234_MAIN_GPIO_PORT_V 20 40 | #define TEGRA234_MAIN_GPIO_PORT_X 21 41 | #define TEGRA234_MAIN_GPIO_PORT_Y 22 42 | #define TEGRA234_MAIN_GPIO_PORT_Z 23 43 | #define TEGRA234_MAIN_GPIO_PORT_AC 24 44 | #define TEGRA234_MAIN_GPIO_PORT_AD 25 45 | #define TEGRA234_MAIN_GPIO_PORT_AE 26 46 | #define TEGRA234_MAIN_GPIO_PORT_AF 27 47 | #define TEGRA234_MAIN_GPIO_PORT_AG 28 48 | 49 | #define TEGRA234_MAIN_GPIO(port, offset) \ 50 | ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) 51 | 52 | /* GPIOs implemented by AON GPIO controller */ 53 | #define TEGRA234_AON_GPIO_PORT_AA 0 54 | #define TEGRA234_AON_GPIO_PORT_BB 1 55 | #define TEGRA234_AON_GPIO_PORT_CC 2 56 | #define TEGRA234_AON_GPIO_PORT_DD 3 57 | #define TEGRA234_AON_GPIO_PORT_EE 4 58 | #define TEGRA234_AON_GPIO_PORT_GG 5 59 | 60 | #define TEGRA234_AON_GPIO(port, offset) \ 61 | ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) 62 | 63 | #endif 64 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/tegra241-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */ 3 | 4 | /* 5 | * This header provides constants for the nvidia,tegra241-gpio DT binding. 6 | * 7 | * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 8 | * provide names for this. 9 | * 10 | * The second cell contains standard flag values specified in gpio.h. 11 | */ 12 | 13 | #ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H 14 | #define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H 15 | 16 | #include 17 | 18 | /* GPIOs implemented by main GPIO controller */ 19 | #define TEGRA241_MAIN_GPIO_PORT_A 0 20 | #define TEGRA241_MAIN_GPIO_PORT_B 1 21 | #define TEGRA241_MAIN_GPIO_PORT_C 2 22 | #define TEGRA241_MAIN_GPIO_PORT_D 3 23 | #define TEGRA241_MAIN_GPIO_PORT_E 4 24 | #define TEGRA241_MAIN_GPIO_PORT_F 5 25 | #define TEGRA241_MAIN_GPIO_PORT_G 6 26 | #define TEGRA241_MAIN_GPIO_PORT_H 7 27 | #define TEGRA241_MAIN_GPIO_PORT_I 8 28 | #define TEGRA241_MAIN_GPIO_PORT_J 9 29 | #define TEGRA241_MAIN_GPIO_PORT_K 10 30 | #define TEGRA241_MAIN_GPIO_PORT_L 11 31 | 32 | #define TEGRA241_MAIN_GPIO(port, offset) \ 33 | ((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset)) 34 | 35 | /* GPIOs implemented by AON GPIO controller */ 36 | #define TEGRA241_AON_GPIO_PORT_AA 0 37 | #define TEGRA241_AON_GPIO_PORT_BB 1 38 | 39 | #define TEGRA241_AON_GPIO(port, offset) \ 40 | ((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset)) 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/gpio/uniphier-gpio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (C) 2017 Socionext Inc. 3 | * Author: Masahiro Yamada 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_GPIO_UNIPHIER_H 7 | #define _DT_BINDINGS_GPIO_UNIPHIER_H 8 | 9 | #define UNIPHIER_GPIO_LINES_PER_BANK 8 10 | 11 | #define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) 12 | 13 | #define UNIPHIER_GPIO_PORT(bank, line) \ 14 | ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) 15 | 16 | #define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) 17 | 18 | #endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ 19 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/apple-aic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 2 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H 3 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H 4 | 5 | #include 6 | 7 | #define AIC_IRQ 0 8 | #define AIC_FIQ 1 9 | 10 | #define AIC_TMR_HV_PHYS 0 11 | #define AIC_TMR_HV_VIRT 1 12 | #define AIC_TMR_GUEST_PHYS 2 13 | #define AIC_TMR_GUEST_VIRT 3 14 | #define AIC_CPU_PMU_E 4 15 | #define AIC_CPU_PMU_P 5 16 | 17 | #endif 18 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/arm-gic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 | /* 3 | * This header provides constants for the ARM GIC. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 7 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 8 | 9 | #include 10 | 11 | /* interrupt specifier cell 0 */ 12 | 13 | #define GIC_SPI 0 14 | #define GIC_PPI 1 15 | 16 | /* 17 | * Interrupt specifier cell 2. 18 | * The flags in irq.h are valid, plus those below. 19 | */ 20 | #define GIC_CPU_MASK_RAW(x) ((x) << 8) 21 | #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/aspeed-scu-ic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0+ */ 2 | 3 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ 4 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ 5 | 6 | #define ASPEED_SCU_IC_VGA_CURSOR_CHANGE 0 7 | #define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE 1 8 | 9 | #define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI 2 10 | #define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO 3 11 | #define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI 4 12 | #define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO 5 13 | #define ASPEED_AST2500_SCU_IC_ISSUE_MSI 6 14 | 15 | #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI 2 16 | #define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO 3 17 | #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI 4 18 | #define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO 5 19 | 20 | #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI 0 21 | #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO 1 22 | 23 | #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */ 24 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/irq-st.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * include/linux/irqchip/irq-st.h 4 | * 5 | * Copyright (C) 2014 STMicroelectronics – All Rights Reserved 6 | * 7 | * Author: Lee Jones 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H 12 | 13 | #define ST_IRQ_SYSCFG_EXT_0 0 14 | #define ST_IRQ_SYSCFG_EXT_1 1 15 | #define ST_IRQ_SYSCFG_EXT_2 2 16 | #define ST_IRQ_SYSCFG_CTI_0 3 17 | #define ST_IRQ_SYSCFG_CTI_1 4 18 | #define ST_IRQ_SYSCFG_PMU_0 5 19 | #define ST_IRQ_SYSCFG_PMU_1 6 20 | #define ST_IRQ_SYSCFG_pl310_L2 7 21 | #define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF 22 | 23 | #define ST_IRQ_SYSCFG_EXT_1_INV 0x1 24 | #define ST_IRQ_SYSCFG_EXT_2_INV 0x2 25 | #define ST_IRQ_SYSCFG_EXT_3_INV 0x4 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/irq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 | /* 3 | * This header provides constants for most IRQ bindings. 4 | * 5 | * Most IRQ bindings include a flags cell as part of the IRQ specifier. 6 | * In most cases, the format of the flags cell uses the standard values 7 | * defined in this header. 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 11 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H 12 | 13 | #define IRQ_TYPE_NONE 0 14 | #define IRQ_TYPE_EDGE_RISING 1 15 | #define IRQ_TYPE_EDGE_FALLING 2 16 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 17 | #define IRQ_TYPE_LEVEL_HIGH 4 18 | #define IRQ_TYPE_LEVEL_LOW 8 19 | 20 | #endif 21 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/irqc-rzg2l.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 | /* 3 | * This header provides constants for Renesas RZ/G2L family IRQC bindings. 4 | * 5 | * Copyright (C) 2022 Renesas Electronics Corp. 6 | * 7 | */ 8 | 9 | #ifndef __DT_BINDINGS_IRQC_RZG2L_H 10 | #define __DT_BINDINGS_IRQC_RZG2L_H 11 | 12 | /* NMI maps to SPI0 */ 13 | #define RZG2L_NMI 0 14 | 15 | /* IRQ0-7 map to SPI1-8 */ 16 | #define RZG2L_IRQ0 1 17 | #define RZG2L_IRQ1 2 18 | #define RZG2L_IRQ2 3 19 | #define RZG2L_IRQ3 4 20 | #define RZG2L_IRQ4 5 21 | #define RZG2L_IRQ5 6 22 | #define RZG2L_IRQ6 7 23 | #define RZG2L_IRQ7 8 24 | 25 | #endif /* __DT_BINDINGS_IRQC_RZG2L_H */ 26 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/mips-gic.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H 3 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H 4 | 5 | #include 6 | 7 | #define GIC_SHARED 0 8 | #define GIC_LOCAL 1 9 | 10 | #endif 11 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/interrupt-controller/mvebu-icu.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for the MVEBU ICU driver. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H 7 | #define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H 8 | 9 | /* interrupt specifier cell 0 */ 10 | 11 | #define ICU_GRP_NSR 0x0 12 | #define ICU_GRP_SR 0x1 13 | #define ICU_GRP_SEI 0x4 14 | #define ICU_GRP_REI 0x5 15 | 16 | #endif 17 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/am33xx.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants specific to AM33XX pinctrl bindings. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_PINCTRL_AM33XX_H 7 | #define _DT_BINDINGS_PINCTRL_AM33XX_H 8 | 9 | #include 10 | 11 | /* am33xx specific mux bit defines */ 12 | #undef PULL_ENA 13 | #undef INPUT_EN 14 | 15 | #define PULL_DISABLE (1 << 3) 16 | #define INPUT_EN (1 << 5) 17 | #define SLEWCTRL_SLOW (1 << 6) 18 | #define SLEWCTRL_FAST 0 19 | 20 | /* update macro depending on INPUT_EN and PULL_ENA */ 21 | #undef PIN_OUTPUT 22 | #undef PIN_OUTPUT_PULLUP 23 | #undef PIN_OUTPUT_PULLDOWN 24 | #undef PIN_INPUT 25 | #undef PIN_INPUT_PULLUP 26 | #undef PIN_INPUT_PULLDOWN 27 | 28 | #define PIN_OUTPUT (PULL_DISABLE) 29 | #define PIN_OUTPUT_PULLUP (PULL_UP) 30 | #define PIN_OUTPUT_PULLDOWN 0 31 | #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 32 | #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 33 | #define PIN_INPUT_PULLDOWN (INPUT_EN) 34 | 35 | /* undef non-existing modes */ 36 | #undef PIN_OFF_NONE 37 | #undef PIN_OFF_OUTPUT_HIGH 38 | #undef PIN_OFF_OUTPUT_LOW 39 | #undef PIN_OFF_INPUT_PULLUP 40 | #undef PIN_OFF_INPUT_PULLDOWN 41 | #undef PIN_OFF_WAKEUPENABLE 42 | 43 | #define AM335X_PIN_OFFSET_MIN 0x0800U 44 | 45 | #define AM335X_PIN_GPMC_AD0 0x800 46 | #define AM335X_PIN_GPMC_AD1 0x804 47 | #define AM335X_PIN_GPMC_AD2 0x808 48 | #define AM335X_PIN_GPMC_AD3 0x80c 49 | #define AM335X_PIN_GPMC_AD4 0x810 50 | #define AM335X_PIN_GPMC_AD5 0x814 51 | #define AM335X_PIN_GPMC_AD6 0x818 52 | #define AM335X_PIN_GPMC_AD7 0x81c 53 | #define AM335X_PIN_GPMC_AD8 0x820 54 | #define AM335X_PIN_GPMC_AD9 0x824 55 | #define AM335X_PIN_GPMC_AD10 0x828 56 | #define AM335X_PIN_GPMC_AD11 0x82c 57 | #define AM335X_PIN_GPMC_AD12 0x830 58 | #define AM335X_PIN_GPMC_AD13 0x834 59 | #define AM335X_PIN_GPMC_AD14 0x838 60 | #define AM335X_PIN_GPMC_AD15 0x83c 61 | #define AM335X_PIN_GPMC_A0 0x840 62 | #define AM335X_PIN_GPMC_A1 0x844 63 | #define AM335X_PIN_GPMC_A2 0x848 64 | #define AM335X_PIN_GPMC_A3 0x84c 65 | #define AM335X_PIN_GPMC_A4 0x850 66 | #define AM335X_PIN_GPMC_A5 0x854 67 | #define AM335X_PIN_GPMC_A6 0x858 68 | #define AM335X_PIN_GPMC_A7 0x85c 69 | #define AM335X_PIN_GPMC_A8 0x860 70 | #define AM335X_PIN_GPMC_A9 0x864 71 | #define AM335X_PIN_GPMC_A10 0x868 72 | #define AM335X_PIN_GPMC_A11 0x86c 73 | #define AM335X_PIN_GPMC_WAIT0 0x870 74 | #define AM335X_PIN_GPMC_WPN 0x874 75 | #define AM335X_PIN_GPMC_BEN1 0x878 76 | #define AM335X_PIN_GPMC_CSN0 0x87c 77 | #define AM335X_PIN_GPMC_CSN1 0x880 78 | #define AM335X_PIN_GPMC_CSN2 0x884 79 | #define AM335X_PIN_GPMC_CSN3 0x888 80 | #define AM335X_PIN_GPMC_CLK 0x88c 81 | #define AM335X_PIN_GPMC_ADVN_ALE 0x890 82 | #define AM335X_PIN_GPMC_OEN_REN 0x894 83 | #define AM335X_PIN_GPMC_WEN 0x898 84 | #define AM335X_PIN_GPMC_BEN0_CLE 0x89c 85 | #define AM335X_PIN_LCD_DATA0 0x8a0 86 | #define AM335X_PIN_LCD_DATA1 0x8a4 87 | #define AM335X_PIN_LCD_DATA2 0x8a8 88 | #define AM335X_PIN_LCD_DATA3 0x8ac 89 | #define AM335X_PIN_LCD_DATA4 0x8b0 90 | #define AM335X_PIN_LCD_DATA5 0x8b4 91 | #define AM335X_PIN_LCD_DATA6 0x8b8 92 | #define AM335X_PIN_LCD_DATA7 0x8bc 93 | #define AM335X_PIN_LCD_DATA8 0x8c0 94 | #define AM335X_PIN_LCD_DATA9 0x8c4 95 | #define AM335X_PIN_LCD_DATA10 0x8c8 96 | #define AM335X_PIN_LCD_DATA11 0x8cc 97 | #define AM335X_PIN_LCD_DATA12 0x8d0 98 | #define AM335X_PIN_LCD_DATA13 0x8d4 99 | #define AM335X_PIN_LCD_DATA14 0x8d8 100 | #define AM335X_PIN_LCD_DATA15 0x8dc 101 | #define AM335X_PIN_LCD_VSYNC 0x8e0 102 | #define AM335X_PIN_LCD_HSYNC 0x8e4 103 | #define AM335X_PIN_LCD_PCLK 0x8e8 104 | #define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec 105 | #define AM335X_PIN_MMC0_DAT3 0x8f0 106 | #define AM335X_PIN_MMC0_DAT2 0x8f4 107 | #define AM335X_PIN_MMC0_DAT1 0x8f8 108 | #define AM335X_PIN_MMC0_DAT0 0x8fc 109 | #define AM335X_PIN_MMC0_CLK 0x900 110 | #define AM335X_PIN_MMC0_CMD 0x904 111 | #define AM335X_PIN_MII1_COL 0x908 112 | #define AM335X_PIN_MII1_CRS 0x90c 113 | #define AM335X_PIN_MII1_RX_ER 0x910 114 | #define AM335X_PIN_MII1_TX_EN 0x914 115 | #define AM335X_PIN_MII1_RX_DV 0x918 116 | #define AM335X_PIN_MII1_TXD3 0x91c 117 | #define AM335X_PIN_MII1_TXD2 0x920 118 | #define AM335X_PIN_MII1_TXD1 0x924 119 | #define AM335X_PIN_MII1_TXD0 0x928 120 | #define AM335X_PIN_MII1_TX_CLK 0x92c 121 | #define AM335X_PIN_MII1_RX_CLK 0x930 122 | #define AM335X_PIN_MII1_RXD3 0x934 123 | #define AM335X_PIN_MII1_RXD2 0x938 124 | #define AM335X_PIN_MII1_RXD1 0x93c 125 | #define AM335X_PIN_MII1_RXD0 0x940 126 | #define AM335X_PIN_RMII1_REF_CLK 0x944 127 | #define AM335X_PIN_MDIO 0x948 128 | #define AM335X_PIN_MDC 0x94c 129 | #define AM335X_PIN_SPI0_SCLK 0x950 130 | #define AM335X_PIN_SPI0_D0 0x954 131 | #define AM335X_PIN_SPI0_D1 0x958 132 | #define AM335X_PIN_SPI0_CS0 0x95c 133 | #define AM335X_PIN_SPI0_CS1 0x960 134 | #define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 135 | #define AM335X_PIN_UART0_CTSN 0x968 136 | #define AM335X_PIN_UART0_RTSN 0x96c 137 | #define AM335X_PIN_UART0_RXD 0x970 138 | #define AM335X_PIN_UART0_TXD 0x974 139 | #define AM335X_PIN_UART1_CTSN 0x978 140 | #define AM335X_PIN_UART1_RTSN 0x97c 141 | #define AM335X_PIN_UART1_RXD 0x980 142 | #define AM335X_PIN_UART1_TXD 0x984 143 | #define AM335X_PIN_I2C0_SDA 0x988 144 | #define AM335X_PIN_I2C0_SCL 0x98c 145 | #define AM335X_PIN_MCASP0_ACLKX 0x990 146 | #define AM335X_PIN_MCASP0_FSX 0x994 147 | #define AM335X_PIN_MCASP0_AXR0 0x998 148 | #define AM335X_PIN_MCASP0_AHCLKR 0x99c 149 | #define AM335X_PIN_MCASP0_ACLKR 0x9a0 150 | #define AM335X_PIN_MCASP0_FSR 0x9a4 151 | #define AM335X_PIN_MCASP0_AXR1 0x9a8 152 | #define AM335X_PIN_MCASP0_AHCLKX 0x9ac 153 | #define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 154 | #define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 155 | #define AM335X_PIN_WARMRSTN 0x9b8 156 | #define AM335X_PIN_NNMI 0x9c0 157 | #define AM335X_PIN_TMS 0x9d0 158 | #define AM335X_PIN_TDI 0x9d4 159 | #define AM335X_PIN_TDO 0x9d8 160 | #define AM335X_PIN_TCK 0x9dc 161 | #define AM335X_PIN_TRSTN 0x9e0 162 | #define AM335X_PIN_EMU0 0x9e4 163 | #define AM335X_PIN_EMU1 0x9e8 164 | #define AM335X_PIN_RTC_PWRONRSTN 0x9f8 165 | #define AM335X_PIN_PMIC_POWER_EN 0x9fc 166 | #define AM335X_PIN_EXT_WAKEUP 0xa00 167 | #define AM335X_PIN_USB0_DRVVBUS 0xa1c 168 | #define AM335X_PIN_USB1_DRVVBUS 0xa34 169 | 170 | #define AM335X_PIN_OFFSET_MAX 0x0a34U 171 | 172 | #endif 173 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/am43xx.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants specific to AM43XX pinctrl bindings. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_PINCTRL_AM43XX_H 7 | #define _DT_BINDINGS_PINCTRL_AM43XX_H 8 | 9 | #define MUX_MODE0 0 10 | #define MUX_MODE1 1 11 | #define MUX_MODE2 2 12 | #define MUX_MODE3 3 13 | #define MUX_MODE4 4 14 | #define MUX_MODE5 5 15 | #define MUX_MODE6 6 16 | #define MUX_MODE7 7 17 | #define MUX_MODE8 8 18 | #define MUX_MODE9 9 19 | 20 | #define PULL_DISABLE (1 << 16) 21 | #define PULL_UP (1 << 17) 22 | #define INPUT_EN (1 << 18) 23 | #define SLEWCTRL_SLOW (1 << 19) 24 | #define SLEWCTRL_FAST 0 25 | #define DS0_FORCE_OFF_MODE (1 << 24) 26 | #define DS0_INPUT (1 << 25) 27 | #define DS0_FORCE_OUT_HIGH (1 << 26) 28 | #define DS0_PULL_UP_DOWN_EN (0 << 27) 29 | #define DS0_PULL_UP_DOWN_DIS (1 << 27) 30 | #define DS0_PULL_UP_SEL (1 << 28) 31 | #define WAKEUP_ENABLE (1 << 29) 32 | 33 | #define DS0_PIN_OUTPUT (DS0_FORCE_OFF_MODE) 34 | #define DS0_PIN_OUTPUT_HIGH (DS0_FORCE_OFF_MODE | DS0_FORCE_OUT_HIGH) 35 | #define DS0_PIN_OUTPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) 36 | #define DS0_PIN_OUTPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_PULL_UP_DOWN_EN) 37 | #define DS0_PIN_INPUT (DS0_FORCE_OFF_MODE | DS0_INPUT) 38 | #define DS0_PIN_INPUT_PULLUP (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN | DS0_PULL_UP_SEL) 39 | #define DS0_PIN_INPUT_PULLDOWN (DS0_FORCE_OFF_MODE | DS0_INPUT | DS0_PULL_UP_DOWN_EN) 40 | 41 | #define PIN_OUTPUT (PULL_DISABLE) 42 | #define PIN_OUTPUT_PULLUP (PULL_UP) 43 | #define PIN_OUTPUT_PULLDOWN 0 44 | #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 45 | #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 46 | #define PIN_INPUT_PULLDOWN (INPUT_EN) 47 | 48 | /* 49 | * Macro to allow using the absolute physical address instead of the 50 | * padconf registers instead of the offset from padconf base. 51 | */ 52 | #define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) 53 | 54 | #endif 55 | 56 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/apple.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ 2 | /* 3 | * This header provides constants for Apple pinctrl bindings. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_PINCTRL_APPLE_H 7 | #define _DT_BINDINGS_PINCTRL_APPLE_H 8 | 9 | #define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16)) 10 | #define APPLE_PIN(pinmux) ((pinmux) & 0xffff) 11 | #define APPLE_FUNC(pinmux) ((pinmux) >> 16) 12 | 13 | #endif /* _DT_BINDINGS_PINCTRL_APPLE_H */ 14 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/at91.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for most at91 pinctrl bindings. 4 | * 5 | * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD 6 | */ 7 | 8 | #ifndef __DT_BINDINGS_AT91_PINCTRL_H__ 9 | #define __DT_BINDINGS_AT91_PINCTRL_H__ 10 | 11 | #define AT91_PINCTRL_NONE (0 << 0) 12 | #define AT91_PINCTRL_PULL_UP (1 << 0) 13 | #define AT91_PINCTRL_MULTI_DRIVE (1 << 1) 14 | #define AT91_PINCTRL_DEGLITCH (1 << 2) 15 | #define AT91_PINCTRL_PULL_DOWN (1 << 3) 16 | #define AT91_PINCTRL_DIS_SCHMIT (1 << 4) 17 | #define AT91_PINCTRL_OUTPUT (1 << 7) 18 | #define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) 19 | #define AT91_PINCTRL_SLEWRATE (1 << 9) 20 | #define AT91_PINCTRL_DEBOUNCE (1 << 16) 21 | #define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) 22 | 23 | #define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) 24 | 25 | #define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) 26 | #define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) 27 | #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) 28 | #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) 29 | 30 | #define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) 31 | #define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) 32 | 33 | #define AT91_PIOA 0 34 | #define AT91_PIOB 1 35 | #define AT91_PIOC 2 36 | #define AT91_PIOD 3 37 | #define AT91_PIOE 4 38 | 39 | #define AT91_PERIPH_GPIO 0 40 | #define AT91_PERIPH_A 1 41 | #define AT91_PERIPH_B 2 42 | #define AT91_PERIPH_C 3 43 | #define AT91_PERIPH_D 4 44 | 45 | #define ATMEL_PIO_DRVSTR_LO 1 46 | #define ATMEL_PIO_DRVSTR_ME 2 47 | #define ATMEL_PIO_DRVSTR_HI 3 48 | 49 | #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ 50 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/bcm2835.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Header providing constants for bcm2835 pinctrl bindings. 4 | * 5 | * Copyright (C) 2015 Stefan Wahren 6 | */ 7 | 8 | #ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ 9 | #define __DT_BINDINGS_PINCTRL_BCM2835_H__ 10 | 11 | /* brcm,function property */ 12 | #define BCM2835_FSEL_GPIO_IN 0 13 | #define BCM2835_FSEL_GPIO_OUT 1 14 | #define BCM2835_FSEL_ALT5 2 15 | #define BCM2835_FSEL_ALT4 3 16 | #define BCM2835_FSEL_ALT0 4 17 | #define BCM2835_FSEL_ALT1 5 18 | #define BCM2835_FSEL_ALT2 6 19 | #define BCM2835_FSEL_ALT3 7 20 | 21 | /* brcm,pull property */ 22 | #define BCM2835_PUD_OFF 0 23 | #define BCM2835_PUD_DOWN 1 24 | #define BCM2835_PUD_UP 2 25 | 26 | #endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ 27 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/brcm,pinctrl-stingray.h: -------------------------------------------------------------------------------- 1 | /* 2 | * BSD LICENSE 3 | * 4 | * Copyright(c) 2017 Broadcom Corporation. All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without 7 | * modification, are permitted provided that the following conditions 8 | * are met: 9 | * 10 | * * Redistributions of source code must retain the above copyright 11 | * notice, this list of conditions and the following disclaimer. 12 | * * Redistributions in binary form must reproduce the above copyright 13 | * notice, this list of conditions and the following disclaimer in 14 | * the documentation and/or other materials provided with the 15 | * distribution. 16 | * * Neither the name of Broadcom Corporation nor the names of its 17 | * contributors may be used to endorse or promote products derived 18 | * from this software without specific prior written permission. 19 | * 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 | */ 32 | 33 | #ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ 34 | #define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ 35 | 36 | /* Alternate functions available in MUX controller */ 37 | #define MODE_NITRO 0 38 | #define MODE_NAND 1 39 | #define MODE_PNOR 2 40 | #define MODE_GPIO 3 41 | 42 | /* Pad configuration attribute */ 43 | #define PAD_SLEW_RATE_ENA (1 << 0) 44 | #define PAD_SLEW_RATE_ENA_MASK (1 << 0) 45 | 46 | #define PAD_DRIVE_STRENGTH_2_MA (0 << 1) 47 | #define PAD_DRIVE_STRENGTH_4_MA (1 << 1) 48 | #define PAD_DRIVE_STRENGTH_6_MA (2 << 1) 49 | #define PAD_DRIVE_STRENGTH_8_MA (3 << 1) 50 | #define PAD_DRIVE_STRENGTH_10_MA (4 << 1) 51 | #define PAD_DRIVE_STRENGTH_12_MA (5 << 1) 52 | #define PAD_DRIVE_STRENGTH_14_MA (6 << 1) 53 | #define PAD_DRIVE_STRENGTH_16_MA (7 << 1) 54 | #define PAD_DRIVE_STRENGTH_MASK (7 << 1) 55 | 56 | #define PAD_PULL_UP_ENA (1 << 4) 57 | #define PAD_PULL_UP_ENA_MASK (1 << 4) 58 | 59 | #define PAD_PULL_DOWN_ENA (1 << 5) 60 | #define PAD_PULL_DOWN_ENA_MASK (1 << 5) 61 | 62 | #define PAD_INPUT_PATH_DIS (1 << 6) 63 | #define PAD_INPUT_PATH_DIS_MASK (1 << 6) 64 | 65 | #define PAD_HYSTERESIS_ENA (1 << 7) 66 | #define PAD_HYSTERESIS_ENA_MASK (1 << 7) 67 | 68 | #endif 69 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/dm814x.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants specific to DM814X pinctrl bindings. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_PINCTRL_DM814X_H 7 | #define _DT_BINDINGS_PINCTRL_DM814X_H 8 | 9 | #include 10 | 11 | #undef INPUT_EN 12 | #undef PULL_UP 13 | #undef PULL_ENA 14 | 15 | /* 16 | * Note that dm814x silicon revision 2.1 and older require input enabled 17 | * (bit 18 set) for all 3.3V I/Os to avoid cumulative hardware damage. For 18 | * more info, see errata advisory 2.1.87. We leave bit 18 out of 19 | * function-mask in dm814x.h and rely on the bootloader for it. 20 | */ 21 | #define INPUT_EN (1 << 18) 22 | #define PULL_UP (1 << 17) 23 | #define PULL_DISABLE (1 << 16) 24 | 25 | /* update macro depending on INPUT_EN and PULL_ENA */ 26 | #undef PIN_OUTPUT 27 | #undef PIN_OUTPUT_PULLUP 28 | #undef PIN_OUTPUT_PULLDOWN 29 | #undef PIN_INPUT 30 | #undef PIN_INPUT_PULLUP 31 | #undef PIN_INPUT_PULLDOWN 32 | 33 | #define PIN_OUTPUT (PULL_DISABLE) 34 | #define PIN_OUTPUT_PULLUP (PULL_UP) 35 | #define PIN_OUTPUT_PULLDOWN 0 36 | #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 37 | #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 38 | #define PIN_INPUT_PULLDOWN (INPUT_EN) 39 | 40 | /* undef non-existing modes */ 41 | #undef PIN_OFF_NONE 42 | #undef PIN_OFF_OUTPUT_HIGH 43 | #undef PIN_OFF_OUTPUT_LOW 44 | #undef PIN_OFF_INPUT_PULLUP 45 | #undef PIN_OFF_INPUT_PULLDOWN 46 | #undef PIN_OFF_WAKEUPENABLE 47 | 48 | #endif 49 | 50 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/dra.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for DRA pinctrl bindings. 4 | * 5 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 6 | * Author: Rajendra Nayak 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_DRA_H 10 | #define _DT_BINDINGS_PINCTRL_DRA_H 11 | 12 | /* DRA7 mux mode options for each pin. See TRM for options */ 13 | #define MUX_MODE0 0x0 14 | #define MUX_MODE1 0x1 15 | #define MUX_MODE2 0x2 16 | #define MUX_MODE3 0x3 17 | #define MUX_MODE4 0x4 18 | #define MUX_MODE5 0x5 19 | #define MUX_MODE6 0x6 20 | #define MUX_MODE7 0x7 21 | #define MUX_MODE8 0x8 22 | #define MUX_MODE9 0x9 23 | #define MUX_MODE10 0xa 24 | #define MUX_MODE11 0xb 25 | #define MUX_MODE12 0xc 26 | #define MUX_MODE13 0xd 27 | #define MUX_MODE14 0xe 28 | #define MUX_MODE15 0xf 29 | 30 | /* Certain pins need virtual mode, but note: they may glitch */ 31 | #define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) 32 | #define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) 33 | #define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) 34 | #define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) 35 | #define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) 36 | #define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) 37 | #define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) 38 | #define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) 39 | #define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) 40 | #define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) 41 | #define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) 42 | #define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) 43 | #define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) 44 | #define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) 45 | #define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) 46 | #define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) 47 | 48 | #define MODE_SELECT (1 << 8) 49 | 50 | #define PULL_ENA (0 << 16) 51 | #define PULL_DIS (1 << 16) 52 | #define PULL_UP (1 << 17) 53 | #define INPUT_EN (1 << 18) 54 | #define SLEWCONTROL (1 << 19) 55 | #define WAKEUP_EN (1 << 24) 56 | #define WAKEUP_EVENT (1 << 25) 57 | 58 | /* Active pin states */ 59 | #define PIN_OUTPUT (0 | PULL_DIS) 60 | #define PIN_OUTPUT_PULLUP (PULL_UP) 61 | #define PIN_OUTPUT_PULLDOWN (0) 62 | #define PIN_INPUT (INPUT_EN | PULL_DIS) 63 | #define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) 64 | #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) 65 | #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) 66 | 67 | /* 68 | * Macro to allow using the absolute physical address instead of the 69 | * padconf registers instead of the offset from padconf base. 70 | */ 71 | #define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) 72 | 73 | /* DRA7 IODELAY configuration parameters */ 74 | #define A_DELAY_PS(val) ((val) & 0xffff) 75 | #define G_DELAY_PS(val) ((val) & 0xffff) 76 | #endif 77 | 78 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/hisi.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for hisilicon pinctrl bindings. 4 | * 5 | * Copyright (c) 2015 HiSilicon Limited. 6 | * Copyright (c) 2015 Linaro Limited. 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_HISI_H 10 | #define _DT_BINDINGS_PINCTRL_HISI_H 11 | 12 | /* iomg bit definition */ 13 | #define MUX_M0 0 14 | #define MUX_M1 1 15 | #define MUX_M2 2 16 | #define MUX_M3 3 17 | #define MUX_M4 4 18 | #define MUX_M5 5 19 | #define MUX_M6 6 20 | #define MUX_M7 7 21 | 22 | /* iocg bit definition */ 23 | #define PULL_MASK (3) 24 | #define PULL_DIS (0) 25 | #define PULL_UP (1 << 0) 26 | #define PULL_DOWN (1 << 1) 27 | 28 | /* drive strength definition */ 29 | #define DRIVE_MASK (7 << 4) 30 | #define DRIVE1_02MA (0 << 4) 31 | #define DRIVE1_04MA (1 << 4) 32 | #define DRIVE1_08MA (2 << 4) 33 | #define DRIVE1_10MA (3 << 4) 34 | #define DRIVE2_02MA (0 << 4) 35 | #define DRIVE2_04MA (1 << 4) 36 | #define DRIVE2_08MA (2 << 4) 37 | #define DRIVE2_10MA (3 << 4) 38 | #define DRIVE3_04MA (0 << 4) 39 | #define DRIVE3_08MA (1 << 4) 40 | #define DRIVE3_12MA (2 << 4) 41 | #define DRIVE3_16MA (3 << 4) 42 | #define DRIVE3_20MA (4 << 4) 43 | #define DRIVE3_24MA (5 << 4) 44 | #define DRIVE3_32MA (6 << 4) 45 | #define DRIVE3_40MA (7 << 4) 46 | #define DRIVE4_02MA (0 << 4) 47 | #define DRIVE4_04MA (2 << 4) 48 | #define DRIVE4_08MA (4 << 4) 49 | #define DRIVE4_10MA (6 << 4) 50 | 51 | /* drive strength definition for hi3660 */ 52 | #define DRIVE6_MASK (15 << 4) 53 | #define DRIVE6_04MA (0 << 4) 54 | #define DRIVE6_12MA (4 << 4) 55 | #define DRIVE6_19MA (8 << 4) 56 | #define DRIVE6_27MA (10 << 4) 57 | #define DRIVE6_32MA (15 << 4) 58 | #define DRIVE7_02MA (0 << 4) 59 | #define DRIVE7_04MA (1 << 4) 60 | #define DRIVE7_06MA (2 << 4) 61 | #define DRIVE7_08MA (3 << 4) 62 | #define DRIVE7_10MA (4 << 4) 63 | #define DRIVE7_12MA (5 << 4) 64 | #define DRIVE7_14MA (6 << 4) 65 | #define DRIVE7_16MA (7 << 4) 66 | #endif 67 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/k210-fpioa.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0+ */ 2 | /* 3 | * Copyright (C) 2020 Sean Anderson 4 | * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5 | */ 6 | #ifndef PINCTRL_K210_FPIOA_H 7 | #define PINCTRL_K210_FPIOA_H 8 | 9 | /* 10 | * Full list of FPIOA functions from 11 | * kendryte-standalone-sdk/lib/drivers/include/fpioa.h 12 | */ 13 | #define K210_PCF_MASK GENMASK(7, 0) 14 | #define K210_PCF_JTAG_TCLK 0 /* JTAG Test Clock */ 15 | #define K210_PCF_JTAG_TDI 1 /* JTAG Test Data In */ 16 | #define K210_PCF_JTAG_TMS 2 /* JTAG Test Mode Select */ 17 | #define K210_PCF_JTAG_TDO 3 /* JTAG Test Data Out */ 18 | #define K210_PCF_SPI0_D0 4 /* SPI0 Data 0 */ 19 | #define K210_PCF_SPI0_D1 5 /* SPI0 Data 1 */ 20 | #define K210_PCF_SPI0_D2 6 /* SPI0 Data 2 */ 21 | #define K210_PCF_SPI0_D3 7 /* SPI0 Data 3 */ 22 | #define K210_PCF_SPI0_D4 8 /* SPI0 Data 4 */ 23 | #define K210_PCF_SPI0_D5 9 /* SPI0 Data 5 */ 24 | #define K210_PCF_SPI0_D6 10 /* SPI0 Data 6 */ 25 | #define K210_PCF_SPI0_D7 11 /* SPI0 Data 7 */ 26 | #define K210_PCF_SPI0_SS0 12 /* SPI0 Chip Select 0 */ 27 | #define K210_PCF_SPI0_SS1 13 /* SPI0 Chip Select 1 */ 28 | #define K210_PCF_SPI0_SS2 14 /* SPI0 Chip Select 2 */ 29 | #define K210_PCF_SPI0_SS3 15 /* SPI0 Chip Select 3 */ 30 | #define K210_PCF_SPI0_ARB 16 /* SPI0 Arbitration */ 31 | #define K210_PCF_SPI0_SCLK 17 /* SPI0 Serial Clock */ 32 | #define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */ 33 | #define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */ 34 | #define K210_PCF_RESV6 20 /* Reserved function */ 35 | #define K210_PCF_RESV7 21 /* Reserved function */ 36 | #define K210_PCF_CLK_SPI1 22 /* Clock SPI1 */ 37 | #define K210_PCF_CLK_I2C1 23 /* Clock I2C1 */ 38 | #define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */ 39 | #define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */ 40 | #define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */ 41 | #define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */ 42 | #define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */ 43 | #define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */ 44 | #define K210_PCF_GPIOHS6 30 /* GPIO High speed 6 */ 45 | #define K210_PCF_GPIOHS7 31 /* GPIO High speed 7 */ 46 | #define K210_PCF_GPIOHS8 32 /* GPIO High speed 8 */ 47 | #define K210_PCF_GPIOHS9 33 /* GPIO High speed 9 */ 48 | #define K210_PCF_GPIOHS10 34 /* GPIO High speed 10 */ 49 | #define K210_PCF_GPIOHS11 35 /* GPIO High speed 11 */ 50 | #define K210_PCF_GPIOHS12 36 /* GPIO High speed 12 */ 51 | #define K210_PCF_GPIOHS13 37 /* GPIO High speed 13 */ 52 | #define K210_PCF_GPIOHS14 38 /* GPIO High speed 14 */ 53 | #define K210_PCF_GPIOHS15 39 /* GPIO High speed 15 */ 54 | #define K210_PCF_GPIOHS16 40 /* GPIO High speed 16 */ 55 | #define K210_PCF_GPIOHS17 41 /* GPIO High speed 17 */ 56 | #define K210_PCF_GPIOHS18 42 /* GPIO High speed 18 */ 57 | #define K210_PCF_GPIOHS19 43 /* GPIO High speed 19 */ 58 | #define K210_PCF_GPIOHS20 44 /* GPIO High speed 20 */ 59 | #define K210_PCF_GPIOHS21 45 /* GPIO High speed 21 */ 60 | #define K210_PCF_GPIOHS22 46 /* GPIO High speed 22 */ 61 | #define K210_PCF_GPIOHS23 47 /* GPIO High speed 23 */ 62 | #define K210_PCF_GPIOHS24 48 /* GPIO High speed 24 */ 63 | #define K210_PCF_GPIOHS25 49 /* GPIO High speed 25 */ 64 | #define K210_PCF_GPIOHS26 50 /* GPIO High speed 26 */ 65 | #define K210_PCF_GPIOHS27 51 /* GPIO High speed 27 */ 66 | #define K210_PCF_GPIOHS28 52 /* GPIO High speed 28 */ 67 | #define K210_PCF_GPIOHS29 53 /* GPIO High speed 29 */ 68 | #define K210_PCF_GPIOHS30 54 /* GPIO High speed 30 */ 69 | #define K210_PCF_GPIOHS31 55 /* GPIO High speed 31 */ 70 | #define K210_PCF_GPIO0 56 /* GPIO pin 0 */ 71 | #define K210_PCF_GPIO1 57 /* GPIO pin 1 */ 72 | #define K210_PCF_GPIO2 58 /* GPIO pin 2 */ 73 | #define K210_PCF_GPIO3 59 /* GPIO pin 3 */ 74 | #define K210_PCF_GPIO4 60 /* GPIO pin 4 */ 75 | #define K210_PCF_GPIO5 61 /* GPIO pin 5 */ 76 | #define K210_PCF_GPIO6 62 /* GPIO pin 6 */ 77 | #define K210_PCF_GPIO7 63 /* GPIO pin 7 */ 78 | #define K210_PCF_UART1_RX 64 /* UART1 Receiver */ 79 | #define K210_PCF_UART1_TX 65 /* UART1 Transmitter */ 80 | #define K210_PCF_UART2_RX 66 /* UART2 Receiver */ 81 | #define K210_PCF_UART2_TX 67 /* UART2 Transmitter */ 82 | #define K210_PCF_UART3_RX 68 /* UART3 Receiver */ 83 | #define K210_PCF_UART3_TX 69 /* UART3 Transmitter */ 84 | #define K210_PCF_SPI1_D0 70 /* SPI1 Data 0 */ 85 | #define K210_PCF_SPI1_D1 71 /* SPI1 Data 1 */ 86 | #define K210_PCF_SPI1_D2 72 /* SPI1 Data 2 */ 87 | #define K210_PCF_SPI1_D3 73 /* SPI1 Data 3 */ 88 | #define K210_PCF_SPI1_D4 74 /* SPI1 Data 4 */ 89 | #define K210_PCF_SPI1_D5 75 /* SPI1 Data 5 */ 90 | #define K210_PCF_SPI1_D6 76 /* SPI1 Data 6 */ 91 | #define K210_PCF_SPI1_D7 77 /* SPI1 Data 7 */ 92 | #define K210_PCF_SPI1_SS0 78 /* SPI1 Chip Select 0 */ 93 | #define K210_PCF_SPI1_SS1 79 /* SPI1 Chip Select 1 */ 94 | #define K210_PCF_SPI1_SS2 80 /* SPI1 Chip Select 2 */ 95 | #define K210_PCF_SPI1_SS3 81 /* SPI1 Chip Select 3 */ 96 | #define K210_PCF_SPI1_ARB 82 /* SPI1 Arbitration */ 97 | #define K210_PCF_SPI1_SCLK 83 /* SPI1 Serial Clock */ 98 | #define K210_PCF_SPI2_D0 84 /* SPI2 Data 0 */ 99 | #define K210_PCF_SPI2_SS 85 /* SPI2 Select */ 100 | #define K210_PCF_SPI2_SCLK 86 /* SPI2 Serial Clock */ 101 | #define K210_PCF_I2S0_MCLK 87 /* I2S0 Master Clock */ 102 | #define K210_PCF_I2S0_SCLK 88 /* I2S0 Serial Clock(BCLK) */ 103 | #define K210_PCF_I2S0_WS 89 /* I2S0 Word Select(LRCLK) */ 104 | #define K210_PCF_I2S0_IN_D0 90 /* I2S0 Serial Data Input 0 */ 105 | #define K210_PCF_I2S0_IN_D1 91 /* I2S0 Serial Data Input 1 */ 106 | #define K210_PCF_I2S0_IN_D2 92 /* I2S0 Serial Data Input 2 */ 107 | #define K210_PCF_I2S0_IN_D3 93 /* I2S0 Serial Data Input 3 */ 108 | #define K210_PCF_I2S0_OUT_D0 94 /* I2S0 Serial Data Output 0 */ 109 | #define K210_PCF_I2S0_OUT_D1 95 /* I2S0 Serial Data Output 1 */ 110 | #define K210_PCF_I2S0_OUT_D2 96 /* I2S0 Serial Data Output 2 */ 111 | #define K210_PCF_I2S0_OUT_D3 97 /* I2S0 Serial Data Output 3 */ 112 | #define K210_PCF_I2S1_MCLK 98 /* I2S1 Master Clock */ 113 | #define K210_PCF_I2S1_SCLK 99 /* I2S1 Serial Clock(BCLK) */ 114 | #define K210_PCF_I2S1_WS 100 /* I2S1 Word Select(LRCLK) */ 115 | #define K210_PCF_I2S1_IN_D0 101 /* I2S1 Serial Data Input 0 */ 116 | #define K210_PCF_I2S1_IN_D1 102 /* I2S1 Serial Data Input 1 */ 117 | #define K210_PCF_I2S1_IN_D2 103 /* I2S1 Serial Data Input 2 */ 118 | #define K210_PCF_I2S1_IN_D3 104 /* I2S1 Serial Data Input 3 */ 119 | #define K210_PCF_I2S1_OUT_D0 105 /* I2S1 Serial Data Output 0 */ 120 | #define K210_PCF_I2S1_OUT_D1 106 /* I2S1 Serial Data Output 1 */ 121 | #define K210_PCF_I2S1_OUT_D2 107 /* I2S1 Serial Data Output 2 */ 122 | #define K210_PCF_I2S1_OUT_D3 108 /* I2S1 Serial Data Output 3 */ 123 | #define K210_PCF_I2S2_MCLK 109 /* I2S2 Master Clock */ 124 | #define K210_PCF_I2S2_SCLK 110 /* I2S2 Serial Clock(BCLK) */ 125 | #define K210_PCF_I2S2_WS 111 /* I2S2 Word Select(LRCLK) */ 126 | #define K210_PCF_I2S2_IN_D0 112 /* I2S2 Serial Data Input 0 */ 127 | #define K210_PCF_I2S2_IN_D1 113 /* I2S2 Serial Data Input 1 */ 128 | #define K210_PCF_I2S2_IN_D2 114 /* I2S2 Serial Data Input 2 */ 129 | #define K210_PCF_I2S2_IN_D3 115 /* I2S2 Serial Data Input 3 */ 130 | #define K210_PCF_I2S2_OUT_D0 116 /* I2S2 Serial Data Output 0 */ 131 | #define K210_PCF_I2S2_OUT_D1 117 /* I2S2 Serial Data Output 1 */ 132 | #define K210_PCF_I2S2_OUT_D2 118 /* I2S2 Serial Data Output 2 */ 133 | #define K210_PCF_I2S2_OUT_D3 119 /* I2S2 Serial Data Output 3 */ 134 | #define K210_PCF_RESV0 120 /* Reserved function */ 135 | #define K210_PCF_RESV1 121 /* Reserved function */ 136 | #define K210_PCF_RESV2 122 /* Reserved function */ 137 | #define K210_PCF_RESV3 123 /* Reserved function */ 138 | #define K210_PCF_RESV4 124 /* Reserved function */ 139 | #define K210_PCF_RESV5 125 /* Reserved function */ 140 | #define K210_PCF_I2C0_SCLK 126 /* I2C0 Serial Clock */ 141 | #define K210_PCF_I2C0_SDA 127 /* I2C0 Serial Data */ 142 | #define K210_PCF_I2C1_SCLK 128 /* I2C1 Serial Clock */ 143 | #define K210_PCF_I2C1_SDA 129 /* I2C1 Serial Data */ 144 | #define K210_PCF_I2C2_SCLK 130 /* I2C2 Serial Clock */ 145 | #define K210_PCF_I2C2_SDA 131 /* I2C2 Serial Data */ 146 | #define K210_PCF_DVP_XCLK 132 /* DVP System Clock */ 147 | #define K210_PCF_DVP_RST 133 /* DVP System Reset */ 148 | #define K210_PCF_DVP_PWDN 134 /* DVP Power Down Mode */ 149 | #define K210_PCF_DVP_VSYNC 135 /* DVP Vertical Sync */ 150 | #define K210_PCF_DVP_HSYNC 136 /* DVP Horizontal Sync */ 151 | #define K210_PCF_DVP_PCLK 137 /* Pixel Clock */ 152 | #define K210_PCF_DVP_D0 138 /* Data Bit 0 */ 153 | #define K210_PCF_DVP_D1 139 /* Data Bit 1 */ 154 | #define K210_PCF_DVP_D2 140 /* Data Bit 2 */ 155 | #define K210_PCF_DVP_D3 141 /* Data Bit 3 */ 156 | #define K210_PCF_DVP_D4 142 /* Data Bit 4 */ 157 | #define K210_PCF_DVP_D5 143 /* Data Bit 5 */ 158 | #define K210_PCF_DVP_D6 144 /* Data Bit 6 */ 159 | #define K210_PCF_DVP_D7 145 /* Data Bit 7 */ 160 | #define K210_PCF_SCCB_SCLK 146 /* Serial Camera Control Bus Clock */ 161 | #define K210_PCF_SCCB_SDA 147 /* Serial Camera Control Bus Data */ 162 | #define K210_PCF_UART1_CTS 148 /* UART1 Clear To Send */ 163 | #define K210_PCF_UART1_DSR 149 /* UART1 Data Set Ready */ 164 | #define K210_PCF_UART1_DCD 150 /* UART1 Data Carrier Detect */ 165 | #define K210_PCF_UART1_RI 151 /* UART1 Ring Indicator */ 166 | #define K210_PCF_UART1_SIR_IN 152 /* UART1 Serial Infrared Input */ 167 | #define K210_PCF_UART1_DTR 153 /* UART1 Data Terminal Ready */ 168 | #define K210_PCF_UART1_RTS 154 /* UART1 Request To Send */ 169 | #define K210_PCF_UART1_OUT2 155 /* UART1 User-designated Output 2 */ 170 | #define K210_PCF_UART1_OUT1 156 /* UART1 User-designated Output 1 */ 171 | #define K210_PCF_UART1_SIR_OUT 157 /* UART1 Serial Infrared Output */ 172 | #define K210_PCF_UART1_BAUD 158 /* UART1 Transmit Clock Output */ 173 | #define K210_PCF_UART1_RE 159 /* UART1 Receiver Output Enable */ 174 | #define K210_PCF_UART1_DE 160 /* UART1 Driver Output Enable */ 175 | #define K210_PCF_UART1_RS485_EN 161 /* UART1 RS485 Enable */ 176 | #define K210_PCF_UART2_CTS 162 /* UART2 Clear To Send */ 177 | #define K210_PCF_UART2_DSR 163 /* UART2 Data Set Ready */ 178 | #define K210_PCF_UART2_DCD 164 /* UART2 Data Carrier Detect */ 179 | #define K210_PCF_UART2_RI 165 /* UART2 Ring Indicator */ 180 | #define K210_PCF_UART2_SIR_IN 166 /* UART2 Serial Infrared Input */ 181 | #define K210_PCF_UART2_DTR 167 /* UART2 Data Terminal Ready */ 182 | #define K210_PCF_UART2_RTS 168 /* UART2 Request To Send */ 183 | #define K210_PCF_UART2_OUT2 169 /* UART2 User-designated Output 2 */ 184 | #define K210_PCF_UART2_OUT1 170 /* UART2 User-designated Output 1 */ 185 | #define K210_PCF_UART2_SIR_OUT 171 /* UART2 Serial Infrared Output */ 186 | #define K210_PCF_UART2_BAUD 172 /* UART2 Transmit Clock Output */ 187 | #define K210_PCF_UART2_RE 173 /* UART2 Receiver Output Enable */ 188 | #define K210_PCF_UART2_DE 174 /* UART2 Driver Output Enable */ 189 | #define K210_PCF_UART2_RS485_EN 175 /* UART2 RS485 Enable */ 190 | #define K210_PCF_UART3_CTS 176 /* UART3 Clear To Send */ 191 | #define K210_PCF_UART3_DSR 177 /* UART3 Data Set Ready */ 192 | #define K210_PCF_UART3_DCD 178 /* UART3 Data Carrier Detect */ 193 | #define K210_PCF_UART3_RI 179 /* UART3 Ring Indicator */ 194 | #define K210_PCF_UART3_SIR_IN 180 /* UART3 Serial Infrared Input */ 195 | #define K210_PCF_UART3_DTR 181 /* UART3 Data Terminal Ready */ 196 | #define K210_PCF_UART3_RTS 182 /* UART3 Request To Send */ 197 | #define K210_PCF_UART3_OUT2 183 /* UART3 User-designated Output 2 */ 198 | #define K210_PCF_UART3_OUT1 184 /* UART3 User-designated Output 1 */ 199 | #define K210_PCF_UART3_SIR_OUT 185 /* UART3 Serial Infrared Output */ 200 | #define K210_PCF_UART3_BAUD 186 /* UART3 Transmit Clock Output */ 201 | #define K210_PCF_UART3_RE 187 /* UART3 Receiver Output Enable */ 202 | #define K210_PCF_UART3_DE 188 /* UART3 Driver Output Enable */ 203 | #define K210_PCF_UART3_RS485_EN 189 /* UART3 RS485 Enable */ 204 | #define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */ 205 | #define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */ 206 | #define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */ 207 | #define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */ 208 | #define K210_PCF_TIMER1_TOGGLE1 194 /* TIMER1 Toggle Output 1 */ 209 | #define K210_PCF_TIMER1_TOGGLE2 195 /* TIMER1 Toggle Output 2 */ 210 | #define K210_PCF_TIMER1_TOGGLE3 196 /* TIMER1 Toggle Output 3 */ 211 | #define K210_PCF_TIMER1_TOGGLE4 197 /* TIMER1 Toggle Output 4 */ 212 | #define K210_PCF_TIMER2_TOGGLE1 198 /* TIMER2 Toggle Output 1 */ 213 | #define K210_PCF_TIMER2_TOGGLE2 199 /* TIMER2 Toggle Output 2 */ 214 | #define K210_PCF_TIMER2_TOGGLE3 200 /* TIMER2 Toggle Output 3 */ 215 | #define K210_PCF_TIMER2_TOGGLE4 201 /* TIMER2 Toggle Output 4 */ 216 | #define K210_PCF_CLK_SPI2 202 /* Clock SPI2 */ 217 | #define K210_PCF_CLK_I2C2 203 /* Clock I2C2 */ 218 | #define K210_PCF_INTERNAL0 204 /* Internal function signal 0 */ 219 | #define K210_PCF_INTERNAL1 205 /* Internal function signal 1 */ 220 | #define K210_PCF_INTERNAL2 206 /* Internal function signal 2 */ 221 | #define K210_PCF_INTERNAL3 207 /* Internal function signal 3 */ 222 | #define K210_PCF_INTERNAL4 208 /* Internal function signal 4 */ 223 | #define K210_PCF_INTERNAL5 209 /* Internal function signal 5 */ 224 | #define K210_PCF_INTERNAL6 210 /* Internal function signal 6 */ 225 | #define K210_PCF_INTERNAL7 211 /* Internal function signal 7 */ 226 | #define K210_PCF_INTERNAL8 212 /* Internal function signal 8 */ 227 | #define K210_PCF_INTERNAL9 213 /* Internal function signal 9 */ 228 | #define K210_PCF_INTERNAL10 214 /* Internal function signal 10 */ 229 | #define K210_PCF_INTERNAL11 215 /* Internal function signal 11 */ 230 | #define K210_PCF_INTERNAL12 216 /* Internal function signal 12 */ 231 | #define K210_PCF_INTERNAL13 217 /* Internal function signal 13 */ 232 | #define K210_PCF_INTERNAL14 218 /* Internal function signal 14 */ 233 | #define K210_PCF_INTERNAL15 219 /* Internal function signal 15 */ 234 | #define K210_PCF_INTERNAL16 220 /* Internal function signal 16 */ 235 | #define K210_PCF_INTERNAL17 221 /* Internal function signal 17 */ 236 | #define K210_PCF_CONSTANT 222 /* Constant function */ 237 | #define K210_PCF_INTERNAL18 223 /* Internal function signal 18 */ 238 | #define K210_PCF_DEBUG0 224 /* Debug function 0 */ 239 | #define K210_PCF_DEBUG1 225 /* Debug function 1 */ 240 | #define K210_PCF_DEBUG2 226 /* Debug function 2 */ 241 | #define K210_PCF_DEBUG3 227 /* Debug function 3 */ 242 | #define K210_PCF_DEBUG4 228 /* Debug function 4 */ 243 | #define K210_PCF_DEBUG5 229 /* Debug function 5 */ 244 | #define K210_PCF_DEBUG6 230 /* Debug function 6 */ 245 | #define K210_PCF_DEBUG7 231 /* Debug function 7 */ 246 | #define K210_PCF_DEBUG8 232 /* Debug function 8 */ 247 | #define K210_PCF_DEBUG9 233 /* Debug function 9 */ 248 | #define K210_PCF_DEBUG10 234 /* Debug function 10 */ 249 | #define K210_PCF_DEBUG11 235 /* Debug function 11 */ 250 | #define K210_PCF_DEBUG12 236 /* Debug function 12 */ 251 | #define K210_PCF_DEBUG13 237 /* Debug function 13 */ 252 | #define K210_PCF_DEBUG14 238 /* Debug function 14 */ 253 | #define K210_PCF_DEBUG15 239 /* Debug function 15 */ 254 | #define K210_PCF_DEBUG16 240 /* Debug function 16 */ 255 | #define K210_PCF_DEBUG17 241 /* Debug function 17 */ 256 | #define K210_PCF_DEBUG18 242 /* Debug function 18 */ 257 | #define K210_PCF_DEBUG19 243 /* Debug function 19 */ 258 | #define K210_PCF_DEBUG20 244 /* Debug function 20 */ 259 | #define K210_PCF_DEBUG21 245 /* Debug function 21 */ 260 | #define K210_PCF_DEBUG22 246 /* Debug function 22 */ 261 | #define K210_PCF_DEBUG23 247 /* Debug function 23 */ 262 | #define K210_PCF_DEBUG24 248 /* Debug function 24 */ 263 | #define K210_PCF_DEBUG25 249 /* Debug function 25 */ 264 | #define K210_PCF_DEBUG26 250 /* Debug function 26 */ 265 | #define K210_PCF_DEBUG27 251 /* Debug function 27 */ 266 | #define K210_PCF_DEBUG28 252 /* Debug function 28 */ 267 | #define K210_PCF_DEBUG29 253 /* Debug function 29 */ 268 | #define K210_PCF_DEBUG30 254 /* Debug function 30 */ 269 | #define K210_PCF_DEBUG31 255 /* Debug function 31 */ 270 | 271 | #define K210_FPIOA(pin, func) (((pin) << 16) | (func)) 272 | 273 | #define K210_PC_POWER_3V3 0 274 | #define K210_PC_POWER_1V8 1 275 | 276 | #endif /* PINCTRL_K210_FPIOA_H */ 277 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/k3.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for pinctrl bindings for TI's K3 SoC 4 | * family. 5 | * 6 | * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 | */ 8 | #ifndef _DT_BINDINGS_PINCTRL_TI_K3_H 9 | #define _DT_BINDINGS_PINCTRL_TI_K3_H 10 | 11 | #define PULLUDEN_SHIFT (16) 12 | #define PULLTYPESEL_SHIFT (17) 13 | #define RXACTIVE_SHIFT (18) 14 | 15 | #define PULL_DISABLE (1 << PULLUDEN_SHIFT) 16 | #define PULL_ENABLE (0 << PULLUDEN_SHIFT) 17 | 18 | #define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) 19 | #define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) 20 | 21 | #define INPUT_EN (1 << RXACTIVE_SHIFT) 22 | #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) 23 | 24 | /* Only these macros are expected be used directly in device tree files */ 25 | #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) 26 | #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) 27 | #define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) 28 | #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 29 | #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 30 | #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) 31 | 32 | #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 33 | #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 34 | 35 | #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 36 | #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 37 | 38 | #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 39 | #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 40 | 41 | #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 42 | #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 43 | 44 | #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 45 | #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 46 | 47 | #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 48 | #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/keystone.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for Keystone pinctrl bindings. 4 | * 5 | * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H 9 | #define _DT_BINDINGS_PINCTRL_KEYSTONE_H 10 | 11 | #define MUX_MODE0 0 12 | #define MUX_MODE1 1 13 | #define MUX_MODE2 2 14 | #define MUX_MODE3 3 15 | #define MUX_MODE4 4 16 | #define MUX_MODE5 5 17 | 18 | #define BUFFER_CLASS_B (0 << 19) 19 | #define BUFFER_CLASS_C (1 << 19) 20 | #define BUFFER_CLASS_D (2 << 19) 21 | #define BUFFER_CLASS_E (3 << 19) 22 | 23 | #define PULL_DISABLE (1 << 16) 24 | #define PIN_PULLUP (1 << 17) 25 | #define PIN_PULLDOWN (0 << 17) 26 | 27 | #define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) 28 | 29 | #define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000) 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/lochnagar.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Device Tree defines for Lochnagar pinctrl 4 | * 5 | * Copyright (c) 2018 Cirrus Logic, Inc. and 6 | * Cirrus Logic International Semiconductor Ltd. 7 | * 8 | * Author: Charles Keepax 9 | */ 10 | 11 | #ifndef DT_BINDINGS_PINCTRL_LOCHNAGAR_H 12 | #define DT_BINDINGS_PINCTRL_LOCHNAGAR_H 13 | 14 | #define LOCHNAGAR1_PIN_CDC_RESET 0 15 | #define LOCHNAGAR1_PIN_DSP_RESET 1 16 | #define LOCHNAGAR1_PIN_CDC_CIF1MODE 2 17 | #define LOCHNAGAR1_PIN_NUM_GPIOS 3 18 | 19 | #define LOCHNAGAR2_PIN_CDC_RESET 0 20 | #define LOCHNAGAR2_PIN_DSP_RESET 1 21 | #define LOCHNAGAR2_PIN_CDC_CIF1MODE 2 22 | #define LOCHNAGAR2_PIN_CDC_LDOENA 3 23 | #define LOCHNAGAR2_PIN_SPDIF_HWMODE 4 24 | #define LOCHNAGAR2_PIN_SPDIF_RESET 5 25 | #define LOCHNAGAR2_PIN_FPGA_GPIO1 6 26 | #define LOCHNAGAR2_PIN_FPGA_GPIO2 7 27 | #define LOCHNAGAR2_PIN_FPGA_GPIO3 8 28 | #define LOCHNAGAR2_PIN_FPGA_GPIO4 9 29 | #define LOCHNAGAR2_PIN_FPGA_GPIO5 10 30 | #define LOCHNAGAR2_PIN_FPGA_GPIO6 11 31 | #define LOCHNAGAR2_PIN_CDC_GPIO1 12 32 | #define LOCHNAGAR2_PIN_CDC_GPIO2 13 33 | #define LOCHNAGAR2_PIN_CDC_GPIO3 14 34 | #define LOCHNAGAR2_PIN_CDC_GPIO4 15 35 | #define LOCHNAGAR2_PIN_CDC_GPIO5 16 36 | #define LOCHNAGAR2_PIN_CDC_GPIO6 17 37 | #define LOCHNAGAR2_PIN_CDC_GPIO7 18 38 | #define LOCHNAGAR2_PIN_CDC_GPIO8 19 39 | #define LOCHNAGAR2_PIN_DSP_GPIO1 20 40 | #define LOCHNAGAR2_PIN_DSP_GPIO2 21 41 | #define LOCHNAGAR2_PIN_DSP_GPIO3 22 42 | #define LOCHNAGAR2_PIN_DSP_GPIO4 23 43 | #define LOCHNAGAR2_PIN_DSP_GPIO5 24 44 | #define LOCHNAGAR2_PIN_DSP_GPIO6 25 45 | #define LOCHNAGAR2_PIN_GF_GPIO2 26 46 | #define LOCHNAGAR2_PIN_GF_GPIO3 27 47 | #define LOCHNAGAR2_PIN_GF_GPIO7 28 48 | #define LOCHNAGAR2_PIN_CDC_AIF1_BCLK 29 49 | #define LOCHNAGAR2_PIN_CDC_AIF1_RXDAT 30 50 | #define LOCHNAGAR2_PIN_CDC_AIF1_LRCLK 31 51 | #define LOCHNAGAR2_PIN_CDC_AIF1_TXDAT 32 52 | #define LOCHNAGAR2_PIN_CDC_AIF2_BCLK 33 53 | #define LOCHNAGAR2_PIN_CDC_AIF2_RXDAT 34 54 | #define LOCHNAGAR2_PIN_CDC_AIF2_LRCLK 35 55 | #define LOCHNAGAR2_PIN_CDC_AIF2_TXDAT 36 56 | #define LOCHNAGAR2_PIN_CDC_AIF3_BCLK 37 57 | #define LOCHNAGAR2_PIN_CDC_AIF3_RXDAT 38 58 | #define LOCHNAGAR2_PIN_CDC_AIF3_LRCLK 39 59 | #define LOCHNAGAR2_PIN_CDC_AIF3_TXDAT 40 60 | #define LOCHNAGAR2_PIN_DSP_AIF1_BCLK 41 61 | #define LOCHNAGAR2_PIN_DSP_AIF1_RXDAT 42 62 | #define LOCHNAGAR2_PIN_DSP_AIF1_LRCLK 43 63 | #define LOCHNAGAR2_PIN_DSP_AIF1_TXDAT 44 64 | #define LOCHNAGAR2_PIN_DSP_AIF2_BCLK 45 65 | #define LOCHNAGAR2_PIN_DSP_AIF2_RXDAT 46 66 | #define LOCHNAGAR2_PIN_DSP_AIF2_LRCLK 47 67 | #define LOCHNAGAR2_PIN_DSP_AIF2_TXDAT 48 68 | #define LOCHNAGAR2_PIN_PSIA1_BCLK 49 69 | #define LOCHNAGAR2_PIN_PSIA1_RXDAT 50 70 | #define LOCHNAGAR2_PIN_PSIA1_LRCLK 51 71 | #define LOCHNAGAR2_PIN_PSIA1_TXDAT 52 72 | #define LOCHNAGAR2_PIN_PSIA2_BCLK 53 73 | #define LOCHNAGAR2_PIN_PSIA2_RXDAT 54 74 | #define LOCHNAGAR2_PIN_PSIA2_LRCLK 55 75 | #define LOCHNAGAR2_PIN_PSIA2_TXDAT 56 76 | #define LOCHNAGAR2_PIN_GF_AIF3_BCLK 57 77 | #define LOCHNAGAR2_PIN_GF_AIF3_RXDAT 58 78 | #define LOCHNAGAR2_PIN_GF_AIF3_LRCLK 59 79 | #define LOCHNAGAR2_PIN_GF_AIF3_TXDAT 60 80 | #define LOCHNAGAR2_PIN_GF_AIF4_BCLK 61 81 | #define LOCHNAGAR2_PIN_GF_AIF4_RXDAT 62 82 | #define LOCHNAGAR2_PIN_GF_AIF4_LRCLK 63 83 | #define LOCHNAGAR2_PIN_GF_AIF4_TXDAT 64 84 | #define LOCHNAGAR2_PIN_GF_AIF1_BCLK 65 85 | #define LOCHNAGAR2_PIN_GF_AIF1_RXDAT 66 86 | #define LOCHNAGAR2_PIN_GF_AIF1_LRCLK 67 87 | #define LOCHNAGAR2_PIN_GF_AIF1_TXDAT 68 88 | #define LOCHNAGAR2_PIN_GF_AIF2_BCLK 69 89 | #define LOCHNAGAR2_PIN_GF_AIF2_RXDAT 70 90 | #define LOCHNAGAR2_PIN_GF_AIF2_LRCLK 71 91 | #define LOCHNAGAR2_PIN_GF_AIF2_TXDAT 72 92 | #define LOCHNAGAR2_PIN_DSP_UART1_RX 73 93 | #define LOCHNAGAR2_PIN_DSP_UART1_TX 74 94 | #define LOCHNAGAR2_PIN_DSP_UART2_RX 75 95 | #define LOCHNAGAR2_PIN_DSP_UART2_TX 76 96 | #define LOCHNAGAR2_PIN_GF_UART2_RX 77 97 | #define LOCHNAGAR2_PIN_GF_UART2_TX 78 98 | #define LOCHNAGAR2_PIN_USB_UART_RX 79 99 | #define LOCHNAGAR2_PIN_CDC_PDMCLK1 80 100 | #define LOCHNAGAR2_PIN_CDC_PDMDAT1 81 101 | #define LOCHNAGAR2_PIN_CDC_PDMCLK2 82 102 | #define LOCHNAGAR2_PIN_CDC_PDMDAT2 83 103 | #define LOCHNAGAR2_PIN_CDC_DMICCLK1 84 104 | #define LOCHNAGAR2_PIN_CDC_DMICDAT1 85 105 | #define LOCHNAGAR2_PIN_CDC_DMICCLK2 86 106 | #define LOCHNAGAR2_PIN_CDC_DMICDAT2 87 107 | #define LOCHNAGAR2_PIN_CDC_DMICCLK3 88 108 | #define LOCHNAGAR2_PIN_CDC_DMICDAT3 89 109 | #define LOCHNAGAR2_PIN_CDC_DMICCLK4 90 110 | #define LOCHNAGAR2_PIN_CDC_DMICDAT4 91 111 | #define LOCHNAGAR2_PIN_DSP_DMICCLK1 92 112 | #define LOCHNAGAR2_PIN_DSP_DMICDAT1 93 113 | #define LOCHNAGAR2_PIN_DSP_DMICCLK2 94 114 | #define LOCHNAGAR2_PIN_DSP_DMICDAT2 95 115 | #define LOCHNAGAR2_PIN_I2C2_SCL 96 116 | #define LOCHNAGAR2_PIN_I2C2_SDA 97 117 | #define LOCHNAGAR2_PIN_I2C3_SCL 98 118 | #define LOCHNAGAR2_PIN_I2C3_SDA 99 119 | #define LOCHNAGAR2_PIN_I2C4_SCL 100 120 | #define LOCHNAGAR2_PIN_I2C4_SDA 101 121 | #define LOCHNAGAR2_PIN_DSP_STANDBY 102 122 | #define LOCHNAGAR2_PIN_CDC_MCLK1 103 123 | #define LOCHNAGAR2_PIN_CDC_MCLK2 104 124 | #define LOCHNAGAR2_PIN_DSP_CLKIN 105 125 | #define LOCHNAGAR2_PIN_PSIA1_MCLK 106 126 | #define LOCHNAGAR2_PIN_PSIA2_MCLK 107 127 | #define LOCHNAGAR2_PIN_GF_GPIO1 108 128 | #define LOCHNAGAR2_PIN_GF_GPIO5 109 129 | #define LOCHNAGAR2_PIN_DSP_GPIO20 110 130 | #define LOCHNAGAR2_PIN_NUM_GPIOS 111 131 | 132 | #endif 133 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/mt6397-pinfunc.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | #ifndef __DTS_MT6397_PINFUNC_H 3 | #define __DTS_MT6397_PINFUNC_H 4 | 5 | #include 6 | 7 | #define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) 8 | #define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) 9 | 10 | #define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) 11 | #define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) 12 | #define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6) 13 | 14 | #define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) 15 | #define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) 16 | #define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6) 17 | 18 | #define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) 19 | #define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1) 20 | #define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6) 21 | 22 | #define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) 23 | #define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1) 24 | 25 | #define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) 26 | #define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1) 27 | 28 | #define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) 29 | #define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1) 30 | 31 | #define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) 32 | #define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1) 33 | 34 | #define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) 35 | #define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1) 36 | 37 | #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) 38 | #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1) 39 | #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6) 40 | #define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7) 41 | 42 | #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) 43 | #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1) 44 | #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6) 45 | #define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7) 46 | 47 | #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) 48 | #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1) 49 | #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6) 50 | #define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7) 51 | 52 | #define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) 53 | #define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1) 54 | #define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2) 55 | #define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3) 56 | #define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6) 57 | #define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7) 58 | 59 | #define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) 60 | #define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1) 61 | #define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2) 62 | #define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3) 63 | #define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6) 64 | #define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7) 65 | 66 | #define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) 67 | #define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1) 68 | #define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2) 69 | #define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3) 70 | #define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6) 71 | #define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7) 72 | 73 | #define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) 74 | #define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1) 75 | #define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2) 76 | #define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3) 77 | #define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6) 78 | #define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7) 79 | 80 | #define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) 81 | #define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1) 82 | #define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2) 83 | #define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3) 84 | #define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6) 85 | #define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7) 86 | 87 | #define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) 88 | #define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1) 89 | #define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2) 90 | #define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3) 91 | #define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6) 92 | #define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7) 93 | 94 | #define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) 95 | #define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1) 96 | #define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2) 97 | #define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3) 98 | #define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4) 99 | #define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5) 100 | #define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6) 101 | #define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7) 102 | 103 | #define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) 104 | #define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1) 105 | #define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2) 106 | #define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3) 107 | #define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4) 108 | #define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5) 109 | #define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6) 110 | #define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7) 111 | 112 | #define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) 113 | #define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1) 114 | #define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2) 115 | #define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3) 116 | #define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6) 117 | #define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7) 118 | 119 | #define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) 120 | #define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1) 121 | #define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2) 122 | #define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3) 123 | #define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4) 124 | #define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6) 125 | #define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7) 126 | 127 | #define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) 128 | #define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1) 129 | #define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2) 130 | #define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3) 131 | #define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6) 132 | #define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7) 133 | 134 | #define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) 135 | #define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1) 136 | #define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2) 137 | #define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3) 138 | #define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6) 139 | #define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7) 140 | 141 | #define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) 142 | #define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1) 143 | #define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2) 144 | #define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3) 145 | #define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6) 146 | #define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7) 147 | 148 | #define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) 149 | #define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1) 150 | #define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2) 151 | #define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3) 152 | #define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6) 153 | #define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7) 154 | 155 | #define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) 156 | #define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1) 157 | #define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2) 158 | #define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3) 159 | #define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4) 160 | #define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5) 161 | #define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6) 162 | #define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7) 163 | 164 | #define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) 165 | #define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1) 166 | #define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2) 167 | #define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3) 168 | #define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4) 169 | #define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5) 170 | #define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6) 171 | #define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7) 172 | 173 | #define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) 174 | #define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1) 175 | #define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2) 176 | #define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4) 177 | #define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5) 178 | #define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6) 179 | #define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7) 180 | 181 | #define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) 182 | #define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1) 183 | #define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2) 184 | #define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4) 185 | #define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5) 186 | #define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6) 187 | #define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7) 188 | 189 | #define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) 190 | #define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1) 191 | #define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2) 192 | #define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3) 193 | #define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4) 194 | #define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5) 195 | #define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6) 196 | #define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7) 197 | 198 | #define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) 199 | #define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1) 200 | #define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2) 201 | #define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3) 202 | #define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6) 203 | #define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7) 204 | 205 | #define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) 206 | #define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1) 207 | #define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2) 208 | #define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6) 209 | #define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7) 210 | 211 | #define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) 212 | #define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1) 213 | #define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2) 214 | #define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3) 215 | #define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6) 216 | #define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7) 217 | 218 | #define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) 219 | #define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1) 220 | #define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2) 221 | #define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6) 222 | #define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7) 223 | 224 | #define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) 225 | #define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1) 226 | #define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2) 227 | #define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3) 228 | #define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6) 229 | #define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7) 230 | 231 | #define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) 232 | #define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1) 233 | #define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2) 234 | #define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6) 235 | #define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7) 236 | 237 | #define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) 238 | #define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1) 239 | #define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6) 240 | #define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7) 241 | 242 | #define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) 243 | #define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1) 244 | #define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6) 245 | #define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7) 246 | 247 | #define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) 248 | #define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1) 249 | #define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6) 250 | #define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7) 251 | 252 | #define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) 253 | #define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1) 254 | #define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6) 255 | #define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7) 256 | 257 | #endif /* __DTS_MT6397_PINFUNC_H */ 258 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/mt65xx.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * Copyright (c) 2014 MediaTek Inc. 4 | * Author: Hongzhou.Yang 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_PINCTRL_MT65XX_H 8 | #define _DT_BINDINGS_PINCTRL_MT65XX_H 9 | 10 | #define MTK_PIN_NO(x) ((x) << 8) 11 | #define MTK_GET_PIN_NO(x) ((x) >> 8) 12 | #define MTK_GET_PIN_FUNC(x) ((x) & 0xf) 13 | 14 | #define MTK_PUPD_SET_R1R0_00 100 15 | #define MTK_PUPD_SET_R1R0_01 101 16 | #define MTK_PUPD_SET_R1R0_10 102 17 | #define MTK_PUPD_SET_R1R0_11 103 18 | 19 | #define MTK_PULL_SET_RSEL_000 200 20 | #define MTK_PULL_SET_RSEL_001 201 21 | #define MTK_PULL_SET_RSEL_010 202 22 | #define MTK_PULL_SET_RSEL_011 203 23 | #define MTK_PULL_SET_RSEL_100 204 24 | #define MTK_PULL_SET_RSEL_101 205 25 | #define MTK_PULL_SET_RSEL_110 206 26 | #define MTK_PULL_SET_RSEL_111 207 27 | 28 | #define MTK_DRIVE_2mA 2 29 | #define MTK_DRIVE_4mA 4 30 | #define MTK_DRIVE_6mA 6 31 | #define MTK_DRIVE_8mA 8 32 | #define MTK_DRIVE_10mA 10 33 | #define MTK_DRIVE_12mA 12 34 | #define MTK_DRIVE_14mA 14 35 | #define MTK_DRIVE_16mA 16 36 | #define MTK_DRIVE_20mA 20 37 | #define MTK_DRIVE_24mA 24 38 | #define MTK_DRIVE_28mA 28 39 | #define MTK_DRIVE_32mA 32 40 | 41 | #endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ 42 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/nomadik.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * nomadik.h 4 | * 5 | * Copyright (C) ST-Ericsson SA 2013 6 | * Author: Gabriel Fernandez for ST-Ericsson. 7 | */ 8 | 9 | #define INPUT_NOPULL 0 10 | #define INPUT_PULLUP 1 11 | #define INPUT_PULLDOWN 2 12 | 13 | #define OUTPUT_LOW 0 14 | #define OUTPUT_HIGH 1 15 | #define DIR_OUTPUT 2 16 | 17 | #define SLPM_DISABLED 0 18 | #define SLPM_ENABLED 1 19 | 20 | #define SLPM_INPUT_NOPULL 0 21 | #define SLPM_INPUT_PULLUP 1 22 | #define SLPM_INPUT_PULLDOWN 2 23 | #define SLPM_DIR_INPUT 3 24 | 25 | #define SLPM_OUTPUT_LOW 0 26 | #define SLPM_OUTPUT_HIGH 1 27 | #define SLPM_DIR_OUTPUT 2 28 | 29 | #define SLPM_WAKEUP_DISABLE 0 30 | #define SLPM_WAKEUP_ENABLE 1 31 | 32 | #define GPIOMODE_DISABLED 0 33 | #define GPIOMODE_ENABLED 1 34 | 35 | #define SLPM_PDIS_DISABLED 0 36 | #define SLPM_PDIS_ENABLED 1 37 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/omap.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for OMAP pinctrl bindings. 4 | * 5 | * Copyright (C) 2009 Nokia 6 | * Copyright (C) 2009-2010 Texas Instruments 7 | */ 8 | 9 | #ifndef _DT_BINDINGS_PINCTRL_OMAP_H 10 | #define _DT_BINDINGS_PINCTRL_OMAP_H 11 | 12 | /* 34xx mux mode options for each pin. See TRM for options */ 13 | #define MUX_MODE0 0 14 | #define MUX_MODE1 1 15 | #define MUX_MODE2 2 16 | #define MUX_MODE3 3 17 | #define MUX_MODE4 4 18 | #define MUX_MODE5 5 19 | #define MUX_MODE6 6 20 | #define MUX_MODE7 7 21 | 22 | /* 24xx/34xx mux bit defines */ 23 | #define PULL_ENA (1 << 3) 24 | #define PULL_UP (1 << 4) 25 | #define ALTELECTRICALSEL (1 << 5) 26 | 27 | /* omap3/4/5 specific mux bit defines */ 28 | #define INPUT_EN (1 << 8) 29 | #define OFF_EN (1 << 9) 30 | #define OFFOUT_EN (1 << 10) 31 | #define OFFOUT_VAL (1 << 11) 32 | #define OFF_PULL_EN (1 << 12) 33 | #define OFF_PULL_UP (1 << 13) 34 | #define WAKEUP_EN (1 << 14) 35 | #define WAKEUP_EVENT (1 << 15) 36 | 37 | /* Active pin states */ 38 | #define PIN_OUTPUT 0 39 | #define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) 40 | #define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) 41 | #define PIN_INPUT INPUT_EN 42 | #define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) 43 | #define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) 44 | 45 | /* Off mode states */ 46 | #define PIN_OFF_NONE 0 47 | #define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) 48 | #define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) 49 | #define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP) 50 | #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN) 51 | #define PIN_OFF_WAKEUPENABLE WAKEUP_EN 52 | 53 | /* 54 | * Macros to allow using the absolute physical address instead of the 55 | * padconf registers instead of the offset from padconf base. 56 | */ 57 | #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) 58 | 59 | #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) 60 | #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) 61 | #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) 62 | #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) 63 | #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) 64 | #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) 65 | #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 66 | #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 67 | #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) 68 | #define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) 69 | 70 | /* 71 | * Macros to allow using the offset from the padconf physical address 72 | * instead of the offset from padconf base. 73 | */ 74 | #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) 75 | 76 | #define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) 77 | #define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) 78 | 79 | /* 80 | * Define some commonly used pins configured by the boards. 81 | * Note that some boards use alternative pins, so check 82 | * the schematics before using these. 83 | */ 84 | #define OMAP3_UART1_RX 0x152 85 | #define OMAP3_UART2_RX 0x14a 86 | #define OMAP3_UART3_RX 0x16e 87 | #define OMAP4_UART2_RX 0xdc 88 | #define OMAP4_UART3_RX 0x104 89 | #define OMAP4_UART4_RX 0x11c 90 | 91 | #endif 92 | 93 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 | /* 3 | * Copyright (C) 2021 Emil Renner Berthing 4 | */ 5 | 6 | #ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ 7 | #define __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ 8 | 9 | #define PAD_GPIO_OFFSET 0 10 | #define PAD_FUNC_SHARE_OFFSET 64 11 | #define PAD_GPIO(x) (PAD_GPIO_OFFSET + (x)) 12 | #define PAD_FUNC_SHARE(x) (PAD_FUNC_SHARE_OFFSET + (x)) 13 | 14 | /* 15 | * GPIOMUX bits: 16 | * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 | 17 | * | dout | doen | din | dout rev | doen rev | gpio nr | 18 | * 19 | * dout: output signal 20 | * doen: output enable signal 21 | * din: optional input signal, 0xff = none 22 | * dout rev: output signal reverse bit 23 | * doen rev: output enable signal reverse bit 24 | * gpio nr: gpio number, 0 - 63 25 | */ 26 | #define GPIOMUX(n, dout, doen, din) ( \ 27 | (((dout) & 0x80000000) >> (31 - 7)) | (((dout) & 0xff) << 24) | \ 28 | (((doen) & 0x80000000) >> (31 - 6)) | (((doen) & 0xff) << 16) | \ 29 | (((din) & 0xff) << 8) | \ 30 | ((n) & 0x3f)) 31 | 32 | #define GPO_REVERSE 0x80000000 33 | 34 | #define GPO_LOW 0 35 | #define GPO_HIGH 1 36 | #define GPO_ENABLE 0 37 | #define GPO_DISABLE 1 38 | #define GPO_CLK_GMAC_PAPHYREF 2 39 | #define GPO_JTAG_TDO 3 40 | #define GPO_JTAG_TDO_OEN 4 41 | #define GPO_DMIC_CLK_OUT 5 42 | #define GPO_DSP_JTDOEN_PAD 6 43 | #define GPO_DSP_JTDO_PAD 7 44 | #define GPO_I2C0_PAD_SCK_OE 8 45 | #define GPO_I2C0_PAD_SCK_OEN (GPO_I2C0_PAD_SCK_OE | GPO_REVERSE) 46 | #define GPO_I2C0_PAD_SDA_OE 9 47 | #define GPO_I2C0_PAD_SDA_OEN (GPO_I2C0_PAD_SDA_OE | GPO_REVERSE) 48 | #define GPO_I2C1_PAD_SCK_OE 10 49 | #define GPO_I2C1_PAD_SCK_OEN (GPO_I2C1_PAD_SCK_OE | GPO_REVERSE) 50 | #define GPO_I2C1_PAD_SDA_OE 11 51 | #define GPO_I2C1_PAD_SDA_OEN (GPO_I2C1_PAD_SDA_OE | GPO_REVERSE) 52 | #define GPO_I2C2_PAD_SCK_OE 12 53 | #define GPO_I2C2_PAD_SCK_OEN (GPO_I2C2_PAD_SCK_OE | GPO_REVERSE) 54 | #define GPO_I2C2_PAD_SDA_OE 13 55 | #define GPO_I2C2_PAD_SDA_OEN (GPO_I2C2_PAD_SDA_OE | GPO_REVERSE) 56 | #define GPO_I2C3_PAD_SCK_OE 14 57 | #define GPO_I2C3_PAD_SCK_OEN (GPO_I2C3_PAD_SCK_OE | GPO_REVERSE) 58 | #define GPO_I2C3_PAD_SDA_OE 15 59 | #define GPO_I2C3_PAD_SDA_OEN (GPO_I2C3_PAD_SDA_OE | GPO_REVERSE) 60 | #define GPO_I2SRX_BCLK_OUT 16 61 | #define GPO_I2SRX_BCLK_OUT_OEN 17 62 | #define GPO_I2SRX_LRCK_OUT 18 63 | #define GPO_I2SRX_LRCK_OUT_OEN 19 64 | #define GPO_I2SRX_MCLK_OUT 20 65 | #define GPO_I2STX_BCLK_OUT 21 66 | #define GPO_I2STX_BCLK_OUT_OEN 22 67 | #define GPO_I2STX_LRCK_OUT 23 68 | #define GPO_I2STX_LRCK_OUT_OEN 24 69 | #define GPO_I2STX_MCLK_OUT 25 70 | #define GPO_I2STX_SDOUT0 26 71 | #define GPO_I2STX_SDOUT1 27 72 | #define GPO_LCD_PAD_CSM_N 28 73 | #define GPO_PWM_PAD_OE_N_BIT0 29 74 | #define GPO_PWM_PAD_OE_N_BIT1 30 75 | #define GPO_PWM_PAD_OE_N_BIT2 31 76 | #define GPO_PWM_PAD_OE_N_BIT3 32 77 | #define GPO_PWM_PAD_OE_N_BIT4 33 78 | #define GPO_PWM_PAD_OE_N_BIT5 34 79 | #define GPO_PWM_PAD_OE_N_BIT6 35 80 | #define GPO_PWM_PAD_OE_N_BIT7 36 81 | #define GPO_PWM_PAD_OUT_BIT0 37 82 | #define GPO_PWM_PAD_OUT_BIT1 38 83 | #define GPO_PWM_PAD_OUT_BIT2 39 84 | #define GPO_PWM_PAD_OUT_BIT3 40 85 | #define GPO_PWM_PAD_OUT_BIT4 41 86 | #define GPO_PWM_PAD_OUT_BIT5 42 87 | #define GPO_PWM_PAD_OUT_BIT6 43 88 | #define GPO_PWM_PAD_OUT_BIT7 44 89 | #define GPO_PWMDAC_LEFT_OUT 45 90 | #define GPO_PWMDAC_RIGHT_OUT 46 91 | #define GPO_QSPI_CSN1_OUT 47 92 | #define GPO_QSPI_CSN2_OUT 48 93 | #define GPO_QSPI_CSN3_OUT 49 94 | #define GPO_REGISTER23_SCFG_CMSENSOR_RST0 50 95 | #define GPO_REGISTER23_SCFG_CMSENSOR_RST1 51 96 | #define GPO_REGISTER32_SCFG_GMAC_PHY_RSTN 52 97 | #define GPO_SDIO0_PAD_CARD_POWER_EN 53 98 | #define GPO_SDIO0_PAD_CCLK_OUT 54 99 | #define GPO_SDIO0_PAD_CCMD_OE 55 100 | #define GPO_SDIO0_PAD_CCMD_OEN (GPO_SDIO0_PAD_CCMD_OE | GPO_REVERSE) 101 | #define GPO_SDIO0_PAD_CCMD_OUT 56 102 | #define GPO_SDIO0_PAD_CDATA_OE_BIT0 57 103 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT0 (GPO_SDIO0_PAD_CDATA_OE_BIT0 | GPO_REVERSE) 104 | #define GPO_SDIO0_PAD_CDATA_OE_BIT1 58 105 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT1 (GPO_SDIO0_PAD_CDATA_OE_BIT1 | GPO_REVERSE) 106 | #define GPO_SDIO0_PAD_CDATA_OE_BIT2 59 107 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT2 (GPO_SDIO0_PAD_CDATA_OE_BIT2 | GPO_REVERSE) 108 | #define GPO_SDIO0_PAD_CDATA_OE_BIT3 60 109 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT3 (GPO_SDIO0_PAD_CDATA_OE_BIT3 | GPO_REVERSE) 110 | #define GPO_SDIO0_PAD_CDATA_OE_BIT4 61 111 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT4 (GPO_SDIO0_PAD_CDATA_OE_BIT4 | GPO_REVERSE) 112 | #define GPO_SDIO0_PAD_CDATA_OE_BIT5 62 113 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT5 (GPO_SDIO0_PAD_CDATA_OE_BIT5 | GPO_REVERSE) 114 | #define GPO_SDIO0_PAD_CDATA_OE_BIT6 63 115 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT6 (GPO_SDIO0_PAD_CDATA_OE_BIT6 | GPO_REVERSE) 116 | #define GPO_SDIO0_PAD_CDATA_OE_BIT7 64 117 | #define GPO_SDIO0_PAD_CDATA_OEN_BIT7 (GPO_SDIO0_PAD_CDATA_OE_BIT7 | GPO_REVERSE) 118 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT0 65 119 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT1 66 120 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT2 67 121 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT3 68 122 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT4 69 123 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT5 70 124 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT6 71 125 | #define GPO_SDIO0_PAD_CDATA_OUT_BIT7 72 126 | #define GPO_SDIO0_PAD_RST_N 73 127 | #define GPO_SDIO1_PAD_CARD_POWER_EN 74 128 | #define GPO_SDIO1_PAD_CCLK_OUT 75 129 | #define GPO_SDIO1_PAD_CCMD_OE 76 130 | #define GPO_SDIO1_PAD_CCMD_OEN (GPO_SDIO1_PAD_CCMD_OE | GPO_REVERSE) 131 | #define GPO_SDIO1_PAD_CCMD_OUT 77 132 | #define GPO_SDIO1_PAD_CDATA_OE_BIT0 78 133 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT0 (GPO_SDIO1_PAD_CDATA_OE_BIT0 | GPO_REVERSE) 134 | #define GPO_SDIO1_PAD_CDATA_OE_BIT1 79 135 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT1 (GPO_SDIO1_PAD_CDATA_OE_BIT1 | GPO_REVERSE) 136 | #define GPO_SDIO1_PAD_CDATA_OE_BIT2 80 137 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT2 (GPO_SDIO1_PAD_CDATA_OE_BIT2 | GPO_REVERSE) 138 | #define GPO_SDIO1_PAD_CDATA_OE_BIT3 81 139 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT3 (GPO_SDIO1_PAD_CDATA_OE_BIT3 | GPO_REVERSE) 140 | #define GPO_SDIO1_PAD_CDATA_OE_BIT4 82 141 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT4 (GPO_SDIO1_PAD_CDATA_OE_BIT4 | GPO_REVERSE) 142 | #define GPO_SDIO1_PAD_CDATA_OE_BIT5 83 143 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT5 (GPO_SDIO1_PAD_CDATA_OE_BIT5 | GPO_REVERSE) 144 | #define GPO_SDIO1_PAD_CDATA_OE_BIT6 84 145 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT6 (GPO_SDIO1_PAD_CDATA_OE_BIT6 | GPO_REVERSE) 146 | #define GPO_SDIO1_PAD_CDATA_OE_BIT7 85 147 | #define GPO_SDIO1_PAD_CDATA_OEN_BIT7 (GPO_SDIO1_PAD_CDATA_OE_BIT7 | GPO_REVERSE) 148 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT0 86 149 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT1 87 150 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT2 88 151 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT3 89 152 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT4 90 153 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT5 91 154 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT6 92 155 | #define GPO_SDIO1_PAD_CDATA_OUT_BIT7 93 156 | #define GPO_SDIO1_PAD_RST_N 94 157 | #define GPO_SPDIF_TX_SDOUT 95 158 | #define GPO_SPDIF_TX_SDOUT_OEN 96 159 | #define GPO_SPI0_PAD_OE_N 97 160 | #define GPO_SPI0_PAD_SCK_OUT 98 161 | #define GPO_SPI0_PAD_SS_0_N 99 162 | #define GPO_SPI0_PAD_SS_1_N 100 163 | #define GPO_SPI0_PAD_TXD 101 164 | #define GPO_SPI1_PAD_OE_N 102 165 | #define GPO_SPI1_PAD_SCK_OUT 103 166 | #define GPO_SPI1_PAD_SS_0_N 104 167 | #define GPO_SPI1_PAD_SS_1_N 105 168 | #define GPO_SPI1_PAD_TXD 106 169 | #define GPO_SPI2_PAD_OE_N 107 170 | #define GPO_SPI2_PAD_SCK_OUT 108 171 | #define GPO_SPI2_PAD_SS_0_N 109 172 | #define GPO_SPI2_PAD_SS_1_N 110 173 | #define GPO_SPI2_PAD_TXD 111 174 | #define GPO_SPI2AHB_PAD_OE_N_BIT0 112 175 | #define GPO_SPI2AHB_PAD_OE_N_BIT1 113 176 | #define GPO_SPI2AHB_PAD_OE_N_BIT2 114 177 | #define GPO_SPI2AHB_PAD_OE_N_BIT3 115 178 | #define GPO_SPI2AHB_PAD_TXD_BIT0 116 179 | #define GPO_SPI2AHB_PAD_TXD_BIT1 117 180 | #define GPO_SPI2AHB_PAD_TXD_BIT2 118 181 | #define GPO_SPI2AHB_PAD_TXD_BIT3 119 182 | #define GPO_SPI3_PAD_OE_N 120 183 | #define GPO_SPI3_PAD_SCK_OUT 121 184 | #define GPO_SPI3_PAD_SS_0_N 122 185 | #define GPO_SPI3_PAD_SS_1_N 123 186 | #define GPO_SPI3_PAD_TXD 124 187 | #define GPO_UART0_PAD_DTRN 125 188 | #define GPO_UART0_PAD_RTSN 126 189 | #define GPO_UART0_PAD_SOUT 127 190 | #define GPO_UART1_PAD_SOUT 128 191 | #define GPO_UART2_PAD_DTR_N 129 192 | #define GPO_UART2_PAD_RTS_N 130 193 | #define GPO_UART2_PAD_SOUT 131 194 | #define GPO_UART3_PAD_SOUT 132 195 | #define GPO_USB_DRV_BUS 133 196 | 197 | #define GPI_CPU_JTAG_TCK 0 198 | #define GPI_CPU_JTAG_TDI 1 199 | #define GPI_CPU_JTAG_TMS 2 200 | #define GPI_CPU_JTAG_TRST 3 201 | #define GPI_DMIC_SDIN_BIT0 4 202 | #define GPI_DMIC_SDIN_BIT1 5 203 | #define GPI_DSP_JTCK_PAD 6 204 | #define GPI_DSP_JTDI_PAD 7 205 | #define GPI_DSP_JTMS_PAD 8 206 | #define GPI_DSP_TRST_PAD 9 207 | #define GPI_I2C0_PAD_SCK_IN 10 208 | #define GPI_I2C0_PAD_SDA_IN 11 209 | #define GPI_I2C1_PAD_SCK_IN 12 210 | #define GPI_I2C1_PAD_SDA_IN 13 211 | #define GPI_I2C2_PAD_SCK_IN 14 212 | #define GPI_I2C2_PAD_SDA_IN 15 213 | #define GPI_I2C3_PAD_SCK_IN 16 214 | #define GPI_I2C3_PAD_SDA_IN 17 215 | #define GPI_I2SRX_BCLK_IN 18 216 | #define GPI_I2SRX_LRCK_IN 19 217 | #define GPI_I2SRX_SDIN_BIT0 20 218 | #define GPI_I2SRX_SDIN_BIT1 21 219 | #define GPI_I2SRX_SDIN_BIT2 22 220 | #define GPI_I2STX_BCLK_IN 23 221 | #define GPI_I2STX_LRCK_IN 24 222 | #define GPI_SDIO0_PAD_CARD_DETECT_N 25 223 | #define GPI_SDIO0_PAD_CARD_WRITE_PRT 26 224 | #define GPI_SDIO0_PAD_CCMD_IN 27 225 | #define GPI_SDIO0_PAD_CDATA_IN_BIT0 28 226 | #define GPI_SDIO0_PAD_CDATA_IN_BIT1 29 227 | #define GPI_SDIO0_PAD_CDATA_IN_BIT2 30 228 | #define GPI_SDIO0_PAD_CDATA_IN_BIT3 31 229 | #define GPI_SDIO0_PAD_CDATA_IN_BIT4 32 230 | #define GPI_SDIO0_PAD_CDATA_IN_BIT5 33 231 | #define GPI_SDIO0_PAD_CDATA_IN_BIT6 34 232 | #define GPI_SDIO0_PAD_CDATA_IN_BIT7 35 233 | #define GPI_SDIO1_PAD_CARD_DETECT_N 36 234 | #define GPI_SDIO1_PAD_CARD_WRITE_PRT 37 235 | #define GPI_SDIO1_PAD_CCMD_IN 38 236 | #define GPI_SDIO1_PAD_CDATA_IN_BIT0 39 237 | #define GPI_SDIO1_PAD_CDATA_IN_BIT1 40 238 | #define GPI_SDIO1_PAD_CDATA_IN_BIT2 41 239 | #define GPI_SDIO1_PAD_CDATA_IN_BIT3 42 240 | #define GPI_SDIO1_PAD_CDATA_IN_BIT4 43 241 | #define GPI_SDIO1_PAD_CDATA_IN_BIT5 44 242 | #define GPI_SDIO1_PAD_CDATA_IN_BIT6 45 243 | #define GPI_SDIO1_PAD_CDATA_IN_BIT7 46 244 | #define GPI_SPDIF_RX_SDIN 47 245 | #define GPI_SPI0_PAD_RXD 48 246 | #define GPI_SPI0_PAD_SS_IN_N 49 247 | #define GPI_SPI1_PAD_RXD 50 248 | #define GPI_SPI1_PAD_SS_IN_N 51 249 | #define GPI_SPI2_PAD_RXD 52 250 | #define GPI_SPI2_PAD_SS_IN_N 53 251 | #define GPI_SPI2AHB_PAD_RXD_BIT0 54 252 | #define GPI_SPI2AHB_PAD_RXD_BIT1 55 253 | #define GPI_SPI2AHB_PAD_RXD_BIT2 56 254 | #define GPI_SPI2AHB_PAD_RXD_BIT3 57 255 | #define GPI_SPI2AHB_PAD_SS_N 58 256 | #define GPI_SPI2AHB_SLV_SCLKIN 59 257 | #define GPI_SPI3_PAD_RXD 60 258 | #define GPI_SPI3_PAD_SS_IN_N 61 259 | #define GPI_UART0_PAD_CTSN 62 260 | #define GPI_UART0_PAD_DCDN 63 261 | #define GPI_UART0_PAD_DSRN 64 262 | #define GPI_UART0_PAD_RIN 65 263 | #define GPI_UART0_PAD_SIN 66 264 | #define GPI_UART1_PAD_SIN 67 265 | #define GPI_UART2_PAD_CTS_N 68 266 | #define GPI_UART2_PAD_DCD_N 69 267 | #define GPI_UART2_PAD_DSR_N 70 268 | #define GPI_UART2_PAD_RI_N 71 269 | #define GPI_UART2_PAD_SIN 72 270 | #define GPI_UART3_PAD_SIN 73 271 | #define GPI_USB_OVER_CURRENT 74 272 | 273 | #define GPI_NONE 0xff 274 | 275 | #endif /* __DT_BINDINGS_PINCTRL_STARFIVE_JH7100_H__ */ 276 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants 4 | * pinctrl bindings. 5 | * 6 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. 7 | * 8 | * Author: Aapo Vienamo 9 | */ 10 | 11 | #ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H 12 | #define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H 13 | 14 | /* Voltage levels of the I/O pad's source rail */ 15 | #define TEGRA_IO_PAD_VOLTAGE_1V8 0 16 | #define TEGRA_IO_PAD_VOLTAGE_3V3 1 17 | 18 | #endif 19 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/pinctrl-tegra-xusb.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | #ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 3 | #define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 4 | 5 | #define TEGRA_XUSB_PADCTL_PCIE 0 6 | #define TEGRA_XUSB_PADCTL_SATA 1 7 | 8 | #endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ 9 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/pinctrl-tegra.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-only */ 2 | /* 3 | * This header provides constants for Tegra pinctrl bindings. 4 | * 5 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 6 | * 7 | * Author: Laxman Dewangan 8 | */ 9 | 10 | #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H 11 | #define _DT_BINDINGS_PINCTRL_TEGRA_H 12 | 13 | /* 14 | * Enable/disable for diffeent dt properties. This is applicable for 15 | * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, 16 | * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. 17 | */ 18 | #define TEGRA_PIN_DISABLE 0 19 | #define TEGRA_PIN_ENABLE 1 20 | 21 | #define TEGRA_PIN_PULL_NONE 0 22 | #define TEGRA_PIN_PULL_DOWN 1 23 | #define TEGRA_PIN_PULL_UP 2 24 | 25 | /* Low power mode driver */ 26 | #define TEGRA_PIN_LP_DRIVE_DIV_8 0 27 | #define TEGRA_PIN_LP_DRIVE_DIV_4 1 28 | #define TEGRA_PIN_LP_DRIVE_DIV_2 2 29 | #define TEGRA_PIN_LP_DRIVE_DIV_1 3 30 | 31 | /* Rising/Falling slew rate */ 32 | #define TEGRA_PIN_SLEW_RATE_FASTEST 0 33 | #define TEGRA_PIN_SLEW_RATE_FAST 1 34 | #define TEGRA_PIN_SLEW_RATE_SLOW 2 35 | #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/pinctrl-zynq.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx Zynq 4 | * 5 | * Copyright (C) 2021 Xilinx, Inc. 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H 9 | #define _DT_BINDINGS_PINCTRL_ZYNQ_H 10 | 11 | /* Configuration options for different power supplies */ 12 | #define IO_STANDARD_LVCMOS18 1 13 | #define IO_STANDARD_LVCMOS25 2 14 | #define IO_STANDARD_LVCMOS33 3 15 | #define IO_STANDARD_HSTL 4 16 | 17 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */ 18 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/pinctrl-zynqmp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * MIO pin configuration defines for Xilinx ZynqMP 4 | * 5 | * Copyright (C) 2020 Xilinx, Inc. 6 | */ 7 | 8 | #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 9 | #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 | 11 | /* Bit value for different voltage levels */ 12 | #define IO_STANDARD_LVCMOS33 0 13 | #define IO_STANDARD_LVCMOS18 1 14 | 15 | /* Bit values for Slew Rates */ 16 | #define SLEW_RATE_FAST 0 17 | #define SLEW_RATE_SLOW 1 18 | 19 | #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 20 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/qcom,pmic-gpio.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for the Qualcomm PMIC GPIO binding. 4 | */ 5 | 6 | #ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H 7 | #define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H 8 | 9 | #define PMIC_GPIO_PULL_UP_30 0 10 | #define PMIC_GPIO_PULL_UP_1P5 1 11 | #define PMIC_GPIO_PULL_UP_31P5 2 12 | #define PMIC_GPIO_PULL_UP_1P5_30 3 13 | 14 | #define PMIC_GPIO_STRENGTH_NO 0 15 | #define PMIC_GPIO_STRENGTH_HIGH 1 16 | #define PMIC_GPIO_STRENGTH_MED 2 17 | #define PMIC_GPIO_STRENGTH_LOW 3 18 | 19 | /* 20 | * Note: PM8018 GPIO3 and GPIO4 are supporting 21 | * only S3 and L2 options (1.8V) 22 | */ 23 | #define PM8018_GPIO_L6 0 24 | #define PM8018_GPIO_L5 1 25 | #define PM8018_GPIO_S3 2 26 | #define PM8018_GPIO_L14 3 27 | #define PM8018_GPIO_L2 4 28 | #define PM8018_GPIO_L4 5 29 | #define PM8018_GPIO_VDD 6 30 | 31 | /* 32 | * Note: PM8038 GPIO7 and GPIO8 are supporting 33 | * only L11 and L4 options (1.8V) 34 | */ 35 | #define PM8038_GPIO_VPH 0 36 | #define PM8038_GPIO_BB 1 37 | #define PM8038_GPIO_L11 2 38 | #define PM8038_GPIO_L15 3 39 | #define PM8038_GPIO_L4 4 40 | #define PM8038_GPIO_L3 5 41 | #define PM8038_GPIO_L17 6 42 | 43 | #define PM8058_GPIO_VPH 0 44 | #define PM8058_GPIO_BB 1 45 | #define PM8058_GPIO_S3 2 46 | #define PM8058_GPIO_L3 3 47 | #define PM8058_GPIO_L7 4 48 | #define PM8058_GPIO_L6 5 49 | #define PM8058_GPIO_L5 6 50 | #define PM8058_GPIO_L2 7 51 | 52 | /* 53 | * Note: PM8916 GPIO1 and GPIO2 are supporting 54 | * only L2(1.15V) and L5(1.8V) options 55 | */ 56 | #define PM8916_GPIO_VPH 0 57 | #define PM8916_GPIO_L2 2 58 | #define PM8916_GPIO_L5 3 59 | 60 | #define PM8917_GPIO_VPH 0 61 | #define PM8917_GPIO_S4 2 62 | #define PM8917_GPIO_L15 3 63 | #define PM8917_GPIO_L4 4 64 | #define PM8917_GPIO_L3 5 65 | #define PM8917_GPIO_L17 6 66 | 67 | #define PM8921_GPIO_VPH 0 68 | #define PM8921_GPIO_BB 1 69 | #define PM8921_GPIO_S4 2 70 | #define PM8921_GPIO_L15 3 71 | #define PM8921_GPIO_L4 4 72 | #define PM8921_GPIO_L3 5 73 | #define PM8921_GPIO_L17 6 74 | 75 | /* 76 | * Note: PM8941 gpios from 15 to 18 are supporting 77 | * only S3 and L6 options (1.8V) 78 | */ 79 | #define PM8941_GPIO_VPH 0 80 | #define PM8941_GPIO_L1 1 81 | #define PM8941_GPIO_S3 2 82 | #define PM8941_GPIO_L6 3 83 | 84 | /* 85 | * Note: PMA8084 gpios from 15 to 18 are supporting 86 | * only S4 and L6 options (1.8V) 87 | */ 88 | #define PMA8084_GPIO_VPH 0 89 | #define PMA8084_GPIO_L1 1 90 | #define PMA8084_GPIO_S4 2 91 | #define PMA8084_GPIO_L6 3 92 | 93 | #define PM8994_GPIO_VPH 0 94 | #define PM8994_GPIO_S4 2 95 | #define PM8994_GPIO_L12 3 96 | 97 | /* To be used with "function" */ 98 | #define PMIC_GPIO_FUNC_NORMAL "normal" 99 | #define PMIC_GPIO_FUNC_PAIRED "paired" 100 | #define PMIC_GPIO_FUNC_FUNC1 "func1" 101 | #define PMIC_GPIO_FUNC_FUNC2 "func2" 102 | #define PMIC_GPIO_FUNC_FUNC3 "func3" 103 | #define PMIC_GPIO_FUNC_FUNC4 "func4" 104 | #define PMIC_GPIO_FUNC_DTEST1 "dtest1" 105 | #define PMIC_GPIO_FUNC_DTEST2 "dtest2" 106 | #define PMIC_GPIO_FUNC_DTEST3 "dtest3" 107 | #define PMIC_GPIO_FUNC_DTEST4 "dtest4" 108 | 109 | #define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 110 | #define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 111 | #define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 112 | #define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 113 | #define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 114 | #define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 115 | #define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 116 | #define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 117 | 118 | #define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 119 | #define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 120 | #define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 121 | #define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 122 | #define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 123 | #define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 124 | #define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 125 | #define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 126 | #define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 127 | #define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 128 | #define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 129 | #define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 130 | #define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 131 | #define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 132 | 133 | #define PM8916_GPIO1_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 134 | #define PM8916_GPIO1_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 135 | #define PM8916_GPIO2_DIV_CLK PMIC_GPIO_FUNC_FUNC1 136 | #define PM8916_GPIO2_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 137 | #define PM8916_GPIO3_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 138 | #define PM8916_GPIO4_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 139 | 140 | #define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 141 | #define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 142 | #define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 143 | #define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 144 | #define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 145 | #define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 146 | 147 | #define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 148 | #define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 149 | #define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 150 | #define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 151 | #define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 152 | #define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 153 | #define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 154 | #define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 155 | 156 | #define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 157 | #define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 158 | #define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 159 | #define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 160 | #define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 161 | #define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 162 | #define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 163 | 164 | #endif 165 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/qcom,pmic-mpp.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * This header provides constants for the Qualcomm PMIC's 4 | * Multi-Purpose Pin binding. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H 8 | #define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H 9 | 10 | /* power-source */ 11 | 12 | /* Digital Input/Output: level [PM8058] */ 13 | #define PM8058_MPP_VPH 0 14 | #define PM8058_MPP_S3 1 15 | #define PM8058_MPP_L2 2 16 | #define PM8058_MPP_L3 3 17 | 18 | /* Digital Input/Output: level [PM8901] */ 19 | #define PM8901_MPP_MSMIO 0 20 | #define PM8901_MPP_DIG 1 21 | #define PM8901_MPP_L5 2 22 | #define PM8901_MPP_S4 3 23 | #define PM8901_MPP_VPH 4 24 | 25 | /* Digital Input/Output: level [PM8921] */ 26 | #define PM8921_MPP_S4 1 27 | #define PM8921_MPP_L15 3 28 | #define PM8921_MPP_L17 4 29 | #define PM8921_MPP_VPH 7 30 | 31 | /* Digital Input/Output: level [PM8821] */ 32 | #define PM8821_MPP_1P8 0 33 | #define PM8821_MPP_VPH 7 34 | 35 | /* Digital Input/Output: level [PM8018] */ 36 | #define PM8018_MPP_L4 0 37 | #define PM8018_MPP_L14 1 38 | #define PM8018_MPP_S3 2 39 | #define PM8018_MPP_L6 3 40 | #define PM8018_MPP_L2 4 41 | #define PM8018_MPP_L5 5 42 | #define PM8018_MPP_VPH 7 43 | 44 | /* Digital Input/Output: level [PM8038] */ 45 | #define PM8038_MPP_L20 0 46 | #define PM8038_MPP_L11 1 47 | #define PM8038_MPP_L5 2 48 | #define PM8038_MPP_L15 3 49 | #define PM8038_MPP_L17 4 50 | #define PM8038_MPP_VPH 7 51 | 52 | #define PM8841_MPP_VPH 0 53 | #define PM8841_MPP_S3 2 54 | 55 | #define PM8916_MPP_VPH 0 56 | #define PM8916_MPP_L2 2 57 | #define PM8916_MPP_L5 3 58 | 59 | #define PM8941_MPP_VPH 0 60 | #define PM8941_MPP_L1 1 61 | #define PM8941_MPP_S3 2 62 | #define PM8941_MPP_L6 3 63 | 64 | #define PMA8084_MPP_VPH 0 65 | #define PMA8084_MPP_L1 1 66 | #define PMA8084_MPP_S4 2 67 | #define PMA8084_MPP_L6 3 68 | 69 | #define PM8994_MPP_VPH 0 70 | /* Only supported for MPP_05-MPP_08 */ 71 | #define PM8994_MPP_L19 1 72 | #define PM8994_MPP_S4 2 73 | #define PM8994_MPP_L12 3 74 | 75 | /* 76 | * Analog Input - Set the source for analog input. 77 | * To be used with "qcom,amux-route" property 78 | */ 79 | #define PMIC_MPP_AMUX_ROUTE_CH5 0 80 | #define PMIC_MPP_AMUX_ROUTE_CH6 1 81 | #define PMIC_MPP_AMUX_ROUTE_CH7 2 82 | #define PMIC_MPP_AMUX_ROUTE_CH8 3 83 | #define PMIC_MPP_AMUX_ROUTE_ABUS1 4 84 | #define PMIC_MPP_AMUX_ROUTE_ABUS2 5 85 | #define PMIC_MPP_AMUX_ROUTE_ABUS3 6 86 | #define PMIC_MPP_AMUX_ROUTE_ABUS4 7 87 | 88 | /* Analog Output: level */ 89 | #define PMIC_MPP_AOUT_LVL_1V25 0 90 | #define PMIC_MPP_AOUT_LVL_1V25_2 1 91 | #define PMIC_MPP_AOUT_LVL_0V625 2 92 | #define PMIC_MPP_AOUT_LVL_0V3125 3 93 | #define PMIC_MPP_AOUT_LVL_MPP 4 94 | #define PMIC_MPP_AOUT_LVL_ABUS1 5 95 | #define PMIC_MPP_AOUT_LVL_ABUS2 6 96 | #define PMIC_MPP_AOUT_LVL_ABUS3 7 97 | 98 | /* To be used with "function" */ 99 | #define PMIC_MPP_FUNC_NORMAL "normal" 100 | #define PMIC_MPP_FUNC_PAIRED "paired" 101 | #define PMIC_MPP_FUNC_DTEST1 "dtest1" 102 | #define PMIC_MPP_FUNC_DTEST2 "dtest2" 103 | #define PMIC_MPP_FUNC_DTEST3 "dtest3" 104 | #define PMIC_MPP_FUNC_DTEST4 "dtest4" 105 | 106 | #endif 107 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/r7s72100-pinctrl.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Defines macros and constants for Renesas RZ/A1 pin controller pin 4 | * muxing functions. 5 | */ 6 | #ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H 7 | #define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H 8 | 9 | #define RZA1_PINS_PER_PORT 16 10 | 11 | /* 12 | * Create the pin index from its bank and position numbers and store in 13 | * the upper 16 bits the alternate function identifier 14 | */ 15 | #define RZA1_PINMUX(b, p, f) ((b) * RZA1_PINS_PER_PORT + (p) | (f << 16)) 16 | 17 | #endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */ 18 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/r7s9210-pinctrl.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Defines macros and constants for Renesas RZ/A2 pin controller pin 4 | * muxing functions. 5 | */ 6 | #ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H 7 | #define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H 8 | 9 | #define RZA2_PINS_PER_PORT 8 10 | 11 | /* Port names as labeled in the Hardware Manual */ 12 | #define PORT0 0 13 | #define PORT1 1 14 | #define PORT2 2 15 | #define PORT3 3 16 | #define PORT4 4 17 | #define PORT5 5 18 | #define PORT6 6 19 | #define PORT7 7 20 | #define PORT8 8 21 | #define PORT9 9 22 | #define PORTA 10 23 | #define PORTB 11 24 | #define PORTC 12 25 | #define PORTD 13 26 | #define PORTE 14 27 | #define PORTF 15 28 | #define PORTG 16 29 | #define PORTH 17 30 | /* No I */ 31 | #define PORTJ 18 32 | #define PORTK 19 33 | #define PORTL 20 34 | #define PORTM 21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */ 35 | 36 | /* 37 | * Create the pin index from its bank and position numbers and store in 38 | * the upper 16 bits the alternate function identifier 39 | */ 40 | #define RZA2_PINMUX(b, p, f) ((b) * RZA2_PINS_PER_PORT + (p) | (f << 16)) 41 | 42 | /* 43 | * Convert a port and pin label to its global pin index 44 | */ 45 | #define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) 46 | 47 | #endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */ 48 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/rockchip.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 | /* 3 | * Header providing constants for Rockchip pinctrl bindings. 4 | * 5 | * Copyright (c) 2013 MundoReader S.L. 6 | * Author: Heiko Stuebner 7 | */ 8 | 9 | #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ 10 | #define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ 11 | 12 | #define RK_PA0 0 13 | #define RK_PA1 1 14 | #define RK_PA2 2 15 | #define RK_PA3 3 16 | #define RK_PA4 4 17 | #define RK_PA5 5 18 | #define RK_PA6 6 19 | #define RK_PA7 7 20 | #define RK_PB0 8 21 | #define RK_PB1 9 22 | #define RK_PB2 10 23 | #define RK_PB3 11 24 | #define RK_PB4 12 25 | #define RK_PB5 13 26 | #define RK_PB6 14 27 | #define RK_PB7 15 28 | #define RK_PC0 16 29 | #define RK_PC1 17 30 | #define RK_PC2 18 31 | #define RK_PC3 19 32 | #define RK_PC4 20 33 | #define RK_PC5 21 34 | #define RK_PC6 22 35 | #define RK_PC7 23 36 | #define RK_PD0 24 37 | #define RK_PD1 25 38 | #define RK_PD2 26 39 | #define RK_PD3 27 40 | #define RK_PD4 28 41 | #define RK_PD5 29 42 | #define RK_PD6 30 43 | #define RK_PD7 31 44 | 45 | #define RK_FUNC_GPIO 0 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/rzg2l-pinctrl.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 | /* 3 | * This header provides constants for Renesas RZ/G2L family pinctrl bindings. 4 | * 5 | * Copyright (C) 2021 Renesas Electronics Corp. 6 | * 7 | */ 8 | 9 | #ifndef __DT_BINDINGS_RZG2L_PINCTRL_H 10 | #define __DT_BINDINGS_RZG2L_PINCTRL_H 11 | 12 | #define RZG2L_PINS_PER_PORT 8 13 | 14 | /* 15 | * Create the pin index from its bank and position numbers and store in 16 | * the upper 16 bits the alternate function identifier 17 | */ 18 | #define RZG2L_PORT_PINMUX(b, p, f) ((b) * RZG2L_PINS_PER_PORT + (p) | ((f) << 16)) 19 | 20 | /* Convert a port and pin label to its global pin index */ 21 | #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin)) 22 | 23 | #endif /* __DT_BINDINGS_RZG2L_PINCTRL_H */ 24 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/rzn1-pinctrl.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Defines macros and constants for Renesas RZ/N1 pin controller pin 4 | * muxing functions. 5 | */ 6 | #ifndef __DT_BINDINGS_RZN1_PINCTRL_H 7 | #define __DT_BINDINGS_RZN1_PINCTRL_H 8 | 9 | #define RZN1_PINMUX(_gpio, _func) \ 10 | (((_func) << 8) | (_gpio)) 11 | 12 | /* 13 | * Given the different levels of muxing on the SoC, it was decided to 14 | * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO 15 | * muxes are all represented by one single value. 16 | * 17 | * You can derive the hardware value pretty easily too, as 18 | * 0...9 are Level 1 19 | * 10...71 are Level 2. The Level 2 mux will be set to this 20 | * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be 21 | * set accordingly. 22 | * 72...103 are for the 2 MDIO muxes. 23 | */ 24 | #define RZN1_FUNC_HIGHZ 0 25 | #define RZN1_FUNC_0L 1 26 | #define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 27 | #define RZN1_FUNC_CLK_ETH_NAND 3 28 | #define RZN1_FUNC_QSPI 4 29 | #define RZN1_FUNC_SDIO 5 30 | #define RZN1_FUNC_LCD 6 31 | #define RZN1_FUNC_LCD_E 7 32 | #define RZN1_FUNC_MSEBIM 8 33 | #define RZN1_FUNC_MSEBIS 9 34 | #define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ 35 | 36 | #define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) 37 | #define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) 38 | #define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) 39 | #define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) 40 | #define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) 41 | #define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) 42 | #define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) 43 | #define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) 44 | #define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) 45 | #define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) 46 | #define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) 47 | #define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) 48 | #define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) 49 | #define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) 50 | #define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) 51 | #define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) 52 | #define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) 53 | #define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) 54 | #define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) 55 | #define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) 56 | #define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) 57 | #define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) 58 | #define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) 59 | #define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) 60 | #define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) 61 | #define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) 62 | #define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) 63 | #define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) 64 | #define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) 65 | #define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) 66 | #define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) 67 | #define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) 68 | #define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) 69 | #define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) 70 | #define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) 71 | #define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) 72 | #define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) 73 | #define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) 74 | #define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) 75 | #define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) 76 | #define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) 77 | #define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) 78 | #define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) 79 | #define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) 80 | #define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) 81 | #define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) 82 | #define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) 83 | #define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) 84 | #define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) 85 | #define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) 86 | #define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) 87 | #define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) 88 | #define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) 89 | #define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) 90 | #define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) 91 | #define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) 92 | #define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) 93 | #define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) 94 | #define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) 95 | #define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) 96 | #define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) 97 | #define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) 98 | 99 | #define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) 100 | 101 | /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ 102 | #define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) 103 | #define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) 104 | #define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) 105 | #define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) 106 | #define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) 107 | #define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) 108 | #define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) 109 | #define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) 110 | /* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 111 | #define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) 112 | #define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) 113 | #define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) 114 | #define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) 115 | #define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) 116 | #define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) 117 | #define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) 118 | #define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) 119 | 120 | /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ 121 | #define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) 122 | #define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) 123 | #define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) 124 | #define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) 125 | #define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) 126 | #define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) 127 | #define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) 128 | #define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) 129 | /* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ 130 | #define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) 131 | #define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) 132 | #define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) 133 | #define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) 134 | #define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) 135 | #define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) 136 | #define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) 137 | #define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) 138 | 139 | #define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) 140 | 141 | #endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ 142 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/rzv2m-pinctrl.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 | /* 3 | * This header provides constants for Renesas RZ/V2M pinctrl bindings. 4 | * 5 | * Copyright (C) 2022 Renesas Electronics Corp. 6 | * 7 | */ 8 | 9 | #ifndef __DT_BINDINGS_RZV2M_PINCTRL_H 10 | #define __DT_BINDINGS_RZV2M_PINCTRL_H 11 | 12 | #define RZV2M_PINS_PER_PORT 16 13 | 14 | /* 15 | * Create the pin index from its bank and position numbers and store in 16 | * the upper 16 bits the alternate function identifier 17 | */ 18 | #define RZV2M_PORT_PINMUX(b, p, f) ((b) * RZV2M_PINS_PER_PORT + (p) | ((f) << 16)) 19 | 20 | /* Convert a port and pin label to its global pin index */ 21 | #define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin)) 22 | 23 | #endif /* __DT_BINDINGS_RZV2M_PINCTRL_H */ 24 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/samsung.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: GPL-2.0 */ 2 | /* 3 | * Samsung's Exynos pinctrl bindings 4 | * 5 | * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6 | * http://www.samsung.com 7 | * Author: Krzysztof Kozlowski 8 | */ 9 | 10 | #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 11 | #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ 12 | 13 | /* 14 | * These bindings are deprecated, because they do not match the actual 15 | * concept of bindings but rather contain pure register values. 16 | * Instead include the header in the DTS source directory. 17 | */ 18 | #warning "These bindings are deprecated. Instead use the header in the DTS source directory." 19 | 20 | #define EXYNOS_PIN_PULL_NONE 0 21 | #define EXYNOS_PIN_PULL_DOWN 1 22 | #define EXYNOS_PIN_PULL_UP 3 23 | 24 | #define S3C64XX_PIN_PULL_NONE 0 25 | #define S3C64XX_PIN_PULL_DOWN 1 26 | #define S3C64XX_PIN_PULL_UP 2 27 | 28 | /* Pin function in power down mode */ 29 | #define EXYNOS_PIN_PDN_OUT0 0 30 | #define EXYNOS_PIN_PDN_OUT1 1 31 | #define EXYNOS_PIN_PDN_INPUT 2 32 | #define EXYNOS_PIN_PDN_PREV 3 33 | 34 | /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ 35 | #define EXYNOS4_PIN_DRV_LV1 0 36 | #define EXYNOS4_PIN_DRV_LV2 2 37 | #define EXYNOS4_PIN_DRV_LV3 1 38 | #define EXYNOS4_PIN_DRV_LV4 3 39 | 40 | /* Drive strengths for Exynos5260 */ 41 | #define EXYNOS5260_PIN_DRV_LV1 0 42 | #define EXYNOS5260_PIN_DRV_LV2 1 43 | #define EXYNOS5260_PIN_DRV_LV4 2 44 | #define EXYNOS5260_PIN_DRV_LV6 3 45 | 46 | /* 47 | * Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except 48 | * GPIO_HSI block) 49 | */ 50 | #define EXYNOS5420_PIN_DRV_LV1 0 51 | #define EXYNOS5420_PIN_DRV_LV2 1 52 | #define EXYNOS5420_PIN_DRV_LV3 2 53 | #define EXYNOS5420_PIN_DRV_LV4 3 54 | 55 | /* Drive strengths for Exynos5433 */ 56 | #define EXYNOS5433_PIN_DRV_FAST_SR1 0 57 | #define EXYNOS5433_PIN_DRV_FAST_SR2 1 58 | #define EXYNOS5433_PIN_DRV_FAST_SR3 2 59 | #define EXYNOS5433_PIN_DRV_FAST_SR4 3 60 | #define EXYNOS5433_PIN_DRV_FAST_SR5 4 61 | #define EXYNOS5433_PIN_DRV_FAST_SR6 5 62 | #define EXYNOS5433_PIN_DRV_SLOW_SR1 8 63 | #define EXYNOS5433_PIN_DRV_SLOW_SR2 9 64 | #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa 65 | #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb 66 | #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc 67 | #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf 68 | 69 | /* Drive strengths for Exynos850 GPIO_HSI block */ 70 | #define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ 71 | #define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ 72 | #define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ 73 | #define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ 74 | #define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ 75 | #define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ 76 | 77 | #define EXYNOS_PIN_FUNC_INPUT 0 78 | #define EXYNOS_PIN_FUNC_OUTPUT 1 79 | #define EXYNOS_PIN_FUNC_2 2 80 | #define EXYNOS_PIN_FUNC_3 3 81 | #define EXYNOS_PIN_FUNC_4 4 82 | #define EXYNOS_PIN_FUNC_5 5 83 | #define EXYNOS_PIN_FUNC_6 6 84 | #define EXYNOS_PIN_FUNC_EINT 0xf 85 | #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 86 | 87 | /* Drive strengths for Exynos7 FSYS1 block */ 88 | #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 89 | #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 90 | #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 91 | #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 92 | #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 93 | #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 94 | 95 | #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ 96 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/sppctl-sp7021.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 | /* 3 | * Sunplus SP7021 dt-bindings Pinctrl header file 4 | * Copyright (C) Sunplus Tech/Tibbo Tech. 5 | * Author: Dvorkin Dmitry 6 | */ 7 | 8 | #ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ 9 | #define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ 10 | 11 | #include 12 | 13 | /* 14 | * Please don't change the order of the following defines. 15 | * They are based on order of 'hardware' control register 16 | * defined in MOON2 ~ MOON3 registers. 17 | */ 18 | #define MUXF_GPIO 0 19 | #define MUXF_IOP 1 20 | #define MUXF_L2SW_CLK_OUT 2 21 | #define MUXF_L2SW_MAC_SMI_MDC 3 22 | #define MUXF_L2SW_LED_FLASH0 4 23 | #define MUXF_L2SW_LED_FLASH1 5 24 | #define MUXF_L2SW_LED_ON0 6 25 | #define MUXF_L2SW_LED_ON1 7 26 | #define MUXF_L2SW_MAC_SMI_MDIO 8 27 | #define MUXF_L2SW_P0_MAC_RMII_TXEN 9 28 | #define MUXF_L2SW_P0_MAC_RMII_TXD0 10 29 | #define MUXF_L2SW_P0_MAC_RMII_TXD1 11 30 | #define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 31 | #define MUXF_L2SW_P0_MAC_RMII_RXD0 13 32 | #define MUXF_L2SW_P0_MAC_RMII_RXD1 14 33 | #define MUXF_L2SW_P0_MAC_RMII_RXER 15 34 | #define MUXF_L2SW_P1_MAC_RMII_TXEN 16 35 | #define MUXF_L2SW_P1_MAC_RMII_TXD0 17 36 | #define MUXF_L2SW_P1_MAC_RMII_TXD1 18 37 | #define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 38 | #define MUXF_L2SW_P1_MAC_RMII_RXD0 20 39 | #define MUXF_L2SW_P1_MAC_RMII_RXD1 21 40 | #define MUXF_L2SW_P1_MAC_RMII_RXER 22 41 | #define MUXF_DAISY_MODE 23 42 | #define MUXF_SDIO_CLK 24 43 | #define MUXF_SDIO_CMD 25 44 | #define MUXF_SDIO_D0 26 45 | #define MUXF_SDIO_D1 27 46 | #define MUXF_SDIO_D2 28 47 | #define MUXF_SDIO_D3 29 48 | #define MUXF_PWM0 30 49 | #define MUXF_PWM1 31 50 | #define MUXF_PWM2 32 51 | #define MUXF_PWM3 33 52 | #define MUXF_PWM4 34 53 | #define MUXF_PWM5 35 54 | #define MUXF_PWM6 36 55 | #define MUXF_PWM7 37 56 | #define MUXF_ICM0_D 38 57 | #define MUXF_ICM1_D 39 58 | #define MUXF_ICM2_D 40 59 | #define MUXF_ICM3_D 41 60 | #define MUXF_ICM0_CLK 42 61 | #define MUXF_ICM1_CLK 43 62 | #define MUXF_ICM2_CLK 44 63 | #define MUXF_ICM3_CLK 45 64 | #define MUXF_SPIM0_INT 46 65 | #define MUXF_SPIM0_CLK 47 66 | #define MUXF_SPIM0_EN 48 67 | #define MUXF_SPIM0_DO 49 68 | #define MUXF_SPIM0_DI 50 69 | #define MUXF_SPIM1_INT 51 70 | #define MUXF_SPIM1_CLK 52 71 | #define MUXF_SPIM1_EN 53 72 | #define MUXF_SPIM1_DO 54 73 | #define MUXF_SPIM1_DI 55 74 | #define MUXF_SPIM2_INT 56 75 | #define MUXF_SPIM2_CLK 57 76 | #define MUXF_SPIM2_EN 58 77 | #define MUXF_SPIM2_DO 59 78 | #define MUXF_SPIM2_DI 60 79 | #define MUXF_SPIM3_INT 61 80 | #define MUXF_SPIM3_CLK 62 81 | #define MUXF_SPIM3_EN 63 82 | #define MUXF_SPIM3_DO 64 83 | #define MUXF_SPIM3_DI 65 84 | #define MUXF_SPI0S_INT 66 85 | #define MUXF_SPI0S_CLK 67 86 | #define MUXF_SPI0S_EN 68 87 | #define MUXF_SPI0S_DO 69 88 | #define MUXF_SPI0S_DI 70 89 | #define MUXF_SPI1S_INT 71 90 | #define MUXF_SPI1S_CLK 72 91 | #define MUXF_SPI1S_EN 73 92 | #define MUXF_SPI1S_DO 74 93 | #define MUXF_SPI1S_DI 75 94 | #define MUXF_SPI2S_INT 76 95 | #define MUXF_SPI2S_CLK 77 96 | #define MUXF_SPI2S_EN 78 97 | #define MUXF_SPI2S_DO 79 98 | #define MUXF_SPI2S_DI 80 99 | #define MUXF_SPI3S_INT 81 100 | #define MUXF_SPI3S_CLK 82 101 | #define MUXF_SPI3S_EN 83 102 | #define MUXF_SPI3S_DO 84 103 | #define MUXF_SPI3S_DI 85 104 | #define MUXF_I2CM0_CLK 86 105 | #define MUXF_I2CM0_DAT 87 106 | #define MUXF_I2CM1_CLK 88 107 | #define MUXF_I2CM1_DAT 89 108 | #define MUXF_I2CM2_CLK 90 109 | #define MUXF_I2CM2_DAT 91 110 | #define MUXF_I2CM3_CLK 92 111 | #define MUXF_I2CM3_DAT 93 112 | #define MUXF_UA1_TX 94 113 | #define MUXF_UA1_RX 95 114 | #define MUXF_UA1_CTS 96 115 | #define MUXF_UA1_RTS 97 116 | #define MUXF_UA2_TX 98 117 | #define MUXF_UA2_RX 99 118 | #define MUXF_UA2_CTS 100 119 | #define MUXF_UA2_RTS 101 120 | #define MUXF_UA3_TX 102 121 | #define MUXF_UA3_RX 103 122 | #define MUXF_UA3_CTS 104 123 | #define MUXF_UA3_RTS 105 124 | #define MUXF_UA4_TX 106 125 | #define MUXF_UA4_RX 107 126 | #define MUXF_UA4_CTS 108 127 | #define MUXF_UA4_RTS 109 128 | #define MUXF_TIMER0_INT 110 129 | #define MUXF_TIMER1_INT 111 130 | #define MUXF_TIMER2_INT 112 131 | #define MUXF_TIMER3_INT 113 132 | #define MUXF_GPIO_INT0 114 133 | #define MUXF_GPIO_INT1 115 134 | #define MUXF_GPIO_INT2 116 135 | #define MUXF_GPIO_INT3 117 136 | #define MUXF_GPIO_INT4 118 137 | #define MUXF_GPIO_INT5 119 138 | #define MUXF_GPIO_INT6 120 139 | #define MUXF_GPIO_INT7 121 140 | 141 | /* 142 | * Please don't change the order of the following defines. 143 | * They are based on order of items in array 'sppctl_list_funcs' 144 | * in Sunplus pinctrl driver. 145 | */ 146 | #define GROP_SPI_FLASH 122 147 | #define GROP_SPI_FLASH_4BIT 123 148 | #define GROP_SPI_NAND 124 149 | #define GROP_CARD0_EMMC 125 150 | #define GROP_SD_CARD 126 151 | #define GROP_UA0 127 152 | #define GROP_ACHIP_DEBUG 128 153 | #define GROP_ACHIP_UA2AXI 129 154 | #define GROP_FPGA_IFX 130 155 | #define GROP_HDMI_TX 131 156 | #define GROP_AUD_EXT_ADC_IFX0 132 157 | #define GROP_AUD_EXT_DAC_IFX0 133 158 | #define GROP_SPDIF_RX 134 159 | #define GROP_SPDIF_TX 135 160 | #define GROP_TDMTX_IFX0 136 161 | #define GROP_TDMRX_IFX0 137 162 | #define GROP_PDMRX_IFX0 138 163 | #define GROP_PCM_IEC_TX 139 164 | #define GROP_LCDIF 140 165 | #define GROP_DVD_DSP_DEBUG 141 166 | #define GROP_I2C_DEBUG 142 167 | #define GROP_I2C_SLAVE 143 168 | #define GROP_WAKEUP 144 169 | #define GROP_UART2AXI 145 170 | #define GROP_USB0_I2C 146 171 | #define GROP_USB1_I2C 147 172 | #define GROP_USB0_OTG 148 173 | #define GROP_USB1_OTG 149 174 | #define GROP_UPHY0_DEBUG 150 175 | #define GROP_UPHY1_DEBUG 151 176 | #define GROP_UPHY0_EXT 152 177 | #define GROP_PROBE_PORT 153 178 | 179 | #endif 180 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/sppctl.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 | /* 3 | * Sunplus dt-bindings Pinctrl header file 4 | * Copyright (C) Sunplus Tech / Tibbo Tech. 5 | * Author: Dvorkin Dmitry 6 | */ 7 | 8 | #ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__ 9 | #define __DT_BINDINGS_PINCTRL_SPPCTL_H__ 10 | 11 | #define IOP_G_MASTE (0x01 << 0) 12 | #define IOP_G_FIRST (0x01 << 1) 13 | 14 | #define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE) 15 | #define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE) 16 | #define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00) 17 | 18 | #define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */ 19 | #define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */ 20 | #define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */ 21 | #define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */ 22 | #define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */ 23 | 24 | /* 25 | * pack into 32-bit value: 26 | * pin# (8bit), typ (8bit), function (8bit), flag (8bit) 27 | */ 28 | #define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \ 29 | ((fun) << 8) | (flg)) 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/stm32-pinfunc.h: -------------------------------------------------------------------------------- 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 | /* 3 | * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 | * Author: Torgue Alexandre for STMicroelectronics. 5 | */ 6 | 7 | #ifndef _DT_BINDINGS_STM32_PINFUNC_H 8 | #define _DT_BINDINGS_STM32_PINFUNC_H 9 | 10 | /* define PIN modes */ 11 | #define GPIO 0x0 12 | #define AF0 0x1 13 | #define AF1 0x2 14 | #define AF2 0x3 15 | #define AF3 0x4 16 | #define AF4 0x5 17 | #define AF5 0x6 18 | #define AF6 0x7 19 | #define AF7 0x8 20 | #define AF8 0x9 21 | #define AF9 0xa 22 | #define AF10 0xb 23 | #define AF11 0xc 24 | #define AF12 0xd 25 | #define AF13 0xe 26 | #define AF14 0xf 27 | #define AF15 0x10 28 | #define ANALOG 0x11 29 | 30 | /* define Pins number*/ 31 | #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) 32 | 33 | #define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) 34 | 35 | /* package information */ 36 | #define STM32MP_PKG_AA 0x1 37 | #define STM32MP_PKG_AB 0x2 38 | #define STM32MP_PKG_AC 0x4 39 | #define STM32MP_PKG_AD 0x8 40 | 41 | #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ 42 | 43 | -------------------------------------------------------------------------------- /devicetree_overlays/dt-bindings/pinctrl/sun4i-a10.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright 2014 Maxime Ripard 3 | * 4 | * Maxime Ripard 5 | * 6 | * This file is dual-licensed: you can use it either under the terms 7 | * of the GPL or the X11 license, at your option. Note that this dual 8 | * licensing only applies to this file, and not this project as a 9 | * whole. 10 | * 11 | * a) This file is free software; you can redistribute it and/or 12 | * modify it under the terms of the GNU General Public License as 13 | * published by the Free Software Foundation; either version 2 of the 14 | * License, or (at your option) any later version. 15 | * 16 | * This file is distributed in the hope that it will be useful, 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | * GNU General Public License for more details. 20 | * 21 | * You should have received a copy of the GNU General Public 22 | * License along with this file; if not, write to the Free 23 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24 | * MA 02110-1301 USA 25 | * 26 | * Or, alternatively, 27 | * 28 | * b) Permission is hereby granted, free of charge, to any person 29 | * obtaining a copy of this software and associated documentation 30 | * files (the "Software"), to deal in the Software without 31 | * restriction, including without limitation the rights to use, 32 | * copy, modify, merge, publish, distribute, sublicense, and/or 33 | * sell copies of the Software, and to permit persons to whom the 34 | * Software is furnished to do so, subject to the following 35 | * conditions: 36 | * 37 | * The above copyright notice and this permission notice shall be 38 | * included in all copies or substantial portions of the Software. 39 | * 40 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 | * OTHER DEALINGS IN THE SOFTWARE. 48 | */ 49 | 50 | #ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ 51 | #define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ 52 | 53 | #define SUN4I_PINCTRL_10_MA 0 54 | #define SUN4I_PINCTRL_20_MA 1 55 | #define SUN4I_PINCTRL_30_MA 2 56 | #define SUN4I_PINCTRL_40_MA 3 57 | 58 | #define SUN4I_PINCTRL_NO_PULL 0 59 | #define SUN4I_PINCTRL_PULL_UP 1 60 | #define SUN4I_PINCTRL_PULL_DOWN 2 61 | 62 | #endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */ 63 | -------------------------------------------------------------------------------- /kernel/linux-headers-6.1.43-105-rockchip_6.1.43-105-rockchip_arm64.deb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dev-null2019/radxa-cm5-uconsole/c2204834e1d7d0acfd64e1b7874d432bc142f1a4/kernel/linux-headers-6.1.43-105-rockchip_6.1.43-105-rockchip_arm64.deb -------------------------------------------------------------------------------- /kernel/linux-image-6.1.43-105-rockchip_6.1.43-105-rockchip_arm64.deb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dev-null2019/radxa-cm5-uconsole/c2204834e1d7d0acfd64e1b7874d432bc142f1a4/kernel/linux-image-6.1.43-105-rockchip_6.1.43-105-rockchip_arm64.deb --------------------------------------------------------------------------------