├── .github └── workflows │ └── rust.yml ├── .gitignore ├── Cargo.lock ├── Cargo.toml ├── LICENSE ├── README.md ├── do-core ├── Cargo.toml └── src │ ├── core.rs │ ├── instruction.rs │ ├── lib.rs │ └── memory.rs └── src └── main.rs /.github/workflows/rust.yml: -------------------------------------------------------------------------------- 1 | name: Rust 2 | 3 | on: 4 | push: 5 | branches: [ "main" ] 6 | pull_request: 7 | branches: [ "main" ] 8 | 9 | env: 10 | CARGO_TERM_COLOR: always 11 | 12 | jobs: 13 | build: 14 | 15 | runs-on: ubuntu-latest 16 | 17 | steps: 18 | - uses: actions/checkout@v3 19 | - name: Build 20 | run: cargo build --verbose 21 | - name: Run tests 22 | run: cargo test --verbose 23 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Generated by Cargo 2 | # will have compiled files and executables 3 | debug/ 4 | target/ 5 | 6 | -------------------------------------------------------------------------------- /Cargo.lock: -------------------------------------------------------------------------------- 1 | # This file is automatically @generated by Cargo. 2 | # It is not intended for manual editing. 3 | version = 3 4 | 5 | [[package]] 6 | name = "atty" 7 | version = "0.2.14" 8 | source = "registry+https://github.com/rust-lang/crates.io-index" 9 | checksum = "d9b39be18770d11421cdb1b9947a45dd3f37e93092cbf377614828a319d5fee8" 10 | dependencies = [ 11 | "hermit-abi", 12 | "libc", 13 | "winapi", 14 | ] 15 | 16 | [[package]] 17 | name = "autocfg" 18 | version = "1.0.1" 19 | source = "registry+https://github.com/rust-lang/crates.io-index" 20 | checksum = "cdb031dd78e28731d87d56cc8ffef4a8f36ca26c38fe2de700543e627f8a464a" 21 | 22 | [[package]] 23 | name = "bitflags" 24 | version = "1.3.2" 25 | source = "registry+https://github.com/rust-lang/crates.io-index" 26 | checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" 27 | 28 | [[package]] 29 | name = "clap" 30 | version = "3.0.14" 31 | source = "registry+https://github.com/rust-lang/crates.io-index" 32 | checksum = "b63edc3f163b3c71ec8aa23f9bd6070f77edbf3d1d198b164afa90ff00e4ec62" 33 | dependencies = [ 34 | "atty", 35 | "bitflags", 36 | "clap_derive", 37 | "indexmap", 38 | "lazy_static", 39 | "os_str_bytes", 40 | "strsim", 41 | "termcolor", 42 | "textwrap", 43 | ] 44 | 45 | [[package]] 46 | name = "clap_derive" 47 | version = "3.0.14" 48 | source = "registry+https://github.com/rust-lang/crates.io-index" 49 | checksum = "9a1132dc3944b31c20dd8b906b3a9f0a5d0243e092d59171414969657ac6aa85" 50 | dependencies = [ 51 | "heck", 52 | "proc-macro-error", 53 | "proc-macro2", 54 | "quote", 55 | "syn", 56 | ] 57 | 58 | [[package]] 59 | name = "do-core" 60 | version = "0.1.0" 61 | 62 | [[package]] 63 | name = "do-core1" 64 | version = "0.1.0" 65 | dependencies = [ 66 | "clap", 67 | "do-core", 68 | ] 69 | 70 | [[package]] 71 | name = "hashbrown" 72 | version = "0.11.2" 73 | source = "registry+https://github.com/rust-lang/crates.io-index" 74 | checksum = "ab5ef0d4909ef3724cc8cce6ccc8572c5c817592e9285f5464f8e86f8bd3726e" 75 | 76 | [[package]] 77 | name = "heck" 78 | version = "0.4.0" 79 | source = "registry+https://github.com/rust-lang/crates.io-index" 80 | checksum = "2540771e65fc8cb83cd6e8a237f70c319bd5c29f78ed1084ba5d50eeac86f7f9" 81 | 82 | [[package]] 83 | name = "hermit-abi" 84 | version = "0.1.19" 85 | source = "registry+https://github.com/rust-lang/crates.io-index" 86 | checksum = "62b467343b94ba476dcb2500d242dadbb39557df889310ac77c5d99100aaac33" 87 | dependencies = [ 88 | "libc", 89 | ] 90 | 91 | [[package]] 92 | name = "indexmap" 93 | version = "1.8.0" 94 | source = "registry+https://github.com/rust-lang/crates.io-index" 95 | checksum = "282a6247722caba404c065016bbfa522806e51714c34f5dfc3e4a3a46fcb4223" 96 | dependencies = [ 97 | "autocfg", 98 | "hashbrown", 99 | ] 100 | 101 | [[package]] 102 | name = "lazy_static" 103 | version = "1.4.0" 104 | source = "registry+https://github.com/rust-lang/crates.io-index" 105 | checksum = "e2abad23fbc42b3700f2f279844dc832adb2b2eb069b2df918f455c4e18cc646" 106 | 107 | [[package]] 108 | name = "libc" 109 | version = "0.2.117" 110 | source = "registry+https://github.com/rust-lang/crates.io-index" 111 | checksum = "e74d72e0f9b65b5b4ca49a346af3976df0f9c61d550727f349ecd559f251a26c" 112 | 113 | [[package]] 114 | name = "memchr" 115 | version = "2.4.1" 116 | source = "registry+https://github.com/rust-lang/crates.io-index" 117 | checksum = "308cc39be01b73d0d18f82a0e7b2a3df85245f84af96fdddc5d202d27e47b86a" 118 | 119 | [[package]] 120 | name = "os_str_bytes" 121 | version = "6.0.0" 122 | source = "registry+https://github.com/rust-lang/crates.io-index" 123 | checksum = "8e22443d1643a904602595ba1cd8f7d896afe56d26712531c5ff73a15b2fbf64" 124 | dependencies = [ 125 | "memchr", 126 | ] 127 | 128 | [[package]] 129 | name = "proc-macro-error" 130 | version = "1.0.4" 131 | source = "registry+https://github.com/rust-lang/crates.io-index" 132 | checksum = "da25490ff9892aab3fcf7c36f08cfb902dd3e71ca0f9f9517bea02a73a5ce38c" 133 | dependencies = [ 134 | "proc-macro-error-attr", 135 | "proc-macro2", 136 | "quote", 137 | "syn", 138 | "version_check", 139 | ] 140 | 141 | [[package]] 142 | name = "proc-macro-error-attr" 143 | version = "1.0.4" 144 | source = "registry+https://github.com/rust-lang/crates.io-index" 145 | checksum = "a1be40180e52ecc98ad80b184934baf3d0d29f979574e439af5a55274b35f869" 146 | dependencies = [ 147 | "proc-macro2", 148 | "quote", 149 | "version_check", 150 | ] 151 | 152 | [[package]] 153 | name = "proc-macro2" 154 | version = "1.0.36" 155 | source = "registry+https://github.com/rust-lang/crates.io-index" 156 | checksum = "c7342d5883fbccae1cc37a2353b09c87c9b0f3afd73f5fb9bba687a1f733b029" 157 | dependencies = [ 158 | "unicode-xid", 159 | ] 160 | 161 | [[package]] 162 | name = "quote" 163 | version = "1.0.15" 164 | source = "registry+https://github.com/rust-lang/crates.io-index" 165 | checksum = "864d3e96a899863136fc6e99f3d7cae289dafe43bf2c5ac19b70df7210c0a145" 166 | dependencies = [ 167 | "proc-macro2", 168 | ] 169 | 170 | [[package]] 171 | name = "strsim" 172 | version = "0.10.0" 173 | source = "registry+https://github.com/rust-lang/crates.io-index" 174 | checksum = "73473c0e59e6d5812c5dfe2a064a6444949f089e20eec9a2e5506596494e4623" 175 | 176 | [[package]] 177 | name = "syn" 178 | version = "1.0.86" 179 | source = "registry+https://github.com/rust-lang/crates.io-index" 180 | checksum = "8a65b3f4ffa0092e9887669db0eae07941f023991ab58ea44da8fe8e2d511c6b" 181 | dependencies = [ 182 | "proc-macro2", 183 | "quote", 184 | "unicode-xid", 185 | ] 186 | 187 | [[package]] 188 | name = "termcolor" 189 | version = "1.1.2" 190 | source = "registry+https://github.com/rust-lang/crates.io-index" 191 | checksum = "2dfed899f0eb03f32ee8c6a0aabdb8a7949659e3466561fc0adf54e26d88c5f4" 192 | dependencies = [ 193 | "winapi-util", 194 | ] 195 | 196 | [[package]] 197 | name = "textwrap" 198 | version = "0.14.2" 199 | source = "registry+https://github.com/rust-lang/crates.io-index" 200 | checksum = "0066c8d12af8b5acd21e00547c3797fde4e8677254a7ee429176ccebbe93dd80" 201 | 202 | [[package]] 203 | name = "unicode-xid" 204 | version = "0.2.2" 205 | source = "registry+https://github.com/rust-lang/crates.io-index" 206 | checksum = "8ccb82d61f80a663efe1f787a51b16b5a51e3314d6ac365b08639f52387b33f3" 207 | 208 | [[package]] 209 | name = "version_check" 210 | version = "0.9.4" 211 | source = "registry+https://github.com/rust-lang/crates.io-index" 212 | checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f" 213 | 214 | [[package]] 215 | name = "winapi" 216 | version = "0.3.9" 217 | source = "registry+https://github.com/rust-lang/crates.io-index" 218 | checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419" 219 | dependencies = [ 220 | "winapi-i686-pc-windows-gnu", 221 | "winapi-x86_64-pc-windows-gnu", 222 | ] 223 | 224 | [[package]] 225 | name = "winapi-i686-pc-windows-gnu" 226 | version = "0.4.0" 227 | source = "registry+https://github.com/rust-lang/crates.io-index" 228 | checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6" 229 | 230 | [[package]] 231 | name = "winapi-util" 232 | version = "0.1.5" 233 | source = "registry+https://github.com/rust-lang/crates.io-index" 234 | checksum = "70ec6ce85bb158151cae5e5c87f95a8e97d2c0c4b001223f33a334e3ce5de178" 235 | dependencies = [ 236 | "winapi", 237 | ] 238 | 239 | [[package]] 240 | name = "winapi-x86_64-pc-windows-gnu" 241 | version = "0.4.0" 242 | source = "registry+https://github.com/rust-lang/crates.io-index" 243 | checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f" 244 | -------------------------------------------------------------------------------- /Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "do-core1" 3 | version = "0.1.0" 4 | authors = ["Samuel Ortiz "] 5 | edition = "2018" 6 | 7 | # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html 8 | 9 | [dependencies] 10 | clap = { version = "3.0.5", features = ["derive"] } 11 | do-core = { path = "do-core" } 12 | 13 | [workspace] 14 | members = [ 15 | "do-core" 16 | ] 17 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. Definitions. 8 | 9 | "License" shall mean the terms and conditions for use, reproduction, 10 | and distribution as defined by Sections 1 through 9 of this document. 11 | 12 | "Licensor" shall mean the copyright owner or entity authorized by 13 | the copyright owner that is granting the License. 14 | 15 | "Legal Entity" shall mean the union of the acting entity and all 16 | other entities that control, are controlled by, or are under common 17 | control with that entity. For the purposes of this definition, 18 | "control" means (i) the power, direct or indirect, to cause the 19 | direction or management of such entity, whether by contract or 20 | otherwise, or (ii) ownership of fifty percent (50%) or more of the 21 | outstanding shares, or (iii) beneficial ownership of such entity. 22 | 23 | "You" (or "Your") shall mean an individual or Legal Entity 24 | exercising permissions granted by this License. 25 | 26 | "Source" form shall mean the preferred form for making modifications, 27 | including but not limited to software source code, documentation 28 | source, and configuration files. 29 | 30 | "Object" form shall mean any form resulting from mechanical 31 | transformation or translation of a Source form, including but 32 | not limited to compiled object code, generated documentation, 33 | and conversions to other media types. 34 | 35 | "Work" shall mean the work of authorship, whether in Source or 36 | Object form, made available under the License, as indicated by a 37 | copyright notice that is included in or attached to the work 38 | (an example is provided in the Appendix below). 39 | 40 | "Derivative Works" shall mean any work, whether in Source or Object 41 | form, that is based on (or derived from) the Work and for which the 42 | editorial revisions, annotations, elaborations, or other modifications 43 | represent, as a whole, an original work of authorship. For the purposes 44 | of this License, Derivative Works shall not include works that remain 45 | separable from, or merely link (or bind by name) to the interfaces of, 46 | the Work and Derivative Works thereof. 47 | 48 | "Contribution" shall mean any work of authorship, including 49 | the original version of the Work and any modifications or additions 50 | to that Work or Derivative Works thereof, that is intentionally 51 | submitted to Licensor for inclusion in the Work by the copyright owner 52 | or by an individual or Legal Entity authorized to submit on behalf of 53 | the copyright owner. For the purposes of this definition, "submitted" 54 | means any form of electronic, verbal, or written communication sent 55 | to the Licensor or its representatives, including but not limited to 56 | communication on electronic mailing lists, source code control systems, 57 | and issue tracking systems that are managed by, or on behalf of, the 58 | Licensor for the purpose of discussing and improving the Work, but 59 | excluding communication that is conspicuously marked or otherwise 60 | designated in writing by the copyright owner as "Not a Contribution." 61 | 62 | "Contributor" shall mean Licensor and any individual or Legal Entity 63 | on behalf of whom a Contribution has been received by Licensor and 64 | subsequently incorporated within the Work. 65 | 66 | 2. Grant of Copyright License. Subject to the terms and conditions of 67 | this License, each Contributor hereby grants to You a perpetual, 68 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 69 | copyright license to reproduce, prepare Derivative Works of, 70 | publicly display, publicly perform, sublicense, and distribute the 71 | Work and such Derivative Works in Source or Object form. 72 | 73 | 3. Grant of Patent License. Subject to the terms and conditions of 74 | this License, each Contributor hereby grants to You a perpetual, 75 | worldwide, non-exclusive, no-charge, royalty-free, irrevocable 76 | (except as stated in this section) patent license to make, have made, 77 | use, offer to sell, sell, import, and otherwise transfer the Work, 78 | where such license applies only to those patent claims licensable 79 | by such Contributor that are necessarily infringed by their 80 | Contribution(s) alone or by combination of their Contribution(s) 81 | with the Work to which such Contribution(s) was submitted. If You 82 | institute patent litigation against any entity (including a 83 | cross-claim or counterclaim in a lawsuit) alleging that the Work 84 | or a Contribution incorporated within the Work constitutes direct 85 | or contributory patent infringement, then any patent licenses 86 | granted to You under this License for that Work shall terminate 87 | as of the date such litigation is filed. 88 | 89 | 4. Redistribution. You may reproduce and distribute copies of the 90 | Work or Derivative Works thereof in any medium, with or without 91 | modifications, and in Source or Object form, provided that You 92 | meet the following conditions: 93 | 94 | (a) You must give any other recipients of the Work or 95 | Derivative Works a copy of this License; and 96 | 97 | (b) You must cause any modified files to carry prominent notices 98 | stating that You changed the files; and 99 | 100 | (c) You must retain, in the Source form of any Derivative Works 101 | that You distribute, all copyright, patent, trademark, and 102 | attribution notices from the Source form of the Work, 103 | excluding those notices that do not pertain to any part of 104 | the Derivative Works; and 105 | 106 | (d) If the Work includes a "NOTICE" text file as part of its 107 | distribution, then any Derivative Works that You distribute must 108 | include a readable copy of the attribution notices contained 109 | within such NOTICE file, excluding those notices that do not 110 | pertain to any part of the Derivative Works, in at least one 111 | of the following places: within a NOTICE text file distributed 112 | as part of the Derivative Works; within the Source form or 113 | documentation, if provided along with the Derivative Works; or, 114 | within a display generated by the Derivative Works, if and 115 | wherever such third-party notices normally appear. The contents 116 | of the NOTICE file are for informational purposes only and 117 | do not modify the License. You may add Your own attribution 118 | notices within Derivative Works that You distribute, alongside 119 | or as an addendum to the NOTICE text from the Work, provided 120 | that such additional attribution notices cannot be construed 121 | as modifying the License. 122 | 123 | You may add Your own copyright statement to Your modifications and 124 | may provide additional or different license terms and conditions 125 | for use, reproduction, or distribution of Your modifications, or 126 | for any such Derivative Works as a whole, provided Your use, 127 | reproduction, and distribution of the Work otherwise complies with 128 | the conditions stated in this License. 129 | 130 | 5. Submission of Contributions. Unless You explicitly state otherwise, 131 | any Contribution intentionally submitted for inclusion in the Work 132 | by You to the Licensor shall be under the terms and conditions of 133 | this License, without any additional terms or conditions. 134 | Notwithstanding the above, nothing herein shall supersede or modify 135 | the terms of any separate license agreement you may have executed 136 | with Licensor regarding such Contributions. 137 | 138 | 6. Trademarks. This License does not grant permission to use the trade 139 | names, trademarks, service marks, or product names of the Licensor, 140 | except as required for reasonable and customary use in describing the 141 | origin of the Work and reproducing the content of the NOTICE file. 142 | 143 | 7. Disclaimer of Warranty. Unless required by applicable law or 144 | agreed to in writing, Licensor provides the Work (and each 145 | Contributor provides its Contributions) on an "AS IS" BASIS, 146 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 147 | implied, including, without limitation, any warranties or conditions 148 | of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A 149 | PARTICULAR PURPOSE. You are solely responsible for determining the 150 | appropriateness of using or redistributing the Work and assume any 151 | risks associated with Your exercise of permissions under this License. 152 | 153 | 8. Limitation of Liability. In no event and under no legal theory, 154 | whether in tort (including negligence), contract, or otherwise, 155 | unless required by applicable law (such as deliberate and grossly 156 | negligent acts) or agreed to in writing, shall any Contributor be 157 | liable to You for damages, including any direct, indirect, special, 158 | incidental, or consequential damages of any character arising as a 159 | result of this License or out of the use or inability to use the 160 | Work (including but not limited to damages for loss of goodwill, 161 | work stoppage, computer failure or malfunction, or any and all 162 | other commercial damages or losses), even if such Contributor 163 | has been advised of the possibility of such damages. 164 | 165 | 9. Accepting Warranty or Additional Liability. While redistributing 166 | the Work or Derivative Works thereof, You may choose to offer, 167 | and charge a fee for, acceptance of support, warranty, indemnity, 168 | or other liability obligations and/or rights consistent with this 169 | License. However, in accepting such obligations, You may act only 170 | on Your own behalf and on Your sole responsibility, not on behalf 171 | of any other Contributor, and only if You agree to indemnify, 172 | defend, and hold each Contributor harmless for any liability 173 | incurred by, or claims asserted against, such Contributor by reason 174 | of your accepting any such warranty or additional liability. 175 | 176 | END OF TERMS AND CONDITIONS 177 | 178 | APPENDIX: How to apply the Apache License to your work. 179 | 180 | To apply the Apache License to your work, attach the following 181 | boilerplate notice, with the fields enclosed by brackets "[]" 182 | replaced with your own identifying information. (Don't include 183 | the brackets!) The text should be enclosed in the appropriate 184 | comment syntax for the file format. We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # do-core1 2 | 3 | The `do-core1` is a simple 32-bit processor architecture, mostly for educational purposes. 4 | 5 | It aims at being a support for system programming and computer architecture fundamentals courses. 6 | 7 | ## Instruction Set Architecture 8 | 9 | The do-core1 [Instruction Set Architecture (ISA)](https://en.wikipedia.org/wiki/Instruction_set) is a simple [Reduced Instruction Set Computer (RISC)](https://en.wikipedia.org/wiki/Reduced_instruction_set_computer) 10 | processor architecture, with a very limited memory model and instruction and register set. 11 | 12 | ### Registers 13 | 14 | `do-core1` exposes **32 registers**, from `R0` to`R31`. 15 | 16 | It also uses one Program Counter (`PC`) register and a operation flags (`RFLAGS`) register. 17 | 18 | All `do-core1` registers are **32 bits wide**. 19 | 20 | ### Memory Model 21 | 22 | `do-core1` can address up to **4GiB (4 Giga Bytes) of physical memory**. 23 | 24 | ### Instruction Set 25 | 26 | `do-core1` is a [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computer) architecture and executes fixed-length 27 | instructions of 32 bits. 28 | 29 | The `do-core1` is a 2-operand architecture, i.e. its instruction takes at most 2 operands. 30 | The result of the instruction is always stored in the first operand. 31 | 32 | `do-core1` operands are register indexes i.e. the instruction operates on `R[op]`. 33 | For example, an operand set to 14 is addressing R14. 34 | 35 | When using 2 operands, a `do-core1` instruction can be split into an operation code (opcode), 36 | the first operand (op0) and the second operand (op1). 37 | The opcode is 6 bits long, and operands are 5 bits long: 38 | 39 | ``` 40 | do-core instruction with 2 operands: 41 | 42 | Bits |15 11|10 6|5 0| 43 | ---------------------------------------------------------- 44 | | op1 (bits 11-15) | op0 (bits 6-10) | Opcode (bits 0-5) | 45 | ---------------------------------------------------------- 46 | ``` 47 | 48 | The `do-core1` is a [load-store](https://en.wikipedia.org/wiki/Load%E2%80%93store_architecture) 49 | architecture and supports the following instructions: 50 | 51 | 52 | | Opcode | Instruction | Description | 53 | |--------|--------------|------------------------------------------------------------------------------------------------| 54 | | `0x00` | `LDW Rn, Rm` | **L**oa**D** **W**ord: Load the 32-bit value at the memory address contained in `Rm` into `Rn` | 55 | | `0x01` | `STW Rn, Rm` | **ST**ore **W**ord: Store the 32-bit value from `Rn` into the memory address contained in `Rm` | 56 | | `0x02` | `ADD Rn, Rm` | **ADD**: Add the value contained in `Rm` into `Rn` (`Rn = Rn + Rm`) | 57 | | `0x03` | `XOR Rn, Rm` | e**X**clusive **OR**: Perform a bitwise exclusive OR between `Rn` and `Rm` (`Rn = Rn ^ Rm`) | 58 | -------------------------------------------------------------------------------- /do-core/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "do-core" 3 | version = "0.1.0" 4 | authors = ["Samuel Ortiz "] 5 | edition = "2018" 6 | 7 | [dependencies] 8 | -------------------------------------------------------------------------------- /do-core/src/core.rs: -------------------------------------------------------------------------------- 1 | use crate::instruction::{Instruction, OpCode}; 2 | use crate::memory::Memory; 3 | use crate::{Error, MAX_REGISTER_INDEX, MEMORY_SIZE}; 4 | 5 | pub struct Core { 6 | registers: [u32; MAX_REGISTER_INDEX as usize + 1], 7 | memory: Memory, 8 | } 9 | 10 | impl Core { 11 | pub fn new() -> Self { 12 | let mut core = Core { 13 | registers: [0u32; MAX_REGISTER_INDEX as usize + 1], 14 | memory: Memory::new(MEMORY_SIZE), 15 | }; 16 | 17 | // Arbitrary initial registers value. 18 | // Registers will eventually be initialized through memory loads. 19 | for (index, register) in core.registers.iter_mut().enumerate() { 20 | *register = index as u32 * 0x10; 21 | } 22 | 23 | core 24 | } 25 | 26 | pub fn register(&self, index: u8) -> Result { 27 | if index > MAX_REGISTER_INDEX { 28 | return Err(Error::Op0OutOfRange); 29 | } 30 | 31 | Ok(self.registers[index as usize]) 32 | } 33 | 34 | pub fn dump(&self, preamble: &str) { 35 | println!("do-core1: {}:", preamble); 36 | for (index, register) in self.registers.iter().enumerate() { 37 | println!("\tR{}: {:#x?}", index, *register); 38 | } 39 | } 40 | 41 | pub fn decode(&mut self, insn: u32) -> Result { 42 | Instruction::disassemble(insn) 43 | } 44 | 45 | pub fn execute(&mut self, insn: Instruction) -> Result<(), Error> { 46 | let opcode = insn.opcode(); 47 | 48 | match opcode { 49 | OpCode::ADD => self.add(insn)?, 50 | OpCode::XOR => self.xor(insn)?, 51 | OpCode::LDW => self.load(insn)?, 52 | OpCode::STW => self.store(insn)?, 53 | } 54 | 55 | Ok(()) 56 | } 57 | 58 | fn add(&mut self, insn: Instruction) -> Result<(), Error> { 59 | let op0 = insn.op0() as usize; 60 | let op1 = insn.op1() as usize; 61 | 62 | self.registers[op0] = 63 | self.registers[op0] 64 | .checked_add(self.registers[op1]) 65 | .ok_or(Error::AdditionOverflow( 66 | self.registers[op0], 67 | self.registers[op1], 68 | ))?; 69 | 70 | Ok(()) 71 | } 72 | 73 | fn xor(&mut self, insn: Instruction) -> Result<(), Error> { 74 | let op0 = insn.op0() as usize; 75 | let op1 = insn.op1() as usize; 76 | 77 | self.registers[op0] = self.registers[op0] ^ self.registers[op1]; 78 | 79 | Ok(()) 80 | } 81 | 82 | fn load(&mut self, insn: Instruction) -> Result<(), Error> { 83 | let op0 = insn.op0() as usize; 84 | let op1 = insn.op1() as usize; 85 | 86 | self.registers[op0] = self.memory.load(self.registers[op1])?.into(); 87 | 88 | Ok(()) 89 | } 90 | 91 | fn store(&mut self, insn: Instruction) -> Result<(), Error> { 92 | let op0 = insn.op0() as usize; 93 | let op1 = insn.op1() as usize; 94 | 95 | self.memory 96 | .store(self.registers[op1], self.registers[op0] as u8) 97 | } 98 | } 99 | 100 | #[cfg(test)] 101 | mod tests { 102 | use crate::core::Core; 103 | use crate::Error; 104 | 105 | #[test] 106 | fn test_core_add_r4_r5() -> Result<(), Error> { 107 | let insn = 0x2902; 108 | let mut cpu = Core::new(); 109 | 110 | let r4 = cpu.register(4)?; 111 | let r5 = cpu.register(5)?; 112 | 113 | let decoded_insn = cpu.decode(insn)?; 114 | cpu.execute(decoded_insn)?; 115 | 116 | let new_r4 = cpu.register(4)?; 117 | 118 | assert_eq!(new_r4, r4 + r5); 119 | 120 | Ok(()) 121 | } 122 | 123 | #[test] 124 | fn test_core_xor_r1_r7() -> Result<(), Error> { 125 | let insn = 0x3843; 126 | let mut cpu = Core::new(); 127 | 128 | let r1 = cpu.register(1)?; 129 | let r7 = cpu.register(7)?; 130 | 131 | let decoded_insn = cpu.decode(insn)?; 132 | cpu.execute(decoded_insn)?; 133 | 134 | let new_r1 = cpu.register(1)?; 135 | 136 | assert_eq!(new_r1, r1 ^ r7); 137 | 138 | Ok(()) 139 | } 140 | } 141 | -------------------------------------------------------------------------------- /do-core/src/instruction.rs: -------------------------------------------------------------------------------- 1 | use crate::{Error, MAX_REGISTER_INDEX}; 2 | 3 | #[allow(dead_code)] 4 | #[derive(Clone, Debug, PartialEq)] 5 | pub enum OpCode { 6 | LDW = 0x00, 7 | STW = 0x01, 8 | ADD = 0x02, 9 | XOR = 0x03, 10 | } 11 | 12 | impl OpCode { 13 | pub fn from_u8(opcode: u8) -> Result { 14 | match opcode { 15 | 0x00 => Ok(OpCode::LDW), 16 | 0x01 => Ok(OpCode::STW), 17 | 0x02 => Ok(OpCode::ADD), 18 | 0x03 => Ok(OpCode::XOR), 19 | _ => Err(Error::InvalidOpCode(opcode)), 20 | } 21 | } 22 | } 23 | 24 | #[derive(Debug)] 25 | pub struct Instruction { 26 | opcode: OpCode, 27 | op0: u8, 28 | op1: u8, 29 | } 30 | 31 | impl Instruction { 32 | // Instruction constructor, a.k.a. disassembler. 33 | pub fn disassemble(insn: u32) -> Result { 34 | // Keep the first 6 bits only 35 | let opcode = OpCode::from_u8((insn & 0x3f) as u8)?; 36 | 37 | // Shift right by 6, keep only the first 5 bits. 38 | let op0 = ((insn >> 6) & 0x1f) as u8; 39 | 40 | // Shift right by 11, keep only the first 5 bits. 41 | let op1: u8 = ((insn >> 11) & 0x1f) as u8; 42 | 43 | if op0 > MAX_REGISTER_INDEX { 44 | return Err(Error::Op0OutOfRange); 45 | } 46 | 47 | if op1 > MAX_REGISTER_INDEX { 48 | return Err(Error::Op1OutOfRange); 49 | } 50 | 51 | Ok(Instruction { opcode, op0, op1 }) 52 | } 53 | 54 | pub fn opcode(&self) -> OpCode { 55 | self.opcode.clone() 56 | } 57 | 58 | pub fn op0(&self) -> u8 { 59 | self.op0 60 | } 61 | 62 | pub fn op1(&self) -> u8 { 63 | self.op1 64 | } 65 | } 66 | 67 | #[cfg(test)] 68 | mod tests { 69 | use crate::instruction::{Instruction, OpCode}; 70 | use crate::Error; 71 | 72 | #[test] 73 | fn test_instruction_disassemble_add_r1_r3() -> Result<(), Error> { 74 | let insn_bytes: u32 = 0x1842; 75 | let insn = Instruction::disassemble(insn_bytes)?; 76 | 77 | assert_eq!(insn.opcode, OpCode::ADD); 78 | assert_eq!(insn.op0, 1); 79 | assert_eq!(insn.op1, 3); 80 | 81 | Ok(()) 82 | } 83 | 84 | #[test] 85 | fn test_instruction_disassemble_badop_r9_r1() -> Result<(), Error> { 86 | // Use all 6 bytes for the opcode. 87 | // It should be invalid for a while... 88 | let insn_bytes: u32 = 0x067f; 89 | assert!(Instruction::disassemble(insn_bytes).is_err()); 90 | 91 | Ok(()) 92 | } 93 | 94 | #[test] 95 | fn test_instruction_disassemble_add_r0_r10() -> Result<(), Error> { 96 | let insn_bytes: u32 = 0x20a; 97 | assert!(Instruction::disassemble(insn_bytes).is_err()); 98 | 99 | Ok(()) 100 | } 101 | 102 | #[test] 103 | fn test_instruction_disassemble_add_r7_r2() -> Result<(), Error> { 104 | let insn_bytes: u32 = 0x11c2; 105 | let insn = Instruction::disassemble(insn_bytes)?; 106 | 107 | assert_eq!(insn.opcode, OpCode::ADD); 108 | assert_eq!(insn.op0, 7); 109 | assert_eq!(insn.op1, 2); 110 | 111 | Ok(()) 112 | } 113 | 114 | #[test] 115 | fn test_instruction_disassemble_ldw_r0_r1() -> Result<(), Error> { 116 | let insn_bytes: u32 = 0x0800; 117 | let insn = Instruction::disassemble(insn_bytes)?; 118 | 119 | assert_eq!(insn.opcode, OpCode::LDW); 120 | assert_eq!(insn.op0, 0); 121 | assert_eq!(insn.op1, 1); 122 | 123 | Ok(()) 124 | } 125 | 126 | #[test] 127 | fn test_instruction_disassemble_xor_r2_r3() -> Result<(), Error> { 128 | let insn_bytes: u32 = 0x1883; 129 | let insn = Instruction::disassemble(insn_bytes)?; 130 | 131 | assert_eq!(insn.opcode, OpCode::XOR); 132 | assert_eq!(insn.op0, 2); 133 | assert_eq!(insn.op1, 3); 134 | 135 | Ok(()) 136 | } 137 | 138 | #[test] 139 | fn test_instruction_disassemble_stw_r5_r0() -> Result<(), Error> { 140 | let insn_bytes: u32 = 0x0141; 141 | let insn = Instruction::disassemble(insn_bytes)?; 142 | 143 | assert_eq!(insn.opcode, OpCode::STW); 144 | assert_eq!(insn.op0, 5); 145 | assert_eq!(insn.op1, 0); 146 | 147 | Ok(()) 148 | } 149 | } 150 | -------------------------------------------------------------------------------- /do-core/src/lib.rs: -------------------------------------------------------------------------------- 1 | use crate::instruction::OpCode; 2 | 3 | #[derive(Debug)] 4 | pub enum Error { 5 | InvalidOpCode(u8), 6 | UnsupportedOpCode(OpCode), 7 | Op0OutOfRange, 8 | Op1OutOfRange, 9 | AdditionOverflow(u32, u32), 10 | MemoryOverflow(u32), 11 | } 12 | 13 | // do-core1 register indexes range from 0 to 31. 14 | pub const MAX_REGISTER_INDEX: u8 = 31; 15 | 16 | // Hard-code do-core memory to 1 MB 17 | pub const MEMORY_SIZE: usize = 0x100000; 18 | 19 | pub mod core; 20 | pub mod instruction; 21 | pub mod memory; 22 | -------------------------------------------------------------------------------- /do-core/src/memory.rs: -------------------------------------------------------------------------------- 1 | use crate::Error; 2 | 3 | pub struct Memory { 4 | size: usize, 5 | memory: Vec, 6 | } 7 | 8 | impl Memory { 9 | pub fn new(size: usize) -> Self { 10 | Memory { 11 | size, 12 | memory: vec![0; size], 13 | } 14 | } 15 | 16 | pub fn load(&self, address: u32) -> Result { 17 | if address > self.size as u32 { 18 | return Err(Error::MemoryOverflow(address)); 19 | } 20 | 21 | Ok(self.memory[address as usize]) 22 | } 23 | 24 | pub fn store(&mut self, address: u32, value: u8) -> Result<(), Error> { 25 | if address > self.size as u32 { 26 | return Err(Error::MemoryOverflow(address)); 27 | } 28 | 29 | self.memory[address as usize] = value; 30 | 31 | Ok(()) 32 | } 33 | } 34 | 35 | #[cfg(test)] 36 | mod tests { 37 | use crate::memory::Memory; 38 | use crate::Error; 39 | 40 | #[test] 41 | fn test_memory_store_load() -> Result<(), Error> { 42 | let mut memory = Memory::new(4096); 43 | 44 | memory.store(0x100, 0xf)?; 45 | assert_eq!(memory.load(0x100)?, 0xf); 46 | 47 | Ok(()) 48 | } 49 | 50 | #[test] 51 | fn test_memory_overflow() -> Result<(), Error> { 52 | let mut memory = Memory::new(4096); 53 | 54 | assert!(memory.store(0x2000, 0xf).is_err()); 55 | 56 | Ok(()) 57 | } 58 | } 59 | -------------------------------------------------------------------------------- /src/main.rs: -------------------------------------------------------------------------------- 1 | use clap::Parser; 2 | use do_core::core::Core; 3 | use do_core::Error; 4 | 5 | #[derive(Parser)] 6 | #[clap(version, author)] 7 | struct DoCoreOpts { 8 | /// DO Core instruction 9 | #[clap(short, long)] 10 | insn: String, 11 | } 12 | 13 | fn main() -> Result<(), Error> { 14 | let mut cpu = Core::new(); 15 | let opts: DoCoreOpts = DoCoreOpts::parse(); 16 | 17 | cpu.dump("Initial CPU state"); 18 | 19 | let insn = cpu.decode(u32::from_str_radix(opts.insn.trim_start_matches("0x"), 16).unwrap())?; 20 | cpu.execute(insn)?; 21 | 22 | cpu.dump("Final CPU state"); 23 | 24 | Ok(()) 25 | } 26 | --------------------------------------------------------------------------------