├── blinky ├── Makefile ├── blinky.v ├── iceFUN.pcf └── readMe ├── ledStrip ├── Makefile ├── iceFUN.pcf ├── ledscan.v ├── ledstrip.v ├── music.v ├── readMe └── top.v ├── leds ├── Makefile ├── iceFUN.pcf ├── leds.v ├── ledscan.v └── readMe ├── music ├── Makefile ├── fpga4fun │ ├── high_speed_pursuit │ │ ├── Makefile │ │ ├── iceFUN.pcf │ │ └── top.v │ ├── music_box │ │ ├── Makefile │ │ ├── iceFUN.pcf │ │ └── top.v │ ├── police_siren │ │ ├── Makefile │ │ ├── iceFUN.pcf │ │ └── top.v │ ├── simple_beep │ │ ├── Makefile │ │ ├── iceFUN.pcf │ │ └── top.v │ └── simple_beep_enhanced │ │ ├── Makefile │ │ ├── iceFUN.pcf │ │ └── top.v ├── iceFUN.pcf ├── ledscan.v ├── music.v ├── readMe └── top.v └── readMe /blinky/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = blinky 3 | DEVICE = 8k 4 | 5 | # Files 6 | FILES = blinky.v 7 | 8 | .PHONY: blinky clean burn 9 | 10 | blinky: 11 | # synthesize using Yosys 12 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 13 | # Place and route using nextpnr 14 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 15 | 16 | # Convert to bitstream using IcePack 17 | icepack $(PROJ).asc $(PROJ).bin 18 | 19 | burn: 20 | iceFUNprog $(PROJ).bin 21 | 22 | clean: 23 | rm *.asc *.bin *blif 24 | -------------------------------------------------------------------------------- /blinky/blinky.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | 19 | // Blink an LED provided an input clock 20 | /* module */ 21 | module top (clk, led1, led2, led3, led4, led5, led6, led7, led8, lcol1, lcol2, lcol3, lcol4 ); 22 | /* I/O */ 23 | input clk; 24 | output led1; 25 | output led2; 26 | output led3; 27 | output led4; 28 | output led5; 29 | output led6; 30 | output led7; 31 | output led8; 32 | output lcol1; 33 | output lcol2; 34 | output lcol3; 35 | output lcol4; 36 | 37 | /* Counter register */ 38 | reg [31:0] counter = 32'b0; 39 | 40 | /* LED drivers - counter is inverted for display because leds are active low */ 41 | assign {led8, led7, led6, led5, led4, led3, led2, led1} = counter[26:19] ^ 8'hff; 42 | assign {lcol4, lcol3, lcol2, lcol1} = 4'b1110; 43 | 44 | 45 | /* Count up on every edge of the incoming 12MHz clk */ 46 | always @ (posedge clk) begin 47 | counter <= counter + 1; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /blinky/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port clk P7 16 | -------------------------------------------------------------------------------- /blinky/readMe: -------------------------------------------------------------------------------- 1 | To build the blinky project, install the icestorm toolchain from http://www.clifford.at/icestorm/ 2 | and the iceFUN programmer from https://github.com/devantech/iceFUNprog 3 | 4 | Open a terminal in the blinky folder and enter: 5 | make blinky 6 | make burn 7 | 8 | 9 | -------------------------------------------------------------------------------- /ledStrip/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = music 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm *.asc *.bin *blif 22 | -------------------------------------------------------------------------------- /ledStrip/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /ledStrip/ledscan.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | // LedScan takes the four led columns as inputs and outputs them to the led matrix 19 | 20 | module LedScan ( 21 | input clk12MHz, 22 | input [7:0] leds1, 23 | input [7:0] leds2, 24 | input [7:0] leds3, 25 | input [7:0] leds4, 26 | output reg [7:0] leds, 27 | output reg [3:0] lcol 28 | ); 29 | 30 | 31 | /* Counter register */ 32 | reg [11:0] timer = 12'b0; 33 | 34 | 35 | always @ (posedge clk12MHz) begin 36 | case (timer[11:10]) 37 | 2'b00: begin 38 | leds[7:0] <= leds1[7:0]; 39 | lcol[3:0] <= 4'b1110; 40 | end 41 | 2'b01: begin 42 | leds[7:0] <= leds2[7:0]; 43 | lcol[3:0] <= 4'b1101; 44 | end 45 | 2'b10: begin 46 | leds[7:0] <= leds3[7:0]; 47 | lcol[3:0] <= 4'b1011; 48 | end 49 | 2'b11: begin 50 | leds[7:0] <= leds4[7:0]; 51 | lcol[3:0] <= 4'b0111; 52 | end 53 | endcase 54 | end 55 | 56 | 57 | // increment the scan timer 58 | always @ (posedge clk12MHz) begin 59 | timer <= timer + 1; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /ledStrip/ledstrip.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | 19 | 20 | module LedStrip ( 21 | input clk12MHz, 22 | input [7:0] RedPWM, 23 | input [7:0] GreenPWM, 24 | input [7:0] BluePWM, 25 | output reg Red, 26 | output reg Green, 27 | output reg Blue 28 | ); 29 | 30 | reg [7:0] timer; 31 | 32 | always @ (posedge clk12MHz) begin 33 | timer <= timer+1; 34 | if(RedPWM==timer) Red <= 1'b0; 35 | else if(timer==8'b0) Red <= 1'b1; 36 | else Red <= Red; 37 | 38 | if(GreenPWM==timer) Green <= 1'b0; 39 | else if(timer==8'b0) Green <= 1'b1; 40 | else Green <= Green; 41 | 42 | if(BluePWM==timer) Blue <= 1'b0; 43 | else if(timer==8'b0) Blue <= 1'b1; 44 | else Blue <= Blue; 45 | end 46 | 47 | endmodule 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /ledStrip/music.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | // LedScan takes the four led columns as inputs and outputs them to the led matrix 19 | 20 | module Music ( 21 | input clk12MHz, 22 | input [7:0] midi, 23 | output reg note 24 | ); 25 | 26 | reg [14:0] notetime; // = 22933; 27 | 28 | // Timer register */ 29 | reg [14:0] timer = 15'b0; 30 | 31 | // increment the note timer 32 | always @ (posedge clk12MHz) begin 33 | if (timer==notetime) begin 34 | timer <= 15'b0; 35 | if(midi[7:0]==0) note <= note; 36 | else note <= !note; 37 | end 38 | else timer <= timer + 1; 39 | end 40 | 41 | 42 | always @ (posedge clk12MHz) begin 43 | notetime <= notetime; 44 | case (midi[7:0]) 45 | 8'd60: notetime <= 22933; // C C4 46 | 8'd67: notetime <= 15306; // G G4 47 | 8'd72: notetime <= 11467; // c C5 48 | 8'd74: notetime <= 10216; // d D5 49 | 8'd76: notetime <= 9101; // e E5 50 | endcase 51 | end 52 | 53 | endmodule 54 | 55 | 56 | 57 | module CloseEncounters ( 58 | input clkNote, 59 | input key, 60 | output reg [7:0] midi 61 | ); 62 | 63 | reg [2:0] state = 3'b000; 64 | 65 | always @ (posedge clkNote) begin 66 | case (state) 67 | 3'b000: 68 | begin 69 | midi[7:0] <= 0; 70 | if(key==0) state <= 3'b001; 71 | else state <= 3'b000; 72 | end 73 | 3'b001: 74 | begin 75 | midi[7:0] <= 74; 76 | state <= 3'b010; 77 | end 78 | 3'b010: 79 | begin 80 | midi[7:0] <= 76; 81 | state <= 3'b011; 82 | end 83 | 3'b011: 84 | begin 85 | midi[7:0] <= 72; 86 | state <= 3'b100; 87 | end 88 | 3'b100: 89 | begin 90 | midi[7:0] <= 60; 91 | state <= 3'b101; 92 | end 93 | 3'b101: 94 | begin 95 | midi[7:0] <= 67; 96 | state <= 3'b110; 97 | end 98 | 3'b110: 99 | begin 100 | midi[7:0] <= 67; 101 | state <= 3'b000; 102 | end 103 | endcase 104 | end 105 | 106 | endmodule 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | -------------------------------------------------------------------------------- /ledStrip/readMe: -------------------------------------------------------------------------------- 1 | To build the ledstrip project, install the icestorm toolchain from http://www.clifford.at/icestorm/ 2 | and the iceFUN programmer from https://github.com/devantech/iceFUNprog 3 | 4 | Open a terminal in the music folder and enter: 5 | make iceFUN 6 | make burn 7 | 8 | This project adds three pwm's to drive the high current LEDs, to the music project 9 | 10 | -------------------------------------------------------------------------------- /ledStrip/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | `include "music.v" 19 | `include "ledscan.v" 20 | `include "ledstrip.v" 21 | 22 | module top ( 23 | input clk12MHz, 24 | input key1, 25 | input key2, 26 | input key3, 27 | input key4, 28 | output led1, 29 | output led2, 30 | output led3, 31 | output led4, 32 | output led5, 33 | output led6, 34 | output led7, 35 | output led8, 36 | output lcol1, 37 | output lcol2, 38 | output lcol3, 39 | output lcol4, 40 | output spkp, 41 | output spkm, 42 | output red, 43 | output green, 44 | output blue 45 | ); 46 | 47 | reg [7:0] RedPWM = 8'b00000100; 48 | reg [7:0] GreenPWM = 8'b00010000; 49 | reg [7:0] BluePWM = 8'b01000000; 50 | 51 | // Counter register 52 | reg [31:0] counter = 32'b0; 53 | 54 | // Midi note number 55 | wire [7:0] midi; 56 | 57 | // these are the led holding registers, whatever you write to these appears on the led display 58 | reg [7:0] leds1; 59 | reg [7:0] leds2; 60 | reg [7:0] leds3; 61 | reg [7:0] leds4; 62 | 63 | // The output from the ledscan module 64 | wire [7:0] leds; 65 | wire [3:0] lcol; 66 | 67 | // The output from the music module 68 | wire note; 69 | 70 | // map the output of ledscan to the port pins 71 | assign { led8, led7, led6, led5, led4, led3, led2, led1 } = leds[7:0]; 72 | assign { lcol4, lcol3, lcol2, lcol1 } = lcol[3:0]; 73 | 74 | 75 | // map the note output from the music module to the port pins 76 | assign spkp = note; 77 | assign spkm = !note; 78 | 79 | // instantiate the led scan module 80 | LedScan scan ( 81 | .clk12MHz(clk12MHz), 82 | .leds1(leds1), 83 | .leds2(leds2), 84 | .leds3(leds3), 85 | .leds4(leds4), 86 | .leds(leds), 87 | .lcol(lcol) 88 | ); 89 | 90 | // instantiate the music module 91 | Music music ( 92 | .clk12MHz(clk12MHz), 93 | .midi(midi), 94 | .note(note) 95 | ); 96 | 97 | // instantiate the close encounters module 98 | CloseEncounters CE ( 99 | .clkNote(counter[21]), 100 | .key(key1), 101 | .midi(midi) 102 | ); 103 | 104 | // instantiate PWM module for the led strip 105 | LedStrip ledstrip ( 106 | .clk12MHz(clk12MHz), 107 | .RedPWM(RedPWM), 108 | .GreenPWM(GreenPWM), 109 | .BluePWM(BluePWM), 110 | .Red(red), 111 | .Green(green), 112 | .Blue(blue) 113 | ); 114 | 115 | // This is where you place data in the leds matrix for display. 116 | // Here we put a counter on the 1st column and a simple pattern on the others 117 | always @ (*) begin 118 | leds1[7:0] = ~counter[28:21]; 119 | leds2[7:0] = 8'b11111100; 120 | leds3[7:0] = 8'b11100011; 121 | leds4[7:4] = 4'b0011; 122 | leds4[3:0] = {key4, key3, key2, key1 }; 123 | end 124 | 125 | // increment the counter every clock, only the upper bits are mapped to the leds. 126 | always @ (posedge clk12MHz) begin 127 | counter <= counter + 1; 128 | end 129 | 130 | endmodule 131 | 132 | 133 | 134 | -------------------------------------------------------------------------------- /leds/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = leds 3 | 4 | # Files 5 | FILES = leds.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | 15 | # Convert to bitstream using IcePack 16 | icepack $(PROJ).asc $(PROJ).bin 17 | 18 | burn: 19 | iceFUNprog $(PROJ).bin 20 | 21 | clean: 22 | rm *.asc *.bin *blif 23 | -------------------------------------------------------------------------------- /leds/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | 18 | set_io --warn-no-port clk12MHz P7 19 | -------------------------------------------------------------------------------- /leds/leds.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | `include "ledscan.v" 19 | 20 | module top ( 21 | input clk12MHz, 22 | output led1, 23 | output led2, 24 | output led3, 25 | output led4, 26 | output led5, 27 | output led6, 28 | output led7, 29 | output led8, 30 | output lcol1, 31 | output lcol2, 32 | output lcol3, 33 | output lcol4 34 | ); 35 | 36 | // these are the led holding registers, whatever you write to these appears on the led display 37 | reg [7:0] leds1; 38 | reg [7:0] leds2; 39 | reg [7:0] leds3; 40 | reg [7:0] leds4; 41 | 42 | // The output from the ledscan module 43 | wire [7:0] leds; 44 | wire [3:0] lcol; 45 | 46 | // map the output of ledscan to the port pins 47 | assign { led8, led7, led6, led5, led4, led3, led2, led1 } = leds[7:0]; 48 | assign { lcol4, lcol3, lcol2, lcol1 } = lcol[3:0]; 49 | 50 | // Counter register 51 | reg [31:0] counter = 32'b0; 52 | 53 | // instantiate the led scan module 54 | LedScan scan ( 55 | .clk12MHz(clk12MHz), 56 | .leds1(leds1), 57 | .leds2(leds2), 58 | .leds3(leds3), 59 | .leds4(leds4), 60 | .leds(leds), 61 | .lcol(lcol) 62 | ); 63 | 64 | 65 | // This is where you place data in the leds matrix for display. 66 | // Here we put a counter on the 1st column and a simple pattern on the others 67 | always @ (*) begin 68 | leds1[7:0] = ~counter[28:21]; 69 | leds2[7:0] = 8'b11111100; 70 | leds3[7:0] = 8'b11100011; 71 | leds4[7:0] = 8'b00111111; 72 | end 73 | 74 | // increment the counter every clock, only the upper bits are mapped to the leds. 75 | always @ (posedge clk12MHz) begin 76 | counter <= counter + 1; 77 | end 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /leds/ledscan.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | // LedScan takes the four led columns as inputs and outputs them to the led matrix 19 | 20 | module LedScan ( 21 | input clk12MHz, 22 | input [7:0] leds1, 23 | input [7:0] leds2, 24 | input [7:0] leds3, 25 | input [7:0] leds4, 26 | output reg [7:0] leds, 27 | output reg [3:0] lcol 28 | ); 29 | 30 | 31 | /* Counter register */ 32 | reg [11:0] timer = 12'b0; 33 | 34 | 35 | always @ (posedge clk12MHz) begin 36 | case (timer[11:10]) 37 | 2'b00: begin 38 | leds[7:0] <= leds1[7:0]; 39 | lcol[3:0] <= 4'b1110; 40 | end 41 | 2'b01: begin 42 | leds[7:0] <= leds2[7:0]; 43 | lcol[3:0] <= 4'b1101; 44 | end 45 | 2'b10: begin 46 | leds[7:0] <= leds3[7:0]; 47 | lcol[3:0] <= 4'b1011; 48 | end 49 | 2'b11: begin 50 | leds[7:0] <= leds4[7:0]; 51 | lcol[3:0] <= 4'b0111; 52 | end 53 | endcase 54 | end 55 | 56 | 57 | // increment the scan timer 58 | always @ (posedge clk12MHz) begin 59 | timer <= timer + 1; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /leds/readMe: -------------------------------------------------------------------------------- 1 | To build the leds project, install the icestorm toolchain from http://www.clifford.at/icestorm/ 2 | and the iceFUN programmer from https://github.com/devantech/iceFUNprog 3 | 4 | Open a terminal in the leds folder and enter: 5 | make iceFUN 6 | make burn 7 | 8 | 9 | -------------------------------------------------------------------------------- /music/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = music 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm *.asc *.bin *blif 22 | -------------------------------------------------------------------------------- /music/fpga4fun/high_speed_pursuit/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = top 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm -f *.asc *.bin *.blif *.json 22 | -------------------------------------------------------------------------------- /music/fpga4fun/high_speed_pursuit/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /music/fpga4fun/high_speed_pursuit/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * (c) https://www.fpga4fun.com 3 | * 4 | * ported to iceFun FPGA by Hirosh Dabui 5 | */ 6 | module top ( 7 | input clk12MHz, 8 | output spkp, 9 | output spkm 10 | ); 11 | 12 | wire clk; 13 | assign spkp = speaker; 14 | assign spkm = ~speaker; 15 | // 25 MHz PLL 16 | SB_PLL40_CORE #( 17 | .FEEDBACK_PATH("SIMPLE"), 18 | .DIVR(4'b0000), // DIVR = 0 19 | .DIVF(7'b1000010), // DIVF = 66 20 | .DIVQ(3'b101), // DIVQ = 5 21 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 22 | ) uut ( 23 | .LOCK(locked), 24 | .RESETB(1'b1), 25 | .BYPASS(1'b0), 26 | .REFERENCECLK(clk12MHz), 27 | .PLLOUTCORE(clk) 28 | ); 29 | 30 | 31 | reg [27:0] tone; 32 | always @(posedge clk) tone <= tone+1; 33 | 34 | wire [6:0] fastsweep = (tone[22] ? tone[21:15] : ~tone[21:15]); 35 | wire [6:0] slowsweep = (tone[25] ? tone[24:18] : ~tone[24:18]); 36 | wire [14:0] clkdivider = {2'b01, (tone[27] ? slowsweep : fastsweep), 6'b000000}; 37 | 38 | reg [14:0] counter; 39 | always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1; 40 | 41 | reg speaker; 42 | always @(posedge clk) if(counter==0) speaker <= ~speaker; 43 | endmodule 44 | -------------------------------------------------------------------------------- /music/fpga4fun/music_box/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = top 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm -f *.asc *.bin *.blif *.json 22 | -------------------------------------------------------------------------------- /music/fpga4fun/music_box/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /music/fpga4fun/music_box/top.v: -------------------------------------------------------------------------------- 1 | // Music demo verilog file 2 | // (c) fpga4fun.com 2003-2015 3 | // Plays a little tune on a speaker 4 | // Use a 25MHz clock if possible (other frequencies will 5 | // change the pitch/speed of the song) 6 | // 7 | // ported to iceFun FPGA by Hirosh Dabui 8 | 9 | 10 | module top ( 11 | input clk12MHz, 12 | output spkp, 13 | output spkm 14 | ); 15 | 16 | wire clk; 17 | assign spkp = speaker; 18 | assign spkm = ~speaker; 19 | // 25 MHz PLL 20 | SB_PLL40_CORE #( 21 | .FEEDBACK_PATH("SIMPLE"), 22 | .DIVR(4'b0000), // DIVR = 0 23 | .DIVF(7'b1000010), // DIVF = 66 24 | .DIVQ(3'b101), // DIVQ = 5 25 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 26 | ) uut ( 27 | .LOCK(locked), 28 | .RESETB(1'b1), 29 | .BYPASS(1'b0), 30 | .REFERENCECLK(clk12MHz), 31 | .PLLOUTCORE(clk) 32 | ); 33 | 34 | 35 | reg [30:0] tone; 36 | always @(posedge clk) tone <= tone+31'd1; 37 | 38 | wire [7:0] fullnote; 39 | music_ROM get_fullnote(.clk(clk), .address(tone[29:22]), .note(fullnote)); 40 | 41 | wire [2:0] octave; 42 | wire [3:0] note; 43 | divide_by12 get_octave_and_note(.numerator(fullnote[5:0]), .quotient(octave), .remainder(note)); 44 | 45 | reg [8:0] clkdivider; 46 | always @* 47 | case(note) 48 | 0: clkdivider = 9'd511;//A 49 | 1: clkdivider = 9'd482;// A#/Bb 50 | 2: clkdivider = 9'd455;//B 51 | 3: clkdivider = 9'd430;//C 52 | 4: clkdivider = 9'd405;// C#/Db 53 | 5: clkdivider = 9'd383;//D 54 | 6: clkdivider = 9'd361;// D#/Eb 55 | 7: clkdivider = 9'd341;//E 56 | 8: clkdivider = 9'd322;//F 57 | 9: clkdivider = 9'd303;// F#/Gb 58 | 10: clkdivider = 9'd286;//G 59 | 11: clkdivider = 9'd270;// G#/Ab 60 | default: clkdivider = 9'd0; 61 | endcase 62 | 63 | reg [8:0] counter_note; 64 | reg [7:0] counter_octave; 65 | always @(posedge clk) counter_note <= counter_note==0 ? clkdivider : counter_note-9'd1; 66 | always @(posedge clk) if(counter_note==0) counter_octave <= counter_octave==0 ? 8'd255 >> octave : counter_octave-8'd1; 67 | always @(posedge clk) if(counter_note==0 && counter_octave==0 && fullnote!=0 && tone[21:18]!=0) speaker <= ~speaker; 68 | endmodule 69 | 70 | 71 | ///////////////////////////////////////////////////// 72 | module divide_by12( 73 | input [5:0] numerator, // value to be divided by 12 74 | output reg [2:0] quotient, 75 | output [3:0] remainder 76 | ); 77 | 78 | reg [1:0] remainder3to2; 79 | always @(numerator[5:2]) 80 | case(numerator[5:2]) 81 | 0: begin quotient=0; remainder3to2=0; end 82 | 1: begin quotient=0; remainder3to2=1; end 83 | 2: begin quotient=0; remainder3to2=2; end 84 | 3: begin quotient=1; remainder3to2=0; end 85 | 4: begin quotient=1; remainder3to2=1; end 86 | 5: begin quotient=1; remainder3to2=2; end 87 | 6: begin quotient=2; remainder3to2=0; end 88 | 7: begin quotient=2; remainder3to2=1; end 89 | 8: begin quotient=2; remainder3to2=2; end 90 | 9: begin quotient=3; remainder3to2=0; end 91 | 10: begin quotient=3; remainder3to2=1; end 92 | 11: begin quotient=3; remainder3to2=2; end 93 | 12: begin quotient=4; remainder3to2=0; end 94 | 13: begin quotient=4; remainder3to2=1; end 95 | 14: begin quotient=4; remainder3to2=2; end 96 | 15: begin quotient=5; remainder3to2=0; end 97 | endcase 98 | 99 | assign remainder[1:0] = numerator[1:0]; // the first 2 bits are copied through 100 | assign remainder[3:2] = remainder3to2; // and the last 2 bits come from the case statement 101 | endmodule 102 | ///////////////////////////////////////////////////// 103 | 104 | 105 | module music_ROM( 106 | input clk, 107 | input [7:0] address, 108 | output reg [7:0] note 109 | ); 110 | 111 | always @(posedge clk) 112 | case(address) 113 | 0: note<= 8'd25; 114 | 1: note<= 8'd27; 115 | 2: note<= 8'd27; 116 | 3: note<= 8'd25; 117 | 4: note<= 8'd22; 118 | 5: note<= 8'd22; 119 | 6: note<= 8'd30; 120 | 7: note<= 8'd30; 121 | 8: note<= 8'd27; 122 | 9: note<= 8'd27; 123 | 10: note<= 8'd25; 124 | 11: note<= 8'd25; 125 | 12: note<= 8'd25; 126 | 13: note<= 8'd25; 127 | 14: note<= 8'd25; 128 | 15: note<= 8'd25; 129 | 16: note<= 8'd25; 130 | 17: note<= 8'd27; 131 | 18: note<= 8'd25; 132 | 19: note<= 8'd27; 133 | 20: note<= 8'd25; 134 | 21: note<= 8'd25; 135 | 22: note<= 8'd30; 136 | 23: note<= 8'd30; 137 | 24: note<= 8'd29; 138 | 25: note<= 8'd29; 139 | 26: note<= 8'd29; 140 | 27: note<= 8'd29; 141 | 28: note<= 8'd29; 142 | 29: note<= 8'd29; 143 | 30: note<= 8'd29; 144 | 31: note<= 8'd29; 145 | 32: note<= 8'd23; 146 | 33: note<= 8'd25; 147 | 34: note<= 8'd25; 148 | 35: note<= 8'd23; 149 | 36: note<= 8'd20; 150 | 37: note<= 8'd20; 151 | 38: note<= 8'd29; 152 | 39: note<= 8'd29; 153 | 40: note<= 8'd27; 154 | 41: note<= 8'd27; 155 | 42: note<= 8'd25; 156 | 43: note<= 8'd25; 157 | 44: note<= 8'd25; 158 | 45: note<= 8'd25; 159 | 46: note<= 8'd25; 160 | 47: note<= 8'd25; 161 | 48: note<= 8'd25; 162 | 49: note<= 8'd27; 163 | 50: note<= 8'd25; 164 | 51: note<= 8'd27; 165 | 52: note<= 8'd25; 166 | 53: note<= 8'd25; 167 | 54: note<= 8'd27; 168 | 55: note<= 8'd27; 169 | 56: note<= 8'd22; 170 | 57: note<= 8'd22; 171 | 58: note<= 8'd22; 172 | 59: note<= 8'd22; 173 | 60: note<= 8'd22; 174 | 61: note<= 8'd22; 175 | 62: note<= 8'd22; 176 | 63: note<= 8'd22; 177 | 64: note<= 8'd25; 178 | 65: note<= 8'd27; 179 | 66: note<= 8'd27; 180 | 67: note<= 8'd25; 181 | 68: note<= 8'd22; 182 | 69: note<= 8'd22; 183 | 70: note<= 8'd30; 184 | 71: note<= 8'd30; 185 | 72: note<= 8'd27; 186 | 73: note<= 8'd27; 187 | 74: note<= 8'd25; 188 | 75: note<= 8'd25; 189 | 76: note<= 8'd25; 190 | 77: note<= 8'd25; 191 | 78: note<= 8'd25; 192 | 79: note<= 8'd25; 193 | 80: note<= 8'd25; 194 | 81: note<= 8'd27; 195 | 82: note<= 8'd25; 196 | 83: note<= 8'd27; 197 | 84: note<= 8'd25; 198 | 85: note<= 8'd25; 199 | 86: note<= 8'd30; 200 | 87: note<= 8'd30; 201 | 88: note<= 8'd29; 202 | 89: note<= 8'd29; 203 | 90: note<= 8'd29; 204 | 91: note<= 8'd29; 205 | 92: note<= 8'd29; 206 | 93: note<= 8'd29; 207 | 94: note<= 8'd29; 208 | 95: note<= 8'd29; 209 | 96: note<= 8'd23; 210 | 97: note<= 8'd25; 211 | 98: note<= 8'd25; 212 | 99: note<= 8'd23; 213 | 100: note<= 8'd20; 214 | 101: note<= 8'd20; 215 | 102: note<= 8'd29; 216 | 103: note<= 8'd29; 217 | 104: note<= 8'd27; 218 | 105: note<= 8'd27; 219 | 106: note<= 8'd25; 220 | 107: note<= 8'd25; 221 | 108: note<= 8'd25; 222 | 109: note<= 8'd25; 223 | 110: note<= 8'd25; 224 | 111: note<= 8'd25; 225 | 112: note<= 8'd25; 226 | 113: note<= 8'd27; 227 | 114: note<= 8'd25; 228 | 115: note<= 8'd27; 229 | 116: note<= 8'd25; 230 | 117: note<= 8'd25; 231 | 118: note<= 8'd32; 232 | 119: note<= 8'd32; 233 | 120: note<= 8'd30; 234 | 121: note<= 8'd30; 235 | 122: note<= 8'd30; 236 | 123: note<= 8'd30; 237 | 124: note<= 8'd30; 238 | 125: note<= 8'd30; 239 | 126: note<= 8'd30; 240 | 127: note<= 8'd30; 241 | 128: note<= 8'd27; 242 | 129: note<= 8'd27; 243 | 130: note<= 8'd27; 244 | 131: note<= 8'd27; 245 | 132: note<= 8'd30; 246 | 133: note<= 8'd30; 247 | 134: note<= 8'd30; 248 | 135: note<= 8'd27; 249 | 136: note<= 8'd25; 250 | 137: note<= 8'd25; 251 | 138: note<= 8'd22; 252 | 139: note<= 8'd22; 253 | 140: note<= 8'd25; 254 | 141: note<= 8'd25; 255 | 142: note<= 8'd25; 256 | 143: note<= 8'd25; 257 | 144: note<= 8'd23; 258 | 145: note<= 8'd23; 259 | 146: note<= 8'd27; 260 | 147: note<= 8'd27; 261 | 148: note<= 8'd25; 262 | 149: note<= 8'd25; 263 | 150: note<= 8'd23; 264 | 151: note<= 8'd23; 265 | 152: note<= 8'd22; 266 | 153: note<= 8'd22; 267 | 154: note<= 8'd22; 268 | 155: note<= 8'd22; 269 | 156: note<= 8'd22; 270 | 157: note<= 8'd22; 271 | 158: note<= 8'd22; 272 | 159: note<= 8'd22; 273 | 160: note<= 8'd20; 274 | 161: note<= 8'd20; 275 | 162: note<= 8'd22; 276 | 163: note<= 8'd22; 277 | 164: note<= 8'd25; 278 | 165: note<= 8'd25; 279 | 166: note<= 8'd27; 280 | 167: note<= 8'd27; 281 | 168: note<= 8'd29; 282 | 169: note<= 8'd29; 283 | 170: note<= 8'd29; 284 | 171: note<= 8'd29; 285 | 172: note<= 8'd29; 286 | 173: note<= 8'd29; 287 | 174: note<= 8'd29; 288 | 175: note<= 8'd29; 289 | 176: note<= 8'd30; 290 | 177: note<= 8'd30; 291 | 178: note<= 8'd30; 292 | 179: note<= 8'd30; 293 | 180: note<= 8'd29; 294 | 181: note<= 8'd29; 295 | 182: note<= 8'd27; 296 | 183: note<= 8'd27; 297 | 184: note<= 8'd25; 298 | 185: note<= 8'd25; 299 | 186: note<= 8'd23; 300 | 187: note<= 8'd20; 301 | 188: note<= 8'd20; 302 | 189: note<= 8'd20; 303 | 190: note<= 8'd20; 304 | 191: note<= 8'd20; 305 | 192: note<= 8'd25; 306 | 193: note<= 8'd27; 307 | 194: note<= 8'd27; 308 | 195: note<= 8'd25; 309 | 196: note<= 8'd22; 310 | 197: note<= 8'd22; 311 | 198: note<= 8'd30; 312 | 199: note<= 8'd30; 313 | 200: note<= 8'd27; 314 | 201: note<= 8'd27; 315 | 202: note<= 8'd25; 316 | 203: note<= 8'd25; 317 | 204: note<= 8'd25; 318 | 205: note<= 8'd25; 319 | 206: note<= 8'd25; 320 | 207: note<= 8'd25; 321 | 208: note<= 8'd25; 322 | 209: note<= 8'd27; 323 | 210: note<= 8'd25; 324 | 211: note<= 8'd27; 325 | 212: note<= 8'd25; 326 | 213: note<= 8'd25; 327 | 214: note<= 8'd30; 328 | 215: note<= 8'd30; 329 | 216: note<= 8'd29; 330 | 217: note<= 8'd29; 331 | 218: note<= 8'd29; 332 | 219: note<= 8'd29; 333 | 220: note<= 8'd29; 334 | 221: note<= 8'd29; 335 | 222: note<= 8'd29; 336 | 223: note<= 8'd29; 337 | 224: note<= 8'd23; 338 | 225: note<= 8'd25; 339 | 226: note<= 8'd25; 340 | 227: note<= 8'd23; 341 | 228: note<= 8'd20; 342 | 229: note<= 8'd20; 343 | 230: note<= 8'd29; 344 | 231: note<= 8'd29; 345 | 232: note<= 8'd27; 346 | 233: note<= 8'd27; 347 | 234: note<= 8'd25; 348 | 235: note<= 8'd25; 349 | 236: note<= 8'd25; 350 | 237: note<= 8'd25; 351 | 238: note<= 8'd25; 352 | 239: note<= 8'd25; 353 | 240: note<= 8'd25; 354 | 241: note<= 8'd0; 355 | 242: note<= 8'd00; 356 | default: note <= 8'd0; 357 | endcase 358 | 359 | endmodule 360 | -------------------------------------------------------------------------------- /music/fpga4fun/police_siren/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = top 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm -f *.asc *.bin *.blif *.json 22 | -------------------------------------------------------------------------------- /music/fpga4fun/police_siren/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /music/fpga4fun/police_siren/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * (c) https://www.fpga4fun.com 3 | * 4 | * ported to iceFun FPGA by Hirosh Dabui 5 | */ 6 | module top ( 7 | input clk12MHz, 8 | output spkp, 9 | output spkm 10 | ); 11 | 12 | wire clk; 13 | assign spkp = speaker; 14 | assign spkm = ~speaker; 15 | // 25 MHz PLL 16 | SB_PLL40_CORE #( 17 | .FEEDBACK_PATH("SIMPLE"), 18 | .DIVR(4'b0000), // DIVR = 0 19 | .DIVF(7'b1000010), // DIVF = 66 20 | .DIVQ(3'b101), // DIVQ = 5 21 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 22 | ) uut ( 23 | .LOCK(locked), 24 | .RESETB(1'b1), 25 | .BYPASS(1'b0), 26 | .REFERENCECLK(clk12MHz), 27 | .PLLOUTCORE(clk) 28 | ); 29 | 30 | 31 | reg [27:0] tone; 32 | always @(posedge clk) tone <= tone+1; 33 | 34 | wire [6:0] fastsweep = (tone[22] ? tone[21:15] : ~tone[21:15]); 35 | wire [6:0] slowsweep = (tone[25] ? tone[24:18] : ~tone[24:18]); 36 | wire [14:0] clkdivider = {2'b01, (tone[27] ? slowsweep : fastsweep), 6'b000000}; 37 | 38 | reg [14:0] counter; 39 | always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1; 40 | 41 | reg speaker; 42 | always @(posedge clk) if(counter==0) speaker <= ~speaker; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /music/fpga4fun/simple_beep/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = top 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm -f *.asc *.bin *.blif *.json 22 | -------------------------------------------------------------------------------- /music/fpga4fun/simple_beep/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /music/fpga4fun/simple_beep/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * (c) https://www.fpga4fun.com 3 | * 4 | * ported to iceFun FPGA by Hirosh Dabui 5 | */ 6 | module top ( 7 | input clk12MHz, 8 | output spkp, 9 | output spkm 10 | ); 11 | 12 | wire clk; 13 | assign spkp = speaker; 14 | assign spkm = ~speaker; 15 | // 25 MHz PLL 16 | SB_PLL40_CORE #( 17 | .FEEDBACK_PATH("SIMPLE"), 18 | .DIVR(4'b0000), // DIVR = 0 19 | .DIVF(7'b1000010), // DIVF = 66 20 | .DIVQ(3'b101), // DIVQ = 5 21 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 22 | ) uut ( 23 | .LOCK(locked), 24 | .RESETB(1'b1), 25 | .BYPASS(1'b0), 26 | .REFERENCECLK(clk12MHz), 27 | .PLLOUTCORE(clk) 28 | ); 29 | 30 | reg [15:0] counter; 31 | always @(posedge clk) counter <= counter+1; 32 | 33 | // and use the most significant bit (MSB) of the counter to drive the speaker 34 | assign speaker = counter[15]; 35 | endmodule 36 | -------------------------------------------------------------------------------- /music/fpga4fun/simple_beep_enhanced/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = top 3 | 4 | # Files 5 | FILES = top.v 6 | 7 | .PHONY: iceFUN clean burn 8 | 9 | iceFUN: 10 | # synthesize using Yosys 11 | yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES) 12 | # Place and route using nextpnr 13 | nextpnr-ice40 -r --hx8k --json $(PROJ).json --package cb132 --asc $(PROJ).asc --opt-timing --pcf iceFUN.pcf 14 | # Convert to bitstream using IcePack 15 | icepack $(PROJ).asc $(PROJ).bin 16 | 17 | burn: 18 | iceFUNprog $(PROJ).bin 19 | 20 | clean: 21 | rm -f *.asc *.bin *.blif *.json 22 | -------------------------------------------------------------------------------- /music/fpga4fun/simple_beep_enhanced/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /music/fpga4fun/simple_beep_enhanced/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * (c) https://www.fpga4fun.com 3 | * 4 | * ported to iceFun FPGA by Hirosh Dabui 5 | */ 6 | module top ( 7 | input clk12MHz, 8 | output spkp, 9 | output spkm 10 | ); 11 | 12 | wire clk; 13 | assign spkp = speaker; 14 | assign spkm = ~speaker; 15 | // 25 MHz PLL 16 | SB_PLL40_CORE #( 17 | .FEEDBACK_PATH("SIMPLE"), 18 | .DIVR(4'b0000), // DIVR = 0 19 | .DIVF(7'b1000010), // DIVF = 66 20 | .DIVQ(3'b101), // DIVQ = 5 21 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 22 | ) uut ( 23 | .LOCK(locked), 24 | .RESETB(1'b1), 25 | .BYPASS(1'b0), 26 | .REFERENCECLK(clk12MHz), 27 | .PLLOUTCORE(clk) 28 | ); 29 | 30 | parameter clkdivider = 25000000/440/2; 31 | 32 | reg [14:0] counter; 33 | always @(posedge clk) if(counter==0) counter <= clkdivider-1; else counter <= counter-1; 34 | 35 | reg speaker; 36 | always @(posedge clk) if(counter==0) speaker <= ~speaker; 37 | endmodule 38 | -------------------------------------------------------------------------------- /music/iceFUN.pcf: -------------------------------------------------------------------------------- 1 | # For iceFUN board 2 | 3 | set_io --warn-no-port led1 C10 4 | set_io --warn-no-port led2 A10 5 | set_io --warn-no-port led3 D7 6 | set_io --warn-no-port led4 D6 7 | set_io --warn-no-port led5 A7 8 | set_io --warn-no-port led6 C7 9 | set_io --warn-no-port led7 A4 10 | set_io --warn-no-port led8 C4 11 | set_io --warn-no-port lcol1 A12 12 | set_io --warn-no-port lcol2 D10 13 | set_io --warn-no-port lcol3 A6 14 | set_io --warn-no-port lcol4 C5 15 | set_io --warn-no-port spkp M12 16 | set_io --warn-no-port spkm M6 17 | set_io --warn-no-port key1 C11 18 | set_io --warn-no-port key2 C6 19 | set_io --warn-no-port key3 A11 20 | set_io --warn-no-port key4 A5 21 | set_io --warn-no-port red P14 22 | set_io --warn-no-port green N14 23 | set_io --warn-no-port blue L14 24 | 25 | set_io --warn-no-port clk12MHz P7 26 | -------------------------------------------------------------------------------- /music/ledscan.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | // LedScan takes the four led columns as inputs and outputs them to the led matrix 19 | 20 | module LedScan ( 21 | input clk12MHz, 22 | input [7:0] leds1, 23 | input [7:0] leds2, 24 | input [7:0] leds3, 25 | input [7:0] leds4, 26 | output reg [7:0] leds, 27 | output reg [3:0] lcol 28 | ); 29 | 30 | 31 | /* Counter register */ 32 | reg [11:0] timer = 12'b0; 33 | 34 | 35 | always @ (posedge clk12MHz) begin 36 | case (timer[11:10]) 37 | 2'b00: begin 38 | leds[7:0] <= leds1[7:0]; 39 | lcol[3:0] <= 4'b1110; 40 | end 41 | 2'b01: begin 42 | leds[7:0] <= leds2[7:0]; 43 | lcol[3:0] <= 4'b1101; 44 | end 45 | 2'b10: begin 46 | leds[7:0] <= leds3[7:0]; 47 | lcol[3:0] <= 4'b1011; 48 | end 49 | 2'b11: begin 50 | leds[7:0] <= leds4[7:0]; 51 | lcol[3:0] <= 4'b0111; 52 | end 53 | endcase 54 | end 55 | 56 | 57 | // increment the scan timer 58 | always @ (posedge clk12MHz) begin 59 | timer <= timer + 1; 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /music/music.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | // LedScan takes the four led columns as inputs and outputs them to the led matrix 19 | 20 | module Music ( 21 | input clk12MHz, 22 | input [7:0] midi, 23 | output reg note 24 | ); 25 | 26 | reg [14:0] notetime; // = 22933; 27 | 28 | // Timer register */ 29 | reg [14:0] timer = 15'b0; 30 | 31 | // increment the note timer 32 | always @ (posedge clk12MHz) begin 33 | if (timer==notetime) begin 34 | timer <= 15'b0; 35 | if(midi[7:0]==0) note <= note; 36 | else note <= !note; 37 | end 38 | else timer <= timer + 1; 39 | end 40 | 41 | 42 | always @ (posedge clk12MHz) begin 43 | notetime <= notetime; 44 | case (midi[7:0]) 45 | 8'd60: notetime <= 22933; // C C4 46 | 8'd67: notetime <= 15306; // G G4 47 | 8'd72: notetime <= 11467; // c C5 48 | 8'd74: notetime <= 10216; // d D5 49 | 8'd76: notetime <= 9101; // e E5 50 | endcase 51 | end 52 | 53 | endmodule 54 | 55 | 56 | 57 | module CloseEncounters ( 58 | input clkNote, 59 | input key, 60 | output reg [7:0] midi 61 | ); 62 | 63 | reg [2:0] state = 3'b000; 64 | 65 | always @ (posedge clkNote) begin 66 | midi[7:0] <= 0; 67 | case (state) 68 | 3'b000: 69 | begin 70 | if(key==0) state <= 3'b001; 71 | else state <= 3'b000; 72 | end 73 | 3'b001: 74 | begin 75 | midi[7:0] <= 74; 76 | state <= 3'b010; 77 | end 78 | 3'b010: 79 | begin 80 | midi[7:0] <= 76; 81 | state <= 3'b011; 82 | end 83 | 3'b011: 84 | begin 85 | midi[7:0] <= 72; 86 | state <= 3'b100; 87 | end 88 | 3'b100: 89 | begin 90 | midi[7:0] <= 60; 91 | state <= 3'b101; 92 | end 93 | 3'b101: 94 | begin 95 | midi[7:0] <= 67; 96 | state <= 3'b110; 97 | end 98 | 3'b110: 99 | begin 100 | midi[7:0] <= 67; 101 | state <= 3'b000; 102 | end 103 | default: state <= 3'b000; 104 | endcase 105 | end 106 | 107 | endmodule 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | -------------------------------------------------------------------------------- /music/readMe: -------------------------------------------------------------------------------- 1 | To build the music project, install the icestorm toolchain from http://www.clifford.at/icestorm/ 2 | and the iceFUN programmer from https://github.com/devantech/iceFUNprog 3 | 4 | Open a terminal in the music folder and enter: 5 | make iceFUN 6 | make burn 7 | 8 | This project adds a tune to the leds project 9 | 10 | -------------------------------------------------------------------------------- /music/top.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 3 | * Copyright(C) 2018 Gerald Coe, Devantech Ltd 4 | * 5 | * Permission to use, copy, modify, and/or distribute this software for any purpose with or 6 | * without fee is hereby granted, provided that the above copyright notice and 7 | * this permission notice appear in all copies. 8 | * 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO 10 | * THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. 11 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 12 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 13 | * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | * 16 | */ 17 | 18 | `include "music.v" 19 | `include "ledscan.v" 20 | 21 | module top ( 22 | input clk12MHz, 23 | input key1, 24 | input key2, 25 | input key3, 26 | input key4, 27 | output led1, 28 | output led2, 29 | output led3, 30 | output led4, 31 | output led5, 32 | output led6, 33 | output led7, 34 | output led8, 35 | output lcol1, 36 | output lcol2, 37 | output lcol3, 38 | output lcol4, 39 | output spkp, 40 | output spkm 41 | ); 42 | 43 | // Counter register 44 | reg [31:0] counter; 45 | 46 | // Midi note number 47 | wire [7:0] midi; 48 | 49 | // these are the led holding registers, whatever you write to these appears on the led display 50 | reg [7:0] leds1; 51 | reg [7:0] leds2; 52 | reg [7:0] leds3; 53 | reg [7:0] leds4; 54 | 55 | // The output from the ledscan module 56 | wire [7:0] leds; 57 | wire [3:0] lcol; 58 | 59 | // The output from the music module 60 | wire note; 61 | 62 | // map the output of ledscan to the port pins 63 | assign { led8, led7, led6, led5, led4, led3, led2, led1 } = leds[7:0]; 64 | assign { lcol4, lcol3, lcol2, lcol1 } = lcol[3:0]; 65 | 66 | 67 | // map the note output from the music module to the port pins 68 | assign spkp = note; 69 | assign spkm = !note; 70 | 71 | // instantiate the led scan module 72 | LedScan scan ( 73 | .clk12MHz(clk12MHz), 74 | .leds1(leds1), 75 | .leds2(leds2), 76 | .leds3(leds3), 77 | .leds4(leds4), 78 | .leds(leds), 79 | .lcol(lcol) 80 | ); 81 | 82 | // instantiate the music module 83 | Music music ( 84 | .clk12MHz(clk12MHz), 85 | .midi(midi), 86 | .note(note) 87 | ); 88 | 89 | // instantiate the close encounters module 90 | CloseEncounters CE ( 91 | .clkNote(counter[21]), 92 | .key(key1), 93 | .midi(midi) 94 | ); 95 | 96 | 97 | // This is where you place data in the leds matrix for display. 98 | // Here we put a counter on the 1st column and a simple pattern on the others 99 | always @ (*) begin 100 | leds1[7:0] = ~counter[28:21]; 101 | leds2[7:0] = 8'b11111100; 102 | leds3[7:0] = 8'b11100011; 103 | leds4[7:4] = 4'b0011; 104 | leds4[3:0] = {key4, key3, key2, key1 }; 105 | end 106 | 107 | // increment the counter every clock, only the upper bits are mapped to the leds. 108 | always @ (posedge clk12MHz) begin 109 | counter <= counter + 1; 110 | end 111 | 112 | endmodule 113 | 114 | 115 | 116 | -------------------------------------------------------------------------------- /readMe: -------------------------------------------------------------------------------- 1 | To build these projects, install the icestorm toolchain from http://www.clifford.at/icestorm/ 2 | and the iceFUN programmer from https://github.com/devantech/iceFUNprog 3 | 4 | These projects run on the Devantech iceFUN iCE40-HX8K FPGA module. 5 | 6 | --------------------------------------------------------------------------------