├── Chapters ├── 12MHz │ ├── 12MHz.odt │ ├── FPGA │ │ ├── XuLA │ │ │ └── fast_blinker │ │ │ │ ├── fast_blinker.ucf │ │ │ │ ├── fast_blinker.vhd │ │ │ │ ├── fast_blinker.xise │ │ │ │ └── fast_blinkerTestBench.vhd │ │ └── XuLA2 │ │ │ └── fast_blinker │ │ │ ├── fast_blinker.ucf │ │ │ ├── fast_blinker.vhd │ │ │ ├── fast_blinker.xise │ │ │ └── fast_blinkerTestBench.vhd │ └── Figures │ │ ├── DfsBlockDiagram.png │ │ └── DfsBlockDiagram.svg ├── CompilerBasics │ ├── CompilerBasics.odt │ └── Figures │ │ ├── CompileFlow.png │ │ ├── CompileFlow.svg │ │ └── Thumbs.db ├── FirstFpgaDesign │ ├── FPGA │ │ ├── XuLA │ │ │ └── blinker │ │ │ │ ├── blinker.vhd │ │ │ │ ├── blinker.xise │ │ │ │ └── blinkerTestBench.vhd │ │ └── XuLA2 │ │ │ └── blinker │ │ │ ├── blinker.vhd │ │ │ ├── blinker.xise │ │ │ └── blinkerTestBench.vhd │ ├── Figures │ │ ├── blinker.png │ │ ├── blinker.svg │ │ ├── blinkerCounter.png │ │ ├── blinkerCounter.svg │ │ ├── blinkerTestBench.png │ │ └── blinkerTestBench.svg │ └── FirstFpgaDesign.odt ├── FirstFpgaDownload │ ├── FPGA │ │ ├── XuLA │ │ │ └── blinker │ │ │ │ ├── blinker.ucf │ │ │ │ ├── blinker.vhd │ │ │ │ ├── blinker.xise │ │ │ │ └── blinkerTestBench.vhd │ │ └── XuLA2 │ │ │ └── blinker │ │ │ ├── blinker.ucf │ │ │ ├── blinker.vhd │ │ │ ├── blinker.xise │ │ │ └── blinkerTestBench.vhd │ ├── Figures │ │ ├── Thumbs.db │ │ ├── XulaBlockDiagram.png │ │ ├── XulaBlockDiagram.svg │ │ ├── XulaGnd.JPG │ │ ├── XulaInsert.JPG │ │ ├── XulaLed.JPG │ │ ├── XulaLedGnd.JPG │ │ ├── XulaProtoPinout.png │ │ ├── XulaResistor.JPG │ │ └── XulaUsbConnect.JPG │ ├── FirstFpgaDownload.odt │ ├── Thumbs.db │ └── Videos │ │ ├── .gitignore │ │ ├── blinker_0001.mp4 │ │ └── blinker_0001.wmv ├── FpgaBasics │ ├── Figures │ │ ├── CPLD.png │ │ ├── CPLD.svg │ │ ├── FPGA.png │ │ ├── FPGA.svg │ │ ├── LUT.png │ │ ├── LUT.svg │ │ ├── PLD.png │ │ ├── PLD.svg │ │ ├── Thumbs.db │ │ └── spaghetti_wiring.png │ └── FpgaBasics.odt ├── FrontMatter │ ├── Figures │ │ ├── XuLA_index.psd │ │ └── xesscorp-logo-big.png │ └── FrontMatter.odt ├── LedsButtons │ ├── FMW │ │ ├── XuLAFmwUpdate.cmd │ │ ├── XuLA_jtag.hex │ │ └── xsusbprg.exe │ ├── FPGA │ │ ├── XuLA │ │ │ ├── pc_blink_sub │ │ │ │ ├── Common.vhd │ │ │ │ ├── HostIo.vhd │ │ │ │ ├── SyncToClk.vhd │ │ │ │ ├── pc_blink_sub.ucf │ │ │ │ ├── pc_blink_sub.vhd │ │ │ │ └── pc_blink_sub.xise │ │ │ ├── pc_blinker │ │ │ │ ├── Common.vhd │ │ │ │ ├── HostIo.vhd │ │ │ │ ├── SyncToClk.vhd │ │ │ │ ├── pc_blinker.ucf │ │ │ │ ├── pc_blinker.vhd │ │ │ │ └── pc_blinker.xise │ │ │ └── pc_subtractor │ │ │ │ ├── Common.vhd │ │ │ │ ├── HostIo.vhd │ │ │ │ ├── SyncToClk.vhd │ │ │ │ ├── pc_subtractor.vhd │ │ │ │ └── pc_subtractor.xise │ │ └── XuLA2 │ │ │ ├── pc_blink_sub │ │ │ ├── Common.vhd │ │ │ ├── HostIo.vhd │ │ │ ├── SyncToClk.vhd │ │ │ ├── pc_blink_sub.ucf │ │ │ ├── pc_blink_sub.vhd │ │ │ └── pc_blink_sub.xise │ │ │ ├── pc_blinker │ │ │ ├── Common.vhd │ │ │ ├── HostIo.vhd │ │ │ ├── SyncToClk.vhd │ │ │ ├── pc_blinker.ucf │ │ │ ├── pc_blinker.vhd │ │ │ └── pc_blinker.xise │ │ │ └── pc_subtractor │ │ │ ├── Common.vhd │ │ │ ├── HostIo.vhd │ │ │ ├── SyncToClk.vhd │ │ │ ├── pc_subtractor.vhd │ │ │ └── pc_subtractor.xise │ ├── Figures │ │ ├── DutShiftReg.png │ │ ├── DutShiftReg.svg │ │ ├── PcBlinker.png │ │ ├── PcBlinker.svg │ │ ├── PcBlinkerSub.png │ │ ├── PcBlinkerSub.svg │ │ ├── PcSub.png │ │ └── PcSub.svg │ ├── LedsButtons.odt │ ├── SFW │ │ ├── pc_blinker_test.py │ │ └── pc_subtractor_test.py │ └── Videos │ │ ├── .gitignore │ │ ├── LogoScreen.png │ │ ├── LogoScreen.svg │ │ └── PcLedBlinker.wmv ├── MicroblazeBlinker │ ├── MicroblazeBlinker.odt │ ├── MicroblazeBlinker.pdf │ └── MicroblazeBlinker.zip ├── Preface │ └── Preface.odt ├── Rams │ ├── FMW │ │ ├── XuLAFmwUpdate.cmd │ │ ├── XuLA_jtag.hex │ │ └── xsusbprg.exe │ ├── FPGA │ │ ├── XuLA │ │ │ ├── BRamSPCoreGen │ │ │ │ ├── BRamSPCoreGen.vhd │ │ │ │ ├── BRamSPCoreGen.xise │ │ │ │ ├── BRamSPCoreGen_tb.vhd │ │ │ │ └── ipcore_dir │ │ │ │ │ ├── BRAM.xco │ │ │ │ │ └── BRAM.xise │ │ │ ├── BRamSPCoreGen2 │ │ │ │ ├── BRamSPCoreGen.vhd │ │ │ │ ├── BRamSPCoreGen.xise │ │ │ │ ├── BRamSPCoreGen_tb.vhd │ │ │ │ └── ipcore_dir │ │ │ │ │ ├── BRAM.vhd │ │ │ │ │ ├── BRAM.xco │ │ │ │ │ └── BRAM.xise │ │ │ ├── BRamSPInf │ │ │ │ ├── BRamSPInf.vhd │ │ │ │ ├── BRamSPInf.xise │ │ │ │ └── BRamSPInf_tb.vhd │ │ │ ├── DRamDPInfClear │ │ │ │ ├── DRamDPInfClear.vhd │ │ │ │ ├── DRamDPInfClear.xise │ │ │ │ └── DRamDPInfClear_tb.vhd │ │ │ ├── DRamSPInf │ │ │ │ ├── DRamSPInf.vhd │ │ │ │ ├── DRamSPInf.xise │ │ │ │ └── DRamSPInf_tb.vhd │ │ │ ├── DRamSPInfClear │ │ │ │ ├── DRamSPInfClear.vhd │ │ │ │ ├── DRamSPInfClear.xise │ │ │ │ └── DRamSPInfClear_tb.vhd │ │ │ ├── DRamTPInfClear │ │ │ │ ├── DRamTPInfClear.vhd │ │ │ │ ├── DRamTPInfClear.xise │ │ │ │ └── DRamTPInfClear_tb.vhd │ │ │ └── SdramSPInst │ │ │ │ ├── ClkGen.vhd │ │ │ │ ├── Common.vhd │ │ │ │ ├── HostIo.vhd │ │ │ │ ├── SdramCntl.vhd │ │ │ │ ├── SdramSPInst.vhd │ │ │ │ ├── SdramSPInst.xise │ │ │ │ ├── SyncToClk.vhd │ │ │ │ └── XuLA.ucf │ │ └── XuLA2 │ │ │ ├── BRamSPCoreGen │ │ │ ├── BRamSPCoreGen.vhd │ │ │ ├── BRamSPCoreGen.xise │ │ │ ├── BRamSPCoreGen_tb.vhd │ │ │ └── ipcore_dir │ │ │ │ ├── BRAM.xco │ │ │ │ └── BRAM.xise │ │ │ ├── BRamSPCoreGen2 │ │ │ ├── BRamSPCoreGen.vhd │ │ │ ├── BRamSPCoreGen.xise │ │ │ ├── BRamSPCoreGen_tb.vhd │ │ │ └── ipcore_dir │ │ │ │ ├── BRAM.vhd │ │ │ │ ├── BRAM.xco │ │ │ │ └── BRAM.xise │ │ │ ├── BRamSPInf │ │ │ ├── BRamSPInf.vhd │ │ │ ├── BRamSPInf.xise │ │ │ └── BRamSPInf_tb.vhd │ │ │ ├── DRamDPInfClear │ │ │ ├── DRamDPInfClear.vhd │ │ │ ├── DRamDPInfClear.xise │ │ │ └── DRamDPInfClear_tb.vhd │ │ │ ├── DRamSPInf │ │ │ ├── DRamSPInf.vhd │ │ │ ├── DRamSPInf.xise │ │ │ └── DRamSPInf_tb.vhd │ │ │ ├── DRamSPInfClear │ │ │ ├── DRamSPInfClear.vhd │ │ │ ├── DRamSPInfClear.xise │ │ │ └── DRamSPInfClear_tb.vhd │ │ │ ├── DRamTPInfClear │ │ │ ├── DRamTPInfClear.vhd │ │ │ ├── DRamTPInfClear.xise │ │ │ └── DRamTPInfClear_tb.vhd │ │ │ └── SdramSPInst │ │ │ ├── ClkGen.vhd │ │ │ ├── Common.vhd │ │ │ ├── HostIo.vhd │ │ │ ├── SdramCntl.vhd │ │ │ ├── SdramSPInst.vhd │ │ │ ├── SdramSPInst.xise │ │ │ ├── SyncToClk.vhd │ │ │ └── XuLA2.ucf │ ├── Figures │ │ ├── InnerProd.png │ │ ├── InnerProd.svg │ │ ├── TripleProd.png │ │ ├── TripleProd.svg │ │ ├── rdtiming.png │ │ ├── sdram.png │ │ ├── sdram.svg │ │ └── wrtiming.png │ ├── Rams.odt │ └── SFW │ │ └── sdram_test.py └── Verilog │ ├── FPGA │ ├── XuLA │ │ └── SdramSPInst │ │ │ ├── ClkGen.vhd │ │ │ ├── Common.vhd │ │ │ ├── HostIo.vhd │ │ │ ├── SdramCntl.vhd │ │ │ ├── SdramSPInst.vhd │ │ │ ├── SdramSPInst.xise │ │ │ ├── SdramSPInstTb.vhd │ │ │ ├── SyncToClk.vhd │ │ │ ├── XuLA.ucf │ │ │ └── mt48lc8m16a2.v │ └── XuLA2 │ │ └── SdramSPInst │ │ ├── ClkGen.vhd │ │ ├── Common.vhd │ │ ├── HostIo.vhd │ │ ├── SdramCntl.vhd │ │ ├── SdramSPInst.vhd │ │ ├── SdramSPInst.xise │ │ ├── SdramSPInstTb.vhd │ │ ├── SyncToClk.vhd │ │ ├── XuLA2.ucf │ │ └── mt48lc8m16a2.v │ └── Verilog.odt ├── FpgasNowWhatBook.odm ├── FpgasNowWhat_examples.7z ├── README └── README.pod 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