├── include ├── timescale.svh ├── enums.svh ├── functions.svh ├── structs.svh └── defines.svh ├── input.vc ├── sim └── models │ ├── micron │ ├── ddr2 │ │ └── fetch.sh │ └── ddr3 │ │ └── fetch.sh │ └── nanya │ └── readme.txt ├── .gitignore ├── test ├── cxx │ ├── vip_dfi_if.h │ ├── vip_nasti_trans.h │ ├── vip_nasti_if.h │ ├── sc_main.cpp │ ├── vip_nasti_channel.cpp │ ├── vip_nasti_channel.h │ ├── vip_dfi_channel.cpp │ └── vip_dfi_channel.h └── sv │ └── top.sv ├── install-systemc.sh ├── install-scv.sh ├── install-verilator.sh ├── README.md ├── Makefile ├── rtl ├── bank_manager.sv ├── refresh_control.sv ├── dfi_mux.sv ├── datapath.sv ├── config_if.sv ├── address_mapper.sv ├── sfifo.sv ├── cali_control.sv ├── afifo.sv ├── nasti_if.sv ├── main_control.sv ├── nasti_frontend.sv ├── nastilite_frontend.sv ├── dfi_if.sv ├── nasti_ddrx_mc.sv └── init_control.sv ├── LICENSE ├── fpga └── kc705 │ ├── tb.sv │ ├── top.sv │ └── sdram.xdc └── .travis.yml /include/timescale.svh: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `timescale 1ps/1ps 6 | -------------------------------------------------------------------------------- /input.vc: -------------------------------------------------------------------------------- 1 | --sc 2 | --exe 3 | --trace 4 | 5 | --coverage 6 | 7 | --top-module top 8 | 9 | -Wno-lint 10 | -------------------------------------------------------------------------------- /include/enums.svh: -------------------------------------------------------------------------------- 1 | 2 | typedef enum logic [1:0] {c9 = 2'b00, c10, c11} col_widths; 3 | typedef enum logic [2:0] {r11 = 3'b000, r12, r13, r14, r15} row_widths; 4 | -------------------------------------------------------------------------------- /sim/models/micron/ddr2/fetch.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | wget https://www.micron.com/~/media/documents/products/sim-model/dram/dram/39571024mb_ddr2.zip 4 | unzip 39571024mb_ddr2.zip 5 | 6 | -------------------------------------------------------------------------------- /sim/models/micron/ddr3/fetch.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | wget https://www.micron.com/~/media/documents/products/sim-model/dram/ddr3/ddr3-sdram-verilog-model.zip 4 | unzip ddr3-sdram-verilog-model.zip 5 | 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | *.sublime-project 3 | *.sublime-workspace 4 | 5 | *.gz 6 | *.tar 7 | *.zip 8 | 9 | sim/models/micron/ddr2/ 10 | sim/models/micron/ddr3/ 11 | 12 | coverage 13 | obj_dir 14 | 15 | *.vcd 16 | *.dat 17 | -------------------------------------------------------------------------------- /sim/models/nanya/readme.txt: -------------------------------------------------------------------------------- 1 | Obtain models from http://www.nanya.com/PageEdition1.aspx?Menu_ID=23&lan=en-us&def=210&isPrint=&KeyWords= and http://www.nanya.com/PageEdition1.aspx?Menu_ID=137&lan=en-us&def=220&isPrint=&KeyWords= 2 | -------------------------------------------------------------------------------- /test/cxx/vip_dfi_if.h: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #ifndef VIP_DFI_IF_H 6 | #define VIP_DFI_IF_H 7 | 8 | 9 | #include "systemc.h" 10 | 11 | class vip_dfi_if : virtual public sc_interface { 12 | 13 | public: 14 | 15 | virtual void read() = 0; 16 | virtual void write( sc_bv<8> *data ) = 0; 17 | 18 | }; 19 | 20 | #endif /* VIP_DFI_IF_H */ 21 | -------------------------------------------------------------------------------- /include/functions.svh: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | function integer ns_to_clk(input real data); 6 | ns_to_clk = $ceil(data/`C_CORE_CLK_PERIOD); 7 | endfunction : ns_to_clk 8 | 9 | function integer ceild(input integer number, input integer div); 10 | if ((number % div) > 0) 11 | ceild = (number/div) + 1; 12 | else 13 | ceild = (number/div); 14 | endfunction : ceild 15 | -------------------------------------------------------------------------------- /install-systemc.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | set -e 4 | 5 | if [ ! -d "${HOME}/systemc-2.3.1/lib-linux64" ]; then 6 | wget http://accellera.org/images/downloads/standards/systemc/systemc-2.3.1.tgz 7 | tar -xzvf systemc-2.3.1.tgz && cd systemc-2.3.1 8 | ./configure --prefix="${HOME}/systemc-2.3.1" && make && make check && make install 9 | else 10 | echo "Using SystemC 2.3.1 from cached directory." 11 | fi 12 | -------------------------------------------------------------------------------- /install-scv.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | set -e 4 | 5 | if [ ! -d "${HOME}/scv-2.0.0/lib-linux64" ]; then 6 | wget http://accellera.org/images/downloads/standards/systemc/scv-2.0.0.tgz 7 | tar -xzvf scv-2.0.0.tgz && cd scv-2.0.0 8 | ./configure --prefix="${HOME}/scv-2.0.0" --with-systemc="${SYSTEMC_HOME}" 9 | make && make check && make install 10 | else 11 | echo "Using SCV 2.0.0 from cached directory." 12 | fi 13 | -------------------------------------------------------------------------------- /install-verilator.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | set -e 4 | 5 | if [ ! -d "${HOME}/verilator/bin" ]; then 6 | wget https://github.com/diadatp/verilator/archive/verilator_3_882.tar.gz 7 | tar -xzvf verilator_3_882.tar.gz && cd verilator-verilator_3_882 8 | autoconf && ./configure --prefix="${HOME}/verilator" && make && make test && make install 9 | else 10 | echo "Using Verilator 3.882 from cached directory." 11 | fi 12 | -------------------------------------------------------------------------------- /test/cxx/vip_nasti_trans.h: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #ifndef VIP_NASTI_TRANS_H 6 | #define VIP_NASTI_TRANS_H 7 | 8 | class vip_nasti_trans { 9 | 10 | public: 11 | 12 | sc_bv<> ; 13 | 14 | }; 15 | 16 | SCV_EXTENSIONS(vip_nasti_trans) { 17 | 18 | public: 19 | 20 | scv_extensions<> ; 21 | 22 | SCV_EXTENSIONS_CTOR(vip_nasti_trans) { 23 | SCV_FIELD(); 24 | } 25 | 26 | }; 27 | 28 | #endif /* VIP_NASTI_TRANS_H */ 29 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # NASTI DDRx MC [![Build Status](https://travis-ci.org/diadatp/nasti-ddrx-mc.svg?branch=master)](https://travis-ci.org/diadatp/nasti-ddrx-mc) 2 | 3 | This project is a high performance memory controller that provides a configurable NASTI slave memory mapped interface to DDR2/3 SDRAM (through DFI 3.1). It is a single channel controller with one NASTI slave port. It has been designed to support a wide range of SDRAM configurations from single chip to multi-rank modules. 4 | 5 | ## Getting Started 6 | 7 | Clone the repository and run 'make setup', this will download and unpack all external project resources. Once this is done run 'make build & make sim' to simulate the controller. -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | 2 | proj_dir = $(abspath .) 3 | 4 | default: 5 | echo "make build" 6 | 7 | setup: 8 | cd $(proj_dir)/sim/models/micron/ddr3/ && ./fetch.sh 9 | cd $(proj_dir)/sim/models/micron/ddr2/ && ./fetch.sh 10 | 11 | build: 12 | cd $(proj_dir) 13 | verilator -f input.vc -I$(proj_dir)/include -I$(proj_dir)/rtl \ 14 | $(proj_dir)/test/sv/top.sv $(proj_dir)/test/cxx/*.cpp \ 15 | -CFLAGS "-I$(SCV_INCLUDE)" -LDFLAGS "-L$(SCV_LIBDIR) -lscv" 16 | make -C obj_dir -j $(JOBS) -f Vtop.mk Vtop 17 | 18 | run: 19 | ./obj_dir/Vtop 20 | 21 | coverage: 22 | verilator_coverage coverage.dat --rank --annotate coverage 23 | 24 | clean: 25 | rm -rf obj_dir coverage dump.vcd coverage.dat 26 | 27 | view: 28 | gtkwave --dump dump.vcd --save main_control.gtkw 29 | -------------------------------------------------------------------------------- /rtl/bank_manager.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This module is responsible keeping track of open rows and banks. 3 | * TODO Implement open row vs. closed row priority. 4 | */ 5 | 6 | `include "timescale.svh" 7 | 8 | module bank_manager #(C_ROW_WIDTH = 14) ( 9 | input core_clk , 10 | input core_arstn , 11 | // 12 | input update_row , 13 | input [C_ROW_WIDTH-1:0] new_row , 14 | output logic [C_ROW_WIDTH-1:0] current_row, 15 | // 16 | input toggle_bank, 17 | output logic bank_open 18 | ); 19 | 20 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_bank 21 | if(~core_arstn) begin 22 | current_row <= '0; 23 | bank_open <= '0; 24 | end else begin 25 | if(1'b1 == update_row) begin 26 | current_row <= new_row; 27 | end 28 | if(1'b1 == toggle_bank) begin 29 | bank_open <= ~bank_open; 30 | end 31 | end 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /test/cxx/vip_nasti_if.h: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #ifndef VIP_NASTI_IF_H 6 | #define VIP_NASTI_IF_H 7 | 8 | #include "systemc.h" 9 | #include "scv.h" 10 | 11 | // #include "vip_nasti_trans.h" 12 | 13 | class vip_nasti_if : virtual public sc_interface { 14 | 15 | public: 16 | 17 | typedef sc_bv<10> aid_t; 18 | typedef sc_uint<64> addr_t; 19 | typedef sc_uint<8> len_t; 20 | typedef sc_bv<3> asize_t; 21 | typedef sc_bv<2> burst_t; 22 | 23 | struct read_t { 24 | aid_t id; 25 | addr_t addr; 26 | len_t len; 27 | asize_t size; 28 | burst_t burst; 29 | }; 30 | 31 | virtual bool burstRead( uint64_t id, uint64_t addr, uint64_t len ) = 0; 32 | virtual bool burstWrite( uint64_t id, uint64_t addr, uint64_t len, sc_bv<8> *data ) = 0; 33 | 34 | }; 35 | 36 | SCV_EXTENSIONS(vip_nasti_if::read_t) { 37 | public: 38 | scv_extensions< vip_nasti_if::aid_t > id; 39 | scv_extensions< vip_nasti_if::addr_t > addr; 40 | scv_extensions< vip_nasti_if::len_t > len; 41 | scv_extensions< vip_nasti_if::asize_t > size; 42 | scv_extensions< vip_nasti_if::burst_t > burst; 43 | 44 | SCV_EXTENSIONS_CTOR(vip_nasti_if::read_t) { 45 | SCV_FIELD(id); 46 | SCV_FIELD(addr); 47 | SCV_FIELD(len); 48 | SCV_FIELD(size); 49 | SCV_FIELD(burst); 50 | } 51 | }; 52 | 53 | #endif /* VIP_NASTI_IF_H */ 54 | -------------------------------------------------------------------------------- /rtl/refresh_control.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This module is responsible for timing refresh requests. 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | module refresh_controller #(LOC = 5) ( 8 | input core_clk , 9 | input core_arstn, 10 | // scheduler side 11 | input ref_req , 12 | output [3:0] warning , 13 | // command generator side 14 | output reg ref_do 15 | ); 16 | 17 | logic [15:0] count; // period = 78.125 us/8 18 | 19 | logic [3:0] preponed ; 20 | logic [3:0] postponed; 21 | 22 | always_ff @(posedge clk_1024khz) begin : proc_count 23 | if(~rstn) begin 24 | count <= 0; 25 | end else begin 26 | count <= count + 1; 27 | end 28 | end 29 | 30 | always_ff @(posedge clk_1024khz) begin : proc_refresh 31 | if(rstn) begin 32 | if((4'b1000 == postponed) && (3'b000 == count[2:0])) begin 33 | // force a request, waited the maximum allowable time 34 | ref_do <= 1'b1; 35 | end else if((1'b1 == ref_req) && (3'b000 != count[2:0]) && (preponed < 4'b1000)) begin 36 | // wants to do a request before necessary, fulfill if possible 37 | preponed <= preponed + 1; 38 | ref_do <= 1'b1; 39 | end else if(3'b000 == count[2:0]) begin 40 | postponed <= postponed + 1; 41 | end 42 | end 43 | end 44 | 45 | assign warning = postponed; 46 | 47 | endmodule 48 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2016, 2 | All rights reserved. 3 | 4 | Redistribution and use in source and binary forms, with or without 5 | modification, are permitted provided that the following conditions are met: 6 | 7 | * Redistributions of source code must retain the above copyright notice, this 8 | list of conditions and the following disclaimer. 9 | 10 | * Redistributions in binary form must reproduce the above copyright notice, 11 | this list of conditions and the following disclaimer in the documentation 12 | and/or other materials provided with the distribution. 13 | 14 | * Neither the name of NASTI-DDRx-MC nor the names of its 15 | contributors may be used to endorse or promote products derived from 16 | this software without specific prior written permission. 17 | 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 | -------------------------------------------------------------------------------- /rtl/dfi_mux.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | module dfi_mux ( 8 | dfi_if.slave cali_dfi, 9 | dfi_if.slave data_dfi, 10 | dfi_if.slave init_dfi, 11 | dfi_if.slave main_dfi, 12 | dfi_if.slave tran_dfi, 13 | input [1:0] sel , 14 | dfi_if.master m_dfi 15 | ); 16 | 17 | always_comb begin : proc_assign 18 | // data 19 | m_dfi.dfi_wrdata = data_dfi.dfi_wrdata; 20 | data_dfi.dfi_rddata = main_dfi.dfi_rddata; 21 | // init 22 | m_dfi.dfi_address = init_dfi.dfi_address; 23 | m_dfi.dfi_bank = init_dfi.dfi_bank; 24 | m_dfi.dfi_ras_n = init_dfi.dfi_ras_n; 25 | m_dfi.dfi_cas_n = init_dfi.dfi_cas_n; 26 | m_dfi.dfi_we_n = init_dfi.dfi_we_n; 27 | m_dfi.dfi_cs_n = init_dfi.dfi_cs_n; 28 | m_dfi.dfi_cke = init_dfi.dfi_cke; 29 | m_dfi.dfi_odt = init_dfi.dfi_odt; 30 | m_dfi.dfi_reset_n = init_dfi.dfi_reset_n; 31 | m_dfi.dfi_dram_clk_disable = init_dfi.dfi_dram_clk_disable; 32 | // main 33 | m_dfi.dfi_data_byte_disable = main_dfi.dfi_data_byte_disable; 34 | m_dfi.dfi_freq_ratio = main_dfi.dfi_freq_ratio; 35 | m_dfi.dfi_init_start = main_dfi.dfi_init_start; 36 | main_dfi.dfi_init_complete = m_dfi.dfi_init_complete; 37 | // tran 38 | m_dfi.dfi_wrdata_en = tran_dfi.dfi_wrdata_en; 39 | m_dfi.dfi_wrdata_cs_n = tran_dfi.dfi_wrdata_cs_n; 40 | m_dfi.dfi_wrdata_mask = tran_dfi.dfi_wrdata_mask; 41 | m_dfi.dfi_rddata_en = tran_dfi.dfi_rddata_en; 42 | m_dfi.dfi_rddata_cs_n = tran_dfi.dfi_rddata_cs_n; 43 | tran_dfi.dfi_rddata_valid = main_dfi.dfi_rddata_valid; 44 | end 45 | 46 | endmodule // dfi_mux 47 | -------------------------------------------------------------------------------- /include/structs.svh: -------------------------------------------------------------------------------- 1 | /** 2 | * This file defines structures that encapsulate transactions within the 3 | * memory controller. 4 | */ 5 | 6 | `include "defines.svh" 7 | 8 | typedef struct packed { 9 | logic [ `C_NASTI_ID_WIDTH-1:0] ar_id ; 10 | logic [`C_NASTI_ADDR_WIDTH-1:0] ar_addr ; 11 | logic [ 7:0] ar_len ; 12 | logic [ 2:0] ar_size ; 13 | logic [ 1:0] ar_burst; 14 | logic [`C_NASTI_USER_WIDTH-1:0] ar_user ; 15 | } ar_trans; 16 | 17 | typedef struct packed { 18 | logic [ `C_NASTI_ID_WIDTH-1:0] aw_id ; 19 | logic [`C_NASTI_ADDR_WIDTH-1:0] aw_addr ; 20 | logic [ 7:0] aw_len ; 21 | logic [ 2:0] aw_size ; 22 | logic [ 1:0] aw_burst; 23 | logic [`C_NASTI_USER_WIDTH-1:0] aw_user ; 24 | } aw_trans; 25 | 26 | typedef struct packed { 27 | logic [ `C_NASTI_DATA_WIDTH-1:0] w_data; 28 | logic [`C_NASTI_DATA_WIDTH/8-1:0] w_strb; 29 | logic w_last; 30 | logic [ `C_NASTI_USER_WIDTH-1:0] w_user; 31 | } w_trans; 32 | 33 | typedef struct packed { 34 | logic [ `C_NASTI_ID_WIDTH-1:0] r_id ; 35 | logic [`C_NASTI_DATA_WIDTH-1:0] r_data; 36 | logic r_last; 37 | logic [ 1:0] r_resp; 38 | logic [`C_NASTI_USER_WIDTH-1:0] r_user; 39 | } r_trans; 40 | 41 | typedef struct packed { 42 | logic [ `C_NASTI_ID_WIDTH-1:0] b_id ; 43 | logic [ 1:0] b_resp; 44 | logic [`C_NASTI_USER_WIDTH-1:0] b_user; 45 | } b_trans; 46 | 47 | typedef struct packed { 48 | logic [ 4:0] id ; 49 | logic rw ; 50 | logic [`C_DFI_BANK_WIDTH-1:0] bank ; 51 | logic [ 15:0] row ; 52 | logic [ 11:0] col ; 53 | logic burst_len; 54 | } sdram_trans; 55 | -------------------------------------------------------------------------------- /rtl/datapath.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | module datapath #( 8 | C_DFI_FREQ_RATIO = 0, 9 | C_DFI_DATA_WIDTH = 0 10 | ) ( 11 | input core_clk , 12 | input core_arstn, 13 | // tm side 14 | input w_wren , 15 | output w_wfull , 16 | input [(C_DFI_FREQ_RATIO*C_DFI_DATA_WIDTH)-1:0] w_wdata , 17 | input r_rden , 18 | output r_rempty , 19 | output [(C_DFI_FREQ_RATIO*C_DFI_DATA_WIDTH)-1:0] r_rdata , 20 | // tc side 21 | output r_wfull , 22 | output w_rempty , 23 | input w_rden , 24 | // 25 | dfi_if.master data_dfi 26 | ); 27 | 28 | sfifo #( 29 | .C_DATA_WIDTH(C_DFI_FREQ_RATIO*C_DFI_DATA_WIDTH), 30 | .C_ADDR_WIDTH(15 ) 31 | ) i_sfifo_read ( 32 | .clk (core_clk ), 33 | .arstn (core_arstn ), 34 | .wdata (data_dfi.dfi_rddata ), 35 | .wfull (r_wfull ), 36 | .wren (data_dfi.dfi_rddata_valid), 37 | .rdata (r_rdata ), 38 | .rempty(r_rempty ), 39 | .rden (r_rden ) 40 | ); 41 | 42 | sfifo #( 43 | .C_DATA_WIDTH(C_DFI_FREQ_RATIO*C_DFI_DATA_WIDTH), 44 | .C_ADDR_WIDTH(15 ) 45 | ) i_sfifo_write ( 46 | .clk (core_clk ), 47 | .arstn (core_arstn ), 48 | .wdata (w_wdata ), 49 | .wfull (w_wfull ), 50 | .wren (w_wren ), 51 | .rdata (m_dfi.dfi_wrdata), 52 | .rempty(w_rempty ), 53 | .rden (w_rden ) 54 | ); 55 | 56 | endmodule // datapath 57 | -------------------------------------------------------------------------------- /fpga/kc705/tb.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | module tb; 8 | 9 | parameter CLKP = 5000; 10 | 11 | logic sysclk_p; 12 | logic sysclk_n; 13 | logic sysrst ; 14 | 15 | always begin 16 | sysclk_p = 0; 17 | forever #(CLKP/2) sysclk_p = ~sysclk_p; 18 | end 19 | 20 | always begin 21 | sysclk_n = 1; 22 | forever #(CLKP/2) sysclk_n = ~sysclk_n; 23 | end 24 | 25 | initial begin 26 | sysrst = 1'b1; 27 | #50000; 28 | sysrst = 1'b0; 29 | end 30 | 31 | reg [ 7:0] gpio_led ; 32 | wire [63:0] ddr_dq ; 33 | wire [ 7:0] ddr_dqs_n ; 34 | wire [ 7:0] ddr_dqs_p ; 35 | logic [15:0] ddr_addr ; 36 | logic [ 2:0] ddr_ba ; 37 | logic ddr_ras_n ; 38 | logic ddr_cas_n ; 39 | logic ddr_we_n ; 40 | logic ddr_reset_n; 41 | logic [ 1:0] ddr_ck_p ; 42 | logic [ 1:0] ddr_ck_n ; 43 | logic [ 1:0] ddr_cke ; 44 | logic [ 1:0] ddr_cs_n ; 45 | logic [ 7:0] ddr_dm ; 46 | logic [ 1:0] ddr_odt ; 47 | 48 | top i_top ( 49 | .sysclk_p (sysclk_p ), 50 | .sysclk_n (sysclk_n ), 51 | .sysrst (sysrst ), 52 | .gpio_led (gpio_led ), 53 | .ddr_dq (ddr_dq ), 54 | .ddr_dqs_n (ddr_dqs_n ), 55 | .ddr_dqs_p (ddr_dqs_p ), 56 | .ddr_addr (ddr_addr ), 57 | .ddr_ba (ddr_ba ), 58 | .ddr_ras_n (ddr_ras_n ), 59 | .ddr_cas_n (ddr_cas_n ), 60 | .ddr_we_n (ddr_we_n ), 61 | .ddr_reset_n(ddr_reset_n), 62 | .ddr_ck_p (ddr_ck_p ), 63 | .ddr_ck_n (ddr_ck_n ), 64 | .ddr_cke (ddr_cke ), 65 | .ddr_cs_n (ddr_cs_n ), 66 | .ddr_dm (ddr_dm ), 67 | .ddr_odt (ddr_odt ) 68 | ); 69 | 70 | logic scl; 71 | wire sda; 72 | wire [7:0] cb ; 73 | logic [2:0] sa ; 74 | 75 | ddr3_dimm i_ddr3_dimm ( 76 | .reset_n(ddr_reset_n), 77 | .ck (ddr_ck_p ), 78 | .ck_n (ddr_ck_n ), 79 | .cke (ddr_cke ), 80 | .s_n (ddr_cs_n ), 81 | .ras_n (ddr_ras_n ), 82 | .cas_n (ddr_cas_n ), 83 | .we_n (ddr_we_n ), 84 | .ba (ddr_ba ), 85 | .addr (ddr_addr ), 86 | .odt (ddr_odt ), 87 | .dqs (ddr_dqs_p ), 88 | .dqs_n (ddr_dqs_n ), 89 | .dq (ddr_dq ), 90 | .cb (cb ), 91 | .scl (scl ), 92 | .sa (sa ), 93 | .sda (sda ) 94 | ); 95 | 96 | endmodule // tb 97 | -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- 1 | #========================================================================= 2 | # Travis CI Configuration 3 | #========================================================================= 4 | # This file configures Travis CI to automatically run tests for this RTL 5 | # project everytime a commit is made. 6 | 7 | language: cpp 8 | 9 | # Prefer use of container-based environment as they start up faster and 10 | # provide more RAM and CPU cores. 11 | sudo: false 12 | 13 | # No Git operations will be performed. Best to fetch only the latest commit. 14 | git: 15 | depth: 1 16 | 17 | # TODO: Verify that this setting is optimal. 18 | env: 19 | - JOBS=4 20 | 21 | # Don't need email notifications for now. 22 | notifications: 23 | email: false 24 | 25 | cache: 26 | directories: 27 | - $HOME/systemc-2.3.1 28 | - $HOME/scv-2.0.0 29 | - $HOME/verilator 30 | 31 | # Install the build requirements 32 | addons: 33 | apt: 34 | sources: 35 | # For gcc-4.8 36 | - ubuntu-toolchain-r-test 37 | packages: 38 | # Dependencies from tutorial 39 | - autoconf 40 | - automake 41 | - autotools-dev 42 | - curl 43 | - libmpc-dev 44 | - libmpfr-dev 45 | - libgmp-dev 46 | - gawk 47 | - build-essential 48 | - bison 49 | - flex 50 | - texinfo 51 | - gperf 52 | - libncurses5-dev 53 | - libusb-1.0-0 54 | - libboost-dev 55 | # Need gcc-4.8 56 | - gcc-4.8 57 | - g++-4.8 58 | 59 | install: 60 | # Download, build and install SystemC 2.3.1. 61 | - bash install-systemc.sh 62 | - export SYSTEMC_HOME=${HOME}/systemc-2.3.1 63 | - export SYSTEMC_INCLUDE=${SYSTEMC_HOME}/include 64 | - export SYSTEMC_LIBDIR=${SYSTEMC_HOME}/lib-linux64 65 | - ls -R ${SYSTEMC_HOME} 66 | # Download, build and install SCV 2.0.0. 67 | - bash install-scv.sh 68 | - export SCV_HOME=${HOME}/scv-2.0.0 69 | - export SCV_INCLUDE=${SCV_HOME}/include 70 | - export SCV_LIBDIR=${SCV_HOME}/lib-linux64 71 | - ls -R ${SCV_HOME} 72 | # Export installed libraries. 73 | - export LD_LIBRARY_PATH=".:${SYSTEMC_LIBDIR}:${SCV_LIBDIR}" 74 | # Download, build and install Verilator 3.882. 75 | - export SYSTEMC_CXX_FLAGS=-pthread 76 | - bash install-verilator.sh 77 | # - export VERILATOR_ROOT=${HOME}/verilator/share/verilator 78 | - export PATH=${HOME}/verilator/bin:$PATH 79 | - verilator -V 80 | - ls -R ${VERILATOR_ROOT} 81 | 82 | before_script: 83 | # Download resources required to run verification. 84 | # - make setup 85 | 86 | script: 87 | # Build the RTL and SystemC tests. 88 | - make build 89 | # Run the simulation. 90 | - make run 91 | 92 | after_success: 93 | # Collect coverage data. 94 | - make coverage 95 | - ls -al * 96 | - tar -zcvf payload.tar.gz dump.vcd coverage.dat 97 | - curl --upload-file ./payload.tar.gz https://transfer.sh 98 | - make clean 99 | -------------------------------------------------------------------------------- /rtl/config_if.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | interface config_if; 8 | 9 | logic [12:0] msr0 ; 10 | logic [12:0] msr1 ; 11 | logic [12:0] msr2 ; 12 | logic [12:0] msr3 ; 13 | logic [ 3:0] tAL ; 14 | logic [ 3:0] tBURST ; 15 | logic [ 3:0] tCCD ; 16 | logic [ 3:0] tCL ; 17 | logic [ 3:0] tCMD ; 18 | logic [ 3:0] tCWD ; 19 | logic [ 3:0] tCWL ; 20 | logic [ 3:0] tFAW ; 21 | logic [ 3:0] tMOD ; 22 | logic [ 3:0] tMRD ; 23 | logic [ 3:0] tOST ; 24 | logic [ 3:0] tphy_rdcslat; 25 | logic [ 3:0] tphy_rdlat ; 26 | logic [ 3:0] tRAS ; 27 | logic [ 3:0] tRC ; 28 | logic [ 3:0] tRCD ; 29 | logic [ 3:0] trdata_en ; 30 | logic [ 3:0] tRFC ; 31 | logic [ 3:0] tRP ; 32 | logic [ 3:0] tRRD ; 33 | logic [ 3:0] tRTP ; 34 | logic [ 3:0] tRTRS ; 35 | logic [ 3:0] tWR ; 36 | logic [ 3:0] tWTR ; 37 | logic [ 3:0] tZQinit ; 38 | logic [ 4:0] tXPR ; 39 | 40 | modport master ( 41 | output msr0, 42 | output msr1, 43 | output msr2, 44 | output msr3, 45 | output tAL, 46 | output tBURST, 47 | output tCCD, 48 | output tCL, 49 | output tCMD, 50 | output tCWD, 51 | output tCWL, 52 | output tFAW, 53 | output tMOD, 54 | output tMRD, 55 | output tOST, 56 | output tphy_rdcslat, 57 | output tphy_rdlat, 58 | output tRAS, 59 | output tRC, 60 | output tRCD, 61 | output trdata_en, 62 | output tRFC, 63 | output tRP, 64 | output tRRD, 65 | output tRTP, 66 | output tRTRS, 67 | output tWR, 68 | output tWTR, 69 | output tZQinit, 70 | output tXPR 71 | ); 72 | 73 | modport slave ( 74 | input msr0, 75 | input msr1, 76 | input msr2, 77 | input msr3, 78 | input tAL, 79 | input tBURST, 80 | input tCCD, 81 | input tCL, 82 | input tCMD, 83 | input tCWD, 84 | input tCWL, 85 | input tFAW, 86 | input tMOD, 87 | input tMRD, 88 | input tOST, 89 | input tphy_rdcslat, 90 | input tphy_rdlat, 91 | input tRAS, 92 | input tRC, 93 | input tRCD, 94 | input trdata_en, 95 | input tRFC, 96 | input tRP, 97 | input tRRD, 98 | input tRTP, 99 | input tRTRS, 100 | input tWR, 101 | input tWTR, 102 | input tZQinit, 103 | input tXPR 104 | ); 105 | 106 | endinterface // config_if 107 | -------------------------------------------------------------------------------- /rtl/address_mapper.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This module is responsible for mapping a NASTI address to SDRAM addressing. 3 | */ 4 | 5 | `include "timescale.svh" 6 | `include "enums.svh" 7 | 8 | module address_mapper #( 9 | C_NASTI_ADDR_WIDTH = 0, 10 | C_NASTI_DATA_WIDTH = 0, 11 | C_DFI_CS_WIDTH = 0, 12 | C_DFI_DATA_WIDTH = 0 13 | ) ( 14 | input row_widths r_width , 15 | input col_widths c_width , 16 | input bor , // bank or rank at msb 17 | // 18 | input [C_NASTI_ADDR_WIDTH-1:0] nasti_addr, 19 | output [ C_DFI_CS_WIDTH-1:0] rank , 20 | output logic [ 2:0] bank , 21 | output logic [ 15:0] row , 22 | output logic [ 11:0] column 23 | ); 24 | 25 | initial begin 26 | // TODO fix in later revision 27 | assert(C_NASTI_DATA_WIDTH >= C_DFI_DATA_WIDTH) else $fatal(1, "[mc] NASTI data width is too small."); 28 | end 29 | 30 | localparam OFFSET_BITS = $clog2(C_DFI_DATA_WIDTH/16); 31 | 32 | always_comb begin : proc_column 33 | column[9:0] = nasti_addr[OFFSET_BITS +: 10]; 34 | unique case (c_width) 35 | c9 : column[11:10] = {1'b0, 1'b0}; 36 | c10 : column[11:10] = {1'b0, nasti_addr[10 + OFFSET_BITS]}; 37 | c11 : column[11:10] = {nasti_addr[11 + OFFSET_BITS], nasti_addr[10 + OFFSET_BITS]}; 38 | endcase 39 | end 40 | 41 | localparam SS_WIDTH = 16 + 3 + C_DFI_CS_WIDTH; 42 | 43 | logic [SS_WIDTH-1:0] second_stage; 44 | 45 | always_comb begin : proc_second_stage 46 | unique case (c_width) 47 | c9 : second_stage = nasti_addr[(10 + OFFSET_BITS) +: SS_WIDTH]; 48 | c10 : second_stage = nasti_addr[(11 + OFFSET_BITS) +: SS_WIDTH]; 49 | c11 : second_stage = nasti_addr[(12 + OFFSET_BITS) +: SS_WIDTH]; 50 | endcase 51 | end 52 | 53 | always_comb begin : proc_row 54 | row[11:0] = second_stage[11:0]; 55 | unique case (r_width) 56 | r11 : row[15:12] = 4'b0000; 57 | r12 : row[15:12] = {3'b000, second_stage[12]}; 58 | r13 : row[15:12] = {2'b0, second_stage[13:12]}; 59 | r14 : row[15:12] = {1'b0, second_stage[14:12]}; 60 | r15 : row[15:12] = second_stage[15:12]; 61 | endcase 62 | end 63 | 64 | always_comb begin : proc_bank 65 | for(int i = 0; i < 3; i++) begin 66 | unique case (r_width) 67 | r11 : bank[i] = second_stage[i + 12]; 68 | r12 : bank[i] = second_stage[i + 13]; 69 | r13 : bank[i] = second_stage[i + 14]; 70 | r14 : bank[i] = second_stage[i + 15]; 71 | r15 : bank[i] = second_stage[i + 16]; 72 | endcase 73 | end 74 | end 75 | 76 | endmodule // address_mapper 77 | -------------------------------------------------------------------------------- /rtl/sfifo.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | `include "defines.svh" 7 | `include "enums.svh" 8 | `include "functions.svh" 9 | `include "structs.svh" 10 | 11 | module sfifo #( 12 | C_DATA_WIDTH = 0, 13 | C_ADDR_WIDTH = 0 14 | ) ( 15 | input clk , 16 | input arstn , 17 | input [C_DATA_WIDTH-1:0] wdata , 18 | output wfull , 19 | input wren , 20 | output [C_DATA_WIDTH-1:0] rdata , 21 | output rempty, 22 | input rden 23 | ); 24 | 25 | localparam upper = ceild(C_DATA_WIDTH, 72); 26 | 27 | logic rst; 28 | assign rst = ~arstn; 29 | 30 | logic [upper-1:0] rempty_i; 31 | logic [upper-1:0] wfull_i ; 32 | 33 | assign rempty = |rempty_i; 34 | assign wfull = |wfull_i; 35 | 36 | 37 | logic [upper-1:0][71:0] rdata_mapped; 38 | logic [upper-1:0][71:0] wdata_mapped; 39 | 40 | generate 41 | for (genvar i = 0; i < C_DATA_WIDTH; i++) begin : gen_map 42 | assign rdata[i] = rdata_mapped[i/72][i%72]; 43 | assign wdata_mapped[i/72][i%72] = wdata[i]; 44 | end 45 | endgenerate 46 | 47 | generate 48 | for (genvar i = 0; i < upper; i++) begin : gen_fifo 49 | FIFO_SYNC_MACRO #( 50 | .DEVICE ("7SERIES"), // Target Device: "7SERIES" 51 | .ALMOST_EMPTY_OFFSET(9'h080 ), // Sets the almost empty threshold 52 | .ALMOST_FULL_OFFSET (9'h080 ), // Sets almost full threshold 53 | .DATA_WIDTH (72 ), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb") 54 | .DO_REG (1 ), // Optional output register (0 or 1) 55 | .FIFO_SIZE ("36Kb" ) // Target BRAM: "18Kb" or "36Kb" 56 | ) FIFO_SYNC_MACRO_inst ( 57 | .ALMOSTEMPTY( ), // 1-bit output almost empty 58 | .ALMOSTFULL ( ), // 1-bit output almost full 59 | .DO (rdata_mapped[i]), // Output data, width defined by DATA_WIDTH parameter 60 | .EMPTY (rempty_i[i] ), // 1-bit output empty 61 | .FULL (wfull_i[i] ), // 1-bit output full 62 | .RDCOUNT ( ), // Output read count, width determined by FIFO depth 63 | .RDERR ( ), // 1-bit output read error 64 | .WRCOUNT ( ), // Output write count, width determined by FIFO depth 65 | .WRERR ( ), // 1-bit output write error 66 | .CLK (clk ), // 1-bit input clock 67 | .DI (wdata_mapped[i]), // Input data, width defined by DATA_WIDTH parameter 68 | .RDEN (rden & ~rst ), // 1-bit input read enable 69 | .RST (rst ), // 1-bit input reset 70 | .WREN (wren & ~rst ) // 1-bit input write enable 71 | ); 72 | end 73 | endgenerate 74 | 75 | endmodule // sfifo 76 | -------------------------------------------------------------------------------- /test/cxx/sc_main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | #include 5 | 6 | #include "systemc.h" 7 | #include "scv.h" 8 | 9 | #include "verilated.h" 10 | #include "verilated_vcd_sc.h" 11 | 12 | #include "vip_nasti_if.h" 13 | #include "vip_nasti_channel.h" 14 | #include "vip_dfi_channel.h" 15 | 16 | #include "Vtop.h" 17 | 18 | int sc_main (int argc, char* argv[]) { 19 | 20 | // testing constrained randomization 21 | scv_random::set_global_seed(rand()); 22 | 23 | scv_smart_ptr< vip_nasti_if::read_t > packet; 24 | for (int k = 0; k < 10; k++) { 25 | packet->next(); 26 | cout << packet->addr << " " << packet->id << endl; 27 | } 28 | 29 | // pass command line arguments to verilator 30 | Verilated::commandArgs(argc, argv); 31 | 32 | // randomize all uninitialized signals 33 | Verilated::randReset(2); 34 | 35 | // should be called before sc_time 36 | sc_set_time_resolution(1, SC_PS); 37 | 38 | // define clock periods 39 | sc_time s_nastil_clk_period(100, SC_NS); // 10 MHz 40 | sc_time s_nasti_clk_period(2, SC_NS); // 500 MHz 41 | sc_time core_clk_period(1.25, SC_NS); // 800 MHz 42 | 43 | // define clocks 44 | sc_clock core_clk ("core_clk", core_clk_period); 45 | sc_clock s_nasti_clk ("s_nasti_clk", s_nasti_clk_period); 46 | sc_clock s_nastil_clk ("s_nastil_clk", s_nastil_clk_period); 47 | 48 | // define top level signals 49 | sc_signal core_arstn; 50 | sc_signal s_nasti_aresetn; 51 | sc_signal s_nastil_aresetn; 52 | 53 | // create instance of DUT and perform interconnect 54 | Vtop* dut = new Vtop("dut"); 55 | 56 | vip_nasti_channel* nasti_channel = new vip_nasti_channel("nasti_channel"); 57 | nasti_channel->slaveBind(dut); 58 | 59 | vip_dfi_channel* dfi_channel = new vip_dfi_channel("dfi_channel"); 60 | dfi_channel->masterBind(dut); 61 | 62 | dut->core_arstn(core_arstn); 63 | dut->s_nasti_aresetn(s_nasti_aresetn); 64 | // dut->s_nastil_aresetn(s_nastil_aresetn); 65 | 66 | dut->core_clk(core_clk); 67 | dut->s_nasti_clk(s_nasti_clk); 68 | // dut->s_nastil_clk(s_nastil_clk); 69 | 70 | // initialize simulation inputs 71 | s_nasti_aresetn = 0; 72 | s_nastil_aresetn = 0; 73 | core_arstn = 0; 74 | 75 | // init trace dump 76 | Verilated::traceEverOn(true); 77 | 78 | // one evaluation before enabling waves 79 | sc_start(1, SC_NS); 80 | 81 | VerilatedVcdSc* tfp = new VerilatedVcdSc; 82 | dut->trace(tfp, 99); 83 | tfp->open("dump.vcd"); 84 | 85 | // run simulation for 100 clock periods 86 | while (VL_TIME_Q() < 1000) { 87 | if (11 == VL_TIME_Q()) { 88 | s_nasti_aresetn = 1; 89 | s_nastil_aresetn = 1; 90 | core_arstn = 1; 91 | } else if (14 == VL_TIME_Q()) { 92 | dfi_channel->dfi_init_complete.write(1); 93 | } 94 | sc_start(1, SC_NS); 95 | // tfp->dump(core_clk); 96 | } 97 | 98 | if (tfp) { 99 | tfp->flush(); 100 | } 101 | 102 | // sc_stop(); 103 | 104 | // test done, close VCD dump and exit 105 | tfp->close(); 106 | 107 | // write coverage data 108 | VerilatedCov::write("coverage.dat"); 109 | 110 | return (0); 111 | } 112 | -------------------------------------------------------------------------------- /rtl/cali_control.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | module cali_control ( 8 | input core_clk , 9 | input core_arstn , 10 | input cali_start, 11 | output cali_done , 12 | config_if.slave s_cfg , 13 | dfi_if.master cali_dfi 14 | ); 15 | 16 | enum logic[5:0] {RESET, IDLE, DONE, XXXX = 'x} state, next; 17 | 18 | logic [15:0] counter ; 19 | logic [15:0] counter_next; 20 | 21 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_state 22 | if(~core_arstn) begin 23 | state <= RESET; 24 | counter <= '0; 25 | end else begin 26 | state <= next; 27 | counter <= counter_next; 28 | end 29 | end 30 | 31 | always_comb begin : proc_next 32 | next = XXXX; 33 | unique case (state) 34 | RESET : 35 | begin 36 | next = IDLE; 37 | counter_next = '0; 38 | end 39 | IDLE : 40 | if(1'b1 == cali_start) begin 41 | next = INIT; 42 | counter_next = counter + 1; 43 | end else begin 44 | next = IDLE; 45 | counter_next = '0; 46 | end 47 | INIT : 48 | if(counter == count_top) begin 49 | next = DONE; 50 | counter_next = '0; 51 | end else begin 52 | next = INIT; 53 | counter_next = counter + 1; 54 | end 55 | WL_START : 56 | begin 57 | next = WL_WAIT; 58 | counter_next = '0; 59 | end 60 | WL_WAIT : 61 | if(1'b1 == init_dfi.dfi_wrlvl_resp) begin 62 | next = RL_START; 63 | counter_next = '0; 64 | end else begin 65 | next = WL_WAIT; 66 | counter_next = counter + 1; 67 | end 68 | RL_START : 69 | begin 70 | next = RL_WAIT; 71 | counter_next = '0; 72 | end 73 | RL_WAIT : 74 | if(1'b1 == init_dfi.dfi_rdlvl_resp) begin 75 | next = RL_START; 76 | counter_next = '0; 77 | end else begin 78 | next = RL_WAIT; 79 | counter_next = counter + 1; 80 | end 81 | DONE : 82 | next = DONE; 83 | endcase 84 | end 85 | 86 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_output 87 | if(~core_arstn) begin 88 | cali_dfi.dfi_reset_n <= 1'b1; 89 | cali_done <= 1'b0; 90 | end else begin 91 | unique case (next) 92 | INIT : begin 93 | cali_dfi.dfi_reset_n <= 1'b0; 94 | end 95 | DONE : begin 96 | cali_done <= 1'b1; 97 | end 98 | endcase 99 | end 100 | end 101 | 102 | endmodule // cali_control 103 | -------------------------------------------------------------------------------- /rtl/afifo.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | `include "defines.svh" 7 | `include "enums.svh" 8 | `include "functions.svh" 9 | `include "structs.svh" 10 | 11 | module afifo #( 12 | C_DATA_WIDTH = 0, 13 | C_ADDR_WIDTH = 0 14 | ) ( 15 | input [C_DATA_WIDTH-1:0] wdata , 16 | output wfull , 17 | input wren , 18 | input wclk , 19 | input wrstn , 20 | output [C_DATA_WIDTH-1:0] rdata , 21 | output rempty, 22 | input rden , 23 | input rclk , 24 | input rrstn 25 | ); 26 | 27 | localparam upper = ceild(C_DATA_WIDTH, 72); 28 | 29 | logic rst; 30 | assign rst = ~ (rrstn & wrstn); 31 | 32 | logic inhibit; 33 | 34 | logic [upper-1:0] rempty_i; 35 | logic [upper-1:0] wfull_i ; 36 | 37 | assign rempty = inhibit | |rempty_i; 38 | assign wfull = inhibit | |wfull_i; 39 | 40 | logic [upper-1:0][71:0] rdata_mapped; 41 | logic [upper-1:0][71:0] wdata_mapped; 42 | 43 | logic [3:0] rst_counter; 44 | 45 | always_ff @(posedge rclk or negedge rrstn) begin : proc_inhibit 46 | if(~rrstn) begin 47 | rst_counter <= 0; 48 | inhibit <= 1; 49 | end else begin 50 | if(4 == rst_counter) begin 51 | rst_counter <= rst_counter; 52 | inhibit <= 0; 53 | end else begin 54 | rst_counter <= rst_counter + 1; 55 | inhibit <= 1; 56 | end 57 | end 58 | end 59 | 60 | generate 61 | for (genvar i = 0; i < C_DATA_WIDTH; i++) begin : gen_map 62 | assign rdata[i] = rdata_mapped[i/72][i%72]; 63 | assign wdata_mapped[i/72][i%72] = wdata[i]; 64 | end 65 | endgenerate 66 | 67 | generate 68 | for (genvar i = 0; i < upper; i++) begin : gen_fifo 69 | FIFO_DUALCLOCK_MACRO #( 70 | .ALMOST_EMPTY_OFFSET (9'h080 ), // Sets the almost empty threshold 71 | .ALMOST_FULL_OFFSET (9'h080 ), // Sets almost full threshold 72 | .DATA_WIDTH (72 ), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb") 73 | .DEVICE ("7SERIES"), // Target device: "7SERIES" 74 | .FIFO_SIZE ("36Kb" ), // Target BRAM: "18Kb" or "36Kb" 75 | .FIRST_WORD_FALL_THROUGH("TRUE" ) // Sets the FIFO FWFT to "TRUE" or "FALSE" 76 | ) FIFO_DUALCLOCK_MACRO_inst ( 77 | .ALMOSTEMPTY( ), // 1-bit output almost empty 78 | .ALMOSTFULL ( ), // 1-bit output almost full 79 | .DO (rdata_mapped[i]), // Output data, width defined by DATA_WIDTH parameter 80 | .EMPTY (rempty_i[i] ), // 1-bit output empty 81 | .FULL (wfull_i[i] ), // 1-bit output full 82 | .RDCOUNT ( ), // Output read count, width determined by FIFO depth 83 | .RDERR ( ), // 1-bit output read error 84 | .WRCOUNT ( ), // Output write count, width determined by FIFO depth 85 | .WRERR ( ), // 1-bit output write error 86 | .DI (wdata_mapped[i]), // Input data, width defined by DATA_WIDTH parameter 87 | .RDCLK (rclk ), // 1-bit input read clock 88 | .RDEN (rden & ~rst ), // 1-bit input read enable 89 | .RST (rst ), // 1-bit input reset 90 | .WRCLK (wclk ), // 1-bit input write clock 91 | .WREN (wren & ~rst ) // 1-bit input write enable 92 | ); 93 | end 94 | endgenerate 95 | 96 | endmodule // afifo 97 | -------------------------------------------------------------------------------- /test/cxx/vip_nasti_channel.cpp: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #include "vip_nasti_channel.h" 6 | 7 | bool vip_nasti_channel::burstRead( uint64_t id, uint64_t addr, uint64_t len ) { 8 | 9 | for (int i = 0; i < len; i++) { 10 | ar_id->write(id); 11 | ar_addr->write(addr); 12 | ar_len->write(len); 13 | ar_size->write(128); 14 | ar_burst->write(0); 15 | ar_lock->write(0); 16 | ar_cache->write(0); 17 | ar_prot->write(0); 18 | ar_qos->write(0); 19 | ar_region->write(0); 20 | ar_user->write(0); 21 | 22 | // NASTI handshake 23 | ar_valid->write(1); 24 | do { 25 | wait(); 26 | } while (!ar_ready->read()); 27 | ar_valid->write(0); 28 | } 29 | 30 | return true; 31 | 32 | } 33 | 34 | bool vip_nasti_channel::burstWrite( uint64_t id, uint64_t addr, uint64_t len, sc_bv<8> *data ) { 35 | 36 | return true; 37 | 38 | } 39 | 40 | void vip_nasti_channel::slaveBind(Vtop *dut) { 41 | 42 | dut->s_nasti_aw_id(aw_id_s); 43 | dut->s_nasti_aw_addr(aw_addr_s); 44 | dut->s_nasti_aw_len(aw_len_s); 45 | dut->s_nasti_aw_size(aw_size_s); 46 | dut->s_nasti_aw_burst(aw_burst_s); 47 | dut->s_nasti_aw_lock(aw_lock_s); 48 | dut->s_nasti_aw_cache(aw_cache_s); 49 | dut->s_nasti_aw_prot(aw_prot_s); 50 | dut->s_nasti_aw_qos(aw_qos_s); 51 | dut->s_nasti_aw_region(aw_region_s); 52 | dut->s_nasti_aw_user(aw_user_s); 53 | dut->s_nasti_aw_valid(aw_valid_s); 54 | dut->s_nasti_aw_ready(aw_ready_s); 55 | dut->s_nasti_w_data(w_data_s); 56 | dut->s_nasti_w_strb(w_strb_s); 57 | dut->s_nasti_w_last(w_last_s); 58 | dut->s_nasti_w_user(w_user_s); 59 | dut->s_nasti_w_valid(w_valid_s); 60 | dut->s_nasti_w_ready(w_ready_s); 61 | dut->s_nasti_b_id(b_id_s); 62 | dut->s_nasti_b_resp(b_resp_s); 63 | dut->s_nasti_b_user(b_user_s); 64 | dut->s_nasti_b_valid(b_valid_s); 65 | dut->s_nasti_b_ready(b_ready_s); 66 | dut->s_nasti_ar_id(ar_id_s); 67 | dut->s_nasti_ar_addr(ar_addr_s); 68 | dut->s_nasti_ar_len(ar_len_s); 69 | dut->s_nasti_ar_size(ar_size_s); 70 | dut->s_nasti_ar_burst(ar_burst_s); 71 | dut->s_nasti_ar_lock(ar_lock_s); 72 | dut->s_nasti_ar_cache(ar_cache_s); 73 | dut->s_nasti_ar_prot(ar_prot_s); 74 | dut->s_nasti_ar_qos(ar_qos_s); 75 | dut->s_nasti_ar_region(ar_region_s); 76 | dut->s_nasti_ar_user(ar_user_s); 77 | dut->s_nasti_ar_valid(ar_valid_s); 78 | dut->s_nasti_ar_ready(ar_ready_s); 79 | dut->s_nasti_r_id(r_id_s); 80 | dut->s_nasti_r_resp(r_resp_s); 81 | dut->s_nasti_r_last(r_last_s); 82 | dut->s_nasti_r_user(r_user_s); 83 | dut->s_nasti_r_valid(r_valid_s); 84 | dut->s_nasti_r_ready(r_ready_s); 85 | dut->s_nasti_r_data(r_data_s); 86 | 87 | aw_id(aw_id_s); 88 | aw_addr(aw_addr_s); 89 | aw_len(aw_len_s); 90 | aw_size(aw_size_s); 91 | aw_burst(aw_burst_s); 92 | aw_lock(aw_lock_s); 93 | aw_cache(aw_cache_s); 94 | aw_prot(aw_prot_s); 95 | aw_qos(aw_qos_s); 96 | aw_region(aw_region_s); 97 | aw_user(aw_user_s); 98 | aw_valid(aw_valid_s); 99 | aw_ready(aw_ready_s); 100 | w_data(w_data_s); 101 | w_strb(w_strb_s); 102 | w_last(w_last_s); 103 | w_user(w_user_s); 104 | w_valid(w_valid_s); 105 | w_ready(w_ready_s); 106 | b_id(b_id_s); 107 | b_resp(b_resp_s); 108 | b_user(b_user_s); 109 | b_valid(b_valid_s); 110 | b_ready(b_ready_s); 111 | ar_id(ar_id_s); 112 | ar_addr(ar_addr_s); 113 | ar_len(ar_len_s); 114 | ar_size(ar_size_s); 115 | ar_burst(ar_burst_s); 116 | ar_lock(ar_lock_s); 117 | ar_cache(ar_cache_s); 118 | ar_prot(ar_prot_s); 119 | ar_qos(ar_qos_s); 120 | ar_region(ar_region_s); 121 | ar_user(ar_user_s); 122 | ar_valid(ar_valid_s); 123 | ar_ready(ar_ready_s); 124 | r_id(r_id_s); 125 | r_resp(r_resp_s); 126 | r_last(r_last_s); 127 | r_user(r_user_s); 128 | r_valid(r_valid_s); 129 | r_ready(r_ready_s); 130 | r_data(r_data_s); 131 | 132 | } 133 | -------------------------------------------------------------------------------- /rtl/nasti_if.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | interface nasti_if #( 8 | C_NASTI_ID_WIDTH = 9, // width of id 9 | C_NASTI_ADDR_WIDTH = 32, // width of address 10 | C_NASTI_DATA_WIDTH = 64, // width of data 11 | C_NASTI_USER_WIDTH = 1 // width of user field, must > 0, let synthesizer trim it if not in use 12 | ); 13 | 14 | initial begin 15 | assert(C_NASTI_USER_WIDTH > 0) else $fatal(1, "[nasti interface] User field must have at least 1 bit!"); 16 | // TODO fix 17 | // assert((32 == C_NASTI_DATA_WIDTH) || (64 == C_NASTI_DATA_WIDTH)) else $fatal(1, "[nastilite interface] Data field must be either 32 or 64 bits wide!"); 18 | end 19 | 20 | // write/read address 21 | logic [ C_NASTI_ID_WIDTH-1:0] aw_id, ar_id; 22 | logic [C_NASTI_ADDR_WIDTH-1:0] aw_addr, ar_addr; 23 | logic [ 7:0] aw_len, ar_len; 24 | logic [ 2:0] aw_size, ar_size; 25 | logic [ 1:0] aw_burst, ar_burst; 26 | logic aw_lock, ar_lock; 27 | logic [ 3:0] aw_cache, ar_cache; 28 | logic [ 2:0] aw_prot, ar_prot; 29 | logic [ 3:0] aw_qos, ar_qos; 30 | logic [ 3:0] aw_region, ar_region; 31 | logic [C_NASTI_USER_WIDTH-1:0] aw_user, ar_user; 32 | logic aw_valid, ar_valid; 33 | logic aw_ready, ar_ready; 34 | 35 | // write/read data 36 | logic [ C_NASTI_DATA_WIDTH-1:0] w_data, r_data; 37 | logic [C_NASTI_DATA_WIDTH/8-1:0] w_strb ; 38 | logic w_last, r_last; 39 | logic [ C_NASTI_USER_WIDTH-1:0] w_user ; 40 | logic w_valid; 41 | logic w_ready; 42 | 43 | // write/read response 44 | logic [ C_NASTI_ID_WIDTH-1:0] b_id, r_id; 45 | logic [ 1:0] b_resp, r_resp; 46 | logic [C_NASTI_USER_WIDTH-1:0] b_user, r_user; 47 | logic b_valid, r_valid; 48 | logic b_ready, r_ready; 49 | 50 | modport master ( 51 | // write/read address 52 | output aw_id, ar_id, 53 | output aw_addr, ar_addr, 54 | output aw_len, ar_len, 55 | output aw_size, ar_size, 56 | output aw_burst, ar_burst, 57 | output aw_lock, ar_lock, 58 | output aw_cache, ar_cache, 59 | output aw_prot, ar_prot, 60 | output aw_qos, ar_qos, 61 | output aw_region, ar_region, 62 | output aw_user, ar_user, 63 | output aw_valid, ar_valid, 64 | input aw_ready, ar_ready, 65 | // write data 66 | output w_data, 67 | output w_strb, 68 | output w_last, 69 | output w_user, 70 | output w_valid, 71 | input w_ready, 72 | // read data 73 | input r_data, 74 | input r_last, 75 | // write/read response 76 | input b_id, r_id, 77 | input b_resp, r_resp, 78 | input b_user, r_user, 79 | input b_valid, r_valid, 80 | output b_ready, r_ready 81 | ); 82 | 83 | modport slave ( 84 | // write/read address 85 | input aw_id, ar_id, 86 | input aw_addr, ar_addr, 87 | input aw_len, ar_len, 88 | input aw_size, ar_size, 89 | input aw_burst, ar_burst, 90 | input aw_lock, ar_lock, 91 | input aw_cache, ar_cache, 92 | input aw_prot, ar_prot, 93 | input aw_qos, ar_qos, 94 | input aw_region, ar_region, 95 | input aw_user, ar_user, 96 | input aw_valid, ar_valid, 97 | output aw_ready, ar_ready, 98 | // write data 99 | input w_data, 100 | input w_strb, 101 | input w_last, 102 | input w_user, 103 | input w_valid, 104 | output w_ready, 105 | // read data 106 | output r_data, 107 | output r_last, 108 | // write/read response 109 | output b_id, r_id, 110 | output b_resp, r_resp, 111 | output b_user, r_user, 112 | output b_valid, r_valid, 113 | input b_ready, r_ready 114 | ); 115 | 116 | endinterface // nasti_if 117 | -------------------------------------------------------------------------------- /include/defines.svh: -------------------------------------------------------------------------------- 1 | /** 2 | * This file defines macros that are used to configure the memory controller. 3 | */ 4 | 5 | // The clock cycle period of the core_clk signal in 1n/1p. 6 | `define C_CORE_CLK_PERIOD 5.000 7 | 8 | // The number of identification tags bits to be supported by the slave. 9 | `define C_NASTI_ID_WIDTH 1 10 | 11 | // The width of the address bus on the NASTI interface. For flexibility in 12 | // dynamic SDRAM density support, a minimum of xx is required. 13 | `define C_NASTI_ADDR_WIDTH 32 14 | 15 | // The width of the data bus on the NASTI interface. This is critical to the 16 | // efficiency of the design. 17 | `define C_NASTI_DATA_WIDTH 64 18 | 19 | // The width of User-defined signals. Usused but set to 1, trimmed by synthesis. 20 | `define C_NASTI_USER_WIDTH 8 21 | 22 | // The width of the NASTI-Lite address bus. Do not touch this value. 23 | `define C_NASTIL_ADDR_WIDTH 6 24 | 25 | // The width of the NASTI-Lite data bus. Set to either 32 or 64. 64 preferred. 26 | `define C_NASTIL_DATA_WIDTH 64 27 | 28 | // The width of User-defined signals. Usused but set to 1, trimmed by synthesis. 29 | `define C_NASTIL_USER_WIDTH 1 30 | 31 | // The number of address bits on the DFI interface. This is the number of 32 | // address bits on the DRAM device. Generall A0-A15. 33 | `define C_DFI_ADDR_WIDTH 16 34 | 35 | // The number of bank bits on the DFI interface. This is the number of bank pins 36 | // on the DRAM device. DDR3 has a fixed 8 bank configuration while DDR2 can be 37 | // either 4 or 8. 38 | `define C_DFI_BANK_WIDTH 3 39 | 40 | // The number of bits required to control the DRAMs, usually a single bit. 41 | `define C_DFI_CTRL_WIDTH 1 42 | 43 | // The number of chip select bits on the DFI interface. This is the number of 44 | // chip select pins on the DRAM bus. It is set to 2 to accomidate a dual rank 45 | // DIMM. 46 | `define C_DFI_CS_WIDTH 2 47 | 48 | // The width of the datapath on the DFI interface. This is generally twice the 49 | // DRAM data width to accomidate for DDR timing. 50 | `define C_DFI_DATA_WIDTH 128 51 | 52 | // The width of the datapath enable signals on the DFI interface. For PHYs with 53 | // an 8-bit slice, this is generally 1/16th of the DFI Data Width to provide a 54 | // single enable bit per memory data slice, but may be 1/4, 1/8, 1/32, or any 55 | // other ratio. Bit zero corresponds to the lowest segment. 56 | `define C_DFI_DATAEN_WIDTH (`C_DFI_DATA_WIDTH/16) 57 | 58 | `define C_DFI_DACS_WIDTH (`C_DFI_CS_WIDTH*`C_DFI_DATAEN_WIDTH) 59 | 60 | // The number of data mask bits on the DFI interface. One per 8 bits of data. 61 | `define C_DFI_DM_WIDTH (`C_DFI_DATA_WIDTH/8) 62 | 63 | // The width of the alert signal on the DFI interface. Typically the PHY would 64 | // drive an alert signal per slice and the alert is typically 1-bit. 65 | `define C_DFI_ALERT_WIDTH 1 66 | 67 | // The width of the error signal on the DFI interface. 68 | `define C_DFI_ERR_WIDTH 1 69 | 70 | `define C_DFI_FREQ_RATIO 4 71 | 72 | // JESD79-3F pg. 33 73 | // CS' RAS' CAS' WE' 74 | `define CMD_MRS 4'b0000 // Mode Register Set 75 | `define CMD_REF 4'b0001 // Refresh 76 | `define CMD_SRE 4'b0001 // Self Refresh Entry 77 | `define CMD_SRX 4'b0000 // Self Refresh Exit 78 | `define CMD_PRE 4'b0010 // Single Bank Precharge 79 | `define CMD_PREA 4'b0011 // Precharge all Banks 80 | `define CMD_ACT 4'b0000 // Bank Activate 81 | `define CMD_WR 4'b0100 // Write (Fixed BL8 or BC4) 82 | `define CMD_WRS4 4'b0100 // Write (BC4, on the Fly) 83 | `define CMD_WRS8 4'b0100 // Write (BL8, on the Fly) 84 | `define CMD_WRA 4'b0100 // Write with Auto Precharge (Fixed BL8 or BC4) 85 | `define CMD_WRAS4 4'b0100 // Write with Auto Precharge (BC4, on the Fly) 86 | `define CMD_WRAS8 4'b0100 // Write with Auto Precharge (BL8, on the Fly) 87 | `define CMD_RD 4'b0101 // Read (Fixed BL8 or BC4) 88 | `define CMD_RDS4 4'b0101 // Read (BC4, on the Fly) 89 | `define CMD_RDS8 4'b0101 // Read (BL8, on the Fly) 90 | `define CMD_RDA 4'b0101 // Read with Auto Precharge (Fixed BL8 or BC4) 91 | `define CMD_RDAS4 4'b0101 // Read with Auto Precharge (BC4, on the Fly) 92 | `define CMD_RDAS8 4'b0101 // Read with Auto Precharge (BL8, on the Fly) 93 | `define CMD_NOP 4'b0111 // No Operation 94 | `define CMD_DES 4'b1000 // Device Deselected 95 | `define CMD_PDE 4'b0000 // Power Down Entry 96 | `define CMD_PDX 4'b0000 // Power Down Exit 97 | `define CMD_ZQCL 4'b0000 // ZQ Calibration Long 98 | `define CMD_ZQCS 4'b0000 // ZQ Calibration Short 99 | 100 | `define den1024Mb 101 | `define sg25E 102 | `define x8 103 | `define SODIMM 104 | `define DEBUG 105 | `define DUAL_RANK 106 | -------------------------------------------------------------------------------- /test/cxx/vip_nasti_channel.h: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #ifndef VIP_NASTI_CHANNEL_H 6 | #define VIP_NASTI_CHANNEL_H 7 | 8 | #include "systemc.h" 9 | 10 | #include "Vtop.h" 11 | 12 | #include "vip_nasti_if.h" 13 | 14 | class vip_nasti_channel : public vip_nasti_if, public sc_channel { 15 | 16 | public: 17 | 18 | sc_out aw_id; 19 | sc_out aw_addr; 20 | sc_out aw_len; 21 | sc_out aw_size; 22 | sc_out aw_burst; 23 | sc_out aw_lock; 24 | sc_out aw_cache; 25 | sc_out aw_prot; 26 | sc_out aw_qos; 27 | sc_out aw_region; 28 | sc_out aw_user; 29 | sc_out aw_valid; 30 | sc_in aw_ready; 31 | 32 | sc_out w_data; 33 | sc_out w_strb; 34 | sc_out w_last; 35 | sc_out w_user; 36 | sc_out w_valid; 37 | sc_in w_ready; 38 | 39 | sc_in b_id; 40 | sc_in b_resp; 41 | sc_in b_user; 42 | sc_in b_valid; 43 | sc_out b_ready; 44 | 45 | sc_out ar_id; 46 | sc_out ar_addr; 47 | sc_out ar_len; 48 | sc_out ar_size; 49 | sc_out ar_burst; 50 | sc_out ar_lock; 51 | sc_out ar_cache; 52 | sc_out ar_prot; 53 | sc_out ar_qos; 54 | sc_out ar_region; 55 | sc_out ar_user; 56 | sc_out ar_valid; 57 | sc_in ar_ready; 58 | 59 | sc_in r_id; 60 | sc_in r_resp; 61 | sc_in r_last; 62 | sc_in r_user; 63 | sc_in r_valid; 64 | sc_out r_ready; 65 | sc_in r_data; 66 | 67 | vip_nasti_channel (sc_module_name name) : 68 | sc_channel(name), 69 | ar_id("ar_id"), 70 | ar_addr("ar_addr"), 71 | ar_len("ar_len"), 72 | ar_size("ar_size"), 73 | ar_burst("ar_burst"), 74 | ar_lock("ar_lock"), 75 | ar_cache("ar_cache"), 76 | ar_prot("ar_prot"), 77 | ar_qos("ar_qos"), 78 | ar_region("ar_region"), 79 | ar_user("ar_user"), 80 | ar_valid("ar_valid"), 81 | ar_ready("ar_ready") 82 | { } 83 | 84 | virtual bool burstRead( uint64_t id, uint64_t addr, uint64_t len ); 85 | virtual bool burstWrite( uint64_t id, uint64_t addr, uint64_t len, sc_bv<8> *data ); 86 | virtual void slaveBind( Vtop* ); 87 | 88 | private: 89 | 90 | sc_signal aw_id_s; 91 | sc_signal aw_addr_s; 92 | sc_signal aw_len_s; 93 | sc_signal aw_size_s; 94 | sc_signal aw_burst_s; 95 | sc_signal aw_lock_s; 96 | sc_signal aw_cache_s; 97 | sc_signal aw_prot_s; 98 | sc_signal aw_qos_s; 99 | sc_signal aw_region_s; 100 | sc_signal aw_user_s; 101 | sc_signal aw_valid_s; 102 | sc_signal aw_ready_s; 103 | sc_signal w_data_s; 104 | sc_signal w_strb_s; 105 | sc_signal w_last_s; 106 | sc_signal w_user_s; 107 | sc_signal w_valid_s; 108 | sc_signal w_ready_s; 109 | sc_signal b_id_s; 110 | sc_signal b_resp_s; 111 | sc_signal b_user_s; 112 | sc_signal b_valid_s; 113 | sc_signal b_ready_s; 114 | sc_signal ar_id_s; 115 | sc_signal ar_addr_s; 116 | sc_signal ar_len_s; 117 | sc_signal ar_size_s; 118 | sc_signal ar_burst_s; 119 | sc_signal ar_lock_s; 120 | sc_signal ar_cache_s; 121 | sc_signal ar_prot_s; 122 | sc_signal ar_qos_s; 123 | sc_signal ar_region_s; 124 | sc_signal ar_user_s; 125 | sc_signal ar_valid_s; 126 | sc_signal ar_ready_s; 127 | sc_signal r_id_s; 128 | sc_signal r_resp_s; 129 | sc_signal r_last_s; 130 | sc_signal r_user_s; 131 | sc_signal r_valid_s; 132 | sc_signal r_ready_s; 133 | sc_signal r_data_s; 134 | 135 | }; 136 | 137 | #endif /* VIP_NASTI_CHANNEL_H */ 138 | -------------------------------------------------------------------------------- /test/cxx/vip_dfi_channel.cpp: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #include "vip_dfi_channel.h" 6 | 7 | void vip_dfi_channel::read() { 8 | 9 | } 10 | 11 | void vip_dfi_channel::write( sc_bv<8>* ) { 12 | 13 | } 14 | 15 | void vip_dfi_channel::masterBind(Vtop* dut) { 16 | 17 | dut->dfi_bank(dfi_bank); 18 | dut->dfi_ras_n(dfi_ras_n); 19 | dut->dfi_cas_n(dfi_cas_n); 20 | dut->dfi_we_n(dfi_we_n); 21 | dut->dfi_wrdata_en(dfi_wrdata_en); 22 | dut->dfi_rddata_en(dfi_rddata_en); 23 | dut->dfi_rddata_valid(dfi_rddata_valid); 24 | dut->dfi_ctrlupd_req(dfi_ctrlupd_req); 25 | dut->dfi_ctrlupd_ack(dfi_ctrlupd_ack); 26 | dut->dfi_phyupd_req(dfi_phyupd_req); 27 | dut->dfi_phyupd_type(dfi_phyupd_type); 28 | dut->dfi_phyupd_ack(dfi_phyupd_ack); 29 | dut->dfi_data_byte_disable(dfi_data_byte_disable); 30 | dut->dfi_dram_clk_disable(dfi_dram_clk_disable); 31 | dut->dfi_freq_ratio(dfi_freq_ratio); 32 | dut->dfi_init_start(dfi_init_start); 33 | dut->dfi_init_complete(dfi_init_complete); 34 | dut->dfi_parity_in(dfi_parity_in); 35 | dut->dfi_alert_n(dfi_alert_n); 36 | dut->dfi_rdlvl_req(dfi_rdlvl_req); 37 | dut->dfi_phy_rdlvl_cs_n(dfi_phy_rdlvl_cs_n); 38 | dut->dfi_rdlvl_en(dfi_rdlvl_en); 39 | dut->dfi_rdlvl_resp(dfi_rdlvl_resp); 40 | dut->dfi_rdlvl_gate_req(dfi_rdlvl_gate_req); 41 | dut->dfi_phy_rdlvl_gate_cs_n(dfi_phy_rdlvl_gate_cs_n); 42 | dut->dfi_rdlvl_gate_en(dfi_rdlvl_gate_en); 43 | dut->dfi_wrlvl_req(dfi_wrlvl_req); 44 | dut->dfi_phy_wrlvl_cs_n(dfi_phy_wrlvl_cs_n); 45 | dut->dfi_wrlvl_en(dfi_wrlvl_en); 46 | dut->dfi_wrlvl_strobe(dfi_wrlvl_strobe); 47 | dut->dfi_wrlvl_resp(dfi_wrlvl_resp); 48 | dut->dfi_lvl_periodic(dfi_lvl_periodic); 49 | dut->dfi_phylvl_req_cs_n(dfi_phylvl_req_cs_n); 50 | dut->dfi_phylvl_ack_cs_n(dfi_phylvl_ack_cs_n); 51 | dut->dfi_lp_ctrl_req(dfi_lp_ctrl_req); 52 | dut->dfi_lp_data_req(dfi_lp_data_req); 53 | dut->dfi_lp_wakeup(dfi_lp_wakeup); 54 | dut->dfi_lp_ack(dfi_lp_ack); 55 | dut->dfi_address(dfi_address); 56 | dut->dfi_cs_n(dfi_cs_n); 57 | dut->dfi_cke(dfi_cke); 58 | dut->dfi_odt(dfi_odt); 59 | dut->dfi_reset_n(dfi_reset_n); 60 | dut->dfi_wrdata_mask(dfi_wrdata_mask); 61 | dut->dfi_error(dfi_error); 62 | dut->dfi_error_info(dfi_error_info); 63 | dut->dfi_wrdata(dfi_wrdata); 64 | dut->dfi_wrdata_cs_n(dfi_wrdata_cs_n); 65 | dut->dfi_rddata(dfi_rddata); 66 | dut->dfi_rddata_cs_n(dfi_rddata_cs_n); 67 | 68 | // dfi_bank(dfi_bank_s); 69 | // dfi_ras_n(dfi_ras_n_s); 70 | // dfi_cas_n(dfi_cas_n_s); 71 | // dfi_we_n(dfi_we_n_s); 72 | // dfi_wrdata_en(dfi_wrdata_en_s); 73 | // dfi_rddata_en(dfi_rddata_en_s); 74 | // dfi_rddata_valid(dfi_rddata_valid_s); 75 | // dfi_ctrlupd_req(dfi_ctrlupd_req_s); 76 | // dfi_ctrlupd_ack(dfi_ctrlupd_ack_s); 77 | // dfi_phyupd_req(dfi_phyupd_req_s); 78 | // dfi_phyupd_type(dfi_phyupd_type_s); 79 | // dfi_phyupd_ack(dfi_phyupd_ack_s); 80 | // dfi_data_byte_disable(dfi_data_byte_disable_s); 81 | // dfi_dram_clk_disable(dfi_dram_clk_disable_s); 82 | // dfi_freq_ratio(dfi_freq_ratio_s); 83 | // dfi_init_start(dfi_init_start_s); 84 | // dfi_init_complete(dfi_init_complete_s); 85 | // dfi_parity_in(dfi_parity_in_s); 86 | // dfi_alert_n(dfi_alert_n_s); 87 | // dfi_rdlvl_req(dfi_rdlvl_req_s); 88 | // dfi_phy_rdlvl_cs_n(dfi_phy_rdlvl_cs_n_s); 89 | // dfi_rdlvl_en(dfi_rdlvl_en_s); 90 | // dfi_rdlvl_resp(dfi_rdlvl_resp_s); 91 | // dfi_rdlvl_gate_req(dfi_rdlvl_gate_req_s); 92 | // dfi_phy_rdlvl_gate_cs_n(dfi_phy_rdlvl_gate_cs_n_s); 93 | // dfi_rdlvl_gate_en(dfi_rdlvl_gate_en_s); 94 | // dfi_wrlvl_req(dfi_wrlvl_req_s); 95 | // dfi_phy_wrlvl_cs_n(dfi_phy_wrlvl_cs_n_s); 96 | // dfi_wrlvl_en(dfi_wrlvl_en_s); 97 | // dfi_wrlvl_strobe(dfi_wrlvl_strobe_s); 98 | // dfi_wrlvl_resp(dfi_wrlvl_resp_s); 99 | // dfi_lvl_periodic(dfi_lvl_periodic_s); 100 | // dfi_phylvl_req_cs_n(dfi_phylvl_req_cs_n_s); 101 | // dfi_phylvl_ack_cs_n(dfi_phylvl_ack_cs_n_s); 102 | // dfi_lp_ctrl_req(dfi_lp_ctrl_req_s); 103 | // dfi_lp_data_req(dfi_lp_data_req_s); 104 | // dfi_lp_wakeup(dfi_lp_wakeup_s); 105 | // dfi_lp_ack(dfi_lp_ack_s); 106 | // dfi_address(dfi_address_s); 107 | // dfi_cs_n(dfi_cs_n_s); 108 | // dfi_cke(dfi_cke_s); 109 | // dfi_odt(dfi_odt_s); 110 | // dfi_reset_n(dfi_reset_n_s); 111 | // dfi_wrdata_mask(dfi_wrdata_mask_s); 112 | // dfi_error(dfi_error_s); 113 | // dfi_error_info(dfi_error_info_s); 114 | // dfi_wrdata(dfi_wrdata_s); 115 | // dfi_wrdata_cs_n(dfi_wrdata_cs_n_s); 116 | // dfi_rddata(dfi_rddata_s); 117 | // dfi_rddata_cs_n(dfi_rddata_cs_n_s); 118 | } 119 | -------------------------------------------------------------------------------- /rtl/main_control.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | module main_control ( 8 | input core_clk , 9 | input core_arstn , 10 | // 11 | input r_empty , 12 | // 13 | output logic ddr_init_start, 14 | input ddr_init_done , 15 | output logic cali_start , 16 | input cali_done , 17 | output logic tran_start , 18 | input tran_done , 19 | // 20 | config_if.slave s_cfg , 21 | output logic [1:0] sel , 22 | dfi_if.master main_dfi 23 | ); 24 | 25 | enum logic[5:0] {RESET, INIT_DFI, INIT_DDR, DO_CALI, IDLE, XXXX = 'x} state, next; 26 | 27 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_state 28 | if(~core_arstn) begin 29 | state <= RESET; 30 | end else begin 31 | state <= next; 32 | end 33 | end 34 | 35 | always_comb begin : proc_next 36 | next = XXXX; 37 | unique case (state) 38 | RESET : 39 | next = INIT_DFI; 40 | INIT_DFI : 41 | if(1'b1 == main_dfi.dfi_init_complete) begin 42 | next = INIT_DDR; 43 | end else begin 44 | next = INIT_DFI; 45 | end 46 | INIT_DDR : 47 | if(1'b1 == ddr_init_done) begin 48 | next = IDLE; 49 | end else begin 50 | next = INIT_DDR; 51 | end 52 | DO_CALI : 53 | if(1'b1 == cali_done) begin 54 | next = IDLE; 55 | end else begin 56 | next = INIT_DDR; 57 | end 58 | IDLE : 59 | if(1'b1 == main_dfi.dfi_rdlvl_req) begin 60 | next = DO_CALI; 61 | end else if(1'b1 == main_dfi.dfi_wrlvl_req) begin 62 | next = DO_CALI; 63 | end else if(1'b1 == main_dfi.dfi_phyupd_req) begin 64 | next = DO_CALI; 65 | end else begin 66 | next = IDLE; 67 | end 68 | endcase 69 | end 70 | 71 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_output 72 | if(~core_arstn) begin 73 | main_dfi.dfi_data_byte_disable <= '0; // don't disable any byte lanes 74 | main_dfi.dfi_dram_clk_disable <= '0; 75 | main_dfi.dfi_freq_ratio <= 2'b11; // 1:4matched frequency 76 | main_dfi.dfi_init_start <= '0; 77 | ddr_init_start <= '0; 78 | tran_start <= '0; 79 | cali_start <= '0; 80 | sel <= '0; 81 | main_dfi.dfi_ctrlupd_req <= '0; 82 | main_dfi.dfi_phyupd_ack <= '0; 83 | main_dfi.dfi_lp_ctrl_req <= '0; 84 | main_dfi.dfi_lp_data_req <= '0; 85 | main_dfi.dfi_lp_wakeup <= '0; 86 | end else begin 87 | unique case (next) 88 | INIT_DFI : begin 89 | main_dfi.dfi_data_byte_disable <= '0; // don't disable any byte lanes 90 | main_dfi.dfi_dram_clk_disable <= '0; 91 | main_dfi.dfi_freq_ratio <= 2'b11; // 1:4matched frequency 92 | main_dfi.dfi_init_start <= 1; 93 | ddr_init_start <= 0; 94 | sel <= 2'b00; 95 | end 96 | INIT_DDR : begin 97 | main_dfi.dfi_data_byte_disable <= '0; // don't disable any byte lanes 98 | main_dfi.dfi_dram_clk_disable <= '0; 99 | main_dfi.dfi_freq_ratio <= 2'b11; // 1:4matched frequency 100 | main_dfi.dfi_init_start <= 1; 101 | ddr_init_start <= 1; 102 | sel <= 2'b01; 103 | end 104 | IDLE : begin 105 | main_dfi.dfi_data_byte_disable <= '0; // don't disable any byte lanes 106 | main_dfi.dfi_dram_clk_disable <= '0; 107 | main_dfi.dfi_freq_ratio <= 2'b11; // 1:4matched frequency 108 | main_dfi.dfi_init_start <= 1; 109 | ddr_init_start <= 1; 110 | sel <= 2'b11; 111 | end 112 | endcase 113 | end 114 | end 115 | 116 | endmodule // main_control 117 | -------------------------------------------------------------------------------- /test/cxx/vip_dfi_channel.h: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | #ifndef VIP_DFI_CHANNEL_H 6 | #define VIP_DFI_CHANNEL_H 7 | 8 | #include "systemc.h" 9 | 10 | #include "Vtop.h" 11 | 12 | #include "vip_dfi_if.h" 13 | 14 | class vip_dfi_channel : public vip_dfi_if, public sc_channel { 15 | 16 | public: 17 | 18 | sc_signal dfi_bank; 19 | sc_signal dfi_ras_n; 20 | sc_signal dfi_cas_n; 21 | sc_signal dfi_we_n; 22 | sc_signal dfi_wrdata_en; 23 | sc_signal dfi_rddata_en; 24 | sc_signal dfi_rddata_valid; 25 | sc_signal dfi_ctrlupd_req; 26 | sc_signal dfi_ctrlupd_ack; 27 | sc_signal dfi_phyupd_req; 28 | sc_signal dfi_phyupd_type; 29 | sc_signal dfi_phyupd_ack; 30 | sc_signal dfi_data_byte_disable; 31 | sc_signal dfi_dram_clk_disable; 32 | sc_signal dfi_freq_ratio; 33 | sc_signal dfi_init_start; 34 | sc_signal dfi_init_complete; 35 | sc_signal dfi_parity_in; 36 | sc_signal dfi_alert_n; 37 | sc_signal dfi_rdlvl_req; 38 | sc_signal dfi_phy_rdlvl_cs_n; 39 | sc_signal dfi_rdlvl_en; 40 | sc_signal dfi_rdlvl_resp; 41 | sc_signal dfi_rdlvl_gate_req; 42 | sc_signal dfi_phy_rdlvl_gate_cs_n; 43 | sc_signal dfi_rdlvl_gate_en; 44 | sc_signal dfi_wrlvl_req; 45 | sc_signal dfi_phy_wrlvl_cs_n; 46 | sc_signal dfi_wrlvl_en; 47 | sc_signal dfi_wrlvl_strobe; 48 | sc_signal dfi_wrlvl_resp; 49 | sc_signal dfi_lvl_periodic; 50 | sc_signal dfi_phylvl_req_cs_n; 51 | sc_signal dfi_phylvl_ack_cs_n; 52 | sc_signal dfi_lp_ctrl_req; 53 | sc_signal dfi_lp_data_req; 54 | sc_signal dfi_lp_wakeup; 55 | sc_signal dfi_lp_ack; 56 | sc_signal dfi_address; 57 | sc_signal dfi_cs_n; 58 | sc_signal dfi_cke; 59 | sc_signal dfi_odt; 60 | sc_signal dfi_reset_n; 61 | sc_signal dfi_wrdata_mask; 62 | sc_signal dfi_error; 63 | sc_signal dfi_error_info; 64 | sc_signal > dfi_wrdata; 65 | sc_signal > dfi_wrdata_cs_n; 66 | sc_signal > dfi_rddata; 67 | sc_signal > dfi_rddata_cs_n; 68 | 69 | vip_dfi_channel (sc_module_name name) : 70 | sc_channel(name) { 71 | dfi_rddata_valid = 0; 72 | dfi_ctrlupd_ack = 0; 73 | dfi_phyupd_req = 0; 74 | dfi_phyupd_type = 0; 75 | dfi_init_complete = 0; 76 | dfi_alert_n = 0; 77 | dfi_rdlvl_req = 0; 78 | dfi_phy_rdlvl_cs_n = 0; 79 | dfi_rdlvl_resp = 0; 80 | dfi_rdlvl_gate_req = 0; 81 | dfi_phy_rdlvl_gate_cs_n = 0; 82 | dfi_wrlvl_req = 0; 83 | dfi_phy_wrlvl_cs_n = 0; 84 | dfi_wrlvl_resp = 0; 85 | dfi_phylvl_req_cs_n = 0; 86 | dfi_lp_ack = 0; 87 | dfi_error = 0; 88 | dfi_error_info = 0; 89 | dfi_rddata = 0; 90 | } 91 | 92 | virtual void read(); 93 | virtual void write( sc_bv<8>* ); 94 | virtual void masterBind(Vtop*); 95 | 96 | private: 97 | 98 | sc_signal dfi_bank_s; 99 | sc_signal dfi_ras_n_s; 100 | sc_signal dfi_cas_n_s; 101 | sc_signal dfi_we_n_s; 102 | sc_signal dfi_wrdata_en_s; 103 | sc_signal dfi_rddata_en_s; 104 | sc_signal dfi_rddata_valid_s; 105 | sc_signal dfi_ctrlupd_req_s; 106 | sc_signal dfi_ctrlupd_ack_s; 107 | sc_signal dfi_phyupd_req_s; 108 | sc_signal dfi_phyupd_type_s; 109 | sc_signal dfi_phyupd_ack_s; 110 | sc_signal dfi_data_byte_disable_s; 111 | sc_signal dfi_dram_clk_disable_s; 112 | sc_signal dfi_freq_ratio_s; 113 | sc_signal dfi_init_start_s; 114 | sc_signal dfi_init_complete_s; 115 | sc_signal dfi_parity_in_s; 116 | sc_signal dfi_alert_n_s; 117 | sc_signal dfi_rdlvl_req_s; 118 | sc_signal dfi_phy_rdlvl_cs_n_s; 119 | sc_signal dfi_rdlvl_en_s; 120 | sc_signal dfi_rdlvl_resp_s; 121 | sc_signal dfi_rdlvl_gate_req_s; 122 | sc_signal dfi_phy_rdlvl_gate_cs_n_s; 123 | sc_signal dfi_rdlvl_gate_en_s; 124 | sc_signal dfi_wrlvl_req_s; 125 | sc_signal dfi_phy_wrlvl_cs_n_s; 126 | sc_signal dfi_wrlvl_en_s; 127 | sc_signal dfi_wrlvl_strobe_s; 128 | sc_signal dfi_wrlvl_resp_s; 129 | sc_signal dfi_lvl_periodic_s; 130 | sc_signal dfi_phylvl_req_cs_n_s; 131 | sc_signal dfi_phylvl_ack_cs_n_s; 132 | sc_signal dfi_lp_ctrl_req_s; 133 | sc_signal dfi_lp_data_req_s; 134 | sc_signal dfi_lp_wakeup_s; 135 | sc_signal dfi_lp_ack_s; 136 | sc_signal dfi_address_s; 137 | sc_signal dfi_cs_n_s; 138 | sc_signal dfi_cke_s; 139 | sc_signal dfi_odt_s; 140 | sc_signal dfi_reset_n_s; 141 | sc_signal dfi_wrdata_mask_s; 142 | sc_signal dfi_error_s; 143 | sc_signal dfi_error_info_s; 144 | sc_signal< sc_bv<128> > dfi_wrdata_s; 145 | sc_signal< sc_bv<128> > dfi_wrdata_cs_n_s; 146 | sc_signal< sc_bv<128> > dfi_rddata_s; 147 | sc_signal< sc_bv<128> > dfi_rddata_cs_n_s; 148 | 149 | }; 150 | 151 | #endif /* VIP_DFI_CHANNEL_H */ 152 | -------------------------------------------------------------------------------- /rtl/nasti_frontend.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This module presents a NASTI slave interface to transaction FIFOs and 3 | * facilitates a clock domain cross. 4 | */ 5 | 6 | `include "timescale.svh" 7 | `include "defines.svh" 8 | `include "enums.svh" 9 | `include "functions.svh" 10 | `include "structs.svh" 11 | 12 | module nasti_frontend #( 13 | C_NASTI_ID_WIDTH = 0, 14 | C_NASTI_ADDR_WIDTH = 0, 15 | C_NASTI_DATA_WIDTH = 0, 16 | C_NASTI_USER_WIDTH = 0, 17 | C_FIFO_DEPTH = 4, // depth of the NASTI FIFOs 18 | C_MAX_PENDING = 5 19 | ) ( 20 | // clocking and reset 21 | input core_clk , 22 | input core_arstn , 23 | // NASTI Interface 24 | input s_nasti_clk , 25 | input s_nasti_aresetn, 26 | nasti_if.slave s_nasti , 27 | // read address and control fifo 28 | output ar_trans ar_rdata , 29 | output ar_rempty , 30 | input ar_rden , 31 | // write address and control fifo 32 | output aw_trans aw_rdata , 33 | output aw_rempty , 34 | input aw_rden , 35 | // write data fifo 36 | output w_trans w_rdata , 37 | output w_rempty , 38 | input w_rden , 39 | // read data fifo 40 | input r_trans r_wdata , 41 | output r_wfull , 42 | input r_wren , 43 | // write response fifo 44 | input b_trans b_wdata , 45 | output b_wfull , 46 | input b_wren 47 | ); 48 | 49 | // write addresss and control 50 | aw_trans wdata_aw; 51 | assign wdata_aw = '{ 52 | aw_id : s_nasti.aw_id, 53 | aw_addr : s_nasti.aw_addr, 54 | aw_len : s_nasti.aw_len, 55 | aw_size : s_nasti.aw_size, 56 | aw_burst : s_nasti.aw_burst, 57 | aw_user : s_nasti.aw_user 58 | }; 59 | 60 | logic wfull_aw; 61 | assign s_nasti.aw_ready = ~wfull_aw; 62 | 63 | afifo #( 64 | .C_DATA_WIDTH($bits(aw_trans)), 65 | .C_ADDR_WIDTH(C_FIFO_DEPTH ) 66 | ) i_afifo_aw ( 67 | .wdata (wdata_aw ), 68 | .wfull (wfull_aw ), 69 | .wren (s_nasti.aw_valid), 70 | .wclk (s_nasti_clk ), 71 | .wrstn (s_nasti_aresetn ), 72 | .rdata (aw_rdata ), 73 | .rempty(aw_rempty ), 74 | .rden (aw_rden ), 75 | .rclk (core_clk ), 76 | .rrstn (core_arstn ) 77 | ); 78 | 79 | // write data 80 | w_trans w_wdata; 81 | assign w_wdata = '{ 82 | w_data : s_nasti.w_data, 83 | w_strb : s_nasti.w_strb, 84 | w_last : s_nasti.w_last, 85 | w_user : s_nasti.w_user 86 | }; 87 | 88 | logic w_wfull; 89 | assign s_nasti.w_ready = ~w_wfull; 90 | 91 | afifo #( 92 | .C_DATA_WIDTH($bits(w_trans)), 93 | .C_ADDR_WIDTH(C_FIFO_DEPTH ) 94 | ) i_afifo_w ( 95 | .wdata (w_wdata ), 96 | .wfull (w_wfull ), 97 | .wren (s_nasti.w_valid), 98 | .wclk (s_nasti_clk ), 99 | .wrstn (s_nasti_aresetn), 100 | .rdata (w_rdata ), 101 | .rempty(w_rempty ), 102 | .rden (w_rden ), 103 | .rclk (core_clk ), 104 | .rrstn (core_arstn ) 105 | ); 106 | 107 | // write response 108 | b_trans b_rdata; 109 | 110 | assign s_nasti.b_id = b_rdata.b_id; 111 | assign s_nasti.b_resp = b_rdata.b_resp; 112 | assign s_nasti.b_user = b_rdata.b_user; 113 | 114 | logic b_rempty; 115 | assign s_nasti.b_valid = ~b_rempty; 116 | 117 | afifo #( 118 | .C_DATA_WIDTH($bits(b_trans)), 119 | .C_ADDR_WIDTH(C_FIFO_DEPTH ) 120 | ) i_afifo_b ( 121 | .wdata (b_wdata ), 122 | .wfull (b_wfull ), 123 | .wren (b_wren ), 124 | .wclk (core_clk ), 125 | .wrstn (core_arstn ), 126 | .rdata (b_rdata ), 127 | .rempty(b_rempty ), 128 | .rden (s_nasti.b_ready), 129 | .rclk (s_nasti_clk ), 130 | .rrstn (s_nasti_aresetn) 131 | ); 132 | 133 | // read address and control 134 | ar_trans wdata_ar; 135 | assign wdata_ar = '{ 136 | ar_id : s_nasti.ar_id, 137 | ar_addr : s_nasti.ar_addr, 138 | ar_len : s_nasti.ar_len, 139 | ar_size : s_nasti.ar_size, 140 | ar_burst : s_nasti.ar_burst, 141 | ar_user : s_nasti.ar_user 142 | }; 143 | 144 | logic wfull_ar; 145 | assign s_nasti.ar_ready = ~wfull_ar; 146 | 147 | afifo #( 148 | .C_DATA_WIDTH($bits(ar_trans)), 149 | .C_ADDR_WIDTH(C_FIFO_DEPTH ) 150 | ) i_afifo_ar ( 151 | .wdata (wdata_ar ), 152 | .wfull (wfull_ar ), 153 | .wren (s_nasti.ar_valid), 154 | .wclk (s_nasti_clk ), 155 | .wrstn (s_nasti_aresetn ), 156 | .rdata (ar_rdata ), 157 | .rempty(ar_rempty ), 158 | .rden (ar_rden ), 159 | .rclk (core_clk ), 160 | .rrstn (core_arstn ) 161 | ); 162 | 163 | // read data and response 164 | r_trans r_rdata; 165 | 166 | assign s_nasti.r_id = r_rdata.r_id; 167 | assign s_nasti.r_data = r_rdata.r_data; 168 | assign s_nasti.r_last = r_rdata.r_last; 169 | assign s_nasti.r_resp = r_rdata.r_resp; 170 | assign s_nasti.r_user = r_rdata.r_user; 171 | 172 | logic r_rempty; 173 | assign s_nasti.r_valid = ~r_rempty; 174 | 175 | afifo #( 176 | .C_DATA_WIDTH($bits(r_trans)), 177 | .C_ADDR_WIDTH(C_FIFO_DEPTH ) 178 | ) i_afifo_r ( 179 | .wdata (r_wdata ), 180 | .wfull (r_wfull ), 181 | .wren (r_wren ), 182 | .wclk (core_clk ), 183 | .wrstn (core_arstn ), 184 | .rdata (r_rdata ), 185 | .rempty(r_rempty ), 186 | .rden (s_nasti.r_ready), 187 | .rclk (s_nasti_clk ), 188 | .rrstn (s_nasti_aresetn) 189 | ); 190 | 191 | endmodule // nasti_frontend 192 | -------------------------------------------------------------------------------- /rtl/nastilite_frontend.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This module is responsible for managing NASTILite communications for the 3 | * configuration registers. It is not capable of handling outstanding 4 | * transactions. The module waits till write address and data are both 5 | * available. 6 | */ 7 | 8 | `include "timescale.svh" 9 | 10 | module nastilite_frontend #( 11 | C_NASTI_ADDR_WIDTH = 5 , // decides width of register addressing. +3 for 64 bit, +2 for 32 bit 12 | C_NASTI_DATA_WIDTH = 64 // width of data, must be either 32 or 64 13 | ) ( 14 | // NASTILite interface 15 | input s_nastilite_clk , 16 | input s_nastilite_aresetn, 17 | nasti_if.slave s_nastilite , 18 | // configuration register outputs 19 | config_if.master m_cfg 20 | ); 21 | 22 | localparam int I_ADDR_OFFSET = (C_NASTI_DATA_WIDTH/32) + 1; 23 | 24 | logic [C_NASTI_ADDR_WIDTH-(C_NASTI_DATA_WIDTH/32):0][C_NASTI_DATA_WIDTH-1:0] cfg_reg; 25 | 26 | logic [C_NASTI_ADDR_WIDTH-1:0] aw_addr; 27 | logic [C_NASTI_ADDR_WIDTH-1:0] ar_addr; 28 | 29 | // write address and data handshake 30 | // awvalid and rvalid assertion is used to latch the address after which 31 | // ready is asserted in the next clock cycle. 32 | always_ff @(posedge s_nastilite_clk) begin : proc_aw_w_handshake 33 | if(~s_nastilite_aresetn) begin 34 | s_nastilite.aw_ready <= 1'b0; 35 | s_nastilite.w_ready <= 1'b0; 36 | aw_addr <= 0; 37 | end else begin 38 | if(~s_nastilite.aw_ready && ~s_nastilite.w_ready && s_nastilite.aw_valid && s_nastilite.w_valid) begin 39 | s_nastilite.aw_ready <= 1'b1; 40 | s_nastilite.w_ready <= 1'b1; 41 | aw_addr <= s_nastilite.aw_addr; 42 | end else begin 43 | s_nastilite.aw_ready <= 1'b0; 44 | s_nastilite.w_ready <= 1'b0; 45 | aw_addr <= aw_addr; 46 | end 47 | end 48 | end 49 | 50 | // implement write transactions. This happens during the clock cycle that 51 | // ready is asserted 52 | always_ff @(posedge s_nastilite_clk) begin : proc_w_data 53 | if(~s_nastilite_aresetn) begin 54 | cfg_reg <= 0; 55 | end else begin 56 | // if all signals are asserted, accept the data into the registers. else keep them. 57 | if(s_nastilite.aw_ready && s_nastilite.w_ready && s_nastilite.aw_valid && s_nastilite.w_valid) begin 58 | for (int i = 0; i < (C_NASTI_DATA_WIDTH/8)-1; i++) begin 59 | if(1'b1 == s_nastilite.w_strb[i]) begin 60 | cfg_reg[aw_addr[C_NASTI_ADDR_WIDTH-1:I_ADDR_OFFSET]][(i*8)+:8] <= s_nastilite.w_data[(i*8)+:8]; 61 | end 62 | end 63 | end else begin 64 | cfg_reg <= cfg_reg; 65 | end 66 | end 67 | end 68 | 69 | // write response handshake 70 | always_ff @(posedge s_nastilite_clk) begin : proc_b_handshake 71 | if(~s_nastilite_aresetn) begin 72 | s_nastilite.b_valid <= 1'b0; 73 | s_nastilite.b_resp <= 2'b00; // default response of OKAY. No error handling. 74 | end else begin 75 | s_nastilite.b_resp <= 2'b00; // default response of OKAY. No error handling. 76 | if(~s_nastilite.b_valid && s_nastilite.aw_ready && s_nastilite.w_ready && s_nastilite.aw_valid && s_nastilite.w_valid) begin 77 | s_nastilite.b_valid <= 1'b1; 78 | end else begin 79 | // wait till bready is asserted before deasserting bvalid 80 | if(s_nastilite.b_valid && s_nastilite.b_ready) begin 81 | s_nastilite.b_valid <= 1'b0; 82 | end 83 | end 84 | 85 | end 86 | end 87 | 88 | // read address handshake 89 | always_ff @(posedge s_nastilite_clk) begin : proc_ar_handshake 90 | if(~s_nastilite_aresetn) begin 91 | s_nastilite.ar_ready <= 1'b0; 92 | ar_addr <= 0; 93 | end else begin 94 | if(~s_nastilite.ar_ready && s_nastilite.ar_valid) begin 95 | s_nastilite.ar_ready <= 1'b1; 96 | ar_addr <= s_nastilite.ar_addr; 97 | end else begin 98 | s_nastilite.ar_ready <= 1'b0; 99 | ar_addr <= 0; 100 | end 101 | end 102 | end 103 | 104 | // read response handshake 105 | always_ff @(posedge s_nastilite_clk) begin : proc_r_handshake 106 | if(~s_nastilite_aresetn) begin 107 | s_nastilite.r_valid <= 1'b0; 108 | s_nastilite.r_resp <= 2'b00; // OKAY resp. 109 | s_nastilite.r_data <= 0; 110 | end else begin 111 | s_nastilite.r_resp <= 2'b00; // OKAY resp. 112 | if(~s_nastilite.r_valid && s_nastilite.ar_valid && s_nastilite.ar_ready) begin 113 | s_nastilite.r_valid <= 1'b1; 114 | s_nastilite.r_data <= cfg_reg[aw_addr[C_NASTI_ADDR_WIDTH-1:I_ADDR_OFFSET]]; 115 | end else begin 116 | // wait till rready is asserted before deasserting bvalid 117 | if(s_nastilite.r_valid && s_nastilite.r_ready) begin 118 | s_nastilite.r_valid <= 1'b0; 119 | s_nastilite.r_data <= 0; 120 | end 121 | end 122 | end 123 | end 124 | 125 | always_comb begin : proc_mapping 126 | m_cfg.msr0 = 13'b0_1001_0010_0000; 127 | m_cfg.msr1 = 13'b1_0000_0100_1100; 128 | m_cfg.msr2 = 13'b0_0000_0000_1000; 129 | m_cfg.msr3 = 13'b0_0000_0000_0000; 130 | m_cfg.tAL = cfg_reg[0][0 +: 4]; 131 | m_cfg.tBURST = cfg_reg[0][1 +: 4]; 132 | m_cfg.tCCD = cfg_reg[0][2 +: 4]; 133 | m_cfg.tCL = cfg_reg[0][3 +: 4]; 134 | m_cfg.tCMD = cfg_reg[0][4 +: 4]; 135 | m_cfg.tCWD = cfg_reg[0][5 +: 4]; 136 | m_cfg.tCWL = cfg_reg[0][6 +: 4]; 137 | m_cfg.tFAW = cfg_reg[0][7 +: 4]; 138 | m_cfg.tMOD = '1; 139 | m_cfg.tMRD = '0; 140 | m_cfg.tOST = '1; 141 | m_cfg.tphy_rdcslat = '1; 142 | m_cfg.tphy_rdlat = '1; 143 | m_cfg.tRAS = '1; 144 | m_cfg.tRC = '1; 145 | m_cfg.tRCD = '1; 146 | m_cfg.trdata_en = '1; 147 | m_cfg.tRFC = '1; 148 | m_cfg.tRP = '1; 149 | m_cfg.tRRD = '1; 150 | m_cfg.tRTP = '1; 151 | m_cfg.tRTRS = '1; 152 | m_cfg.tWR = '1; 153 | m_cfg.tWTR = '1; 154 | m_cfg.tZQinit = '1; 155 | m_cfg.tXPR = '1; 156 | end 157 | 158 | endmodule //nastilite_frontend 159 | -------------------------------------------------------------------------------- /rtl/dfi_if.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * Parameterised DFI interface definition. 3 | */ 4 | 5 | `include "timescale.svh" 6 | 7 | interface dfi_if #( 8 | C_DFI_FREQ_RATIO = 0, 9 | C_DFI_ADDR_WIDTH = 0, 10 | C_DFI_BANK_WIDTH = 0, 11 | C_DFI_CTRL_WIDTH = 0, 12 | C_DFI_CS_WIDTH = 0, 13 | C_DFI_DATAEN_WIDTH = 0, 14 | C_DFI_DATA_WIDTH = 0, 15 | C_DFI_WRDACS_WIDTH = 0, 16 | C_DFI_DM_WIDTH = 0, 17 | C_DFI_ALERT_WIDTH = 0, 18 | C_DFI_ERR_WIDTH = 0 19 | ); 20 | 21 | // DFI control interface 22 | logic [C_DFI_ADDR_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_address; 23 | logic [C_DFI_BANK_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_bank ; 24 | logic [C_DFI_CTRL_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_ras_n ; 25 | logic [C_DFI_CTRL_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_cas_n ; 26 | logic [C_DFI_CTRL_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_we_n ; 27 | logic [ C_DFI_CS_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_cs_n ; 28 | logic [ C_DFI_CS_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_cke ; 29 | logic [ C_DFI_CS_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_odt ; 30 | logic [ C_DFI_CS_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_reset_n; // ddr3 only 31 | 32 | // DFI write data interface 33 | logic [C_DFI_DATAEN_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_wrdata_en ; 34 | logic [ C_DFI_DATA_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_wrdata ; 35 | logic [C_DFI_WRDACS_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_wrdata_cs_n; 36 | logic [ C_DFI_DM_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_wrdata_mask; 37 | 38 | // DFI read data interface 39 | logic [C_DFI_DATAEN_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_rddata_en ; 40 | logic [ C_DFI_DATA_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_rddata ; 41 | logic [C_DFI_WRDACS_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_rddata_cs_n ; 42 | logic [C_DFI_DATAEN_WIDTH-1:0][C_DFI_FREQ_RATIO-1:0] dfi_rddata_valid; 43 | 44 | // DFI update interface 45 | logic dfi_ctrlupd_req; 46 | logic dfi_ctrlupd_ack; 47 | logic dfi_phyupd_req ; 48 | logic [1:0] dfi_phyupd_type; 49 | logic dfi_phyupd_ack ; 50 | 51 | // DFI status interface 52 | logic [(C_DFI_DATA_WIDTH/8)-1:0] dfi_data_byte_disable; 53 | logic [ C_DFI_CS_WIDTH-1:0] dfi_dram_clk_disable ; 54 | logic [ 1:0] dfi_freq_ratio ; 55 | logic dfi_init_start ; 56 | logic dfi_init_complete ; 57 | logic dfi_parity_in ; 58 | logic [ C_DFI_ALERT_WIDTH-1:0] dfi_alert_n ; 59 | 60 | // DFI training interface 61 | logic dfi_rdlvl_req ; // ddr3 only 62 | logic dfi_phy_rdlvl_cs_n ; // ddr3 only 63 | logic dfi_rdlvl_en ; // ddr3 only 64 | logic dfi_rdlvl_resp ; // ddr3 only 65 | logic dfi_rdlvl_gate_req ; // ddr3 only 66 | logic dfi_phy_rdlvl_gate_cs_n; // ddr3 only 67 | logic dfi_rdlvl_gate_en ; // ddr3 only 68 | logic dfi_wrlvl_req ; // ddr3 only 69 | logic dfi_phy_wrlvl_cs_n ; // ddr3 only 70 | logic dfi_wrlvl_en ; // ddr3 only 71 | logic dfi_wrlvl_strobe ; // ddr3 only 72 | logic dfi_wrlvl_resp ; // ddr3 only 73 | logic dfi_lvl_periodic ; 74 | logic dfi_phylvl_req_cs_n ; 75 | logic dfi_phylvl_ack_cs_n ; 76 | 77 | // DFI low power control interface 78 | logic dfi_lp_ctrl_req; 79 | logic dfi_lp_data_req; 80 | logic dfi_lp_wakeup ; 81 | logic dfi_lp_ack ; 82 | 83 | // DFI error interface 84 | logic [ C_DFI_ERR_WIDTH-1:0] dfi_error ; 85 | logic [(4*C_DFI_ERR_WIDTH)-1:0] dfi_error_info; 86 | 87 | modport master ( 88 | output dfi_address , 89 | output dfi_bank , 90 | output dfi_ras_n , 91 | output dfi_cas_n , 92 | output dfi_we_n , 93 | output dfi_cs_n , 94 | output dfi_cke , 95 | output dfi_odt , 96 | output dfi_reset_n , // ddr3 only 97 | output dfi_wrdata_en , 98 | output dfi_wrdata , 99 | output dfi_wrdata_cs_n , 100 | output dfi_wrdata_mask , 101 | output dfi_rddata_en , 102 | input dfi_rddata , 103 | output dfi_rddata_cs_n , 104 | input dfi_rddata_valid , 105 | output dfi_ctrlupd_req , 106 | input dfi_ctrlupd_ack , 107 | input dfi_phyupd_req , 108 | input dfi_phyupd_type , 109 | output dfi_phyupd_ack , 110 | output dfi_data_byte_disable , 111 | output dfi_dram_clk_disable , 112 | output dfi_freq_ratio , 113 | output dfi_init_start , 114 | input dfi_init_complete , 115 | output dfi_parity_in , 116 | input dfi_alert_n , 117 | input dfi_rdlvl_req , // ddr3 only 118 | input dfi_phy_rdlvl_cs_n , // ddr3 only 119 | output dfi_rdlvl_en , // ddr3 only 120 | input dfi_rdlvl_resp , // ddr3 only 121 | input dfi_rdlvl_gate_req , // ddr3 only 122 | input dfi_phy_rdlvl_gate_cs_n, // ddr3 only 123 | output dfi_rdlvl_gate_en , // ddr3 only 124 | input dfi_wrlvl_req , // ddr3 only 125 | input dfi_phy_wrlvl_cs_n , // ddr3 only 126 | output dfi_wrlvl_en , // ddr3 only 127 | output dfi_wrlvl_strobe , // ddr3 only 128 | input dfi_wrlvl_resp , // ddr3 only 129 | output dfi_lvl_periodic , 130 | input dfi_phylvl_req_cs_n , 131 | output dfi_phylvl_ack_cs_n , 132 | output dfi_lp_ctrl_req , 133 | output dfi_lp_data_req , 134 | output dfi_lp_wakeup , 135 | input dfi_lp_ack , 136 | input dfi_error , 137 | input dfi_error_info, 138 | import task cmd(input logic [3:0] phase, input logic[3:0] opcode), 139 | import task mrs(input logic [1:0] addr, input logic [12:0] value) 140 | ); 141 | 142 | modport slave ( 143 | input dfi_address , 144 | input dfi_bank , 145 | input dfi_ras_n , 146 | input dfi_cas_n , 147 | input dfi_we_n , 148 | input dfi_cs_n , 149 | input dfi_cke , 150 | input dfi_odt , 151 | input dfi_reset_n , // ddr3 only 152 | input dfi_wrdata_en , 153 | input dfi_wrdata , 154 | input dfi_wrdata_cs_n , 155 | input dfi_wrdata_mask , 156 | input dfi_rddata_en , 157 | output dfi_rddata , 158 | input dfi_rddata_cs_n , 159 | output dfi_rddata_valid , 160 | input dfi_ctrlupd_req , 161 | output dfi_ctrlupd_ack , 162 | output dfi_phyupd_req , 163 | output dfi_phyupd_type , 164 | input dfi_phyupd_ack , 165 | input dfi_data_byte_disable , 166 | input dfi_dram_clk_disable , 167 | input dfi_freq_ratio , 168 | input dfi_init_start , 169 | output dfi_init_complete , 170 | input dfi_parity_in , 171 | output dfi_alert_n , 172 | output dfi_rdlvl_req , // ddr3 only 173 | output dfi_phy_rdlvl_cs_n , // ddr3 only 174 | input dfi_rdlvl_en , // ddr3 only 175 | output dfi_rdlvl_resp , // ddr3 only 176 | output dfi_rdlvl_gate_req , // ddr3 only 177 | output dfi_phy_rdlvl_gate_cs_n, // ddr3 only 178 | input dfi_rdlvl_gate_en , // ddr3 only 179 | output dfi_wrlvl_req , // ddr3 only 180 | output dfi_phy_wrlvl_cs_n , // ddr3 only 181 | input dfi_wrlvl_en , // ddr3 only 182 | input dfi_wrlvl_strobe , // ddr3 only 183 | output dfi_wrlvl_resp , // ddr3 only 184 | input dfi_lvl_periodic , 185 | output dfi_phylvl_req_cs_n , 186 | input dfi_phylvl_ack_cs_n , 187 | input dfi_lp_ctrl_req , 188 | input dfi_lp_data_req , 189 | input dfi_lp_wakeup , 190 | output dfi_lp_ack , 191 | output dfi_error , 192 | output dfi_error_info 193 | ); 194 | 195 | task cmd(input logic [1:0] phase, input logic[3:0] opcode); 196 | dfi_cs_n[0][phase] <= opcode[3]; 197 | dfi_ras_n[0][phase] <= opcode[2]; 198 | dfi_cas_n[0][phase] <= opcode[1]; 199 | dfi_we_n[0][phase] <= opcode[0]; 200 | endtask : cmd 201 | 202 | task mrs(input logic [1:0] addr, input logic [12:0] value); 203 | dfi_bank[2] <= '0; 204 | dfi_bank[1] <= {C_DFI_FREQ_RATIO{addr[1]}}; 205 | dfi_bank[0] <= {C_DFI_FREQ_RATIO{addr[0]}}; 206 | dfi_address[15] <= '0; 207 | dfi_address[14] <= '0; 208 | dfi_address[13] <= '0; 209 | dfi_address[12] <= {C_DFI_FREQ_RATIO{value[12]}}; 210 | dfi_address[11] <= {C_DFI_FREQ_RATIO{value[11]}}; 211 | dfi_address[10] <= {C_DFI_FREQ_RATIO{value[10]}}; 212 | dfi_address[9] <= {C_DFI_FREQ_RATIO{value[9]}}; 213 | dfi_address[8] <= {C_DFI_FREQ_RATIO{value[8]}}; 214 | dfi_address[7] <= {C_DFI_FREQ_RATIO{value[7]}}; 215 | dfi_address[6] <= {C_DFI_FREQ_RATIO{value[6]}}; 216 | dfi_address[5] <= {C_DFI_FREQ_RATIO{value[5]}}; 217 | dfi_address[4] <= {C_DFI_FREQ_RATIO{value[4]}}; 218 | dfi_address[3] <= {C_DFI_FREQ_RATIO{value[3]}}; 219 | dfi_address[2] <= {C_DFI_FREQ_RATIO{value[2]}}; 220 | dfi_address[1] <= {C_DFI_FREQ_RATIO{value[1]}}; 221 | dfi_address[0] <= {C_DFI_FREQ_RATIO{value[0]}}; 222 | endtask : mrs 223 | 224 | endinterface // dfi_if 225 | -------------------------------------------------------------------------------- /rtl/nasti_ddrx_mc.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This is the top module for the memory controller. 3 | * tcmd_lat = 1 4 | */ 5 | 6 | `include "timescale.svh" 7 | `include "defines.svh" 8 | `include "enums.svh" 9 | `include "functions.svh" 10 | `include "structs.svh" 11 | 12 | module nasti_ddrx_mc #( 13 | C_DFI_ADDR_WIDTH = 0, 14 | C_DFI_ALERT_WIDTH = 0, 15 | C_DFI_BANK_WIDTH = 0, 16 | C_DFI_CS_WIDTH = 0, 17 | C_DFI_CTRL_WIDTH = 0, 18 | C_DFI_DATA_WIDTH = 0, 19 | C_DFI_DATAEN_WIDTH = 0, 20 | C_DFI_DM_WIDTH = 0, 21 | C_DFI_ERR_WIDTH = 0, 22 | C_DFI_FREQ_RATIO = 0, 23 | C_DFI_WRDACS_WIDTH = 0, 24 | C_NASTI_ADDR_WIDTH = 0, 25 | C_NASTI_DATA_WIDTH = 0, 26 | C_NASTI_ID_WIDTH = 0, 27 | C_NASTI_USER_WIDTH = 0, 28 | C_NASTIL_ADDR_WIDTH = 0, 29 | C_NASTIL_DATA_WIDTH = 0 30 | ) ( 31 | input core_clk , 32 | input core_arstn , 33 | // NASTI-Lite interface 34 | input s_nastilite_clk , 35 | input s_nastilite_aresetn, 36 | nasti_if.slave s_nastilite , 37 | // NASTI interface 38 | input s_nasti_clk , 39 | input s_nasti_aresetn , 40 | nasti_if.slave s_nasti , 41 | // DDR PHY interface 42 | dfi_if.master m_dfi 43 | ); 44 | 45 | config_if cfg (); 46 | 47 | dfi_if #( 48 | .C_DFI_FREQ_RATIO (C_DFI_FREQ_RATIO ), 49 | .C_DFI_ADDR_WIDTH (C_DFI_ADDR_WIDTH ), 50 | .C_DFI_BANK_WIDTH (C_DFI_BANK_WIDTH ), 51 | .C_DFI_CTRL_WIDTH (C_DFI_CTRL_WIDTH ), 52 | .C_DFI_CS_WIDTH (C_DFI_CS_WIDTH ), 53 | .C_DFI_DATAEN_WIDTH(C_DFI_DATAEN_WIDTH), 54 | .C_DFI_DATA_WIDTH (C_DFI_DATA_WIDTH ), 55 | .C_DFI_WRDACS_WIDTH(C_DFI_CS_WIDTH ), 56 | .C_DFI_DM_WIDTH (C_DFI_DM_WIDTH ), 57 | .C_DFI_ALERT_WIDTH (C_DFI_ALERT_WIDTH ), 58 | .C_DFI_ERR_WIDTH (C_DFI_ERR_WIDTH ) 59 | ) cali_dfi (), data_dfi(), init_dfi(), main_dfi(), tran_dfi(); 60 | 61 | nastilite_frontend #( 62 | .C_NASTI_ADDR_WIDTH(C_NASTI_ADDR_WIDTH), 63 | .C_NASTI_DATA_WIDTH(C_NASTI_DATA_WIDTH) 64 | ) i_nastilite_frontend ( 65 | .s_nastilite_clk (s_nastilite_clk ), 66 | .s_nastilite_aresetn(s_nastilite_aresetn), 67 | .s_nastilite (s_nastilite ), 68 | .m_cfg (cfg ) 69 | ); 70 | 71 | ar_trans ar_rdata ; 72 | logic ar_rempty; 73 | logic ar_rden ; 74 | 75 | r_trans r_wdata; 76 | logic r_wfull; 77 | logic r_wren ; 78 | 79 | aw_trans aw_rdata ; 80 | logic aw_rempty; 81 | logic aw_rden ; 82 | 83 | w_trans w_rdata ; 84 | logic w_rempty; 85 | logic w_rden ; 86 | 87 | b_trans b_wdata; 88 | logic b_wfull; 89 | logic b_wren ; 90 | 91 | nasti_frontend #( 92 | .C_NASTI_ID_WIDTH (C_NASTI_ID_WIDTH ), 93 | .C_NASTI_ADDR_WIDTH(C_NASTI_ADDR_WIDTH), 94 | .C_NASTI_DATA_WIDTH(C_NASTI_DATA_WIDTH), 95 | .C_NASTI_USER_WIDTH(C_NASTI_USER_WIDTH), 96 | .C_FIFO_DEPTH (4 ) 97 | ) i_nasti_frontend ( 98 | .core_clk (core_clk ), 99 | .core_arstn (core_arstn ), 100 | .s_nasti_clk (s_nasti_clk ), 101 | .s_nasti_aresetn(s_nasti_aresetn), 102 | .s_nasti (s_nasti ), 103 | .ar_rdata (ar_rdata ), 104 | .ar_rempty (ar_rempty ), 105 | .ar_rden (ar_rden ), 106 | .aw_rdata (aw_rdata ), 107 | .aw_rempty (aw_rempty ), 108 | .aw_rden (aw_rden ), 109 | .w_rdata (w_rdata ), 110 | .w_rempty (w_rempty ), 111 | .w_rden (w_rden ), 112 | .r_wdata (r_wdata ), 113 | .r_wfull (r_wfull ), 114 | .r_wren (r_wren ), 115 | .b_wdata (b_wdata ), 116 | .b_wfull (b_wfull ), 117 | .b_wren (b_wren ) 118 | ); 119 | 120 | sdram_trans tr_wdata; 121 | logic tr_wfull; 122 | logic tr_wren ; 123 | 124 | tran_mapper #( 125 | .C_DFI_CS_WIDTH (C_DFI_CS_WIDTH ), 126 | .C_DFI_DATA_WIDTH (C_DFI_DATA_WIDTH ), 127 | .C_NASTI_ADDR_WIDTH(C_NASTI_ADDR_WIDTH), 128 | .C_NASTI_DATA_WIDTH(C_NASTI_DATA_WIDTH) 129 | ) i_tran_mapper ( 130 | .core_clk (core_clk ), 131 | .core_arstn(core_arstn), 132 | .aw_rdata (aw_rdata ), 133 | .aw_rempty (aw_rempty ), 134 | .aw_rden (aw_rden ), 135 | .w_rdata (w_rdata ), 136 | .w_rempty (w_rempty ), 137 | .w_rden (w_rden ), 138 | .b_wdata (b_wdata ), 139 | .b_wfull (b_wfull ), 140 | .b_wren (b_wren ), 141 | .ar_rdata (ar_rdata ), 142 | .ar_rempty (ar_rempty ), 143 | .ar_rden (ar_rden ), 144 | .r_wdata (r_wdata ), 145 | .r_wfull (r_wfull ), 146 | .r_wren (r_wren ), 147 | .tr_wdata (tr_wdata ), 148 | .tr_wfull (tr_wfull ), 149 | .tr_wren (tr_wren ), 150 | .s_cfg (cfg ) 151 | ); 152 | 153 | sdram_trans tr_rdata ; 154 | logic tr_rempty; 155 | logic tr_rden ; 156 | 157 | sfifo #( 158 | .C_DATA_WIDTH($bits(sdram_trans)), 159 | .C_ADDR_WIDTH(8 ) 160 | ) i_sfifo_tran_fifo ( 161 | .clk (core_clk ), 162 | .arstn (core_arstn), 163 | .wdata (tr_wdata ), 164 | .wfull (tr_wfull ), 165 | .wren (tr_wren ), 166 | .rdata (tr_rdata ), 167 | .rempty(tr_rempty ), 168 | .rden (tr_rden ) 169 | ); 170 | 171 | logic [(C_DFI_FREQ_RATIO*C_DFI_DATA_WIDTH)-1:0] r_rdata ; 172 | logic r_rempty; 173 | logic r_rden ; 174 | logic [(C_DFI_FREQ_RATIO*C_DFI_DATA_WIDTH)-1:0] w_wdata ; 175 | logic w_wfull ; 176 | logic w_wren ; 177 | 178 | // datapath #( 179 | // .C_DFI_FREQ_RATIO(C_DFI_FREQ_RATIO), 180 | // .C_DFI_DATA_WIDTH(C_DFI_DATA_WIDTH) 181 | // ) i_datapath ( 182 | // .core_clk (core_clk ), 183 | // .core_arstn(core_arstn), 184 | // .r_rdata (r_rdata ), 185 | // .r_rempty (r_rempty ), 186 | // .r_rden (r_rden ), 187 | // .w_wdata (w_wdata ), 188 | // .w_wfull (w_wfull ), 189 | // .w_wren (w_wren ), 190 | // .data_dfi (data_dfi ) 191 | // ); 192 | 193 | // logic tran_do; 194 | // sdram_trans tr_data; 195 | // logic tr_rinc; 196 | // tran_control i_tran_control ( 197 | // .core_clk (core_clk ), 198 | // .core_arstn(core_arstn), 199 | // .tran_do (tran_do ), 200 | // .s_cfg (s_cfg ), 201 | // .tran_dfi (tran_dfi ), 202 | // .tr_data (tr_data ), 203 | // .tr_rempty (tr_rempty ), 204 | // .tr_rinc (tr_rinc ) 205 | // ); 206 | 207 | 208 | // generate 209 | // for (genvar i = 0; i < C_DFI_BANK_WIDTH; i++) begin 210 | // bank_manager i_bank_manager ( 211 | // .core_clk (core_clk ), 212 | // .core_arstn(core_arstn), 213 | // .row (row ), 214 | // .dsa (dsa ) 215 | // ); 216 | // end 217 | // endgenerate 218 | 219 | logic r_empty ; 220 | logic ddr_init_start; 221 | logic ddr_init_done ; 222 | logic tran_start ; 223 | logic tran_pause ; 224 | logic [1:0] sel ; 225 | logic cali_start ; 226 | logic cali_done ; 227 | logic tran_done ; 228 | 229 | main_control i_main_control ( 230 | .core_clk (core_clk ), 231 | .core_arstn (core_arstn ), 232 | .r_empty (r_empty ), 233 | .ddr_init_start(ddr_init_start), 234 | .ddr_init_done (ddr_init_done ), 235 | .cali_start (cali_start ), 236 | .cali_done (cali_done ), 237 | .tran_start (tran_start ), 238 | .tran_done (tran_done ), 239 | .s_cfg (cfg ), 240 | .sel (sel ), 241 | .main_dfi (main_dfi ) 242 | ); 243 | 244 | init_control i_init_control ( 245 | .core_clk (core_clk ), 246 | .core_arstn (core_arstn ), 247 | .ddr_init_start(ddr_init_start), 248 | .ddr_init_done (ddr_init_done ), 249 | .s_cfg (cfg ), 250 | .init_dfi (init_dfi ) 251 | ); 252 | 253 | // tran_control i_tran_control ( 254 | // .core_clk (core_clk ), 255 | // .core_arstn(core_arstn), 256 | // .tran_start(tran_start), 257 | // .tran_pause(tran_pause), 258 | // .s_cfg (cfg ), 259 | // .tran_dfi (tran_dfi ) 260 | // ); 261 | 262 | // logic clk_1024khz; 263 | // logic rstn ; 264 | // logic ref_req ; 265 | // logic [3:0] warning ; 266 | // reg ref_do ; 267 | 268 | // refresh_controller i_refresh_controller ( 269 | // .clk_1024khz(clk_1024khz), 270 | // .rstn (rstn ), 271 | // .ref_req (ref_req ), 272 | // .warning (warning ), 273 | // .ref_do (ref_do ) 274 | // ); 275 | 276 | dfi_mux i_dfi_mux ( 277 | .cali_dfi(cali_dfi), 278 | .data_dfi(data_dfi), 279 | .init_dfi(init_dfi), 280 | .main_dfi(main_dfi), 281 | .tran_dfi(tran_dfi), 282 | .sel (sel ), 283 | .m_dfi (m_dfi ) 284 | ); 285 | 286 | endmodule // nasti_ddrx_mc 287 | -------------------------------------------------------------------------------- /rtl/init_control.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * This module is the initialization controller. 3 | */ 4 | 5 | `include "timescale.svh" 6 | `include "defines.svh" 7 | `include "defines.svh" 8 | `include "enums.svh" 9 | `include "functions.svh" 10 | `include "structs.svh" 11 | 12 | module init_control ( 13 | input core_clk , 14 | input core_arstn , 15 | input ddr_init_start, 16 | output logic ddr_init_done , 17 | config_if.slave s_cfg , 18 | dfi_if.master init_dfi 19 | ); 20 | 21 | enum logic[5:0] {RESET, IDLE, WAIT_200US, WAIT_500US, WAIT_XPR, ISSUE_MR2, WAIT_MR2, ISSUE_MR3, WAIT_MR3, ISSUE_MR1, WAIT_MR1, ISSUE_MR0, WAIT_MR0, ISSUE_ZQCL, WAIT_ZQCL, RL_START, RL_WAIT, RL_DONE, WL_START, WL_WAIT, WL_DONE, DONE, XXXX = 'x} state, next; 22 | 23 | logic [15:0] counter ; 24 | logic [15:0] counter_next; 25 | 26 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_state 27 | if(~core_arstn) begin 28 | state <= RESET; 29 | counter <= '0; 30 | end else begin 31 | state <= next; 32 | counter <= counter_next; 33 | end 34 | end 35 | 36 | always_comb begin : proc_next 37 | next = XXXX; 38 | unique case (state) 39 | RESET : begin 40 | next = IDLE; 41 | counter_next = '0; 42 | end 43 | IDLE : if(1'b1 == ddr_init_start) begin 44 | next = WAIT_200US; 45 | counter_next = 1'b1; 46 | end else begin 47 | next = IDLE; 48 | counter_next = '0; 49 | end 50 | WAIT_200US : if(ns_to_clk(200) == counter) begin 51 | next = WAIT_500US; 52 | counter_next = 1'b1; 53 | end else begin 54 | next = WAIT_200US; 55 | counter_next = counter + 1; 56 | end 57 | WAIT_500US : if(ns_to_clk(500) == counter) begin 58 | next = WAIT_XPR; 59 | counter_next = 1'b1; 60 | end else begin 61 | next = WAIT_500US; 62 | counter_next = counter + 1; 63 | end 64 | WAIT_XPR : if(s_cfg.tXPR == counter) begin 65 | next = ISSUE_MR2; 66 | counter_next = '0; 67 | end else begin 68 | next = WAIT_XPR; 69 | counter_next = counter + 1; 70 | end 71 | ISSUE_MR2 : if(1'b1 == s_cfg.tMRD) begin 72 | next = WAIT_MR2; 73 | counter_next = 1'b1; 74 | end else begin 75 | next = ISSUE_MR3; 76 | counter_next = '0; 77 | end 78 | WAIT_MR2 : if(s_cfg.tMRD == counter) begin 79 | next = ISSUE_MR3; 80 | counter_next = '0; 81 | end else begin 82 | next = WAIT_MR2; 83 | counter_next = counter + 1; 84 | end 85 | ISSUE_MR3 : if(1'b1 == s_cfg.tMRD) begin 86 | next = WAIT_MR3; 87 | counter_next = 1'b1; 88 | end else begin 89 | next = ISSUE_MR1; 90 | counter_next = '0; 91 | end 92 | WAIT_MR3 : if(s_cfg.tMRD == counter) begin 93 | next = ISSUE_MR1; 94 | counter_next = '0; 95 | end else begin 96 | next = WAIT_MR3; 97 | counter_next = counter + 1; 98 | end 99 | ISSUE_MR1 : if(1'b1 == s_cfg.tMRD) begin 100 | next = WAIT_MR1; 101 | counter_next = 1'b1; 102 | end else begin 103 | next = ISSUE_MR0; 104 | counter_next = '0; 105 | end 106 | WAIT_MR1 : if(s_cfg.tMRD == counter) begin 107 | next = ISSUE_MR0; 108 | counter_next = '0; 109 | end else begin 110 | next = WAIT_MR1; 111 | counter_next = counter + 1; 112 | end 113 | ISSUE_MR0 : if(1'b1 == s_cfg.tMRD) begin 114 | next = WAIT_MR0; 115 | counter_next = 1'b1; 116 | end else begin 117 | next = ISSUE_ZQCL; 118 | counter_next = '0; 119 | end 120 | WAIT_MR0 : if(s_cfg.tMOD == counter) begin 121 | next = ISSUE_ZQCL; 122 | counter_next = '0; 123 | end else begin 124 | next = WAIT_MR0; 125 | counter_next = counter + 1; 126 | end 127 | ISSUE_ZQCL : begin 128 | next = WAIT_ZQCL; 129 | counter_next = 1'b1; 130 | end 131 | WAIT_ZQCL : if(s_cfg.tZQinit == counter) begin 132 | next = WL_START; 133 | counter_next = '0; 134 | end else begin 135 | next = WAIT_ZQCL; 136 | counter_next = counter + 1; 137 | end 138 | WL_START : begin 139 | next = WL_WAIT; 140 | counter_next = 1'b1; 141 | end 142 | WL_WAIT : if(1'b1 == init_dfi.dfi_wrlvl_resp) begin 143 | next = RL_START; 144 | counter_next = '0; 145 | end else begin 146 | next = WL_WAIT; 147 | counter_next = counter + 1; 148 | end 149 | RL_START : begin 150 | next = RL_WAIT; 151 | counter_next = 1'b1; 152 | end 153 | RL_WAIT : if(1'b1 == init_dfi.dfi_rdlvl_resp) begin 154 | next = DONE; 155 | counter_next = '0; 156 | end else begin 157 | next = RL_WAIT; 158 | counter_next = counter + 1; 159 | end 160 | DONE : begin 161 | next = DONE; 162 | counter_next = '0; 163 | end 164 | endcase 165 | end 166 | 167 | always_ff @(posedge core_clk or negedge core_arstn) begin : proc_output 168 | if(~core_arstn) begin 169 | ddr_init_done <= '0; 170 | init_dfi.dfi_address[15:0] <= '0; 171 | init_dfi.dfi_bank <= '0; 172 | init_dfi.dfi_ras_n[0] <= '1; 173 | init_dfi.dfi_cas_n[0] <= '1; 174 | init_dfi.dfi_we_n[0] <= '1; 175 | init_dfi.dfi_cs_n[1:0] <= '1; 176 | init_dfi.dfi_cke <= '0; 177 | init_dfi.dfi_odt <= '0; 178 | init_dfi.dfi_reset_n[0] <= '0; 179 | init_dfi.dfi_dram_clk_disable <= '0; 180 | end else begin 181 | ddr_init_done <= '0; 182 | init_dfi.dfi_address <= '0; 183 | init_dfi.dfi_bank <= '0; 184 | init_dfi.dfi_cke <= '1; 185 | init_dfi.dfi_odt <= '0; 186 | init_dfi.dfi_reset_n[0] <= '1; 187 | init_dfi.dfi_dram_clk_disable <= '0; 188 | init_dfi.cmd(0, `CMD_NOP); 189 | init_dfi.cmd(1, `CMD_NOP); 190 | init_dfi.cmd(2, `CMD_NOP); 191 | init_dfi.cmd(3, `CMD_NOP); 192 | unique case (next) 193 | IDLE : begin 194 | init_dfi.dfi_reset_n <= '0; 195 | init_dfi.dfi_cke <= '0; 196 | init_dfi.cmd(0, `CMD_NOP); 197 | init_dfi.cmd(1, `CMD_NOP); 198 | init_dfi.cmd(2, `CMD_NOP); 199 | init_dfi.cmd(3, `CMD_NOP); 200 | end 201 | WAIT_200US : begin 202 | init_dfi.dfi_reset_n <= '0; 203 | init_dfi.dfi_cke <= '0; 204 | init_dfi.cmd(0, `CMD_NOP); 205 | init_dfi.cmd(1, `CMD_NOP); 206 | init_dfi.cmd(2, `CMD_NOP); 207 | init_dfi.cmd(3, `CMD_NOP); 208 | end 209 | WAIT_500US : begin 210 | init_dfi.dfi_cke <= '0; 211 | init_dfi.cmd(0, `CMD_NOP); 212 | init_dfi.cmd(1, `CMD_NOP); 213 | init_dfi.cmd(2, `CMD_NOP); 214 | init_dfi.cmd(3, `CMD_NOP); 215 | end 216 | WAIT_XPR : begin 217 | init_dfi.cmd(0, `CMD_NOP); 218 | init_dfi.cmd(1, `CMD_NOP); 219 | init_dfi.cmd(2, `CMD_NOP); 220 | init_dfi.cmd(3, `CMD_NOP); 221 | end 222 | ISSUE_MR2 : begin 223 | init_dfi.cmd(0, `CMD_MRS); 224 | init_dfi.cmd(1, `CMD_NOP); 225 | init_dfi.cmd(2, `CMD_NOP); 226 | init_dfi.cmd(3, `CMD_NOP); 227 | init_dfi.mrs(2, s_cfg.msr2); 228 | end 229 | WAIT_MR2 : begin 230 | init_dfi.cmd(0, `CMD_NOP); 231 | init_dfi.cmd(1, `CMD_NOP); 232 | init_dfi.cmd(2, `CMD_NOP); 233 | init_dfi.cmd(3, `CMD_NOP); 234 | init_dfi.mrs(2, s_cfg.msr2); 235 | end 236 | ISSUE_MR3 : begin 237 | init_dfi.cmd(0, `CMD_MRS); 238 | init_dfi.cmd(1, `CMD_NOP); 239 | init_dfi.cmd(2, `CMD_NOP); 240 | init_dfi.cmd(3, `CMD_NOP); 241 | init_dfi.mrs(3, s_cfg.msr3); 242 | end 243 | WAIT_MR3 : begin 244 | init_dfi.cmd(0, `CMD_NOP); 245 | init_dfi.cmd(1, `CMD_NOP); 246 | init_dfi.cmd(2, `CMD_NOP); 247 | init_dfi.cmd(3, `CMD_NOP); 248 | init_dfi.mrs(3, s_cfg.msr3); 249 | end 250 | ISSUE_MR1 : begin 251 | init_dfi.cmd(0, `CMD_MRS); 252 | init_dfi.cmd(1, `CMD_NOP); 253 | init_dfi.cmd(2, `CMD_NOP); 254 | init_dfi.cmd(3, `CMD_NOP); 255 | init_dfi.mrs(1, s_cfg.msr1); 256 | end 257 | WAIT_MR1 : begin 258 | init_dfi.cmd(0, `CMD_NOP); 259 | init_dfi.cmd(1, `CMD_NOP); 260 | init_dfi.cmd(2, `CMD_NOP); 261 | init_dfi.cmd(3, `CMD_NOP); 262 | init_dfi.mrs(1, s_cfg.msr1); 263 | end 264 | ISSUE_MR0 : begin 265 | init_dfi.cmd(0, `CMD_MRS); 266 | init_dfi.cmd(1, `CMD_NOP); 267 | init_dfi.cmd(2, `CMD_NOP); 268 | init_dfi.cmd(3, `CMD_NOP); 269 | init_dfi.mrs(0, s_cfg.msr0); 270 | end 271 | WAIT_MR0 : begin 272 | init_dfi.cmd(0, `CMD_NOP); 273 | init_dfi.cmd(1, `CMD_NOP); 274 | init_dfi.cmd(2, `CMD_NOP); 275 | init_dfi.cmd(3, `CMD_NOP); 276 | init_dfi.mrs(0, s_cfg.msr0); 277 | end 278 | ISSUE_ZQCL : begin 279 | init_dfi.cmd(0, `CMD_ZQCL); 280 | init_dfi.cmd(1, `CMD_NOP); 281 | init_dfi.cmd(2, `CMD_NOP); 282 | init_dfi.cmd(3, `CMD_NOP); 283 | end 284 | WAIT_ZQCL : begin 285 | init_dfi.cmd(0, `CMD_NOP); 286 | init_dfi.cmd(1, `CMD_NOP); 287 | init_dfi.cmd(2, `CMD_NOP); 288 | init_dfi.cmd(3, `CMD_NOP); 289 | end 290 | WL_START : begin 291 | init_dfi.cmd(0, `CMD_NOP); 292 | init_dfi.cmd(1, `CMD_NOP); 293 | init_dfi.cmd(2, `CMD_NOP); 294 | init_dfi.cmd(3, `CMD_NOP); 295 | end 296 | WL_WAIT : begin 297 | init_dfi.cmd(0, `CMD_NOP); 298 | init_dfi.cmd(1, `CMD_NOP); 299 | init_dfi.cmd(2, `CMD_NOP); 300 | init_dfi.cmd(3, `CMD_NOP); 301 | end 302 | RL_START : begin 303 | 304 | end 305 | RL_WAIT : begin 306 | 307 | end 308 | DONE : begin 309 | ddr_init_done <= 1'b1; 310 | init_dfi.cmd(0, `CMD_NOP); 311 | init_dfi.cmd(1, `CMD_NOP); 312 | init_dfi.cmd(2, `CMD_NOP); 313 | init_dfi.cmd(3, `CMD_NOP); 314 | end 315 | endcase 316 | end 317 | end 318 | 319 | endmodule // init_control 320 | -------------------------------------------------------------------------------- /fpga/kc705/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `include "timescale.svh" 6 | `include "defines.svh" 7 | 8 | module top ( 9 | // KC705 resources 10 | input sysclk_p , 11 | input sysclk_n , 12 | input sysrst , 13 | output reg [ 7:0] gpio_led , 14 | // DDR3 interface 15 | inout [63:0] ddr_dq , 16 | inout [ 7:0] ddr_dqs_n , 17 | inout [ 7:0] ddr_dqs_p , 18 | output [15:0] ddr_addr , 19 | output [ 2:0] ddr_ba , 20 | output ddr_ras_n , 21 | output ddr_cas_n , 22 | output ddr_we_n , 23 | output ddr_reset_n, 24 | output [ 1:0] ddr_ck_p , 25 | output [ 1:0] ddr_ck_n , 26 | output [ 1:0] ddr_cke , 27 | output [ 1:0] ddr_cs_n , 28 | output [ 7:0] ddr_dm , 29 | output [ 1:0] ddr_odt 30 | ); 31 | 32 | logic sysclk; 33 | 34 | IBUFGDS #( 35 | .DIFF_TERM ("FALSE" ), // Differential Termination 36 | .IBUF_LOW_PWR("TRUE" ), // Low power="TRUE", Highest performance="FALSE" 37 | .IOSTANDARD ("DEFAULT") // Specify the input I/O standard 38 | ) sysclk_IBUFGDS_inst ( 39 | .O (sysclk ), // Clock buffer output 40 | .I (sysclk_p), // Diff_p clock buffer input (connect directly to top-level port) 41 | .IB(sysclk_n) // Diff_n clock buffer input (connect directly to top-level port) 42 | ); 43 | 44 | logic mmcm_locked; 45 | logic mmcm_clkfb ; 46 | 47 | logic clk_ubuf ; 48 | logic clk_90_ubuf ; 49 | logic clkdiv2_ubuf; 50 | logic clkdiv4_ubuf; 51 | 52 | (* LOC = "MMCME2_ADV_X1Y1" *) 53 | 54 | MMCME2_BASE #( 55 | .BANDWIDTH ("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW) 56 | .CLKFBOUT_MULT_F (4.000 ), // Multiply value for all CLKOUT (2.000-64.000). 57 | .CLKFBOUT_PHASE (0.000 ), // Phase offset in degrees of CLKFB (-360.000-360.000). 58 | .CLKIN1_PERIOD (5.000 ), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). 59 | // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) 60 | .CLKOUT0_DIVIDE_F (2.000 ), // Divide amount for CLKOUT0 (1.000-128.000). 61 | .CLKOUT1_DIVIDE (2 ), 62 | .CLKOUT2_DIVIDE (4 ), 63 | .CLKOUT3_DIVIDE (8 ), 64 | .CLKOUT4_DIVIDE (1 ), 65 | .CLKOUT5_DIVIDE (1 ), 66 | .CLKOUT6_DIVIDE (1 ), 67 | // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99). 68 | .CLKOUT0_DUTY_CYCLE(0.50 ), 69 | .CLKOUT1_DUTY_CYCLE(0.50 ), 70 | .CLKOUT2_DUTY_CYCLE(0.50 ), 71 | .CLKOUT3_DUTY_CYCLE(0.50 ), 72 | .CLKOUT4_DUTY_CYCLE(0.50 ), 73 | .CLKOUT5_DUTY_CYCLE(0.50 ), 74 | .CLKOUT6_DUTY_CYCLE(0.50 ), 75 | // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000). 76 | .CLKOUT0_PHASE (000.000 ), 77 | .CLKOUT1_PHASE (090.000 ), 78 | .CLKOUT2_PHASE (000.000 ), 79 | .CLKOUT3_PHASE (000.000 ), 80 | .CLKOUT4_PHASE (000.000 ), 81 | .CLKOUT5_PHASE (000.000 ), 82 | .CLKOUT6_PHASE (000.000 ), 83 | .CLKOUT4_CASCADE ("FALSE" ), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) 84 | .DIVCLK_DIVIDE (1 ), // Master division value (1-106) 85 | .REF_JITTER1 (0.000 ), // Reference input jitter in UI (0.000-0.999). 86 | .STARTUP_WAIT ("FALSE" ) // Delays DONE until MMCM is locked (FALSE, TRUE) 87 | ) MMCME2_BASE_inst ( 88 | // Clock Outputs: 1-bit (each) output: User configurable clock outputs 89 | .CLKOUT0 (clk_ubuf ), // 1-bit output: CLKOUT0 90 | .CLKOUT0B ( ), // 1-bit output: Inverted CLKOUT0 91 | .CLKOUT1 (clk_90_ubuf ), // 1-bit output: CLKOUT1 92 | .CLKOUT1B ( ), // 1-bit output: Inverted CLKOUT1 93 | .CLKOUT2 (clkdiv2_ubuf), // 1-bit output: CLKOUT2 94 | .CLKOUT2B ( ), // 1-bit output: Inverted CLKOUT2 95 | .CLKOUT3 (clkdiv4_ubuf), // 1-bit output: CLKOUT3 96 | .CLKOUT3B ( ), // 1-bit output: Inverted CLKOUT3 97 | .CLKOUT4 ( ), // 1-bit output: CLKOUT4 98 | .CLKOUT5 ( ), // 1-bit output: CLKOUT5 99 | .CLKOUT6 ( ), // 1-bit output: CLKOUT6 100 | // Feedback Clocks: 1-bit (each) output: Clock feedback ports 101 | .CLKFBOUT (mmcm_clkfb ), // 1-bit output: Feedback clock 102 | .CLKFBOUTB( ), // 1-bit output: Inverted CLKFBOUT 103 | // Status Ports: 1-bit (each) output: MMCM status ports 104 | .LOCKED (mmcm_locked ), // 1-bit output: LOCK 105 | // Clock Inputs: 1-bit (each) input: Clock input 106 | .CLKIN1 (sysclk ), // 1-bit input: Clock 107 | // Control Ports: 1-bit (each) input: MMCM control ports 108 | .PWRDWN (1'b0 ), // 1-bit input: Power-down 109 | .RST (sysrst ), // 1-bit input: Reset 110 | // Feedback Clocks: 1-bit (each) input: Clock feedback ports 111 | .CLKFBIN (mmcm_clkfb ) // 1-bit input: Feedback clock 112 | ); 113 | 114 | logic clk ; 115 | logic clk_90 ; 116 | logic clkdiv2; 117 | logic clkdiv4; 118 | 119 | BUFIO clk_BUFIO_inst ( 120 | .O(clk ), // 1-bit output: Clock output (connect to I/O clock loads). 121 | .I(clk_ubuf) // 1-bit input: Clock input (connect to an IBUF or BUFMR). 122 | ); 123 | 124 | BUFIO clk_90_BUFIO_inst ( 125 | .O(clk_90 ), // 1-bit output: Clock output (connect to I/O clock loads). 126 | .I(clk_90_ubuf) // 1-bit input: Clock input (connect to an IBUF or BUFMR). 127 | ); 128 | 129 | BUFG clkdiv2_BUFG_inst ( 130 | .O(clkdiv2 ), // 1-bit output: Clock output (connect to I/O clock loads). 131 | .I(clkdiv2_ubuf) // 1-bit input: Clock input (connect to an IBUFG or BUFMR). 132 | ); 133 | 134 | BUFG clkdiv4_BUFG_inst ( 135 | .O(clkdiv4 ), // 1-bit output: Clock output (connect to I/O clock loads). 136 | .I(clkdiv4_ubuf) // 1-bit input: Clock input (connect to an IBUFG or BUFMR). 137 | ); 138 | 139 | logic clk_300mhz_ubuf; 140 | logic pll_clkfb ; 141 | logic pll_locked ; 142 | 143 | (* LOC = "PLLE2_ADV_X1Y1" *) 144 | 145 | PLLE2_BASE #( 146 | .BANDWIDTH ("OPTIMIZED"), // OPTIMIZED, HIGH, LOW 147 | .CLKFBOUT_MULT (6 ), // Multiply value for all CLKOUT, (2-64) 148 | .CLKFBOUT_PHASE (0.0 ), // Phase offset in degrees of CLKFB, (-360.000-360.000). 149 | .CLKIN1_PERIOD (5.000 ), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). 150 | // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128) 151 | .CLKOUT0_DIVIDE (4 ), 152 | .CLKOUT1_DIVIDE (1 ), 153 | .CLKOUT2_DIVIDE (1 ), 154 | .CLKOUT3_DIVIDE (1 ), 155 | .CLKOUT4_DIVIDE (1 ), 156 | .CLKOUT5_DIVIDE (1 ), 157 | // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999). 158 | .CLKOUT0_DUTY_CYCLE(0.5 ), 159 | .CLKOUT1_DUTY_CYCLE(0.5 ), 160 | .CLKOUT2_DUTY_CYCLE(0.5 ), 161 | .CLKOUT3_DUTY_CYCLE(0.5 ), 162 | .CLKOUT4_DUTY_CYCLE(0.5 ), 163 | .CLKOUT5_DUTY_CYCLE(0.5 ), 164 | // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000). 165 | .CLKOUT0_PHASE (0.0 ), 166 | .CLKOUT1_PHASE (0.0 ), 167 | .CLKOUT2_PHASE (0.0 ), 168 | .CLKOUT3_PHASE (0.0 ), 169 | .CLKOUT4_PHASE (0.0 ), 170 | .CLKOUT5_PHASE (0.0 ), 171 | .DIVCLK_DIVIDE (1 ), // Master division value, (1-56) 172 | .REF_JITTER1 (0.0 ), // Reference input jitter in UI, (0.000-0.999). 173 | .STARTUP_WAIT ("FALSE" ) // Delay DONE until PLL Locks, ("TRUE"/"FALSE") 174 | ) PLLE2_BASE_inst ( 175 | // Clock Outputs: 1-bit (each) output: User configurable clock outputs 176 | .CLKOUT0 (clk_300mhz_ubuf), // 1-bit output: CLKOUT0 177 | .CLKOUT1 ( ), // 1-bit output: CLKOUT1 178 | .CLKOUT2 ( ), // 1-bit output: CLKOUT2 179 | .CLKOUT3 ( ), // 1-bit output: CLKOUT3 180 | .CLKOUT4 ( ), // 1-bit output: CLKOUT4 181 | .CLKOUT5 ( ), // 1-bit output: CLKOUT5 182 | // Feedback Clocks: 1-bit (each) output: Clock feedback ports 183 | .CLKFBOUT(pll_clkfb ), // 1-bit output: Feedback clock 184 | .LOCKED (pll_locked ), // 1-bit output: LOCK 185 | .CLKIN1 (sysclk ), // 1-bit input: Input clock 186 | // Control Ports: 1-bit (each) input: PLL control ports 187 | .PWRDWN (1'b0 ), // 1-bit input: Power-down 188 | .RST (sysrst ), // 1-bit input: Reset 189 | // Feedback Clocks: 1-bit (each) input: Clock feedback ports 190 | .CLKFBIN (pll_clkfb ) // 1-bit input: Feedback clock 191 | ); 192 | 193 | logic clk_300mhz; 194 | 195 | BUFG clk_300mhz_BUFG_inst ( 196 | .O(clk_300mhz ), // 1-bit output: Clock output (connect to I/O clock loads). 197 | .I(clk_300mhz_ubuf) // 1-bit input: Clock input (connect to an IBUFG or BUFMR). 198 | ); 199 | 200 | nasti_if #( 201 | .C_NASTI_ID_WIDTH (`C_NASTI_ID_WIDTH ), 202 | .C_NASTI_ADDR_WIDTH(`C_NASTI_ADDR_WIDTH), 203 | .C_NASTI_DATA_WIDTH(`C_NASTI_DATA_WIDTH), 204 | .C_NASTI_USER_WIDTH(`C_NASTI_USER_WIDTH) 205 | ) nasti (); 206 | 207 | always_comb begin : proc_nasti 208 | nasti.aw_region = '0; 209 | nasti.w_user = '0; 210 | nasti.ar_region = '0; 211 | end 212 | 213 | nasti_if #( 214 | .C_NASTI_ID_WIDTH (`C_NASTI_ID_WIDTH ), 215 | .C_NASTI_ADDR_WIDTH(`C_NASTIL_ADDR_WIDTH), 216 | .C_NASTI_DATA_WIDTH(`C_NASTIL_DATA_WIDTH), 217 | .C_NASTI_USER_WIDTH(`C_NASTI_USER_WIDTH ) 218 | ) nastilite (); 219 | 220 | dfi_if #( 221 | .C_DFI_FREQ_RATIO (`C_DFI_FREQ_RATIO ), 222 | .C_DFI_ADDR_WIDTH (`C_DFI_ADDR_WIDTH ), 223 | .C_DFI_BANK_WIDTH (`C_DFI_BANK_WIDTH ), 224 | .C_DFI_CTRL_WIDTH (`C_DFI_CTRL_WIDTH ), 225 | .C_DFI_CS_WIDTH (`C_DFI_CS_WIDTH ), 226 | .C_DFI_DATAEN_WIDTH(`C_DFI_DATAEN_WIDTH), 227 | .C_DFI_DATA_WIDTH (`C_DFI_DATA_WIDTH ), 228 | .C_DFI_WRDACS_WIDTH(`C_DFI_DACS_WIDTH ), 229 | .C_DFI_DM_WIDTH (`C_DFI_DM_WIDTH ), 230 | .C_DFI_ALERT_WIDTH (`C_DFI_ALERT_WIDTH ), 231 | .C_DFI_ERR_WIDTH (`C_DFI_ERR_WIDTH ) 232 | ) dfi (); 233 | 234 | logic dfi_arstn ; 235 | logic core_ext_start; 236 | logic axi_tg_irq_out; 237 | 238 | axi_traffic_gen_0 axi_traffic_gen_0_inst ( 239 | .s_axi_aclk (clkdiv4 ), // input wire s_axi_aclk 240 | .s_axi_aresetn (dfi_arstn ), // input wire s_axi_aresetn 241 | .core_ext_start(core_ext_start), // input wire core_ext_start 242 | .m_axi_awid (nasti.aw_id ), // output wire [0 : 0] m_axi_awid 243 | .m_axi_awaddr (nasti.aw_addr ), // output wire [31 : 0] m_axi_awaddr 244 | .m_axi_awlen (nasti.aw_len ), // output wire [7 : 0] m_axi_awlen 245 | .m_axi_awsize (nasti.aw_size ), // output wire [2 : 0] m_axi_awsize 246 | .m_axi_awburst (nasti.aw_burst), // output wire [1 : 0] m_axi_awburst 247 | .m_axi_awlock (nasti.aw_lock ), // output wire [0 : 0] m_axi_awlock 248 | .m_axi_awcache (nasti.aw_cache), // output wire [3 : 0] m_axi_awcache 249 | .m_axi_awprot (nasti.aw_prot ), // output wire [2 : 0] m_axi_awprot 250 | .m_axi_awqos (nasti.aw_qos ), // output wire [3 : 0] m_axi_awqos 251 | .m_axi_awuser (nasti.aw_user ), // output wire [7 : 0] m_axi_awuser 252 | .m_axi_awvalid (nasti.aw_valid), // output wire m_axi_awvalid 253 | .m_axi_awready (nasti.aw_ready), // input wire m_axi_awready 254 | .m_axi_wlast (nasti.w_last ), // output wire m_axi_wlast 255 | .m_axi_wdata (nasti.w_data ), // output wire [63 : 0] m_axi_wdata 256 | .m_axi_wstrb (nasti.w_strb ), // output wire [7 : 0] m_axi_wstrb 257 | .m_axi_wvalid (nasti.w_valid ), // output wire m_axi_wvalid 258 | .m_axi_wready (nasti.w_ready ), // input wire m_axi_wready 259 | .m_axi_bid (nasti.b_id ), // input wire [0 : 0] m_axi_bid 260 | .m_axi_bresp (nasti.b_resp ), // input wire [1 : 0] m_axi_bresp 261 | .m_axi_bvalid (nasti.b_valid ), // input wire m_axi_bvalid 262 | .m_axi_bready (nasti.b_ready ), // output wire m_axi_bready 263 | .m_axi_arid (nasti.ar_id ), // output wire [0 : 0] m_axi_arid 264 | .m_axi_araddr (nasti.ar_addr ), // output wire [31 : 0] m_axi_araddr 265 | .m_axi_arlen (nasti.ar_len ), // output wire [7 : 0] m_axi_arlen 266 | .m_axi_arsize (nasti.ar_size ), // output wire [2 : 0] m_axi_arsize 267 | .m_axi_arburst (nasti.ar_burst), // output wire [1 : 0] m_axi_arburst 268 | .m_axi_arlock (nasti.ar_lock ), // output wire [0 : 0] m_axi_arlock 269 | .m_axi_arcache (nasti.ar_cache), // output wire [3 : 0] m_axi_arcache 270 | .m_axi_arprot (nasti.ar_prot ), // output wire [2 : 0] m_axi_arprot 271 | .m_axi_arqos (nasti.ar_qos ), // output wire [3 : 0] m_axi_arqos 272 | .m_axi_aruser (nasti.ar_user ), // output wire [7 : 0] m_axi_aruser 273 | .m_axi_arvalid (nasti.ar_valid), // output wire m_axi_arvalid 274 | .m_axi_arready (nasti.ar_ready), // input wire m_axi_arready 275 | .m_axi_rid (nasti.r_id ), // input wire [0 : 0] m_axi_rid 276 | .m_axi_rlast (nasti.r_last ), // input wire m_axi_rlast 277 | .m_axi_rdata (nasti.r_data ), // input wire [63 : 0] m_axi_rdata 278 | .m_axi_rresp (nasti.r_resp ), // input wire [1 : 0] m_axi_rresp 279 | .m_axi_rvalid (nasti.r_valid ), // input wire m_axi_rvalid 280 | .m_axi_rready (nasti.r_ready ), // output wire m_axi_rready 281 | .irq_out (axi_tg_irq_out) // output wire irq_out 282 | ); 283 | 284 | logic [3:0] rst_counter; 285 | 286 | always_ff @(posedge sysclk or negedge mmcm_locked) begin : proc_reset 287 | if(sysrst) begin 288 | rst_counter <= 0; 289 | dfi_arstn <= 0; 290 | core_ext_start <= 0; 291 | end else if(~mmcm_locked | ~pll_locked) begin 292 | rst_counter <= 0; 293 | dfi_arstn <= 0; 294 | core_ext_start <= 0; 295 | end else begin 296 | if(15 == rst_counter) begin 297 | rst_counter <= rst_counter; 298 | dfi_arstn <= 1; 299 | core_ext_start <= 1; 300 | end else begin 301 | rst_counter <= rst_counter + 1; 302 | dfi_arstn <= 0; 303 | core_ext_start <= 0; 304 | end 305 | end 306 | end 307 | 308 | nasti_ddrx_mc #( 309 | .C_DFI_FREQ_RATIO (`C_DFI_FREQ_RATIO ), 310 | .C_NASTI_ID_WIDTH (`C_NASTI_ID_WIDTH ), 311 | .C_NASTI_ADDR_WIDTH (`C_NASTI_ADDR_WIDTH ), 312 | .C_NASTI_DATA_WIDTH (`C_NASTI_DATA_WIDTH ), 313 | .C_NASTI_USER_WIDTH (`C_NASTI_USER_WIDTH ), 314 | .C_NASTIL_ADDR_WIDTH(`C_NASTIL_ADDR_WIDTH), 315 | .C_NASTIL_DATA_WIDTH(`C_NASTIL_DATA_WIDTH), 316 | .C_DFI_ADDR_WIDTH (`C_DFI_ADDR_WIDTH ), 317 | .C_DFI_BANK_WIDTH (`C_DFI_BANK_WIDTH ), 318 | .C_DFI_CTRL_WIDTH (`C_DFI_CTRL_WIDTH ), 319 | .C_DFI_CS_WIDTH (`C_DFI_CS_WIDTH ), 320 | .C_DFI_DATAEN_WIDTH (`C_DFI_DATAEN_WIDTH ), 321 | .C_DFI_DATA_WIDTH (`C_DFI_DATA_WIDTH ), 322 | .C_DFI_WRDACS_WIDTH (`C_DFI_CS_WIDTH ), 323 | .C_DFI_DM_WIDTH (`C_DFI_DM_WIDTH ), 324 | .C_DFI_ALERT_WIDTH (`C_DFI_ALERT_WIDTH ), 325 | .C_DFI_ERR_WIDTH (`C_DFI_ERR_WIDTH ) 326 | ) i_nasti_ddrx_mc ( 327 | .core_clk (clkdiv4 ), 328 | .core_arstn (dfi_arstn), 329 | .s_nastilite_clk (clkdiv4 ), 330 | .s_nastilite_aresetn(dfi_arstn), 331 | .s_nastilite (nastilite), 332 | .s_nasti_clk (clkdiv4 ), 333 | .s_nasti_aresetn (dfi_arstn), 334 | .s_nasti (nasti ), 335 | .m_dfi (dfi ) 336 | ); 337 | 338 | phy_top i_phy_top ( 339 | .dfi_clk (clk ), 340 | .dfi_clk_90 (clk_90 ), 341 | .dfi_clkdiv2(clkdiv2 ), 342 | .dfi_clkdiv4(clkdiv4 ), 343 | .dfi_arstn (dfi_arstn ), 344 | .s_dfi (dfi ), 345 | .ddr_dq (ddr_dq ), 346 | .ddr_dqs_n (ddr_dqs_n ), 347 | .ddr_dqs_p (ddr_dqs_p ), 348 | .ddr_addr (ddr_addr ), 349 | .ddr_ba (ddr_ba ), 350 | .ddr_ras_n (ddr_ras_n ), 351 | .ddr_cas_n (ddr_cas_n ), 352 | .ddr_we_n (ddr_we_n ), 353 | .ddr_reset_n(ddr_reset_n), 354 | .ddr_ck_p (ddr_ck_p ), 355 | .ddr_ck_n (ddr_ck_n ), 356 | .ddr_cke (ddr_cke ), 357 | .ddr_cs_n (ddr_cs_n ), 358 | .ddr_dm (ddr_dm ), 359 | .ddr_odt (ddr_odt ), 360 | .clk_300mhz (clk_300mhz ) 361 | ); 362 | 363 | assign gpio_led[0] = mmcm_locked; 364 | assign gpio_led[1] = pll_locked; 365 | assign gpio_led[2] = axi_tg_irq_out; 366 | assign gpio_led[3] = mmcm_locked; 367 | assign gpio_led[4] = mmcm_locked; 368 | assign gpio_led[5] = mmcm_locked; 369 | assign gpio_led[6] = mmcm_locked; 370 | assign gpio_led[7] = mmcm_locked; 371 | 372 | endmodule // top 373 | -------------------------------------------------------------------------------- /test/sv/top.sv: -------------------------------------------------------------------------------- 1 | /** 2 | * 3 | */ 4 | 5 | `timescale 1ps / 1ps 6 | 7 | `include "defines.svh" 8 | 9 | module top ( 10 | input core_clk , 11 | input core_arstn , 12 | // NASTI interface 13 | input s_nasti_clk , 14 | input s_nasti_aresetn , 15 | //// NASTI slave write address channel 16 | input [ `C_NASTI_ID_WIDTH-1:0] s_nasti_aw_id , 17 | input [ `C_NASTI_ADDR_WIDTH-1:0] s_nasti_aw_addr , 18 | input [ 7:0] s_nasti_aw_len , 19 | input [ 2:0] s_nasti_aw_size , 20 | input [ 1:0] s_nasti_aw_burst , 21 | input s_nasti_aw_lock , 22 | input [ 3:0] s_nasti_aw_cache , 23 | input [ 2:0] s_nasti_aw_prot , 24 | input [ 3:0] s_nasti_aw_qos , 25 | input [ 3:0] s_nasti_aw_region , 26 | input [ `C_NASTI_USER_WIDTH-1:0] s_nasti_aw_user , 27 | input s_nasti_aw_valid , 28 | output s_nasti_aw_ready , 29 | //// NASTI slave write data channel 30 | input [ `C_NASTI_DATA_WIDTH-1:0] s_nasti_w_data , 31 | input [ (`C_NASTI_DATA_WIDTH/8)-1:0] s_nasti_w_strb , 32 | input s_nasti_w_last , 33 | input [ `C_NASTI_USER_WIDTH-1:0] s_nasti_w_user , 34 | input s_nasti_w_valid , 35 | output s_nasti_w_ready , 36 | //// NASTI slave write response channel 37 | output [ `C_NASTI_ID_WIDTH-1:0] s_nasti_b_id , 38 | output [ 1:0] s_nasti_b_resp , 39 | output [ `C_NASTI_USER_WIDTH-1:0] s_nasti_b_user , 40 | output s_nasti_b_valid , 41 | input s_nasti_b_ready , 42 | //// NASTI slave read address channel 43 | input [ `C_NASTI_ID_WIDTH-1:0] s_nasti_ar_id , 44 | input [ `C_NASTI_ADDR_WIDTH-1:0] s_nasti_ar_addr , 45 | input [ 7:0] s_nasti_ar_len , 46 | input [ 2:0] s_nasti_ar_size , 47 | input [ 1:0] s_nasti_ar_burst , 48 | input [ 0:0] s_nasti_ar_lock , 49 | input [ 3:0] s_nasti_ar_cache , 50 | input [ 2:0] s_nasti_ar_prot , 51 | input [ 3:0] s_nasti_ar_qos , 52 | input [ 3:0] s_nasti_ar_region , 53 | input [ `C_NASTI_USER_WIDTH-1:0] s_nasti_ar_user , 54 | input s_nasti_ar_valid , 55 | output s_nasti_ar_ready , 56 | //// NASTI slave read data channel 57 | output [ `C_NASTI_ID_WIDTH-1:0] s_nasti_r_id , 58 | output [ `C_NASTI_DATA_WIDTH-1:0] s_nasti_r_data , 59 | output [ 1:0] s_nasti_r_resp , 60 | output s_nasti_r_last , 61 | output [ `C_NASTI_USER_WIDTH-1:0] s_nasti_r_user , 62 | output s_nasti_r_valid , 63 | input s_nasti_r_ready , 64 | // // NASTI-Lite interface 65 | // input s_nastil_clk , 66 | // input s_nastil_aresetn , 67 | // //// NASTI-Lite slave write address channel 68 | // input [ `C_NASTIL_ADDR_WIDTH-1:0] s_nastil_aw_addr , 69 | // input [ 7:0] s_nastil_aw_len , 70 | // input [ 2:0] s_nastil_aw_size , 71 | // input [ 1:0] s_nastil_aw_burst , 72 | // input s_nastil_aw_lock , 73 | // input [ 3:0] s_nastil_aw_cache , 74 | // input [ 2:0] s_nastil_aw_prot , 75 | // input [ 3:0] s_nastil_aw_qos , 76 | // input [ 3:0] s_nastil_aw_region , 77 | // input [ `C_NASTIL_USER_WIDTH-1:0] s_nastil_aw_user , 78 | // input s_nastil_aw_valid , 79 | // output s_nastil_aw_ready , 80 | // //// NASTI-Lite slave write data channel 81 | // input [ `C_NASTIL_DATA_WIDTH-1:0] s_nastil_w_data , 82 | // input [(`C_NASTIL_DATA_WIDTH/8)-1:0] s_nastil_w_strb , 83 | // input s_nastil_w_last , 84 | // input [ `C_NASTIL_USER_WIDTH-1:0] s_nastil_w_user , 85 | // input s_nastil_w_valid , 86 | // output s_nastil_w_ready , 87 | // //// NASTI-Lite slave write response channel 88 | // output [ 1:0] s_nastil_b_resp , 89 | // output [ `C_NASTIL_USER_WIDTH-1:0] s_nastil_b_user , 90 | // output s_nastil_b_valid , 91 | // input s_nastil_b_ready , 92 | // //// NASTI-Lite slave read address channel 93 | // input [ `C_NASTIL_ADDR_WIDTH-1:0] s_nastil_ar_addr , 94 | // input [ 7:0] s_nastil_ar_len , 95 | // input [ 2:0] s_nastil_ar_size , 96 | // input [ 1:0] s_nastil_ar_burst , 97 | // input [ 0:0] s_nastil_ar_lock , 98 | // input [ 3:0] s_nastil_ar_cache , 99 | // input [ 2:0] s_nastil_ar_prot , 100 | // input [ 3:0] s_nastil_ar_qos , 101 | // input [ 3:0] s_nastil_ar_region , 102 | // input [ `C_NASTIL_USER_WIDTH-1:0] s_nastil_ar_user , 103 | // input s_nastil_ar_valid , 104 | // output s_nastil_ar_ready , 105 | // //// NASTI-Lite slave read data channel 106 | // output [ `C_NASTIL_DATA_WIDTH-1:0] s_nastil_r_data , 107 | // output [ 1:0] s_nastil_r_resp , 108 | // output s_nastil_r_last , 109 | // output [ `C_NASTIL_USER_WIDTH-1:0] s_nastil_r_user , 110 | // output s_nastil_r_valid , 111 | // input s_nastil_r_ready , 112 | // DFI interface 113 | //// DFI read interface 114 | output [ `C_DFI_ADDR_WIDTH-1:0] dfi_address , 115 | output [ `C_DFI_BANK_WIDTH-1:0] dfi_bank , 116 | output [ `C_DFI_CTRL_WIDTH-1:0] dfi_ras_n , 117 | output [ `C_DFI_CTRL_WIDTH-1:0] dfi_cas_n , 118 | output [ `C_DFI_CTRL_WIDTH-1:0] dfi_we_n , 119 | output [ `C_DFI_CS_WIDTH-1:0] dfi_cs_n , 120 | output [ `C_DFI_CS_WIDTH-1:0] dfi_cke , 121 | output [ `C_DFI_CS_WIDTH-1:0] dfi_odt , 122 | output [ `C_DFI_CS_WIDTH-1:0] dfi_reset_n , 123 | //// DFI write data interface 124 | output [ `C_DFI_DATAEN_WIDTH-1:0] dfi_wrdata_en , 125 | output [ `C_DFI_DATA_WIDTH-1:0] dfi_wrdata , 126 | output [ `C_DFI_DACS_WIDTH-1:0] dfi_wrdata_cs_n , 127 | output [ `C_DFI_DM_WIDTH-1:0] dfi_wrdata_mask , 128 | //// DFI read data interface 129 | output [ `C_DFI_DATAEN_WIDTH-1:0] dfi_rddata_en , 130 | input [ `C_DFI_DATA_WIDTH-1:0] dfi_rddata , 131 | output [ `C_DFI_DACS_WIDTH-1:0] dfi_rddata_cs_n , 132 | input [ `C_DFI_DATAEN_WIDTH-1:0] dfi_rddata_valid , 133 | //// DFI update interface 134 | output dfi_ctrlupd_req , 135 | input dfi_ctrlupd_ack , 136 | input dfi_phyupd_req , 137 | input dfi_phyupd_type , 138 | output dfi_phyupd_ack , 139 | //// DFI status interface 140 | output dfi_data_byte_disable , 141 | output dfi_dram_clk_disable , 142 | output [ 1:0] dfi_freq_ratio , 143 | output dfi_init_start , 144 | input dfi_init_complete , 145 | output dfi_parity_in , 146 | input dfi_alert_n , 147 | //// DFI training interface 148 | input dfi_rdlvl_req , 149 | input dfi_phy_rdlvl_cs_n , 150 | output dfi_rdlvl_en , 151 | input dfi_rdlvl_resp , 152 | input dfi_rdlvl_gate_req , 153 | input dfi_phy_rdlvl_gate_cs_n, 154 | output dfi_rdlvl_gate_en , 155 | input dfi_wrlvl_req , 156 | input dfi_phy_wrlvl_cs_n , 157 | output dfi_wrlvl_en , 158 | output dfi_wrlvl_strobe , 159 | input dfi_wrlvl_resp , 160 | output dfi_lvl_periodic , 161 | input dfi_phylvl_req_cs_n , 162 | output dfi_phylvl_ack_cs_n , 163 | //// DFI low power control interface 164 | output dfi_lp_ctrl_req , 165 | output dfi_lp_data_req , 166 | output dfi_lp_wakeup , 167 | input dfi_lp_ack , 168 | //// DFI error interface 169 | input [ `C_DFI_ERR_WIDTH-1:0] dfi_error , 170 | input [ (4*`C_DFI_ERR_WIDTH)-1:0] dfi_error_info 171 | ); 172 | 173 | nasti_if #( 174 | .C_NASTI_ID_WIDTH (`C_NASTI_ID_WIDTH ), 175 | .C_NASTI_ADDR_WIDTH(`C_NASTI_ADDR_WIDTH), 176 | .C_NASTI_DATA_WIDTH(`C_NASTI_DATA_WIDTH), 177 | .C_NASTI_USER_WIDTH(`C_NASTI_USER_WIDTH) 178 | ) nasti (); 179 | 180 | nasti_if #( 181 | .C_NASTI_ID_WIDTH (`C_NASTI_ID_WIDTH ), 182 | .C_NASTI_ADDR_WIDTH(`C_NASTIL_ADDR_WIDTH), 183 | .C_NASTI_DATA_WIDTH(`C_NASTIL_DATA_WIDTH), 184 | .C_NASTI_USER_WIDTH(`C_NASTI_USER_WIDTH ) 185 | ) nastilite (); 186 | 187 | dfi_if #( 188 | .C_DFI_ADDR_WIDTH (`C_DFI_ADDR_WIDTH ), 189 | .C_DFI_BANK_WIDTH (`C_DFI_BANK_WIDTH ), 190 | .C_DFI_CTRL_WIDTH (`C_DFI_CTRL_WIDTH ), 191 | .C_DFI_CS_WIDTH (`C_DFI_CS_WIDTH ), 192 | .C_DFI_DATAEN_WIDTH(`C_DFI_DATAEN_WIDTH), 193 | .C_DFI_DATA_WIDTH (`C_DFI_DATA_WIDTH ), 194 | .C_DFI_WRDACS_WIDTH(`C_DFI_DACS_WIDTH ), 195 | .C_DFI_DM_WIDTH (`C_DFI_DM_WIDTH ), 196 | .C_DFI_ALERT_WIDTH (`C_DFI_ALERT_WIDTH ), 197 | .C_DFI_ERR_WIDTH (`C_DFI_ERR_WIDTH ) 198 | ) dfi (); 199 | 200 | nasti_ddrx_mc #( 201 | .C_NASTI_ID_WIDTH (`C_NASTI_ID_WIDTH ), 202 | .C_NASTI_ADDR_WIDTH (`C_NASTI_ADDR_WIDTH ), 203 | .C_NASTI_DATA_WIDTH (`C_NASTI_DATA_WIDTH ), 204 | .C_NASTI_USER_WIDTH (`C_NASTI_USER_WIDTH ), 205 | .C_NASTIL_ADDR_WIDTH(`C_NASTIL_ADDR_WIDTH), 206 | .C_NASTIL_DATA_WIDTH(`C_NASTIL_DATA_WIDTH) 207 | ) i_nasti_ddrx_mc ( 208 | .core_clk (core_clk ), 209 | .core_arstn (core_arstn ), 210 | .s_nastilite_clk (s_nastil_clk ), 211 | .s_nastilite_aresetn(s_nastil_aresetn), 212 | .s_nastilite (nastilite ), 213 | .s_nasti_clk (s_nasti_clk ), 214 | .s_nasti_aresetn (s_nasti_aresetn ), 215 | .s_nasti (nasti ), 216 | .m_dfi (dfi ) 217 | ); 218 | 219 | 220 | assign nasti.aw_id = s_nasti_aw_id; 221 | assign nasti.aw_addr = s_nasti_aw_addr; 222 | assign nasti.aw_len = s_nasti_aw_len; 223 | assign nasti.aw_size = s_nasti_aw_size; 224 | assign nasti.aw_burst = s_nasti_aw_burst; 225 | assign nasti.aw_lock = s_nasti_aw_lock; 226 | assign nasti.aw_cache = s_nasti_aw_cache; 227 | assign nasti.aw_prot = s_nasti_aw_prot; 228 | assign nasti.aw_qos = s_nasti_aw_qos; 229 | assign nasti.aw_region = s_nasti_aw_region; 230 | assign nasti.aw_user = s_nasti_aw_user; 231 | assign nasti.aw_valid = s_nasti_aw_valid; 232 | assign s_nasti_aw_ready = nasti.aw_ready; 233 | assign nasti.w_data = s_nasti_w_data; 234 | assign nasti.w_strb = s_nasti_w_strb; 235 | assign nasti.w_last = s_nasti_w_last; 236 | assign nasti.w_user = s_nasti_w_user; 237 | assign nasti.w_valid = s_nasti_w_valid; 238 | assign s_nasti_w_ready = nasti.w_ready; 239 | assign s_nasti_b_id = nasti.b_id; 240 | assign s_nasti_b_resp = nasti.b_resp; 241 | assign s_nasti_b_user = nasti.b_user; 242 | assign s_nasti_b_valid = nasti.b_valid; 243 | assign nasti.b_ready = s_nasti_b_ready; 244 | assign nasti.ar_id = s_nasti_ar_id; 245 | assign nasti.ar_addr = s_nasti_ar_addr; 246 | assign nasti.ar_len = s_nasti_ar_len; 247 | assign nasti.ar_size = s_nasti_ar_size; 248 | assign nasti.ar_burst = s_nasti_ar_burst; 249 | assign nasti.ar_lock = s_nasti_ar_lock; 250 | assign nasti.ar_cache = s_nasti_ar_cache; 251 | assign nasti.ar_prot = s_nasti_ar_prot; 252 | assign nasti.ar_qos = s_nasti_ar_qos; 253 | assign nasti.ar_region = s_nasti_ar_region; 254 | assign nasti.ar_user = s_nasti_ar_user; 255 | assign nasti.ar_valid = s_nasti_ar_valid; 256 | assign s_nasti_ar_ready = nasti.ar_ready; 257 | assign s_nasti_r_id = nasti.r_id; 258 | assign s_nasti_r_data = nasti.r_data; 259 | assign s_nasti_r_resp = nasti.r_resp; 260 | assign s_nasti_r_last = nasti.r_last; 261 | assign s_nasti_r_user = nasti.r_user; 262 | assign s_nasti_r_valid = nasti.r_valid; 263 | assign nasti.r_ready = s_nasti_r_ready; 264 | 265 | // assign nastilite.aw_addr = s_nastil_aw_addr; 266 | // assign nastilite.aw_len = s_nastil_aw_len; 267 | // assign nastilite.aw_size = s_nastil_aw_size; 268 | // assign nastilite.aw_burst = s_nastil_aw_burst; 269 | // assign nastilite.aw_lock = s_nastil_aw_lock; 270 | // assign nastilite.aw_cache = s_nastil_aw_cache; 271 | // assign nastilite.aw_prot = s_nastil_aw_prot; 272 | // assign nastilite.aw_qos = s_nastil_aw_qos; 273 | // assign nastilite.aw_region = s_nastil_aw_region; 274 | // assign nastilite.aw_user = s_nastil_aw_user; 275 | // assign nastilite.aw_valid = s_nastil_aw_valid; 276 | // assign s_nastil_aw_ready = nastilite.aw_ready; 277 | // assign nastilite.w_data = s_nastil_w_data; 278 | // assign nastilite.w_strb = s_nastil_w_strb; 279 | // assign nastilite.w_last = s_nastil_w_last; 280 | // assign nastilite.w_user = s_nastil_w_user; 281 | // assign nastilite.w_valid = s_nastil_w_valid; 282 | // assign s_nastil_w_ready = nastilite.w_ready; 283 | // assign s_nastil_b_resp = nastilite.b_resp; 284 | // assign s_nastil_b_user = nastilite.b_user; 285 | // assign s_nastil_b_valid = nastilite.b_valid; 286 | // assign nastilite.b_ready = s_nastil_b_ready; 287 | // assign nastilite.ar_addr = s_nastil_ar_addr; 288 | // assign nastilite.ar_len = s_nastil_ar_len; 289 | // assign nastilite.ar_size = s_nastil_ar_size; 290 | // assign nastilite.ar_burst = s_nastil_ar_burst; 291 | // assign nastilite.ar_lock = s_nastil_ar_lock; 292 | // assign nastilite.ar_cache = s_nastil_ar_cache; 293 | // assign nastilite.ar_prot = s_nastil_ar_prot; 294 | // assign nastilite.ar_qos = s_nastil_ar_qos; 295 | // assign nastilite.ar_region = s_nastil_ar_region; 296 | // assign nastilite.ar_user = s_nastil_ar_user; 297 | // assign nastilite.ar_valid = s_nastil_ar_valid; 298 | // assign s_nastil_ar_ready = nastilite.ar_ready; 299 | // assign s_nastil_r_data = nastilite.r_data; 300 | // assign s_nastil_r_resp = nastilite.r_resp; 301 | // assign s_nastil_r_last = nastilite.r_last; 302 | // assign s_nastil_r_user = nastilite.r_user; 303 | // assign s_nastil_r_valid = nastilite.r_valid; 304 | // assign nastilite.r_ready = s_nastil_r_ready; 305 | 306 | assign dfi_address = dfi.dfi_address; 307 | assign dfi_bank = dfi.dfi_bank; 308 | assign dfi_ras_n = dfi.dfi_ras_n; 309 | assign dfi_cas_n = dfi.dfi_cas_n; 310 | assign dfi_we_n = dfi.dfi_we_n; 311 | assign dfi_cs_n = dfi.dfi_cs_n; 312 | assign dfi_cke = dfi.dfi_cke; 313 | assign dfi_odt = dfi.dfi_odt; 314 | assign dfi_reset_n = dfi.dfi_reset_n; 315 | assign dfi_wrdata_en = dfi.dfi_wrdata_en; 316 | assign dfi_wrdata = dfi.dfi_wrdata; 317 | assign dfi_wrdata_cs_n = dfi.dfi_wrdata_cs_n; 318 | assign dfi_wrdata_mask = dfi.dfi_wrdata_mask; 319 | assign dfi_rddata_en = dfi.dfi_rddata_en; 320 | assign dfi.dfi_rddata = dfi_rddata; 321 | assign dfi_rddata_cs_n = dfi.dfi_rddata_cs_n; 322 | assign dfi.dfi_rddata_valid = dfi_rddata_valid; 323 | assign dfi_ctrlupd_req = dfi.dfi_ctrlupd_req; 324 | assign dfi.dfi_ctrlupd_ack = dfi_ctrlupd_ack; 325 | assign dfi.dfi_phyupd_req = dfi_phyupd_req; 326 | assign dfi.dfi_phyupd_type = dfi_phyupd_type; 327 | assign dfi_phyupd_ack = dfi.dfi_phyupd_ack; 328 | assign dfi_data_byte_disable = dfi.dfi_data_byte_disable; 329 | assign dfi_dram_clk_disable = dfi.dfi_dram_clk_disable; 330 | assign dfi_freq_ratio = dfi.dfi_freq_ratio; 331 | assign dfi_init_start = dfi.dfi_init_start; 332 | assign dfi.dfi_init_complete = dfi_init_complete; 333 | assign dfi_parity_in = dfi.dfi_parity_in; 334 | assign dfi.dfi_alert_n = dfi_alert_n; 335 | assign dfi.dfi_rdlvl_req = dfi_rdlvl_req; 336 | assign dfi.dfi_phy_rdlvl_cs_n = dfi_phy_rdlvl_cs_n; 337 | assign dfi_rdlvl_en = dfi.dfi_rdlvl_en; 338 | assign dfi.dfi_rdlvl_resp = dfi_rdlvl_resp; 339 | assign dfi.dfi_rdlvl_gate_req = dfi_rdlvl_gate_req; 340 | assign dfi.dfi_phy_rdlvl_gate_cs_n = dfi_phy_rdlvl_gate_cs_n; 341 | assign dfi_rdlvl_gate_en = dfi.dfi_rdlvl_gate_en; 342 | assign dfi.dfi_wrlvl_req = dfi_wrlvl_req; 343 | assign dfi.dfi_phy_wrlvl_cs_n = dfi_phy_wrlvl_cs_n; 344 | assign dfi_wrlvl_en = dfi.dfi_wrlvl_en; 345 | assign dfi_wrlvl_strobe = dfi.dfi_wrlvl_strobe; 346 | assign dfi.dfi_wrlvl_resp = dfi_wrlvl_resp; 347 | assign dfi_lvl_periodic = dfi.dfi_lvl_periodic; 348 | assign dfi.dfi_phylvl_req_cs_n = dfi_phylvl_req_cs_n; 349 | assign dfi_phylvl_ack_cs_n = dfi.dfi_phylvl_ack_cs_n; 350 | assign dfi_lp_ctrl_req = dfi.dfi_lp_ctrl_req; 351 | assign dfi_lp_data_req = dfi.dfi_lp_data_req; 352 | assign dfi_lp_wakeup = dfi.dfi_lp_wakeup; 353 | assign dfi.dfi_lp_ack = dfi_lp_ack; 354 | assign dfi.dfi_error = dfi_error; 355 | assign dfi.dfi_error_info = dfi_error_info; 356 | 357 | endmodule // top 358 | -------------------------------------------------------------------------------- /fpga/kc705/sdram.xdc: -------------------------------------------------------------------------------- 1 | 2 | # clocks 3 | create_clock -period 5 [get_ports sysclk_p] 4 | set_property IOSTANDARD DIFF_SSTL15 [get_ports sysclk_p] 5 | set_property PACKAGE_PIN AD12 [get_ports sysclk_p] 6 | 7 | set_property IOSTANDARD DIFF_SSTL15 [get_ports sysclk_n] 8 | set_property PACKAGE_PIN AD11 [get_ports sysclk_n] 9 | 10 | # reset 11 | set_property IOSTANDARD LVCMOS15 [get_ports sysrst] 12 | set_property PACKAGE_PIN AB7 [get_ports sysrst] 13 | 14 | # GPIO LEDs 15 | set_property PACKAGE_PIN AB8 [get_ports gpio_led[0]] 16 | set_property IOSTANDARD LVCMOS15 [get_ports gpio_led[0]] 17 | 18 | set_property PACKAGE_PIN AA8 [get_ports gpio_led[1]] 19 | set_property IOSTANDARD LVCMOS15 [get_ports gpio_led[1]] 20 | 21 | set_property PACKAGE_PIN AC9 [get_ports gpio_led[2]] 22 | set_property IOSTANDARD LVCMOS15 [get_ports gpio_led[2]] 23 | 24 | set_property PACKAGE_PIN AB9 [get_ports gpio_led[3]] 25 | set_property IOSTANDARD LVCMOS15 [get_ports gpio_led[3]] 26 | 27 | set_property IOSTANDARD LVCMOS25 [get_ports gpio_led[4]] 28 | set_property PACKAGE_PIN AE26 [get_ports gpio_led[4]] 29 | 30 | set_property IOSTANDARD LVCMOS25 [get_ports gpio_led[5]] 31 | set_property PACKAGE_PIN G19 [get_ports gpio_led[5]] 32 | 33 | set_property IOSTANDARD LVCMOS25 [get_ports gpio_led[6]] 34 | set_property PACKAGE_PIN E18 [get_ports gpio_led[6]] 35 | 36 | set_property IOSTANDARD LVCMOS25 [get_ports gpio_led[7]] 37 | set_property PACKAGE_PIN F16 [get_ports gpio_led[7]] 38 | 39 | # DCI_CASCADE 40 | set_property DCI_CASCADE {32 34} [get_iobanks 33] 41 | 42 | # ddr3 dq 43 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[0]] 44 | set_property PACKAGE_PIN AA15 [get_ports ddr_dq[0]] 45 | set_property SLEW FAST [get_ports ddr_dq[0]] 46 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[0]] 47 | 48 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[1]] 49 | set_property PACKAGE_PIN AA16 [get_ports ddr_dq[1]] 50 | set_property SLEW FAST [get_ports ddr_dq[1]] 51 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[1]] 52 | 53 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[2]] 54 | set_property PACKAGE_PIN AC14 [get_ports ddr_dq[2]] 55 | set_property SLEW FAST [get_ports ddr_dq[2]] 56 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[2]] 57 | 58 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[3]] 59 | set_property PACKAGE_PIN AD14 [get_ports ddr_dq[3]] 60 | set_property SLEW FAST [get_ports ddr_dq[3]] 61 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[3]] 62 | 63 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[4]] 64 | set_property PACKAGE_PIN AA17 [get_ports ddr_dq[4]] 65 | set_property SLEW FAST [get_ports ddr_dq[4]] 66 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[4]] 67 | 68 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[5]] 69 | set_property PACKAGE_PIN AB15 [get_ports ddr_dq[5]] 70 | set_property SLEW FAST [get_ports ddr_dq[5]] 71 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[5]] 72 | 73 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[6]] 74 | set_property PACKAGE_PIN AE15 [get_ports ddr_dq[6]] 75 | set_property SLEW FAST [get_ports ddr_dq[6]] 76 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[6]] 77 | 78 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[7]] 79 | set_property PACKAGE_PIN Y15 [get_ports ddr_dq[7]] 80 | set_property SLEW FAST [get_ports ddr_dq[7]] 81 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[7]] 82 | 83 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[8]] 84 | set_property PACKAGE_PIN AB19 [get_ports ddr_dq[8]] 85 | set_property SLEW FAST [get_ports ddr_dq[8]] 86 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[8]] 87 | 88 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[9]] 89 | set_property PACKAGE_PIN AD16 [get_ports ddr_dq[9]] 90 | set_property SLEW FAST [get_ports ddr_dq[9]] 91 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[9]] 92 | 93 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[10]] 94 | set_property PACKAGE_PIN AC19 [get_ports ddr_dq[10]] 95 | set_property SLEW FAST [get_ports ddr_dq[10]] 96 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[10]] 97 | 98 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[11]] 99 | set_property PACKAGE_PIN AD17 [get_ports ddr_dq[11]] 100 | set_property SLEW FAST [get_ports ddr_dq[11]] 101 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[11]] 102 | 103 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[12]] 104 | set_property PACKAGE_PIN AA18 [get_ports ddr_dq[12]] 105 | set_property SLEW FAST [get_ports ddr_dq[12]] 106 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[12]] 107 | 108 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[13]] 109 | set_property PACKAGE_PIN AB18 [get_ports ddr_dq[13]] 110 | set_property SLEW FAST [get_ports ddr_dq[13]] 111 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[13]] 112 | 113 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[14]] 114 | set_property PACKAGE_PIN AE18 [get_ports ddr_dq[14]] 115 | set_property SLEW FAST [get_ports ddr_dq[14]] 116 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[14]] 117 | 118 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[15]] 119 | set_property PACKAGE_PIN AD18 [get_ports ddr_dq[15]] 120 | set_property SLEW FAST [get_ports ddr_dq[15]] 121 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[15]] 122 | 123 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[16]] 124 | set_property PACKAGE_PIN AG19 [get_ports ddr_dq[16]] 125 | set_property SLEW FAST [get_ports ddr_dq[16]] 126 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[16]] 127 | 128 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[17]] 129 | set_property PACKAGE_PIN AK19 [get_ports ddr_dq[17]] 130 | set_property SLEW FAST [get_ports ddr_dq[17]] 131 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[17]] 132 | 133 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[18]] 134 | set_property PACKAGE_PIN AG18 [get_ports ddr_dq[18]] 135 | set_property SLEW FAST [get_ports ddr_dq[18]] 136 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[18]] 137 | 138 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[19]] 139 | set_property PACKAGE_PIN AF18 [get_ports ddr_dq[19]] 140 | set_property SLEW FAST [get_ports ddr_dq[19]] 141 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[19]] 142 | 143 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[20]] 144 | set_property PACKAGE_PIN AH19 [get_ports ddr_dq[20]] 145 | set_property SLEW FAST [get_ports ddr_dq[20]] 146 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[20]] 147 | 148 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[21]] 149 | set_property PACKAGE_PIN AJ19 [get_ports ddr_dq[21]] 150 | set_property SLEW FAST [get_ports ddr_dq[21]] 151 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[21]] 152 | 153 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[22]] 154 | set_property PACKAGE_PIN AE19 [get_ports ddr_dq[22]] 155 | set_property SLEW FAST [get_ports ddr_dq[22]] 156 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[22]] 157 | 158 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[23]] 159 | set_property PACKAGE_PIN AD19 [get_ports ddr_dq[23]] 160 | set_property SLEW FAST [get_ports ddr_dq[23]] 161 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[23]] 162 | 163 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[24]] 164 | set_property PACKAGE_PIN AK16 [get_ports ddr_dq[24]] 165 | set_property SLEW FAST [get_ports ddr_dq[24]] 166 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[24]] 167 | 168 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[25]] 169 | set_property PACKAGE_PIN AJ17 [get_ports ddr_dq[25]] 170 | set_property SLEW FAST [get_ports ddr_dq[25]] 171 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[25]] 172 | 173 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[26]] 174 | set_property PACKAGE_PIN AG15 [get_ports ddr_dq[26]] 175 | set_property SLEW FAST [get_ports ddr_dq[26]] 176 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[26]] 177 | 178 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[27]] 179 | set_property PACKAGE_PIN AF15 [get_ports ddr_dq[27]] 180 | set_property SLEW FAST [get_ports ddr_dq[27]] 181 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[27]] 182 | 183 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[28]] 184 | set_property PACKAGE_PIN AH17 [get_ports ddr_dq[28]] 185 | set_property SLEW FAST [get_ports ddr_dq[28]] 186 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[28]] 187 | 188 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[29]] 189 | set_property PACKAGE_PIN AG14 [get_ports ddr_dq[29]] 190 | set_property SLEW FAST [get_ports ddr_dq[29]] 191 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[29]] 192 | 193 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[30]] 194 | set_property PACKAGE_PIN AH15 [get_ports ddr_dq[30]] 195 | set_property SLEW FAST [get_ports ddr_dq[30]] 196 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[30]] 197 | 198 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[31]] 199 | set_property PACKAGE_PIN AK15 [get_ports ddr_dq[31]] 200 | set_property SLEW FAST [get_ports ddr_dq[31]] 201 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[31]] 202 | 203 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[32]] 204 | set_property PACKAGE_PIN AK8 [get_ports ddr_dq[32]] 205 | set_property SLEW FAST [get_ports ddr_dq[32]] 206 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[32]] 207 | 208 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[33]] 209 | set_property PACKAGE_PIN AK6 [get_ports ddr_dq[33]] 210 | set_property SLEW FAST [get_ports ddr_dq[33]] 211 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[33]] 212 | 213 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[34]] 214 | set_property PACKAGE_PIN AG7 [get_ports ddr_dq[34]] 215 | set_property SLEW FAST [get_ports ddr_dq[34]] 216 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[34]] 217 | 218 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[35]] 219 | set_property PACKAGE_PIN AF7 [get_ports ddr_dq[35]] 220 | set_property SLEW FAST [get_ports ddr_dq[35]] 221 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[35]] 222 | 223 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[36]] 224 | set_property PACKAGE_PIN AF8 [get_ports ddr_dq[36]] 225 | set_property SLEW FAST [get_ports ddr_dq[36]] 226 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[36]] 227 | 228 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[37]] 229 | set_property PACKAGE_PIN AK4 [get_ports ddr_dq[37]] 230 | set_property SLEW FAST [get_ports ddr_dq[37]] 231 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[37]] 232 | 233 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[38]] 234 | set_property PACKAGE_PIN AJ8 [get_ports ddr_dq[38]] 235 | set_property SLEW FAST [get_ports ddr_dq[38]] 236 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[38]] 237 | 238 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[39]] 239 | set_property PACKAGE_PIN AJ6 [get_ports ddr_dq[39]] 240 | set_property SLEW FAST [get_ports ddr_dq[39]] 241 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[39]] 242 | 243 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[40]] 244 | set_property PACKAGE_PIN AH5 [get_ports ddr_dq[40]] 245 | set_property SLEW FAST [get_ports ddr_dq[40]] 246 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[40]] 247 | 248 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[41]] 249 | set_property PACKAGE_PIN AH6 [get_ports ddr_dq[41]] 250 | set_property SLEW FAST [get_ports ddr_dq[41]] 251 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[41]] 252 | 253 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[42]] 254 | set_property PACKAGE_PIN AJ2 [get_ports ddr_dq[42]] 255 | set_property SLEW FAST [get_ports ddr_dq[42]] 256 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[42]] 257 | 258 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[43]] 259 | set_property PACKAGE_PIN AH2 [get_ports ddr_dq[43]] 260 | set_property SLEW FAST [get_ports ddr_dq[43]] 261 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[43]] 262 | 263 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[44]] 264 | set_property PACKAGE_PIN AH4 [get_ports ddr_dq[44]] 265 | set_property SLEW FAST [get_ports ddr_dq[44]] 266 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[44]] 267 | 268 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[45]] 269 | set_property PACKAGE_PIN AJ4 [get_ports ddr_dq[45]] 270 | set_property SLEW FAST [get_ports ddr_dq[45]] 271 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[45]] 272 | 273 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[46]] 274 | set_property PACKAGE_PIN AK1 [get_ports ddr_dq[46]] 275 | set_property SLEW FAST [get_ports ddr_dq[46]] 276 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[46]] 277 | 278 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[47]] 279 | set_property PACKAGE_PIN AJ1 [get_ports ddr_dq[47]] 280 | set_property SLEW FAST [get_ports ddr_dq[47]] 281 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[47]] 282 | 283 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[48]] 284 | set_property PACKAGE_PIN AF1 [get_ports ddr_dq[48]] 285 | set_property SLEW FAST [get_ports ddr_dq[48]] 286 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[48]] 287 | 288 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[49]] 289 | set_property PACKAGE_PIN AF2 [get_ports ddr_dq[49]] 290 | set_property SLEW FAST [get_ports ddr_dq[49]] 291 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[49]] 292 | 293 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[50]] 294 | set_property PACKAGE_PIN AE4 [get_ports ddr_dq[50]] 295 | set_property SLEW FAST [get_ports ddr_dq[50]] 296 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[50]] 297 | 298 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[51]] 299 | set_property PACKAGE_PIN AE3 [get_ports ddr_dq[51]] 300 | set_property SLEW FAST [get_ports ddr_dq[51]] 301 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[51]] 302 | 303 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[52]] 304 | set_property PACKAGE_PIN AF3 [get_ports ddr_dq[52]] 305 | set_property SLEW FAST [get_ports ddr_dq[52]] 306 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[52]] 307 | 308 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[53]] 309 | set_property PACKAGE_PIN AF5 [get_ports ddr_dq[53]] 310 | set_property SLEW FAST [get_ports ddr_dq[53]] 311 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[53]] 312 | 313 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[54]] 314 | set_property PACKAGE_PIN AE1 [get_ports ddr_dq[54]] 315 | set_property SLEW FAST [get_ports ddr_dq[54]] 316 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[54]] 317 | 318 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[55]] 319 | set_property PACKAGE_PIN AE5 [get_ports ddr_dq[55]] 320 | set_property SLEW FAST [get_ports ddr_dq[55]] 321 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[55]] 322 | 323 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[56]] 324 | set_property PACKAGE_PIN AC1 [get_ports ddr_dq[56]] 325 | set_property SLEW FAST [get_ports ddr_dq[56]] 326 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[56]] 327 | 328 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[57]] 329 | set_property PACKAGE_PIN AD3 [get_ports ddr_dq[57]] 330 | set_property SLEW FAST [get_ports ddr_dq[57]] 331 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[57]] 332 | 333 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[58]] 334 | set_property PACKAGE_PIN AC4 [get_ports ddr_dq[58]] 335 | set_property SLEW FAST [get_ports ddr_dq[58]] 336 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[58]] 337 | 338 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[59]] 339 | set_property PACKAGE_PIN AC5 [get_ports ddr_dq[59]] 340 | set_property SLEW FAST [get_ports ddr_dq[59]] 341 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[59]] 342 | 343 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[60]] 344 | set_property PACKAGE_PIN AE6 [get_ports ddr_dq[60]] 345 | set_property SLEW FAST [get_ports ddr_dq[60]] 346 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[60]] 347 | 348 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[61]] 349 | set_property PACKAGE_PIN AD6 [get_ports ddr_dq[61]] 350 | set_property SLEW FAST [get_ports ddr_dq[61]] 351 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[61]] 352 | 353 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[62]] 354 | set_property PACKAGE_PIN AC2 [get_ports ddr_dq[62]] 355 | set_property SLEW FAST [get_ports ddr_dq[62]] 356 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[62]] 357 | 358 | set_property IOSTANDARD SSTL15_T_DCI [get_ports ddr_dq[63]] 359 | set_property PACKAGE_PIN AD4 [get_ports ddr_dq[63]] 360 | set_property SLEW FAST [get_ports ddr_dq[63]] 361 | set_property VCCAUX_IO HIGH [get_ports ddr_dq[63]] 362 | 363 | # ddr3 dqs 364 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[0]] 365 | set_property PACKAGE_PIN AC15 [get_ports ddr_dqs_n[0]] 366 | set_property SLEW FAST [get_ports ddr_dqs_n[0]] 367 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[0]] 368 | 369 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[0]] 370 | set_property PACKAGE_PIN AC16 [get_ports ddr_dqs_p[0]] 371 | set_property SLEW FAST [get_ports ddr_dqs_p[0]] 372 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[0]] 373 | 374 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[1]] 375 | set_property PACKAGE_PIN Y18 [get_ports ddr_dqs_n[1]] 376 | set_property SLEW FAST [get_ports ddr_dqs_n[1]] 377 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[1]] 378 | 379 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[1]] 380 | set_property PACKAGE_PIN Y19 [get_ports ddr_dqs_p[1]] 381 | set_property SLEW FAST [get_ports ddr_dqs_p[1]] 382 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[1]] 383 | 384 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[2]] 385 | set_property PACKAGE_PIN AK18 [get_ports ddr_dqs_n[2]] 386 | set_property SLEW FAST [get_ports ddr_dqs_n[2]] 387 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[2]] 388 | 389 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[2]] 390 | set_property PACKAGE_PIN AJ18 [get_ports ddr_dqs_p[2]] 391 | set_property SLEW FAST [get_ports ddr_dqs_p[2]] 392 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[2]] 393 | 394 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[3]] 395 | set_property PACKAGE_PIN AJ16 [get_ports ddr_dqs_n[3]] 396 | set_property SLEW FAST [get_ports ddr_dqs_n[3]] 397 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[3]] 398 | 399 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[3]] 400 | set_property PACKAGE_PIN AH16 [get_ports ddr_dqs_p[3]] 401 | set_property SLEW FAST [get_ports ddr_dqs_p[3]] 402 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[3]] 403 | 404 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[4]] 405 | set_property PACKAGE_PIN AJ7 [get_ports ddr_dqs_n[4]] 406 | set_property SLEW FAST [get_ports ddr_dqs_n[4]] 407 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[4]] 408 | 409 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[4]] 410 | set_property PACKAGE_PIN AH7 [get_ports ddr_dqs_p[4]] 411 | set_property SLEW FAST [get_ports ddr_dqs_p[4]] 412 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[4]] 413 | 414 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[5]] 415 | set_property PACKAGE_PIN AH1 [get_ports ddr_dqs_n[5]] 416 | set_property SLEW FAST [get_ports ddr_dqs_n[5]] 417 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[5]] 418 | 419 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[5]] 420 | set_property PACKAGE_PIN AG2 [get_ports ddr_dqs_p[5]] 421 | set_property SLEW FAST [get_ports ddr_dqs_p[5]] 422 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[5]] 423 | 424 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[6]] 425 | set_property PACKAGE_PIN AG3 [get_ports ddr_dqs_n[6]] 426 | set_property SLEW FAST [get_ports ddr_dqs_n[6]] 427 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[6]] 428 | 429 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[6]] 430 | set_property PACKAGE_PIN AG4 [get_ports ddr_dqs_p[6]] 431 | set_property SLEW FAST [get_ports ddr_dqs_p[6]] 432 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[6]] 433 | 434 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_n[7]] 435 | set_property PACKAGE_PIN AD1 [get_ports ddr_dqs_n[7]] 436 | set_property SLEW FAST [get_ports ddr_dqs_n[7]] 437 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_n[7]] 438 | 439 | set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr_dqs_p[7]] 440 | set_property PACKAGE_PIN AD2 [get_ports ddr_dqs_p[7]] 441 | set_property SLEW FAST [get_ports ddr_dqs_p[7]] 442 | set_property VCCAUX_IO HIGH [get_ports ddr_dqs_p[7]] 443 | 444 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[0]] 445 | set_property PACKAGE_PIN AH12 [get_ports ddr_addr[0]] 446 | set_property SLEW FAST [get_ports ddr_addr[0]] 447 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[0]] 448 | 449 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[1]] 450 | set_property PACKAGE_PIN AG13 [get_ports ddr_addr[1]] 451 | set_property SLEW FAST [get_ports ddr_addr[1]] 452 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[1]] 453 | 454 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[2]] 455 | set_property PACKAGE_PIN AG12 [get_ports ddr_addr[2]] 456 | set_property SLEW FAST [get_ports ddr_addr[2]] 457 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[2]] 458 | 459 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[3]] 460 | set_property PACKAGE_PIN AF12 [get_ports ddr_addr[3]] 461 | set_property SLEW FAST [get_ports ddr_addr[3]] 462 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[3]] 463 | 464 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[4]] 465 | set_property PACKAGE_PIN AJ12 [get_ports ddr_addr[4]] 466 | set_property SLEW FAST [get_ports ddr_addr[4]] 467 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[4]] 468 | 469 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[5]] 470 | set_property PACKAGE_PIN AJ13 [get_ports ddr_addr[5]] 471 | set_property SLEW FAST [get_ports ddr_addr[5]] 472 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[5]] 473 | 474 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[6]] 475 | set_property PACKAGE_PIN AJ14 [get_ports ddr_addr[6]] 476 | set_property SLEW FAST [get_ports ddr_addr[6]] 477 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[6]] 478 | 479 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[7]] 480 | set_property PACKAGE_PIN AH14 [get_ports ddr_addr[7]] 481 | set_property SLEW FAST [get_ports ddr_addr[7]] 482 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[7]] 483 | 484 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[8]] 485 | set_property PACKAGE_PIN AK13 [get_ports ddr_addr[8]] 486 | set_property SLEW FAST [get_ports ddr_addr[8]] 487 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[8]] 488 | 489 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[9]] 490 | set_property PACKAGE_PIN AK14 [get_ports ddr_addr[9]] 491 | set_property SLEW FAST [get_ports ddr_addr[9]] 492 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[9]] 493 | 494 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[10]] 495 | set_property PACKAGE_PIN AF13 [get_ports ddr_addr[10]] 496 | set_property SLEW FAST [get_ports ddr_addr[10]] 497 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[10]] 498 | 499 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[11]] 500 | set_property PACKAGE_PIN AE13 [get_ports ddr_addr[11]] 501 | set_property SLEW FAST [get_ports ddr_addr[11]] 502 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[11]] 503 | 504 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[12]] 505 | set_property PACKAGE_PIN AJ11 [get_ports ddr_addr[12]] 506 | set_property SLEW FAST [get_ports ddr_addr[12]] 507 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[12]] 508 | 509 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[13]] 510 | set_property PACKAGE_PIN AH11 [get_ports ddr_addr[13]] 511 | set_property SLEW FAST [get_ports ddr_addr[13]] 512 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[13]] 513 | 514 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[14]] 515 | set_property PACKAGE_PIN AK10 [get_ports ddr_addr[14]] 516 | set_property SLEW FAST [get_ports ddr_addr[14]] 517 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[14]] 518 | 519 | set_property IOSTANDARD SSTL15 [get_ports ddr_addr[15]] 520 | set_property PACKAGE_PIN AK11 [get_ports ddr_addr[15]] 521 | set_property SLEW FAST [get_ports ddr_addr[15]] 522 | set_property VCCAUX_IO HIGH [get_ports ddr_addr[15]] 523 | 524 | # ddr3 ba 525 | set_property IOSTANDARD SSTL15 [get_ports ddr_ba[0]] 526 | set_property PACKAGE_PIN AH9 [get_ports ddr_ba[0]] 527 | set_property SLEW FAST [get_ports ddr_ba[0]] 528 | set_property VCCAUX_IO HIGH [get_ports ddr_ba[0]] 529 | 530 | set_property IOSTANDARD SSTL15 [get_ports ddr_ba[1]] 531 | set_property PACKAGE_PIN AG9 [get_ports ddr_ba[1]] 532 | set_property SLEW FAST [get_ports ddr_ba[1]] 533 | set_property VCCAUX_IO HIGH [get_ports ddr_ba[1]] 534 | 535 | set_property IOSTANDARD SSTL15 [get_ports ddr_ba[2]] 536 | set_property PACKAGE_PIN AK9 [get_ports ddr_ba[2]] 537 | set_property SLEW FAST [get_ports ddr_ba[2]] 538 | set_property VCCAUX_IO HIGH [get_ports ddr_ba[2]] 539 | 540 | # ddr3 ras 541 | set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n] 542 | set_property PACKAGE_PIN AD9 [get_ports ddr_ras_n] 543 | set_property SLEW FAST [get_ports ddr_ras_n] 544 | set_property VCCAUX_IO HIGH [get_ports ddr_ras_n] 545 | 546 | # ddr3 cas 547 | set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n] 548 | set_property PACKAGE_PIN AC11 [get_ports ddr_cas_n] 549 | set_property SLEW FAST [get_ports ddr_cas_n] 550 | set_property VCCAUX_IO HIGH [get_ports ddr_cas_n] 551 | 552 | # ddr3 we 553 | set_property IOSTANDARD SSTL15 [get_ports ddr_we_n] 554 | set_property PACKAGE_PIN AE9 [get_ports ddr_we_n] 555 | set_property SLEW FAST [get_ports ddr_we_n] 556 | set_property VCCAUX_IO HIGH [get_ports ddr_we_n] 557 | 558 | # ddr3 reset 559 | set_property IOSTANDARD LVCMOS15 [get_ports ddr_reset_n] 560 | set_property PACKAGE_PIN AK3 [get_ports ddr_reset_n] 561 | set_property SLEW FAST [get_ports ddr_reset_n] 562 | set_property VCCAUX_IO HIGH [get_ports ddr_reset_n] 563 | 564 | # ddr3 ck 565 | set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_ck_n[0]] 566 | set_property PACKAGE_PIN AH10 [get_ports ddr_ck_n[0]] 567 | set_property SLEW FAST [get_ports ddr_ck_n[0]] 568 | set_property VCCAUX_IO HIGH [get_ports ddr_ck_n[0]] 569 | 570 | set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_ck_p[0]] 571 | set_property PACKAGE_PIN AG10 [get_ports ddr_ck_p[0]] 572 | set_property SLEW FAST [get_ports ddr_ck_p[0]] 573 | set_property VCCAUX_IO HIGH [get_ports ddr_ck_p[0]] 574 | 575 | set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_ck_n[1]] 576 | set_property PACKAGE_PIN AF11 [get_ports ddr_ck_n[1]] 577 | set_property SLEW FAST [get_ports ddr_ck_n[1]] 578 | set_property VCCAUX_IO HIGH [get_ports ddr_ck_n[1]] 579 | 580 | set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_ck_p[1]] 581 | set_property PACKAGE_PIN AE11 [get_ports ddr_ck_p[1]] 582 | set_property SLEW FAST [get_ports ddr_ck_p[1]] 583 | set_property VCCAUX_IO HIGH [get_ports ddr_ck_p[1]] 584 | 585 | # ddr3 cke 586 | set_property IOSTANDARD SSTL15 [get_ports ddr_cke[0]] 587 | set_property PACKAGE_PIN AF10 [get_ports ddr_cke[0]] 588 | set_property SLEW FAST [get_ports ddr_cke[0]] 589 | set_property VCCAUX_IO HIGH [get_ports ddr_cke[0]] 590 | 591 | set_property IOSTANDARD SSTL15 [get_ports ddr_cke[1]] 592 | set_property PACKAGE_PIN AE10 [get_ports ddr_cke[1]] 593 | set_property SLEW FAST [get_ports ddr_cke[1]] 594 | set_property VCCAUX_IO HIGH [get_ports ddr_cke[1]] 595 | 596 | # ddr3 cs 597 | set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n[0]] 598 | set_property PACKAGE_PIN AC12 [get_ports ddr_cs_n[0]] 599 | set_property SLEW FAST [get_ports ddr_cs_n[0]] 600 | set_property VCCAUX_IO HIGH [get_ports ddr_cs_n[0]] 601 | 602 | set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n[1]] 603 | set_property PACKAGE_PIN AE8 [get_ports ddr_cs_n[1]] 604 | set_property SLEW FAST [get_ports ddr_cs_n[1]] 605 | set_property VCCAUX_IO HIGH [get_ports ddr_cs_n[1]] 606 | 607 | # ddr3 dm 608 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[0]] 609 | set_property PACKAGE_PIN Y16 [get_ports ddr_dm[0]] 610 | set_property SLEW FAST [get_ports ddr_dm[0]] 611 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[0]] 612 | 613 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[1]] 614 | set_property PACKAGE_PIN AB17 [get_ports ddr_dm[1]] 615 | set_property SLEW FAST [get_ports ddr_dm[1]] 616 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[1]] 617 | 618 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[2]] 619 | set_property PACKAGE_PIN AF17 [get_ports ddr_dm[2]] 620 | set_property SLEW FAST [get_ports ddr_dm[2]] 621 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[2]] 622 | 623 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[3]] 624 | set_property PACKAGE_PIN AE16 [get_ports ddr_dm[3]] 625 | set_property SLEW FAST [get_ports ddr_dm[3]] 626 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[3]] 627 | 628 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[4]] 629 | set_property PACKAGE_PIN AK5 [get_ports ddr_dm[4]] 630 | set_property SLEW FAST [get_ports ddr_dm[4]] 631 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[4]] 632 | 633 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[5]] 634 | set_property PACKAGE_PIN AJ3 [get_ports ddr_dm[5]] 635 | set_property SLEW FAST [get_ports ddr_dm[5]] 636 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[5]] 637 | 638 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[6]] 639 | set_property PACKAGE_PIN AF6 [get_ports ddr_dm[6]] 640 | set_property SLEW FAST [get_ports ddr_dm[6]] 641 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[6]] 642 | 643 | set_property IOSTANDARD SSTL15 [get_ports ddr_dm[7]] 644 | set_property PACKAGE_PIN AC7 [get_ports ddr_dm[7]] 645 | set_property SLEW FAST [get_ports ddr_dm[7]] 646 | set_property VCCAUX_IO HIGH [get_ports ddr_dm[7]] 647 | 648 | # ddr3 odt 649 | set_property IOSTANDARD SSTL15 [get_ports ddr_odt[0]] 650 | set_property PACKAGE_PIN AD8 [get_ports ddr_odt[0]] 651 | set_property SLEW FAST [get_ports ddr_odt[0]] 652 | set_property VCCAUX_IO HIGH [get_ports ddr_odt[0]] 653 | 654 | set_property IOSTANDARD SSTL15 [get_ports ddr_odt[1]] 655 | set_property PACKAGE_PIN AC10 [get_ports ddr_odt[1]] 656 | set_property SLEW FAST [get_ports ddr_odt[1]] 657 | set_property VCCAUX_IO HIGH [get_ports ddr_odt[1]] 658 | 659 | # set_property LOC BUFIO_X1Y0 [get_cells i_phy_top/gen_dqs_32[0].BUFIO_inst_n] 660 | # set_property LOC BUFIO_X1Y1 [get_cells i_phy_top/gen_dqs_32[1].BUFIO_inst_n] 661 | # set_property LOC BUFIO_X1Y2 [get_cells i_phy_top/gen_dqs_32[2].BUFIO_inst_n] 662 | # set_property LOC BUFIO_X1Y3 [get_cells i_phy_top/gen_dqs_32[3].BUFIO_inst_n] 663 | --------------------------------------------------------------------------------