├── .gitignore
├── Reports
    ├── Report MS2.docx
    ├── Report MS3.docx
    └── Final Report.docx
├── Test
    ├── testCase.txt
    └── cpu_tb_sim.wcfg
├── RTL
    ├── Others
    │   ├── Decoder5_32.v
    │   ├── Mux2_1.v
    │   ├── ShiftLeft1.v
    │   ├── Mux4_1.v
    │   ├── SignExtend.v
    │   └── SSDDriver.v
    ├── ALU
    │   ├── Full_Adder.v
    │   ├── AdderSub.v
    │   ├── RippleAdder.v
    │   └── ALU.v
    ├── Registers
    │   ├── FlipFlop.v
    │   ├── RegWLoad.v
    │   ├── RegFile.v
    │   └── regfileModel.v
    ├── ClkInverter.v
    ├── Adder.v
    ├── Other Units
    │   ├── ClkDiv.v
    │   ├── ImmGen.v
    │   └── ForwardUnit.v
    ├── TestBench
    │   ├── clkDiv_tb.v
    │   ├── cpu_tb.v
    │   └── mem_tb.v
    ├── memAddressSelectUnit.v
    ├── RegSrcUnit.v
    ├── InterruptAddressGenerator.v
    ├── Control
    │   ├── ALUControl.v
    │   ├── BranchUnit.v
    │   └── ControlUnit.v
    ├── PIC.v
    ├── RISCV_TOP.v
    ├── TMRGenerator.v
    ├── Interrupt_Detector.v
    ├── Memory
    │   └── Memory.v
    ├── Global
    │   └── values.v
    ├── CSRRegFile.v
    ├── decompression.v
    └── RISCV.v
└── README.md


/.gitignore:
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1 | # Created by .ignore support plugin (hsz.mobi)
2 | .idea/
3 | 


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/Reports/Report MS2.docx:
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https://raw.githubusercontent.com/djzenma/RV32IC-CPU/HEAD/Reports/Report MS2.docx


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/Reports/Report MS3.docx:
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https://raw.githubusercontent.com/djzenma/RV32IC-CPU/HEAD/Reports/Report MS3.docx


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/Reports/Final Report.docx:
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https://raw.githubusercontent.com/djzenma/RV32IC-CPU/HEAD/Reports/Final Report.docx


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/Test/testCase.txt:
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1 | 93 00 80 01 13 01 20 00 93 01 30 00 67 81 00 00 13 02 40 00 93 02 50 00 17 8F 00 00 13 03 60 00 


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/RTL/Others/Decoder5_32.v:
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 1 | // file: Decoder5_32.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module Decoder5_32 (
 7 |     input en,
 8 |     input [4:0] dec_in, 
 9 |     output [31:0] dec_out
10 | );
11 | 
12 |     assign dec_out = en?(1<<dec_in):0;
13 | endmodule
14 | 
15 | 


--------------------------------------------------------------------------------
/RTL/ALU/Full_Adder.v:
--------------------------------------------------------------------------------
 1 | // file: Full_Adder.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module Full_Adder (
 7 |     input a, 
 8 |     input b, 
 9 |     input cin,
10 |     output sum, 
11 |     output cout 
12 | );
13 | 
14 |   assign sum = a ^ b ^ cin;
15 |   assign cout = ((a ^ b) & cin) | (a & b);
16 | endmodule
17 | 
18 | 


--------------------------------------------------------------------------------
/RTL/Others/Mux2_1.v:
--------------------------------------------------------------------------------
 1 | // file: Mux2_1.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module Mux2_1 (
 7 |     sel,
 8 |     in1,
 9 |     in2,
10 |     out
11 | );
12 |     parameter N=1;
13 |     output [N-1:0] out;
14 |     input [N-1:0] in1, in2;
15 |     input sel;
16 |     
17 |     assign out = (sel) ? in2 : in1;
18 | endmodule
19 | 
20 | 


--------------------------------------------------------------------------------
/RTL/Registers/FlipFlop.v:
--------------------------------------------------------------------------------
 1 | // file: FlipFlop.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module FlipFlop(
 7 |     input clk, 
 8 |     input rst, 
 9 |     input d, 
10 |     output reg q
11 | );
12 | 
13 |     always @(posedge clk or posedge rst) begin
14 |         if(rst == 1)
15 |             q<=0;
16 |         else
17 |             q<=d;
18 |     end
19 | 
20 | endmodule
21 | 
22 | 


--------------------------------------------------------------------------------
/RTL/ALU/AdderSub.v:
--------------------------------------------------------------------------------
 1 | // file: AdderSub.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module AdderSub (
 7 |     input sub,
 8 |     input [31:0] a,
 9 |     input [31:0] b,
10 |     output [31:0] s
11 | );
12 | 
13 |     wire co;
14 |     wire ci;
15 |     wire [31:0] b2;
16 |     
17 |     assign ci=sub?1:0;
18 |     assign b2=sub?~b:b;
19 |     
20 |     RippleAdder r(a,b2,ci,s,co);
21 | endmodule
22 | 
23 | 


--------------------------------------------------------------------------------
/RTL/Others/ShiftLeft1.v:
--------------------------------------------------------------------------------
 1 | // file: ShiftLeft1.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module ShiftLeft1 (
 7 |     input [31:0] d_in,
 8 |     output [31:0] d_out 
 9 | );
10 | 
11 |     assign d_out = {d_in,1'b0};
12 | endmodule
13 | 
14 | module ShiftLeft2 (
15 |     input [25:0] d_in,
16 |     output [31:0] d_out 
17 | );
18 | 
19 |     assign d_out = {d_in,2'b0};
20 | endmodule
21 | 
22 | 
23 | module ShiftLeft #(parameter shamt=0) (
24 |     input [31:0] d_in,
25 |     output [31:0] d_out 
26 | );
27 | 
28 | assign d_out = d_in << shamt;
29 | 
30 | endmodule


--------------------------------------------------------------------------------
/RTL/ALU/RippleAdder.v:
--------------------------------------------------------------------------------
 1 | // file: RippleAdder.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module RippleAdder (
 7 |     input[31:0] a, 
 8 |     input[31:0] b,
 9 |     input ci,
10 |     output[31:0] s,
11 |     output co,
12 |     output last_ci
13 | );
14 |     
15 |     wire [32:0] cs;
16 |     
17 |     assign cs[0] = ci;
18 |     assign co = cs[32];
19 |     assign last_ci = cs[31];
20 | 
21 |     genvar i;
22 |     generate
23 |     for(i=0;i<32;i=i+1)
24 |         Full_Adder a1(a[i],b[i],cs[i],s[i],cs[i+1]);
25 |     endgenerate
26 |     
27 | endmodule
28 | 
29 | 


--------------------------------------------------------------------------------
/RTL/Others/Mux4_1.v:
--------------------------------------------------------------------------------
 1 | // file: Mux4_1.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module Mux4_1 (
 7 |     sel,
 8 |     in1,
 9 |     in2,
10 |     in3,
11 |     in4,
12 |     out
13 | );
14 | 
15 |     parameter N=1;
16 |     input [1:0] sel;
17 |     input [N-1:0] in1, in2, in3, in4;
18 |     output reg [N-1:0] out;
19 |     
20 |     always @(*) begin
21 |         case(sel)
22 |             2'b00: out = in1;
23 |             2'b01: out = in2;
24 |             2'b10: out = in3;
25 |             2'b11: out = in4;
26 |         endcase
27 |     end
28 |     
29 | endmodule
30 | 
31 | 


--------------------------------------------------------------------------------
/RTL/ClkInverter.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/01/2018 03:59:00 PM
 7 | // Design Name: 
 8 | // Module Name: ClkInverter
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module ClkInverter(
24 |     input clk_i,
25 |     output clk_o
26 |     );
27 |     
28 |     assign clk_o = ~clk_i;
29 | endmodule
30 | 


--------------------------------------------------------------------------------
/RTL/Adder.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/23/2018 11:04:07 PM
 7 | // Design Name: 
 8 | // Module Name: Adder
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module Adder(input[31:0] a,
24 |             input [31:0] b,
25 |             output[31:0] res);
26 |             
27 |             assign res = a + b;
28 | endmodule
29 | 


--------------------------------------------------------------------------------
/RTL/Other Units/ClkDiv.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/27/2018 12:15:23 AM
 7 | // Design Name: 
 8 | // Module Name: ClkDiv
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module ClkDiv(input clk, input rst, output reg clk_o);
24 | 
25 | always @(posedge clk, posedge rst) begin
26 |     if(rst)
27 |         clk_o = 1'b1;
28 |     else
29 |         clk_o = ~clk_o;
30 | end
31 | endmodule


--------------------------------------------------------------------------------
/RTL/Others/SignExtend.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/27/2018 06:41:27 PM
 7 | // Design Name: 
 8 | // Module Name: SignExtend
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module SignExtend #(parameter size=16) (input [size:0] in, output [31:0] out);
24 | 
25 | wire[size-1:0] temp;
26 | 
27 | genvar i;
28 | 
29 | generate
30 |     for(i=0; i<size; i=i+1) 
31 |         assign temp[i] = in[size-1];
32 | endgenerate
33 | 
34 | assign out = {temp, in};
35 | 
36 | endmodule
37 | 


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/RTL/TestBench/clkDiv_tb.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/27/2018 12:18:05 AM
 7 | // Design Name: 
 8 | // Module Name: clkDiv_tb
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module clkDiv_tb( );
24 | reg clk, rst;
25 | wire clk_o, clk_oRF;
26 | 
27 | ClkDiv clkD (clk, rst, clk_o);
28 | ClkDivRF clkDRF (clk, rst, clk_oRF);
29 | 
30 | always begin
31 | clk=~clk;
32 | #10;
33 | end
34 | 
35 | initial begin
36 | clk = 0;
37 | rst = 1;
38 | #15;
39 | rst = 0;
40 | end
41 | 
42 | endmodule
43 | 


--------------------------------------------------------------------------------
/RTL/Registers/RegWLoad.v:
--------------------------------------------------------------------------------
 1 | // file: RegWLoad.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module RegWLoad(
 7 |     clk,
 8 |     rst,
 9 |     load,
10 |     data_in,
11 |     data_out
12 | );
13 | 
14 |     parameter SIZE = 32;
15 | 
16 |     input               clk, rst, load;
17 |     input  [SIZE - 1:0] data_in;
18 |     output [SIZE - 1:0] data_out;
19 | 
20 |     wire   [SIZE - 1:0] ds;
21 | 
22 |     genvar i;
23 |     generate
24 |         for (i = 0;i < SIZE; i = i + 1) begin
25 |             Mux2_1 m (.sel (load),
26 |                       .in1 (data_out[i]),
27 |                       .in2 (data_in[i]),
28 |                       .out (ds[i]));
29 |             FlipFlop f (.clk (clk),
30 |                         .rst (rst),
31 |                         .d   (ds[i]),
32 |                         .q   (data_out[i]));
33 |         end
34 |     endgenerate
35 | 
36 | endmodule
37 | 
38 | 


--------------------------------------------------------------------------------
/RTL/memAddressSelectUnit.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/06/2018 10:28:16 PM
 7 | // Design Name: 
 8 | // Module Name: memAddressSelectUnit
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module memAddressSelectUnit(
24 |     input clk_fast,
25 |     input clk_slow,
26 |     output reg select
27 |     );
28 |     
29 |     always @ (posedge clk_fast) begin
30 |         if(clk_slow == 0)
31 |             select = 0;
32 |         else
33 |             select = 1;
34 |     end
35 |     
36 | endmodule
37 | 


--------------------------------------------------------------------------------
/RTL/TestBench/cpu_tb.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/26/2018 09:19:49 PM
 7 | // Design Name: 
 8 | // Module Name: cpu_tb
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module cpu_tb();
24 | 
25 | reg clk, rst;
26 | 
27 | 
28 | RISCV_TOP cpuTest (    
29 |     .clk(clk),
30 |     .rst(rst),
31 |     .en_inter(1'b0),
32 |     .intReq(8'b0),
33 |     .nmi(1'b0)
34 | );
35 | 
36 | always begin
37 | clk=~clk;
38 | #10;
39 | end
40 | 
41 | initial begin
42 | clk=0;
43 | rst=1;
44 | 
45 | #20;
46 | rst=0;
47 | end
48 | 
49 | endmodule
50 | 


--------------------------------------------------------------------------------
/RTL/Other Units/ImmGen.v:
--------------------------------------------------------------------------------
 1 | // file: ImmGen.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module ImmGen (
 7 |     input  wire [31:0]  IR,
 8 |     output reg  [31:0]  Imm
 9 | );
10 | 
11 | always @(*) begin
12 | 	case (`OPCODE)
13 | 		`OPCODE_Arith_I   : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
14 | 		`OPCODE_Store     :     Imm = { {21{IR[31]}}, IR[30:25], IR[11:8], IR[7] };
15 | 		`OPCODE_LUI       :     Imm = { IR[31], IR[30:20], IR[19:12], 12'b0 };
16 | 		`OPCODE_AUIPC     :     Imm = { IR[31], IR[30:20], IR[19:12], 12'b0 };
17 | 		`OPCODE_JAL       : 	Imm = { {12{IR[31]}}, IR[19:12], IR[20], IR[30:25], IR[24:21], 1'b0 };
18 | 		`OPCODE_JALR      : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] };
19 | 		`OPCODE_Branch    : 	Imm = { {20{IR[31]}}, IR[7], IR[30:25], IR[11:8], 1'b0};
20 | 		default           : 	Imm = { {21{IR[31]}}, IR[30:25], IR[24:21], IR[20] }; // IMM_I
21 | 	endcase 
22 | end
23 | 
24 | endmodule
25 | 
26 | 
27 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
 1 | # RV32IC-CPU
 2 | Implementation of the RV32IC Processor in Verilog HDL
 3 | 
 4 | <h1>Directories</h1>
 5 | The Repository contains the following Directories:
 6 | <h3>RTL</h3>
 7 | Contains all the verilog implementations
 8 | 
 9 | <h3>Test</h3>
10 | Contains the testCase.txt file where you can put your own testcases (assembly instructions), and contains a simulation configuration file that you can use to see a nice looking simulation.
11 | 
12 | <h3>Reports</h3>
13 | Contains a full detailed documentation about the CPU implementation.
14 | 
15 | <h1>Test it yourself!</h1>
16 | If you want to test your own code on my RISCV32IC CPU, please do the following: <br>
17 | 1. convert your code to hex, <br>
18 | 2. then go to the file “RTL/TestBench/testCase.txt” in the project directory and paste your code into it. <br>
19 | 3. Please make sure to change the path of the "testCase.txt" file in the $readmemh() function in the Memory module according to your own path.
20 | 
21 | 
22 | 


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/RTL/RegSrcUnit.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/03/2018 10:23:44 PM
 7 | // Design Name: 
 8 | // Module Name: RegSrcUnit
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module RegSrcUnit(
24 |         input clk,
25 |         input regWrite,
26 |         output reg regMuxSelect
27 | );
28 | 
29 |     always @(negedge clk) begin
30 |         if(!regWrite && !clk)
31 |         if(regWrite)
32 |             regMuxSelect = 1'b1;
33 |         else
34 |             regMuxSelect = 1'b0;
35 |     end
36 |     
37 |     always @(posedge clk) begin
38 |         regMuxSelect = 1'b0;
39 |      end
40 |         
41 |     
42 |     
43 | endmodule
44 | 


--------------------------------------------------------------------------------
/RTL/InterruptAddressGenerator.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/13/2018 08:05:36 PM
 7 | // Design Name: 
 8 | // Module Name: InterruptAddressGenerator
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module InterruptAddressGenerator(
24 |     input             interruptF,
25 |     input      [2:0]  interSel,
26 |     input      [2:0]  intNum,
27 |     output reg [31:0] addr
28 | );
29 | 
30 | always @(*) begin
31 |     if(interruptF) begin
32 |         case(interSel)
33 |             `NMI:   addr = 32'h10;
34 |             `ECALL: addr = 32'h20;
35 |             `EBREAK:addr = 32'h30;
36 |             `TMR:   addr = 32'h40;
37 |             `INT:   addr = 32'h100 + (intNum * 32'h10);
38 |         endcase
39 |     end
40 | end
41 | 
42 | endmodule
43 | 


--------------------------------------------------------------------------------
/RTL/TestBench/mem_tb.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/26/2018 10:34:55 PM
 7 | // Design Name: 
 8 | // Module Name: mem_tb
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module mem_tb();
24 | 
25 | reg         clk, rst, MemRead, MemWrite;
26 | reg  [1:0]  mode;
27 |     reg  [5:0]  addr;
28 |     reg  [31:0] data_in;
29 |     wire [31:0] data_out;
30 |     
31 |     Memory MEM (clk, rst,MemRead,MemWrite,mode,addr,data_in,data_out);
32 |     
33 |     always begin
34 |     clk=~clk;
35 |     #10;
36 |     
37 |     end
38 |     
39 |     initial begin
40 |     clk=0;
41 |     rst=1;
42 |     MemWrite = 0;
43 |     mode=0;
44 |     addr=0;
45 |     data_in=15;
46 |     
47 |     #20;
48 |     MemRead=1;
49 |     
50 |     end
51 | 
52 | endmodule
53 | 


--------------------------------------------------------------------------------
/RTL/Control/ALUControl.v:
--------------------------------------------------------------------------------
 1 | // file: ALUControl.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module ALUControl(
 7 |     input [1:0]      ALUOp,
 8 |     input [2:0]      func3,
 9 |     input [6:0]      func7,
10 |     output reg [3:0] sel
11 | );
12 | 
13 |     always @(*) begin         // TODO :: Remove negedge clk
14 |         case (ALUOp)
15 |             `ALUOP_ADD: sel = `ALU_ADD; //add
16 |             `ALUOP_SUB: sel = `ALU_SUB;  //sub
17 |             `ALUOP_OTHER: begin
18 |                 sel =   (func3 == `F3_SLL) ? `ALU_SLL:      // TODO :: convert to case
19 |                         (func3 == `F3_SLT) ? `ALU_SLT:
20 |                         (func3 == `F3_SLTU) ? `ALU_SLTU:
21 |                         (func3 == `F3_XOR) ? `ALU_XOR:
22 |                         (func3 == `F3_SRL) ? `ALU_SRL:
23 |                         (func3 == `F3_OR) ? `ALU_OR:
24 |                         (func3 == `F3_AND) ? `ALU_AND:
25 |                         (func3 == `F3_SRL && func7 == `F7_SRA) ? `ALU_SRA:
26 |                         `ALU_ADD;
27 |             end
28 |             default : sel = `ALU_PASS;
29 |         endcase
30 |     end
31 | 
32 | endmodule
33 | 
34 | 


--------------------------------------------------------------------------------
/RTL/PIC.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/13/2018 06:16:18 PM
 7 | // Design Name: 
 8 | // Module Name: PIC
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module PIC(input [7:0] intReq, output Int, output[2:0] Int_Num);
24 |     assign Int = (intReq[0] || intReq[1] || intReq[2] || intReq[3] || intReq[4] || intReq[5] || intReq[6] || intReq[7]);
25 |     assign Int_Num =    (intReq[0]) ? 3'b000 :
26 |                         (intReq[1]) ? 3'b001 :   
27 |                         (intReq[2]) ? 3'b010 :
28 |                         (intReq[3]) ? 3'b011 :   
29 |                         (intReq[4]) ? 3'b100 :
30 |                         (intReq[5]) ? 3'b101 :   
31 |                         (intReq[6]) ? 3'b110 :
32 |                         3'b111; 
33 | endmodule
34 | 


--------------------------------------------------------------------------------
/RTL/Other Units/ForwardUnit.v:
--------------------------------------------------------------------------------
 1 | // file: ForwardUnit.v
 2 | // author: @mobs_11
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | 
 7 | module ForwardUnit(
 8 |     input [4:0]     ID_EX_Rs1,
 9 |     input [4:0]     ID_EX_Rs2,
10 |     input           EX_MEM_RegWrite,
11 |     input [4:0]     EX_MEM_Rd,
12 |     input           MEM_WB_RegWrite,
13 |     input [4:0]     MEM_WB_Rd,
14 |     output reg[1:0] ForwardA,
15 |     output reg[1:0] ForwardB
16 | 
17 | );  
18 | 
19 |     always @ (*) begin
20 |         if (EX_MEM_RegWrite && (EX_MEM_Rd != 0) && (EX_MEM_Rd == ID_EX_Rs1))
21 |             ForwardA = 2'b10;
22 |         else if (MEM_WB_RegWrite && (MEM_WB_Rd != 0) && (MEM_WB_Rd == ID_EX_Rs1) && !(EX_MEM_RegWrite && (EX_MEM_Rd != 0) && (EX_MEM_Rd == ID_EX_Rs1) ) )
23 |             ForwardA = 2'b01;
24 |         else 
25 |             ForwardA = 2'b00;
26 |     end
27 |     
28 |     always @ (*) begin
29 |         if (EX_MEM_RegWrite && (EX_MEM_Rd != 0) && (EX_MEM_Rd == ID_EX_Rs2))
30 |             ForwardB = 2'b10;
31 |         else if (MEM_WB_RegWrite && (MEM_WB_Rd != 0) && (MEM_WB_Rd == ID_EX_Rs2) && !(EX_MEM_RegWrite && (EX_MEM_Rd != 0) && (EX_MEM_Rd == ID_EX_Rs2) ) )
32 |             ForwardB = 2'b01;
33 |         else
34 |             ForwardB = 2'b00;
35 |     end
36 |     
37 | endmodule
38 | 
39 | 


--------------------------------------------------------------------------------
/RTL/RISCV_TOP.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/13/2018 06:13:20 PM
 7 | // Design Name: 
 8 | // Module Name: RISCV_TOP
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module RISCV_TOP(    
24 |     input       clk,
25 |     input       rst,
26 |     input       en_inter,
27 |     input [7:0] intReq,
28 |     input       nmi,
29 |     output [31:0] out
30 | );
31 | 
32 | wire int; 
33 | wire [2:0] int_num;
34 | 
35 | PIC pic (.intReq(intReq), .Int(int), .Int_Num(int_num));
36 | 
37 | RISCV CPU (
38 |         .clk_i(clk),
39 |         .rst(rst),
40 |         .en_inter(1'b1),
41 |         .int(int),
42 |         .int_num(int_num),
43 |         .nmi(nmi),
44 |         .en_nmi(1'b0),
45 |         .en_ecall(1'b1),
46 |         .en_ebreak(1'b0),
47 |         .en_int(1'b0),
48 |         .en_tmr(1'b1),
49 |         .limit(0),
50 |         .out(out)
51 | );          
52 | 
53 | endmodule
54 | 


--------------------------------------------------------------------------------
/RTL/TMRGenerator.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/13/2018 07:06:58 PM
 7 | // Design Name: 
 8 | // Module Name: NmiGenerator
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module TMRGenerator(
24 |     input         clk,
25 |     input         rst,
26 |     input [31:0]  limit,
27 |     output reg    tmrF
28 | );
29 | 
30 | reg [31:0] count;
31 | 
32 | always @ (posedge clk) begin
33 |     if(rst) begin
34 |         count <= 32'b0;
35 |         tmrF  <= 1'b0;
36 |     end
37 |     else begin
38 |         if(count == limit) begin
39 |             count <= 32'b0;
40 |             tmrF <= 1'b1;
41 |         end
42 |         if(count == limit + 1) begin
43 |             count <= 32'b0;
44 |             tmrF <= 1'b0;
45 |         end
46 |         else begin
47 |             count <= count + 1;
48 |             tmrF <= 1'b0;
49 |         end
50 |     end
51 | end
52 | 
53 | endmodule
54 | 


--------------------------------------------------------------------------------
/RTL/Control/BranchUnit.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/29/2018 06:53:37 PM
 7 | // Design Name: 
 8 | // Module Name: BranchUnit
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | module BranchUnit(  input branch,
23 |                     input s,
24 |                     input z,
25 |                     input c,
26 |                     input v,
27 |                     input [2:0] func3,
28 |                     output reg branchTaken);
29 |                     
30 |     always @ * begin
31 |         case(func3)
32 |             `BR_BEQ:  branchTaken = z & branch;         
33 | 			`BR_BNE:  branchTaken = ~z & branch;        
34 | 			`BR_BLT:  branchTaken = (s != v) & branch;
35 | 			`BR_BGE:  branchTaken = (s == v) & branch;  
36 | 			`BR_BLTU: branchTaken = (~c) & branch;      
37 | 			`BR_BGEU: branchTaken = (c) & branch; 
38 | 			default:  branchTaken = 1'b0;
39 | 		endcase
40 |     end
41 |     
42 | endmodule
43 | 
44 | 
45 | 


--------------------------------------------------------------------------------
/RTL/Registers/RegFile.v:
--------------------------------------------------------------------------------
 1 | // file: RegFile.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module RegFile(
 7 |     input         clk,
 8 |     input         clk_slow,
 9 |     input         rst,
10 |     input         WriteEn,
11 |     input  [4:0]  rs1_rd,
12 |     input  [4:0]  rs2,
13 |     input  [31:0] write_data,
14 |     output reg [31:0] read_data1,
15 |     output reg [31:0] read_data2
16 | );
17 | 
18 |     wire [31:0] xs[31:0];
19 |     wire [31:0] load;
20 |     wire write;
21 |     
22 |     Decoder5_32 dec (   .en(WriteEn),
23 |                         .dec_in(rs1_rd), 
24 |                         .dec_out(load)
25 |     );
26 | 
27 |     RegWLoad r0 (clk, rst, 1'b0, write_data, xs[0]); //Reg x0 cannot be written (load = 0)
28 |     genvar i;
29 |     generate
30 |         for (i = 1;i < 32; i = i + 1)
31 |             RegWLoad ri (
32 |                 .clk(clk),
33 |                 .rst(rst),
34 |                 .load(load[i] & write),
35 |                 .data_in(write_data),
36 |                 .data_out(xs[i])
37 |             );
38 |     endgenerate
39 |     
40 |     assign write = (clk ^ clk_slow);
41 |     
42 |     always @(negedge clk) begin
43 | //       if(~WriteEn) begin
44 |             read_data1 = xs[rs1_rd];
45 |             read_data2 = xs[rs2];
46 | //       end
47 |     end
48 |     
49 | endmodule
50 | 
51 | 


--------------------------------------------------------------------------------
/RTL/Registers/regfileModel.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 10/26/2018 11:02:30 PM
 7 | // Design Name: 
 8 | // Module Name: regfileModel
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | 
23 | module regfileModel( input clk, input rst, input en, input[4:0] rs1, input[4:0] rs2, input[4:0] rd, input[31:0] RegW, output[31:0] RegR1, output[31:0] RegR2);
24 |     wire[4:0] regsrc;
25 |     RegFile rf (.clk        (~clk),
26 |                 .rst        (rst),
27 |                 .WriteEn    (en),
28 |                 .rs1_rd     (regsrc),
29 |                 .rs2        (rs2),
30 |                 .write_data (RegW),
31 |                 .read_data1 (RegR1),
32 |                 .read_data2 (RegR2)
33 |         );
34 |         Mux2_1#(5) MuxregFile (.sel (en),
35 |                                  .in1 (rs1),
36 |                                  .in2 (rd),
37 |                                  .out (regsrc)
38 |         );
39 |                   
40 | endmodule
41 | 


--------------------------------------------------------------------------------
/RTL/Interrupt_Detector.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date: 11/13/2018 06:34:31 PM
 7 | // Design Name: 
 8 | // Module Name: Interrupt_Detector
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool Versions: 
12 | // Description: 
13 | // 
14 | // Dependencies: 
15 | // 
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | // 
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | module Interrupt_Detector(
23 |         input       nmi,
24 |         input       ecall,
25 |         input       ebreak,
26 |         input       int,
27 |         input       tmr,
28 |         
29 |         input       en_inter,
30 |         
31 |         input       en_ecall,
32 |         input       en_int,
33 |         input       en_tmr,
34 |         
35 |         output      interFlag,
36 |         output [2:0] interSel 
37 | );
38 | 
39 | assign interFlag = ( (nmi) || (ebreak) || (en_int && int && en_inter) || (en_tmr && tmr && en_inter) || (en_ecall && ecall && en_inter) );
40 | 
41 | assign interSel =   (nmi)    ? `NMI:
42 |                     (ebreak) ? `EBREAK :
43 |                     (tmr)    ? `TMR:
44 |                     (int)    ? `INT:
45 |                     `ECALL;
46 | endmodule
47 | 


--------------------------------------------------------------------------------
/RTL/ALU/ALU.v:
--------------------------------------------------------------------------------
 1 | // file: ALU.v
 2 | // author: Engineer Mazen Amr & Engineer Mohamed Hossam
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module ALU(
 7 |     input [3:0]       sel,
 8 |     input [31:0]      a,
 9 |     input [31:0]      b,
10 |     output reg [31:0] result,
11 |     output            z,
12 |     output            s,
13 |     output            c,
14 |     output            v
15 | );
16 | 
17 |     wire [31:0] sum, difference;
18 |     reg  [31:0] tempA, tempB;
19 |     wire        cout, ci;
20 | 
21 |     always @ (*) begin
22 |         case (sel)
23 |             
24 |             `ALU_ADD: begin
25 |                 result = a + b; 
26 | //                $display("Add result: %d + %d = %d", a, b, result);
27 |             end
28 |             `ALU_SUB: begin
29 |                 result = a - b;
30 |                 $display("Add result: %d + %d = %d", a, b, result);
31 |             end
32 |             `ALU_PASS:result = result;  
33 |             `ALU_OR:  result = a | b;
34 |             `ALU_AND: result = a & b;
35 |             `ALU_XOR: result = a ^ b;
36 |             `ALU_SRL: result = a >> b;
37 |             `ALU_SRA: result = a >>> b;
38 |             `ALU_SLL: result = a << b;
39 |             `ALU_SLT: result = (a<b) ? 1 : 0;
40 |             `ALU_SLTU: begin
41 |                 if (a[31])
42 |                     tempA = (~a) + 1;
43 |                 else
44 |                     tempA = tempA;
45 |                 if (b[31])
46 |                     tempB = (~b) + 1;
47 |                 else
48 |                     tempB = tempB;
49 |                 result = ( tempA < tempB ) ? 1 : 0;
50 |             end
51 |             default: result = 0;
52 |         endcase
53 | 
54 |     end
55 |     
56 |     RippleAdder rca (
57 |         .a(a), 
58 |         .b(b),
59 |         .ci(1'b0),
60 |         .s(sum),
61 |         .co(cout),
62 |         .last_ci(ci)
63 |     );
64 |     assign difference = a - b;
65 |     assign z = (difference == 0) ? 1 : 0;
66 |     assign s = result[31];
67 |     assign c = cout;
68 |     assign v = (ci^cout);
69 |     
70 | endmodule
71 | 
72 | 


--------------------------------------------------------------------------------
/RTL/Others/SSDDriver.v:
--------------------------------------------------------------------------------
 1 | // file: SSDDriver.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module SSDDriver(
 7 |     input            clk,
 8 |     input [12:0]     num,
 9 |     output reg [3:0] Anode,
10 |     output reg [6:0] LED_out
11 | );
12 | 
13 |     reg [3:0]  LED_BCD;
14 |     reg [19:0] refresh_counter = 0; // 20-bit counter
15 |     wire [1:0] LED_activating_counter;
16 | 
17 |     always @(posedge clk)
18 |         begin
19 |             refresh_counter <= refresh_counter + 1;
20 |         end
21 | 
22 |     assign LED_activating_counter = refresh_counter[19:18];
23 | 
24 |     always @ (* )
25 |         begin
26 |             case (LED_activating_counter)
27 |                 2'b00: begin
28 |                     Anode = 4'b0111;
29 |                     LED_BCD = num / 1000;
30 |                 end
31 |                 2'b01: begin
32 |                     Anode = 4'b1011;
33 |                     LED_BCD = (num % 1000) / 100;
34 |                 end
35 |                 2'b10: begin
36 |                     Anode = 4'b1101;
37 |                     LED_BCD = ((num % 1000) % 100) / 10;
38 |                 end
39 |                 2'b11: begin
40 |                     Anode = 4'b1110;
41 |                     LED_BCD = ((num % 1000) % 100) % 10;
42 |                 end
43 |             endcase
44 |         end
45 | 
46 |     always @ (* )
47 |         begin
48 |             case (LED_BCD)
49 |                 4'b0000: LED_out = 7'b0000001; // "0"
50 |                 4'b0001: LED_out = 7'b1001111; // "1"
51 |                 4'b0010: LED_out = 7'b0010010; // "2"
52 |                 4'b0011: LED_out = 7'b0000110; // "3"
53 |                 4'b0100: LED_out = 7'b1001100; // "4"
54 |                 4'b0101: LED_out = 7'b0100100; // "5"
55 |                 4'b0110: LED_out = 7'b0100000; // "6"
56 |                 4'b0111: LED_out = 7'b0001111; // "7"
57 |                 4'b1000: LED_out = 7'b0000000; // "8"
58 |                 4'b1001: LED_out = 7'b0000100; // "9"
59 |                 default: LED_out = 7'b0000001; // "0"
60 |             endcase
61 |         end
62 | endmodule
63 | 
64 | 


--------------------------------------------------------------------------------
/RTL/Memory/Memory.v:
--------------------------------------------------------------------------------
 1 | // file: DataMem.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 |  module Memory(
 7 |     input         clk,
 8 |     input         clk_i,
 9 |     input         rst,
10 |     input         MemRead,
11 |     input         MemWrite,
12 |     input  [2:0]  mode,
13 |     input  [31:0] addr,
14 |     input  [31:0] data_in,
15 |     output reg [31:0] data_out
16 | );
17 | 
18 |     reg [7:0] mem [4095:0];
19 |     wire [31:0] extended16, extended24;
20 |     
21 |     always @(*) begin
22 |         if (clk)
23 |             data_out = {mem[addr+3], mem[addr+2], mem[addr+1], mem[addr]}; 
24 |         else begin
25 |                 case(mode)
26 |                     3'b000: data_out = {mem[addr+3], mem[addr+2], mem[addr+1], mem[addr]}; 
27 |                     3'b001: data_out = {16'b0, mem[addr+1], mem[addr]};   // loading unsigned HW
28 |                     3'b010: data_out = {24'b0,mem[addr]};                // loading unsigned  B
29 |                     3'b011: data_out = extended16;                        // loading signed HW
30 |                     3'b100: data_out = extended24;                        // loading signed  B
31 |                 endcase
32 |             end
33 |     end
34 |     
35 |     SignExtend #(16) x16 ( .in( {mem[addr+1], mem[addr]} ), .out(extended16));
36 |     SignExtend #(24) x24 ( .in(mem[addr]) , .out(extended24));
37 |      
38 | 
39 |     always @(posedge rst or negedge clk)
40 |         begin
41 |             if (rst == 1) begin 
42 |                 $readmemh("C:/Users/eidma/Desktop/PrjSim/testCase.txt",mem);
43 | //                // CSRC
44 | //                mem[8] = 8'h73;
45 | //                mem[9] = 8'he2;
46 | //                mem[10] = 8'h24;
47 | //                mem[11] = 8'hb0;
48 | //                // MRET
49 | //                mem[32] = 8'b01110011;
50 | //                mem[33] = 8'b00000000;
51 | //                mem[34] = 8'b00100000;
52 | //                mem[35] = 8'b00110000;
53 |             end
54 |             else begin
55 |                 if (MemWrite && clk_i) begin
56 |                     case(mode)
57 |                         3'b000: begin 
58 |                             mem[addr] =  data_in[7:0];
59 |                             mem[addr+1] =  data_in[15:8];
60 |                             mem[addr+2] =  data_in[23:16];
61 |                             mem[addr+3] =  data_in[31:24];
62 |                         end 
63 |                         3'b001: begin
64 |                             $display("address = %d", addr);
65 |                             mem[addr] =  data_in[7:0];
66 |                             mem[addr+1] =  data_in[15:8];
67 |                         end
68 |                             3'b010: mem[addr] = data_in[7:0]; 
69 |                     endcase                
70 |                 end
71 |             end
72 |             
73 |     end
74 |    
75 | endmodule
76 | 
77 | 
78 | 


--------------------------------------------------------------------------------
/RTL/Global/values.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 10/26/2018 07:51:20 PM
  7 | // Design Name: 
  8 | // Module Name: values
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | `define     IR_rs1          19:15
 24 | `define     IR_rs2          24:20
 25 | `define     IR_rd           11:7
 26 | `define     IR_opcode       6:2
 27 | `define     IR_funct3       14:12
 28 | `define     IR_funct7       31:25
 29 | `define     IR_shamt        24:20
 30 | `define     IR_csr          31:20
 31 | 
 32 | 
 33 | `define     OPCODE_Branch   5'b11_000
 34 | `define     OPCODE_Load     5'b00_000
 35 | `define     OPCODE_Store    5'b01_000
 36 | `define     OPCODE_JALR     5'b11_001
 37 | `define     OPCODE_JAL      5'b11_011
 38 | `define     OPCODE_Arith_I  5'b00_100
 39 | `define     OPCODE_Arith_R  5'b01_100
 40 | `define     OPCODE_AUIPC    5'b00_101
 41 | `define     OPCODE_LUI      5'b01_101
 42 | `define     OPCODE_SYSTEM   5'b11_100 
 43 | `define     OPCODE_Custom   5'b10_001
 44 | 
 45 | // FUNC3
 46 | `define     F3_ADD          3'b000
 47 | `define     F3_SLL          3'b001
 48 | `define     F3_SLT          3'b010
 49 | `define     F3_SLTU         3'b011
 50 | `define     F3_XOR          3'b100
 51 | `define     F3_SRL          3'b101
 52 | `define     F3_OR           3'b110
 53 | `define     F3_AND          3'b111
 54 | `define     PRIV            3'b000
 55 | 
 56 | // FUNC7
 57 | `define     F7_SRA          7'b0100000
 58 | `define     F7_SUB          7'b0100000
 59 | 
 60 | // FUNC12
 61 | `define     MRET            12'h302
 62 | 
 63 | `define     BR_BEQ          3'b000
 64 | `define     BR_BNE          3'b001
 65 | `define     BR_BLT          3'b100
 66 | `define     BR_BGE          3'b101
 67 | `define     BR_BLTU         3'b110
 68 | `define     BR_BGEU         3'b111
 69 | 
 70 | `define     S_SW            3'b010
 71 | `define     S_SH            3'b001
 72 | `define     S_SB            3'b000
 73 | 
 74 | `define     L_LW            3'b010
 75 | `define     L_LH            3'b001
 76 | `define     L_LB            3'b000
 77 | `define     L_LBU           3'b100
 78 | `define     L_LHU           3'b101
 79 | 
 80 | `define     OPCODE          IR[`IR_opcode]
 81 | 
 82 | // ALUOp R Format
 83 | `define     ALUOP_ADD       2'b00
 84 | `define     ALUOP_SUB       2'b01
 85 | `define     ALUOP_OTHER     2'b10
 86 | 
 87 | // ALUOp R Format
 88 | `define     ALU_ADD         4'b00_00
 89 | `define     ALU_SUB         4'b00_01
 90 | `define     ALU_PASS        4'b00_11
 91 | `define     ALU_OR          4'b01_00
 92 | `define     ALU_AND         4'b01_01
 93 | `define     ALU_XOR         4'b01_11
 94 | `define     ALU_SRL         4'b10_00
 95 | `define     ALU_SRA         4'b10_10
 96 | `define     ALU_SLL         4'b10_01
 97 | `define     ALU_SLT         4'b11_01
 98 | `define     ALU_SLTU        4'b11_11
 99 | 
100 | 
101 | `define     MEM_W           3'b000
102 | `define     MEM_HW          3'b001
103 | `define     MEM_B           3'b010
104 | 
105 | // Interrupt Selections
106 | `define     NMI             3'b000
107 | `define     EBREAK          3'b001
108 | `define     TMR             3'b010
109 | `define     INT             3'b011
110 | `define     ECALL           3'b100
111 | 
112 | `define MEPC_ADDR   12'h341
113 | `define MCYCLE_ADDR   12'hb00
114 | `define MTIME_ADDR   12'hb01
115 | `define MINSTRET_ADDR   12'hb02
116 | `define MTIMECMP_ADDR   12'hb03
117 | `define MIE_ADDR   12'h304
118 | 
119 | `define     CODE_SEGMENT    32'h000
120 | 
121 | `define     SYS_EC_EB       3'b000
122 | `define     SYS_CSRRW       3'b001
123 | `define     SYS_CSRRS       3'b010
124 | `define     SYS_CSRRC       3'b011
125 | `define     SYS_CSRRWI      3'b101
126 | `define     SYS_CSRRSI      3'b110
127 | `define     SYS_CSRRCI      3'b111
128 | 


--------------------------------------------------------------------------------
/RTL/Control/ControlUnit.v:
--------------------------------------------------------------------------------
 1 | // file: ControlUnit.v
 2 | // author: @cherifsalama
 3 | 
 4 | `timescale 1ns/1ns
 5 | 
 6 | module ControlUnit(
 7 |     input [31:0] instr,
 8 |     input  [4:0] opcode,
 9 |     output       Branch,
10 |     output [1:0] Jump,
11 |     output       MemRead,
12 |     output       MemToReg,
13 |     output [1:0] ALUOp,
14 |     output       MemWrite,
15 |     output       ALUSrc,
16 |     output       RegWrite, 
17 |     output [2:0] Mode,
18 |     output       Lui,
19 |     output       Auipc,
20 |     output       ECall,
21 |     output       EBreak,
22 |     output       MRET,
23 |     output       CSRWrite,
24 |     output       CSRSet,
25 |     output       CSRClear,
26 |     output       CSRI
27 | );
28 |     
29 |     assign Jump = (opcode == `OPCODE_JAL) ? 2'b01: 
30 |                   (opcode == `OPCODE_JALR) ? 2'b10:
31 |                   2'b00;
32 |                   
33 |     assign Branch = (opcode == `OPCODE_Branch) ? 1'b1 : 1'b0;
34 |     assign MemRead = (opcode == `OPCODE_Load) ? 1'b1 : 1'b0;
35 |     assign MemToReg = (opcode == `OPCODE_Load) ? 1'b1: 1'b0;
36 |     assign MemWrite = (opcode == `OPCODE_Store) ? 1'b1 : 1'b0;
37 |     assign ALUSrc = ((opcode == `OPCODE_Arith_I) || (opcode == `OPCODE_Store) || (opcode == `OPCODE_Load) || (opcode == `OPCODE_AUIPC)) ? 1'b1 : 1'b0;
38 |     assign RegWrite = ((opcode == `OPCODE_Load) || (opcode == `OPCODE_Arith_R) || (opcode == `OPCODE_Arith_I) || (opcode == `OPCODE_JAL) || (opcode == `OPCODE_JALR) || (opcode == `OPCODE_LUI) || (opcode == `OPCODE_AUIPC) || (CSRWrite) ) ? 1'b1 : 1'b0;
39 |     
40 |     assign Mode = (opcode == `OPCODE_Store && instr[14:12] == `S_SW) ? `MEM_W:
41 |                     (opcode == `OPCODE_Store && instr[14:12] == `S_SH) ? `MEM_HW:
42 |                     (opcode == `OPCODE_Store && instr[14:12] == `S_SB) ? `MEM_B:
43 |                     (opcode == `OPCODE_Load && instr[14:12] == `L_LW) ? `MEM_W:
44 |                     (opcode == `OPCODE_Load && instr[14:12] == `L_LH) ? `MEM_HW:
45 |                     (opcode == `OPCODE_Load && instr[14:12] == `L_LB &&  instr[1:0] != 2'b00) ? `MEM_B:
46 |                     (opcode == `OPCODE_Load && instr[14:12] == `L_LBU) ? `MEM_B:
47 |                     (opcode == `OPCODE_Load && instr[14:12] == `L_LHU) ? `MEM_HW:
48 |                     `MEM_W;      // Default reading mode is word
49 |                     
50 |     assign ALUOp =  ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_ADD && instr[31:25] == `F7_SUB)?  `ALUOP_SUB : // R aluOps
51 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_ADD)?  `ALUOP_ADD :      
52 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_SLL)?  `ALUOP_OTHER :
53 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_SLT)?  `ALUOP_OTHER :
54 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_SLTU)? `ALUOP_OTHER :
55 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_XOR)?  `ALUOP_OTHER :
56 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_SRL)?  `ALUOP_OTHER :
57 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_OR) ?  `ALUOP_OTHER :
58 |                     ((opcode == `OPCODE_Arith_R || opcode == `OPCODE_Arith_I) && instr[14:12] == `F3_AND)?  `ALUOP_OTHER :
59 |                     
60 |                     (opcode == `OPCODE_Branch && instr[14:12] == `BR_BEQ) ? `ALUOP_SUB :
61 |                     (opcode == `OPCODE_Branch && instr[14:12] == `BR_BNE) ? `ALUOP_SUB :
62 |                     (opcode == `OPCODE_Branch && instr[14:12] == `BR_BLT) ? `ALUOP_SUB :
63 |                     (opcode == `OPCODE_Branch && instr[14:12] == `BR_BGE) ? `ALUOP_SUB :
64 |                     (opcode == `OPCODE_Branch && instr[14:12] == `BR_BLTU)? `ALUOP_SUB :     // TODO
65 |                     (opcode == `OPCODE_Branch && instr[14:12] == `BR_BGEU)? `ALUOP_SUB :     // TODO
66 |                     
67 |                     (opcode == `OPCODE_Load) ? `ALUOP_ADD :
68 |                     
69 |                     (opcode == `OPCODE_AUIPC) ? `ALUOP_ADD :
70 |                     `ALU_PASS;              // Default Value if opcode not defined
71 |         
72 |     assign Lui  =   (opcode == `OPCODE_LUI) ? 1'b1 : 1'b0;
73 |     
74 |     assign Auipc = (opcode == `OPCODE_AUIPC) ? 1'b1 : 1'b0;
75 |     
76 |     assign ECall =  (opcode == `OPCODE_SYSTEM && instr[14:12] == `SYS_EC_EB && instr[20] == 1'b0 && instr[31:20] != `MRET) ? 1'b1 : 1'b0;
77 |     
78 |     assign EBreak = (opcode == `OPCODE_SYSTEM && instr[14:12] == `SYS_EC_EB && instr[20] == 1'b1) ? 1'b1 : 1'b0;
79 |     
80 |     assign MRET =   (opcode == `OPCODE_SYSTEM && instr[14:12] == `PRIV && instr[31:20] == `MRET) ? 1'b1 : 1'b0;
81 |     
82 |     assign CSRWrite = (opcode == `OPCODE_SYSTEM && (instr[14:12] == `SYS_CSRRW ||  instr[14:12] == `SYS_CSRRS || instr[14:12] == `SYS_CSRRC || instr[14:12] == `SYS_CSRRWI ||  instr[14:12] == `SYS_CSRRSI || instr[14:12] == `SYS_CSRRCI)) ? 1'b1 : 1'b0;
83 |     
84 |     assign CSRSet = (opcode == `OPCODE_SYSTEM &&  instr[14:12] == `SYS_CSRRS) ? 1'b1 : 1'b0;
85 |     
86 |     assign CSRClear = (opcode == `OPCODE_SYSTEM &&  instr[14:12] == `SYS_CSRRC) ? 1'b1 : 1'b0;
87 |     
88 |     assign CSRI = (opcode == `OPCODE_SYSTEM && (instr[14:12] == `SYS_CSRRWI ||  instr[14:12] == `SYS_CSRRSI || instr[14:12] == `SYS_CSRRCI) ) ? 1'b1 : 1'b0;
89 | 
90 | endmodule
91 | 


--------------------------------------------------------------------------------
/RTL/CSRRegFile.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company: 
  4 | // Engineer: 
  5 | // 
  6 | // Create Date: 11/17/2018 05:27:41 PM
  7 | // Design Name: 
  8 | // Module Name: CSRRegFile
  9 | // Project Name: 
 10 | // Target Devices: 
 11 | // Tool Versions: 
 12 | // Description: 
 13 | // 
 14 | // Dependencies: 
 15 | // 
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | // 
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | module CSRRegFile(
 23 |     input    clk,
 24 |     input    clk_slow,
 25 |     input    rst,
 26 |     input [31:0] pc,
 27 |     input    nmi,
 28 |     input    ecall,
 29 |     input    ebreak,
 30 |     input    int,
 31 |     input    en_inter, 
 32 |     input    en_ecall, 
 33 |     input    en_int, 
 34 |     input    en_tmr,
 35 |     input [11:0] addr,
 36 |     input    CSR_Write,
 37 |     input [31:0] CSR_Write_Data,
 38 |     input    Set,
 39 |     input    Clear,
 40 |     input    JumpOrBranch,
 41 |     output reg [31:0] CSR_Read_Data,
 42 |     output   interF,
 43 |     output [31:0] interAddr
 44 | );
 45 | 
 46 | `define MEPC 3'b000
 47 | `define MCYCLE 3'b001
 48 | `define MTIME 3'b010
 49 | `define MINSTRET 3'b011
 50 | `define MTIMECMP 3'b100
 51 | `define MIE 3'b101
 52 | `define MIP 3'b110
 53 | 
 54 | /**
 55 |  CRS Registers
 56 |  0. 0x341 mepc 
 57 |  1. 0xB00 mcycle 
 58 |  2. 0xB01 mtime 
 59 |  3. 0xB02 minstret 
 60 |  4. 0xB03 mtimecmp 
 61 |  
 62 |  5. 0x304 mie [0] 0 => 1 To Enable TMR, [1] 0 => 1 To Enable  EX_INTERRUPT, [2] 0 => 1 TO Enable ECALL, [3] TO GLOBALLY DISABLE/ENABLE
 63 |  6. 0x344 mip 0 => 1 iff TMR IS HIGH, 0 => 1 iff NMI || EX_INTERRUPT IS HIGH, 0 => 1 iff EBREAK OR ECALL IS HIGH WITH EACH CLOCK CYCLE
 64 | */
 65 | 
 66 | /**
 67 |   CSR Registers Classifications
 68 |   
 69 |   Standard Read-Write
 70 |   MEPC //STORES ADDRESS OF PC AS IS WITHOUT INCREMENT
 71 |   MIE
 72 |   MIP
 73 |   Read-Write Shadows
 74 |   MCYCLE
 75 |   MTIME
 76 |   MINSTRET
 77 |   MTIMECMP
 78 | */
 79 | 
 80 | reg [31:0] CSR [6:0];
 81 | reg [2:0] Selected_Addr;
 82 | reg [31:0] count;
 83 | 
 84 | reg tmr;
 85 | wire [2:0] interSel, int_num;
 86 | wire load;
 87 | 
 88 | 
 89 | //Convert Incoming RISC V standard addr to selected address
 90 | always @(*) begin
 91 |     Selected_Addr = (addr == 12'h341) ? `MEPC :
 92 |                    (addr == 12'hb00) ? `MCYCLE :
 93 |                    (addr == 12'hb01) ? `MTIME :
 94 |                    (addr == 12'hb02) ? `MINSTRET :
 95 |                    (addr == 12'hb03) ? `MTIMECMP :
 96 |                    (addr == 12'h304) ? `MIE :
 97 |                    `MIP ;
 98 | end
 99 | 
100 | 
101 | //rst or write with posedge of clk
102 | always @(posedge clk) begin
103 |     if(rst) begin
104 |         CSR[`MTIME] = 32'd22000;
105 |         CSR[`MTIMECMP] = 32'd22010;
106 |         CSR[`MEPC] = 32'b0;
107 |         CSR[`MINSTRET] = 32'b0;
108 |         CSR[`MCYCLE] = 32'b0;
109 |         CSR[`MIP] = 32'b0;
110 |         CSR[`MIE] = 32'b01111;
111 |         count = 0;
112 |     end
113 | end
114 | 
115 | //Read with negedge of clk
116 | always @(negedge clk) begin
117 |     CSR_Read_Data = CSR[Selected_Addr] ;
118 | end
119 | 
120 | always @(posedge clk_slow) begin
121 |     // MCYCLES Reg Handling
122 |     CSR[`MCYCLE] = CSR[`MCYCLE] + 1;
123 |     
124 |     // MTIME && MTIMECMP Regs Handling
125 |     if(count == 10) begin
126 |         CSR[`MTIME] = CSR[`MTIME] + 1;
127 |         count = count + 1;
128 |     end
129 |     else if(count == 10 + 1) begin
130 |         count = 0;
131 |     end
132 |     else
133 |         count = count + 1;
134 |         
135 |     if(CSR[`MTIME] == CSR[`MTIMECMP]) begin
136 |         CSR[`MTIMECMP] = CSR[`MTIMECMP] + 10;
137 |         tmr = 1'b1;
138 |     end
139 |     else begin
140 |         CSR[`MTIMECMP] = CSR[`MTIMECMP];
141 |         tmr = 1'b0;
142 |     end
143 |     
144 |     // MinStret Reg Handling
145 |     if(!JumpOrBranch)
146 |         CSR[`MINSTRET] = CSR[`MINSTRET] + 1;
147 | end
148 | 
149 | assign load = clk ^ clk_slow;
150 | 
151 | always @(load) begin
152 | // Writing
153 |     if(CSR_Write) begin
154 |         if(Set) // CSRS
155 |             CSR[Selected_Addr] = CSR[Selected_Addr] | CSR_Write_Data;
156 |         else if(Clear)  // CSRC
157 |             CSR[Selected_Addr] = CSR[Selected_Addr] & ~CSR_Write_Data;
158 |         else    // CSRW
159 |             CSR[Selected_Addr] = CSR_Write_Data;
160 |     end
161 |     else
162 |         CSR[Selected_Addr] = CSR[Selected_Addr];
163 | end
164 | 
165 | always @ (posedge clk) begin
166 |     CSR[`MIE] = {28'b0, en_inter, en_ecall, en_int, en_tmr};
167 |     CSR[`MIP] = {29'b0, (ecall || ebreak), int, tmr};
168 |     
169 |     
170 |     if(interF && pc >= `CODE_SEGMENT)
171 |         CSR[`MEPC] = pc;
172 | end
173 | 
174 | 
175 | Interrupt_Detector interUnit (
176 |                 .nmi(nmi),
177 |                 .ecall(ecall),
178 |                 .ebreak(ebreak),
179 |                 .int(int),
180 |                 .tmr(tmr),
181 |                 
182 |                 .en_inter(en_inter),
183 |                 
184 |                 .en_ecall(en_ecall),
185 |                 .en_int(en_int),
186 |                 .en_tmr(en_tmr),
187 |                 
188 |                 .interFlag(interF),
189 |                 .interSel(interSel) 
190 | );
191 | 
192 | InterruptAddressGenerator intrAdrrGen(
193 |                 .interruptF(interF),
194 |                 .interSel(interSel),
195 |                 .intNum(int_num),
196 |                 .addr(interAddr)
197 | );
198 | 
199 | 
200 | endmodule


--------------------------------------------------------------------------------
/RTL/decompression.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns/1ps
  2 | //////////////////////////////////////////////////////////////////////////////////
  3 | // Company:
  4 | // Engineer:
  5 | //
  6 | // Create Date: 11/07/2018 05:58:14 PM
  7 | // Design Name:
  8 | // Module Name: DecompressionUnit
  9 | // Project Name:
 10 | // Target Devices:
 11 | // Tool Versions:
 12 | // Description:
 13 | //
 14 | // Dependencies:
 15 | //
 16 | // Revision:
 17 | // Revision 0.01 - File Created
 18 | // Additional Comments:
 19 | //
 20 | //////////////////////////////////////////////////////////////////////////////////
 21 | 
 22 | 
 23 | module Decompression(
 24 |     input [15:0]      IF_Instr_16,
 25 |     output reg [31:0] IF_Dec_32
 26 | );
 27 | 
 28 |     always @ (*) begin
 29 |       
 30 |         case ({IF_Instr_16[15:13], IF_Instr_16[1:0]})
 31 |             /* c.addi4spn ---------------------------------------------------------------------*/
 32 |             5'b00000: IF_Dec_32 = {2'b00, IF_Instr_16[10:7], IF_Instr_16[12:11], IF_Instr_16[5], IF_Instr_16[6], 2'b00, 5'd2, 3'b000, 2'b01, IF_Instr_16[4:2], 7'b0010011};
 33 |             /* c.lw ---------------------------------------------------------------------------*/
 34 |             5'b01000: IF_Dec_32 = {5'b00000, IF_Instr_16[5], IF_Instr_16[12:10], IF_Instr_16[6], 2'b00, 2'b01, IF_Instr_16[9:7], 3'b010, 2'b01, IF_Instr_16[4:2], 7'b0000011};
 35 |             /* c.sw ---------------------------------------------------------------------------*/
 36 |             5'b11000: IF_Dec_32 = {5'b00000, IF_Instr_16[5], IF_Instr_16[12], 2'b01, IF_Instr_16[4:2], 2'b01, IF_Instr_16[9:7], 3'b010, IF_Instr_16[11:10], IF_Instr_16[6], 2'b00, 7'b0100011};
 37 |             5'b00001: begin
 38 |                 /* c.nop ----------------------------------------------------------------------*/
 39 |                 if (IF_Instr_16[12:2] == 11'b0)
 40 |                     IF_Dec_32 = {25'b0, 7'b0010011};
 41 |                     /* c.addi --------------------------------------------------------------------*/
 42 |                 else IF_Dec_32 = {{7{IF_Instr_16[12]}}, IF_Instr_16[6:2], IF_Instr_16[11:7], 3'b000, IF_Instr_16[11:7], 7'b0010011};
 43 |             end
 44 |             /* c.jal --------------------------------------------------------------------------*/
 45 |             5'b00101: IF_Dec_32 = {IF_Instr_16[12], IF_Instr_16[8], IF_Instr_16[10:9], IF_Instr_16[6], IF_Instr_16[7], IF_Instr_16[2], IF_Instr_16[11], IF_Instr_16[5:3], IF_Instr_16[12], {8{IF_Instr_16[12]}}, 5'd1, 7'b1101111};
 46 |             /* c.li ---------------------------------------------------------------------------*/
 47 |             5'b01001: IF_Dec_32 = {{7{IF_Instr_16[12]}}, IF_Instr_16[6:2], 5'd0, 3'b000, IF_Instr_16[11:7], 7'b0010011};
 48 |             5'b01101: begin
 49 |                 /* c.addi16sp ------------------------------------------------------------------*/
 50 |                 if (IF_Instr_16[11:7] == 5'd2)
 51 |                     IF_Dec_32 = {{3{IF_Instr_16[12]}}, IF_Instr_16[4], IF_Instr_16[3], IF_Instr_16[5], IF_Instr_16[2], IF_Instr_16[6], 4'b0000, 5'd2, 3'b000, 5'd2, 7'b0010011};
 52 |                     /* c.lui -----------------------------------------------------------------------*/
 53 |                 else IF_Dec_32 = {{15{IF_Instr_16[12]}}, IF_Instr_16[6:2], IF_Instr_16[11:7], 7'b0110111};
 54 |             end
 55 |             5'b10001: begin
 56 |                 /* c.sub --------------------------------------------------------------------*/
 57 |                 if (IF_Instr_16[12:10] == 3'b011 && IF_Instr_16[6:5] == 2'b00)
 58 |                     IF_Dec_32 = {7'b0100000, 2'b01, IF_Instr_16[4:2], 2'b01, IF_Instr_16[9:7], 3'b000, 2'b01, IF_Instr_16[9:7], 7'b0110011};
 59 |                     /* c.xor --------------------------------------------------------------------*/
 60 |                 else if (IF_Instr_16[12:10] == 3'b011 && IF_Instr_16[6:5] == 2'b01)
 61 |                     IF_Dec_32 = {7'b0000000, 2'b01, IF_Instr_16[4:2], 2'b01, IF_Instr_16[9:7], 3'b100, 2'b01, IF_Instr_16[9:7], 7'b0110011};
 62 |                     /* c.or --------------------------------------------------------------------*/
 63 |                 else if (IF_Instr_16[12:10] == 3'b011 && IF_Instr_16[6:5] == 2'b10)
 64 |                     IF_Dec_32 = {7'b0000000, 2'b01, IF_Instr_16[4:2], 2'b01, IF_Instr_16[9:7], 3'b110, 2'b01, IF_Instr_16[9:7], 7'b0110011};
 65 |                     /* c.and --------------------------------------------------------------------*/
 66 |                 else if (IF_Instr_16[12:10] == 3'b011 && IF_Instr_16[6:5] == 2'b11)
 67 |                     IF_Dec_32 = {7'b0000000, 2'b01, IF_Instr_16[4:2], 2'b01, IF_Instr_16[9:7], 3'b111, 2'b01, IF_Instr_16[9:7], 7'b0110011};
 68 |                     /* c.andi --------------------------------------------------------------------*/
 69 |                 else if (IF_Instr_16[11:10] == 2'b10)
 70 |                     IF_Dec_32 = {{7{IF_Instr_16[12]}}, IF_Instr_16[6:2], 2'b01, IF_Instr_16[9:7], 3'b111, 2'b01, IF_Instr_16[9:7], 7'b0010011};
 71 |                     /* Skip instruction ---------------------------------------------------------*/
 72 |                 else if (IF_Instr_16[12] == 1'b0 && IF_Instr_16[6:2] == 5'b0)
 73 |                     IF_Dec_32 = 32'b0;
 74 |                     /* c.srli --------------------------------------------------------------------*/
 75 |                 else if (IF_Instr_16[11:10] == 2'b00)
 76 |                     IF_Dec_32 = {7'b0000000, IF_Instr_16[6:2], 2'b01, IF_Instr_16[9:7], 3'b101, 2'b01, IF_Instr_16[9:7], 7'b0010011};
 77 |                     /* c.srai --------------------------------------------------------------------*/
 78 |                 else
 79 |                     IF_Dec_32 = {7'b0100000, IF_Instr_16[6:2], 2'b01, IF_Instr_16[9:7], 3'b101, 2'b01, IF_Instr_16[9:7], 7'b0010011};
 80 |             end
 81 |             /* c.j -----------------------------------------------------------------------*/
 82 |             5'b10101: IF_Dec_32 = {IF_Instr_16[12], IF_Instr_16[8], IF_Instr_16[10:9], IF_Instr_16[6], IF_Instr_16[7], IF_Instr_16[2], IF_Instr_16[11], IF_Instr_16[5:3], IF_Instr_16[12], {8{IF_Instr_16[12]}}, 5'd0, 7'b1101111};
 83 |             /* c.beqz --------------------------------------------------------------------*/
 84 |             5'b11001: IF_Dec_32 = {{4{IF_Instr_16[12]}}, IF_Instr_16[6], IF_Instr_16[5], IF_Instr_16[2], 5'd0, 2'b01, IF_Instr_16[9:7], 3'b000, IF_Instr_16[11], IF_Instr_16[10], IF_Instr_16[4], IF_Instr_16[3], IF_Instr_16[12], 7'b1100011};
 85 |             /* c.bnez --------------------------------------------------------------------*/
 86 |             5'b11101: IF_Dec_32 = {{4{IF_Instr_16[12]}}, IF_Instr_16[6], IF_Instr_16[5], IF_Instr_16[2], 5'd0, 2'b01, IF_Instr_16[9:7], 3'b001, IF_Instr_16[11], IF_Instr_16[10], IF_Instr_16[4], IF_Instr_16[3], IF_Instr_16[12], 7'b1100011};
 87 |             /* c.slli --------------------------------------------------------------------*/
 88 |             5'b00010: IF_Dec_32 = {7'b0000000, IF_Instr_16[6:2], IF_Instr_16[11:7], 3'b001, IF_Instr_16[11:7], 7'b0010011};
 89 |             /* c.lwsp --------------------------------------------------------------------*/
 90 |             5'b01010: IF_Dec_32 = {4'b0000, IF_Instr_16[3:2], IF_Instr_16[12], IF_Instr_16[6:4], 2'b0, 5'd2, 3'b010, IF_Instr_16[11:7], 7'b0000011};
 91 |             /* c.swsp --------------------------------------------------------------------*/
 92 |             5'b11010: IF_Dec_32 = {4'b0000, IF_Instr_16[8:7], IF_Instr_16[12], IF_Instr_16[6:2], 5'd2, 3'b010, IF_Instr_16[11:9], 2'b00, 7'b0100011};
 93 |             5'b10010: begin
 94 |                 if (IF_Instr_16[6:2] == 5'd0) begin
 95 |                     /* c.jalr --------------------------------------------------------------------*/
 96 |                     if (IF_Instr_16[12] && IF_Instr_16[11:7] != 5'b0)
 97 |                         IF_Dec_32 = {12'b0, IF_Instr_16[11:7], 3'b000, 5'd1, 7'b1100111};
 98 |                         /* c.jr --------------------------------------------------------------------*/
 99 |                     else IF_Dec_32 = {12'b0, IF_Instr_16[11:7], 3'b000, 5'd0, 7'b1100111};
100 |                 end 
101 |                 else if (IF_Instr_16[11:7] != 5'b0) begin
102 |                     /* c.mv --------------------------------------------------------------------*/
103 |                     if (IF_Instr_16[12] == 1'b0)
104 |                         IF_Dec_32 = {7'b0000000, IF_Instr_16[6:2], 5'd0, 3'b000, IF_Instr_16[11:7], 7'b0110011};
105 |                         /* c.add --------------------------------------------------------------------*/
106 |                     else IF_Dec_32 = {7'b0000000, IF_Instr_16[6:2], IF_Instr_16[11:7], 3'b000, IF_Instr_16[11:7], 7'b0110011};
107 |                 end
108 |             end
109 |             default : IF_Dec_32 = 32'b0;
110 |         endcase
111 |     end
112 | 
113 | endmodule
114 | 


--------------------------------------------------------------------------------
/RTL/RISCV.v:
--------------------------------------------------------------------------------
  1 | // file: RISCV.v
  2 | // author: @mazenAmr
  3 | 
  4 | `timescale 1ns/1ns
  5 | 
  6 | 
  7 | 
  8 | module RISCV(
  9 |     input             clk_i,
 10 |     input             rst,
 11 |     input             en_inter,
 12 |     input             int,
 13 |     input             int_num,
 14 |     input             nmi,
 15 |     input             en_nmi,
 16 |     input             en_ecall,
 17 |     input             en_ebreak,
 18 |     input             en_int,
 19 |     input             en_tmr,
 20 |     input   [31:0]    limit,
 21 |     output  [31:0]    out
 22 | );
 23 |     /*
 24 |     *   Variables Declaration
 25 |     */
 26 |     wire [31:0] PC_out, PCAdder_out, BranchAdder_out, PC_Or_Branch,
 27 |                 RegR1, RegR2, RegW, ImmGen_out, ALUSrcMux_out,
 28 |                 ALU_out, Mem_out, Inst, PC_Or_Jal, decompressedInstr;
 29 |     wire        Branch, MemRead, MemToReg, MemWrite, ALUSrc, RegWrite, Zero;
 30 |     wire [1:0]  ALUOp, Jump;
 31 |     wire [3:0]  ALUSel;
 32 |     wire        branchTaken, clk_RF, clk_inv, clk, memSelect;
 33 |     reg [31:0]  PC_in;
 34 |  
 35 |     
 36 |     // IF_ID pipeline reg wires
 37 |     wire [31:0] IF_ID_PC, IF_ID_Inst, jump_address, jal_branch_address, jalR_address, PC4_Or_Branch, IF_ID_InstOut, PC_PLUS_FOUR, PC_PLUS_TWO;
 38 |     wire [2:0]  IF_ID_Mode;
 39 |     wire [4:0]  rs2;
 40 |     wire [1:0]  fwdA, fwdB;
 41 |     wire        IF_ID_luiControl, CompressedFlag, ECall, EBreak, MRET, CSRWrite, CSRSet, CSRClear, CSRI, Auipc;
 42 |     
 43 |     wire [12:0] ctrls_part1;
 44 |     wire [3:0] ctrls_part2;
 45 |     wire [4:0] ctrls_part3;
 46 |     
 47 | 
 48 |     // ID_EX pipeline reg wires
 49 |     reg  [31:0] ALU_OprandA, ALU_OprandB, ALU_OprandA_fwdRes;
 50 |     wire [31:0] ID_EX_PC, ID_EX_RegR1, ID_EX_RegR2, ID_EX_Imm, ID_EX_interAddr, PC_in_wo_inter, ID_EX_Inst, csr_read;
 51 |     wire [12:0] ID_EX_Ctrl;
 52 |     wire [9:0]  ID_EX_Func;
 53 |     wire [4:0]  ID_EX_Rs1, ID_EX_Rs2, ID_EX_Rd, regsrc;
 54 |     wire [2:0]  ID_EX_Mode;
 55 |     wire [31:0] memMuxOut;
 56 |     wire [2:0]  interSel;
 57 |     wire        ID_EX_luiControl, interF, tmr, ID_EX_ECall, ID_EX_EBreak, ID_EX_MRET, ID_EX_CSRWrite, ID_EX_CSRSet, ID_EX_CSRClear, ID_EX_CSRI, ID_EX_Auipc;
 58 |     wire [11:0] csrAddr, csrAddrR;
 59 |    
 60 |     // EX_MEM pipeline reg wires
 61 |     wire [31:0] EX_MEM_BranchAddOut, EX_MEM_ALU_out, EX_MEM_RegR2, EX_MEM_PC, EX_MEM_Imm, EX_MEM_csr_read, EX_MEM_RegR1, EX_MEM_Inst;
 62 |     wire [9:0]  EX_MEM_Ctrl;
 63 |     wire [4:0]  EX_MEM_Rd, EX_MEM_Rs1;
 64 |     wire        EX_MEM_Zero, sFlag, vFlag, cFlag, EX_MEM_luiControl, EX_MEM_CSRWrite, EX_MEM_CSRSet, EX_MEM_CSRClear, EX_MEM_CSRI, EX_MEM_branchTaken;
 65 |     
 66 |     // MEM_WB pipeline reg wires
 67 |     wire [31:0] MEM_WB_Mem_out, MEM_WB_ALU_out, MEM_WB_PC, RegData, MEM_WB_Imm, MEM_WB_csr_read, RegW_No_Inter, MEM_WB_RegR1, MEM_WB_Inst, MEM_WB_CSRData;
 68 |     wire [3:0]  MEM_WB_Ctrl;
 69 |     wire [4:0]  MEM_WB_Rd, MEM_WB_Rs1;
 70 |     wire        regMuxSelection, jalSel, MEM_WB_luiControl, MEM_WB_CSRWrite, MEM_WB_CSRSet, MEM_WB_CSRClear, MEM_WB_CSRI, MEM_WB_branchTaken, JumpOrBranch;
 71 | 
 72 | 
 73 |     ClkDiv clkDiv (.clk(clk_i), .rst(rst), .clk_o(clk));
 74 |         //ClkDivRF clkDivRF (.clk(clk_i), .rst(rst), .clk_o(clk_RF));
 75 |         
 76 |     ClkInverter clkInv (
 77 |                         .clk_i(clk),
 78 |                         .clk_o(clk_inv)
 79 |     );
 80 |     
 81 |     /*
 82 |     *   Pipeline Registers  
 83 |     */
 84 | 
 85 |     RegWLoad#(64) IF_ID (.clk      (clk_inv),
 86 |                          .rst      (rst),
 87 |                          .load     (1'b1),
 88 |                          .data_in  ({PC_out, Mem_out}),
 89 |                          .data_out ({IF_ID_PC, IF_ID_InstOut})
 90 |     );
 91 |     
 92 |     
 93 |         
 94 |     RegWLoad#(207) ID_EX (.clk (clk),
 95 |                           .rst (rst),
 96 |                           .load (1'b1),
 97 |                           .data_in ({ ctrls_part1,// all the control signals
 98 |                                    IF_ID_PC, RegR1, RegR2, ImmGen_out,
 99 |                                    IF_ID_Inst[31:25], IF_ID_Inst[14:12],
100 |                                    IF_ID_Inst[19:15], IF_ID_Inst[24:20], IF_ID_Inst[11:7], ctrls_part2, IF_ID_InstOut, ctrls_part3}), // the 3 regs
101 |                           .data_out ({ID_EX_Ctrl, ID_EX_PC, ID_EX_RegR1, ID_EX_RegR2, ID_EX_Imm, // ID_EX_Ctrl has all the 11 bits (7) controls
102 |                                    ID_EX_Func, ID_EX_Rs1, ID_EX_Rs2, ID_EX_Rd, ID_EX_luiControl, ID_EX_ECall, ID_EX_EBreak, ID_EX_MRET, ID_EX_Inst, ID_EX_CSRWrite, ID_EX_CSRSet, ID_EX_CSRClear, ID_EX_CSRI, ID_EX_Auipc}) 
103 |     );
104 | 
105 |     RegWLoad#(283) EX_MEM (.clk (clk_inv),
106 |                            .rst (rst),
107 |                            .load (1'b1),
108 |                            .data_in ({ID_EX_Ctrl[12:3], // Jump, IF_ID_Mode, RegWrite,MemToReg, and Branch,MemRead,MemWrite
109 |                                     BranchAdder_out, Zero, ALU_out,
110 |                                     ID_EX_RegR2, ID_EX_Rd, ID_EX_PC, ID_EX_Imm, ID_EX_luiControl, csr_read, ID_EX_CSRWrite, ID_EX_RegR1, ID_EX_Inst, ID_EX_CSRSet, ID_EX_CSRClear, ID_EX_Rs1, ID_EX_CSRI, branchTaken}),
111 |                            .data_out ({EX_MEM_Ctrl, // EX_MEM_Ctrl = Jump, IF_ID_Mode, RegWrite,MemToReg, and Branch,MemRead,MemWrite
112 |                                     EX_MEM_BranchAddOut, EX_MEM_Zero,
113 |                                     EX_MEM_ALU_out,
114 |                                     EX_MEM_RegR2, EX_MEM_Rd, EX_MEM_PC, EX_MEM_Imm, EX_MEM_luiControl, EX_MEM_csr_read, EX_MEM_CSRWrite, EX_MEM_RegR1, EX_MEM_Inst, EX_MEM_CSRSet, EX_MEM_CSRClear, EX_MEM_Rs1, EX_MEM_CSRI, EX_MEM_branchTaken})
115 |     );
116 | 
117 | 
118 |     RegWLoad#(244) MEM_WB (.clk (clk),
119 |                           .rst (rst),
120 |                           .load (1'b1),
121 |                           .data_in ({ {EX_MEM_Ctrl[9:8], EX_MEM_Ctrl[4:3]}, // RegWrite,MemToReg
122 |                                    Mem_out, EX_MEM_ALU_out, EX_MEM_Rd, EX_MEM_PC, EX_MEM_Imm, EX_MEM_luiControl, EX_MEM_csr_read, EX_MEM_CSRWrite, EX_MEM_RegR1, EX_MEM_Inst, EX_MEM_CSRSet, EX_MEM_CSRClear, EX_MEM_Rs1, EX_MEM_CSRI, EX_MEM_branchTaken}),
123 |                           .data_out ({MEM_WB_Ctrl, MEM_WB_Mem_out, MEM_WB_ALU_out, MEM_WB_Rd, MEM_WB_PC, MEM_WB_Imm, MEM_WB_luiControl, MEM_WB_csr_read, MEM_WB_CSRWrite, MEM_WB_RegR1, MEM_WB_Inst, MEM_WB_CSRSet, MEM_WB_CSRClear, MEM_WB_Rs1, MEM_WB_CSRI, MEM_WB_branchTaken})
124 |     );
125 | 
126 |     /*
127 |     *   Fetch
128 |     */
129 | 
130 |     RegWLoad PC (.clk      (clk),
131 |                  .rst      (rst),
132 |                  .load     (1'b1),
133 |                  .data_in  (PC_in),
134 |                  .data_out (PC_out)
135 |     );
136 | 
137 | 
138 |     /*
139 |     *   Decode
140 |     */
141 |  
142 |     Decompression decUnit (
143 |         .IF_Instr_16(IF_ID_InstOut[15:0]),
144 |         .IF_Dec_32(decompressedInstr)
145 |     );
146 |     assign CompressedFlag = (IF_ID_InstOut[1:0] != 2'b11) ? 1 : 0;
147 |     assign IF_ID_Inst = (CompressedFlag == 1'b1) ? decompressedInstr : IF_ID_InstOut;
148 |     
149 |     assign rs2 = IF_ID_Inst[24:20];
150 |     
151 |     
152 |    
153 |     RegFile rf (.clk    (clk_i),
154 |             .clk_slow   (clk),
155 |             .rst        (rst),
156 |             .WriteEn    (MEM_WB_Ctrl[1]), // RegWrite
157 |             .rs1_rd     (regsrc),
158 |             .rs2        (rs2),
159 |             .write_data (RegW),
160 |             .read_data1 (RegR1),
161 |             .read_data2 (RegR2)
162 |     );
163 |     
164 |     RegSrcUnit regSrcUnit (
165 |             .clk(clk),
166 |             .regWrite(MEM_WB_Ctrl[1]), // RegWrite
167 |             .regMuxSelect(regMuxSelection)
168 |     );
169 | 
170 |     Mux2_1#(5) MuxregFile (.sel (clk), // RegWrite
171 |                              .in1 (IF_ID_Inst[19:15]),  // rs1
172 |                              .in2 (MEM_WB_Rd),
173 |                              .out (regsrc)
174 |     );
175 |                              
176 |     ImmGen ig (.IR  (IF_ID_Inst),
177 |                .Imm (ImmGen_out)
178 |     );
179 |     
180 |     
181 | 
182 |     ControlUnit cu (.instr    (IF_ID_Inst),
183 |                     .opcode   (IF_ID_Inst[6:2]), 
184 |                     .Branch   (Branch),
185 |                     .Jump     (Jump),
186 |                     .MemRead  (MemRead),
187 |                     .MemToReg (MemToReg),
188 |                     .ALUOp    (ALUOp),
189 |                     .MemWrite (MemWrite),
190 |                     .ALUSrc   (ALUSrc),
191 |                     .RegWrite (RegWrite),
192 |                     .Mode     (IF_ID_Mode),
193 |                     .Lui      (IF_ID_luiControl),
194 |                     .Auipc    (Auipc),
195 |                     .ECall    (ECall),
196 |                     .EBreak   (EBreak),
197 |                     .MRET     (MRET),
198 |                     .CSRWrite (CSRWrite),
199 |                     .CSRSet   (CSRSet),
200 |                     .CSRClear (CSRClear),
201 |                     .CSRI     (CSRI)
202 |     );
203 |     
204 |     // if branch taken, or jump, or MRET => flush
205 |     
206 |     assign ctrls_part1 = (ID_EX_Ctrl[12:11] || branchTaken || ID_EX_MRET) ? {13'b0} : {Jump, IF_ID_Mode, RegWrite, MemToReg, Branch, MemRead, MemWrite, ALUOp, ALUSrc};
207 |     assign ctrls_part2 = (ID_EX_Ctrl[12:11] || branchTaken || ID_EX_MRET) ? {4'b0} : {IF_ID_luiControl, ECall, EBreak, MRET};
208 |     assign ctrls_part3 = (ID_EX_Ctrl[12:11] || branchTaken || ID_EX_MRET) ? {5'b0} : {CSRWrite, CSRSet, CSRClear, CSRI, Auipc};
209 | 
210 |     /*
211 |     *   Execute  
212 |     */
213 | 
214 |     
215 |     ForwardUnit FwdUnit (
216 |         .ID_EX_Rs1(ID_EX_Rs1),
217 |         .ID_EX_Rs2(ID_EX_Rs2),
218 |         .EX_MEM_RegWrite(EX_MEM_Ctrl[4]),
219 |         .EX_MEM_Rd(EX_MEM_Rd),
220 |         .MEM_WB_RegWrite(MEM_WB_Ctrl[1]),
221 |         .MEM_WB_Rd(MEM_WB_Rd),
222 |         .ForwardA(fwdA),
223 |         .ForwardB(fwdB)
224 |     );
225 | 
226 |     // Forwarding MUX A & MUX B
227 |     always @ (*) begin
228 |         if(ID_EX_Auipc)
229 |             ALU_OprandA = ID_EX_PC;
230 |         else begin
231 |             case(fwdA)
232 |                 2'b00:
233 |                     ALU_OprandA = ID_EX_RegR1;
234 |                 2'b10:
235 |                     ALU_OprandA = EX_MEM_ALU_out;
236 |                 2'b01:
237 |                     ALU_OprandA = RegW;
238 |                 default:
239 |                     ALU_OprandA = ID_EX_RegR1;
240 |             endcase
241 |         end
242 |         
243 |         case(fwdB)
244 |             2'b00:
245 |                 ALU_OprandB = ALUSrcMux_out;
246 |             2'b10:
247 |                 ALU_OprandB = EX_MEM_ALU_out;
248 |             2'b01:
249 |                 ALU_OprandB = RegW;
250 |             default:
251 |                 ALU_OprandB = ALUSrcMux_out;
252 |         endcase
253 |     
254 |     end
255 |      
256 |     Mux2_1#(32) aluSrcBMux (.sel (ID_EX_Ctrl[0]),   // ALUSrc
257 |                             .in1 (ID_EX_RegR2),
258 |                             .in2 (ID_EX_Imm),
259 |                             .out (ALUSrcMux_out)
260 |     );
261 |     
262 | 
263 |     ALU a1 (
264 |             .sel (ALUSel),
265 |             .a   (ALU_OprandA),
266 |             .b   (ALU_OprandB),
267 |             .result   (ALU_out),
268 |             .z   (Zero),
269 |             .s   (sFlag),
270 |             .c   (cFlag),
271 |             .v   (vFlag)
272 |     );
273 |     
274 |     
275 |     BranchUnit branchUnit ( 
276 |                 .branch(ID_EX_Ctrl[5]),     // BRANCH
277 |                 .s(sFlag),
278 |                 .z(Zero),
279 |                 .c(cFlag),
280 |                 .v(vFlag),
281 |                 .func3(ID_EX_Func[2:0]),
282 |                 .branchTaken (branchTaken)
283 |     );
284 | 
285 |     
286 |     Adder OffsetPC ( 
287 |                     .a(ID_EX_PC),
288 |                     .b(ID_EX_Imm),
289 |                     .res(BranchAdder_out)
290 |     );
291 | 
292 |     Adder PC_plus_four ( 
293 |                 .a(IF_ID_PC),
294 |                 .b(4),
295 |                 .res(PC_PLUS_FOUR)
296 |     );
297 |     
298 |     Adder PC_plus_two ( 
299 |                     .a(IF_ID_PC),
300 |                     .b(2),
301 |                     .res(PC_PLUS_TWO)
302 |     );
303 |         
304 |     // beq: PC + imm
305 |     Mux2_1#(32) BranchOrPCMux (.sel (branchTaken),
306 |                                   .in1 (PC_PLUS_FOUR),  
307 |                                   .in2 (BranchAdder_out),
308 |                                   .out (PC4_Or_Branch)
309 |     );
310 |     
311 |     Mux2_1#(32) BranchOrPCPlus4OrPcPlus2Mux (   .sel (CompressedFlag),
312 |                                   .in1 (PC4_Or_Branch),      
313 |                                   .in2 (PC_PLUS_TWO),      
314 |                                   .out (PC_Or_Branch)
315 |     );
316 |     
317 |     Mux4_1 #(32) srcOfPC(
318 |          .sel(ID_EX_Ctrl[12:11]),   // Jump
319 |          .in1(PC_Or_Branch),
320 |          .in2(jal_branch_address),
321 |          .in3(jalR_address),
322 |          .in4(),
323 |          .out(PC_in_wo_inter)
324 |      );
325 |      
326 |       
327 |     // jalr: reg + imm
328 |      Adder jalRAdder ( 
329 |                           .a(ID_EX_RegR1),
330 |                           .b(ID_EX_Imm),
331 |                           .res(jalR_address)
332 |       );
333 | 
334 |     ALUControl acu (
335 |                     .ALUOp (ID_EX_Ctrl[2:1]),     //  ALUOp
336 |                     .func3 (ID_EX_Func[2:0]),
337 |                     .func7 (ID_EX_Func[9:3]),
338 |                     .sel   (ALUSel)
339 |     );
340 | 
341 |  // jal: address + PC
342 |     
343 |     Adder JalAddressAdder ( 
344 |                       .a(ID_EX_Imm),
345 |                       .b(ID_EX_PC),
346 |                       .res(jal_branch_address)
347 |     );
348 |         
349 |     
350 |     /*********************************************************************/
351 |     
352 |     assign csrAddrR = (ID_EX_MRET) ? `MEPC_ADDR : ID_EX_Inst[31:20];
353 |     assign csrAddr = (clk) ? MEM_WB_Inst[31:20]: csrAddrR;
354 |     
355 |     assign MEM_WB_CSRData = (MEM_WB_CSRI)? {27'b0, MEM_WB_Rs1} : MEM_WB_RegR1;
356 |     
357 |     assign JumpOrBranch = (jalSel || MEM_WB_branchTaken)? 1'b1 : 1'b0 ;
358 |     
359 |    CSRRegFile csrFile(
360 |         .clk(clk_i),
361 |         .clk_slow(clk),
362 |         .rst(rst),
363 |         .pc(ID_EX_PC),
364 |         .nmi(nmi),
365 |         .ecall(ID_EX_ECall),
366 |         .ebreak(ID_EX_EBreak),
367 |         .int(int),
368 |         .en_inter(en_inter), 
369 |         .en_ecall(en_ecall), 
370 |         .en_int(en_int), 
371 |         .en_tmr(en_tmr),
372 |         .addr(csrAddr),
373 |         .CSR_Write(MEM_WB_CSRWrite),
374 |         .CSR_Write_Data(MEM_WB_CSRData),
375 |         .Set(MEM_WB_CSRSet),
376 |         .Clear(MEM_WB_CSRClear),
377 |         .JumpOrBranch(JumpOrBranch),
378 |         .CSR_Read_Data(csr_read),
379 |         .interF(interF),
380 |         .interAddr(ID_EX_interAddr)
381 |     );
382 | 
383 |     /**********************************************************************/
384 |     always @(*) begin
385 |         if(ID_EX_MRET)
386 |             PC_in = csr_read + 4 ;
387 |         else if(interF)
388 |             PC_in = ID_EX_interAddr;
389 |         else
390 |             PC_in = PC_in_wo_inter;
391 |     end
392 |     
393 |     /*
394 |     *   Mem  
395 |     */
396 |    
397 |     Memory Mem (
398 |         .clk(clk),
399 |         .clk_i(clk_i),
400 |         .rst(rst),
401 |         .MemRead(EX_MEM_Ctrl[1]),
402 |         .MemWrite(EX_MEM_Ctrl[0]),
403 |         .mode(EX_MEM_Ctrl[7:5]),
404 |         .addr(memMuxOut),
405 |         .data_in(EX_MEM_RegR2),
406 |         .data_out(Mem_out)
407 |     );
408 |     
409 |     memAddressSelectUnit MemSrcAddress (
410 |         .clk_fast(clk_i),
411 |         .clk_slow(clk),
412 |         .select(memSelect)
413 |     );
414 |         
415 |     Mux2_1 #(32) MemMux (.sel (memSelect),      // ~clk_i
416 |                         .in1 (PC_out),
417 |                         .in2 (EX_MEM_ALU_out),
418 |                         .out (memMuxOut)
419 |     );
420 |     
421 | 
422 |     /*
423 |     *   Write Back  
424 |     */
425 |     Mux2_1#(32) regWSrcMux1 (.sel (MEM_WB_Ctrl[0]),  // MemToReg
426 |                             .in1 (MEM_WB_ALU_out),
427 |                             .in2 (MEM_WB_Mem_out),
428 |                             .out (RegData)
429 |     );
430 |     
431 |     assign jalSel = (MEM_WB_Ctrl[2] || MEM_WB_Ctrl[3]);
432 |     Mux2_1#(32) regWSrcMux2 (    .sel (jalSel),  // Jump
433 |                                 .in1 (RegData),
434 |                                 .in2 (MEM_WB_PC + 4),
435 |                                 .out (PC_Or_Jal)
436 |     );
437 | 
438 |     Mux2_1#(32) regWSrcMux3 (    .sel (MEM_WB_luiControl), 
439 |                                     .in1 (PC_Or_Jal),
440 |                                     .in2 (MEM_WB_Imm),
441 |                                     .out (RegW_No_Inter)
442 |     );
443 |     assign RegW = (MEM_WB_CSRWrite) ? MEM_WB_csr_read : RegW_No_Inter;
444 |     
445 |     // only to see delay
446 |     assign out = RegW;
447 | 
448 | endmodule
449 | 
450 | 


--------------------------------------------------------------------------------
/Test/cpu_tb_sim.wcfg:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8"?>
  2 | <wave_config>
  3 |    <wave_state>
  4 |    </wave_state>
  5 |    <db_ref_list>
  6 |       <db_ref path="cpu_tb_behav.wdb" id="1">
  7 |          <top_modules>
  8 |             <top_module name="cpu_tb" />
  9 |             <top_module name="glbl" />
 10 |          </top_modules>
 11 |       </db_ref>
 12 |    </db_ref_list>
 13 |    <zoom_setting>
 14 |       <ZoomStartTime time="0fs"></ZoomStartTime>
 15 |       <ZoomEndTime time="317649631fs"></ZoomEndTime>
 16 |       <Cursor1Time time="150000000fs"></Cursor1Time>
 17 |    </zoom_setting>
 18 |    <column_width_setting>
 19 |       <NameColumnWidth column_width="175"></NameColumnWidth>
 20 |       <ValueColumnWidth column_width="136"></ValueColumnWidth>
 21 |    </column_width_setting>
 22 |    <WVObjectSize size="93" />
 23 |    <wvobject fp_name="/cpu_tb/clk" type="logic">
 24 |       <obj_property name="DisplayName">label</obj_property>
 25 |       <obj_property name="ElementShortName">clk</obj_property>
 26 |       <obj_property name="ObjectShortName">clk</obj_property>
 27 |       <obj_property name="label">clk_fast</obj_property>
 28 |    </wvobject>
 29 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/clk" type="logic">
 30 |       <obj_property name="ElementShortName">clk</obj_property>
 31 |       <obj_property name="ObjectShortName">clk</obj_property>
 32 |    </wvobject>
 33 |    <wvobject fp_name="/cpu_tb/rst" type="logic">
 34 |       <obj_property name="ElementShortName">rst</obj_property>
 35 |       <obj_property name="ObjectShortName">rst</obj_property>
 36 |    </wvobject>
 37 |    <wvobject type="divider" fp_name="divider172">
 38 |       <obj_property name="label">PC</obj_property>
 39 |       <obj_property name="DisplayName">label</obj_property>
 40 |       <obj_property name="BkColor">#FFFFFF</obj_property>
 41 |    </wvobject>
 42 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/PC_in" type="array">
 43 |       <obj_property name="ElementShortName">PC_in[31:0]</obj_property>
 44 |       <obj_property name="ObjectShortName">PC_in[31:0]</obj_property>
 45 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
 46 |    </wvobject>
 47 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/PC_out" type="array">
 48 |       <obj_property name="ElementShortName">PC_out[31:0]</obj_property>
 49 |       <obj_property name="ObjectShortName">PC_out[31:0]</obj_property>
 50 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
 51 |    </wvobject>
 52 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/IF_ID_PC" type="array">
 53 |       <obj_property name="ElementShortName">IF_ID_PC[31:0]</obj_property>
 54 |       <obj_property name="ObjectShortName">IF_ID_PC[31:0]</obj_property>
 55 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
 56 |    </wvobject>
 57 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_PC" type="array">
 58 |       <obj_property name="ElementShortName">ID_EX_PC[31:0]</obj_property>
 59 |       <obj_property name="ObjectShortName">ID_EX_PC[31:0]</obj_property>
 60 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
 61 |    </wvobject>
 62 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/EX_MEM_PC" type="array">
 63 |       <obj_property name="ElementShortName">EX_MEM_PC[31:0]</obj_property>
 64 |       <obj_property name="ObjectShortName">EX_MEM_PC[31:0]</obj_property>
 65 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
 66 |    </wvobject>
 67 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_PC" type="array">
 68 |       <obj_property name="ElementShortName">MEM_WB_PC[31:0]</obj_property>
 69 |       <obj_property name="ObjectShortName">MEM_WB_PC[31:0]</obj_property>
 70 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
 71 |    </wvobject>
 72 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ctrls_part1" type="array">
 73 |       <obj_property name="ElementShortName">ctrls_part1[12:0]</obj_property>
 74 |       <obj_property name="ObjectShortName">ctrls_part1[12:0]</obj_property>
 75 |    </wvobject>
 76 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ctrls_part2" type="array">
 77 |       <obj_property name="ElementShortName">ctrls_part2[3:0]</obj_property>
 78 |       <obj_property name="ObjectShortName">ctrls_part2[3:0]</obj_property>
 79 |    </wvobject>
 80 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ctrls_part3" type="array">
 81 |       <obj_property name="ElementShortName">ctrls_part3[4:0]</obj_property>
 82 |       <obj_property name="ObjectShortName">ctrls_part3[4:0]</obj_property>
 83 |       <obj_property name="isExpanded"></obj_property>
 84 |    </wvobject>
 85 |    <wvobject type="divider" fp_name="divider51">
 86 |       <obj_property name="label">CSR</obj_property>
 87 |       <obj_property name="DisplayName">label</obj_property>
 88 |       <obj_property name="BkColor">#E0FFFF</obj_property>
 89 |    </wvobject>
 90 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/csrFile/interUnit/ecall" type="logic">
 91 |       <obj_property name="ElementShortName">ecall</obj_property>
 92 |       <obj_property name="ObjectShortName">ecall</obj_property>
 93 |    </wvobject>
 94 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/csrFile/interUnit/ebreak" type="logic">
 95 |       <obj_property name="ElementShortName">ebreak</obj_property>
 96 |       <obj_property name="ObjectShortName">ebreak</obj_property>
 97 |    </wvobject>
 98 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/csrFile/interUnit/interFlag" type="logic">
 99 |       <obj_property name="ElementShortName">interFlag</obj_property>
100 |       <obj_property name="ObjectShortName">interFlag</obj_property>
101 |    </wvobject>
102 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/interF" type="logic">
103 |       <obj_property name="ElementShortName">interF</obj_property>
104 |       <obj_property name="ObjectShortName">interF</obj_property>
105 |    </wvobject>
106 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_EBreak" type="logic">
107 |       <obj_property name="ElementShortName">ID_EX_EBreak</obj_property>
108 |       <obj_property name="ObjectShortName">ID_EX_EBreak</obj_property>
109 |    </wvobject>
110 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_ECall" type="logic">
111 |       <obj_property name="ElementShortName">ID_EX_ECall</obj_property>
112 |       <obj_property name="ObjectShortName">ID_EX_ECall</obj_property>
113 |    </wvobject>
114 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_MRET" type="logic">
115 |       <obj_property name="ElementShortName">ID_EX_MRET</obj_property>
116 |       <obj_property name="ObjectShortName">ID_EX_MRET</obj_property>
117 |    </wvobject>
118 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_interAddr" type="array">
119 |       <obj_property name="ElementShortName">ID_EX_interAddr[31:0]</obj_property>
120 |       <obj_property name="ObjectShortName">ID_EX_interAddr[31:0]</obj_property>
121 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
122 |    </wvobject>
123 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/csr_read" type="array">
124 |       <obj_property name="ElementShortName">csr_read[31:0]</obj_property>
125 |       <obj_property name="ObjectShortName">csr_read[31:0]</obj_property>
126 |    </wvobject>
127 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/csrAddr" type="array">
128 |       <obj_property name="ElementShortName">csrAddr[11:0]</obj_property>
129 |       <obj_property name="ObjectShortName">csrAddr[11:0]</obj_property>
130 |       <obj_property name="Radix">HEXRADIX</obj_property>
131 |    </wvobject>
132 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_CSRWrite" type="logic">
133 |       <obj_property name="ElementShortName">MEM_WB_CSRWrite</obj_property>
134 |       <obj_property name="ObjectShortName">MEM_WB_CSRWrite</obj_property>
135 |    </wvobject>
136 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_RegR1" type="array">
137 |       <obj_property name="ElementShortName">MEM_WB_RegR1[31:0]</obj_property>
138 |       <obj_property name="ObjectShortName">MEM_WB_RegR1[31:0]</obj_property>
139 |       <obj_property name="Radix">BINARYRADIX</obj_property>
140 |    </wvobject>
141 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_CSRData" type="array">
142 |       <obj_property name="ElementShortName">MEM_WB_CSRData[31:0]</obj_property>
143 |       <obj_property name="ObjectShortName">MEM_WB_CSRData[31:0]</obj_property>
144 |       <obj_property name="Radix">BINARYRADIX</obj_property>
145 |    </wvobject>
146 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_CSRI" type="logic">
147 |       <obj_property name="ElementShortName">MEM_WB_CSRI</obj_property>
148 |       <obj_property name="ObjectShortName">MEM_WB_CSRI</obj_property>
149 |    </wvobject>
150 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/csrFile/CSR" type="array">
151 |       <obj_property name="ElementShortName">CSR[6:0][31:0]</obj_property>
152 |       <obj_property name="ObjectShortName">CSR[6:0][31:0]</obj_property>
153 |       <obj_property name="isExpanded"></obj_property>
154 |    </wvobject>
155 |    <wvobject type="divider" fp_name="divider167">
156 |       <obj_property name="label">Branch Or PC Mux</obj_property>
157 |       <obj_property name="DisplayName">label</obj_property>
158 |       <obj_property name="BkColor">#E0FFFF</obj_property>
159 |    </wvobject>
160 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/CompressedFlag" type="logic">
161 |       <obj_property name="ElementShortName">CompressedFlag</obj_property>
162 |       <obj_property name="ObjectShortName">CompressedFlag</obj_property>
163 |    </wvobject>
164 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/PC4_Or_Branch" type="array">
165 |       <obj_property name="ElementShortName">PC4_Or_Branch[31:0]</obj_property>
166 |       <obj_property name="ObjectShortName">PC4_Or_Branch[31:0]</obj_property>
167 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
168 |    </wvobject>
169 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_PC" type="array">
170 |       <obj_property name="ElementShortName">ID_EX_PC[31:0]</obj_property>
171 |       <obj_property name="ObjectShortName">ID_EX_PC[31:0]</obj_property>
172 |    </wvobject>
173 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/PC_Or_Branch" type="array">
174 |       <obj_property name="ElementShortName">PC_Or_Branch[31:0]</obj_property>
175 |       <obj_property name="ObjectShortName">PC_Or_Branch[31:0]</obj_property>
176 |    </wvobject>
177 |    <wvobject type="divider" fp_name="divider165">
178 |       <obj_property name="label">PC Src Mux</obj_property>
179 |       <obj_property name="DisplayName">label</obj_property>
180 |       <obj_property name="BkColor">#E0FFFF</obj_property>
181 |    </wvobject>
182 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/srcOfPC/sel" type="array">
183 |       <obj_property name="ElementShortName">sel[1:0]</obj_property>
184 |       <obj_property name="ObjectShortName">sel[1:0]</obj_property>
185 |    </wvobject>
186 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/srcOfPC/in1" type="array">
187 |       <obj_property name="ElementShortName">in1[31:0]</obj_property>
188 |       <obj_property name="ObjectShortName">in1[31:0]</obj_property>
189 |    </wvobject>
190 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/srcOfPC/in2" type="array">
191 |       <obj_property name="ElementShortName">in2[31:0]</obj_property>
192 |       <obj_property name="ObjectShortName">in2[31:0]</obj_property>
193 |    </wvobject>
194 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/srcOfPC/in3" type="array">
195 |       <obj_property name="ElementShortName">in3[31:0]</obj_property>
196 |       <obj_property name="ObjectShortName">in3[31:0]</obj_property>
197 |    </wvobject>
198 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/srcOfPC/out" type="array">
199 |       <obj_property name="ElementShortName">out[31:0]</obj_property>
200 |       <obj_property name="ObjectShortName">out[31:0]</obj_property>
201 |       <obj_property name="Radix">HEXRADIX</obj_property>
202 |    </wvobject>
203 |    <wvobject type="divider" fp_name="divider4194">
204 |       <obj_property name="label">MEM Address MUX</obj_property>
205 |       <obj_property name="DisplayName">label</obj_property>
206 |       <obj_property name="BkColor">#E0FFFF</obj_property>
207 |    </wvobject>
208 |    <wvobject type="divider" fp_name="divider173">
209 |       <obj_property name="label">MEMORY</obj_property>
210 |       <obj_property name="DisplayName">label</obj_property>
211 |       <obj_property name="BkColor">#E0FFFF</obj_property>
212 |    </wvobject>
213 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/memMuxOut" type="array">
214 |       <obj_property name="ElementShortName">memMuxOut[31:0]</obj_property>
215 |       <obj_property name="ObjectShortName">memMuxOut[31:0]</obj_property>
216 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
217 |    </wvobject>
218 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/Mem_out" type="array">
219 |       <obj_property name="ElementShortName">Mem_out[31:0]</obj_property>
220 |       <obj_property name="ObjectShortName">Mem_out[31:0]</obj_property>
221 |    </wvobject>
222 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/Mem/mem" type="array">
223 |       <obj_property name="ElementShortName">mem[4095:0][7:0]</obj_property>
224 |       <obj_property name="ObjectShortName">mem[4095:0][7:0]</obj_property>
225 |    </wvobject>
226 |    <wvobject type="divider" fp_name="divider4236">
227 |       <obj_property name="label">IF_ID Reg</obj_property>
228 |       <obj_property name="DisplayName">label</obj_property>
229 |       <obj_property name="BkColor">#E0FFFF</obj_property>
230 |    </wvobject>
231 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/IF_ID_InstOut" type="array">
232 |       <obj_property name="ElementShortName">IF_ID_InstOut[31:0]</obj_property>
233 |       <obj_property name="ObjectShortName">IF_ID_InstOut[31:0]</obj_property>
234 |    </wvobject>
235 |    <wvobject type="divider" fp_name="divider120">
236 |       <obj_property name="label">Stages Regs</obj_property>
237 |       <obj_property name="DisplayName">label</obj_property>
238 |       <obj_property name="BkColor">#E0FFFF</obj_property>
239 |    </wvobject>
240 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_PC" type="array">
241 |       <obj_property name="ElementShortName">ID_EX_PC[31:0]</obj_property>
242 |       <obj_property name="ObjectShortName">ID_EX_PC[31:0]</obj_property>
243 |    </wvobject>
244 |    <wvobject type="divider" fp_name="divider174">
245 |       <obj_property name="label">Register</obj_property>
246 |       <obj_property name="DisplayName">label</obj_property>
247 |       <obj_property name="BkColor">#E0FFFF</obj_property>
248 |    </wvobject>
249 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/clk" type="logic">
250 |       <obj_property name="ElementShortName">clk</obj_property>
251 |       <obj_property name="ObjectShortName">clk</obj_property>
252 |    </wvobject>
253 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_CSRWrite" type="logic">
254 |       <obj_property name="ElementShortName">MEM_WB_CSRWrite</obj_property>
255 |       <obj_property name="ObjectShortName">MEM_WB_CSRWrite</obj_property>
256 |    </wvobject>
257 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_csr_read" type="array">
258 |       <obj_property name="ElementShortName">MEM_WB_csr_read[31:0]</obj_property>
259 |       <obj_property name="ObjectShortName">MEM_WB_csr_read[31:0]</obj_property>
260 |    </wvobject>
261 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/RegW" type="array">
262 |       <obj_property name="ElementShortName">RegW[31:0]</obj_property>
263 |       <obj_property name="ObjectShortName">RegW[31:0]</obj_property>
264 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
265 |    </wvobject>
266 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/WriteEn" type="logic">
267 |       <obj_property name="ElementShortName">WriteEn</obj_property>
268 |       <obj_property name="ObjectShortName">WriteEn</obj_property>
269 |    </wvobject>
270 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/regsrc" type="array">
271 |       <obj_property name="ElementShortName">regsrc[4:0]</obj_property>
272 |       <obj_property name="ObjectShortName">regsrc[4:0]</obj_property>
273 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
274 |    </wvobject>
275 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/rs2" type="array">
276 |       <obj_property name="ElementShortName">rs2[4:0]</obj_property>
277 |       <obj_property name="ObjectShortName">rs2[4:0]</obj_property>
278 |    </wvobject>
279 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/RegR1" type="array">
280 |       <obj_property name="ElementShortName">RegR1[31:0]</obj_property>
281 |       <obj_property name="ObjectShortName">RegR1[31:0]</obj_property>
282 |    </wvobject>
283 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/RegR2" type="array">
284 |       <obj_property name="ElementShortName">RegR2[31:0]</obj_property>
285 |       <obj_property name="ObjectShortName">RegR2[31:0]</obj_property>
286 |    </wvobject>
287 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs" type="array">
288 |       <obj_property name="ElementShortName">xs[31:0][31:0]</obj_property>
289 |       <obj_property name="ObjectShortName">xs[31:0][31:0]</obj_property>
290 |       <obj_property name="isExpanded"></obj_property>
291 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[31]" type="array">
292 |          <obj_property name="ElementShortName">[31][31:0]</obj_property>
293 |          <obj_property name="ObjectShortName">[31][31:0]</obj_property>
294 |       </wvobject>
295 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[30]" type="array">
296 |          <obj_property name="ElementShortName">[30][31:0]</obj_property>
297 |          <obj_property name="ObjectShortName">[30][31:0]</obj_property>
298 |       </wvobject>
299 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[29]" type="array">
300 |          <obj_property name="ElementShortName">[29][31:0]</obj_property>
301 |          <obj_property name="ObjectShortName">[29][31:0]</obj_property>
302 |       </wvobject>
303 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[28]" type="array">
304 |          <obj_property name="ElementShortName">[28][31:0]</obj_property>
305 |          <obj_property name="ObjectShortName">[28][31:0]</obj_property>
306 |       </wvobject>
307 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[27]" type="array">
308 |          <obj_property name="ElementShortName">[27][31:0]</obj_property>
309 |          <obj_property name="ObjectShortName">[27][31:0]</obj_property>
310 |       </wvobject>
311 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[26]" type="array">
312 |          <obj_property name="ElementShortName">[26][31:0]</obj_property>
313 |          <obj_property name="ObjectShortName">[26][31:0]</obj_property>
314 |       </wvobject>
315 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[25]" type="array">
316 |          <obj_property name="ElementShortName">[25][31:0]</obj_property>
317 |          <obj_property name="ObjectShortName">[25][31:0]</obj_property>
318 |       </wvobject>
319 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[24]" type="array">
320 |          <obj_property name="ElementShortName">[24][31:0]</obj_property>
321 |          <obj_property name="ObjectShortName">[24][31:0]</obj_property>
322 |       </wvobject>
323 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[23]" type="array">
324 |          <obj_property name="ElementShortName">[23][31:0]</obj_property>
325 |          <obj_property name="ObjectShortName">[23][31:0]</obj_property>
326 |       </wvobject>
327 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[22]" type="array">
328 |          <obj_property name="ElementShortName">[22][31:0]</obj_property>
329 |          <obj_property name="ObjectShortName">[22][31:0]</obj_property>
330 |       </wvobject>
331 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[21]" type="array">
332 |          <obj_property name="ElementShortName">[21][31:0]</obj_property>
333 |          <obj_property name="ObjectShortName">[21][31:0]</obj_property>
334 |       </wvobject>
335 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[20]" type="array">
336 |          <obj_property name="ElementShortName">[20][31:0]</obj_property>
337 |          <obj_property name="ObjectShortName">[20][31:0]</obj_property>
338 |       </wvobject>
339 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[19]" type="array">
340 |          <obj_property name="ElementShortName">[19][31:0]</obj_property>
341 |          <obj_property name="ObjectShortName">[19][31:0]</obj_property>
342 |       </wvobject>
343 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[18]" type="array">
344 |          <obj_property name="ElementShortName">[18][31:0]</obj_property>
345 |          <obj_property name="ObjectShortName">[18][31:0]</obj_property>
346 |       </wvobject>
347 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[17]" type="array">
348 |          <obj_property name="ElementShortName">[17][31:0]</obj_property>
349 |          <obj_property name="ObjectShortName">[17][31:0]</obj_property>
350 |       </wvobject>
351 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[16]" type="array">
352 |          <obj_property name="ElementShortName">[16][31:0]</obj_property>
353 |          <obj_property name="ObjectShortName">[16][31:0]</obj_property>
354 |       </wvobject>
355 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[15]" type="array">
356 |          <obj_property name="ElementShortName">[15][31:0]</obj_property>
357 |          <obj_property name="ObjectShortName">[15][31:0]</obj_property>
358 |       </wvobject>
359 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[14]" type="array">
360 |          <obj_property name="ElementShortName">[14][31:0]</obj_property>
361 |          <obj_property name="ObjectShortName">[14][31:0]</obj_property>
362 |       </wvobject>
363 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[13]" type="array">
364 |          <obj_property name="ElementShortName">[13][31:0]</obj_property>
365 |          <obj_property name="ObjectShortName">[13][31:0]</obj_property>
366 |       </wvobject>
367 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[12]" type="array">
368 |          <obj_property name="ElementShortName">[12][31:0]</obj_property>
369 |          <obj_property name="ObjectShortName">[12][31:0]</obj_property>
370 |       </wvobject>
371 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[11]" type="array">
372 |          <obj_property name="ElementShortName">[11][31:0]</obj_property>
373 |          <obj_property name="ObjectShortName">[11][31:0]</obj_property>
374 |       </wvobject>
375 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[10]" type="array">
376 |          <obj_property name="ElementShortName">[10][31:0]</obj_property>
377 |          <obj_property name="ObjectShortName">[10][31:0]</obj_property>
378 |       </wvobject>
379 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[9]" type="array">
380 |          <obj_property name="ElementShortName">[9][31:0]</obj_property>
381 |          <obj_property name="ObjectShortName">[9][31:0]</obj_property>
382 |       </wvobject>
383 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[8]" type="array">
384 |          <obj_property name="ElementShortName">[8][31:0]</obj_property>
385 |          <obj_property name="ObjectShortName">[8][31:0]</obj_property>
386 |       </wvobject>
387 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[7]" type="array">
388 |          <obj_property name="ElementShortName">[7][31:0]</obj_property>
389 |          <obj_property name="ObjectShortName">[7][31:0]</obj_property>
390 |       </wvobject>
391 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[6]" type="array">
392 |          <obj_property name="ElementShortName">[6][31:0]</obj_property>
393 |          <obj_property name="ObjectShortName">[6][31:0]</obj_property>
394 |       </wvobject>
395 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[5]" type="array">
396 |          <obj_property name="ElementShortName">[5][31:0]</obj_property>
397 |          <obj_property name="ObjectShortName">[5][31:0]</obj_property>
398 |       </wvobject>
399 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[4]" type="array">
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483 |       </wvobject>
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492 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[13]" type="array">
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498 |          <obj_property name="ObjectShortName">[12][31:0]</obj_property>
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500 |       <wvobject fp_name="/cpu_tb/cpuTest/CPU/rf/xs[11]" type="array">
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551 |       <obj_property name="DisplayName">label</obj_property>
552 |       <obj_property name="BkColor">#E0FFFF</obj_property>
553 |    </wvobject>
554 |    <wvobject type="divider" fp_name="divider4237">
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556 |       <obj_property name="DisplayName">label</obj_property>
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559 |    <wvobject type="divider" fp_name="divider210">
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562 |       <obj_property name="BkColor">#E0FFFF</obj_property>
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566 |       <obj_property name="ObjectShortName">fwdA[1:0]</obj_property>
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570 |       <obj_property name="ObjectShortName">fwdB[1:0]</obj_property>
571 |    </wvobject>
572 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_RegR1" type="array">
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574 |       <obj_property name="ObjectShortName">ID_EX_RegR1[31:0]</obj_property>
575 |       <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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577 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ALUSrcMux_out" type="array">
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594 |       <obj_property name="ObjectShortName">ALU_out[31:0]</obj_property>
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597 |    <wvobject type="divider" fp_name="divider4278">
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599 |       <obj_property name="DisplayName">label</obj_property>
600 |       <obj_property name="BkColor">#E0FFFF</obj_property>
601 |    </wvobject>
602 |    <wvobject type="divider" fp_name="divider213">
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605 |       <obj_property name="BkColor">#E0FFFF</obj_property>
606 |    </wvobject>
607 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/branchTaken" type="logic">
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609 |       <obj_property name="ObjectShortName">branchTaken</obj_property>
610 |    </wvobject>
611 |    <wvobject type="divider" fp_name="divider8403">
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614 |       <obj_property name="BkColor">#E0FFFF</obj_property>
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616 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/instr" type="array">
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618 |       <obj_property name="ObjectShortName">instr[31:0]</obj_property>
619 |    </wvobject>
620 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/opcode" type="array">
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622 |       <obj_property name="ObjectShortName">opcode[4:0]</obj_property>
623 |    </wvobject>
624 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/Branch" type="logic">
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626 |       <obj_property name="ObjectShortName">Branch</obj_property>
627 |    </wvobject>
628 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/Jump" type="array">
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630 |       <obj_property name="ObjectShortName">Jump[1:0]</obj_property>
631 |    </wvobject>
632 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/MemRead" type="logic">
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634 |       <obj_property name="ObjectShortName">MemRead</obj_property>
635 |    </wvobject>
636 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/MemToReg" type="logic">
637 |       <obj_property name="ElementShortName">MemToReg</obj_property>
638 |       <obj_property name="ObjectShortName">MemToReg</obj_property>
639 |    </wvobject>
640 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/ALUOp" type="array">
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642 |       <obj_property name="ObjectShortName">ALUOp[1:0]</obj_property>
643 |    </wvobject>
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646 |       <obj_property name="ObjectShortName">MemWrite</obj_property>
647 |    </wvobject>
648 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/ALUSrc" type="logic">
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650 |       <obj_property name="ObjectShortName">ALUSrc</obj_property>
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654 |       <obj_property name="ObjectShortName">RegWrite</obj_property>
655 |    </wvobject>
656 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/Mode" type="array">
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658 |       <obj_property name="ObjectShortName">Mode[2:0]</obj_property>
659 |    </wvobject>
660 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/Lui" type="logic">
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662 |       <obj_property name="ObjectShortName">Lui</obj_property>
663 |    </wvobject>
664 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/ECall" type="logic">
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666 |       <obj_property name="ObjectShortName">ECall</obj_property>
667 |    </wvobject>
668 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/EBreak" type="logic">
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670 |       <obj_property name="ObjectShortName">EBreak</obj_property>
671 |    </wvobject>
672 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/MRET" type="logic">
673 |       <obj_property name="ElementShortName">MRET</obj_property>
674 |       <obj_property name="ObjectShortName">MRET</obj_property>
675 |    </wvobject>
676 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/cu/CSRWrite" type="logic">
677 |       <obj_property name="ElementShortName">CSRWrite</obj_property>
678 |       <obj_property name="ObjectShortName">CSRWrite</obj_property>
679 |    </wvobject>
680 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/MEM_WB_Ctrl[1]" type="logic">
681 |       <obj_property name="ElementShortName">[1]</obj_property>
682 |       <obj_property name="ObjectShortName">[1]</obj_property>
683 |    </wvobject>
684 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/EX_MEM_Ctrl[4]" type="logic">
685 |       <obj_property name="ElementShortName">[4]</obj_property>
686 |       <obj_property name="ObjectShortName">[4]</obj_property>
687 |    </wvobject>
688 |    <wvobject fp_name="/cpu_tb/cpuTest/CPU/ID_EX_Ctrl[7]" type="logic">
689 |       <obj_property name="ElementShortName">[7]</obj_property>
690 |       <obj_property name="ObjectShortName">[7]</obj_property>
691 |    </wvobject>
692 | </wave_config>
693 | 


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