├── ChangeLog_core.txt ├── ChangeLog_tools.txt ├── core ├── bench │ └── verilog │ │ ├── dbg_uart_tasks.v │ │ ├── msp_debug.v │ │ ├── ram.v │ │ ├── registers.v │ │ ├── tb_openMSP430.v │ │ └── timescale.v ├── doc │ └── slau049f.pdf ├── rtl │ └── verilog │ │ ├── omsp_alu.v │ │ ├── omsp_clock_module.v │ │ ├── omsp_dbg.v │ │ ├── omsp_dbg_hwbrk.v │ │ ├── omsp_dbg_uart.v │ │ ├── omsp_execution_unit.v │ │ ├── omsp_frontend.v │ │ ├── omsp_mem_backbone.v │ │ ├── omsp_multiplier.v │ │ ├── omsp_register_file.v │ │ ├── omsp_sfr.v │ │ ├── omsp_sync_cell.v │ │ ├── omsp_watchdog.v │ │ ├── openMSP430.v │ │ ├── openMSP430_defines.v │ │ ├── openMSP430_undefines.v │ │ └── periph │ │ ├── omsp_gpio.v │ │ ├── omsp_timerA.v │ │ ├── omsp_timerA_defines.v │ │ ├── omsp_timerA_undefines.v │ │ ├── template_periph_16b.v │ │ └── template_periph_8b.v ├── sim │ └── rtl_sim │ │ ├── bin │ │ ├── asm2ihex.sh │ │ ├── cov_exclude.dat │ │ ├── cov_exclude_bits.dat │ │ ├── cov_iccr_merge.cf │ │ ├── cov_ncverilog.ccf │ │ ├── cov_ncverilog.tcl │ │ ├── ihex2mem.tcl │ │ ├── msp430sim │ │ ├── msp430sim_c │ │ ├── rtlsim.sh │ │ └── template.def │ │ ├── run │ │ ├── load_waveform.sav │ │ ├── run │ │ ├── run_all │ │ ├── run_all_mpy │ │ ├── run_c │ │ ├── run_coverage_analysis │ │ └── run_disassemble │ │ ├── src-c │ │ └── sandbox │ │ │ ├── linker.def │ │ │ ├── main.c │ │ │ ├── makefile │ │ │ └── sandbox.v │ │ └── src │ │ ├── c-jump_jc.s43 │ │ ├── c-jump_jc.v │ │ ├── c-jump_jeq.s43 │ │ ├── c-jump_jeq.v │ │ ├── c-jump_jge.s43 │ │ ├── c-jump_jge.v │ │ ├── c-jump_jl.s43 │ │ ├── c-jump_jl.v │ │ ├── c-jump_jmp.s43 │ │ ├── c-jump_jmp.v │ │ ├── c-jump_jn.s43 │ │ ├── c-jump_jn.v │ │ ├── c-jump_jnc.s43 │ │ ├── c-jump_jnc.v │ │ ├── c-jump_jne.s43 │ │ ├── c-jump_jne.v │ │ ├── clock_module.s43 │ │ ├── clock_module.v │ │ ├── dbg_cpu.s43 │ │ ├── dbg_cpu.v │ │ ├── dbg_halt_irq.s43 │ │ ├── dbg_halt_irq.v │ │ ├── dbg_hwbrk0.s43 │ │ ├── dbg_hwbrk0.v │ │ ├── dbg_hwbrk1.s43 │ │ ├── dbg_hwbrk1.v │ │ ├── dbg_hwbrk2.s43 │ │ ├── dbg_hwbrk2.v │ │ ├── dbg_hwbrk3.s43 │ │ ├── dbg_hwbrk3.v │ │ ├── dbg_mem.s43 │ │ ├── dbg_mem.v │ │ ├── dbg_onoff.s43 │ │ ├── dbg_onoff.v │ │ ├── dbg_uart.s43 │ │ ├── dbg_uart.v │ │ ├── gpio_irq.s43 │ │ ├── gpio_irq.v │ │ ├── gpio_rdwr.s43 │ │ ├── gpio_rdwr.v │ │ ├── ldscript_example.x │ │ ├── mpy_basic.s43 │ │ ├── mpy_basic.v │ │ ├── mpy_mac.s43 │ │ ├── mpy_mac.v │ │ ├── mpy_macs.s43 │ │ ├── mpy_macs.v │ │ ├── mpy_mpy.s43 │ │ ├── mpy_mpy.v │ │ ├── mpy_mpys.s43 │ │ ├── mpy_mpys.v │ │ ├── op_modes.s43 │ │ ├── op_modes.v │ │ ├── sandbox.s43 │ │ ├── sandbox.v │ │ ├── sing-op_call.s43 │ │ ├── sing-op_call.v │ │ ├── sing-op_call_rom-rd.s43 │ │ ├── sing-op_call_rom-rd.v │ │ ├── sing-op_push.s43 │ │ ├── sing-op_push.v │ │ ├── sing-op_push_rom-rd.s43 │ │ ├── sing-op_push_rom-rd.v │ │ ├── sing-op_reti.s43 │ │ ├── sing-op_reti.v │ │ ├── sing-op_rra.s43 │ │ ├── sing-op_rra.v │ │ ├── sing-op_rrc.s43 │ │ ├── sing-op_rrc.v │ │ ├── sing-op_swpb.s43 │ │ ├── sing-op_swpb.v │ │ ├── sing-op_sxt.s43 │ │ ├── sing-op_sxt.v │ │ ├── submit.f │ │ ├── tA_capture.s43 │ │ ├── tA_capture.v │ │ ├── tA_clkmux.s43 │ │ ├── tA_clkmux.v │ │ ├── tA_compare.s43 │ │ ├── tA_compare.v │ │ ├── tA_modes.s43 │ │ ├── tA_modes.v │ │ ├── tA_output.s43 │ │ ├── tA_output.v │ │ ├── template_periph_16b.s43 │ │ ├── template_periph_16b.v │ │ ├── template_periph_8b.s43 │ │ ├── template_periph_8b.v │ │ ├── two-op_add-b.s43 │ │ ├── two-op_add-b.v │ │ ├── two-op_add.s43 │ │ ├── two-op_add.v │ │ ├── two-op_add_rom-rd.s43 │ │ ├── two-op_add_rom-rd.v │ │ ├── two-op_addc.s43 │ │ ├── two-op_addc.v │ │ ├── two-op_and.s43 │ │ ├── two-op_and.v │ │ ├── two-op_bic.s43 │ │ ├── two-op_bic.v │ │ ├── two-op_bis.s43 │ │ ├── two-op_bis.v │ │ ├── two-op_bit.s43 │ │ ├── two-op_bit.v │ │ ├── two-op_cmp.s43 │ │ ├── two-op_cmp.v │ │ ├── two-op_dadd.s43 │ │ ├── two-op_dadd.v │ │ ├── two-op_mov-b.s43 │ │ ├── two-op_mov-b.v │ │ ├── two-op_mov.s43 │ │ ├── two-op_mov.v │ │ ├── two-op_sub.s43 │ │ ├── two-op_sub.v │ │ ├── two-op_subc.s43 │ │ ├── two-op_subc.v │ │ ├── two-op_xor.s43 │ │ ├── two-op_xor.v │ │ ├── wdt_clkmux.s43 │ │ ├── wdt_clkmux.v │ │ ├── wdt_interval.s43 │ │ ├── wdt_interval.v │ │ ├── wdt_watchdog.s43 │ │ └── wdt_watchdog.v └── synthesis │ ├── actel │ ├── design_files.sdc │ ├── design_files.v │ ├── libero_designer.tcl │ ├── run_analysis.log │ ├── run_analysis.mpy.log │ ├── run_analysis.tcl │ ├── src │ │ ├── omsp_alu.v │ │ ├── omsp_clock_module.v │ │ ├── omsp_dbg.v │ │ ├── omsp_dbg_hwbrk.v │ │ ├── omsp_dbg_uart.v │ │ ├── omsp_execution_unit.v │ │ ├── omsp_frontend.v │ │ ├── omsp_mem_backbone.v │ │ ├── omsp_register_file.v │ │ ├── omsp_sfr.v │ │ ├── omsp_watchdog.v │ │ ├── openMSP430.v │ │ ├── openMSP430_defines.v │ │ ├── openMSP430_fpga.v │ │ ├── openMSP430_undefines.v │ │ ├── smartgen │ │ │ ├── dmem.v │ │ │ └── pmem.v │ │ └── timescale.v │ └── synplify.tcl │ ├── altera │ ├── design_files.v │ ├── openMSP430_fpga.tcl │ ├── run_analysis.area.log │ ├── run_analysis.area.mpy.log │ ├── run_analysis.speed.log │ ├── run_analysis.speed.mpy.log │ ├── run_analysis.tcl │ └── src │ │ ├── arch.v │ │ ├── megawizard │ │ ├── arria2gx_dmem.v │ │ ├── arria2gx_pmem.v │ │ ├── arriagx_dmem.v │ │ ├── arriagx_pmem.v │ │ ├── cyclone2_dmem.v │ │ ├── cyclone2_pmem.v │ │ ├── cyclone3_dmem.v │ │ ├── cyclone3_pmem.v │ │ ├── cyclone4gx_dmem.v │ │ ├── cyclone4gx_pmem.v │ │ ├── stratix2_dmem.v │ │ ├── stratix2_pmem.v │ │ ├── stratix3_dmem.v │ │ ├── stratix3_pmem.v │ │ ├── stratix_dmem.v │ │ └── stratix_pmem.v │ │ ├── openMSP430_defines.v │ │ ├── openMSP430_fpga.v │ │ ├── openMSP430_undefines.v │ │ └── timescale.v │ ├── synopsys │ ├── constraints.tcl │ ├── library.tcl │ ├── read.tcl │ ├── run_syn │ └── synthesis.tcl │ └── xilinx │ ├── openMSP430_fpga.prj │ ├── openMSP430_fpga.ucf │ ├── run_analysis.area.log │ ├── run_analysis.area.mpy.log │ ├── run_analysis.speed.log │ ├── run_analysis.speed.mpy.log │ ├── run_analysis.tcl │ ├── src │ ├── arch.v │ ├── coregen │ │ ├── .lso │ │ ├── blk_mem_gen_ds512.pdf │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── spartan3.cgp │ │ ├── spartan3_dmem.gise │ │ ├── spartan3_dmem.ise │ │ ├── spartan3_dmem.ngc │ │ ├── spartan3_dmem.v │ │ ├── spartan3_dmem.veo │ │ ├── spartan3_dmem.xco │ │ ├── spartan3_dmem.xise │ │ ├── spartan3_dmem_flist.txt │ │ ├── spartan3_dmem_readme.txt │ │ ├── spartan3_dmem_xmdf.tcl │ │ ├── spartan3_pmem.gise │ │ ├── spartan3_pmem.ise │ │ ├── spartan3_pmem.ngc │ │ ├── spartan3_pmem.v │ │ ├── spartan3_pmem.veo │ │ ├── spartan3_pmem.xco │ │ ├── spartan3_pmem.xise │ │ ├── spartan3_pmem_flist.txt │ │ ├── spartan3_pmem_readme.txt │ │ ├── spartan3_pmem_xmdf.tcl │ │ ├── spartan3a.cgp │ │ ├── spartan3a_dmem.asy │ │ ├── spartan3a_dmem.gise │ │ ├── spartan3a_dmem.ise │ │ ├── spartan3a_dmem.ngc │ │ ├── spartan3a_dmem.v │ │ ├── spartan3a_dmem.veo │ │ ├── spartan3a_dmem.vhd │ │ ├── spartan3a_dmem.vho │ │ ├── spartan3a_dmem.xco │ │ ├── spartan3a_dmem.xise │ │ ├── spartan3a_dmem_flist.txt │ │ ├── spartan3a_dmem_readme.txt │ │ ├── spartan3a_dmem_xmdf.tcl │ │ ├── spartan3a_pmem.gise │ │ ├── spartan3a_pmem.ise │ │ ├── spartan3a_pmem.ngc │ │ ├── spartan3a_pmem.v │ │ ├── spartan3a_pmem.veo │ │ ├── spartan3a_pmem.xco │ │ ├── spartan3a_pmem.xise │ │ ├── spartan3a_pmem_flist.txt │ │ ├── spartan3a_pmem_readme.txt │ │ ├── spartan3a_pmem_xmdf.tcl │ │ ├── spartan3adsp.cgp │ │ ├── spartan3adsp_dmem.asy │ │ ├── spartan3adsp_dmem.gise │ │ ├── spartan3adsp_dmem.ise │ │ ├── spartan3adsp_dmem.ngc │ │ ├── spartan3adsp_dmem.sym │ │ ├── spartan3adsp_dmem.v │ │ ├── spartan3adsp_dmem.veo │ │ ├── spartan3adsp_dmem.vhd │ │ ├── spartan3adsp_dmem.vho │ │ ├── spartan3adsp_dmem.xco │ │ ├── spartan3adsp_dmem.xise │ │ ├── spartan3adsp_dmem_flist.txt │ │ ├── spartan3adsp_dmem_readme.txt │ │ ├── spartan3adsp_dmem_xmdf.tcl │ │ ├── spartan3adsp_pmem.asy │ │ ├── spartan3adsp_pmem.gise │ │ ├── spartan3adsp_pmem.ise │ │ ├── spartan3adsp_pmem.ngc │ │ ├── spartan3adsp_pmem.sym │ │ ├── spartan3adsp_pmem.v │ │ ├── spartan3adsp_pmem.veo │ │ ├── spartan3adsp_pmem.vhd │ │ ├── spartan3adsp_pmem.vho │ │ ├── spartan3adsp_pmem.xco │ │ ├── spartan3adsp_pmem.xise │ │ ├── spartan3adsp_pmem_flist.txt │ │ ├── spartan3adsp_pmem_readme.txt │ │ ├── spartan3adsp_pmem_xmdf.tcl │ │ ├── spartan3e.cgp │ │ ├── spartan3e_dmem.gise │ │ ├── spartan3e_dmem.ise │ │ ├── spartan3e_dmem.ngc │ │ ├── spartan3e_dmem.v │ │ ├── spartan3e_dmem.veo │ │ ├── spartan3e_dmem.xco │ │ ├── spartan3e_dmem.xise │ │ ├── spartan3e_dmem_flist.txt │ │ ├── spartan3e_dmem_readme.txt │ │ ├── spartan3e_dmem_xmdf.tcl │ │ ├── spartan3e_pmem.gise │ │ ├── spartan3e_pmem.ise │ │ ├── spartan3e_pmem.ngc │ │ ├── spartan3e_pmem.v │ │ ├── spartan3e_pmem.veo │ │ ├── spartan3e_pmem.xco │ │ ├── spartan3e_pmem.xise │ │ ├── spartan3e_pmem_flist.txt │ │ ├── spartan3e_pmem_readme.txt │ │ ├── spartan3e_pmem_xmdf.tcl │ │ ├── spartan6.cgp │ │ ├── spartan6_dmem.gise │ │ ├── spartan6_dmem.ise │ │ ├── spartan6_dmem.ngc │ │ ├── spartan6_dmem.v │ │ ├── spartan6_dmem.veo │ │ ├── spartan6_dmem.xco │ │ ├── spartan6_dmem.xise │ │ ├── spartan6_dmem_flist.txt │ │ ├── spartan6_dmem_readme.txt │ │ ├── spartan6_dmem_xmdf.tcl │ │ ├── spartan6_pmem.gise │ │ ├── spartan6_pmem.ise │ │ ├── spartan6_pmem.ngc │ │ ├── spartan6_pmem.v │ │ ├── spartan6_pmem.veo │ │ ├── spartan6_pmem.xco │ │ ├── spartan6_pmem.xise │ │ ├── spartan6_pmem_flist.txt │ │ ├── spartan6_pmem_readme.txt │ │ ├── spartan6_pmem_xmdf.tcl │ │ ├── virtex4.cgp │ │ ├── virtex4_dmem.gise │ │ ├── virtex4_dmem.ise │ │ ├── virtex4_dmem.ngc │ │ ├── virtex4_dmem.v │ │ ├── virtex4_dmem.veo │ │ ├── virtex4_dmem.xco │ │ ├── virtex4_dmem.xise │ │ ├── virtex4_dmem_flist.txt │ │ ├── virtex4_dmem_readme.txt │ │ ├── virtex4_dmem_xmdf.tcl │ │ ├── virtex4_pmem.gise │ │ ├── virtex4_pmem.ise │ │ ├── virtex4_pmem.ngc │ │ ├── virtex4_pmem.v │ │ ├── virtex4_pmem.veo │ │ ├── virtex4_pmem.xco │ │ ├── virtex4_pmem.xise │ │ ├── virtex4_pmem_flist.txt │ │ ├── virtex4_pmem_readme.txt │ │ ├── virtex4_pmem_xmdf.tcl │ │ ├── virtex4lx.cgp │ │ ├── virtex5.cgp │ │ ├── virtex5_dmem.gise │ │ ├── virtex5_dmem.ise │ │ ├── virtex5_dmem.ngc │ │ ├── virtex5_dmem.v │ │ ├── virtex5_dmem.veo │ │ ├── virtex5_dmem.xco │ │ ├── virtex5_dmem.xise │ │ ├── virtex5_dmem_flist.txt │ │ ├── virtex5_dmem_readme.txt │ │ ├── virtex5_dmem_xmdf.tcl │ │ ├── virtex5_pmem.gise │ │ ├── virtex5_pmem.ise │ │ ├── virtex5_pmem.ngc │ │ ├── virtex5_pmem.v │ │ ├── virtex5_pmem.veo │ │ ├── virtex5_pmem.xco │ │ ├── virtex5_pmem.xise │ │ ├── virtex5_pmem_flist.txt │ │ ├── virtex5_pmem_readme.txt │ │ ├── virtex5_pmem_xmdf.tcl │ │ ├── virtex6.cgp │ │ ├── virtex6_dmem.asy │ │ ├── virtex6_dmem.gise │ │ ├── virtex6_dmem.ise │ │ ├── virtex6_dmem.ngc │ │ ├── virtex6_dmem.v │ │ ├── virtex6_dmem.veo │ │ ├── virtex6_dmem.vhd │ │ ├── virtex6_dmem.vho │ │ ├── virtex6_dmem.xco │ │ ├── virtex6_dmem.xise │ │ ├── virtex6_dmem_flist.txt │ │ ├── virtex6_dmem_readme.txt │ │ ├── virtex6_dmem_xmdf.tcl │ │ ├── virtex6_pmem.asy │ │ ├── virtex6_pmem.gise │ │ ├── virtex6_pmem.ise │ │ ├── virtex6_pmem.ngc │ │ ├── virtex6_pmem.v │ │ ├── virtex6_pmem.veo │ │ ├── virtex6_pmem.vhd │ │ ├── virtex6_pmem.vho │ │ ├── virtex6_pmem.xco │ │ ├── virtex6_pmem.xise │ │ ├── virtex6_pmem_flist.txt │ │ ├── virtex6_pmem_readme.txt │ │ └── virtex6_pmem_xmdf.tcl │ ├── openMSP430_defines.v │ ├── openMSP430_fpga.v │ ├── openMSP430_undefines.v │ └── timescale.v │ ├── xst_verilog_spartan3.opt │ ├── xst_verilog_spartan3a.opt │ ├── xst_verilog_spartan3adsp.opt │ ├── xst_verilog_spartan3e.opt │ ├── xst_verilog_spartan6.opt │ ├── xst_verilog_virtex4.opt │ ├── xst_verilog_virtex5.opt │ └── xst_verilog_virtex6.opt ├── doc ├── html │ ├── area_speed.html │ ├── core.html │ ├── files_directory_description.html │ ├── images │ │ ├── clock_diagram.odg │ │ ├── clock_diagram.png │ │ ├── clock_example.odg │ │ ├── clock_example.png │ │ ├── core_integration.odg │ │ ├── core_integration.png │ │ ├── cpu_mem_space.odg │ │ ├── cpu_mem_space.png │ │ ├── cpu_structure.odg │ │ ├── cpu_structure.png │ │ ├── dbg_uart_8N1.odg │ │ ├── dbg_uart_8N1.png │ │ ├── dbg_uart_cmd_frame.odg │ │ ├── dbg_uart_cmd_frame.png │ │ ├── dbg_uart_cmd_read.odg │ │ ├── dbg_uart_cmd_read.png │ │ ├── dbg_uart_cmd_read_burst.odg │ │ ├── dbg_uart_cmd_read_burst.png │ │ ├── dbg_uart_cmd_write.odg │ │ ├── dbg_uart_cmd_write.png │ │ ├── dbg_uart_cmd_write_burst.odg │ │ ├── dbg_uart_cmd_write_burst.png │ │ ├── dbg_uart_sync_frame.odg │ │ ├── dbg_uart_sync_frame.png │ │ ├── gdbproxy_flow.odg │ │ ├── gdbproxy_flow.png │ │ ├── openmsp430-extra_info.png │ │ ├── openmsp430-gdbproxy-ddd.png │ │ ├── openmsp430-gdbproxy-eclipse.png │ │ ├── openmsp430-gdbproxy.png │ │ ├── openmsp430-loader_lin.png │ │ ├── openmsp430-loader_win.png │ │ ├── openmsp430-minidebug.png │ │ ├── spacewar.png │ │ ├── wave_clocks.odg │ │ ├── wave_clocks.png │ │ ├── wave_dmem.odg │ │ ├── wave_dmem.png │ │ ├── wave_irq.odg │ │ ├── wave_irq.png │ │ ├── wave_per.odg │ │ ├── wave_per.png │ │ ├── wave_pmem.odg │ │ ├── wave_pmem.png │ │ ├── wave_resets.odg │ │ ├── wave_resets.png │ │ └── wave_sdi.png │ ├── integration.html │ ├── overview.html │ ├── serial_debug_interface.html │ └── software_development_tools.html ├── openMSP430.odt ├── openMSP430.pdf └── size_speed_analysis.ods ├── fpga ├── actel_m1a3pl_dev_kit │ ├── bench │ │ └── verilog │ │ │ ├── DAC121S101.v │ │ │ ├── dbg_uart_tasks.v │ │ │ ├── msp_debug.v │ │ │ ├── proasic3l.v │ │ │ ├── registers.v │ │ │ ├── tb_openMSP430_fpga.v │ │ │ └── timescale.v │ ├── doc │ │ ├── M1A3PL_DEV_KIT_QS.pdf │ │ └── M1IGLOO_StarterKit_v1_5_UG.pdf │ ├── rtl │ │ └── verilog │ │ │ ├── dac_spi_if.v │ │ │ ├── openMSP430_fpga.v │ │ │ ├── openmsp430 │ │ │ ├── omsp_alu.v │ │ │ ├── omsp_clock_module.v │ │ │ ├── omsp_dbg.v │ │ │ ├── omsp_dbg_hwbrk.v │ │ │ ├── omsp_dbg_uart.v │ │ │ ├── omsp_execution_unit.v │ │ │ ├── omsp_frontend.v │ │ │ ├── omsp_mem_backbone.v │ │ │ ├── omsp_multiplier.v │ │ │ ├── omsp_register_file.v │ │ │ ├── omsp_sfr.v │ │ │ ├── omsp_sync_cell.v │ │ │ ├── omsp_watchdog.v │ │ │ ├── openMSP430.v │ │ │ ├── openMSP430_defines.v │ │ │ ├── openMSP430_undefines.v │ │ │ └── periph │ │ │ │ ├── omsp_gpio.v │ │ │ │ ├── omsp_timerA.v │ │ │ │ ├── omsp_timerA_defines.v │ │ │ │ ├── omsp_timerA_undefines.v │ │ │ │ ├── template_periph_16b.v │ │ │ │ └── template_periph_8b.v │ │ │ └── smartgen │ │ │ ├── dmem_128B.v │ │ │ └── pmem_2kB.v │ ├── sim │ │ └── rtl_sim │ │ │ ├── bin │ │ │ ├── ihex2mem.tcl │ │ │ ├── msp430sim │ │ │ └── rtlsim.sh │ │ │ ├── run │ │ │ ├── run │ │ │ └── run_disassemble │ │ │ └── src │ │ │ ├── spacewar.v │ │ │ └── submit.f │ ├── software │ │ └── spacewar │ │ │ ├── Spacewar!_Oscilloscope_Game_(MSP430) │ │ │ ├── bzsin.c │ │ │ ├── cline.c │ │ │ ├── compar.c │ │ │ ├── explode.c │ │ │ ├── hardware.c │ │ │ ├── main.c │ │ │ ├── makefile │ │ │ ├── oscilloscope_screenshot.png │ │ │ ├── point.c │ │ │ ├── reset.c │ │ │ ├── rocket1.c │ │ │ ├── rocket2.c │ │ │ ├── score.c │ │ │ ├── spacewar.h │ │ │ └── update.c │ └── synthesis │ │ └── actel │ │ ├── design_constraints.pdc │ │ ├── design_constraints.post.sdc │ │ ├── design_constraints.pre.sdc │ │ ├── design_files.v │ │ ├── libero_designer.tcl │ │ ├── prepare_implementation.tcl │ │ └── synplify.tcl ├── altera_de1_board │ ├── README │ ├── bench │ │ └── verilog │ │ │ ├── altsyncram.v │ │ │ ├── msp_debug.v │ │ │ ├── registers.v │ │ │ ├── tb_openMSP430_fpga.v │ │ │ └── timescale.v │ ├── doc │ │ ├── DE1_Board_Schematic.pdf │ │ ├── DE1_Reference_Manual.pdf │ │ └── DE1_User Guide.pdf │ ├── rtl │ │ └── verilog │ │ │ ├── OpenMSP430_fpga.v │ │ │ ├── driver_7segment.v │ │ │ ├── ext_de1_sram.v │ │ │ ├── io_mux.v │ │ │ ├── openmsp430 │ │ │ ├── omsp_alu.v │ │ │ ├── omsp_clock_module.v │ │ │ ├── omsp_dbg.v │ │ │ ├── omsp_dbg_hwbrk.v │ │ │ ├── omsp_dbg_uart.v │ │ │ ├── omsp_execution_unit.v │ │ │ ├── omsp_frontend.v │ │ │ ├── omsp_mem_backbone.v │ │ │ ├── omsp_multiplier.v │ │ │ ├── omsp_register_file.v │ │ │ ├── omsp_sfr.v │ │ │ ├── omsp_sync_cell.v │ │ │ ├── omsp_watchdog.v │ │ │ ├── openMSP430.v │ │ │ ├── openMSP430_defines.v │ │ │ ├── openMSP430_undefines.v │ │ │ └── periph │ │ │ │ ├── omsp_gpio.v │ │ │ │ ├── omsp_timerA.v │ │ │ │ ├── omsp_timerA_defines.v │ │ │ │ ├── omsp_timerA_undefines.v │ │ │ │ ├── template_periph_16b.v │ │ │ │ └── template_periph_8b.v │ │ │ ├── ram16x512.v │ │ │ └── rom16x2048.v │ ├── sim │ │ └── rtl_sim │ │ │ ├── bin │ │ │ ├── ihex2mem.tcl │ │ │ ├── msp430sim │ │ │ └── rtlsim.sh │ │ │ ├── run │ │ │ ├── run │ │ │ └── run_disassemble │ │ │ └── src │ │ │ ├── memledtest.v │ │ │ └── submit.f │ ├── software │ │ ├── bin │ │ │ ├── mifwrite │ │ │ ├── mifwrite.cpp │ │ │ └── mifwrite.exe │ │ └── memledtest │ │ │ ├── 7seg.c │ │ │ ├── 7seg.h │ │ │ ├── README │ │ │ ├── gray.c │ │ │ ├── gray.h │ │ │ ├── hardware.h │ │ │ ├── link.ld │ │ │ ├── main.c │ │ │ ├── makefile │ │ │ ├── memtest.c │ │ │ └── memtest.h │ └── synthesis │ │ └── altera │ │ ├── OpenMSP430_fpga.qpf │ │ ├── main.qsf │ │ ├── main.sof │ │ └── openMSP430_fpga_top.v ├── xilinx_avnet_lx9microbard │ ├── README │ ├── doc │ │ ├── S90_Avt_S6LX9_MicroBoard_Schematic_RevB_112801.pdf │ │ ├── U60_xlx_s9_lx9_fpga_microboard-ug022811.pdf │ │ └── msp430f1121a.pdf │ ├── firmware │ │ ├── hello │ │ │ ├── Makefile │ │ │ ├── hardware.h │ │ │ └── main.c │ │ └── ta_uart │ │ │ ├── Makefile │ │ │ ├── README.txt │ │ │ ├── hardware.h │ │ │ ├── main.c │ │ │ ├── swuart.h │ │ │ ├── swuart.s │ │ │ └── ta_uart.lst │ └── ise │ │ ├── openMSP430_fpga.bit │ │ ├── openMSP430_fpga.ucf │ │ ├── openmsp430.xise │ │ └── rtl │ │ └── verilog │ │ ├── coregen │ │ ├── blk_mem_gen_v6_2_readme.txt │ │ ├── chipscope_icon.asy │ │ ├── chipscope_icon.gise │ │ ├── chipscope_icon.ngc │ │ ├── chipscope_icon.v │ │ ├── chipscope_icon.veo │ │ ├── chipscope_icon.xco │ │ ├── chipscope_icon.xise │ │ ├── chipscope_icon_flist.txt │ │ ├── chipscope_icon_readme.txt │ │ ├── chipscope_icon_xmdf.tcl │ │ ├── chipscope_ila.asy │ │ ├── chipscope_ila.cdc │ │ ├── chipscope_ila.ejp │ │ ├── chipscope_ila.gise │ │ ├── chipscope_ila.ngc │ │ ├── chipscope_ila.v │ │ ├── chipscope_ila.veo │ │ ├── chipscope_ila.xco │ │ ├── chipscope_ila.xise │ │ ├── chipscope_ila_flist.txt │ │ ├── chipscope_ila_readme.txt │ │ ├── chipscope_ila_xmdf.tcl │ │ ├── coregen.cgc │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── ram_8x512.asy │ │ ├── ram_8x512.gise │ │ ├── ram_8x512.ngc │ │ ├── ram_8x512.v │ │ ├── ram_8x512.veo │ │ ├── ram_8x512.xco │ │ ├── ram_8x512.xise │ │ ├── ram_8x512_flist.txt │ │ ├── ram_8x512_xmdf.tcl │ │ ├── rom_8x2k.asy │ │ ├── rom_8x2k.gise │ │ ├── rom_8x2k.ngc │ │ ├── rom_8x2k.v │ │ ├── rom_8x2k.veo │ │ ├── rom_8x2k.xco │ │ ├── rom_8x2k.xise │ │ ├── rom_8x2k_flist.txt │ │ ├── rom_8x2k_xmdf.tcl │ │ └── summary.log │ │ ├── io_mux.v │ │ ├── openMSP430_fpga.v │ │ └── openmsp430 │ │ ├── omsp_alu.v │ │ ├── omsp_clock_module.v │ │ ├── omsp_dbg.v │ │ ├── omsp_dbg_hwbrk.v │ │ ├── omsp_dbg_uart.v │ │ ├── omsp_execution_unit.v │ │ ├── omsp_frontend.v │ │ ├── omsp_mem_backbone.v │ │ ├── omsp_multiplier.v │ │ ├── omsp_register_file.v │ │ ├── omsp_sfr.v │ │ ├── omsp_sync_cell.v │ │ ├── omsp_watchdog.v │ │ ├── openMSP430.v │ │ ├── openMSP430_defines.v │ │ ├── openMSP430_undefines.v │ │ └── periph │ │ ├── omsp_gpio.v │ │ ├── omsp_timerA.v │ │ ├── omsp_timerA_defines.v │ │ ├── omsp_timerA_undefines.v │ │ ├── template_periph_16b.v │ │ └── template_periph_8b.v └── xilinx_diligent_s3board │ ├── bench │ └── verilog │ │ ├── glbl.v │ │ ├── msp_debug.v │ │ ├── registers.v │ │ ├── tb_openMSP430_fpga.v │ │ └── timescale.v │ ├── doc │ ├── board_user_guide.pdf │ ├── msp430f1121a.pdf │ └── xapp462.pdf │ ├── rtl │ └── verilog │ │ ├── coregen │ │ ├── coregen.cgp │ │ ├── coregen.log │ │ ├── ram_8x512_hi.asy │ │ ├── ram_8x512_hi.ngc │ │ ├── ram_8x512_hi.sym │ │ ├── ram_8x512_hi.v │ │ ├── ram_8x512_hi.veo │ │ ├── ram_8x512_hi.xco │ │ ├── ram_8x512_hi_flist.txt │ │ ├── ram_8x512_hi_readme.txt │ │ ├── ram_8x512_hi_xmdf.tcl │ │ ├── ram_8x512_lo.asy │ │ ├── ram_8x512_lo.ngc │ │ ├── ram_8x512_lo.sym │ │ ├── ram_8x512_lo.v │ │ ├── ram_8x512_lo.veo │ │ ├── ram_8x512_lo.xco │ │ ├── ram_8x512_lo_flist.txt │ │ ├── ram_8x512_lo_readme.txt │ │ ├── ram_8x512_lo_xmdf.tcl │ │ ├── rom_8x2k_hi.asy │ │ ├── rom_8x2k_hi.ngc │ │ ├── rom_8x2k_hi.sym │ │ ├── rom_8x2k_hi.v │ │ ├── rom_8x2k_hi.veo │ │ ├── rom_8x2k_hi.xco │ │ ├── rom_8x2k_hi_flist.txt │ │ ├── rom_8x2k_hi_readme.txt │ │ ├── rom_8x2k_hi_xmdf.tcl │ │ ├── rom_8x2k_lo.asy │ │ ├── rom_8x2k_lo.ngc │ │ ├── rom_8x2k_lo.sym │ │ ├── rom_8x2k_lo.v │ │ ├── rom_8x2k_lo.veo │ │ ├── rom_8x2k_lo.xco │ │ ├── rom_8x2k_lo_flist.txt │ │ ├── rom_8x2k_lo_readme.txt │ │ ├── rom_8x2k_lo_xmdf.tcl │ │ ├── xlnx_auto_0.ise │ │ └── xlnx_auto_0_xdb │ │ │ └── tmp │ │ │ ├── ise.lock │ │ │ └── ise │ │ │ └── __OBJSTORE__ │ │ │ └── HierarchicalDesign │ │ │ └── HDProject │ │ │ ├── HDProject │ │ │ └── HDProject_StrTbl │ │ ├── driver_7segment.v │ │ ├── io_mux.v │ │ ├── openMSP430_fpga.v │ │ └── openmsp430 │ │ ├── omsp_alu.v │ │ ├── omsp_clock_module.v │ │ ├── omsp_dbg.v │ │ ├── omsp_dbg_hwbrk.v │ │ ├── omsp_dbg_uart.v │ │ ├── omsp_execution_unit.v │ │ ├── omsp_frontend.v │ │ ├── omsp_mem_backbone.v │ │ ├── omsp_multiplier.v │ │ ├── omsp_register_file.v │ │ ├── omsp_sfr.v │ │ ├── omsp_sync_cell.v │ │ ├── omsp_watchdog.v │ │ ├── openMSP430.v │ │ ├── openMSP430_defines.v │ │ ├── openMSP430_undefines.v │ │ └── periph │ │ ├── omsp_gpio.v │ │ ├── omsp_timerA.v │ │ ├── omsp_timerA_defines.v │ │ ├── omsp_timerA_undefines.v │ │ ├── template_periph_16b.v │ │ └── template_periph_8b.v │ ├── sim │ └── rtl_sim │ │ ├── bin │ │ ├── ihex2mem.tcl │ │ ├── msp430sim │ │ └── rtlsim.sh │ │ ├── run │ │ ├── run │ │ └── run_disassemble │ │ └── src │ │ ├── leds.v │ │ ├── submit.f │ │ └── ta_uart.v │ ├── software │ ├── leds │ │ ├── 7seg.c │ │ ├── 7seg.h │ │ ├── hardware.h │ │ ├── main.c │ │ └── makefile │ └── ta_uart │ │ ├── README.txt │ │ ├── fll.h │ │ ├── fll.s │ │ ├── hardware.h │ │ ├── main.c │ │ ├── makefile │ │ ├── miniterm.py │ │ ├── swuart.h │ │ └── swuart.s │ └── synthesis │ └── xilinx │ ├── create_bitstream.bat │ ├── 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