├── scripts ├── sout_line ├── tload.sh ├── RULER ├── set_sprite.pl ├── texloader.pl ├── serialray.pl └── textureprep.pl ├── ipcore_dir ├── .gitignore ├── div_8_dot_8_nodsp.ncf ├── lcd_spi_clk │ ├── simulation │ │ ├── timing │ │ │ ├── vcs_session.tcl │ │ │ ├── ucli_commands.key │ │ │ ├── sdf_cmd_file │ │ │ ├── simcmds.tcl │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_mti.do │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_ncsim.sh │ │ │ ├── simulate_mti.bat │ │ │ ├── wave.do │ │ │ └── simulate_vcs.sh │ │ └── functional │ │ │ ├── ucli_commands.key │ │ │ ├── simcmds.tcl │ │ │ ├── vcs_session.tcl │ │ │ ├── simulate_mti.sh │ │ │ ├── simulate_isim.sh │ │ │ ├── simulate_mti.do │ │ │ ├── wave.do │ │ │ ├── simulate_mti.bat │ │ │ ├── simulate_isim.bat │ │ │ ├── simulate_ncsim.sh │ │ │ └── simulate_vcs.sh │ ├── implement │ │ ├── xst.prj │ │ ├── xst.scr │ │ ├── planAhead_rdn.sh │ │ ├── planAhead_ise.sh │ │ ├── planAhead_rdn.bat │ │ ├── planAhead_ise.bat │ │ ├── planAhead_ise.tcl │ │ ├── planAhead_rdn.tcl │ │ ├── implement.sh │ │ └── implement.bat │ ├── doc │ │ └── pg065_clk_wiz.pdf │ └── example_design │ │ ├── lcd_spi_clk_exdes.ucf │ │ └── lcd_spi_clk_exdes.xdc ├── div_8_dot_8_nodsp.ngc ├── div_8_dot_8_nodsp │ └── doc │ │ └── ds819_div_gen.pdf ├── coregen.cgp ├── lcd_spi_clk.asy ├── div_8_dot_8_nodsp_flist.txt ├── lcd_spi_clk.sym ├── div_8_dot_8_nodsp.asy ├── div_8_dot_8_nodsp.gise ├── div_8_dot_8_nodsp.xco ├── lcd_spi_clk_flist.txt ├── lcd_spi_clk.gise ├── lcd_spi_clk.ucf ├── lcd_spi_clk.ncf ├── lcd_spi_clk.xdc ├── div_8_dot_8_nodsp_xmdf.tcl └── lcd_spi_clk.veo ├── img ├── screen.png ├── screen_fb.png ├── soundwave.png ├── impressionist.png └── map_point_glitch.png ├── syn └── .gitignore ├── texture └── LAB │ ├── guns │ ├── gun2.png │ ├── gun3.png │ ├── gun4.png │ ├── gun6.png │ ├── gun0a.png │ ├── gun0b.png │ ├── gun0c.png │ ├── gun0d.png │ ├── gun0e.png │ ├── gun1a.png │ ├── gun1b.png │ ├── gun1c.png │ ├── gun2b.png │ ├── gun2c.png │ ├── gun3a.png │ ├── gun3b.png │ ├── gun3c.png │ ├── gun3d.png │ ├── gun4b.png │ ├── gun4c.png │ ├── gun5a.png │ ├── gun5b.png │ ├── gun5c.png │ ├── gun6b.png │ └── gun6c.png │ ├── door │ ├── door0.png │ ├── door_blue.png │ ├── door_red.png │ ├── door_surp.png │ └── door_green.png │ ├── sprites │ ├── fat0.png │ ├── fat1.png │ ├── fly0.png │ ├── fly1.png │ ├── gib0.png │ ├── gib1.png │ ├── gib2.png │ ├── gib3.png │ ├── brain.png │ ├── cobra0.png │ ├── cobra1.png │ ├── cobra2.png │ ├── column.png │ ├── crate.png │ ├── d_bin.png │ ├── d_lamp.png │ ├── d_slab.png │ ├── d_tree.png │ ├── frog0.png │ ├── frog1.png │ ├── frog2.png │ ├── frog3.png │ ├── frog4.png │ ├── i_clip.png │ ├── i_fuel.png │ ├── i_nuke.png │ ├── robot0.png │ ├── robot1.png │ ├── robot2.png │ ├── scrap0.png │ ├── shard.png │ ├── wasp0.png │ ├── wasp1.png │ ├── wasp2.png │ ├── wasp3.png │ ├── wasp5.png │ ├── acidspit.png │ ├── bloodspr.png │ ├── ceil_slab.png │ ├── cobraatt0.png │ ├── cobraatt1.png │ ├── cobraatt2.png │ ├── cobrahit0.png │ ├── cobrahit1.png │ ├── cobrahit2.png │ ├── cobrahit3.png │ ├── cobrahit4.png │ ├── cricket.png │ ├── d_filebin.png │ ├── d_grass.png │ ├── d_table.png │ ├── fatatt0.png │ ├── fatatt1.png │ ├── fathit0.png │ ├── fathit1.png │ ├── fathit2.png │ ├── fathit3.png │ ├── fathit4.png │ ├── fireball0.png │ ├── grenade.png │ ├── i_ammobox.png │ ├── i_armor.png │ ├── i_bonus.png │ ├── i_grenade.png │ ├── i_health.png │ ├── i_keyblue.png │ ├── i_keyred.png │ ├── i_nuker.png │ ├── i_pistol.png │ ├── i_rifle.png │ ├── i_spawn.png │ ├── i_spawner.png │ ├── insect0.png │ ├── insect1.png │ ├── insect2.png │ ├── mutant0.png │ ├── mutant1.png │ ├── mutant2.png │ ├── mutatt0.png │ ├── mutatt1.png │ ├── muthit0.png │ ├── muthit1.png │ ├── muthit2.png │ ├── muthit3.png │ ├── plasmball.png │ ├── robotatt0.png │ ├── robotatt1.png │ ├── robothit0.png │ ├── ceil_grass.png │ ├── i_fireball.png │ ├── i_keygreen.png │ ├── insectatt0.png │ ├── insectatt1.png │ ├── insecthit0.png │ ├── insecthit1.png │ ├── insecthit2.png │ └── insecthit3.png │ ├── wall │ ├── tile000.png │ ├── tile050.png │ ├── tile051.png │ ├── tile065.png │ ├── tile066.png │ ├── tile067.png │ ├── tile068.png │ ├── tile069.png │ ├── tile070.png │ ├── tile071.png │ ├── tile072.png │ ├── tile073.png │ ├── tile074.png │ ├── tile075.png │ ├── tile076.png │ ├── tile077.png │ ├── tile078.png │ ├── tile079.png │ ├── tile080.png │ ├── tile081.png │ ├── tile082.png │ ├── tile083.png │ ├── tile084.png │ ├── tile085.png │ ├── tile086.png │ ├── tile087.png │ ├── tile088.png │ ├── tile089.png │ ├── tile090.png │ ├── tile091.png │ ├── tile092.png │ ├── tile093.png │ ├── tile094.png │ ├── tile095.png │ ├── tile096.png │ ├── tile097.png │ ├── tile098.png │ ├── tile099.png │ ├── tile100.png │ ├── tile101.png │ ├── tile102.png │ ├── tile103.png │ ├── tile104.png │ ├── tile105.png │ ├── tile106.png │ ├── tile107.png │ ├── tile108.png │ ├── tile109.png │ ├── tile110.png │ ├── tile111.png │ ├── tile112.png │ ├── tile113.png │ ├── tile115.png │ ├── tile116.png │ ├── tile117.png │ ├── tile118.png │ ├── tile119.png │ ├── tile120.png │ ├── tile121.png │ ├── tile122.png │ ├── tile123.png │ ├── tile124.png │ ├── tile125.png │ ├── tile126.png │ ├── tile127.png │ ├── tile128.png │ ├── tile129.png │ ├── tile130.png │ ├── tile131.png │ ├── tile132.png │ └── tile133.png │ └── readme.txt ├── src ├── map_rom.v ├── map.pl ├── iheight_rom.v ├── idist_rom.v ├── floordist_rom.v ├── height_rom.v ├── angle_rom.v ├── camerax_rom.v ├── task_crossdomain.v ├── cclk_detector.v ├── line_writer_tb.v ├── map2 ├── map ├── map3 ├── mojo.ucf ├── cast_ray_tb.v ├── spi_slave.v ├── sprite_tb.v ├── serial_rx.v ├── lcd_driver.v ├── spi.v ├── mmap_tb.v ├── simple_dual_ram.v ├── serial_tx.v ├── floordist.rom └── sprite_scanline.v ├── LICENSE.txt └── .project /scripts/sout_line: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ipcore_dir/.gitignore: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp.ncf: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | -------------------------------------------------------------------------------- /img/screen.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/img/screen.png -------------------------------------------------------------------------------- /img/screen_fb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/img/screen_fb.png -------------------------------------------------------------------------------- /img/soundwave.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/img/soundwave.png -------------------------------------------------------------------------------- /syn/.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore everything in this directory 2 | * 3 | # Except this file 4 | !.gitignore -------------------------------------------------------------------------------- /img/impressionist.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/img/impressionist.png -------------------------------------------------------------------------------- /img/map_point_glitch.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/img/map_point_glitch.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun2.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun3.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun4.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun6.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun6.png -------------------------------------------------------------------------------- /texture/LAB/door/door0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/door/door0.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun0a.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun0a.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun0b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun0b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun0c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun0c.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun0d.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun0d.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun0e.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun0e.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun1a.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun1a.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun1b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun1b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun1c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun1c.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun2b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun2b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun2c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun2c.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun3a.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun3a.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun3b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun3b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun3c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun3c.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun3d.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun3d.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun4b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun4b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun4c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun4c.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun5a.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun5a.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun5b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun5b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun5c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun5c.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun6b.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun6b.png -------------------------------------------------------------------------------- /texture/LAB/guns/gun6c.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/guns/gun6c.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fat0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fat0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fat1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fat1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fly0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fly0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fly1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fly1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/gib0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/gib0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/gib1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/gib1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/gib2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/gib2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/gib3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/gib3.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile000.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile000.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile050.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile050.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile051.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile051.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile065.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile065.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile066.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile066.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile067.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile067.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile068.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile068.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile069.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile069.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile070.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile070.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile071.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile071.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile072.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile072.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile073.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile073.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile074.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile074.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile075.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile075.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile076.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile076.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile077.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile077.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile078.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile078.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile079.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile079.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile080.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile080.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile081.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile081.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile082.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile082.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile083.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile083.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile084.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile084.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile085.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile085.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile086.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile086.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile087.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile087.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile088.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile088.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile089.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile089.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile090.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile090.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile091.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile091.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile092.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile092.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile093.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile093.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile094.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile094.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile095.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile095.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile096.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile096.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile097.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile097.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile098.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile098.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile099.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile099.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile100.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile100.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile101.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile101.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile102.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile102.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile103.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile103.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile104.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile104.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile105.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile105.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile106.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile106.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile107.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile107.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile108.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile108.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile109.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile109.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile110.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile110.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile111.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile111.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile112.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile112.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile113.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile113.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile115.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile115.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile116.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile116.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile117.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile117.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile118.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile118.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile119.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile119.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile120.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile120.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile121.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile121.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile122.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile122.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile123.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile123.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile124.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile124.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile125.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile125.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile126.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile126.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile127.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile127.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile128.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile128.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile129.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile129.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile130.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile130.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile131.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile131.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile132.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile132.png -------------------------------------------------------------------------------- /texture/LAB/wall/tile133.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/wall/tile133.png -------------------------------------------------------------------------------- /texture/LAB/door/door_blue.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/door/door_blue.png -------------------------------------------------------------------------------- /texture/LAB/door/door_red.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/door/door_red.png -------------------------------------------------------------------------------- /texture/LAB/door/door_surp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/door/door_surp.png -------------------------------------------------------------------------------- /texture/LAB/sprites/brain.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/brain.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobra0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobra0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobra1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobra1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobra2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobra2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/column.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/column.png -------------------------------------------------------------------------------- /texture/LAB/sprites/crate.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/crate.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_bin.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_bin.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_lamp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_lamp.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_slab.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_slab.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_tree.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_tree.png -------------------------------------------------------------------------------- /texture/LAB/sprites/frog0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/frog0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/frog1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/frog1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/frog2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/frog2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/frog3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/frog3.png -------------------------------------------------------------------------------- /texture/LAB/sprites/frog4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/frog4.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_clip.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_clip.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_fuel.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_fuel.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_nuke.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_nuke.png -------------------------------------------------------------------------------- /texture/LAB/sprites/robot0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/robot0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/robot1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/robot1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/robot2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/robot2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/scrap0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/scrap0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/shard.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/shard.png -------------------------------------------------------------------------------- /texture/LAB/sprites/wasp0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/wasp0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/wasp1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/wasp1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/wasp2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/wasp2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/wasp3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/wasp3.png -------------------------------------------------------------------------------- /texture/LAB/sprites/wasp5.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/wasp5.png -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp.ngc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/ipcore_dir/div_8_dot_8_nodsp.ngc -------------------------------------------------------------------------------- /texture/LAB/door/door_green.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/door/door_green.png -------------------------------------------------------------------------------- /texture/LAB/sprites/acidspit.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/acidspit.png -------------------------------------------------------------------------------- /texture/LAB/sprites/bloodspr.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/bloodspr.png -------------------------------------------------------------------------------- /texture/LAB/sprites/ceil_slab.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/ceil_slab.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobraatt0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobraatt0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobraatt1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobraatt1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobraatt2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobraatt2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobrahit0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobrahit0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobrahit1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobrahit1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobrahit2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobrahit2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobrahit3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobrahit3.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cobrahit4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cobrahit4.png -------------------------------------------------------------------------------- /texture/LAB/sprites/cricket.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/cricket.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_filebin.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_filebin.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_grass.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_grass.png -------------------------------------------------------------------------------- /texture/LAB/sprites/d_table.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/d_table.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fatatt0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fatatt0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fatatt1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fatatt1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fathit0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fathit0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fathit1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fathit1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fathit2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fathit2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fathit3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fathit3.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fathit4.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fathit4.png -------------------------------------------------------------------------------- /texture/LAB/sprites/fireball0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/fireball0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/grenade.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/grenade.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_ammobox.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_ammobox.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_armor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_armor.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_bonus.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_bonus.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_grenade.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_grenade.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_health.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_health.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_keyblue.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_keyblue.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_keyred.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_keyred.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_nuker.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_nuker.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_pistol.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_pistol.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_rifle.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_rifle.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_spawn.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_spawn.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_spawner.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_spawner.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insect0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insect0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insect1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insect1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insect2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insect2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/mutant0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/mutant0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/mutant1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/mutant1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/mutant2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/mutant2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/mutatt0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/mutatt0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/mutatt1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/mutatt1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/muthit0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/muthit0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/muthit1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/muthit1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/muthit2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/muthit2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/muthit3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/muthit3.png -------------------------------------------------------------------------------- /texture/LAB/sprites/plasmball.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/plasmball.png -------------------------------------------------------------------------------- /texture/LAB/sprites/robotatt0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/robotatt0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/robotatt1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/robotatt1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/robothit0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/robothit0.png -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/xst.prj: -------------------------------------------------------------------------------- 1 | verilog work ../../lcd_spi_clk.v 2 | verilog work ../example_design/lcd_spi_clk_exdes.v 3 | -------------------------------------------------------------------------------- /texture/LAB/sprites/ceil_grass.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/ceil_grass.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_fireball.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_fireball.png -------------------------------------------------------------------------------- /texture/LAB/sprites/i_keygreen.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/i_keygreen.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insectatt0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insectatt0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insectatt1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insectatt1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insecthit0.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insecthit0.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insecthit1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insecthit1.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insecthit2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insecthit2.png -------------------------------------------------------------------------------- /texture/LAB/sprites/insecthit3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/texture/LAB/sprites/insecthit3.png -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/ucli_commands.key: -------------------------------------------------------------------------------- 1 | 2 | call {$vcdpluson} 3 | run 50000ns 4 | call {$vcdplusclose} 5 | quit 6 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/doc/pg065_clk_wiz.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/ipcore_dir/lcd_spi_clk/doc/pg065_clk_wiz.pdf -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/sdf_cmd_file: -------------------------------------------------------------------------------- 1 | COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", 2 | SCOPE = lcd_spi_clk_tb.dut; 3 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp/doc/ds819_div_gen.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dormando/verilog-raycaster/HEAD/ipcore_dir/div_8_dot_8_nodsp/doc/ds819_div_gen.pdf -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/ucli_commands.key: -------------------------------------------------------------------------------- 1 | call {$vcdpluson} 2 | call {$vcdplusmemon(lcd_spi_clk_tb.dut.counter)} 3 | run 4 | call {$vcdplusclose} 5 | quit 6 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /lcd_spi_clk_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simcmds.tcl: -------------------------------------------------------------------------------- 1 | # file: simcmds.tcl 2 | 3 | # create the simulation script 4 | vcd dumpfile isim.vcd 5 | vcd dumpvars -m /lcd_spi_clk_tb -l 0 6 | wave add / 7 | run 50000ns 8 | quit 9 | 10 | -------------------------------------------------------------------------------- /scripts/tload.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | ./texloader.pl tout/tile110.png.flat tout/tile082.png.flat tout/tile084.png.flat tout/tile085.png.flat tout/tile093.png.flat tout/tile096.png.flat tout/tile097.png.flat tout/tile106.png.flat sout/brain.png.flat 3 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/xst.scr: -------------------------------------------------------------------------------- 1 | run 2 | -ifmt MIXED 3 | -top lcd_spi_clk_exdes 4 | -p xc6slx9-tqg144-2 5 | -ifn xst.prj 6 | -ofn lcd_spi_clk_exdes 7 | -keep_hierarchy soft 8 | -equivalent_register_removal no 9 | -max_fanout 65535 10 | -------------------------------------------------------------------------------- /ipcore_dir/coregen.cgp: -------------------------------------------------------------------------------- 1 | SET busformat = BusFormatAngleBracketNotRipped 2 | SET designentry = Verilog 3 | SET device = xc6slx9 4 | SET devicefamily = spartan6 5 | SET flowvendor = Other 6 | SET package = tqg144 7 | SET speedgrade = -2 8 | SET verilogsim = true 9 | SET vhdlsim = false 10 | -------------------------------------------------------------------------------- /scripts/RULER: -------------------------------------------------------------------------------- 1 | because shifting fixed point math variables is hard on the brain. 2 | 3 | Q16 . 16 4 | 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 5 | REAL: 6 | 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16.15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 | 8 | -------------------------------------------------------------------------------- /src/map_rom.v: -------------------------------------------------------------------------------- 1 | module map_rom ( 2 | input [7:0] x, 3 | input [7:0] y, 4 | output reg [3:0] point 5 | ); 6 | 7 | reg [3:0] map [23:0][23:0]; 8 | 9 | initial begin 10 | `include "map.rom" 11 | end 12 | 13 | always @(*) begin 14 | if (x < 24 && y < 24) 15 | point = map[x][y]; 16 | else 17 | point = 4'd1; 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /texture/LAB/readme.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | all textures from my game LAB 4 | 5 | in case you never heard of it it's a little Wolf3D clone made in Flash AS3 6 | ( and you can play/download it for free: https://mutantleg.itch.io/lab ) 7 | 8 | all these gfx is hereby public domain (CC0) 9 | (credit is not required but much appreciated indeed) 10 | 11 | game and graphics by Mutantleg (me) (2015) 12 | 13 | 14 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 lcd_spi_clk 4 | RECTANGLE Normal 32 32 576 1088 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName clk_in1 8 | PINATTR Polarity IN 9 | LINE Normal 608 80 576 80 10 | PIN 608 80 RIGHT 36 11 | PINATTR PinName clk_out1 12 | PINATTR Polarity OUT 13 | LINE Normal 608 176 576 176 14 | PIN 608 176 RIGHT 36 15 | PINATTR PinName clk_out2 16 | PINATTR Polarity OUT 17 | 18 | -------------------------------------------------------------------------------- /src/map.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | 3 | use warnings; 4 | use strict; 5 | 6 | my $mfile = $ARGV[0]; 7 | 8 | open(my $fh, "< $mfile") or die "boop: $!"; 9 | my $x = 0; 10 | while (my $l = <$fh>) { 11 | chomp $l; 12 | my $y = 0; 13 | $l =~ s/^\s+//; 14 | $l =~ s/,$//; 15 | $l =~ s/[{}]//g; 16 | for my $col (split(/,/, $l)) { 17 | print " map[$x][$y] = 4'd$col;\n"; 18 | $y++; 19 | } 20 | $x++; 21 | } 22 | close($fh); 23 | -------------------------------------------------------------------------------- /src/iheight_rom.v: -------------------------------------------------------------------------------- 1 | module iheight_rom ( 2 | input clk, 3 | input [8:0] addr, 4 | output [15:0] iheight // Q8.8 texture / height 5 | ); 6 | 7 | reg [15:0] iheights [1023:0]; 8 | 9 | reg [15:0] iheight_d, iheight_q; 10 | 11 | assign iheight = iheight_q; 12 | 13 | initial begin 14 | `include "iheight.rom" 15 | end 16 | 17 | always @(*) begin 18 | iheight_d = iheights[addr]; 19 | end 20 | 21 | always @(posedge clk) begin 22 | iheight_q <= iheight_d; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | demo_tb/tb_div_8_dot_8_nodsp.vhd 4 | div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt 5 | div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html 6 | div_8_dot_8_nodsp/doc/ds819_div_gen.pdf 7 | div_8_dot_8_nodsp.asy 8 | div_8_dot_8_nodsp.gise 9 | div_8_dot_8_nodsp.ngc 10 | div_8_dot_8_nodsp.v 11 | div_8_dot_8_nodsp.veo 12 | div_8_dot_8_nodsp.xco 13 | div_8_dot_8_nodsp.xise 14 | div_8_dot_8_nodsp_flist.txt 15 | div_8_dot_8_nodsp_xmdf.tcl 16 | -------------------------------------------------------------------------------- /src/idist_rom.v: -------------------------------------------------------------------------------- 1 | module idist_rom ( 2 | input clk, 3 | input [9:0] addr, 4 | output [15:0] idist // Q8.8 inverse distance 5 | ); 6 | 7 | reg [15:0] idists [1023:0]; 8 | 9 | reg [15:0] idist_d, idist_q; 10 | 11 | assign idist = idist_q; 12 | 13 | initial begin 14 | `include "idist.rom" 15 | end 16 | 17 | always @(*) begin 18 | if (addr < 10'd1023) 19 | idist_d = idists[addr]; 20 | else 21 | idist_d = 16'd0; 22 | end 23 | 24 | always @(posedge clk) begin 25 | idist_q <= idist_d; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /src/floordist_rom.v: -------------------------------------------------------------------------------- 1 | module floordist_rom ( 2 | input clk, 3 | input [8:0] addr, 4 | output [15:0] floordist // Q8.8 5 | ); 6 | 7 | reg [15:0] floor_dist [119:0]; 8 | 9 | reg [15:0] fd_d, fd_q; 10 | 11 | assign floordist = fd_q; 12 | 13 | initial begin 14 | `include "floordist.rom" 15 | end 16 | 17 | always @(*) begin 18 | if (addr < 8'd120) 19 | fd_d = floor_dist[8'd119 - addr]; 20 | else 21 | fd_d = floor_dist[addr - 8'd119]; 22 | end 23 | 24 | always @(posedge clk) begin 25 | fd_q <= fd_d; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /src/height_rom.v: -------------------------------------------------------------------------------- 1 | module height_rom ( 2 | input clk, 3 | input [9:0] addr, 4 | output [39:0] height // 8bit height, Q8.8 texture scale, Q8.8 inverse distance 5 | ); 6 | 7 | reg [39:0] heights [1023:0]; 8 | 9 | reg [39:0] height_d, height_q; 10 | 11 | assign height = height_q; 12 | 13 | initial begin 14 | `include "height.rom" 15 | end 16 | 17 | always @(*) begin 18 | if (addr < 16'd1023) 19 | height_d = heights[addr]; 20 | else 21 | height_d = 40'd0; 22 | end 23 | 24 | always @(posedge clk) begin 25 | height_q <= height_d; 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /src/angle_rom.v: -------------------------------------------------------------------------------- 1 | // Primary "turn" angles. Later adjusted by cameraX multiplier before turning 2 | // into rays. 3 | module angle_rom ( 4 | input clk, 5 | input [6:0] addr, 6 | output [79:0] angle // dirX, dirY, planeX, planeY Q8.8, invDet Q8.8 7 | ); 8 | 9 | reg [79:0] angles [125:0]; 10 | 11 | reg [79:0] a_d, a_q; 12 | 13 | assign angle = a_q; 14 | 15 | initial begin 16 | `include "angle.rom" 17 | end 18 | 19 | always @(*) begin 20 | if (addr < 7'd126) 21 | a_d = angles[addr]; 22 | else 23 | a_d = 80'd0; 24 | end 25 | 26 | always @(posedge clk) begin 27 | a_q <= a_d; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /src/camerax_rom.v: -------------------------------------------------------------------------------- 1 | // not using signed values here since I had some bugs. 2 | // users of this data need to treat it as signed. 3 | module camerax_rom ( 4 | input clk, 5 | input [8:0] addr, 6 | output [15:0] camerax // Q8.8 7 | ); 8 | 9 | reg [15:0] camerax_pos [319:0]; 10 | 11 | reg [15:0] cx_d, cx_q; 12 | 13 | assign camerax = cx_q; 14 | 15 | initial begin 16 | `include "camerax.rom" 17 | end 18 | 19 | always @(*) begin 20 | if (addr < 9'd320) 21 | cx_d = camerax_pos[addr]; 22 | else 23 | cx_d = 16'd0; 24 | end 25 | 26 | always @(posedge clk) begin 27 | cx_q <= cx_d; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /scripts/set_sprite.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | # sets a sprite position. 3 | 4 | use warnings; 5 | use strict; 6 | use Device::SerialPort; 7 | use Data::Dumper qw/Dumper/; 8 | 9 | $|++; 10 | my $port = Device::SerialPort->new("/dev/ttyACM0"); 11 | 12 | #$port->baudrate(9600); 13 | #$port->baudrate(115200); 14 | $port->baudrate(256000); 15 | $port->databits(8); 16 | $port->parity("none"); 17 | $port->stopbits(1); 18 | # timeout stuff 19 | $port->read_char_time(0); 20 | $port->read_const_time(1000); 21 | 22 | my $map_x = $ARGV[0] or die "moo"; 23 | my $map_y = $ARGV[1] or die "boo"; 24 | 25 | my $cmd = 0b10000110; 26 | my $map_pos = pack('ss', int($map_x * 2**8), int($map_y * 2**8)); 27 | # FIXME: hard coded texture ID + sprite id (also pick a position :P) 28 | my $packed = pack('CScccc', $cmd, 0, 0, 8, 8, 0); 29 | $port->write($packed . $map_pos); 30 | 31 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/vcs_session.tcl: -------------------------------------------------------------------------------- 1 | gui_open_window Wave 2 | gui_sg_create lcd_spi_clk_group 3 | gui_list_add_group -id Wave.1 {lcd_spi_clk_group} 4 | gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.test_phase} 5 | gui_set_radix -radix {ascii} -signals {lcd_spi_clk_tb.test_phase} 6 | gui_sg_addsignal -group lcd_spi_clk_group {{Input_clocks}} -divider 7 | gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.CLK_IN1} 8 | gui_sg_addsignal -group lcd_spi_clk_group {{Output_clocks}} -divider 9 | gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.dut.clk} 10 | gui_list_expand -id Wave.1 lcd_spi_clk_tb.dut.clk 11 | gui_sg_addsignal -group lcd_spi_clk_group {{Counters}} -divider 12 | gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.COUNT} 13 | gui_sg_addsignal -group lcd_spi_clk_group {lcd_spi_clk_tb.dut.counter} 14 | gui_list_expand -id Wave.1 lcd_spi_clk_tb.dut.counter 15 | gui_zoom -window Wave.1 -full 16 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.sym: -------------------------------------------------------------------------------- 1 | 2 | 3 | BLOCK 4 | 2018-12-10T8:32:51 5 | 6 | 7 | 8 | 9 | lcd_spi_clk 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /LICENSE.txt: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2018 Dormando 4 | Copyright (c) 2015 Embedded Micro 5 | 6 | Permission is hereby granted, free of charge, to any person obtaining a copy 7 | of this software and associated documentation files (the "Software"), to deal 8 | in the Software without restriction, including without limitation the rights 9 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | copies of the Software, and to permit persons to whom the Software is 11 | furnished to do so, subject to the following conditions: 12 | 13 | The above copyright notice and this permission notice shall be included in 14 | all copies or substantial portions of the Software. 15 | 16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | THE SOFTWARE. 23 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | TEXT 32 32 LEFT 4 div_8_dot_8_nodsp 4 | RECTANGLE Normal 32 32 608 576 5 | LINE Normal 0 80 32 80 6 | PIN 0 80 LEFT 36 7 | PINATTR PinName s_axis_dividend_tvalid 8 | PINATTR Polarity IN 9 | LINE Normal 0 112 32 112 10 | PIN 0 112 LEFT 36 11 | PINATTR PinName s_axis_dividend_tready 12 | PINATTR Polarity OUT 13 | LINE Wide 0 144 32 144 14 | PIN 0 144 LEFT 36 15 | PINATTR PinName s_axis_dividend_tdata[23:0] 16 | PINATTR Polarity IN 17 | LINE Normal 0 272 32 272 18 | PIN 0 272 LEFT 36 19 | PINATTR PinName s_axis_divisor_tvalid 20 | PINATTR Polarity IN 21 | LINE Normal 0 304 32 304 22 | PIN 0 304 LEFT 36 23 | PINATTR PinName s_axis_divisor_tready 24 | PINATTR Polarity OUT 25 | LINE Wide 0 336 32 336 26 | PIN 0 336 LEFT 36 27 | PINATTR PinName s_axis_divisor_tdata[15:0] 28 | PINATTR Polarity IN 29 | LINE Normal 0 464 32 464 30 | PIN 0 464 LEFT 36 31 | PINATTR PinName aclk 32 | PINATTR Polarity IN 33 | LINE Normal 640 80 608 80 34 | PIN 640 80 RIGHT 36 35 | PINATTR PinName m_axis_dout_tvalid 36 | PINATTR Polarity OUT 37 | LINE Wide 640 144 608 144 38 | PIN 640 144 RIGHT 36 39 | PINATTR PinName m_axis_dout_tdata[39:0] 40 | PINATTR Polarity OUT 41 | 42 | -------------------------------------------------------------------------------- /src/task_crossdomain.v: -------------------------------------------------------------------------------- 1 | // taken from: https://www.fpga4fun.com/CrossClockDomain3.html 2 | // copyrighted fpga4fun.com & KNJN LLC. 3 | 4 | module task_crossdomain( 5 | input clka, 6 | input taskstart_clka, 7 | output taskbusy_clka, taskdone_clka, 8 | 9 | input clkb, 10 | output taskstart_clkb, taskbusy_clkb, 11 | input taskdone_clkb 12 | ); 13 | 14 | reg FlagToggle_clkA = 0; 15 | reg FlagToggle_clkB = 0; 16 | reg Busyhold_clkB = 0; 17 | reg [2:0] SyncA_clkB = 0; 18 | reg [2:0] SyncB_clkA = 0; 19 | 20 | always @(posedge clka) FlagToggle_clkA <= FlagToggle_clkA ^ (taskstart_clka & ~taskbusy_clka); 21 | 22 | always @(posedge clkb) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA}; 23 | assign taskstart_clkb = (SyncA_clkB[2] ^ SyncA_clkB[1]); 24 | assign taskbusy_clkb = taskstart_clkb | Busyhold_clkB; 25 | always @(posedge clkb) Busyhold_clkB <= ~taskdone_clkb & taskbusy_clkb; 26 | always @(posedge clkb) if(taskbusy_clkb & taskdone_clkb) FlagToggle_clkB <= FlagToggle_clkA; 27 | 28 | always @(posedge clka) SyncB_clkA <= {SyncB_clkA[1:0], FlagToggle_clkB}; 29 | assign taskbusy_clka = FlagToggle_clkA ^ SyncB_clkA[2]; 30 | assign taskdone_clka = SyncB_clkA[2] ^ SyncB_clkA[1]; 31 | endmodule 32 | -------------------------------------------------------------------------------- /src/cclk_detector.v: -------------------------------------------------------------------------------- 1 | // from embedded micro base project 2 | 3 | module cclk_detector #( 4 | parameter CLK_RATE = 50000000 5 | )( 6 | input clk, 7 | input rst, 8 | input cclk, 9 | output ready 10 | ); 11 | 12 | parameter CTR_SIZE = $clog2(CLK_RATE/50000); 13 | 14 | reg [CTR_SIZE-1:0] ctr_d, ctr_q; 15 | reg ready_d, ready_q; 16 | 17 | assign ready = ready_q; 18 | 19 | // ready should only go high once cclk has been high for a while 20 | // if cclk ever falls, ready should go low again 21 | always @(ctr_q or cclk) begin 22 | ready_d = 1'b0; 23 | if (cclk == 1'b0) begin // when cclk is 0 reset the counter 24 | ctr_d = 1'b0; 25 | end else if (ctr_q != {CTR_SIZE{1'b1}}) begin 26 | ctr_d = ctr_q + 1'b1; // counter isn't max value yet 27 | end else begin 28 | ctr_d = ctr_q; 29 | ready_d = 1'b1; // counter reached the max, we are ready 30 | end 31 | 32 | end 33 | 34 | always @(posedge clk) begin 35 | if (rst) begin 36 | ctr_q <= 1'b0; 37 | ready_q <= 1'b0; 38 | end else begin 39 | ctr_q <= ctr_d; 40 | ready_q <= ready_d; 41 | end 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /src/line_writer_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module line_writer_tb( 4 | ); 5 | 6 | reg clk; 7 | reg rst; 8 | 9 | reg start; 10 | reg [7:0] pixel; 11 | reg [23:0] height; 12 | reg [6:0] tex_x; 13 | reg [$clog2(240)-1:0] ram_raddr; 14 | wire [7:0] ram_read_data; 15 | 16 | reg [12:0] tram_waddr; 17 | reg [7:0] tram_write_data; 18 | reg tram_write_en; 19 | 20 | line_writer DUT ( 21 | .clk(clk), 22 | .rst(rst), 23 | .start(start), 24 | .pixel(pixel), 25 | .height(height), 26 | .tex_x(tex_x), 27 | .rdy(rdy), 28 | .ram_raddr(ram_raddr), 29 | .ram_read_data(ram_read_data) 30 | ); 31 | 32 | initial begin 33 | clk = 0; 34 | forever #10 clk = ~clk; 35 | end 36 | 37 | initial begin 38 | rst = 1'b1; 39 | repeat(6) @(posedge clk); 40 | rst = 1'b0; 41 | repeat(2) @(posedge clk); 42 | start = 1'b1; 43 | pixel = 8'd1; 44 | height = 24'hee_00_22; 45 | tex_x = 7'd15; 46 | @(posedge clk); 47 | start = 1'b0; 48 | ram_raddr = 8'd100; 49 | repeat(400) @(posedge clk); 50 | #5000 51 | $finish; 52 | end 53 | 54 | initial begin 55 | #500000000 56 | $finish; 57 | end 58 | endmodule 59 | -------------------------------------------------------------------------------- /src/map2: -------------------------------------------------------------------------------- 1 | {8,8,8,8,8,8,8,8,8,8,8,4,4,6,4,4,6,4,6,4,4,4,6,4}, 2 | {8,0,0,0,0,0,0,0,0,0,8,4,0,0,0,0,0,0,0,0,0,0,0,4}, 3 | {8,0,3,3,0,0,0,0,0,8,8,4,0,0,0,0,0,0,0,0,0,0,0,6}, 4 | {8,0,0,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6}, 5 | {8,0,3,3,0,0,0,0,0,8,8,4,0,0,0,0,0,0,0,0,0,0,0,4}, 6 | {8,0,0,0,0,0,0,0,0,0,8,4,0,0,0,0,0,6,6,6,0,6,4,6}, 7 | {8,8,8,8,0,8,8,8,8,8,8,4,4,4,4,4,4,6,0,0,0,0,0,6}, 8 | {7,7,7,7,0,7,7,7,7,0,8,0,8,0,8,0,8,4,0,4,0,6,0,6}, 9 | {7,7,0,0,0,0,0,0,7,8,0,8,0,8,0,8,8,6,0,0,0,0,0,6}, 10 | {7,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8,6,0,0,0,0,0,4}, 11 | {7,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8,6,0,6,0,6,0,6}, 12 | {7,7,0,0,0,0,0,0,7,8,0,8,0,8,0,8,8,6,4,6,0,6,6,6}, 13 | {7,7,7,7,0,7,7,7,7,8,8,4,0,6,8,4,8,3,3,3,0,3,3,3}, 14 | {2,2,2,2,0,2,2,2,2,4,6,4,0,0,6,0,6,3,0,0,0,0,0,3}, 15 | {2,2,0,0,0,0,0,2,2,4,0,0,0,0,0,0,4,3,0,0,0,0,0,3}, 16 | {2,0,0,0,0,0,0,0,2,4,0,0,0,0,0,0,4,3,0,0,0,0,0,3}, 17 | {1,0,0,0,0,0,0,0,1,4,4,4,4,4,6,0,6,3,3,0,0,0,3,3}, 18 | {2,0,0,0,0,0,0,0,2,2,2,1,2,2,2,6,6,0,0,5,0,5,0,5}, 19 | {2,2,0,0,0,0,0,2,2,2,0,0,0,2,2,0,5,0,5,0,0,0,5,5}, 20 | {2,0,0,0,0,0,0,0,2,0,0,0,0,0,2,5,0,5,0,5,0,5,0,5}, 21 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5}, 22 | {2,0,0,0,0,0,0,0,2,0,0,0,0,0,2,5,0,5,0,5,0,5,0,5}, 23 | {2,2,0,0,0,0,0,2,2,2,0,0,0,2,2,0,5,0,5,0,0,0,5,5}, 24 | {2,2,2,2,1,2,2,2,2,2,2,1,2,2,2,5,5,5,5,5,5,5,5,5} 25 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | -------------------------------------------------------------------------------- /src/map: -------------------------------------------------------------------------------- 1 | {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 2 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 3 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 4 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 5 | {1,0,0,0,0,0,2,2,2,2,2,0,0,0,0,6,0,7,0,8,0,0,0,1}, 6 | {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, 7 | {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,4,0,0,0,5,0,0,0,1}, 8 | {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, 9 | {1,0,0,0,0,0,2,2,0,2,2,0,0,0,0,1,0,2,0,3,0,0,0,1}, 10 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 11 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 12 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 13 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 14 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 15 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 16 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 17 | {1,4,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 18 | {1,4,0,4,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 19 | {1,4,0,0,0,0,5,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 20 | {1,4,0,4,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 21 | {1,4,0,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 22 | {1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 23 | {1,4,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 24 | {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 25 | 26 | -------------------------------------------------------------------------------- /src/map3: -------------------------------------------------------------------------------- 1 | {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 2 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 3 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 4 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 5 | {1,0,0,0,0,0,2,2,2,2,2,0,0,0,0,6,0,7,0,8,0,0,0,1}, 6 | {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, 7 | {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,4,0,0,0,5,0,0,0,1}, 8 | {1,0,0,0,0,0,2,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,1}, 9 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,2,0,3,0,0,0,1}, 10 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 11 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 12 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 13 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 14 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 15 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 16 | {1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 17 | {1,4,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 18 | {1,4,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 19 | {1,4,0,0,0,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 20 | {1,4,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 21 | {1,4,0,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 22 | {1,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 23 | {1,4,4,4,4,4,4,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, 24 | {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 25 | 26 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | Mojo-Demo 4 | 5 | 6 | 7 | 8 | 9 | net.sourceforge.veditor.simulateBuilder 10 | 11 | 12 | net.sourceforge.veditor.simulateBuilder.00000000Default.CleanCommand 13 | echo 'Clean' 14 | 15 | 16 | net.sourceforge.veditor.simulateBuilder.00000000Default.buildOrder 17 | 0 18 | 19 | 20 | net.sourceforge.veditor.simulateBuilder.00000000Default.command 21 | echo 'No Build Configuration Specified' 22 | 23 | 24 | net.sourceforge.veditor.simulateBuilder.00000000Default.enable 25 | false 26 | 27 | 28 | net.sourceforge.veditor.simulateBuilder.00000000Default.name 29 | Default 30 | 31 | 32 | net.sourceforge.veditor.simulateBuilder.00000000Default.parser 33 | 34 | 35 | 36 | net.sourceforge.veditor.simulateBuilder.00000000Default.workFolder 37 | 38 | 39 | 40 | 41 | 42 | 43 | net.sourceforge.veditor.HdlNature 44 | 45 | 46 | -------------------------------------------------------------------------------- /src/mojo.ucf: -------------------------------------------------------------------------------- 1 | #Created by Constraints Editor (xc6slx9-tqg144-3) - 2012/11/05 2 | NET "clk" TNM_NET = clk; 3 | TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%; 4 | 5 | # PlanAhead Generated physical constraints 6 | NET "clk" LOC = P56 | IOSTANDARD = LVTTL; 7 | NET "rst_n" LOC = P38 | IOSTANDARD = LVTTL; 8 | 9 | NET "cclk" LOC = P70 | IOSTANDARD = LVTTL; 10 | 11 | NET "led<0>" LOC = P134 | IOSTANDARD = LVTTL; 12 | NET "led<1>" LOC = P133 | IOSTANDARD = LVTTL; 13 | NET "led<2>" LOC = P132 | IOSTANDARD = LVTTL; 14 | NET "led<3>" LOC = P131 | IOSTANDARD = LVTTL; 15 | NET "led<4>" LOC = P127 | IOSTANDARD = LVTTL; 16 | NET "led<5>" LOC = P126 | IOSTANDARD = LVTTL; 17 | NET "led<6>" LOC = P124 | IOSTANDARD = LVTTL; 18 | NET "led<7>" LOC = P123 | IOSTANDARD = LVTTL; 19 | 20 | NET "spi_mosi" LOC = P44 | IOSTANDARD = LVTTL; 21 | NET "spi_miso" LOC = P45 | IOSTANDARD = LVTTL; 22 | NET "spi_ss" LOC = P48 | IOSTANDARD = LVTTL; 23 | NET "spi_sck" LOC = P43 | IOSTANDARD = LVTTL; 24 | NET "spi_channel<0>" LOC = P46 | IOSTANDARD = LVTTL; 25 | NET "spi_channel<1>" LOC = P61 | IOSTANDARD = LVTTL; 26 | NET "spi_channel<2>" LOC = P62 | IOSTANDARD = LVTTL; 27 | NET "spi_channel<3>" LOC = P65 | IOSTANDARD = LVTTL; 28 | 29 | NET "avr_tx" LOC = P55 | IOSTANDARD = LVTTL; 30 | NET "avr_rx" LOC = P59 | IOSTANDARD = LVTTL; 31 | NET "avr_rx_busy" LOC = P39 | IOSTANDARD = LVTTL; 32 | 33 | NET "lcd_sck" LOC = P17 | IOSTANDARD = LVTTL; 34 | NET "lcd_mosi" LOC = P16 | IOSTANDARD = LVTTL; 35 | NET "lcd_ss" LOC = P15 | IOSTANDARD = LVTTL; 36 | NET "lcd_dcx" LOC = P14 | IOSTANDARD = LVTTL; 37 | NET "lcd_bl" LOC = P12 | IOSTANDARD = LVTTL; 38 | NET "lcd_rst" LOC = P11 | IOSTANDARD = LVTTL; 39 | -------------------------------------------------------------------------------- /scripts/texloader.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | 3 | use warnings; 4 | use strict; 5 | use Device::SerialPort; 6 | 7 | my $port = Device::SerialPort->new("/dev/ttyACM0"); 8 | 9 | #$port->baudrate(9600); 10 | $port->baudrate(115200); 11 | $port->databits(8); 12 | $port->parity("none"); 13 | $port->stopbits(1); 14 | # timeout stuff 15 | $port->read_char_time(0); 16 | $port->read_const_time(1000); 17 | 18 | my $offset = 0; 19 | my $poffset = 0; 20 | 21 | for my $file (@ARGV) { 22 | load_tex($file, $offset); 23 | my $pal = $file; 24 | $pal =~ s/\.flat/.pal/; 25 | load_pal($pal, $poffset); 26 | $offset += 1024; 27 | $poffset += 15; 28 | select undef, undef, undef, 0.25; 29 | } 30 | 31 | sub load_pal { 32 | my $file = shift; 33 | my $offset = shift; 34 | print "$file...\n"; 35 | open(my $fh, "<$file") or die "boop: $!"; 36 | my $buf; 37 | my $pbuf; 38 | my $cnt = 0; 39 | while (read($fh, $buf, 2)) { 40 | $pbuf .= $buf . pack('n', 0); 41 | $cnt++; 42 | } 43 | close($fh); 44 | 45 | my $cmd = 0b11000001; 46 | my $packed = pack('CSL', $cmd, $cnt-1, $offset); 47 | $port->write($packed); 48 | $port->write($pbuf); 49 | } 50 | 51 | sub load_tex { 52 | my $file = shift; 53 | my $offset = shift; 54 | print "$file...\n"; 55 | open(my $fh, "<$file") or die "boop: $!"; 56 | my $buf; 57 | my $pbuf; 58 | while (read($fh, $buf, 1)) { 59 | $pbuf .= pack('L', ord($buf)); 60 | } 61 | close($fh); 62 | 63 | my $cmd = 0b11000011; 64 | my $packed = pack('CSL', $cmd, 1023, $offset); 65 | $port->write($packed); 66 | $port->write($pbuf); 67 | } 68 | -------------------------------------------------------------------------------- /src/cast_ray_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module cast_ray_tb( 4 | ); 5 | 6 | reg clk; 7 | reg rst; 8 | 9 | reg [8:0] x; 10 | reg [6:0] turn; 11 | 12 | reg [15:0] map_pos_x; 13 | reg [15:0] map_pos_y; 14 | 15 | reg start; 16 | wire busy; 17 | wire [23:0] line_height; 18 | wire [7:0] line_color; 19 | wire [6:0] line_tex_x; 20 | 21 | cast_ray DUT ( 22 | .clk(clk), 23 | .rst(rst), 24 | .x(x), 25 | .turn(turn), 26 | .map_pos_x(map_pos_x), 27 | .map_pos_y(map_pos_y), 28 | .start(start), 29 | .busy(busy), 30 | .line_height(line_height), 31 | .line_color(line_color), 32 | .line_tex_x(line_tex_x) 33 | ); 34 | 35 | // wait by delay for clocks rather than manually run them. 36 | initial begin 37 | clk = 0; 38 | forever #10 clk = ~clk; 39 | end 40 | 41 | initial begin 42 | rst = 1'b1; 43 | repeat(6) @(posedge clk); 44 | rst = 1'b0; 45 | repeat(2) @(posedge clk); 46 | /*delta_dist_n_x = 16'hFF_00; 47 | delta_dist_n_y = 16'hFE_7D; 48 | map_pos_x = 16'h16_00; 49 | map_pos_y = 16'h16_00;*/ 50 | // 37 fe d0 fe 51 | //delta_dist_n_y = 16'hFE_37; 52 | //delta_dist_n_x = 16'hFE_D0; 53 | // 0c 13 90 14 54 | x = 9'd30; 55 | turn = 7'd16; 56 | map_pos_x = 16'h13_0c; 57 | map_pos_y = 16'h14_90; 58 | start = 1'b1; 59 | @(posedge clk); 60 | start = 1'b0; 61 | repeat(100) @(posedge clk); 62 | // done and line_height should be set. 63 | #5000 64 | $finish; 65 | end 66 | 67 | initial begin 68 | #500000000 69 | $finish; 70 | end 71 | endmodule 72 | -------------------------------------------------------------------------------- /src/spi_slave.v: -------------------------------------------------------------------------------- 1 | module spi_slave( 2 | input clk, 3 | input rst, 4 | input ss, 5 | input mosi, 6 | output miso, 7 | input sck, 8 | output done, 9 | input [7:0] din, 10 | output [7:0] dout 11 | ); 12 | 13 | reg mosi_d, mosi_q; 14 | reg ss_d, ss_q; 15 | reg sck_d, sck_q; 16 | reg sck_old_d, sck_old_q; 17 | reg [7:0] data_d, data_q; 18 | reg done_d, done_q; 19 | reg [2:0] bit_ct_d, bit_ct_q; 20 | reg [7:0] dout_d, dout_q; 21 | reg miso_d, miso_q; 22 | 23 | assign miso = miso_q; 24 | assign done = done_q; 25 | assign dout = dout_q; 26 | 27 | always @(*) begin 28 | ss_d = ss; 29 | mosi_d = mosi; 30 | miso_d = miso_q; 31 | sck_d = sck; 32 | sck_old_d = sck_q; 33 | data_d = data_q; 34 | done_d = 1'b0; 35 | bit_ct_d = bit_ct_q; 36 | dout_d = dout_q; 37 | 38 | if (ss_q) begin 39 | bit_ct_d = 3'b0; 40 | data_d = din; 41 | miso_d = data_q[7]; 42 | end else begin 43 | if (!sck_old_q && sck_q) begin // rising edge 44 | data_d = {data_q[6:0], mosi_q}; 45 | bit_ct_d = bit_ct_q + 1'b1; 46 | if (bit_ct_q == 3'b111) begin 47 | dout_d = {data_q[6:0], mosi_q}; 48 | done_d = 1'b1; 49 | data_d = din; 50 | end 51 | end else if (sck_old_q && !sck_q) begin // falling edge 52 | miso_d = data_q[7]; 53 | end 54 | end 55 | end 56 | 57 | always @(posedge clk) begin 58 | if (rst) begin 59 | done_q <= 1'b0; 60 | bit_ct_q <= 3'b0; 61 | dout_q <= 8'b0; 62 | miso_q <= 1'b1; 63 | end else begin 64 | done_q <= done_d; 65 | bit_ct_q <= bit_ct_d; 66 | dout_q <= dout_d; 67 | miso_q <= miso_d; 68 | end 69 | 70 | sck_q <= sck_d; 71 | mosi_q <= mosi_d; 72 | ss_q <= ss_d; 73 | data_q <= data_d; 74 | sck_old_q <= sck_old_d; 75 | 76 | end 77 | 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /src/sprite_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sprite_tb( 4 | ); 5 | 6 | reg clk; 7 | reg rst; 8 | 9 | reg start; 10 | wire done; 11 | //reg [79:0] angle; 12 | reg [15:0] map_pos_x; 13 | reg [15:0] map_pos_y; 14 | 15 | reg [6:0] smeta_waddr; 16 | reg [39:0] smeta_write_data; 17 | reg smeta_write_en; 18 | reg [6:0] stmeta_raddr; 19 | wire [119:0] stmeta_read_data; 20 | 21 | reg [6:0] angle_addr; 22 | wire [79:0] angle; 23 | angle_rom angle_rom ( 24 | .clk(clk), 25 | .addr(angle_addr), 26 | .angle(angle) // 4x Q8.8: dirX, dirY, planeX, planeY 27 | ); 28 | 29 | sprite DUT ( 30 | .clk(clk), 31 | .rst(rst), 32 | .start(start), 33 | .done(done), 34 | .angle(angle), 35 | .map_pos_x(map_pos_x), 36 | .map_pos_y(map_pos_y), 37 | .smeta_waddr(smeta_waddr), 38 | .smeta_write_data(smeta_write_data), 39 | .smeta_write_en(smeta_write_en), 40 | .stmeta_raddr(stmeta_raddr), 41 | .stmeta_read_data(stmeta_read_data) 42 | ); 43 | 44 | initial begin 45 | clk = 0; 46 | forever #10 clk = ~clk; 47 | end 48 | 49 | initial begin 50 | rst = 1'b1; 51 | repeat(6) @(posedge clk); 52 | rst = 1'b0; 53 | repeat(2) @(posedge clk); 54 | smeta_waddr = 0; 55 | // texture 1, map pos h12, h12. 56 | smeta_write_data = 40'h01_1200_1200; 57 | smeta_write_en = 1'b1; 58 | angle_addr = 0; 59 | repeat(1) @(posedge clk); 60 | smeta_write_en = 1'b0; 61 | //angle = 80'hff_00_00_00_00_00_00_a8_02_f0; 62 | //angle = 80'hff_00_00_00_00_00_00_a8_01_83; 63 | map_pos_x = 16'h13_00; 64 | map_pos_y = 16'h13_00; 65 | start = 1'b1; 66 | repeat(1) @(posedge clk); 67 | start = 1'b0; 68 | repeat(400) @(posedge clk); 69 | #5000 70 | $finish; 71 | end 72 | 73 | initial begin 74 | #500000000 75 | $finish; 76 | end 77 | endmodule 78 | -------------------------------------------------------------------------------- /scripts/serialray.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | 3 | use warnings; 4 | use strict; 5 | use Device::SerialPort; 6 | use Data::Dumper qw/Dumper/; 7 | 8 | $|++; 9 | my $port = Device::SerialPort->new("/dev/ttyACM0"); 10 | 11 | $port->baudrate(9600); 12 | #$port->baudrate(115200); 13 | #$port->baudrate(256000); 14 | $port->databits(8); 15 | $port->parity("none"); 16 | $port->stopbits(1); 17 | # timeout stuff 18 | $port->read_char_time(0); 19 | $port->read_const_time(1000); 20 | 21 | open(my $sout_line, "> sout_line") or die "meh: $!"; 22 | $sout_line->autoflush(1); 23 | 24 | my $leds = $ARGV[0]; 25 | my $map_x = $ARGV[1]; 26 | my $map_y = $ARGV[2]; 27 | my $turn = $ARGV[3]; 28 | # show how many CPU cycles the frame took. 29 | my $cycles = $ARGV[4] || 0; 30 | # Blank LED's. 31 | my $cmd = 0b10000000; 32 | my $packed = pack('CSLL', $cmd, 0, 0, $leds); 33 | $port->write($packed); 34 | select undef, undef, undef, 0.1; 35 | 36 | print "casting rays...\n"; 37 | cast_rays(); 38 | 39 | sub reduce { 40 | my $f = int($_[0] * 2**8); 41 | $f = -3200 if ($f < -32000); 42 | $f = 32000 if ($f > 32000); 43 | return $f; 44 | } 45 | 46 | sub cast_rays { 47 | my $cmd = 0b11000100; 48 | my $map_pos = pack('ss', int($map_x * 2**8), int($map_y * 2**8)); 49 | my $packed = pack('CSL', $cmd, 1, 0); 50 | $port->write($packed . $map_pos . pack('L', $turn)); 51 | return unless $cycles; 52 | # Should be more or less instantly done, but sleep a bit anyway. 53 | select undef, undef, undef, 0.1; 54 | $cmd = 0b00000100; 55 | $packed = pack('CSL', $cmd, 0, 0); 56 | $port->write($packed); 57 | { 58 | my $buf = ''; 59 | my $timeout = 2; 60 | while ($timeout) { 61 | my ($count, $got) = $port->read(255); 62 | if ($count > 0) { 63 | $buf .= $got; 64 | last if length($buf) >= 4; 65 | } else { 66 | $timeout--; 67 | } 68 | print STDERR "cycle $count\n"; 69 | } 70 | print "cycle count: ", unpack('L', $buf), "\n"; 71 | open(my $dump, "> cycle_output") or die "meh: $!"; 72 | print $dump $buf; 73 | close($dump); 74 | } 75 | } 76 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp.xco: -------------------------------------------------------------------------------- 1 | ############################################################## 2 | # 3 | # Xilinx Core Generator version 14.7 4 | # Date: Fri Nov 30 06:46:53 2018 5 | # 6 | ############################################################## 7 | # 8 | # This file contains the customisation parameters for a 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended 10 | # that you do not manually alter this file as it may cause 11 | # unexpected and unsupported behavior. 12 | # 13 | ############################################################## 14 | # 15 | # Generated from component: xilinx.com:ip:div_gen:4.0 16 | # 17 | ############################################################## 18 | # 19 | # BEGIN Project Options 20 | SET addpads = false 21 | SET asysymbol = true 22 | SET busformat = BusFormatAngleBracketNotRipped 23 | SET createndf = false 24 | SET designentry = Verilog 25 | SET device = xc6slx9 26 | SET devicefamily = spartan6 27 | SET flowvendor = Other 28 | SET formalverification = false 29 | SET foundationsym = false 30 | SET implementationfiletype = Ngc 31 | SET package = tqg144 32 | SET removerpms = false 33 | SET simulationfiles = Behavioral 34 | SET speedgrade = -2 35 | SET verilogsim = true 36 | SET vhdlsim = false 37 | # END Project Options 38 | # BEGIN Select 39 | SELECT Divider_Generator xilinx.com:ip:div_gen:4.0 40 | # END Select 41 | # BEGIN Parameters 42 | CSET aclken=false 43 | CSET algorithm_type=Radix2 44 | CSET aresetn=false 45 | CSET clocks_per_division=4 46 | CSET component_name=div_8_dot_8_nodsp 47 | CSET divide_by_zero_detect=false 48 | CSET dividend_and_quotient_width=24 49 | CSET dividend_has_tlast=false 50 | CSET dividend_has_tuser=false 51 | CSET dividend_tuser_width=1 52 | CSET divisor_has_tlast=false 53 | CSET divisor_has_tuser=false 54 | CSET divisor_tuser_width=1 55 | CSET divisor_width=16 56 | CSET flowcontrol=NonBlocking 57 | CSET fractional_width=16 58 | CSET latency=45 59 | CSET latency_configuration=Automatic 60 | CSET operand_sign=Signed 61 | CSET optimizegoal=Performance 62 | CSET outtlastbehv=Null 63 | CSET outtready=false 64 | CSET remainder_type=Fractional 65 | # END Parameters 66 | # BEGIN Extra information 67 | MISC pkg_timestamp=2013-07-22T10:43:42Z 68 | # END Extra information 69 | GENERATE 70 | # CRC: bbab219b 71 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk_flist.txt: -------------------------------------------------------------------------------- 1 | # Output products list for 2 | _xmsgs/pn_parser.xmsgs 3 | lcd_spi_clk/clk_wiz_v3_6_readme.txt 4 | lcd_spi_clk/doc/clk_wiz_v3_6_readme.txt 5 | lcd_spi_clk/doc/clk_wiz_v3_6_vinfo.html 6 | lcd_spi_clk/doc/pg065_clk_wiz.pdf 7 | lcd_spi_clk/example_design/lcd_spi_clk_exdes.ucf 8 | lcd_spi_clk/example_design/lcd_spi_clk_exdes.v 9 | lcd_spi_clk/example_design/lcd_spi_clk_exdes.xdc 10 | lcd_spi_clk/implement/implement.bat 11 | lcd_spi_clk/implement/implement.sh 12 | lcd_spi_clk/implement/planAhead_ise.bat 13 | lcd_spi_clk/implement/planAhead_ise.sh 14 | lcd_spi_clk/implement/planAhead_ise.tcl 15 | lcd_spi_clk/implement/planAhead_rdn.bat 16 | lcd_spi_clk/implement/planAhead_rdn.sh 17 | lcd_spi_clk/implement/planAhead_rdn.tcl 18 | lcd_spi_clk/implement/xst.prj 19 | lcd_spi_clk/implement/xst.scr 20 | lcd_spi_clk/simulation/functional/simcmds.tcl 21 | lcd_spi_clk/simulation/functional/simulate_isim.bat 22 | lcd_spi_clk/simulation/functional/simulate_isim.sh 23 | lcd_spi_clk/simulation/functional/simulate_mti.bat 24 | lcd_spi_clk/simulation/functional/simulate_mti.do 25 | lcd_spi_clk/simulation/functional/simulate_mti.sh 26 | lcd_spi_clk/simulation/functional/simulate_ncsim.sh 27 | lcd_spi_clk/simulation/functional/simulate_vcs.sh 28 | lcd_spi_clk/simulation/functional/ucli_commands.key 29 | lcd_spi_clk/simulation/functional/vcs_session.tcl 30 | lcd_spi_clk/simulation/functional/wave.do 31 | lcd_spi_clk/simulation/functional/wave.sv 32 | lcd_spi_clk/simulation/lcd_spi_clk_tb.v 33 | lcd_spi_clk/simulation/timing/lcd_spi_clk_tb.v 34 | lcd_spi_clk/simulation/timing/sdf_cmd_file 35 | lcd_spi_clk/simulation/timing/simcmds.tcl 36 | lcd_spi_clk/simulation/timing/simulate_isim.sh 37 | lcd_spi_clk/simulation/timing/simulate_mti.bat 38 | lcd_spi_clk/simulation/timing/simulate_mti.do 39 | lcd_spi_clk/simulation/timing/simulate_mti.sh 40 | lcd_spi_clk/simulation/timing/simulate_ncsim.sh 41 | lcd_spi_clk/simulation/timing/simulate_vcs.sh 42 | lcd_spi_clk/simulation/timing/ucli_commands.key 43 | lcd_spi_clk/simulation/timing/vcs_session.tcl 44 | lcd_spi_clk/simulation/timing/wave.do 45 | lcd_spi_clk.asy 46 | lcd_spi_clk.gise 47 | lcd_spi_clk.ucf 48 | lcd_spi_clk.v 49 | lcd_spi_clk.veo 50 | lcd_spi_clk.xco 51 | lcd_spi_clk.xdc 52 | lcd_spi_clk.xise 53 | lcd_spi_clk_flist.txt 54 | lcd_spi_clk_xmdf.tcl 55 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.gise: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 11.1 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /scripts/textureprep.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | # parses textures/sprites into flat data loadable by the serial protocol, 3 | # along with palette files for each. 4 | # see: tload.sh and texloader.pl 5 | 6 | use warnings; 7 | use strict; 8 | 9 | use GD; 10 | 11 | my $sdir = $ARGV[0]; 12 | my $odir = $ARGV[1]; 13 | my $sprite = $ARGV[2] || 0; 14 | 15 | opendir(my $dh, $sdir) or die "meh: $!"; 16 | while (readdir($dh)) { 17 | next unless $_ =~ m/\.png$/; 18 | process($_); 19 | } 20 | closedir($dh); 21 | 22 | sub sixteenbit { 23 | my @c = @_; 24 | $c[0] = ($c[0] * 249 + 1024) >> 11; 25 | $c[1] = ($c[1] * 253 + 505) >> 10; 26 | $c[2] = ($c[2] * 249 + 1024) >> 11; 27 | my $bin = pack('s', ($c[0] << 11) | ($c[1] << 5) | $c[2]); 28 | return $bin; 29 | } 30 | 31 | sub process { 32 | my $file = shift; 33 | my $im = GD::Image->newFromPng($sdir . $file, 1); 34 | # 15 colors + alpha channel (always high color). 35 | 36 | my $nim = new GD::Image->newTrueColor(32, 32); 37 | $nim->alphaBlending(0); 38 | $nim->saveAlpha(1); 39 | # we downsample to 32x32x4bit to save block RAM. 40 | $nim->copyResampled($im, 0, 0, 0, 0, 32, 32, 64, 64); 41 | $nim->trueColorToPalette(0, 14); 42 | my $total = $nim->colorsTotal; 43 | # some of the source sprites aren't 64x64 44 | if ($total == 256 || $im->width != 64 || $im->height != 64) { 45 | print "Skipping: $file: $total\n"; 46 | return; 47 | } 48 | print "$file: $total\n"; 49 | 50 | # Copy color index. 51 | open(my $pal, "> $odir/$file.pal") or die "boop: $!"; 52 | for (0 .. $total-1) { 53 | print $pal sixteenbit($nim->rgb($_)); 54 | } 55 | close($pal); 56 | 57 | my @f; 58 | open(my $flat, "> $odir/$file.flat") or die "boop: $!"; 59 | # the alpha seems to get randomized during "dithering" above. 60 | # in these particular source images the corner is always a transparent 61 | # one, so find that index and re-slot it into our alpha channel number. 62 | my $alpha = $nim->getPixel(0, 0); 63 | for (my $x = 0; $x < $nim->width; $x++) { 64 | for (my $y = 0; $y < $nim->height; $y++) { 65 | my $c = $nim->getPixel($x, $y); 66 | #print $flat $f[$x][$y], " "; 67 | #print $flat $c, " "; 68 | if ($c == $alpha && $sprite) { 69 | # only for sprites! 70 | # keep a consistent alpha channel. 71 | $c = 15; 72 | } 73 | #print "C: $c\n"; 74 | print $flat pack('C', $c); 75 | } 76 | } 77 | 78 | open(my $out, "> $odir/$file") or die "boop: $!"; 79 | binmode $out; 80 | print $out $nim->png; 81 | close($out); 82 | close($flat); 83 | } 84 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.ucf: -------------------------------------------------------------------------------- 1 | # file: lcd_spi_clk.ucf 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system 52 | #---------------------------------------------------------------- 53 | NET "CLK_IN1" TNM_NET = "CLK_IN1"; 54 | TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; 55 | 56 | 57 | # FALSE PATH constraints 58 | 59 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.ncf: -------------------------------------------------------------------------------- 1 | # file: lcd_spi_clk.ucf 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system 52 | #---------------------------------------------------------------- 53 | NET "CLK_IN1" TNM_NET = "CLK_IN1"; 54 | TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; 55 | 56 | 57 | # FALSE PATH constraints 58 | 59 | 60 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # file: planAhead_rdn.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | #----------------------------------------------------------------------------- 52 | # Script to synthesize and implement the RTL provided for the XADC wizard 53 | #----------------------------------------------------------------------------- 54 | rm -rf results 55 | mkdir results 56 | cd results 57 | planAhead -mode batch -source ../planAhead_rdn.tcl 58 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/planAhead_ise.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # file: planAhead_ise.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | #----------------------------------------------------------------------------- 52 | # Script to synthesize and implement the RTL provided for the clocking wizard 53 | #----------------------------------------------------------------------------- 54 | 55 | rm -rf results 56 | mkdir results 57 | cd results 58 | 59 | planAhead -mode batch -source ../planAhead_ise.tcl 60 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.ucf: -------------------------------------------------------------------------------- 1 | # file: lcd_spi_clk_exdes.ucf 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system 52 | #---------------------------------------------------------------- 53 | NET "CLK_IN1" TNM_NET = "CLK_IN1"; 54 | TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps; 55 | 56 | 57 | # FALSE PATH constraints 58 | PIN "COUNTER_RESET" TIG; 59 | 60 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #/bin/sh 2 | # file: simulate_mti.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | # set up the working directory 51 | set work work 52 | vlib work 53 | 54 | # compile all of the files 55 | vlog -work work $XILINX/verilog/src/glbl.v 56 | vlog -work work ../../../lcd_spi_clk.v 57 | vlog -work work ../../example_design/lcd_spi_clk_exdes.v 58 | vlog -work work ../lcd_spi_clk_tb.v 59 | 60 | # run the simulation 61 | vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.lcd_spi_clk_tb work.glbl 62 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.bat: -------------------------------------------------------------------------------- 1 | REM file: planAhead_rdn.sh 2 | REM 3 | REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | REM 5 | REM This file contains confidential and proprietary information 6 | REM of Xilinx, Inc. and is protected under U.S. and 7 | REM international copyright and other intellectual property 8 | REM laws. 9 | REM 10 | REM DISCLAIMER 11 | REM This disclaimer is not a license and does not grant any 12 | REM rights to the materials distributed herewith. Except as 13 | REM otherwise provided in a valid license issued to you by 14 | REM Xilinx, and to the maximum extent permitted by applicable 15 | REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | REM (2) Xilinx shall not be liable (whether in contract or tort, 21 | REM including negligence, or under any other theory of 22 | REM liability) for any loss or damage of any kind or nature 23 | REM related to, arising under or in connection with these 24 | REM materials, including for any direct, or any indirect, 25 | REM special, incidental, or consequential loss or damage 26 | REM (including loss of data, profits, goodwill, or any type of 27 | REM loss or damage suffered as a result of any action brought 28 | REM by a third party) even if such damage or loss was 29 | REM reasonably foreseeable or Xilinx had been advised of the 30 | REM possibility of the same. 31 | REM 32 | REM CRITICAL APPLICATIONS 33 | REM Xilinx products are not designed or intended to be fail- 34 | REM safe, or for use in any application requiring fail-safe 35 | REM performance, such as life-support or safety devices or 36 | REM systems, Class III medical devices, nuclear facilities, 37 | REM applications related to the deployment of airbags, or any 38 | REM other applications that could lead to death, personal 39 | REM injury, or severe property or environmental damage 40 | REM (individually and collectively, "Critical 41 | REM Applications"). Customer assumes the sole risk and 42 | REM liability of any use of Xilinx products in Critical 43 | REM Applications, subject only to applicable laws and 44 | REM regulations governing limitations on product liability. 45 | REM 46 | REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | REM PART OF THIS FILE AT ALL TIMES. 48 | REM 49 | 50 | REM----------------------------------------------------------------------------- 51 | REM Script to synthesize and implement the RTL provided for the XADC wizard 52 | REM----------------------------------------------------------------------------- 53 | 54 | del \f results 55 | mkdir results 56 | cd results 57 | 58 | planAhead -mode batch -source ..\planAhead_rdn.tcl 59 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.sh: -------------------------------------------------------------------------------- 1 | # file: simulate_isim.sh 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # lin64 51 | # create the project 52 | vlogcomp -work work ${XILINX}/verilog/src/glbl.v 53 | vlogcomp -work work ../../../lcd_spi_clk.v 54 | vlogcomp -work work ../../example_design/lcd_spi_clk_exdes.v 55 | vlogcomp -work work ../lcd_spi_clk_tb.v 56 | 57 | # compile the project 58 | fuse work.lcd_spi_clk_tb work.glbl -L unisims_ver -o lcd_spi_clk_isim.exe 59 | 60 | # run the simulation script 61 | ./lcd_spi_clk_isim.exe -gui -tclbatch simcmds.tcl 62 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/planAhead_ise.bat: -------------------------------------------------------------------------------- 1 | REM file: planAhead_ise.bat 2 | REM 3 | REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | REM 5 | REM This file contains confidential and proprietary information 6 | REM of Xilinx, Inc. and is protected under U.S. and 7 | REM international copyright and other intellectual property 8 | REM laws. 9 | REM 10 | REM DISCLAIMER 11 | REM This disclaimer is not a license and does not grant any 12 | REM rights to the materials distributed herewith. Except as 13 | REM otherwise provided in a valid license issued to you by 14 | REM Xilinx, and to the maximum extent permitted by applicable 15 | REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | REM (2) Xilinx shall not be liable (whether in contract or tort, 21 | REM including negligence, or under any other theory of 22 | REM liability) for any loss or damage of any kind or nature 23 | REM related to, arising under or in connection with these 24 | REM materials, including for any direct, or any indirect, 25 | REM special, incidental, or consequential loss or damage 26 | REM (including loss of data, profits, goodwill, or any type of 27 | REM loss or damage suffered as a result of any action brought 28 | REM by a third party) even if such damage or loss was 29 | REM reasonably foreseeable or Xilinx had been advised of the 30 | REM possibility of the same. 31 | REM 32 | REM CRITICAL APPLICATIONS 33 | REM Xilinx products are not designed or intended to be fail- 34 | REM safe, or for use in any application requiring fail-safe 35 | REM performance, such as life-support or safety devices or 36 | REM systems, Class III medical devices, nuclear facilities, 37 | REM applications related to the deployment of airbags, or any 38 | REM other applications that could lead to death, personal 39 | REM injury, or severe property or environmental damage 40 | REM (individually and collectively, "Critical 41 | REM Applications"). Customer assumes the sole risk and 42 | REM liability of any use of Xilinx products in Critical 43 | REM Applications, subject only to applicable laws and 44 | REM regulations governing limitations on product liability. 45 | REM 46 | REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | REM PART OF THIS FILE AT ALL TIMES. 48 | REM 49 | 50 | REM----------------------------------------------------------------------------- 51 | REM Script to synthesize and implement the RTL provided for the clocking wizard 52 | REM----------------------------------------------------------------------------- 53 | 54 | del \f results 55 | mkdir results 56 | cd results 57 | 58 | planAhead -mode batch -source ..\planAhead_ise.tcl 59 | -------------------------------------------------------------------------------- /src/serial_rx.v: -------------------------------------------------------------------------------- 1 | // from embedded micro base project 2 | module serial_rx #( 3 | parameter CLK_PER_BIT = 50 4 | )( 5 | input clk, 6 | input rst, 7 | input rx, 8 | output [7:0] data, 9 | output new_data 10 | ); 11 | 12 | // clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value 13 | parameter CTR_SIZE = $clog2(CLK_PER_BIT); 14 | 15 | localparam STATE_SIZE = 2; 16 | localparam IDLE = 2'd0, 17 | WAIT_HALF = 2'd1, 18 | WAIT_FULL = 2'd2, 19 | WAIT_HIGH = 2'd3; 20 | 21 | reg [CTR_SIZE-1:0] ctr_d, ctr_q; 22 | reg [2:0] bit_ctr_d, bit_ctr_q; 23 | reg [7:0] data_d, data_q; 24 | reg new_data_d, new_data_q; 25 | reg [STATE_SIZE-1:0] state_d, state_q = IDLE; 26 | reg rx_d, rx_q; 27 | 28 | assign new_data = new_data_q; 29 | assign data = data_q; 30 | 31 | always @(*) begin 32 | rx_d = rx; 33 | state_d = state_q; 34 | ctr_d = ctr_q; 35 | bit_ctr_d = bit_ctr_q; 36 | data_d = data_q; 37 | new_data_d = 1'b0; 38 | 39 | case (state_q) 40 | IDLE: begin 41 | bit_ctr_d = 3'b0; 42 | ctr_d = 1'b0; 43 | if (rx_q == 1'b0) begin 44 | state_d = WAIT_HALF; 45 | end 46 | end 47 | WAIT_HALF: begin 48 | ctr_d = ctr_q + 1'b1; 49 | if (ctr_q == (CLK_PER_BIT >> 1)) begin 50 | ctr_d = 1'b0; 51 | state_d = WAIT_FULL; 52 | end 53 | end 54 | WAIT_FULL: begin 55 | ctr_d = ctr_q + 1'b1; 56 | if (ctr_q == CLK_PER_BIT - 1) begin 57 | data_d = {rx_q, data_q[7:1]}; 58 | bit_ctr_d = bit_ctr_q + 1'b1; 59 | ctr_d = 1'b0; 60 | if (bit_ctr_q == 3'd7) begin 61 | state_d = WAIT_HIGH; 62 | new_data_d = 1'b1; 63 | end 64 | end 65 | end 66 | WAIT_HIGH: begin 67 | if (rx_q == 1'b1) begin 68 | state_d = IDLE; 69 | end 70 | end 71 | default: begin 72 | state_d = IDLE; 73 | end 74 | endcase 75 | 76 | end 77 | 78 | always @(posedge clk) begin 79 | if (rst) begin 80 | ctr_q <= 1'b0; 81 | bit_ctr_q <= 3'b0; 82 | new_data_q <= 1'b0; 83 | state_q <= IDLE; 84 | end else begin 85 | ctr_q <= ctr_d; 86 | bit_ctr_q <= bit_ctr_d; 87 | new_data_q <= new_data_d; 88 | state_q <= state_d; 89 | end 90 | 91 | rx_q <= rx_d; 92 | data_q <= data_d; 93 | end 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.sh: -------------------------------------------------------------------------------- 1 | #/bin/sh 2 | # file: simulate_mti.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # set up the working directory 52 | set work work 53 | vlib work 54 | 55 | # compile all of the files 56 | vlog -work work $XILINX/verilog/src/glbl.v 57 | vlog -work work ../../implement/results/routed.v 58 | vlog -work work lcd_spi_clk_tb.v 59 | 60 | # run the simulation 61 | vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax lcd_spi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.lcd_spi_clk_tb work.glbl 62 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.do: -------------------------------------------------------------------------------- 1 | # file: simulate_mti.do 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # set up the working directory 51 | set work work 52 | vlib work 53 | 54 | # compile all of the files 55 | vlog -work work $env(XILINX)/verilog/src/glbl.v 56 | vlog -work work ../../../lcd_spi_clk.v 57 | vlog -work work ../../example_design/lcd_spi_clk_exdes.v 58 | vlog -work work ../lcd_spi_clk_tb.v 59 | 60 | # run the simulation 61 | vsim -t ps -voptargs="+acc" -L unisims_ver work.lcd_spi_clk_tb work.glbl 62 | do wave.do 63 | log lcd_spi_clk_tb/dut/counter 64 | log -r /* 65 | run 50000ns 66 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/wave.do: -------------------------------------------------------------------------------- 1 | # file: wave.do 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | add wave -noupdate -format Literal -radix ascii /lcd_spi_clk_tb/test_phase 51 | add wave -noupdate -divider {Input clocks} 52 | add wave -noupdate -format Logic /lcd_spi_clk_tb/CLK_IN1 53 | add wave -noupdate -divider {Output clocks} 54 | add wave -noupdate -format Literal -expand /lcd_spi_clk_tb/dut/clk 55 | add wave -noupdate -divider Counters 56 | add wave -noupdate -format Literal -radix hexadecimal /lcd_spi_clk_tb/COUNT 57 | add wave -noupdate -format Literal -radix hexadecimal -expand /lcd_spi_clk_tb/dut/counter 58 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.do: -------------------------------------------------------------------------------- 1 | # file: simulate_mti.do 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # set up the working directory 51 | set work work 52 | vlib work 53 | 54 | # compile all of the files 55 | vlog -work work $env(XILINX)/verilog/src/glbl.v 56 | vlog -work work ../../implement/results/routed.v 57 | vlog -work work lcd_spi_clk_tb.v 58 | 59 | # run the simulation 60 | vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax lcd_spi_clk_tb/dut=../../implement/results/routed.sdf +no_notifier work.lcd_spi_clk_tb work.glbl 61 | #do wave.do 62 | #log -r /* 63 | run 50000ns 64 | 65 | 66 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simulate_isim.sh: -------------------------------------------------------------------------------- 1 | # file: simulate_isim.sh 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # create the project 51 | vlogcomp -work work ${XILINX}/verilog/src/glbl.v 52 | vlogcomp -work work ../../implement/results/routed.v 53 | vlogcomp -work work lcd_spi_clk_tb.v 54 | 55 | # compile the project 56 | fuse work.lcd_spi_clk_tb work.glbl -L secureip -L simprims_ver -o lcd_spi_clk_isim.exe 57 | 58 | # run the simulation script 59 | ./lcd_spi_clk_isim.exe -tclbatch simcmds.tcl -sdfmax /lcd_spi_clk_tb/dut=../../implement/results/routed.sdf 60 | 61 | # run the simulation script 62 | #./lcd_spi_clk_isim.exe -gui -tclbatch simcmds.tcl 63 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | REM file: simulate_mti.bat 2 | REM 3 | REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | REM 5 | REM This file contains confidential and proprietary information 6 | REM of Xilinx, Inc. and is protected under U.S. and 7 | REM international copyright and other intellectual property 8 | REM laws. 9 | REM 10 | REM DISCLAIMER 11 | REM This disclaimer is not a license and does not grant any 12 | REM rights to the materials distributed herewith. Except as 13 | REM otherwise provided in a valid license issued to you by 14 | REM Xilinx, and to the maximum extent permitted by applicable 15 | REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | REM (2) Xilinx shall not be liable (whether in contract or tort, 21 | REM including negligence, or under any other theory of 22 | REM liability) for any loss or damage of any kind or nature 23 | REM related to, arising under or in connection with these 24 | REM materials, including for any direct, or any indirect, 25 | REM special, incidental, or consequential loss or damage 26 | REM (including loss of data, profits, goodwill, or any type of 27 | REM loss or damage suffered as a result of any action brought 28 | REM by a third party) even if such damage or loss was 29 | REM reasonably foreseeable or Xilinx had been advised of the 30 | REM possibility of the same. 31 | REM 32 | REM CRITICAL APPLICATIONS 33 | REM Xilinx products are not designed or intended to be fail- 34 | REM safe, or for use in any application requiring fail-safe 35 | REM performance, such as life-support or safety devices or 36 | REM systems, Class III medical devices, nuclear facilities, 37 | REM applications related to the deployment of airbags, or any 38 | REM other applications that could lead to death, personal 39 | REM injury, or severe property or environmental damage 40 | REM (individually and collectively, "Critical 41 | REM Applications"). Customer assumes the sole risk and 42 | REM liability of any use of Xilinx products in Critical 43 | REM Applications, subject only to applicable laws and 44 | REM regulations governing limitations on product liability. 45 | REM 46 | REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | REM PART OF THIS FILE AT ALL TIMES. 48 | REM 49 | 50 | REM set up the working directory 51 | vlib work 52 | 53 | REM compile all of the files 54 | vlog -work work %XILINX%\verilog\src\glbl.v 55 | vlog -work work ..\..\..\lcd_spi_clk.v 56 | vlog -work work ..\..\example_design\lcd_spi_clk_exdes.v 57 | vlog -work work ..\lcd_spi_clk_tb.v 58 | 59 | REM run the simulation 60 | vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.lcd_spi_clk_tb work.glbl 61 | 62 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_isim.bat: -------------------------------------------------------------------------------- 1 | REM file: simulate_isim.bat 2 | REM 3 | REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | REM 5 | REM This file contains confidential and proprietary information 6 | REM of Xilinx, Inc. and is protected under U.S. and 7 | REM international copyright and other intellectual property 8 | REM laws. 9 | REM 10 | REM DISCLAIMER 11 | REM This disclaimer is not a license and does not grant any 12 | REM rights to the materials distributed herewith. Except as 13 | REM otherwise provided in a valid license issued to you by 14 | REM Xilinx, and to the maximum extent permitted by applicable 15 | REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | REM (2) Xilinx shall not be liable (whether in contract or tort, 21 | REM including negligence, or under any other theory of 22 | REM liability) for any loss or damage of any kind or nature 23 | REM related to, arising under or in connection with these 24 | REM materials, including for any direct, or any indirect, 25 | REM special, incidental, or consequential loss or damage 26 | REM (including loss of data, profits, goodwill, or any type of 27 | REM loss or damage suffered as a result of any action brought 28 | REM by a third party) even if such damage or loss was 29 | REM reasonably foreseeable or Xilinx had been advised of the 30 | REM possibility of the same. 31 | REM 32 | REM CRITICAL APPLICATIONS 33 | REM Xilinx products are not designed or intended to be fail- 34 | REM safe, or for use in any application requiring fail-safe 35 | REM performance, such as life-support or safety devices or 36 | REM systems, Class III medical devices, nuclear facilities, 37 | REM applications related to the deployment of airbags, or any 38 | REM other applications that could lead to death, personal 39 | REM injury, or severe property or environmental damage 40 | REM (individually and collectively, "Critical 41 | REM Applications"). Customer assumes the sole risk and 42 | REM liability of any use of Xilinx products in Critical 43 | REM Applications, subject only to applicable laws and 44 | REM regulations governing limitations on product liability. 45 | REM 46 | REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | REM PART OF THIS FILE AT ALL TIMES. 48 | REM 49 | 50 | vlogcomp -work work %XILINX%\verilog\src\glbl.v 51 | vlogcomp -work work ..\..\..\lcd_spi_clk.v 52 | vlogcomp -work work ..\..\example_design\lcd_spi_clk_exdes.v 53 | vlogcomp -work work ..\lcd_spi_clk_tb.v 54 | 55 | REM compile the project 56 | fuse work.lcd_spi_clk_tb work.glbl -L unisims_ver -o lcd_spi_clk_isim.exe 57 | 58 | REM run the simulation script 59 | .\lcd_spi_clk_isim.exe -gui -tclbatch simcmds.tcl 60 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_ncsim.sh: -------------------------------------------------------------------------------- 1 | #/bin/sh 2 | # file: simulate_ncsim.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # set up the working directory 52 | mkdir work 53 | 54 | # compile all of the files 55 | ncvlog -work work ${XILINX}/verilog/src/glbl.v 56 | ncvlog -work work ../../../lcd_spi_clk.v 57 | ncvlog -work work ../../example_design/lcd_spi_clk_exdes.v 58 | ncvlog -work work ../lcd_spi_clk_tb.v 59 | 60 | # elaborate and run the simulation 61 | ncelab -work work -access +wc work.lcd_spi_clk_tb work.glbl 62 | ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.lcd_spi_clk_tb 63 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simulate_ncsim.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # file: simulate_ncsim.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # set up the working directory 52 | mkdir work 53 | 54 | # compile all of the files 55 | ncvlog -work work ${XILINX}/verilog/src/glbl.v 56 | ncvlog -work work ../../implement/results/routed.v 57 | ncvlog -work work lcd_spi_clk_tb.v 58 | 59 | # elaborate and run the simulation 60 | ncsdfc ../../implement/results/routed.sdf 61 | 62 | ncelab -work work -access +wc -pulse_r 10 -nonotifier work.lcd_spi_clk_tb work.glbl -sdf_cmd_file sdf_cmd_file 63 | ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.lcd_spi_clk_tb 64 | 65 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simulate_mti.bat: -------------------------------------------------------------------------------- 1 | REM file: simulate_mti.bat 2 | REM 3 | REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | REM 5 | REM This file contains confidential and proprietary information 6 | REM of Xilinx, Inc. and is protected under U.S. and 7 | REM international copyright and other intellectual property 8 | REM laws. 9 | REM 10 | REM DISCLAIMER 11 | REM This disclaimer is not a license and does not grant any 12 | REM rights to the materials distributed herewith. Except as 13 | REM otherwise provided in a valid license issued to you by 14 | REM Xilinx, and to the maximum extent permitted by applicable 15 | REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | REM (2) Xilinx shall not be liable (whether in contract or tort, 21 | REM including negligence, or under any other theory of 22 | REM liability) for any loss or damage of any kind or nature 23 | REM related to, arising under or in connection with these 24 | REM materials, including for any direct, or any indirect, 25 | REM special, incidental, or consequential loss or damage 26 | REM (including loss of data, profits, goodwill, or any type of 27 | REM loss or damage suffered as a result of any action brought 28 | REM by a third party) even if such damage or loss was 29 | REM reasonably foreseeable or Xilinx had been advised of the 30 | REM possibility of the same. 31 | REM 32 | REM CRITICAL APPLICATIONS 33 | REM Xilinx products are not designed or intended to be fail- 34 | REM safe, or for use in any application requiring fail-safe 35 | REM performance, such as life-support or safety devices or 36 | REM systems, Class III medical devices, nuclear facilities, 37 | REM applications related to the deployment of airbags, or any 38 | REM other applications that could lead to death, personal 39 | REM injury, or severe property or environmental damage 40 | REM (individually and collectively, "Critical 41 | REM Applications"). Customer assumes the sole risk and 42 | REM liability of any use of Xilinx products in Critical 43 | REM Applications, subject only to applicable laws and 44 | REM regulations governing limitations on product liability. 45 | REM 46 | REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | REM PART OF THIS FILE AT ALL TIMES. 48 | REM 49 | # set up the working directory 50 | set work work 51 | vlib work 52 | 53 | REM compile all of the files 54 | vlog -work work %XILINX%\verilog\src\glbl.v 55 | vlog -work work ..\..\implement\results\routed.v 56 | vlog -work work lcd_spi_clk_tb.v 57 | 58 | REM run the simulation 59 | vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax lcd_spi_clk_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.lcd_spi_clk_tb work.glbl 60 | -------------------------------------------------------------------------------- /src/lcd_driver.v: -------------------------------------------------------------------------------- 1 | // the actual SPI driver for the LCD runs in a separate clock domain, so we 2 | // need to use the task_crossdomain module to safely signal to the SPI and 3 | // back. This adds a few cycles of delay on either side. 4 | // Further improvements could queue the next byte and ensure the SPI stays 5 | // fed. 6 | module lcd_driver ( 7 | input clk, 8 | input fclk, // faster clock for SPI 9 | input rst, 10 | output lcd_sck, 11 | output lcd_mosi, 12 | output lcd_ss, 13 | output lcd_dcx, // lo: data, hi: cmd 14 | // TODO: backlight and reset. 15 | input [7:0] data_in, // data to write out 16 | input data_dcx, // lo: data, hi: cmd 17 | input start, 18 | output busy, 19 | output reg done // done executing transfer. 20 | ); 21 | 22 | localparam STATE_SIZE = 2; 23 | localparam IDLE = 0, 24 | START_TRANSFER = 1, 25 | WAIT_TRANSFER = 2; 26 | 27 | reg [STATE_SIZE-1:0] state_d, state_q; 28 | 29 | reg [7:0] data_d, data_q; 30 | 31 | wire spi_busy; 32 | reg spi_start; 33 | wire spi_start_l, spi_done_l; 34 | reg data_dcx_d, data_dcx_q; 35 | 36 | assign lcd_dcx = data_dcx_q; 37 | assign busy = state_q != IDLE; 38 | 39 | task_crossdomain task_crossdomain( 40 | .clka(clk), // external (slow) clock domain 41 | .taskstart_clka(spi_start), 42 | .taskbusy_clka(spi_busy), 43 | .taskdone_clka(), 44 | .clkb(fclk), // internal (fast) clock domain 45 | .taskstart_clkb(spi_start_l), 46 | .taskbusy_clkb(), 47 | .taskdone_clkb(spi_done_l) 48 | ); 49 | 50 | spi #(.CLK_DIV(2)) lcd_spi ( 51 | .clk(fclk), 52 | .rst(rst), 53 | .mosi(lcd_mosi), 54 | .miso(), 55 | .sck(lcd_sck), 56 | .start(spi_start_l), 57 | .ss(lcd_ss), 58 | .data_in(data_q), 59 | .data_out(), 60 | .busy(), 61 | .new_data(spi_done_l) 62 | ); 63 | 64 | always @(*) begin 65 | data_dcx_d = data_dcx_q; 66 | data_d = data_q; 67 | spi_start = 1'b0; 68 | done = 1'b0; 69 | state_d = state_q; 70 | 71 | case (state_q) 72 | IDLE: begin 73 | if (start) begin 74 | data_dcx_d = data_dcx; 75 | data_d = data_in; 76 | state_d = START_TRANSFER; 77 | end 78 | end 79 | START_TRANSFER: begin 80 | if (!spi_busy) begin 81 | spi_start = 1'b1; 82 | state_d = WAIT_TRANSFER; 83 | end 84 | end 85 | WAIT_TRANSFER: begin 86 | if (!spi_busy) begin 87 | done = 1'b1; 88 | state_d = IDLE; 89 | end 90 | end 91 | default: state_d = IDLE; 92 | endcase 93 | end 94 | 95 | always @(posedge clk) begin 96 | if (rst) begin 97 | state_q <= IDLE; 98 | data_dcx_q <= 0; 99 | data_q <= 0; 100 | end else begin 101 | state_q <= state_d; 102 | data_dcx_q <= data_dcx_d; 103 | data_q <= data_d; 104 | end 105 | end 106 | 107 | endmodule 108 | -------------------------------------------------------------------------------- /src/spi.v: -------------------------------------------------------------------------------- 1 | // (modified) from mojo example source code. 2 | // (same MIT license) 3 | 4 | module spi #(parameter CLK_DIV = 2)( 5 | input clk, 6 | input rst, 7 | input miso, 8 | output mosi, 9 | output sck, 10 | input start, 11 | output reg ss, // lcd_ss 12 | input[7:0] data_in, 13 | output[7:0] data_out, 14 | output busy, 15 | output new_data 16 | ); 17 | 18 | localparam STATE_SIZE = 2; 19 | localparam IDLE = 2'd0, 20 | WAIT_HALF = 2'd1, 21 | TRANSFER = 2'd2; 22 | 23 | reg [STATE_SIZE-1:0] state_d, state_q; 24 | 25 | reg [7:0] data_d, data_q; 26 | reg [CLK_DIV-1:0] sck_d, sck_q; 27 | reg mosi_d, mosi_q; 28 | reg [2:0] ctr_d, ctr_q; 29 | reg new_data_d, new_data_q; 30 | reg [7:0] data_out_d, data_out_q; 31 | 32 | assign mosi = mosi_q; 33 | // CPHA = 1 34 | //assign sck = (~sck_q[CLK_DIV-1]) & (state_q == TRANSFER); 35 | assign sck = (sck_q[CLK_DIV-1]) & (state_q == TRANSFER); // CPHA = 0 36 | assign busy = state_q != IDLE; 37 | assign data_out = data_out_q; 38 | assign new_data = new_data_q; 39 | 40 | always @(*) begin 41 | sck_d = sck_q; 42 | data_d = data_q; 43 | mosi_d = mosi_q; 44 | ctr_d = ctr_q; 45 | new_data_d = 1'b0; 46 | data_out_d = data_out_q; 47 | state_d = state_q; 48 | ss = 1'b1; // ss high when idle. 49 | 50 | case (state_q) 51 | IDLE: begin 52 | sck_d = 4'b0; 53 | ctr_d = 3'b0; 54 | if (start == 1'b1) begin 55 | data_d = data_in; 56 | state_d = WAIT_HALF; 57 | end 58 | end 59 | WAIT_HALF: begin 60 | sck_d = sck_q + 1'b1; 61 | if (sck_q == {CLK_DIV-1{1'b1}}) begin 62 | sck_d = 1'b0; 63 | state_d = TRANSFER; 64 | end 65 | end 66 | TRANSFER: begin 67 | sck_d = sck_q + 1'b1; 68 | ss = 1'b0; // low when active. 69 | if (sck_q == 4'b0000) begin 70 | mosi_d = data_q[7]; 71 | end else if (sck_q == {CLK_DIV-1{1'b1}}) begin 72 | data_d = {data_q[6:0], miso}; 73 | end else if (sck_q == {CLK_DIV{1'b1}}) begin 74 | ctr_d = ctr_q + 1'b1; 75 | if (ctr_q == 3'b111) begin 76 | state_d = IDLE; 77 | data_out_d = data_q; 78 | new_data_d = 1'b1; 79 | end 80 | end 81 | end 82 | endcase 83 | end 84 | 85 | always @(posedge clk) begin 86 | if (rst) begin 87 | ctr_q <= 3'b0; 88 | data_q <= 8'b0; 89 | sck_q <= 4'b0; 90 | mosi_q <= 1'b0; 91 | state_q <= IDLE; 92 | data_out_q <= 8'b0; 93 | new_data_q <= 1'b0; 94 | end else begin 95 | ctr_q <= ctr_d; 96 | data_q <= data_d; 97 | sck_q <= sck_d; 98 | mosi_q <= mosi_d; 99 | state_q <= state_d; 100 | data_out_q <= data_out_d; 101 | new_data_q <= new_data_d; 102 | end 103 | end 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/wave.do: -------------------------------------------------------------------------------- 1 | # file: wave.do 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | onerror {resume} 51 | quietly WaveActivateNextPane {} 0 52 | add wave -noupdate /lcd_spi_clk_tb/CLK_IN1 53 | add wave -noupdate /lcd_spi_clk_tb/COUNT 54 | TreeUpdate [SetDefaultTree] 55 | WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} 56 | configure wave -namecolwidth 238 57 | configure wave -valuecolwidth 107 58 | configure wave -justifyvalue left 59 | configure wave -signalnamewidth 0 60 | configure wave -snapdistance 10 61 | configure wave -datasetprefix 0 62 | configure wave -rowmargin 4 63 | configure wave -childrowmargin 2 64 | configure wave -gridoffset 0 65 | configure wave -gridperiod 1 66 | configure wave -griddelta 40 67 | configure wave -timeline 0 68 | configure wave -timelineunits ps 69 | update 70 | WaveRestoreZoom {0 ps} {74848022 ps} 71 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/functional/simulate_vcs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # file: simulate_vcs.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # remove old files 52 | rm -rf simv* csrc DVEfiles AN.DB 53 | 54 | # compile all of the files 55 | # Note that -sverilog is not strictly required- You can 56 | # remove the -sverilog if you change the type of the 57 | # localparam for the periods in the testbench file to 58 | # [63:0] from time 59 | vlogan -sverilog \ 60 | ${XILINX}/verilog/src/glbl.v \ 61 | ../../../lcd_spi_clk.v \ 62 | ../../example_design/lcd_spi_clk_exdes.v \ 63 | ../lcd_spi_clk_tb.v 64 | 65 | # prepare the simulation 66 | vcs +vcs+lic+wait -debug lcd_spi_clk_tb glbl 67 | 68 | # run the simulation 69 | ./simv -ucli -i ucli_commands.key 70 | 71 | # launch the viewer 72 | dve -vpd vcdplus.vpd -session vcs_session.tcl 73 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.xdc: -------------------------------------------------------------------------------- 1 | # file: lcd_spi_clk.xdc 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system 52 | #---------------------------------------------------------------- 53 | create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] 54 | set_propagated_clock CLK_IN1 55 | set_input_jitter CLK_IN1 0.2 56 | 57 | 58 | # Derived clock periods. These are commented out because they are 59 | # automatically propogated by the tools 60 | # However, if you'd like to use them for module level testing, you 61 | # can copy them into your module level timing checks 62 | #----------------------------------------------------------------- 63 | 64 | #----------------------------------------------------------------- 65 | 66 | #----------------------------------------------------------------- 67 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/simulation/timing/simulate_vcs.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # file: simulate_vcs.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # remove old files 52 | rm -rf simv* csrc DVEfiles AN.DB 53 | 54 | # compile all of the files 55 | # Note that -sverilog is not strictly required- You can 56 | # remove the -sverilog if you change the type of the 57 | # localparam for the periods in the testbench file to 58 | # [63:0] from time 59 | vlogan -sverilog \ 60 | lcd_spi_clk_tb.v \ 61 | ../../implement/results/routed.v 62 | 63 | 64 | # prepare the simulation 65 | vcs -sdf max:lcd_spi_clk_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ 66 | +libext+.v -debug lcd_spi_clk_tb.v ../../implement/results/routed.v 67 | 68 | # run the simulation 69 | ./simv -ucli -i ucli_commands.key 70 | 71 | # launch the viewer 72 | #dve -vpd vcdplus.vpd -session vcs_session.tcl 73 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/example_design/lcd_spi_clk_exdes.xdc: -------------------------------------------------------------------------------- 1 | # file: lcd_spi_clk_exdes.xdc 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system 52 | #---------------------------------------------------------------- 53 | create_clock -name CLK_IN1 -period 20.0 [get_ports CLK_IN1] 54 | set_propagated_clock CLK_IN1 55 | set_input_jitter CLK_IN1 0.2 56 | 57 | # FALSE PATH constraint added on COUNTER_RESET 58 | set_false_path -from [get_ports "COUNTER_RESET"] 59 | 60 | # Derived clock periods. These are commented out because they are 61 | # automatically propogated by the tools 62 | # However, if you'd like to use them for module level testing, you 63 | # can copy them into your module level timing checks 64 | #----------------------------------------------------------------- 65 | 66 | #----------------------------------------------------------------- 67 | 68 | #----------------------------------------------------------------- 69 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/planAhead_ise.tcl: -------------------------------------------------------------------------------- 1 | # file: planAhead_ise.tcl 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | set projDir [file dirname [info script]] 51 | set projName lcd_spi_clk 52 | set topName lcd_spi_clk_exdes 53 | set device xc6slx9tqg144-2 54 | 55 | create_project $projName $projDir/results/$projName -part $device 56 | 57 | set_property design_mode RTL [get_filesets sources_1] 58 | 59 | ## Source files 60 | #set verilogSources [glob $srcDir/*.v] 61 | import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/lcd_spi_clk_exdes.v 62 | import_files -fileset [get_filesets sources_1] -force -norecurse ../../../lcd_spi_clk.v 63 | 64 | 65 | #UCF file 66 | import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/lcd_spi_clk_exdes.ucf 67 | 68 | set_property top $topName [get_property srcset [current_run]] 69 | 70 | launch_runs -runs synth_1 71 | wait_on_run synth_1 72 | 73 | set_property add_step Bitgen [get_runs impl_1] 74 | launch_runs -runs impl_1 75 | wait_on_run impl_1 76 | 77 | 78 | 79 | -------------------------------------------------------------------------------- /src/mmap_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:29:36 10/21/2018 7 | // Design Name: 8 | // Module Name: mmap_interface_tb 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mmap_interface_tb( 22 | ); 23 | 24 | reg clk; 25 | reg rst; 26 | 27 | wire [7:0] tx_data; 28 | wire new_tx_data; 29 | reg tx_busy; 30 | reg [7:0] rx_data; 31 | reg new_rx_data; 32 | 33 | wire m_new_cmd; 34 | wire m_write; 35 | wire [5:0] m_cmd; 36 | wire [31:0] m_address; 37 | reg [31:0] s_data; 38 | reg s_drdy; 39 | 40 | mmap_protocol DUT ( 41 | .clk(clk), 42 | .rst(rst), 43 | .tx_data(tx_data), 44 | .new_tx_data(new_tx_data), 45 | .tx_busy(tx_busy), 46 | .rx_data(rx_data), 47 | .new_rx_data(new_rx_data), 48 | .m_new_cmd(m_new_cmd), 49 | .m_cmd(m_cmd), 50 | .m_write(m_write), 51 | .m_address(m_address), 52 | .s_data(s_data), 53 | .s_drdy(s_drdy) 54 | ); 55 | 56 | // wait by delay for clocks rather than manually run them. 57 | initial begin 58 | clk = 0; 59 | forever #10 clk = ~clk; 60 | end 61 | 62 | initial begin 63 | rst = 1'b1; 64 | repeat(6) @(posedge clk); 65 | rst = 1'b0; 66 | repeat(2) @(posedge clk); 67 | // command byte 68 | new_rx_data = 1'b1; 69 | rx_data = 8'b11000000; 70 | @(posedge clk); 71 | // "packet count" 16bit. 72 | rx_data = 8'd0; 73 | repeat(2) @(posedge clk); 74 | // "address" bytes. hold open for four clocks. 75 | rx_data = 8'b00000001; 76 | repeat(4) @(posedge clk); 77 | // "data" bytes. hold for another four clocks to load 78 | rx_data = 8'b01111111; 79 | repeat(4) @(posedge clk); 80 | // command should be parsed by now. 81 | new_rx_data = 1'b0; 82 | rx_data = 8'd0; 83 | repeat(8) @(posedge clk); 84 | // NEXT: issue a read command 85 | new_rx_data = 1'b1; 86 | rx_data = 8'b00000001; 87 | @(posedge clk); 88 | // packet count 16bit 89 | rx_data = 8'b00000000; 90 | repeat(2) @(posedge clk); 91 | // "address" bytes. four clocks to fill 92 | rx_data = 8'b00010000; 93 | repeat(4) @(posedge clk); 94 | // m_new_cmd should be high 95 | // m_write should be low. 96 | // m_address should be full 97 | new_rx_data = 1'b0; 98 | @(posedge clk); 99 | @(posedge clk); 100 | //new_rx_data = 1'b1; 101 | // reads request s_drdy and s_data to be set. 102 | s_data = {16{2'b10}}; 103 | s_drdy = 1'b1; 104 | tx_busy = 1'b0; 105 | @(posedge clk); 106 | s_drdy = 1'b0; 107 | // during next repetitions, tx_data, new_tx_data, etc should be flipped 108 | repeat(25) @(posedge clk) 109 | #5000 110 | $finish; 111 | end 112 | 113 | initial begin 114 | #500000000 115 | $finish; 116 | end 117 | endmodule 118 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/planAhead_rdn.tcl: -------------------------------------------------------------------------------- 1 | # file : planAhead_rdn.tcl 2 | # 3 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | set device xc6slx9tqg144-2 51 | set projName lcd_spi_clk 52 | set design lcd_spi_clk 53 | set projDir [file dirname [info script]] 54 | create_project $projName $projDir/results/$projName -part $device -force 55 | set_property design_mode RTL [current_fileset -srcset] 56 | set top_module lcd_spi_clk_exdes 57 | set_property top lcd_spi_clk_exdes [get_property srcset [current_run]] 58 | add_files -norecurse {../../../lcd_spi_clk.v} 59 | add_files -norecurse {../../example_design/lcd_spi_clk_exdes.v} 60 | import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/lcd_spi_clk_exdes.xdc} 61 | synth_design 62 | opt_design 63 | place_design 64 | route_design 65 | write_sdf -rename_top_module lcd_spi_clk_exdes -file routed.sdf 66 | write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module lcd_spi_clk_exdes -file routed.v 67 | report_timing -nworst 30 -path_type full -file routed.twr 68 | report_drc -file report.drc 69 | write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit 70 | -------------------------------------------------------------------------------- /src/simple_dual_ram.v: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | 3 | The MIT License (MIT) 4 | 5 | Copyright (c) 2015 Embedded Micro 6 | 7 | Permission is hereby granted, free of charge, to any person obtaining a copy 8 | of this software and associated documentation files (the "Software"), to deal 9 | in the Software without restriction, including without limitation the rights 10 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | copies of the Software, and to permit persons to whom the Software is 12 | furnished to do so, subject to the following conditions: 13 | 14 | The above copyright notice and this permission notice shall be included in 15 | all copies or substantial portions of the Software. 16 | 17 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 | THE SOFTWARE. 24 | 25 | ***************************************************************************** 26 | 27 | This module is a simple dual port RAM. This RAM is implemented in such a 28 | way that Xilinx's tools will recognize it as a RAM and implement large 29 | instances in block RAM instead of flip-flops. 30 | 31 | The parameter SIZE is used to specify the word size. That is the size of 32 | each entry in the RAM. 33 | 34 | The parameter DEPTH is used to specify how many entries are in the RAM. 35 | 36 | read_data outputs the value of the entry pointed to by raddr in the previous 37 | clock cycle. That means to read address 10, you would set address to be 10 38 | and wait one cycle for its value to show up. The RAM is always reading whatever 39 | address is. If you don't need to read, just ignore this value. 40 | 41 | To write, set write_en to 1, write_data to the value to write, and waddr to 42 | the address you want to write. 43 | 44 | You should avoid reading and writing to the same address simultaneously. 45 | */ 46 | 47 | module simple_dual_ram #( 48 | parameter SIZE = 32, // size of each entry 49 | parameter DEPTH = 320 // number of entries 50 | )( 51 | // write interface 52 | input wclk, // write clock 53 | input [$clog2(DEPTH)-1:0] waddr, // write address 54 | input [SIZE-1:0] write_data, // write data 55 | input write_en, // write enable (1 = write) 56 | 57 | // read interface 58 | input rclk, // read clock 59 | input [$clog2(DEPTH)-1:0] raddr, // read address 60 | output reg [SIZE-1:0] read_data // read data 61 | ); 62 | 63 | reg [SIZE-1:0] mem [DEPTH-1:0]; // memory array 64 | 65 | // write clock domain 66 | always @(posedge wclk) begin 67 | if (write_en) // if write enable 68 | mem[waddr] <= write_data; // write memory 69 | end 70 | 71 | // read clock domain 72 | always @(posedge rclk) begin 73 | read_data <= mem[raddr]; // read memory 74 | end 75 | 76 | endmodule 77 | -------------------------------------------------------------------------------- /src/serial_tx.v: -------------------------------------------------------------------------------- 1 | // from embedded micro base project 2 | module serial_tx #( 3 | parameter CLK_PER_BIT = 50 4 | )( 5 | input clk, 6 | input rst, 7 | output tx, 8 | input block, 9 | output busy, 10 | input [7:0] data, 11 | input new_data 12 | ); 13 | 14 | // clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value 15 | parameter CTR_SIZE = $clog2(CLK_PER_BIT); 16 | 17 | localparam STATE_SIZE = 2; 18 | localparam IDLE = 2'd0, 19 | START_BIT = 2'd1, 20 | DATA = 2'd2, 21 | STOP_BIT = 2'd3; 22 | 23 | reg [CTR_SIZE-1:0] ctr_d, ctr_q; 24 | reg [2:0] bit_ctr_d, bit_ctr_q; 25 | reg [7:0] data_d, data_q; 26 | reg [STATE_SIZE-1:0] state_d, state_q = IDLE; 27 | reg tx_d, tx_q; 28 | reg busy_d, busy_q; 29 | reg block_d, block_q; 30 | 31 | assign tx = tx_q; 32 | assign busy = busy_q; 33 | 34 | always @(*) begin 35 | block_d = block; 36 | ctr_d = ctr_q; 37 | bit_ctr_d = bit_ctr_q; 38 | data_d = data_q; 39 | state_d = state_q; 40 | busy_d = busy_q; 41 | 42 | case (state_q) 43 | IDLE: begin 44 | if (block_q) begin 45 | busy_d = 1'b1; 46 | tx_d = 1'b1; 47 | end else begin 48 | busy_d = 1'b0; 49 | tx_d = 1'b1; 50 | bit_ctr_d = 3'b0; 51 | ctr_d = 1'b0; 52 | if (new_data) begin 53 | data_d = data; 54 | state_d = START_BIT; 55 | busy_d = 1'b1; 56 | end 57 | end 58 | end 59 | START_BIT: begin 60 | busy_d = 1'b1; 61 | ctr_d = ctr_q + 1'b1; 62 | tx_d = 1'b0; 63 | if (ctr_q == CLK_PER_BIT - 1) begin 64 | ctr_d = 1'b0; 65 | state_d = DATA; 66 | end 67 | end 68 | DATA: begin 69 | busy_d = 1'b1; 70 | tx_d = data_q[bit_ctr_q]; 71 | ctr_d = ctr_q + 1'b1; 72 | if (ctr_q == CLK_PER_BIT - 1) begin 73 | ctr_d = 1'b0; 74 | bit_ctr_d = bit_ctr_q + 1'b1; 75 | if (bit_ctr_q == 7) begin 76 | state_d = STOP_BIT; 77 | end 78 | end 79 | end 80 | STOP_BIT: begin 81 | busy_d = 1'b1; 82 | tx_d = 1'b1; 83 | ctr_d = ctr_q + 1'b1; 84 | if (ctr_q == CLK_PER_BIT - 1) begin 85 | state_d = IDLE; 86 | end 87 | end 88 | default: begin 89 | state_d = IDLE; 90 | end 91 | endcase 92 | end 93 | 94 | always @(posedge clk) begin 95 | if (rst) begin 96 | state_q <= IDLE; 97 | tx_q <= 1'b1; 98 | end else begin 99 | state_q <= state_d; 100 | tx_q <= tx_d; 101 | end 102 | 103 | block_q <= block_d; 104 | data_q <= data_d; 105 | bit_ctr_q <= bit_ctr_d; 106 | ctr_q <= ctr_d; 107 | busy_q <= busy_d; 108 | end 109 | 110 | endmodule 111 | -------------------------------------------------------------------------------- /ipcore_dir/div_8_dot_8_nodsp_xmdf.tcl: -------------------------------------------------------------------------------- 1 | # The package naming convention is _xmdf 2 | package provide div_8_dot_8_nodsp_xmdf 1.0 3 | 4 | # This includes some utilities that support common XMDF operations 5 | package require utilities_xmdf 6 | 7 | # Define a namespace for this package. The name of the name space 8 | # is _xmdf 9 | namespace eval ::div_8_dot_8_nodsp_xmdf { 10 | # Use this to define any statics 11 | } 12 | 13 | # Function called by client to rebuild the params and port arrays 14 | # Optional when the use context does not require the param or ports 15 | # arrays to be available. 16 | proc ::div_8_dot_8_nodsp_xmdf::xmdfInit { instance } { 17 | # Variable containing name of library into which module is compiled 18 | # Recommendation: 19 | # Required 20 | utilities_xmdf::xmdfSetData $instance Module Attributes Name div_8_dot_8_nodsp 21 | } 22 | # ::div_8_dot_8_nodsp_xmdf::xmdfInit 23 | 24 | # Function called by client to fill in all the xmdf* data variables 25 | # based on the current settings of the parameters 26 | proc ::div_8_dot_8_nodsp_xmdf::xmdfApplyParams { instance } { 27 | 28 | set fcount 0 29 | # Array containing libraries that are assumed to exist 30 | # Examples include unisim and xilinxcorelib 31 | # Optional 32 | # In this example, we assume that the unisim library will 33 | # be available to the simulation and synthesis tool 34 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library 35 | utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim 36 | incr fcount 37 | 38 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path demo_tb/tb_div_8_dot_8_nodsp.vhd 39 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore 40 | incr fcount 41 | 42 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp/doc/div_gen_v4_0_readme.txt 43 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore 44 | incr fcount 45 | 46 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp/doc/div_gen_v4_0_vinfo.html 47 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore 48 | incr fcount 49 | 50 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp/doc/ds819_div_gen.pdf 51 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore 52 | incr fcount 53 | 54 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.asy 55 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy 56 | incr fcount 57 | 58 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.ngc 59 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc 60 | incr fcount 61 | 62 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.v 63 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog 64 | incr fcount 65 | 66 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.veo 67 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template 68 | incr fcount 69 | 70 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp.xco 71 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip 72 | incr fcount 73 | 74 | utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_8_dot_8_nodsp_xmdf.tcl 75 | utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView 76 | incr fcount 77 | 78 | utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module div_8_dot_8_nodsp 79 | incr fcount 80 | 81 | } 82 | 83 | # ::gen_comp_name_xmdf::xmdfApplyParams 84 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/implement.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # file: implement.sh 3 | # 4 | # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | #----------------------------------------------------------------------------- 52 | # Script to synthesize and implement the RTL provided for the clocking wizard 53 | #----------------------------------------------------------------------------- 54 | 55 | # Clean up the results directory 56 | rm -rf results 57 | mkdir results 58 | 59 | # Copy unisim_comp.v file to results directory 60 | cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ 61 | 62 | # Synthesize the Verilog Wrapper Files 63 | echo 'Synthesizing Clocking Wizard design with XST' 64 | xst -ifn xst.scr 65 | mv lcd_spi_clk_exdes.ngc results/ 66 | 67 | # Copy the constraints files generated by Coregen 68 | echo 'Copying files from constraints directory to results directory' 69 | cp ../example_design/lcd_spi_clk_exdes.ucf results/ 70 | 71 | cd results 72 | 73 | echo 'Running ngdbuild' 74 | ngdbuild -uc lcd_spi_clk_exdes.ucf lcd_spi_clk_exdes 75 | 76 | echo 'Running map' 77 | map -timing lcd_spi_clk_exdes -o mapped.ncd 78 | 79 | echo 'Running par' 80 | par -w mapped.ncd routed mapped.pcf 81 | 82 | echo 'Running trce' 83 | trce -e 10 routed -o routed mapped.pcf 84 | 85 | echo 'Running design through bitgen' 86 | bitgen -w routed 87 | 88 | echo 'Running netgen to create gate level model for the clocking wizard example design' 89 | netgen -ofmt verilog -sim -sdf_anno false -tm lcd_spi_clk_exdes -w routed.ncd routed.v 90 | 91 | cd .. 92 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk.veo: -------------------------------------------------------------------------------- 1 | // 2 | // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //---------------------------------------------------------------------------- 49 | // User entered comments 50 | //---------------------------------------------------------------------------- 51 | // None 52 | // 53 | //---------------------------------------------------------------------------- 54 | // "Output Output Phase Duty Pk-to-Pk Phase" 55 | // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" 56 | //---------------------------------------------------------------------------- 57 | // CLK_OUT1___250.000______0.000______50.0______280.000____150.000 58 | // CLK_OUT2____50.000______0.000______50.0______200.000____150.000 59 | // 60 | //---------------------------------------------------------------------------- 61 | // "Input Clock Freq (MHz) Input Jitter (UI)" 62 | //---------------------------------------------------------------------------- 63 | // __primary__________50.000____________0.010 64 | 65 | // The following must be inserted into your Verilog file for this 66 | // core to be instantiated. Change the instance name and port connections 67 | // (in parentheses) to your own signal names. 68 | 69 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 70 | 71 | lcd_spi_clk instance_name 72 | (// Clock in ports 73 | .clk_in(clk_in), // IN 74 | // Clock out ports 75 | .clk_fout(clk_fout), // OUT 76 | .clk_nout(clk_nout)); // OUT 77 | // INST_TAG_END ------ End INSTANTIATION Template --------- 78 | -------------------------------------------------------------------------------- /ipcore_dir/lcd_spi_clk/implement/implement.bat: -------------------------------------------------------------------------------- 1 | REM file: implement.bat 2 | REM 3 | REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | REM 5 | REM This file contains confidential and proprietary information 6 | REM of Xilinx, Inc. and is protected under U.S. and 7 | REM international copyright and other intellectual property 8 | REM laws. 9 | REM 10 | REM DISCLAIMER 11 | REM This disclaimer is not a license and does not grant any 12 | REM rights to the materials distributed herewith. Except as 13 | REM otherwise provided in a valid license issued to you by 14 | REM Xilinx, and to the maximum extent permitted by applicable 15 | REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | REM (2) Xilinx shall not be liable (whether in contract or tort, 21 | REM including negligence, or under any other theory of 22 | REM liability) for any loss or damage of any kind or nature 23 | REM related to, arising under or in connection with these 24 | REM materials, including for any direct, or any indirect, 25 | REM special, incidental, or consequential loss or damage 26 | REM (including loss of data, profits, goodwill, or any type of 27 | REM loss or damage suffered as a result of any action brought 28 | REM by a third party) even if such damage or loss was 29 | REM reasonably foreseeable or Xilinx had been advised of the 30 | REM possibility of the same. 31 | REM 32 | REM CRITICAL APPLICATIONS 33 | REM Xilinx products are not designed or intended to be fail- 34 | REM safe, or for use in any application requiring fail-safe 35 | REM performance, such as life-support or safety devices or 36 | REM systems, Class III medical devices, nuclear facilities, 37 | REM applications related to the deployment of airbags, or any 38 | REM other applications that could lead to death, personal 39 | REM injury, or severe property or environmental damage 40 | REM (individually and collectively, "Critical 41 | REM Applications"). Customer assumes the sole risk and 42 | REM liability of any use of Xilinx products in Critical 43 | REM Applications, subject only to applicable laws and 44 | REM regulations governing limitations on product liability. 45 | REM 46 | REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | REM PART OF THIS FILE AT ALL TIMES. 48 | REM 49 | 50 | REM ----------------------------------------------------------------------------- 51 | REM Script to synthesize and implement the RTL provided for the clocking wizard 52 | REM ----------------------------------------------------------------------------- 53 | 54 | REM Clean up the results directory 55 | rmdir /S /Q results 56 | mkdir results 57 | 58 | REM Copy unisim_comp.v file to results directory 59 | copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ 60 | 61 | REM Synthesize the Verilog Wrapper Files 62 | echo 'Synthesizing Clocking Wizard design with XST' 63 | xst -ifn xst.scr 64 | move lcd_spi_clk_exdes.ngc results\ 65 | 66 | REM Copy the constraints files generated by Coregen 67 | echo 'Copying files from constraints directory to results directory' 68 | copy ..\example_design\lcd_spi_clk_exdes.ucf results\ 69 | 70 | cd results 71 | 72 | echo 'Running ngdbuild' 73 | ngdbuild -uc lcd_spi_clk_exdes.ucf lcd_spi_clk_exdes 74 | 75 | echo 'Running map' 76 | map -timing -pr b lcd_spi_clk_exdes -o mapped.ncd 77 | 78 | echo 'Running par' 79 | par -w mapped.ncd routed mapped.pcf 80 | 81 | echo 'Running trce' 82 | trce -e 10 routed -o routed mapped.pcf 83 | 84 | echo 'Running design through bitgen' 85 | bitgen -w routed 86 | 87 | echo 'Running netgen to create gate level model for the clocking wizard example design' 88 | netgen -ofmt verilog -sim -sdf_anno false -tm lcd_spi_clk_exdes -w routed.ncd routed.v 89 | cd .. 90 | 91 | -------------------------------------------------------------------------------- /src/floordist.rom: -------------------------------------------------------------------------------- 1 | floor_dist[0] = 16'h78_00; 2 | floor_dist[1] = 16'h3c_00; 3 | floor_dist[2] = 16'h28_00; 4 | floor_dist[3] = 16'h1e_00; 5 | floor_dist[4] = 16'h18_00; 6 | floor_dist[5] = 16'h14_00; 7 | floor_dist[6] = 16'h11_24; 8 | floor_dist[7] = 16'h0f_00; 9 | floor_dist[8] = 16'h0d_55; 10 | floor_dist[9] = 16'h0c_00; 11 | floor_dist[10] = 16'h0a_e8; 12 | floor_dist[11] = 16'h0a_00; 13 | floor_dist[12] = 16'h09_3b; 14 | floor_dist[13] = 16'h08_92; 15 | floor_dist[14] = 16'h08_00; 16 | floor_dist[15] = 16'h07_80; 17 | floor_dist[16] = 16'h07_0f; 18 | floor_dist[17] = 16'h06_aa; 19 | floor_dist[18] = 16'h06_50; 20 | floor_dist[19] = 16'h06_00; 21 | floor_dist[20] = 16'h05_b6; 22 | floor_dist[21] = 16'h05_74; 23 | floor_dist[22] = 16'h05_37; 24 | floor_dist[23] = 16'h05_00; 25 | floor_dist[24] = 16'h04_cc; 26 | floor_dist[25] = 16'h04_9d; 27 | floor_dist[26] = 16'h04_71; 28 | floor_dist[27] = 16'h04_49; 29 | floor_dist[28] = 16'h04_23; 30 | floor_dist[29] = 16'h04_00; 31 | floor_dist[30] = 16'h03_de; 32 | floor_dist[31] = 16'h03_c0; 33 | floor_dist[32] = 16'h03_a2; 34 | floor_dist[33] = 16'h03_87; 35 | floor_dist[34] = 16'h03_6d; 36 | floor_dist[35] = 16'h03_55; 37 | floor_dist[36] = 16'h03_3e; 38 | floor_dist[37] = 16'h03_28; 39 | floor_dist[38] = 16'h03_13; 40 | floor_dist[39] = 16'h03_00; 41 | floor_dist[40] = 16'h02_ed; 42 | floor_dist[41] = 16'h02_db; 43 | floor_dist[42] = 16'h02_ca; 44 | floor_dist[43] = 16'h02_ba; 45 | floor_dist[44] = 16'h02_aa; 46 | floor_dist[45] = 16'h02_9b; 47 | floor_dist[46] = 16'h02_8d; 48 | floor_dist[47] = 16'h02_80; 49 | floor_dist[48] = 16'h02_72; 50 | floor_dist[49] = 16'h02_66; 51 | floor_dist[50] = 16'h02_5a; 52 | floor_dist[51] = 16'h02_4e; 53 | floor_dist[52] = 16'h02_43; 54 | floor_dist[53] = 16'h02_38; 55 | floor_dist[54] = 16'h02_2e; 56 | floor_dist[55] = 16'h02_24; 57 | floor_dist[56] = 16'h02_1a; 58 | floor_dist[57] = 16'h02_11; 59 | floor_dist[58] = 16'h02_08; 60 | floor_dist[59] = 16'h02_00; 61 | floor_dist[60] = 16'h01_f7; 62 | floor_dist[61] = 16'h01_ef; 63 | floor_dist[62] = 16'h01_e7; 64 | floor_dist[63] = 16'h01_e0; 65 | floor_dist[64] = 16'h01_d8; 66 | floor_dist[65] = 16'h01_d1; 67 | floor_dist[66] = 16'h01_ca; 68 | floor_dist[67] = 16'h01_c3; 69 | floor_dist[68] = 16'h01_bd; 70 | floor_dist[69] = 16'h01_b6; 71 | floor_dist[70] = 16'h01_b0; 72 | floor_dist[71] = 16'h01_aa; 73 | floor_dist[72] = 16'h01_a4; 74 | floor_dist[73] = 16'h01_9f; 75 | floor_dist[74] = 16'h01_99; 76 | floor_dist[75] = 16'h01_94; 77 | floor_dist[76] = 16'h01_8e; 78 | floor_dist[77] = 16'h01_89; 79 | floor_dist[78] = 16'h01_84; 80 | floor_dist[79] = 16'h01_80; 81 | floor_dist[80] = 16'h01_7b; 82 | floor_dist[81] = 16'h01_76; 83 | floor_dist[82] = 16'h01_72; 84 | floor_dist[83] = 16'h01_6d; 85 | floor_dist[84] = 16'h01_69; 86 | floor_dist[85] = 16'h01_65; 87 | floor_dist[86] = 16'h01_61; 88 | floor_dist[87] = 16'h01_5d; 89 | floor_dist[88] = 16'h01_59; 90 | floor_dist[89] = 16'h01_55; 91 | floor_dist[90] = 16'h01_51; 92 | floor_dist[91] = 16'h01_4d; 93 | floor_dist[92] = 16'h01_4a; 94 | floor_dist[93] = 16'h01_46; 95 | floor_dist[94] = 16'h01_43; 96 | floor_dist[95] = 16'h01_40; 97 | floor_dist[96] = 16'h01_3c; 98 | floor_dist[97] = 16'h01_39; 99 | floor_dist[98] = 16'h01_36; 100 | floor_dist[99] = 16'h01_33; 101 | floor_dist[100] = 16'h01_30; 102 | floor_dist[101] = 16'h01_2d; 103 | floor_dist[102] = 16'h01_2a; 104 | floor_dist[103] = 16'h01_27; 105 | floor_dist[104] = 16'h01_24; 106 | floor_dist[105] = 16'h01_21; 107 | floor_dist[106] = 16'h01_1f; 108 | floor_dist[107] = 16'h01_1c; 109 | floor_dist[108] = 16'h01_19; 110 | floor_dist[109] = 16'h01_17; 111 | floor_dist[110] = 16'h01_14; 112 | floor_dist[111] = 16'h01_12; 113 | floor_dist[112] = 16'h01_0f; 114 | floor_dist[113] = 16'h01_0d; 115 | floor_dist[114] = 16'h01_0b; 116 | floor_dist[115] = 16'h01_08; 117 | floor_dist[116] = 16'h01_06; 118 | floor_dist[117] = 16'h01_04; 119 | floor_dist[118] = 16'h01_02; 120 | floor_dist[119] = 16'h01_00; 121 | -------------------------------------------------------------------------------- /src/sprite_scanline.v: -------------------------------------------------------------------------------- 1 | // module for culling and sorting sprites to be displayed on a particular 2 | // scanline. 3 | 4 | // This uses the pre-transformed sprite data to determine if a sprite scanline 5 | // exists on the current line or not. 6 | // It caches data for up to N sprites, which is then read by the line writer 7 | // during the display routine. 8 | // This module gets kicked off while the walls are being drawn. 9 | 10 | // Note how this isn't generally optimized: this has to scan every possible 11 | // sprite once per scanline, then sort, which is only consistently faster than 12 | // the wall draw if there're < 128 sprites in a level. 13 | // 14 | // However, this is fine for this implementation since each sprite cull test 15 | // can be done within a single cycle! 16 | // A better one, and more closely matching the wolf3D engine, would have the 17 | // sprite pre-transform sort sprites into map squares. The raycaster then logs 18 | // which tiles it sees for each ray, which is used to more quickly cull 19 | // sprites. It can also be used to improve ordering since map tiles can be 20 | // examined from near-to-far, so you only have to sort sprites within 21 | // a particular tile. 22 | 23 | module sprite_scanline ( 24 | input clk, 25 | input rst, 26 | 27 | input start, 28 | output reg done, 29 | 30 | input [8:0] x, // camera X position 31 | input [15:0] wall_z, // z buffer of casted wall 32 | 33 | // transformed sprite metadata 34 | output reg [6:0] stmeta_raddr, 35 | input [119:0] stmeta_read_data, 36 | 37 | // hook sorted registers into line writer 38 | input [2:0] sprite_addr, 39 | output reg [119:0] sprite_meta, 40 | output reg [2:0] sprite_count 41 | ); 42 | 43 | localparam WIDTH = 320; 44 | 45 | localparam IDLE = 0, 46 | CULL_FETCH = 1, 47 | CULL = 2; 48 | reg [3:0] state_d, state_q; 49 | 50 | reg [6:0] count_d, count_q; 51 | reg [2:0] scount_d, scount_q; 52 | // add an extra bit so we can do signed comparisons. 53 | reg signed [15:0] camera_x_d, camera_x_q; 54 | 55 | // FIXME: use pointers instead and serve from stmeta_raddr. 56 | reg [119:0] sprites [2:0]; 57 | 58 | reg save_meta; 59 | 60 | always @(*) begin 61 | state_d = state_q; 62 | count_d = count_q; 63 | stmeta_raddr = count_q; 64 | camera_x_d = camera_x_q; 65 | save_meta = 1'b0; 66 | sprite_count = scount_q; 67 | scount_d = scount_q; 68 | done = 1'b0; 69 | 70 | case (state_q) 71 | IDLE: begin 72 | count_d = 0; 73 | if (start) begin 74 | state_d = CULL_FETCH; 75 | camera_x_d = x - 1'b1; 76 | scount_d = 3'd0; 77 | end 78 | end 79 | CULL_FETCH: begin 80 | // load the metadata from RAM 81 | // can remove this step once tested/understood better. 82 | state_d = CULL; 83 | end 84 | CULL: begin 85 | // First test is the wall Z depth cull. 86 | // Then, if camera X is within sprite X draw boundaries 87 | if ($signed(stmeta_read_data[111:96]) < wall_z 88 | && $signed(stmeta_read_data[111:96]) > 0 89 | && $signed(stmeta_read_data[31:16]) <= camera_x_q 90 | && $signed(stmeta_read_data[15:0]) >= camera_x_q 91 | ) begin 92 | // save the sprite info if it's visible 93 | save_meta = 1'b1; 94 | scount_d = scount_q + 1'b1; 95 | end 96 | count_d = count_q + 1'b1; 97 | if (count_q == 127 || scount_d == 8) begin 98 | done = 1'b1; 99 | state_d = IDLE; 100 | end else begin 101 | state_d = CULL_FETCH; 102 | end 103 | end 104 | endcase 105 | end 106 | 107 | always @(posedge clk) begin 108 | if (rst) begin 109 | state_q <= IDLE; 110 | end else begin 111 | state_q <= state_d; 112 | end 113 | 114 | count_q <= count_d; 115 | camera_x_q <= camera_x_d; 116 | scount_q <= scount_d; 117 | if (save_meta) begin 118 | sprites[count_q] <= stmeta_read_data; 119 | end 120 | sprite_meta <= sprites[sprite_addr]; 121 | end 122 | 123 | endmodule 124 | --------------------------------------------------------------------------------