├── image ├── image.bin ├── image.rom └── kproc.sys ├── bootloader ├── kproc.sys ├── bootloader.bin ├── bootloader.rom └── initcode │ ├── init.bin │ ├── bitmap.raw │ ├── backlight.bin │ ├── lcd_clear.bin │ └── init.scr ├── datasheets ├── MP1470.pdf ├── UM6K1N.pdf ├── BL5372_V1.2_cn.pdf ├── DS-HY461x_EN_V3.0.pdf ├── IT985x_V0.9.1_20180111.pdf ├── ILI9806E_IDT_V092_20130806.pdf ├── MTW38266G系列-智城云Wi-Fi模块硬件规格书V3.0.pdf └── gd5f1gq4xbxig_rev3.0_20190505.pdf ├── doc └── images │ └── pcb-front.jpg ├── tools └── dumpscript │ ├── CMakeLists.txt │ └── main.c ├── .gitignore ├── LICENSE └── README.md /image/image.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/doyaGu/C0501Q_HWJL01/HEAD/image/image.bin -------------------------------------------------------------------------------- /image/image.rom: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/doyaGu/C0501Q_HWJL01/HEAD/datasheets/IT985x_V0.9.1_20180111.pdf -------------------------------------------------------------------------------- /tools/dumpscript/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | project(dumpscript C) 2 | 3 | set(CMAKE_C_STANDARD 99) 4 | 5 | add_executable(dumpscript main.c) -------------------------------------------------------------------------------- /datasheets/ILI9806E_IDT_V092_20130806.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/doyaGu/C0501Q_HWJL01/HEAD/datasheets/ILI9806E_IDT_V092_20130806.pdf -------------------------------------------------------------------------------- /datasheets/MTW38266G系列-智城云Wi-Fi模块硬件规格书V3.0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/doyaGu/C0501Q_HWJL01/HEAD/datasheets/MTW38266G系列-智城云Wi-Fi模块硬件规格书V3.0.pdf -------------------------------------------------------------------------------- /datasheets/gd5f1gq4xbxig_rev3.0_20190505.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/doyaGu/C0501Q_HWJL01/HEAD/datasheets/gd5f1gq4xbxig_rev3.0_20190505.pdf -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | 54 | # SDK build files 55 | sdk/build/linux/* 56 | sdk/build/openrtos/* 57 | sdk/build/win32/* 58 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 papuras 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # C0501Q_HWJL01 2 | The related resources for this device. 3 | 4 | 5 | 6 | ## Photo 7 | 8 | ![PCB Front](https://raw.githubusercontent.com/doyaGu/C0501Q_HWJL01/main/doc/images/pcb-front.jpg) 9 | 10 | 11 | ## Hardware Spec 12 | 13 | ### POWER & USB 14 | 15 | | Header Pinout | Pinout | Pin Number | 16 | | :-----------: | :----: | :--------: | 17 | | D+ | DP0 | PIN122 | 18 | | D- | DM0 | PIN123 | 19 | | GND | GND | - | 20 | | RX | GPIO23 | PIN31 | 21 | | TX | GPIO22 | PIN30 | 22 | | VCC | VCC | - | 23 | 24 | 25 | 26 | ### SPI & Debug 27 | 28 | | Header Pinout | Debugger Pinout | Pinout | Pin Number | 29 | | :-----------: | :-------------: | :----: | :--------: | 30 | | CLK | TCK | GPIO0 | PIN6 | 31 | | CSN | TMS | GPIO1 | PIN7 | 32 | | MOSI | TDI | GPIO2 | PIN8 | 33 | | MISO | TDO | GPIO3 | PIN9 | 34 | | GND | GND | - | - | 35 | | DB_TX | RxD | GPIO4 | PIN10 | 36 | | 3V3 | VCC | - | - | 37 | | NC | NC | - | - | 38 | 39 | 40 | 41 | ### LCD: DX050H049 42 | 43 | | No. | LCM Pinout | Pinout | Pin Number | 44 | | :-----------: | :-----------: | :----: | :--------: | 45 | | 1 | LEDK | GND | - | 46 | | 2 | LEDA | 16V [Controlled by GPIO78] | PIN112 | 47 | | 3 | GND | GND | - | 48 | | 4 | VDD | 3V3 [Controlled by GPIO38] | PIN63 | 49 | | 5 | R7 | LD23 (GPIO39) | PIN65 | 50 | | 6 | R6 | LD22 (GPIO40) | PIN67 | 51 | | 7 | R5 | LD21 (GPIO41) | PIN68 | 52 | | 8 | R4 | LD20 (GPIO42) | PIN69 | 53 | | 9 | R3 | LD19 (GPIO43) | PIN70 | 54 | | 10 | R2 | LD18 (GPIO44) | PIN71 | 55 | | 11 | R1 | LD17 (GPIO45) | PIN72 | 56 | | 12 | R0 | LD16 (GPIO46) | PIN74 | 57 | | 13 | G7 | LD15 (GPIO47) | PIN75 | 58 | | 14 | G6 | LD14 (GPIO48) | PIN76 | 59 | | 15 | G5 | LD13 (GPIO49) | PIN77 | 60 | | 16 | G4 | LD12 (GPIO50) | PIN78 | 61 | | 17 | G3 | LD11 (GPIO51) | PIN79 | 62 | | 18 | G2 | LD10 (GPIO52) | PIN81 | 63 | | 19 | G1 | LD9 (GPIO53) | PIN82 | 64 | | 20 | G0 | LD8 (GPIO54) | PIN83 | 65 | | 21 | B7 | LD7 (GPIO55) | PIN84 | 66 | | 22 | B6 | LD6 (GPIO56) | PIN85 | 67 | | 23 | B5 | LD5 (GPIO57) | PIN86 | 68 | | 24 | B4 | LD4 (GPIO58) | PIN87 | 69 | | 25 | B3 | LD3 (GPIO59) | PIN88 | 70 | | 26 | B2 | LD2 (GPIO60) | PIN89 | 71 | | 27 | B1 | LD1 (GPIO61) | PIN90 | 72 | | 28 | B0 | LD0 (GPIO62) | PIN91 | 73 | | 29 | GND | GND | - | 74 | | 30 | DOTCLK | LDCLK (GPIO66) | PIN99 | 75 | | 31 | NC | NC | - | 76 | | 32 | HSYNC | LHSYNC (GPIO67) | PIN99 | 77 | | 33 | VSYNC | LVSYNC (GPIO68) | PIN100 | 78 | | 34 | DE | LDEN (GPIO65) | PIN96 | 79 | | 35 | NC? | NC? | - | 80 | | 36 | GND | GND | - | 81 | | 37 | RESET | GPIO64 | PIN95 | 82 | | 38 | SDA | GPIO69 | PIN94 | 83 | | 39 | SCL | GPIO70 | PIN62 | 84 | | 40 | CS | GPIO71 | PIN103 | 85 | 86 | 87 | 88 | ### CTP: HY4633 89 | 90 | | Header Pinout | Pinout | Pin Number | 91 | | :-----------: | :----: | :--------: | 92 | | IIC1_SDA | GPIO25 | PIN34 | 93 | | IIC1_SCL | GPIO26 | PIN35 | 94 | | INT | GPIO27 | PIN36 | 95 | | RST | GPIO28 | PIN37 | 96 | 97 | 98 | 99 | ### SPI-NAND: 5F1GQ4UBYIG 100 | 101 | | Header Pinout | Pinout | Pin Number | 102 | | :-----------: | :----: | :--------: | 103 | | SPI0_CS# | GPIO14 | PIN21 | 104 | | SPI0_DIN | GPIO18 | PIN25 | 105 | | SPI0_DOUT | GPIO19 | PIN26 | 106 | | SPI0_CLK | GPIO20 | PIN27 | 107 | 108 | 109 | 110 | ### WIFI: MTW38266G 111 | 112 | | Header Pinout | Pinout | Pin Number | 113 | | :-------: | :----: | :--------: | 114 | | GND | GND | - | 115 | | RST | NC | - | 116 | | DP/RX | DP1 | PIN125 | 117 | | DM/TX | DM1 | PIN126 | 118 | | VCC | VCC | - | 119 | 120 | 121 | 122 | ### RTC: BL5372 123 | 124 | | Header Pinout | Pinout | Pin Number | 125 | | :-----------: | :----: | :--------: | 126 | | IIC1_SDA | GPIO25 | PIN34 | 127 | | IIC1_SCL | GPIO26 | PIN35 | 128 | | INTRB | GPIO29 | PIN38 | 129 | 130 | -------------------------------------------------------------------------------- /tools/dumpscript/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | 7 | /* Reverse the bytes in a 32-bit value */ 8 | #define SWAP32(q) ((((q) >> 24) & 0xff) + (((q) >> 8) & 0xff00) + \ 9 | (((q) & 0xff00) << 8) + (((q) & 0xff) << 24)) 10 | 11 | #define MAX_LABEL 128 12 | #define MAX_OPERANDS 4 13 | #define MAX_FILENAME 2048 14 | #define MAX_CMD_SIZE 0x1000000 15 | 16 | static const char *PROGRAM_NAME = "dumpscript"; 17 | 18 | typedef enum ds_error { 19 | ERROR_NONE = 0, 20 | ERROR_UNKNOWN_OPCODE, 21 | ERROR_FILE_OPEN, 22 | ERROR_FILE_READ, 23 | ERROR_EOF, 24 | } ds_error_t; 25 | 26 | typedef enum opcode_type { 27 | OPCODE_BRANCH = 0, 28 | OPCODE_CONTROL, 29 | OPCODE_IO, 30 | } opcode_type_t; 31 | 32 | typedef enum operand_type { 33 | OPERAND_NONE = 0, 34 | OPERAND_ADDRESS, 35 | OPERAND_DATA, 36 | OPERAND_MASK, 37 | OPERAND_VAL, 38 | OPERAND_OFFSET, 39 | OPERAND_LENGTH, 40 | OPERAND_WIDTH, 41 | OPERAND_PITCH, 42 | } operand_type_t; 43 | 44 | typedef struct opcode { 45 | char *op; 46 | uint32_t hex; 47 | int operands; 48 | operand_type_t operand_types[MAX_OPERANDS]; 49 | opcode_type_t type; 50 | } opcode_t; 51 | 52 | typedef uint32_t operand_t; 53 | 54 | typedef struct cmd { 55 | int id; 56 | size_t offset; 57 | const opcode_t *opcode; 58 | operand_t operand[MAX_OPERANDS]; 59 | char label[MAX_LABEL]; 60 | char data_name[MAX_LABEL]; // only used by DATA 61 | uint8_t *data; // only used by DATA 62 | } cmd_t; 63 | 64 | static const opcode_t opcodes[] = { 65 | {"beq", 0XFFFFFFE0, 2, {OPERAND_VAL, OPERAND_OFFSET}, OPCODE_BRANCH}, 66 | {"bne", 0XFFFFFFE1, 2, {OPERAND_VAL, OPERAND_OFFSET}, OPCODE_BRANCH}, 67 | {"bgt", 0XFFFFFFE2, 2, {OPERAND_VAL, OPERAND_OFFSET}, OPCODE_BRANCH}, 68 | {"bgte", 0XFFFFFFE3, 2, {OPERAND_VAL, OPERAND_OFFSET}, OPCODE_BRANCH}, 69 | {"blt", 0XFFFFFFE4, 2, {OPERAND_VAL, OPERAND_OFFSET}, OPCODE_BRANCH}, 70 | {"blte", 0XFFFFFFE5, 2, {OPERAND_VAL, OPERAND_OFFSET}, OPCODE_BRANCH}, 71 | {"skip", 0XFFFFFFF7, 1, {OPERAND_OFFSET}, OPCODE_CONTROL}, 72 | {"read_mask", 0XFFFFFFF8, 2, {OPERAND_ADDRESS, OPERAND_MASK}, OPCODE_IO}, 73 | {"goto", 0XFFFFFFF9, 1, {OPERAND_ADDRESS}, OPCODE_CONTROL}, 74 | {"write_mask", 0XFFFFFFFA, 2, {OPERAND_ADDRESS, OPERAND_MASK}, OPCODE_IO}, 75 | {"call", 0XFFFFFFFB, 1, {OPERAND_ADDRESS}, OPCODE_CONTROL}, 76 | {"data_wait1", 0XFFFFFFFC, 2, {OPERAND_ADDRESS, OPERAND_MASK}, OPCODE_CONTROL}, 77 | {"data_wait0", 0XFFFFFFFD, 2, {OPERAND_ADDRESS, OPERAND_MASK}, OPCODE_CONTROL}, 78 | {"data", 0XFFFFFFFE, 4 /* Actually 5 */, {OPERAND_ADDRESS, OPERAND_LENGTH, OPERAND_WIDTH, OPERAND_PITCH}, OPCODE_IO}, 79 | {"wait", 0XFFFFFFFF, 1, {OPERAND_DATA}, OPCODE_CONTROL}, 80 | {"write", 0, /* No opcode */ 2, {OPERAND_DATA, OPERAND_DATA}, OPCODE_IO} 81 | }; 82 | 83 | static const int OPCODE_NUM = sizeof opcodes / sizeof(opcode_t); 84 | 85 | static inline bool is_cmd_data(cmd_t *cmd) { 86 | return cmd->opcode->hex == 0XFFFFFFFE; 87 | } 88 | 89 | typedef struct arguments { 90 | bool verbose; 91 | char infile[MAX_FILENAME]; 92 | char outfile[MAX_FILENAME]; 93 | } arguments_t; 94 | 95 | static struct ds_state { 96 | size_t offset; 97 | int id; 98 | ds_error_t error; 99 | } state = { 100 | .offset = 0, 101 | .id = 0, 102 | .error = ERROR_NONE 103 | }; 104 | 105 | static void usage() { 106 | fprintf(stderr, "Usage:\n\t%s [options] [infile] [outfile]\n", PROGRAM_NAME); 107 | fprintf(stderr, "Options:\n"); 108 | fprintf(stderr, "\t-v\toutput verbose information"); 109 | } 110 | 111 | static void die(const char *msg, int ret_code) { 112 | fprintf(stderr, "%s: %s\n", PROGRAM_NAME, msg); 113 | exit(ret_code); 114 | } 115 | 116 | static inline bool next_hex(FILE *infile, uint32_t *hex) { 117 | if (fread(hex, 4, 1, infile) != 1) { 118 | if (feof(infile)) { 119 | state.error = ERROR_EOF; 120 | } else if (ferror(infile)) { 121 | state.error = ERROR_FILE_READ; 122 | } 123 | return false; 124 | } 125 | *hex = SWAP32(*hex); 126 | state.offset += 4; 127 | return true; 128 | } 129 | 130 | static inline void retract_hex(FILE *infile) { 131 | fseek(infile, -4, SEEK_CUR); 132 | state.offset -= 4; 133 | } 134 | 135 | static inline const opcode_t *match_opcode(uint32_t hex) { 136 | for (int i = 0; i < (sizeof opcodes / sizeof(opcode_t)); ++i) { 137 | if (hex == opcodes[i].hex) { 138 | return &opcodes[i]; 139 | } 140 | } 141 | return &opcodes[OPCODE_NUM - 1]; 142 | } 143 | 144 | static bool fill_operands(FILE *infile, cmd_t *cmd) { 145 | for (int i = 0; i < cmd->opcode->operands; ++i) { 146 | next_hex(infile, &cmd->operand[i]); 147 | } 148 | } 149 | 150 | static void get_data(FILE *infile, cmd_t *cmd) { 151 | const uint32_t length = cmd->operand[1]; 152 | const uint32_t width = cmd->operand[2]; 153 | const size_t filesize = length * width; 154 | cmd->data = malloc(filesize); 155 | if (!cmd->data) { 156 | die("No enough memory!", -1); 157 | } 158 | 159 | if (fread(cmd->data, sizeof(uint8_t), filesize, infile) != filesize) { 160 | die("Reading data failed!", -1); 161 | } 162 | 163 | state.offset += filesize; 164 | } 165 | 166 | static bool decode(FILE *infile, cmd_t *cmd) { 167 | cmd->id = state.id++; 168 | cmd->offset = state.offset; 169 | 170 | uint32_t hex = 0xFFFFFEF; 171 | if (!next_hex(infile, &hex)) { 172 | return false; 173 | } 174 | 175 | cmd->opcode = match_opcode(hex); 176 | if (cmd->opcode->hex == 0) { 177 | retract_hex(infile); 178 | }; 179 | fill_operands(infile, cmd); 180 | switch (cmd->opcode->operands) { 181 | case 1: { 182 | if (cmd->opcode->operand_types[0] == OPERAND_ADDRESS) { 183 | sprintf(cmd->label, "%s(0x%.4x)", cmd->opcode->op, cmd->operand[0]); 184 | } else { 185 | sprintf(cmd->label, "%s(%u)", cmd->opcode->op, cmd->operand[0]); 186 | } 187 | } 188 | break; 189 | case 2: 190 | sprintf(cmd->label, "%s(0x%.4x, 0x%.4x)", cmd->opcode->op, cmd->operand[0], cmd->operand[1]); 191 | break; 192 | case 4: { 193 | const uint32_t base = cmd->operand[0]; 194 | const uint32_t length = cmd->operand[1]; 195 | const uint32_t width = cmd->operand[2]; 196 | const uint32_t pitch = cmd->operand[3]; 197 | snprintf(cmd->data_name, MAX_LABEL, "data_0x%.8x_%ux%u_%u", base, length, width, pitch); 198 | sprintf(cmd->label, "%s(0x%.8x, %.4u, %.4u, %.4u, \"%s\")", cmd->opcode->op, cmd->operand[0], cmd->operand[1], 199 | cmd->operand[2], cmd->operand[3], cmd->data_name); 200 | get_data(infile, cmd); 201 | } 202 | break; 203 | default: 204 | die("Abnormal error!", -2); 205 | break; 206 | } 207 | return true; 208 | } 209 | 210 | static void output_cmd(FILE *outfile, cmd_t *cmd) { 211 | fprintf(outfile, "%s;\n", cmd->label); 212 | } 213 | 214 | static void output_data(cmd_t *cmd) { 215 | const char *filename = cmd->data_name; 216 | FILE *outfile = fopen(filename, "wb"); 217 | if (!outfile) { 218 | perror("Error"); 219 | die("Unable to open the output data file!", -1); 220 | } 221 | 222 | const uint32_t length = cmd->operand[1]; 223 | const uint32_t width = cmd->operand[2]; 224 | const size_t filesize = length * width; 225 | if (fwrite(cmd->data, sizeof(uint8_t), filesize, outfile) != filesize) { 226 | die("Writing data failed!", -1); 227 | } 228 | free(cmd->data); 229 | } 230 | 231 | static void parse_args(int argc, char *argv[], arguments_t *args) { 232 | int n = argc - 2; 233 | if (n < 1) { 234 | usage(); 235 | exit(0); 236 | } 237 | 238 | for (int i = 1; i < n; ++i) { 239 | const char *option = argv[i]; 240 | if (*option == '-') { 241 | switch (*(option + 1)) { 242 | case 'v': 243 | args->verbose = true; 244 | break; 245 | default: 246 | die("Unknown option!", -1); 247 | } 248 | } else { 249 | die("Wrong argument order!", -1); 250 | } 251 | } 252 | 253 | strncpy(args->infile, argv[argc - 2], MAX_FILENAME); 254 | strncpy(args->outfile, argv[argc - 1], MAX_FILENAME); 255 | } 256 | 257 | void decompile(FILE *infile, FILE *outfile) { 258 | cmd_t cmd = {0}; 259 | while (state.error == ERROR_NONE && decode(infile, &cmd)) { 260 | if (is_cmd_data(&cmd)) { 261 | output_data(&cmd); 262 | } 263 | output_cmd(outfile, &cmd); 264 | } 265 | } 266 | 267 | int main(int argc, char *argv[]) { 268 | arguments_t args = { 269 | .verbose = false, 270 | }; 271 | parse_args(argc, argv, &args); 272 | 273 | FILE *infile = fopen(args.infile, "rb"); 274 | if (!infile) { 275 | perror("Error"); 276 | die("Unable to open the input file!", -1); 277 | } 278 | 279 | FILE *outfile = fopen(args.outfile, "w"); 280 | if (!outfile) { 281 | perror("Error"); 282 | die("Unable to open the output file!", -1); 283 | } 284 | 285 | decompile(infile, outfile); 286 | } -------------------------------------------------------------------------------- /bootloader/initcode/init.scr: -------------------------------------------------------------------------------- 1 | // ============================================== 2 | // Enable timer 6 to measure booting time 3 | // ============================================== 4 | write(0xa494, 0x0000); // Diable timer 6 5 | write(0xa462, 0x0000); // Clear timer 6 counter 6 | write(0xa460, 0x0000); 7 | write(0xa494, 0x000d); // Enable timer 6, one-shot mode 8 | 9 | // ============================================== 10 | // NOR clock div = WCLK/8 = (3+1)*2 11 | // ============================================== 12 | write(0x9c04, 0x0003); 13 | 14 | // ============================================== 15 | // Engine & Clcok Setting 16 | // ============================================== 17 | // General reset register and General clock register 18 | write(0x0012, 0x0008); // Enable MCLK for host 19 | write(0x0014, 0xc001); // MCLK PLL1_OUT1 / 2 (Memory 160MHz) 20 | write(0x0016, 0x102a); 21 | // write(0x0018, 0xc001); // NCLK PLL1_OUT2 / 1 (AHB/RISC 160MHz) 22 | write(0x0018, 0xc800); 23 | 24 | if (read_mask(0x0000, 0x0003)!=0x0003) { // Booting mode 25 | write(0x001a, 0x0028); // Do not reset AHB on booting 26 | } else { 27 | write(0x001a, 0x1028); 28 | } 29 | 30 | write(0x001c, 0xc003); // WCLK PLL1_OUT1 / 4 (APB 80MHz) 31 | 32 | if (read_mask(0x0000, 0x0003)!=0x0003) { // Booting mode 33 | write(0x001e, 0x0aaa); // Do not reset APB on booting 34 | } else { 35 | write(0x001e, 0x3aaa); 36 | } 37 | 38 | write(0x0020, 0x0a2a); // APB Clock 39 | 40 | if (read_mask(0x0000, 0x0003)!=0x0003) { // Booting mode 41 | write(0x0022, 0x3c00); // APB Reset, do not reset NOR0, SDIP on booting 42 | } else { 43 | write(0x0022, 0x3f00); 44 | } 45 | 46 | write(0x0024, 0x9000); // GCLK PLL1_OUT2 / 1 (2D 213MHz) 47 | write(0x0026, 0x3000); // Disable 2D clock 48 | write(0x0028, 0xc000); // DCLK PPL3_OUT1 (LCD) 49 | write(0x002a, 0x3000); // Disable LCD clock 50 | write(0x0030, 0x8001); // ICLK PLL1_OUT1 / 2 (ISP 160MHz) 51 | write(0x0032, 0x7000); // Reset ISP, and disable clock 52 | write(0x0034, 0x8001); // XCLK PLL1_OUT1 / 2 (Video 160MHz) 53 | write(0x0036, 0xf000); // Reset Video & JPEG, and disable clock 54 | write(0x0038, 0x9001); // JCLK PLL1_OUT2 / 2 (JPEG 106.5MHz) 55 | write(0x003A, 0xa000); // AMCLK PLL2_OUT1 (Audio, run-time adjust sampling rate) 56 | write(0x003C, 0x8000); // ZCLK PLL2_OUT1 / 1 (Audio, run-time adjust sampling rate) 57 | write(0x003e, 0x7000); // Reset IIS, and disable clock 58 | write(0x0040, 0x8007); // PCLK PLL1_OUT1 / 8 (PCR 40MHz) 59 | write(0x0042, 0x0000); // PCLK disable 60 | write(0x0044, 0xf000); // Reset RISC and disable clock 61 | write(0x0046, 0x100a); // Reset USB and enable clock 62 | write(0x0048, 0x7000); // Reset TSI and disable clock 63 | write(0x004c, 0xc000); // FCLK PLL1_OUT1 (ARM 320MHz) 64 | 65 | if (read_mask(0x0000, 0x0003)!=0x0003) { // Booting mode 66 | write(0x004e, 0x003f); // Do not reset ARM on booting 67 | } else { 68 | write(0x004e, 0x803f); 69 | } 70 | 71 | write(0x005c, 0x0400); // Reset TSO and disable clock 72 | write(0x0060, 0x8000); // Reset MAC and disable clock 73 | write(0x0062, 0x0008); // Reset CAP and disable clock 74 | write(0x0064, 0x0000); // Disable CAPCLK 75 | 76 | // Disable CLK Reset 77 | write(0x0016, 0x002a); // Enable M1CLK/N2CLK/N10CLK Setting 78 | write(0x001a, 0x0028); // Enable N1CLK Setting, Enable DPU clock 79 | write(0x001e, 0x0aaa); // Enable W0CLK/W1CLK/W2CLK/W3CLk/W4CLK/W5CLK Setting 80 | write(0x0020, 0x0a2a); // Enable W6CLK/W7CLK/W8CLK/W9CLk/W11CLK Setting, Disable W10CLK (KBC) 81 | write(0x0022, 0x0000); // USB Clock Setting 82 | write(0x0026, 0x0000); // Disable CQ 83 | write(0x002a, 0x0000); // Disable DCLK LCD Clock Setting 84 | write(0x0032, 0x0000); // Disable M5CLK/ICLK/I1CLK Clock Setting 85 | write(0x0036, 0x0000); // Disable JPEG Clock Setting 86 | write(0x003e, 0x0000); // Disable Audio DAC Clock Setting 87 | write(0x0042, 0x0000); // Disable PCR Clock Setting 88 | write(0x0044, 0x0000); // Disable RISC Clock Setting 89 | write(0x0046, 0x0000); // Disable USB Clock Setting 90 | write(0x0048, 0x0000); // Disable TSI Clock Setting 91 | write(0x004e, 0x003a); // Enable ARM Clcok Setting 92 | write(0x005c, 0x0400); // Disable TSO Clock Setting 93 | write(0x0060, 0x0000); // Disable MAC Clock Setting 94 | write(0x0062, 0x0000); // Disable TSP and CAPCLK(M17CLK) 95 | write(0x0080, 0x018F); // PCR clock = 40M/400 = 100KHz 96 | 97 | // SDCLK div = WCLK/4 98 | write(0xb010, 0x000c); 99 | 100 | // pull-up unused GPIO 82~97, 100~102 for IT9852 or IT9854 101 | if (read_mask(0x0000, 0x6000)==0x4000) { // IT9852 102 | write(0x8096, 0xfffc); // enable GPIO 82~95 pull-up 103 | write(0x809a, 0xfffc); // enable GPIO 82~95 pull-up 104 | write(0x80d4, 0x0073); // enable GPIO 96~97, 100~102 pull-up 105 | write(0x80d8, 0x0073); // enable GPIO 96~97, 100~102 pull-up 106 | } else if (read_mask(0x0000, 0x6000)==0x0000) { // IT9854 107 | write(0x8096, 0xfffc); // enable GPIO 82~95 pull-up 108 | write(0x809a, 0xfffc); // enable GPIO 82~95 pull-up 109 | write(0x80d4, 0x0073); // enable GPIO 96~97, 100~102 pull-up 110 | write(0x80d8, 0x0073); // enable GPIO 96~97, 100~102 pull-up 111 | } 112 | 113 | // Set Host clock to PLL2 temporary, and set it to PLL1_OUT2 latter 114 | write(0x0010, 0x5000); // BCLK PLL2_OUT1 (Host 33MHz) 115 | 116 | // ============================================== 117 | // PLL1 640MHz ck1_n1=320MHz , ck1_n2=213MHz 118 | // ============================================== 119 | write(0x00a0, 0x450c); 120 | write(0x00a2, 0x0302); 121 | write(0x00a4, 0x2280); 122 | write(0x00a4, 0x3280); 123 | write(0x00a4, 0x2280); 124 | 125 | 126 | // Set the host clock to PLL1_OUT2 127 | write(0x0010, 0x4802); // BCLK PLL1_OUT2 / 3 (Host 64MHz) 128 | 129 | // Host bus controller registers 130 | write(0x0200, 0x0000); 131 | write(0x0210, 0x0002); // Host_IO_Drv="01" 132 | write(0x0214, 0x0c00); 133 | 134 | // ============================================== 135 | // AHB Setting 136 | // ============================================== 137 | write(0x03da, 0x7508); // AHB Wrapper Setting 138 | write(0x03de, 0x000f); // AHB time out 139 | 140 | 141 | // ============================================== 142 | // Memory Setting for Winbond DDR2 143 | // ============================================== 144 | if (read_mask(0x0000, 0x1000)==0x0000) { 145 | // Memory IO strength Setting 146 | 147 | // Memory controller registers 148 | // select MA13 MA12 as bank address 149 | // linear mode, 512Mbits 4banks 16bits_BusWidth 10Bits_col_add(2KByte per page) 150 | if (read_mask(0x0000, 0x6000)==0x4000) { // IT9852 151 | write(0x0300, 0x3298); 152 | } else { // IT9854, IT9856, IT9866 153 | write(0x0300, 0x32a8); 154 | } 155 | write(0x030a, 0x0025); // Enable auto precharge, Turbo mode, RISC R/W merge 156 | write(0x0310, 0x1a22); 157 | write(0x0312, 0x6412); // B0DTWR, B0DTWTR, B0DTXP, B0DTRTW, B0DTRFC, B0DTRCD, B0DTRP 158 | write(0x0314, 0x0028); 159 | write(0x0316, 0x1000); // B0DTDQSMCLK=00, B0DTDQL=6 160 | write(0x0318, 0x2208); 161 | write(0x031a, 0x2000); // B0DTWL, B0DTEnCKGat, B0DTRAS 162 | write(0x031c, 0x6121); 163 | 164 | // ============================================== 165 | // Memory Setting for Etron DDR2 166 | // ============================================== 167 | } else { 168 | // Memory IO strength Setting 169 | 170 | // Memory controller registers 171 | // select MA13 MA12 as bank address 172 | // linear mode, 512Mbits 4banks 16bits_BusWidth 10Bits_col_add(2KByte per page) 173 | if (read_mask(0x0000, 0x6000)==0x4000) { // IT9852 174 | write(0x0300, 0x3298); 175 | } else { // IT9854, IT9856, IT9866 176 | write(0x0300, 0x32a8); 177 | } 178 | write(0x030a, 0x0025); // Enable auto precharge, Turbo mode, RISC R/W merge 179 | write(0x0310, 0x1a22); 180 | write(0x0312, 0x6412); // B0DTWR, B0DTWTR, B0DTXP, B0DTRTW, B0DTRFC, B0DTRCD, B0DTRP 181 | write(0x0314, 0x0028); // B0DTDQSMCLK=00, B0DTDQL=6 182 | write(0x0316, 0x1000); 183 | write(0x0318, 0x2208); 184 | write(0x031a, 0x2000); // B0DTWL, B0DTEnCKGat, B0DTRAS 185 | write(0x031c, 0x6121); 186 | } 187 | 188 | // ============================================== 189 | // DDRPLL reset and start 190 | // ============================================== 191 | write(0x0340, 0x2a40); // Reset PLL 192 | write(0x0340, 0x2a44); // Start PLL 193 | write(0x0340, 0x3a44); // Update PLL 194 | write(0x0340, 0x2a44); // Start PLL 195 | write(0x0342, 0x0882); // DLL reset 196 | 197 | // ============================================== 198 | // Open auto digital delay lock loop 199 | // ============================================== 200 | write(0x0320, 0x704a); // auto DDLL 201 | write(0x0322, 0x0a4a); 202 | write(0x0324, 0x0a4a); 203 | write(0x0320, 0xf04a); // update phase from average compare cycle 204 | 205 | // ============================================== 206 | // Memory Setting for Winbond DDR2 207 | // ============================================== 208 | if (read_mask(0x0000, 0x1000)==0x0000) { 209 | write(0x0348, 0xe002); // B0DTDQSI 210 | write(0x0334, 0x0000); // MCLKP Out Setting & MA &CMD 211 | write(0x0336, 0xc000); // ODT Enable & MDQS IO Driving 212 | write(0x0330, 0x8000); // IO Driving 213 | write(0x0332, 0x1400); // odt 150 ohm 214 | write(0x0396, 0xa000); // MAX GNT 215 | 216 | write(0x0338, 0x0000); 217 | write(0x033a, 0x0f08); 218 | write(0x0338, 0x0080); 219 | 220 | write(0x0338, 0x0001); 221 | write(0x033a, 0x0f08); 222 | write(0x0338, 0x0081); 223 | 224 | write(0x0338, 0x0002); 225 | write(0x033a, 0x0f08); 226 | write(0x0338, 0x0082); 227 | 228 | write(0x0338, 0x0003); 229 | write(0x033a, 0x0f08); 230 | write(0x0338, 0x0083); 231 | 232 | write(0x0338, 0x0004); 233 | write(0x033a, 0x0f08); 234 | write(0x0338, 0x0084); 235 | 236 | write(0x0338, 0x0005); 237 | write(0x033a, 0x0f08); 238 | write(0x0338, 0x0085); 239 | 240 | write(0x0338, 0x0006); 241 | write(0x033a, 0x0f08); 242 | write(0x0338, 0x0086); 243 | 244 | write(0x0338, 0x0007); 245 | write(0x033a, 0x0f08); 246 | write(0x0338, 0x0087); 247 | 248 | write(0x0338, 0x0008); 249 | write(0x033a, 0x0f08); 250 | write(0x0338, 0x0088); 251 | 252 | write(0x0338, 0x0009); 253 | write(0x033a, 0x0f08); 254 | write(0x0338, 0x0089); 255 | 256 | write(0x0338, 0x000a); 257 | write(0x033a, 0x0f08); 258 | write(0x0338, 0x008a); 259 | 260 | write(0x0338, 0x000b); 261 | write(0x033a, 0x0f08); 262 | write(0x0338, 0x008b); 263 | 264 | write(0x0338, 0x000c); 265 | write(0x033a, 0x0f08); 266 | write(0x0338, 0x008c); 267 | 268 | write(0x0338, 0x000d); 269 | write(0x033a, 0x0f08); 270 | write(0x0338, 0x008d); 271 | 272 | write(0x0338, 0x000e); 273 | write(0x033a, 0x0f08); 274 | write(0x0338, 0x008e); 275 | 276 | write(0x0338, 0x000f); 277 | write(0x033a, 0x0f08); 278 | write(0x0338, 0x008f); 279 | 280 | write(0x0338, 0x8200); // Enable Absorber 281 | write(0x0320, 0xf84a); // update phase from Dram refresh 282 | 283 | // Extend mode register 2: 1X refresh rate 284 | write(0x0304, 0x8000); 285 | write(0x0308, 0x0800); // tune tRC for tref 286 | wait(1); 287 | write(0x0308, 0x8800); // turn off PD 288 | write(0x0316, 0x1177); 289 | wait(1); 290 | 291 | // Extend mode register 3: 292 | write(0x0304, 0xc000); 293 | write(0x0308, 0x0800); // tune tRC for tref 294 | wait(1); 295 | write(0x0308, 0x8800); // turn off PD 296 | wait(1); 297 | 298 | // Extend mode register: DLL enable 299 | write(0x0304, 0x4000); 300 | write(0x0308, 0x0800); // tune tRC for tref 301 | wait(1); 302 | write(0x0308, 0x8800); // turn off PD 303 | wait(1); 304 | 305 | // mode register: burst length=4, CAS latency=6 , DLL reset 306 | // write(0x0304, 0x0f62); 307 | write(0x0304, 0x0162); 308 | write(0x0308, 0x0800); // tune tRC for tref 309 | wait(1); 310 | write(0x0308, 0x8800); // turn off PD 311 | wait(1); 312 | 313 | // mode register: burst length=4, CAS latency=6, DLL reset Off 314 | // write(0x0304, 0x0e62); 315 | write(0x0304, 0x0862); 316 | write(0x0308, 0x0800); // tune tRC for tref 317 | wait(1); 318 | write(0x0308, 0xc800); // turn off PD 319 | wait(1); 320 | 321 | // Extend mode register: OCD default 322 | write(0x0304, 0x43c0); 323 | write(0x0308, 0x0800); // tune tRC for tref 324 | wait(1); 325 | write(0x0308, 0x8800); // turn off PD 326 | wait(1); 327 | 328 | // Extend mode register: OCD exit 329 | write(0x0304, 0x4042); // odt 150 ohm 330 | write(0x0308, 0x0800); // tune tRC for tref 331 | wait(1); 332 | write(0x0308, 0xc880); // turn off PD 333 | wait(1); 334 | 335 | // ============================================== 336 | // Memory Setting for Etron DDR2 337 | // ============================================== 338 | } else { 339 | write(0x0348, 0xe002); // B0DTDQSI 340 | write(0x0334, 0x0000); // MCLKP Out Setting & MA &CMD 341 | write(0x0336, 0xc000); // ODT Enable & MDQS IO Driving 342 | write(0x0330, 0x8000); // IO Driving 343 | write(0x0332, 0x1400); // odt 150 ohm 344 | write(0x0396, 0xa000); // MAX GNT 345 | 346 | write(0x0338, 0x0000); 347 | write(0x033a, 0x0f08); 348 | write(0x0338, 0x0080); 349 | 350 | write(0x0338, 0x0001); 351 | write(0x033a, 0x0f08); 352 | write(0x0338, 0x0081); 353 | 354 | write(0x0338, 0x0002); 355 | write(0x033a, 0x0f08); 356 | write(0x0338, 0x0082); 357 | 358 | write(0x0338, 0x0003); 359 | write(0x033a, 0x0f08); 360 | write(0x0338, 0x0083); 361 | 362 | write(0x0338, 0x0004); 363 | write(0x033a, 0x0f08); 364 | write(0x0338, 0x0084); 365 | 366 | write(0x0338, 0x0005); 367 | write(0x033a, 0x0f08); 368 | write(0x0338, 0x0085); 369 | 370 | write(0x0338, 0x0006); 371 | write(0x033a, 0x0f08); 372 | write(0x0338, 0x0086); 373 | 374 | write(0x0338, 0x0007); 375 | write(0x033a, 0x0f08); 376 | write(0x0338, 0x0087); 377 | 378 | write(0x0338, 0x0008); 379 | write(0x033a, 0x0f08); 380 | write(0x0338, 0x0088); 381 | 382 | write(0x0338, 0x0009); 383 | write(0x033a, 0x0f08); 384 | write(0x0338, 0x0089); 385 | 386 | write(0x0338, 0x000a); 387 | write(0x033a, 0x0f08); 388 | write(0x0338, 0x008a); 389 | 390 | write(0x0338, 0x000b); 391 | write(0x033a, 0x0f08); 392 | write(0x0338, 0x008b); 393 | 394 | write(0x0338, 0x000c); 395 | write(0x033a, 0x0f08); 396 | write(0x0338, 0x008c); 397 | 398 | write(0x0338, 0x000d); 399 | write(0x033a, 0x0f08); 400 | write(0x0338, 0x008d); 401 | 402 | write(0x0338, 0x000e); 403 | write(0x033a, 0x0f08); 404 | write(0x0338, 0x008e); 405 | 406 | write(0x0338, 0x000f); 407 | write(0x033a, 0x0f08); 408 | write(0x0338, 0x008f); 409 | 410 | write(0x0338, 0x8200); // Enable Absorber 411 | write(0x0320, 0xf84a); // update phase from Dram refresh 412 | 413 | // Extend mode register 2: 1X refresh rate 414 | write(0x0304, 0x8000); 415 | write(0x0308, 0x0800); // tune tRC for tref 416 | wait(1); 417 | write(0x0308, 0x8800); // turn off PD 418 | write(0x0316, 0x1177); 419 | wait(1); 420 | 421 | // Extend mode register 3: 422 | write(0x0304, 0xc000); 423 | write(0x0308, 0x0800); // tune tRC for tref 424 | wait(1); 425 | write(0x0308, 0x8800); // turn off PD 426 | wait(1); 427 | 428 | // Extend mode register: DLL enable 429 | write(0x0304, 0x4000); 430 | write(0x0308, 0x0800); // tune tRC for tref 431 | wait(1); 432 | write(0x0308, 0x8800); // turn off PD 433 | wait(1); 434 | 435 | // mode register: burst length=4, CAS latency=6 , DLL reset 436 | // write(0x0304, 0x0f62); 437 | write(0x0304, 0x0162); 438 | write(0x0308, 0x0800); // tune tRC for tref 439 | wait(1); 440 | write(0x0308, 0x8800); // turn off PD 441 | wait(1); 442 | 443 | // mode register: burst length=4, CAS latency=6, DLL reset Off 444 | // write(0x0304, 0x0e62); 445 | write(0x0304, 0x0862); 446 | write(0x0308, 0x0800); // tune tRC for tref 447 | wait(1); 448 | write(0x0308, 0xc800); // turn off PD 449 | wait(1); 450 | 451 | // Extend mode register: OCD default 452 | write(0x0304, 0x43c0); 453 | write(0x0308, 0x0800); // tune tRC for tref 454 | wait(1); 455 | write(0x0308, 0x8800); // turn off PD 456 | wait(1); 457 | 458 | // Extend mode register: OCD exit 459 | write(0x0304, 0x4042); // odt 150 ohm 460 | write(0x0308, 0x0800); // tune tRC for tref 461 | wait(1); 462 | write(0x0308, 0xc880); // turn off PD 463 | wait(1); 464 | } 465 | 466 | // Memory Priority Setting for Arbitration, original priority USB > ARM > RISC > AHB 467 | write(0x0382, 0x100c); // swap the priority fo USB > AHB > RISC > ARM 468 | write(0x0386, 0x110d); 469 | 470 | // ============================================== 471 | // End of Memory Setting 472 | // ============================================== 473 | 474 | // ============================================== 475 | // Setting to resume from RAM 476 | // ============================================== 477 | if (0) { // turn it on if the suspend to RAM is supported 478 | if (read_mask(0x0000, 0x0003)!=0x0003) { // booting mode 479 | if (read_mask(0xde50002c, 0x7e000000) != 0x02000000) { // read the tag from RTC register 480 | write(0x0308, 0xc800); // exit self refresh 481 | wait(50*1000); // wait 50 ms 482 | goto(0x800001c0); // goto startup.S itpSuspendRestore function 483 | } 484 | } 485 | } 486 | 487 | // data(0x00000000, 1, ${CFG_LCD_CLEAR_FILESIZE}, ${CFG_LCD_CLEAR_FILESIZE}, "lcd_clear.bin"); 488 | data(0x00000000, 1, 172, 172, "lcd_clear.bin"); 489 | 490 | /* ************************************************* */ 491 | /* IT9850, Enable DCLK Clock Setting */ 492 | /* ************************************************* */ 493 | write(0x002A, 0x0022); 494 | 495 | /* ************************************************** */ 496 | /* PLL3 810MHz, ck3_n1=30MHz, ck3_n2=30MHz FPS = 62Hz */ 497 | /* ************************************************** */ 498 | write(0x00C0, 0x400C); 499 | write(0x00C2, 0x001B); 500 | write(0x00C4, 0x232A); 501 | write(0x00C4, 0x332A); 502 | write(0x00C4, 0x232A); 503 | 504 | write(0x0028, 0xC000); 505 | //LCD reset 506 | write(0x002A, 0x3022); 507 | wait(500); 508 | write(0x002A, 0x0022); 509 | wait(500); 510 | 511 | /* ************************************************* */ 512 | /* General Setting */ 513 | /* ************************************************* */ 514 | write(0x1100, 0x2000); 515 | write(0x1102, 0x0A60); // Dst=RGB565, 24bit 516 | write(0x1104, 0xE002); // DCLK falling Latch, Hsync Negative, Ysync Negative 517 | write(0x1106, 0x0000); // SW flip, [1:0]: layer1 Buffer:A, [5:4]:Ui decompress Buffer B 518 | write(0x1108, 0x0F00); 519 | // write(0x110c, ${CFG_LCD_WIDTH}); 520 | write(0x110c, 480); // width 521 | // write(0x110e, ${CFG_LCD_HEIGHT}); 522 | write(0x110e, 854); // height 523 | // write(0x1110, ${CFG_LCD_PITCH}); 524 | write(0x1110, 960); // pitch 525 | // write(0x1112, ${CFG_LCDA_ADDR} & 0xffff); 526 | write(0x1112, 0x03DA7880 & 0xffff); // base 527 | // write(0x1114, ${CFG_LCDA_ADDR} >> 16); 528 | write(0x1114, 0x03DA7880 >> 16); // base 529 | 530 | call(0x80000000); 531 | 532 | /* boot DATA start_addr length width pitch filename */ 533 | // data(${CFG_LCD_BOOT_BITMAP_ADDR}, ${CFG_LCD_BOOT_BITMAP_HEIGHT}, ${CFG_LCD_BOOT_BITMAP_WIDTH}, ${CFG_LCD_PITCH}, "bitmap.raw"); 534 | data(0x03E011D8, 90, 528, 960, "bitmap.raw"); 535 | 536 | /* ************************************************* */ 537 | /* Hardware Cursor Setting */ 538 | /* ************************************************* */ 539 | write(0x1120, 0x0000); 540 | write(0x1138, 0x2000); //request threshold 541 | 542 | /* ************************************************* */ 543 | /* CTG Setting */ 544 | /* ************************************************* */ 545 | 546 | 547 | // Interface Setting 548 | write(0x1190, 0x0007); 549 | write(0x1192, 0x020E); 550 | write(0x1194, 0x038A); 551 | 552 | //Output HSync 553 | write(0x11A0, 0x1000); 554 | write(0x11A2, 0x0001); 555 | write(0x11A4, 0x2004); 556 | write(0x11A6, 0x0001); 557 | write(0x11A8, 0x120A); 558 | write(0x11AA, 0x0001); 559 | write(0x11AC, 0x2000); 560 | write(0x11AE, 0x0001); 561 | //Output VSync 562 | write(0x11B0, 0x5006); 563 | write(0x11B2, 0x0000); 564 | write(0x11B4, 0x2006); 565 | write(0x11B6, 0x0001); 566 | write(0x11B8, 0x1006); 567 | write(0x11BA, 0x0388); 568 | write(0x11BC, 0x2006); 569 | write(0x11BE, 0x0000); 570 | //Output DE 571 | write(0x11C0, 0x1006); 572 | write(0x11C2, 0x0012); 573 | write(0x11C4, 0x21e6); 574 | write(0x11C6, 0x0368); 575 | write(0x11C8, 0x1006); 576 | write(0x11CA, 0x0012); 577 | write(0x11CC, 0x21E6); 578 | write(0x11CE, 0x0368); 579 | 580 | /* ************************************************* */ 581 | /* Pin Share setting */ 582 | /* ************************************************* */ 583 | write(0x1258, 0x8000); // Enable IO output 584 | 585 | write(0x8108, 0x4000); // 39, Mode1 586 | write(0x810A, 0x5555); // 40~47, Mode1 587 | write(0x810C, 0x5555); // 48~55, Mode1 588 | write(0x810E, 0x1555); // 56~62, Mode1 589 | write(0x8110, 0x0156); // 64, Mode2, 65~68, Mode1 590 | 591 | /* ************************************************* */ 592 | /* Enable LCD */ 593 | /* ************************************************* */ 594 | write(0x111E, 0x0001); // Sync Fire 595 | wait(500); // 9850 unit: us 596 | write(0x111E, 0x0003); // Display Fire 597 | 598 | // delay 20ms then turn on backlight 599 | if (read_mask(0x0002, 0xffff) == 0x9070) { 600 | wait(10000000); // delay 10000000*3 CPU cycles on 9070 601 | } else if (read_mask(0x0002, 0xffff) == 0x9910) { 602 | wait(10000000); // delay 10000000*3 CPU cycles on 9910 603 | } else { 604 | wait(20*10000); // delay 16ms on P9850 or after project 605 | } 606 | //data(0x00000000, 1, CFG_BACKLIGHT_FILESIZE, CFG_BACKLIGHT_FILESIZE, "backlight.bin"); 607 | data(0x00000000, 1, 3040, 3040, "backlight.bin"); 608 | // call(CFG_BACKLIGHT_ENTRY_ADDR); 609 | call(0x800007e8); 610 | 611 | --------------------------------------------------------------------------------