├── .gitignore ├── .vscode ├── .cortex-debug.registers.state.json ├── tasks.json ├── launch.json └── settings.json ├── OpenOCD_config ├── .gitignore ├── start-ocd-server ├── start-ocd-server-edgb ├── ATMEL-ICE-OpenOCD-SAMR21-ZLL.cfg └── ATMEL-ICE-OpenOCD-samr21e18a.cfg ├── third_party ├── temp ├── CMSIS │ ├── core │ │ └── cmsis_version.h │ └── r21 │ │ ├── source │ │ ├── system_samr21.h │ │ └── system_samr21.c │ │ └── include │ │ ├── instance │ │ ├── rfctrl.h │ │ ├── pac0.h │ │ ├── pac1.h │ │ ├── pac2.h │ │ ├── wdt.h │ │ ├── gclk.h │ │ ├── eic.h │ │ ├── nvmctrl.h │ │ ├── pm.h │ │ ├── ac.h │ │ ├── adc.h │ │ ├── dsu.h │ │ └── mtb.h │ │ ├── samr21.h │ │ └── component │ │ ├── pac.h │ │ ├── rfctrl.h │ │ └── hmatrixb.h ├── Makefile ├── CMakeLists.txt ├── tinyusb_config │ └── tusb_config.h └── ATMEL │ └── LINKER │ ├── samr21e18a_flash.ld │ ├── samr21e18a_flash copy.ld │ └── samr21e18a_flash_gcf_offset.ld ├── .gitmodules ├── script ├── flashRcpDebug.sh ├── flashRcpRelease.sh ├── flashRcpConbee2Debug.sh ├── bootstrap.sh ├── buildRcpDebug.sh ├── buildRcpRelease.sh ├── buildRcpConbee2Debug.sh ├── buildRcpConbee2.sh └── buildRcpRaspbee2.sh ├── src ├── openthread-core-r21-config-check.h ├── OT-HAL │ ├── otPlatEntropy.c │ ├── include │ │ └── otPlatSystemHeader.h │ ├── otPlatLog.c │ ├── otFlash.c │ ├── otPlatAlarm.c │ ├── otPlatSystem.c │ └── otPlatUartUsb.c ├── HAL │ ├── include │ │ ├── samr21Usb.h │ │ ├── samr21FeCtrl.h │ │ ├── samr21SysTick.h │ │ ├── samr21Clock.h │ │ ├── samr21Rtc.h │ │ ├── samr21Uart.h │ │ ├── samr21Dma.h │ │ ├── samr21Nvm.h │ │ └── samr21Timer.h │ ├── samr21SysTick.c │ ├── samr21FeCtrl.c │ ├── samr21Usb.c │ ├── samr21Rtc.c │ └── samr21Nvm.c ├── arm-none-eabi-gcc.cmake ├── CMakeLists.txt ├── platformVersion.h ├── OT-Utils │ └── include │ │ ├── otUtilities_sourceMatch.h │ │ ├── otUtilities_codeUtils.h │ │ ├── otUtilities_uart.h │ │ └── otUtilities_linkMetrics.h ├── Makefile ├── syscallRedirect.c └── openthread-core-r21-config.h ├── test ├── sniffer.c ├── mainGCF.c └── mainMisc.c ├── Makefile ├── CMakeLists.txt └── LICENSE /.gitignore: -------------------------------------------------------------------------------- 1 | gcc-arm-none-eabi 2 | out 3 | -------------------------------------------------------------------------------- /.vscode/.cortex-debug.registers.state.json: -------------------------------------------------------------------------------- 1 | [] -------------------------------------------------------------------------------- /OpenOCD_config/.gitignore: -------------------------------------------------------------------------------- 1 | tempOcdInstance.pid 2 | -------------------------------------------------------------------------------- /OpenOCD_config/start-ocd-server: -------------------------------------------------------------------------------- 1 | sudo openocd -f ATMEL-ICE-OpenOCD-samr21e18a.cfg 2 | -------------------------------------------------------------------------------- /OpenOCD_config/start-ocd-server-edgb: -------------------------------------------------------------------------------- 1 | sudo openocd -f board/atmel_samr21_xplained_pro.cfg 2 | -------------------------------------------------------------------------------- /third_party/temp: -------------------------------------------------------------------------------- 1 | 2 | s PUBLIC 3 | -T${PROJECT_SOURCE_DIR}/third_party/ATMEL/LINKER/samr21e18a_flash.ld 4 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "openthread"] 2 | path = openthread 3 | url = https://github.com/openthread/openthread 4 | [submodule "third_party/tinyusb"] 5 | path = third_party/tinyusb 6 | url = https://github.com/hathach/tinyusb/ 7 | -------------------------------------------------------------------------------- /OpenOCD_config/ATMEL-ICE-OpenOCD-SAMR21-ZLL.cfg: -------------------------------------------------------------------------------- 1 | # EDBG in-circuit debugger. 2 | adapter driver cmsis-dap 3 | cmsis_dap_vid_pid 0x03eb 0x2111 4 | 5 | # Chip info 6 | set CHIPNAME atsamr21e18a 7 | source [find target/at91samdXX.cfg] 8 | -------------------------------------------------------------------------------- /OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg: -------------------------------------------------------------------------------- 1 | # Atmel-ICE JTAG/SWD in-circuit debugger. 2 | adapter driver cmsis-dap 3 | cmsis_dap_vid_pid 0x03eb 0x2141 4 | 5 | # Chip info 6 | set CHIPNAME atsamr21e18a 7 | source [find target/at91samdXX.cfg] 8 | -------------------------------------------------------------------------------- /script/flashRcpDebug.sh: -------------------------------------------------------------------------------- 1 | openocd -f ./OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg & 2 | ./gcc-arm-none-eabi/bin/arm-none-eabi-gdb --init-eval-command='target extended-remote localhost:3333' ./out/rcpDebug/bin/ot-rcp -eval-command='load' 3 | killall openocd 4 | -------------------------------------------------------------------------------- /script/flashRcpRelease.sh: -------------------------------------------------------------------------------- 1 | openocd -f ./OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg & 2 | ./gcc-arm-none-eabi/bin/arm-none-eabi-gdb --init-eval-command='target extended-remote localhost:3333' ./out/rcpRelease/bin/ot-rcp -eval-command='load' 3 | killall openocd 4 | -------------------------------------------------------------------------------- /script/flashRcpConbee2Debug.sh: -------------------------------------------------------------------------------- 1 | openocd -f ./OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg & 2 | ./gcc-arm-none-eabi/bin/arm-none-eabi-gdb --init-eval-command='target extended-remote localhost:3333' ./out/rcpConbee2Debug/bin/ot-rcp -eval-command='load' 3 | killall openocd 4 | -------------------------------------------------------------------------------- /src/openthread-core-r21-config-check.h: -------------------------------------------------------------------------------- 1 | #ifndef OPENTHREAD_CORE_SAMR21_CONFIG_CHECK_H_ 2 | #define OPENTHREAD_CORE_SAMR21_CONFIG_CHECK_H_ 3 | 4 | #if OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT 5 | #error "Platform samr21 doesn't support configuration option: OPENTHREAD_CONFIG_RADIO_915MHZ_OQPSK_SUPPORT" 6 | #endif 7 | 8 | #endif /* OPENTHREAD_CORE_SAMR21_CONFIG_CHECK_H_ */ -------------------------------------------------------------------------------- /src/OT-HAL/otPlatEntropy.c: -------------------------------------------------------------------------------- 1 | //Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | #include "openthread/platform/entropy.h" 3 | 4 | #include "samr21Trx.h" 5 | 6 | otError otPlatEntropyGet(uint8_t *aOutput, uint16_t aOutputLength) 7 | { 8 | for (uint16_t i = 0; i < aOutputLength; i++) 9 | { 10 | aOutput[i] = samr21Trx_getRandomByte(); 11 | } 12 | return OT_ERROR_NONE; 13 | } 14 | -------------------------------------------------------------------------------- /test/sniffer.c: -------------------------------------------------------------------------------- 1 | int main(int argc, char const *argv[]) 2 | { 3 | samr21Nvm_init(); 4 | samr21ClockTrxSrcInit(); 5 | samr21Trx_interfaceInit(); 6 | 7 | samr21Trx_setupMClk(0x5); //MCLK 1MHz -> 16 Mhz 8 | samr21ClockInitAfterTrxSetup(); 9 | 10 | samr21TimerInit(); 11 | 12 | samr21DebugPortsInit(); 13 | samr21RadioInit(); 14 | 15 | samr21Usb_init(); 16 | 17 | 18 | while (/* condition */) 19 | { 20 | /* code */ 21 | } 22 | 23 | 24 | 25 | } -------------------------------------------------------------------------------- /src/HAL/include/samr21Usb.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | 12 | #ifndef _SAMR21_USB_H_ 13 | #define _SAMR21_USB_H_ 14 | 15 | #include "samr21.h" 16 | 17 | 18 | 19 | /** 20 | * Inits the Ports and Clocks for the TinyUSB Driver 21 | */ 22 | void samr21Usb_init(); 23 | 24 | /** 25 | * Deinit Clock for USB Module 26 | */ 27 | void samr21Usb_deinit(); 28 | 29 | #endif //_SAMR21_USB_H_ -------------------------------------------------------------------------------- /src/HAL/include/samr21FeCtrl.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #include "samr21.h" 11 | 12 | #ifndef _SAMR21_FECTRL_H_ 13 | #define _SAMR21_FECTRL_H_ 14 | 15 | /** 16 | * Sets up the FE-CTRL Multiplexer of the SAMR21, so the Frontend can be Controlled by the TRX 17 | * 18 | * This is used by the ConBee2 19 | */ 20 | void samr21RadioFeCtrl_init(void); 21 | 22 | 23 | #endif //_SAMR21_FECTRL_H_ -------------------------------------------------------------------------------- /src/OT-HAL/include/otPlatSystemHeader.h: -------------------------------------------------------------------------------- 1 | //Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | 3 | #ifndef _SAMR21_OT_PLATFORM_H_ 4 | #define _SAMR21_OT_PLATFORM_H_ 5 | 6 | 7 | //Handler that checks for new USB/UART Packages 8 | void samr21OtPlat_uartCommTask(); 9 | 10 | //Handler that notifies upper layer about received Frames and the status of ongoing transmissions 11 | void samr21OtPlat_radioTick(); 12 | 13 | //Inits Timer for OT Orchestration 14 | void samr21OtPlat_alarmInit(); 15 | 16 | //Handles Timer for OT Orchestration 17 | void samr21OtPlat_alarmTask(); 18 | 19 | 20 | //Handler that Transmit Frames to the Host device 21 | #endif //_SAMR21_OT_PLATFORM_H_ 22 | -------------------------------------------------------------------------------- /src/HAL/include/samr21SysTick.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | #ifndef _SAMR21_NOP_DELAY_H_ 12 | #define _SAMR21_NOP_DELAY_H_ 13 | 14 | #include "samr21.h" 15 | 16 | /** 17 | * Sets the SysTick Counter to block Operation till the specified amount of CPU Cycles has passed 18 | * 19 | * @param[in] delayCycles amount of CPU Cycles the function should block operation 20 | */ 21 | void samr21SysTick_delayTicks(uint32_t delayCycles); 22 | 23 | #endif // _SAMR21_NOP_DELAY_H_ -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | flashTestRX: 2 | cd ./test && make flashRX 3 | 4 | flashTestTX: 5 | cd ./test && make flashTX 6 | 7 | flashTestED: 8 | cd ./test && make flashED 9 | 10 | flashTestMisc: 11 | cd ./test && make flashMisc 12 | 13 | testGCF: 14 | cd ./test && make testGCF 15 | ./gcc-arm-none-eabi/bin/arm-none-eabi-objcopy -O binary ./out/images/testGCF.elf ./out/images/testGCF.bin 16 | 17 | getToolchain: 18 | wget https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2 19 | tar xfvj gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2 20 | mv gcc-arm-none-eabi-10.3-2021.10 gcc-arm-none-eabi 21 | rm gcc-arm-none-eabi-10.3-2021.10-x86_64-linux.tar.bz2 22 | 23 | 24 | cleanAll: 25 | rm ./out/* -rf 26 | 27 | killOCD: 28 | cd ./test && make killOCD -------------------------------------------------------------------------------- /src/arm-none-eabi-gcc.cmake: -------------------------------------------------------------------------------- 1 | set(CMAKE_SYSTEM_NAME Generic) 2 | set(CMAKE_SYSTEM_PROCESSOR ARM) 3 | 4 | set(CMAKE_C_COMPILER "${PROJECT_SOURCE_DIR}/gcc-arm-none-eabi/bin/arm-none-eabi-gcc") 5 | set(CMAKE_CXX_COMPILER "${PROJECT_SOURCE_DIR}/gcc-arm-none-eabi/bin/arm-none-eabi-g++") 6 | set(CMAKE_ASM_COMPILER "${PROJECT_SOURCE_DIR}/gcc-arm-none-eabi/bin/arm-none-eabi-as") 7 | set(CMAKE_RANLIB "${PROJECT_SOURCE_DIR}/gcc-arm-none-eabi/bin/arm-none-eabi-ranlib") 8 | 9 | 10 | set(COMMON_C_FLAGS "-mcpu=cortex-m0plus -mfloat-abi=soft -mthumb") 11 | 12 | set(CMAKE_C_FLAGS_INIT "${COMMON_C_FLAGS} -std=gnu99") 13 | set(CMAKE_CXX_FLAGS_INIT "${COMMON_C_FLAGS} -fno-exceptions -fno-rtti") 14 | set(CMAKE_ASM_FLAGS_INIT "${COMMON_C_FLAGS}") 15 | set(CMAKE_EXE_LINKER_FLAGS_INIT "${COMMON_C_FLAGS} --specs=nosys.specs -Wl,--entry=Reset_Handler") 16 | -------------------------------------------------------------------------------- /src/HAL/samr21SysTick.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #include "samr21SysTick.h" 11 | 12 | void samr21SysTick_delayTicks(uint32_t a_delayCycles){ 13 | if(a_delayCycles) 14 | { 15 | //Sets the trigger value 16 | SysTick->LOAD = a_delayCycles; 17 | //Clear current value register 18 | SysTick->VAL = 0; 19 | //Enable Systick 20 | SysTick->CTRL = 21 | SysTick_CTRL_CLKSOURCE_Msk 22 | |SysTick_CTRL_ENABLE_Msk 23 | ; 24 | 25 | //Delay Loop 26 | while(!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); 27 | 28 | //Disable Systick 29 | SysTick->CTRL = 0; 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | cmake_minimum_required(VERSION 3.10.2) 3 | 4 | set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") 5 | 6 | project(ot-samr21 VERSION 0.0.1) 7 | 8 | set(OT_PLATFORM_LIB "openthread-r21") 9 | 10 | 11 | 12 | set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${PROJECT_BINARY_DIR}/lib) 13 | set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${PROJECT_BINARY_DIR}/lib) 14 | set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${PROJECT_BINARY_DIR}/bin) 15 | 16 | 17 | add_subdirectory(openthread) 18 | 19 | target_compile_definitions(ot-config INTERFACE 20 | OPENTHREAD_CONFIG_FILE="${PROJECT_SOURCE_DIR}/src/openthread-core-r21-config.h" 21 | OPENTHREAD_PROJECT_CORE_CONFIG_FILE="${PROJECT_SOURCE_DIR}/src/openthread-core-r21-config.h" 22 | OPENTHREAD_CORE_CONFIG_PLATFORM_CHECK_FILE="${PROJECT_SOURCE_DIR}/src/openthread-core-r21-config-check.h" 23 | ) 24 | 25 | target_include_directories(ot-config INTERFACE 26 | ${PROJECT_SOURCE_DIR}/src/OT-HAL/ 27 | ${PROJECT_SOURCE_DIR}/src/OT-HAL/include/ 28 | 29 | ${PROJECT_SOURCE_DIR}/src/HAL/include/ 30 | ) 31 | 32 | add_subdirectory(third_party) 33 | add_subdirectory(src) -------------------------------------------------------------------------------- /src/OT-HAL/otPlatLog.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | #include "samr21Uart.h" 6 | 7 | #define LOG_PARSE_BUFFER_SIZE 128 8 | char sLogString[LOG_PARSE_BUFFER_SIZE + 1]; 9 | 10 | static void logOutput(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, va_list ap) 11 | { 12 | uartBuffer_t * buffer = samr21Uart_allocTransmitBuffer(); 13 | 14 | if (!buffer) 15 | { 16 | //No Output Buffer Available 17 | return; 18 | } 19 | 20 | buffer->length = vsnprintf(buffer->data, UART_BUFFER_SIZE-1, aFormat, ap); 21 | 22 | 23 | samr21Uart_checkForPendingTransmit(); 24 | } 25 | 26 | OT_TOOL_WEAK void otPlatLog(otLogLevel aLogLevel, otLogRegion aLogRegion, const char *aFormat, ...) 27 | { 28 | va_list ap; 29 | 30 | va_start(ap, aFormat); 31 | 32 | logOutput(aLogLevel, aLogRegion, aFormat, ap); 33 | 34 | va_end(ap); 35 | 36 | 37 | OT_UNUSED_VARIABLE(aLogLevel); 38 | OT_UNUSED_VARIABLE(aLogRegion); 39 | OT_UNUSED_VARIABLE(aFormat); 40 | } -------------------------------------------------------------------------------- /script/bootstrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | scriptDir=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) 3 | ARCH=$(uname -m) 4 | 5 | if [ ! -d "${scriptDir}/../gcc-arm-none-eabi" ]; then 6 | # Take action if $DIR exists. # 7 | echo "No Toolchain found!" 8 | echo "Downloading Arm M0+ Toolchain to:" 9 | echo "${scriptDir}/../gcc-arm-none-eabi" 10 | wget "https://developer.arm.com/-/media/Files/downloads/gnu-rm/10.3-2021.10/gcc-arm-none-eabi-10.3-2021.10-${ARCH}-linux.tar.bz2" \ 11 | -O ${scriptDir}/../gcc-arm-none-eabi.tar.bz2 12 | tar xfvj ${scriptDir}/../gcc-arm-none-eabi.tar.bz2 13 | rm ${scriptDir}/../gcc-arm-none-eabi.tar.bz2 14 | mv gcc-arm-none-eabi-10.3-2021.10 gcc-arm-none-eabi 15 | fi 16 | 17 | 18 | if command -v apt-get; then 19 | sudo apt install openocd 20 | elif command -v rpm; then 21 | sudo dnf install openocd 22 | elif command -v pacman; then 23 | sudo pacman -S openocd 24 | else 25 | echo No Known Package Manager found, Please install OpenOCD manualy 26 | 27 | fi 28 | 29 | bash "${scriptDir}/../openthread/script/bootstrap" 30 | 31 | -------------------------------------------------------------------------------- /script/buildRcpDebug.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | scriptDir=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) 4 | set -euxo pipefail 5 | 6 | OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} 7 | 8 | OT_SRCDIR="${scriptDir}/.." 9 | readonly OT_SRCDIR 10 | 11 | OT_OPTIONS=( 12 | "-DCMAKE_TOOLCHAIN_FILE=${OT_SRCDIR}/src/arm-none-eabi-gcc.cmake" 13 | "-DCMAKE_BUILD_TYPE=Debug" 14 | "-DOT_LOG_LEVEL=DEBG" 15 | "-DOT_PLATFORM=external" 16 | "-DOT_SLAAC=ON" 17 | "-DOT_APP_RCP=ON" 18 | "-DOT_RCP=ON" 19 | "-DOT_FTD=OFF" 20 | "-DOT_MTD=OFF" 21 | "-DOT_APP_CLI=OFF" 22 | "-DOT_APP_NCP=OFF" 23 | ) 24 | readonly OT_OPTIONS 25 | 26 | build() 27 | { 28 | local builddir="${OT_CMAKE_BUILD_DIR:-${OT_SRCDIR}/out/rcpDebug}" 29 | 30 | 31 | mkdir -p "${builddir}" 32 | cd "${builddir}" 33 | 34 | cmake -GNinja -DOT_COMPILE_WARNING_AS_ERROR=ON "$@" "${OT_SRCDIR}" 35 | 36 | if [[ -n ${OT_CMAKE_NINJA_TARGET[*]} ]]; then 37 | ninja "${OT_CMAKE_NINJA_TARGET[@]}" 38 | else 39 | ninja 40 | fi 41 | 42 | cd "${OT_SRCDIR}" 43 | } 44 | 45 | main() 46 | { 47 | local options=("${OT_OPTIONS[@]}") 48 | 49 | options+=("$@") 50 | 51 | build "${options[@]}" 52 | } 53 | 54 | main "$@" 55 | -------------------------------------------------------------------------------- /script/buildRcpRelease.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | scriptDir=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) 4 | set -euxo pipefail 5 | 6 | OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} 7 | 8 | OT_SRCDIR="${scriptDir}/.." 9 | readonly OT_SRCDIR 10 | 11 | OT_OPTIONS=( 12 | "-DCMAKE_TOOLCHAIN_FILE=${OT_SRCDIR}/src/arm-none-eabi-gcc.cmake" 13 | "-DCMAKE_BUILD_TYPE=Release" 14 | "-DOT_LOG_LEVEL=NONE" 15 | "-DOT_PLATFORM=external" 16 | "-DOT_SLAAC=ON" 17 | "-DOT_APP_RCP=ON" 18 | "-DOT_RCP=ON" 19 | "-DOT_FTD=OFF" 20 | "-DOT_MTD=OFF" 21 | "-DOT_APP_CLI=OFF" 22 | "-DOT_APP_NCP=OFF" 23 | ) 24 | readonly OT_OPTIONS 25 | 26 | build() 27 | { 28 | local builddir="${OT_CMAKE_BUILD_DIR:-${OT_SRCDIR}/out/rcpRelease}" 29 | 30 | 31 | mkdir -p "${builddir}" 32 | cd "${builddir}" 33 | 34 | cmake -GNinja -DOT_COMPILE_WARNING_AS_ERROR=ON "$@" "${OT_SRCDIR}" 35 | 36 | if [[ -n ${OT_CMAKE_NINJA_TARGET[*]} ]]; then 37 | ninja "${OT_CMAKE_NINJA_TARGET[@]}" 38 | else 39 | ninja 40 | fi 41 | 42 | cd "${OT_SRCDIR}" 43 | } 44 | 45 | main() 46 | { 47 | local options=("${OT_OPTIONS[@]}") 48 | 49 | options+=("$@") 50 | 51 | build "${options[@]}" 52 | } 53 | 54 | main "$@" 55 | -------------------------------------------------------------------------------- /script/buildRcpConbee2Debug.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | scriptDir=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) 4 | set -euxo pipefail 5 | 6 | OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} 7 | 8 | OT_SRCDIR="${scriptDir}/.." 9 | readonly OT_SRCDIR 10 | 11 | OT_OPTIONS=( 12 | "-DCMAKE_TOOLCHAIN_FILE=${OT_SRCDIR}/src/arm-none-eabi-gcc.cmake" 13 | "-DCMAKE_BUILD_TYPE=Debug" 14 | "-DOT_LOG_LEVEL=DEBG" 15 | "-DOT_PLATFORM=external" 16 | "-DOT_SLAAC=ON" 17 | "-DOT_APP_RCP=ON" 18 | "-DOT_RCP=ON" 19 | "-DOT_FTD=OFF" 20 | "-DOT_MTD=OFF" 21 | "-DOT_APP_CLI=OFF" 22 | "-DOT_APP_NCP=OFF" 23 | "-DTARGET_DEVICE=CONBEE2" 24 | ) 25 | readonly OT_OPTIONS 26 | 27 | build() 28 | { 29 | local builddir="${OT_CMAKE_BUILD_DIR:-${OT_SRCDIR}/out/rcpConbee2Debug}" 30 | 31 | 32 | mkdir -p "${builddir}" 33 | cd "${builddir}" 34 | 35 | cmake -GNinja -DOT_COMPILE_WARNING_AS_ERROR=ON "$@" "${OT_SRCDIR}" 36 | 37 | if [[ -n ${OT_CMAKE_NINJA_TARGET[*]} ]]; then 38 | ninja "${OT_CMAKE_NINJA_TARGET[@]}" 39 | else 40 | ninja 41 | fi 42 | 43 | cd "${OT_SRCDIR}" 44 | } 45 | 46 | main() 47 | { 48 | local options=("${OT_OPTIONS[@]}") 49 | 50 | options+=("$@") 51 | 52 | build "${options[@]}" 53 | } 54 | 55 | main "$@" 56 | -------------------------------------------------------------------------------- /script/buildRcpConbee2.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | scriptDir=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) 4 | set -euxo pipefail 5 | 6 | OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} 7 | 8 | OT_SRCDIR="${scriptDir}/.." 9 | readonly OT_SRCDIR 10 | 11 | OT_OPTIONS=( 12 | "-DCMAKE_TOOLCHAIN_FILE=${OT_SRCDIR}/src/arm-none-eabi-gcc.cmake" 13 | "-DCMAKE_BUILD_TYPE=Release" 14 | "-DOT_PLATFORM=external" 15 | "-DOT_SLAAC=ON" 16 | "-DOT_APP_RCP=ON" 17 | "-DOT_RCP=ON" 18 | "-DOT_FTD=OFF" 19 | "-DOT_MTD=OFF" 20 | "-DOT_APP_CLI=OFF" 21 | "-DOT_APP_NCP=OFF" 22 | "-DDDEL_GCF_BUILD=ON" 23 | "-DTARGET_DEVICE=CONBEE2" 24 | ) 25 | readonly OT_OPTIONS 26 | 27 | build() 28 | { 29 | local builddir="${OT_CMAKE_BUILD_DIR:-${OT_SRCDIR}/out/rcpConbee2}" 30 | 31 | 32 | mkdir -p "${builddir}" 33 | cd "${builddir}" 34 | 35 | cmake -GNinja -DOT_COMPILE_WARNING_AS_ERROR=ON "$@" "${OT_SRCDIR}" 36 | 37 | if [[ -n ${OT_CMAKE_NINJA_TARGET[*]} ]]; then 38 | ninja "${OT_CMAKE_NINJA_TARGET[@]}" 39 | else 40 | ninja 41 | fi 42 | 43 | cd "${OT_SRCDIR}" 44 | } 45 | 46 | main() 47 | { 48 | local options=("${OT_OPTIONS[@]}") 49 | 50 | options+=("$@") 51 | 52 | build "${options[@]}" 53 | 54 | exec ${OT_SRCDIR}/gcc-arm-none-eabi/bin/arm-none-eabi-objcopy -O binary ${OT_SRCDIR}/out/rcpConbee2/bin/ot-rcp ${OT_SRCDIR}/out/rcpConbee2/ot-rcp-cb2-gcf.bin 55 | } 56 | 57 | main "$@" 58 | -------------------------------------------------------------------------------- /script/buildRcpRaspbee2.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | scriptDir=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) 4 | set -euxo pipefail 5 | 6 | OT_CMAKE_NINJA_TARGET=${OT_CMAKE_NINJA_TARGET:-} 7 | 8 | OT_SRCDIR="${scriptDir}/.." 9 | readonly OT_SRCDIR 10 | 11 | OT_OPTIONS=( 12 | "-DCMAKE_TOOLCHAIN_FILE=${OT_SRCDIR}/src/arm-none-eabi-gcc.cmake" 13 | "-DCMAKE_BUILD_TYPE=Release" 14 | "-DOT_PLATFORM=external" 15 | "-DOT_SLAAC=ON" 16 | "-DOT_APP_RCP=ON" 17 | "-DOT_RCP=ON" 18 | "-DOT_FTD=OFF" 19 | "-DOT_MTD=OFF" 20 | "-DOT_APP_CLI=OFF" 21 | "-DOT_APP_NCP=OFF" 22 | "-DDDEL_GCF_BUILD=ON" 23 | "-DTARGET_DEVICE=RASPBEE2" 24 | ) 25 | readonly OT_OPTIONS 26 | 27 | build() 28 | { 29 | local builddir="${OT_CMAKE_BUILD_DIR:-${OT_SRCDIR}/out/rcpRaspbee2}" 30 | 31 | 32 | mkdir -p "${builddir}" 33 | cd "${builddir}" 34 | 35 | cmake -GNinja -DOT_COMPILE_WARNING_AS_ERROR=ON "$@" "${OT_SRCDIR}" 36 | 37 | if [[ -n ${OT_CMAKE_NINJA_TARGET[*]} ]]; then 38 | ninja "${OT_CMAKE_NINJA_TARGET[@]}" 39 | else 40 | ninja 41 | fi 42 | 43 | cd "${OT_SRCDIR}" 44 | } 45 | 46 | main() 47 | { 48 | local options=("${OT_OPTIONS[@]}") 49 | 50 | options+=("$@") 51 | 52 | build "${options[@]}" 53 | 54 | exec ${OT_SRCDIR}/gcc-arm-none-eabi/bin/arm-none-eabi-objcopy -O binary ${OT_SRCDIR}/out/rcpRaspbee2/bin/ot-rcp ${OT_SRCDIR}/out/rcpRaspbee2/ot-rcp-rb2-gcf.bin 55 | } 56 | 57 | main "$@" 58 | -------------------------------------------------------------------------------- /src/HAL/include/samr21Clock.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | #ifndef _SAMR21_CLOCK_H_ 12 | #define _SAMR21_CLOCK_H_ 13 | 14 | #include "samr21.h" 15 | #include 16 | #include 17 | 18 | 19 | /** 20 | * Inits the Clocking Tree to a minimum state where all peripheral are disabled. 21 | * Only the SERCOM4 Module gets feed by a internal 1MHz Oscillator Clock. 22 | * This is done so a basic Communication with the AT86RF233 is possible. 23 | * 24 | * CPU = 1MHz 25 | * USB = disabled 26 | * EIC = disabled 27 | * Timer and RTC = disabled 28 | * UART = disabled 29 | * TRX-SPI = 1MHz 30 | */ 31 | void samr21Clock_enableFallbackClockTree(void); 32 | 33 | /** 34 | * Inits the DFLL to output 48MHz. 35 | * Uses the MCLK from the AT86RF233 as a Reference for Accuracy. 36 | * Before calling this Function the AT86RF233 must be setup to output 1MHz on the MCLK Pin. 37 | * 38 | * Alternatively the USB-BUS SOF Signal can be used as the Reference (#ifdef SAMR21_USE_USB_CLOCK). 39 | * 40 | * 41 | * CPU = 48MHz 42 | * USB = 48MHz 43 | * EIC = 48MHz 44 | * Timer and RTC = 1MHz 45 | * UART = 1MHz 46 | * TRX-SPI = 12MHz 47 | */ 48 | void samr21Clock_enableOperatingClockTree(void); 49 | #endif //_SAMR21_CLOCK_H_ -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2022, dresden elektronik ingenieurtechnik gmbh 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | 1. Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | 2. Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | 3. Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /.vscode/tasks.json: -------------------------------------------------------------------------------- 1 | { 2 | // See https://go.microsoft.com/fwlink/?LinkId=733558 3 | // for the documentation about the tasks.json format 4 | "version": "2.0.0", 5 | "tasks": [ 6 | { 7 | "label": "build RCP Debug", 8 | "type": "shell", 9 | "command": "${workspaceFolder}/script/buildRcpDebug.sh", 10 | "presentation": { 11 | "reveal": "silent", 12 | "revealProblems": "onProblem", 13 | "close": true 14 | }, 15 | "dependsOn": [ 16 | "clean all" 17 | ] 18 | }, 19 | { 20 | "label": "build RCP Release", 21 | "type": "shell", 22 | "command": "${workspaceFolder}/script/buildRcpRelease.sh", 23 | "presentation": { 24 | "reveal": "silent", 25 | "revealProblems": "onProblem", 26 | "close": true 27 | } 28 | }, 29 | { 30 | "label": "build RCP ConBee2", 31 | "type": "shell", 32 | "command": "${workspaceFolder}/script/buildRcpConbee.sh", 33 | "presentation": { 34 | "reveal": "silent", 35 | "revealProblems": "onProblem", 36 | "close": true 37 | } 38 | }, 39 | { 40 | "label": "clean all", 41 | "type": "shell", 42 | "command": "rm ${workspaceFolder}/out -rf", 43 | "presentation": { 44 | "reveal": "silent", 45 | "revealProblems": "onProblem", 46 | "close": true 47 | } 48 | } 49 | ] 50 | } -------------------------------------------------------------------------------- /src/HAL/include/samr21Rtc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | #ifndef _SAMR21_RTC_H_ 12 | #define _SAMR21_RTC_H_ 13 | 14 | #include "samr21.h" 15 | #include 16 | 17 | #define SAMR21_RTC_MAX_VALUE 0xFFFFFFFF 18 | 19 | /** 20 | * Sets up the RTC as a microsecond timer 21 | * and forces a synchronous read-access to the rtc Value Register 22 | */ 23 | void samr21Rtc_init(); 24 | 25 | /** 26 | * Disables the RTC and the synchronous read-access to the rtc Value Register 27 | */ 28 | void samr21Rtc_deinit(); 29 | 30 | /** 31 | * Gets a microseconds timestamp since the last initiation of the RTC-Module 32 | * 33 | * @returns a uint32 microseconds Timestamp since the initiation of the rtc 34 | */ 35 | uint32_t samr21Rtc_getTimestamp(); 36 | 37 | /** 38 | * Sets a microseconds timestamp for an Alarm 39 | * RTC_Handler()-ISR is invoked when alarm triggers 40 | * 41 | * @param[in] alarmTimestamp an absolute timestamp for when the RTC Alarm is supposed to be triggered 42 | */ 43 | void samr21Rtc_setAbsoluteAlarm(uint32_t alarmTimestamp); 44 | 45 | /** 46 | * Sets a Alarm on the RTC that triggers after the specified Time 47 | * RTC_Handler()-ISR is invoked when alarm triggers 48 | * 49 | * @param[in] duration the duration after which the Alarm triggers 50 | */ 51 | void samr21Rtc_setRelativeAlarm(uint32_t duration); 52 | 53 | /** 54 | * Stops the currently armed RTC Alarm 55 | */ 56 | void samr21Rtc_disableAlarm(); 57 | 58 | #endif //_SAMR21_RTC_H_ -------------------------------------------------------------------------------- /src/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_library(openthread-r21 2 | HAL/samr21Clock.c 3 | HAL/samr21SysTick.c 4 | HAL/samr21Nvm.c 5 | HAL/samr21Rtc.c 6 | HAL/samr21Timer.c 7 | HAL/samr21Usb.c 8 | HAL/samr21Uart.c 9 | HAL/samr21Dma.c 10 | HAL/samr21Radio.c 11 | HAL/samr21Trx.c 12 | HAL/samr21FeCtrl.c 13 | OT-Utils/otUtilities_linkMetrics.cpp 14 | OT-Utils/otUtilities_macFrame.cpp 15 | OT-Utils/otUtilities_sourceMatch.c 16 | OT-HAL/otPlatAlarm.c 17 | OT-HAL/otFlash.c 18 | OT-HAL/otPlatEntropy.c 19 | OT-HAL/otPlatRadio.c 20 | OT-HAL/otPlatSystem.c 21 | OT-HAL/otPlatUartUsb.c 22 | OT-HAL/otPlatLog.c 23 | syscallRedirect.c 24 | ) 25 | 26 | 27 | target_include_directories(openthread-r21 28 | PRIVATE 29 | ${OT_PUBLIC_INCLUDES} 30 | HAL 31 | HAL/include 32 | HAL/radio 33 | OT-HAL 34 | OT-HAL/include 35 | OT-Utils 36 | OT-Utils/include 37 | ./ 38 | ) 39 | 40 | set_target_properties(openthread-r21 41 | PROPERTIES 42 | C_STANDARD 99 43 | CXX_STANDARD 11 44 | ) 45 | 46 | if(OT_CFLAGS MATCHES "-pedantic-errors") 47 | string(REPLACE "-pedantic-errors" "" OT_CFLAGS "${OT_CFLAGS}") 48 | endif() 49 | 50 | target_link_libraries(openthread-r21 51 | PUBLIC 52 | samr21-CMSIS 53 | samr21-tusb 54 | -Wl,--gc-sections 55 | -Wl,-Map=$.map 56 | PRIVATE 57 | ot-config 58 | ) 59 | 60 | target_compile_definitions(openthread-r21 61 | PUBLIC 62 | ${OT_PLATFORM_DEFINES} 63 | -D__SAMR21E18A__ 64 | ) 65 | 66 | target_compile_options(openthread-r21 67 | PRIVATE 68 | -Wno-implicit-function-declaration 69 | -Wno-expansion-to-defined 70 | ${OT_CFLAGS} 71 | ) 72 | 73 | -------------------------------------------------------------------------------- /third_party/CMSIS/core/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.5 5 | * @date 02. February 2022 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2022 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /src/platformVersion.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017, The OpenThread Authors. 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 3. Neither the name of the copyright holder nor the 13 | * names of its contributors may be used to endorse or promote products 14 | * derived from this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 | * POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | // this converts to string 30 | #define STR_(X) #X 31 | #define STR(X) STR_(X) 32 | 33 | #define OT_SAMR21_PLATFORM_VERSION_MAJOR 01 34 | #define OT_SAMR21_PLATFORM_VERSION_MINOR 02 35 | -------------------------------------------------------------------------------- /src/HAL/samr21FeCtrl.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #include "samr21FeCtrl.h" 11 | 12 | 13 | void samr21FeCtrl_init(void) 14 | { 15 | #if defined(TARGET_DEVICE) && ((TARGET_DEVICE == CONBEE2) || (TARGET_DEVICE == RASPBEE2)) 16 | 17 | PM->APBCMASK.bit.RFCTRL_ = 1; 18 | 19 | PORT->Group[0].DIRSET.reg= PORT_PA08; 20 | //Setup Mux Settings 21 | PORT->Group[0].WRCONFIG.reg = 22 | //PORT_WRCONFIG_HWSEL 23 | PORT_WRCONFIG_WRPINCFG 24 | |PORT_WRCONFIG_WRPMUX 25 | |PORT_WRCONFIG_PMUX(MUX_PA08F_RFCTRL_FECTRL0) 26 | //PORT_WRCONFIG_PULLEN 27 | //|PORT_WRCONFIG_INEN 28 | |PORT_WRCONFIG_PMUXEN 29 | |PORT_WRCONFIG_PINMASK(PORT_PA08) //lower Halfword 30 | ; 31 | //Setup Mux Settings 32 | PORT->Group[0].DIRSET.reg= PORT_PA09; 33 | PORT->Group[0].WRCONFIG.reg = 34 | //PORT_WRCONFIG_HWSEL 35 | PORT_WRCONFIG_WRPINCFG 36 | |PORT_WRCONFIG_WRPMUX 37 | |PORT_WRCONFIG_PMUX(MUX_PA09F_RFCTRL_FECTRL1) 38 | //PORT_WRCONFIG_PULLEN 39 | //|PORT_WRCONFIG_INEN 40 | |PORT_WRCONFIG_PMUXEN 41 | |PORT_WRCONFIG_PINMASK(PORT_PA09) //lower Halfword 42 | ; 43 | 44 | //PA Bypass 45 | PORT->Group[0].DIRSET.reg= PORT_PA16; 46 | PORT->Group[0].OUTSET.reg= PORT_PA16; 47 | 48 | //PA Enable 49 | PORT->Group[0].DIRSET.reg= PORT_PA17; 50 | PORT->Group[0].OUTSET.reg= PORT_PA17; 51 | 52 | RFCTRL->FECFG.bit.F0CFG = 0x03; 53 | RFCTRL->FECFG.bit.F1CFG = 0x02; 54 | 55 | #endif 56 | } 57 | 58 | 59 | void samr21FeCtrl_enable(void) 60 | { 61 | 62 | } 63 | 64 | 65 | void samr21FeCtrl_disable(void) 66 | { 67 | 68 | } -------------------------------------------------------------------------------- /third_party/CMSIS/r21/source/system_samr21.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Low-level initialization functions called upon chip startup 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SYSTEM_SAMR21_H_INCLUDED_ 35 | #define _SYSTEM_SAMR21_H_INCLUDED_ 36 | 37 | #ifdef __cplusplus 38 | extern "C" { 39 | #endif 40 | 41 | #include 42 | 43 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 44 | 45 | void SystemInit(void); 46 | void SystemCoreClockUpdate(void); 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* SYSTEM_SAMR21_H_INCLUDED */ 53 | -------------------------------------------------------------------------------- /src/HAL/include/samr21Uart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | 12 | #ifndef _SAMR21_UART_H_ 13 | #define _SAMR21_UART_H_ 14 | 15 | #include "samr21.h" 16 | #include "samr21Uart.h" 17 | 18 | #ifndef UART_BUFFER_SIZE 19 | #define UART_BUFFER_SIZE 128 20 | #endif 21 | 22 | #ifndef NUM_UART_BUFFER 23 | #define NUM_UART_BUFFER 3 24 | #endif 25 | 26 | typedef struct uartBuffer_s 27 | { 28 | uint8_t data[UART_BUFFER_SIZE]; 29 | int16_t length; 30 | }uartBuffer_t; 31 | 32 | /** 33 | * Inits the SERCOM2 and corrsponding Pins of the SAMR21 as a UART Debug Output 34 | */ 35 | void samr21Uart_init(); 36 | 37 | /** 38 | * Deinits the SERCOM2 of the SAMR21 39 | */ 40 | void samr21Uart_deinit(); 41 | 42 | 43 | /** 44 | * Sends a Single Character of data via the DEBUG-UART (SERCOM2) 45 | * 46 | * @param[in] data Character to be vie Debug UART 47 | */ 48 | void samr21Uart_sendByte(uint8_t data); 49 | 50 | 51 | /** 52 | * Allocates a Buffer to be filled by the Application 53 | * 54 | * The given Buffer is considered invalid until a Length is set. 55 | * So length should be set last when modifying the Buffer 56 | * 57 | * @returns a Pointer to a empty TransmitBuffer or NULL if none is available 58 | */ 59 | uartBuffer_t * samr21Uart_allocTransmitBuffer(void); 60 | 61 | /** 62 | * Queues up a given Byte Array to be transmitted asynchronously via the UART 63 | * 64 | * @param[in] data pointer to the ByteArray the supposed to be transmitted 65 | * @param[in] length length of the ByteArray supposed to be transmitted 66 | * 67 | * @returns num of bytes queued up for Transmission 68 | */ 69 | uint16_t samr21Uart_write(uint8_t * data, uint16_t length); 70 | 71 | /** 72 | * Checks for allocated AND VALID (length > 0) Transmit-Buffer and starts the DMA if needed 73 | */ 74 | void samr21Uart_checkForPendingTransmit(void); 75 | 76 | #endif //_SAMR21_UART_H_ 77 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/rfctrl.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for RFCTRL 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_RFCTRL_INSTANCE_ 35 | #define _SAMR21_RFCTRL_INSTANCE_ 36 | 37 | /* ========== Register definition for RFCTRL peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_RFCTRL_FECFG (0x42005400U) /**< \brief (RFCTRL) Front-end control bus configuration */ 40 | #else 41 | #define REG_RFCTRL_FECFG (*(RwReg16*)0x42005400U) /**< \brief (RFCTRL) Front-end control bus configuration */ 42 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 43 | 44 | /* ========== Instance parameters for RFCTRL peripheral ========== */ 45 | #define RFCTRL_FBUSMSB 5 46 | 47 | #endif /* _SAMR21_RFCTRL_INSTANCE_ */ 48 | -------------------------------------------------------------------------------- /.vscode/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | // Use IntelliSense to learn about possible attributes. 3 | // Hover to view descriptions of existing attributes. 4 | // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 5 | "version": "0.2.0", 6 | "configurations": [ 7 | { 8 | "name": "RCP Debug", 9 | "cwd": "${workspaceFolder}", 10 | "executable": "${workspaceFolder}/out/rcpDebug/bin/ot-rcp", 11 | "request": "launch", 12 | "type": "cortex-debug", 13 | "servertype": "openocd", 14 | "configFiles": [ "${workspaceFolder}/OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg" ], 15 | "gdbTarget": "localhost:3333", 16 | "gdbPath" : "${workspaceFolder}/gcc-arm-none-eabi/bin/arm-none-eabi-gdb", 17 | "toolchainPrefix" : "${workspaceFolder}/gcc-arm-none-eabi/bin/arm-none-eabi-", 18 | "preLaunchTask": "build RCP Debug" 19 | }, 20 | { 21 | "name": "RCP Debug Attach", 22 | "cwd": "${workspaceFolder}", 23 | "executable": "${workspaceFolder}/out/rcpDebug/bin/ot-rcp", 24 | "request": "attach", 25 | "type": "cortex-debug", 26 | "servertype": "openocd", 27 | "configFiles": [ "${workspaceFolder}/OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg" ], 28 | "gdbTarget": "localhost:3333", 29 | "gdbPath" : "${workspaceFolder}/gcc-arm-none-eabi/bin/arm-none-eabi-gdb", 30 | "toolchainPrefix" : "${workspaceFolder}/gcc-arm-none-eabi/bin/arm-none-eabi-", 31 | "preLaunchTask": "build RCP Debug" 32 | }, 33 | { 34 | "name": "ConBee Debug Attach", 35 | "cwd": "${workspaceFolder}", 36 | "executable": "${workspaceFolder}/out/rcpConbee2/bin/ot-rcp", 37 | "request": "attach", 38 | "type": "cortex-debug", 39 | "servertype": "openocd", 40 | "configFiles": [ "${workspaceFolder}/OpenOCD_config/ATMEL-ICE-OpenOCD-samr21e18a.cfg" ], 41 | "gdbTarget": "localhost:3333", 42 | "gdbPath" : "${workspaceFolder}/gcc-arm-none-eabi/bin/arm-none-eabi-gdb", 43 | "toolchainPrefix" : "${workspaceFolder}/gcc-arm-none-eabi/bin/arm-none-eabi-", 44 | } 45 | ] 46 | } -------------------------------------------------------------------------------- /src/HAL/samr21Usb.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #include "samr21Usb.h" 11 | 12 | void samr21Usb_init(){ 13 | 14 | //Enable in Power Manger 15 | PM->APBBMASK.bit.USB_ = 1; 16 | 17 | //Setup Ports for USB 18 | 19 | //Setup PIN PA24 as USB D- 20 | //Make Output 21 | PORT->Group[0].DIRSET.reg= PORT_PA24; 22 | 23 | //Setup Mux Settings 24 | PORT->Group[0].WRCONFIG.reg = 25 | PORT_WRCONFIG_HWSEL 26 | |PORT_WRCONFIG_WRPINCFG 27 | |PORT_WRCONFIG_WRPMUX 28 | |PORT_WRCONFIG_PMUX(MUX_PA24G_USB_DM) 29 | //|PORT_WRCONFIG_PULLEN 30 | //|PORT_WRCONFIG_INEN 31 | |PORT_WRCONFIG_PMUXEN 32 | |PORT_WRCONFIG_PINMASK(PORT_PA24 >> 16) //upper Halfword 33 | ; 34 | PORT->Group[0].OUTCLR.reg= PORT_PA24; 35 | 36 | //Setup PIN PA25 as USB D+ 37 | //Make Output 38 | PORT->Group[0].DIRSET.reg= PORT_PA25; 39 | 40 | //Setup Mux Settings 41 | PORT->Group[0].WRCONFIG.reg = 42 | PORT_WRCONFIG_HWSEL 43 | |PORT_WRCONFIG_WRPINCFG 44 | |PORT_WRCONFIG_WRPMUX 45 | |PORT_WRCONFIG_PMUX(MUX_PA25G_USB_DP) 46 | //|PORT_WRCONFIG_PULLEN 47 | //|PORT_WRCONFIG_INEN 48 | |PORT_WRCONFIG_PMUXEN 49 | |PORT_WRCONFIG_PINMASK(PORT_PA25 >> 16) //upper Halfword 50 | ; 51 | PORT->Group[0].OUTCLR.reg= PORT_PA25; 52 | 53 | __NVIC_EnableIRQ(USB_IRQn); 54 | } 55 | 56 | void samr21Usb_deinit(){ 57 | 58 | // Disable IRQ in NVIC 59 | __NVIC_DisableIRQ(USB_IRQn); 60 | 61 | USB->DEVICE.CTRLA.bit.ENABLE = 0; 62 | while (USB->DEVICE.CTRLA.bit.ENABLE); 63 | 64 | USB->DEVICE.CTRLA.bit.SWRST = 1; 65 | while (USB->DEVICE.SYNCBUSY.bit.SWRST); 66 | 67 | PM->APBBMASK.bit.USB_ = 0; 68 | } 69 | 70 | 71 | //--------------------------------------------------------------------+ 72 | // TINY USB 73 | //--------------------------------------------------------------------+ 74 | 75 | //IRQ Handler wrapper 76 | void dcd_int_handler (uint8_t rhport); 77 | void USB_Handler(){ 78 | dcd_int_handler(0); 79 | } 80 | 81 | -------------------------------------------------------------------------------- /src/HAL/include/samr21Dma.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2024 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | #ifndef _SAMR21_DMA_H_ 12 | #define _SAMR21_DMA_H_ 13 | 14 | #include "samr21.h" 15 | #include 16 | #include 17 | #include 18 | 19 | #ifndef SAMR21_NUM_DMA_CHANNEL 20 | #define SAMR21_NUM_DMA_CHANNEL 2 21 | #endif 22 | 23 | typedef void (*samr21Dma_done_cb)(void); 24 | 25 | 26 | 27 | /** 28 | * Inits the DMA Module 29 | * 30 | * Must be called before any DMA Action can take place 31 | * 32 | */ 33 | void samr21Dma_init(void); 34 | 35 | /** 36 | * Sets up a DMA Channel for Asynchronous memcpy to a Peripheral 37 | * 38 | * @param[in] channel channel used for the DMA Action (lower Channel have higher Priority) 39 | * @param[in] targetAddress address to the desired Peripheral DATA Register 40 | * @param[in] triggerSource trigger that initiates the transfer of a Single Byte 41 | * @param[in] callbackFunc function called after a DMA-Transaction is finished (can be NULL if none is used) 42 | * 43 | * @returns True if Channel was initted correctly 44 | * 45 | */ 46 | bool samr21Dma_initChannel(uint8_t channel, uint32_t targetAddress, uint8_t triggerSource, samr21Dma_done_cb callbackFunc); 47 | 48 | 49 | /** 50 | * Sets DMA Channel as Active, so it reacts to Trigger Events 51 | * 52 | * @param[in] channel channel used for the DMA Action (lower Channel have higher Priority) 53 | * @param[in] data pointer to the ByteArray the supposed to be copied 54 | * @param[in] dataLength length of the ByteArray supposed to be copied 55 | * @param[in] linkedDescriptor DMA Descriptor to a queued DMA-Job 56 | * 57 | * @returns True if Channel was activated 58 | * 59 | */ 60 | bool samr21Dma_activateChannel(uint8_t channel, uint8_t * data, uint32_t dataLength, DmacDescriptor * linkedDescriptor); 61 | 62 | 63 | /** 64 | * Forces a Trigger Event on specified DMA Channel 65 | * 66 | * Used to Jump-Start Transfers 67 | * 68 | * @param[in] channel channel thats supposed to be triggered 69 | */ 70 | void samr21Dma_triggerChannelAction(uint8_t channel); 71 | 72 | #endif //_SAMR21_DMA_H_ -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/pac0.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PAC0 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_PAC0_INSTANCE_ 35 | #define _SAMR21_PAC0_INSTANCE_ 36 | 37 | /* ========== Register definition for PAC0 peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */ 40 | #define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */ 41 | #else 42 | #define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */ 43 | #define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */ 44 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 45 | 46 | /* ========== Instance parameters for PAC0 peripheral ========== */ 47 | #define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset 48 | 49 | #endif /* _SAMR21_PAC0_INSTANCE_ */ 50 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/pac1.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PAC1 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_PAC1_INSTANCE_ 35 | #define _SAMR21_PAC1_INSTANCE_ 36 | 37 | /* ========== Register definition for PAC1 peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */ 40 | #define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */ 41 | #else 42 | #define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */ 43 | #define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */ 44 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 45 | 46 | /* ========== Instance parameters for PAC1 peripheral ========== */ 47 | #define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset 48 | 49 | #endif /* _SAMR21_PAC1_INSTANCE_ */ 50 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/pac2.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PAC2 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_PAC2_INSTANCE_ 35 | #define _SAMR21_PAC2_INSTANCE_ 36 | 37 | /* ========== Register definition for PAC2 peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */ 40 | #define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */ 41 | #else 42 | #define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */ 43 | #define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */ 44 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 45 | 46 | /* ========== Instance parameters for PAC2 peripheral ========== */ 47 | #define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset 48 | 49 | #endif /* _SAMR21_PAC2_INSTANCE_ */ 50 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/samr21.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Top header file for SAMR21 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_ 35 | #define _SAMR21_ 36 | 37 | /** 38 | * \defgroup SAMR21_definitions SAMR21 Device Definitions 39 | * \brief SAMR21 CMSIS Definitions. 40 | */ 41 | 42 | #if defined(__SAMR21E16A__) || defined(__ATSAMR21E16A__) 43 | #include "samr21e16a.h" 44 | #elif defined(__SAMR21E17A__) || defined(__ATSAMR21E17A__) 45 | #include "samr21e17a.h" 46 | #elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__) 47 | #include "samr21e18a.h" 48 | #elif defined(__SAMR21E19A__) || defined(__ATSAMR21E19A__) 49 | #include "samr21e19a.h" 50 | #elif defined(__SAMR21G16A__) || defined(__ATSAMR21G16A__) 51 | #include "samr21g16a.h" 52 | #elif defined(__SAMR21G17A__) || defined(__ATSAMR21G17A__) 53 | #include "samr21g17a.h" 54 | #elif defined(__SAMR21G18A__) || defined(__ATSAMR21G18A__) 55 | #include "samr21g18a.h" 56 | #else 57 | #error Library does not support the specified device. 58 | #endif 59 | 60 | #endif /* _SAMR21_ */ 61 | -------------------------------------------------------------------------------- /src/HAL/include/samr21Nvm.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #ifndef _SAMR21_NVM_H_ 11 | #define _SAMR21_NVM_H_ 12 | 13 | #include "samr21.h" 14 | #include "samr21At86rf233.h" 15 | #include 16 | #include 17 | 18 | #define SAMR21_NVM_NUM_PAGES 4096 19 | #define SAMR21_NVM_SIZE_PAGE 64 20 | #define SAMR21_NVM_PAGES_PER_ROW 4 21 | #define SAMR21_NVM_SIZE_ROW (SAMR21_NVM_PAGES_PER_ROW * SAMR21_NVM_SIZE_PAGE) 22 | 23 | #define SAMR21_NVM_USER_ROW_ADDR 0x00804000 24 | #define SAMR21_NVM_USER_ROW_IEEE_ADDR (SAMR21_NVM_USER_ROW_ADDR + 0x0000000A) 25 | #define SAMR21_NVM_USER_ROW_USB_I_SERIAL (SAMR21_NVM_USER_ROW_ADDR + 0x00000012) 26 | 27 | 28 | /** 29 | * Inits the NVM-Controller. Enables Manual Write and sets appropiate Wait States 30 | * See SAMR21 datasheet 20. NVMCTRL – Non-Volatile Memory Controller 31 | */ 32 | void samr21Nvm_init(); 33 | 34 | /** 35 | * Reads out the Unique IEEE 64Bit Extended Address from NVMEM to a given buffer 36 | * 37 | * @param[out] ieeeAddr pointer to Buffer where the address is written to 38 | */ 39 | void samr21Nvm_getIeeeAddr(uint8_t * ieeeAddr); 40 | 41 | 42 | /** 43 | * Reads a given NV-Memory Region for a specified Length and copys the data to a given Buffer 44 | * 45 | * @param[in] addr address when the NVMEM Read start 46 | * @param[in] len length of the data to be read 47 | * @param[out] buffer Pointer to Buffer where data is written to 48 | * 49 | * 50 | */ 51 | void samr21Nvm_readAt(uint32_t addr, uint8_t* buffer_p, uint32_t len); 52 | 53 | 54 | /** 55 | * Writes to a given location in NV-Memory 56 | * 57 | * @param[in] addr address when the NVMEM Write takes place 58 | * @param[in] len length of the data to be written 59 | * @param[out] buffer Pointer to data to be written into NVMEM 60 | * 61 | * 62 | */ 63 | void samr21Nvm_writeWithinRow(uint32_t addr, uint8_t* data_p, uint32_t len); 64 | 65 | /** 66 | * Erases the row a given location is part of 67 | * 68 | * @param[in] addr address within the row to be erased 69 | * 70 | */ 71 | void samr21NvmEraseRow(uint32_t addr); 72 | 73 | #endif //_SAMR21_PM_H_ -------------------------------------------------------------------------------- /third_party/CMSIS/r21/source/system_samr21.c: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Low-level initialization functions called upon chip startup. 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #include "samr21.h" 35 | 36 | /** 37 | * Initial system clock frequency. The System RC Oscillator (RCSYS) provides 38 | * the source for the main clock at chip startup. 39 | */ 40 | #define __SYSTEM_CLOCK (1000000) 41 | 42 | uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ 43 | 44 | /** 45 | * Initialize the system 46 | * 47 | * @brief Setup the microcontroller system. 48 | * Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | void SystemInit(void) 51 | { 52 | // Keep the default device state after reset 53 | SystemCoreClock = __SYSTEM_CLOCK; 54 | return; 55 | } 56 | 57 | /** 58 | * Update SystemCoreClock variable 59 | * 60 | * @brief Updates the SystemCoreClock with current core Clock 61 | * retrieved from cpu registers. 62 | */ 63 | void SystemCoreClockUpdate(void) 64 | { 65 | // Not implemented 66 | SystemCoreClock = __SYSTEM_CLOCK; 67 | return; 68 | } 69 | -------------------------------------------------------------------------------- /src/HAL/samr21Rtc.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #include "samr21Rtc.h" 11 | 12 | extern uint32_t g_currentRtcClkCycle_ns; 13 | 14 | void samr21Rtc_init() 15 | { 16 | //Enable RTC In Power Manger 17 | PM->APBAMASK.bit.RTC_ = 1; 18 | 19 | //Reset RTC first 20 | RTC->MODE0.CTRL.bit.SWRST = 1; 21 | 22 | //Wait for Reset to finish 23 | while(RTC->MODE0.CTRL.bit.SWRST || RTC->MODE0.STATUS.bit.SYNCBUSY); 24 | 25 | //Setup the RTC 26 | RTC->MODE0.CTRL.reg= 27 | RTC_MODE0_CTRL_PRESCALER(0x0) // 1 Mhz 28 | //|RTC_MODE0_CTRL_MATCHCLR 29 | |RTC_MODE0_CTRL_MODE(0x0) //COUNT 32Bit mode 30 | |RTC_MODE0_CTRL_ENABLE 31 | ; 32 | 33 | //Wait for Setup to finish 34 | while(RTC->MODE0.STATUS.bit.SYNCBUSY); 35 | 36 | //Force permanent Sync with COUT Register 37 | RTC->MODE0.READREQ.reg= 38 | RTC_READREQ_ADDR(RTC_MODE0_COUNT_OFFSET) 39 | |RTC_READREQ_RCONT 40 | ; 41 | } 42 | 43 | void samr21Rtc_deinit(){ 44 | //Disable IRQ 45 | NVIC_DisableIRQ(RTC_IRQn); 46 | 47 | if (RTC->MODE0.READREQ.bit.RCONT) 48 | { 49 | //Disable permanent Sync with COUT Register 50 | RTC->MODE0.READREQ.bit.RCONT = 0; 51 | while (RTC->MODE0.READREQ.bit.RCONT ); 52 | } 53 | 54 | if ( RTC->MODE0.CTRL.bit.ENABLE ){ 55 | RTC->MODE0.CTRL.bit.ENABLE = 0; 56 | while(RTC->MODE0.CTRL.bit.ENABLE || RTC->MODE0.STATUS.bit.SYNCBUSY); 57 | } 58 | } 59 | 60 | uint32_t samr21Rtc_getTimestamp(){ 61 | return RTC->MODE0.COUNT.reg; 62 | } 63 | 64 | void samr21Rtc_setAbsoluteAlarm(uint32_t a_alarmTimestamp){ 65 | RTC->MODE0.COMP[0].reg = a_alarmTimestamp; 66 | RTC->MODE0.INTFLAG.bit.CMP0 = 1; 67 | RTC->MODE0.INTENSET.bit.CMP0 = 1; 68 | NVIC_EnableIRQ(RTC_IRQn); 69 | } 70 | 71 | void samr21Rtc_setRelativeAlarm(uint32_t a_duration){ 72 | RTC->MODE0.COMP[0].reg = samr21Rtc_getTimestamp() + a_duration; 73 | RTC->MODE0.INTFLAG.bit.CMP0 = 1; 74 | RTC->MODE0.INTENSET.bit.CMP0 = 1; 75 | NVIC_EnableIRQ(RTC_IRQn); 76 | } 77 | 78 | void samr21Rtc_disableAlarm(){ 79 | NVIC_DisableIRQ(RTC_IRQn); 80 | RTC->MODE0.INTFLAG.bit.CMP0 = 1; 81 | RTC->MODE0.INTENCLR.bit.CMP0 = 1; 82 | } 83 | 84 | -------------------------------------------------------------------------------- /third_party/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CC=../gcc-arm-none-eabi/bin/arm-none-eabi-gcc 3 | CXX=../gcc-arm-none-eabi/bin/arm-none-eabi-g++ 4 | ASM=../gcc-arm-none-eabi/bin/arm-none-eabi-as 5 | GDB=../gcc-arm-none-eabi/bin/arm-none-eabi-gdb 6 | MKDIR=mkdir 7 | 8 | MACH=cortex-m0plus 9 | 10 | OPT=-O0 11 | 12 | TINYUSB_OUT_DIR=../out/tinyUSB 13 | CMSIS_OUT_DIR=../out/CMSIS_Startup 14 | 15 | CMSIS_DEVICE_DIR=./CMSIS/r21 16 | CMSIS_CORE_DIR=./CMSIS/core 17 | 18 | TINYUSB_SRC_DIR=./tinyusb/src 19 | TINYUSB_MOD_SRC_DIR=./tinyusb_modified/src 20 | TINYUSB_CONF_DIR=./tinyusb_config 21 | 22 | INCDIRS= \ 23 | -I. \ 24 | -I$(CMSIS_DEVICE_DIR)/include \ 25 | -I$(CMSIS_DEVICE_DIR)/source \ 26 | -I$(CMSIS_CORE_DIR) \ 27 | -I$(TINYUSB_SRC_DIR) \ 28 | -I$(TINYUSB_CONF_DIR) 29 | 30 | DEFINES= -D__SAMR21E18A__ 31 | 32 | CFLAGS= \ 33 | -c \ 34 | -g \ 35 | -mcpu=$(MACH) \ 36 | --specs=nosys.specs \ 37 | -mfloat-abi=soft \ 38 | -mthumb \ 39 | -std=gnu99 \ 40 | -Wall \ 41 | $(OPT) \ 42 | $(INCDIRS) \ 43 | $(DEFINES) 44 | 45 | all:tinyUSB CMSIS_Startup 46 | 47 | tinyUSB:\ 48 | $(TINYUSB_OUT_DIR) \ 49 | $(TINYUSB_OUT_DIR)/tusb.o \ 50 | $(TINYUSB_OUT_DIR)/usbd.o \ 51 | $(TINYUSB_OUT_DIR)/usbd_control.o \ 52 | $(TINYUSB_OUT_DIR)/tusb_fifo.o \ 53 | $(TINYUSB_OUT_DIR)/cdc_device.o \ 54 | $(TINYUSB_OUT_DIR)/usb_descriptors.o \ 55 | $(TINYUSB_OUT_DIR)/dcd_samr.o 56 | 57 | CMSIS_Startup:\ 58 | $(CMSIS_OUT_DIR) \ 59 | $(CMSIS_OUT_DIR)/system_samr21.o \ 60 | $(CMSIS_OUT_DIR)/startup_samr21.o \ 61 | 62 | 63 | $(TINYUSB_OUT_DIR): 64 | $(MKDIR) -p $@ 65 | 66 | $(CMSIS_OUT_DIR): 67 | $(MKDIR) -p $@ 68 | 69 | $(TINYUSB_OUT_DIR)/tusb.o:\ 70 | $(TINYUSB_SRC_DIR)/tusb.c 71 | $(CC) $(CFLAGS) -o $@ $^ 72 | 73 | $(TINYUSB_OUT_DIR)/usbd.o:\ 74 | $(TINYUSB_SRC_DIR)/device/usbd.c 75 | $(CC) $(CFLAGS) -o $@ $^ 76 | 77 | $(TINYUSB_OUT_DIR)/usbd_control.o:\ 78 | $(TINYUSB_SRC_DIR)/device/usbd_control.c 79 | $(CC) $(CFLAGS) -o $@ $^ 80 | 81 | $(TINYUSB_OUT_DIR)/tusb_fifo.o:\ 82 | $(TINYUSB_SRC_DIR)/common/tusb_fifo.c 83 | $(CC) $(CFLAGS) -o $@ $^ 84 | 85 | $(TINYUSB_OUT_DIR)/cdc_device.o:\ 86 | $(TINYUSB_SRC_DIR)/class/cdc/cdc_device.c 87 | $(CC) $(CFLAGS) -o $@ $^ 88 | 89 | $(TINYUSB_OUT_DIR)/usb_descriptors.o:\ 90 | $(TINYUSB_CONF_DIR)/usb_descriptors.c 91 | $(CC) $(CFLAGS) -o $@ $^ 92 | 93 | $(TINYUSB_OUT_DIR)/dcd_samr.o:\ 94 | $(TINYUSB_MOD_SRC_DIR)/portable/microchip/samr/dcd_samr.c 95 | $(CC) $(CFLAGS) -o $@ $^ 96 | 97 | 98 | $(CMSIS_OUT_DIR)/system_samr21.o:\ 99 | $(CMSIS_DEVICE_DIR)/source/system_samr21.c 100 | $(CC) $(CFLAGS) -o $@ $^ 101 | 102 | $(CMSIS_OUT_DIR)/startup_samr21.o:\ 103 | $(CMSIS_DEVICE_DIR)/source/gcc/startup_samr21.c 104 | $(CC) $(CFLAGS) -o $@ $^ 105 | 106 | 107 | clean: 108 | rm -rf $(CMSIS_OUT_DIR) 109 | rm -rf $(TINYUSB_OUT_DIR) 110 | 111 | -------------------------------------------------------------------------------- /third_party/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | add_library(samr21-CMSIS 3 | ${PROJECT_SOURCE_DIR}/third_party/CMSIS/r21/source/system_samr21.c 4 | ${PROJECT_SOURCE_DIR}/third_party/CMSIS/r21/source/gcc/startup_samr21.c 5 | ) 6 | 7 | add_library(samr21-tusb 8 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb/src/tusb.c 9 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb/src/device/usbd.c 10 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb/src/device/usbd_control.c 11 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb/src/common/tusb_fifo.c 12 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb/src/class/cdc/cdc_device.c 13 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb_config/usb_descriptors.c 14 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb_modified/src/portable/microchip/samr/dcd_samr.c 15 | ) 16 | 17 | target_include_directories(samr21-tusb 18 | PUBLIC 19 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb/src 20 | ${PROJECT_SOURCE_DIR}/third_party/tinyusb_config 21 | ) 22 | 23 | target_include_directories(samr21-CMSIS 24 | PUBLIC 25 | ${PROJECT_SOURCE_DIR}/third_party/CMSIS/r21/source 26 | ${PROJECT_SOURCE_DIR}/third_party/CMSIS/r21/include 27 | ${PROJECT_SOURCE_DIR}/third_party/CMSIS/core 28 | ${PROJECT_SOURCE_DIR}/third_party/ATMEL/LINKER 29 | ${PROJECT_SOURCE_DIR}/third_party/ATMEL/AT86RF233 30 | ) 31 | 32 | if(OT_CFLAGS MATCHES "-pedantic-errors") 33 | string(REPLACE "-pedantic-errors" "" OT_CFLAGS "${OT_CFLAGS}") 34 | endif() 35 | 36 | 37 | set(SAMR21_PLATFORM_DEFINES "__SAMR21G18A__") 38 | 39 | if(TARGET_DEVICE STREQUAL "CONBEE2") 40 | list(APPEND SAMR21_PLATFORM_DEFINES "TARGET_DEVICE=CONBEE2") 41 | elseif(TARGET_DEVICE STREQUAL "RASPBEE2") 42 | list(APPEND SAMR21_PLATFORM_DEFINES "TARGET_DEVICE=RASPBEE2") 43 | endif() 44 | 45 | if(DDEL_GCF_BUILD) 46 | message("Building with GCF Offset") 47 | target_link_libraries(samr21-CMSIS 48 | PUBLIC 49 | -T${PROJECT_SOURCE_DIR}/third_party/ATMEL/LINKER/samr21e18a_flash_gcf_offset.ld 50 | PRIVATE 51 | ot-config 52 | ) 53 | list(APPEND SAMR21_PLATFORM_DEFINES "GCF_BUILD=1") 54 | else() 55 | target_link_libraries(samr21-CMSIS 56 | PUBLIC 57 | -T${PROJECT_SOURCE_DIR}/third_party/ATMEL/LINKER/samr21e18a_flash.ld 58 | PRIVATE 59 | ot-config 60 | ) 61 | endif() 62 | 63 | target_compile_definitions(samr21-CMSIS 64 | PUBLIC 65 | ${OT_PLATFORM_DEFINES} 66 | ${SAMR21_PLATFORM_DEFINES} 67 | ) 68 | 69 | target_link_libraries(samr21-tusb 70 | PRIVATE 71 | samr21-CMSIS 72 | ot-config 73 | openthread-r21 74 | ) 75 | 76 | message("OT DEFINES ${OT_PLATFORM_DEFINES}") 77 | message("TARGET_DEVICE ${TARGET_DEVICE}") 78 | message("PLATFORM DEFINES ${SAMR21_PLATFORM_DEFINES}") 79 | 80 | target_compile_definitions(samr21-tusb 81 | PUBLIC 82 | ${OT_PLATFORM_DEFINES} 83 | ${SAMR21_PLATFORM_DEFINES} 84 | ) 85 | -------------------------------------------------------------------------------- /src/OT-Utils/include/otUtilities_sourceMatch.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019, The OpenThread Authors. 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 3. Neither the name of the copyright holder nor the 13 | * names of its contributors may be used to endorse or promote products 14 | * derived from this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 | * POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | /** 30 | * @file 31 | * @brief 32 | * This file defines the software source match table interfaces used by 33 | * soft_source_match_table.c. 34 | */ 35 | 36 | #ifndef SOFT_SOURCE_MATCH_TABLE_H 37 | #define SOFT_SOURCE_MATCH_TABLE_H 38 | 39 | #include "openthread-core-config.h" 40 | #include 41 | 42 | #include 43 | 44 | #ifdef __cplusplus 45 | extern "C" { 46 | #endif 47 | 48 | #ifndef RADIO_CONFIG_SRC_MATCH_SHORT_ENTRY_NUM 49 | #define RADIO_CONFIG_SRC_MATCH_SHORT_ENTRY_NUM OPENTHREAD_CONFIG_MLE_MAX_CHILDREN 50 | #endif 51 | 52 | #ifndef RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM 53 | #define RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM OPENTHREAD_CONFIG_MLE_MAX_CHILDREN 54 | #endif 55 | 56 | #if RADIO_CONFIG_SRC_MATCH_SHORT_ENTRY_NUM || RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM 57 | void utilsSoftSrcMatchSetPanId(uint16_t aPanId); 58 | #endif // RADIO_CONFIG_SRC_MATCH_SHORT_ENTRY_NUM || RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM 59 | 60 | #if RADIO_CONFIG_SRC_MATCH_SHORT_ENTRY_NUM 61 | int16_t utilsSoftSrcMatchShortFindEntry(uint16_t aShortAddress); 62 | #endif // RADIO_CONFIG_SRC_MATCH_SHORT_ENTRY_NUM 63 | 64 | #if RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM 65 | int16_t utilsSoftSrcMatchExtFindEntry(const otExtAddress *aExtAddress); 66 | #endif // RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM 67 | 68 | #ifdef __cplusplus 69 | } // extern "C" 70 | #endif 71 | 72 | #endif // SOFT_SOURCE_MATCH_TABLE_H 73 | -------------------------------------------------------------------------------- /src/OT-HAL/otFlash.c: -------------------------------------------------------------------------------- 1 | // Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | 3 | #include "openthread/platform/radio.h" 4 | #include "samr21Nvm.h" 5 | 6 | #ifdef _DEBUG 7 | #include 8 | #endif 9 | 10 | 11 | #if defined(TARGET_DEVICE) && (TARGET_DEVICE == CONBEE2) 12 | #define SAMR21_OT_NVM_ROWS 14 13 | #else 14 | #define SAMR21_OT_NVM_ROWS 16 15 | #endif 16 | 17 | #define SAMR21_OT_SWAP_SIZE ((SAMR21_OT_NVM_ROWS * SAMR21_NVM_SIZE_ROW) / 2) 18 | 19 | 20 | //From Linker Script 21 | extern uint32_t _snvmem; 22 | 23 | 24 | void otPlatFlashInit(otInstance *a_instance){ 25 | OT_UNUSED_VARIABLE(a_instance); 26 | } 27 | 28 | uint32_t otPlatFlashGetSwapSize(otInstance *a_instance){ 29 | OT_UNUSED_VARIABLE(a_instance); 30 | 31 | //Flash is Split into 2 Swap Areas 32 | return SAMR21_OT_SWAP_SIZE; 33 | } 34 | 35 | 36 | void otPlatFlashErase(otInstance *a_instance, uint8_t a_swapIndex){ 37 | OT_UNUSED_VARIABLE(a_instance); 38 | 39 | #ifdef _DEBUG 40 | assert(a_SwapIndex <= 1) 41 | #endif 42 | 43 | uint32_t swapBaseAddress = &_snvmem; 44 | 45 | if(a_swapIndex){ 46 | swapBaseAddress += SAMR21_OT_SWAP_SIZE; 47 | } 48 | 49 | for (uint8_t i = 0; i < (SAMR21_OT_NVM_ROWS / 2); i++) 50 | { 51 | samr21Nvm_eraseRowAt( swapBaseAddress + (SAMR21_NVM_SIZE_ROW * i)); 52 | } 53 | } 54 | 55 | void otPlatFlashRead(otInstance *a_instance, uint8_t a_swapIndex, uint32_t a_offset, void *a_data_p, uint32_t a_size){ 56 | OT_UNUSED_VARIABLE(a_instance); 57 | 58 | #ifdef _DEBUG 59 | assert(a_SwapIndex <= 1) 60 | #endif 61 | 62 | uint32_t swapBaseAddress = &_snvmem; 63 | 64 | if(a_swapIndex){ 65 | swapBaseAddress += SAMR21_OT_SWAP_SIZE; 66 | } 67 | 68 | samr21Nvm_readAt(swapBaseAddress+a_offset, a_data_p, a_size); 69 | } 70 | 71 | void otPlatFlashWrite(otInstance *a_instance, uint8_t a_swapIndex, uint32_t a_offset, const void *a_data_p, uint32_t a_size){ 72 | OT_UNUSED_VARIABLE(a_instance); 73 | 74 | #ifdef _DEBUG 75 | assert(a_SwapIndex <= 1) 76 | #endif 77 | 78 | uint32_t swapBaseAddress = &_snvmem; 79 | 80 | if(a_swapIndex){ 81 | swapBaseAddress += SAMR21_OT_SWAP_SIZE; 82 | } 83 | 84 | uint32_t rowOffset = a_offset % (SAMR21_NVM_SIZE_PAGE * SAMR21_NVM_PAGES_PER_ROW); 85 | 86 | if( SAMR21_NVM_SIZE_ROW - rowOffset >= a_size){ 87 | samr21Nvm_writeWithinRow(swapBaseAddress + a_offset, a_data_p, a_size); 88 | return; 89 | } 90 | 91 | samr21Nvm_writeWithinRow(swapBaseAddress + a_offset, a_data_p, SAMR21_NVM_SIZE_ROW - rowOffset); 92 | 93 | uint32_t bytesWritten = SAMR21_NVM_SIZE_ROW - rowOffset; 94 | 95 | while ( bytesWritten < a_size) 96 | { 97 | uint16_t sizeNextWriteBlock = (a_size - bytesWritten > SAMR21_NVM_SIZE_ROW ? SAMR21_NVM_SIZE_ROW : a_size - bytesWritten); 98 | samr21Nvm_writeWithinRow( 99 | swapBaseAddress + a_offset + bytesWritten, 100 | a_data_p + bytesWritten, 101 | sizeNextWriteBlock 102 | ); 103 | 104 | bytesWritten += sizeNextWriteBlock; 105 | } 106 | } -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/wdt.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for WDT 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_WDT_INSTANCE_ 35 | #define _SAMR21_WDT_INSTANCE_ 36 | 37 | /* ========== Register definition for WDT peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */ 40 | #define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */ 41 | #define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ 42 | #define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ 43 | #define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ 44 | #define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ 45 | #define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */ 46 | #define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */ 47 | #else 48 | #define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */ 49 | #define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */ 50 | #define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ 51 | #define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ 52 | #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ 53 | #define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ 54 | #define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */ 55 | #define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */ 56 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 | 58 | /* ========== Instance parameters for WDT peripheral ========== */ 59 | #define WDT_GCLK_ID 3 // Index of Generic Clock 60 | 61 | #endif /* _SAMR21_WDT_INSTANCE_ */ 62 | -------------------------------------------------------------------------------- /src/OT-Utils/include/otUtilities_codeUtils.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2017, The OpenThread Authors. 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 3. Neither the name of the copyright holder nor the 13 | * names of its contributors may be used to endorse or promote products 14 | * derived from this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 | * POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | /** 30 | * @file 31 | * This file includes macros for validating runtime conditions. 32 | */ 33 | 34 | #ifndef CODE_UTILS_H 35 | #define CODE_UTILS_H 36 | 37 | /** 38 | * This checks for the specified condition, which is expected to 39 | * commonly be true, and branches to the local label 'exit' if the 40 | * condition is false. 41 | * 42 | * @param[in] aCondition A Boolean expression to be evaluated. 43 | * 44 | */ 45 | #define otEXPECT(aCondition) \ 46 | do \ 47 | { \ 48 | if (!(aCondition)) \ 49 | { \ 50 | goto exit; \ 51 | } \ 52 | } while (0) 53 | 54 | /** 55 | * This checks for the specified condition, which is expected to 56 | * commonly be true, and both executes @p anAction and branches to 57 | * the local label 'exit' if the condition is false. 58 | * 59 | * @param[in] aCondition A Boolean expression to be evaluated. 60 | * @param[in] aAction An expression or block to execute when the 61 | * assertion fails. 62 | * 63 | */ 64 | #define otEXPECT_ACTION(aCondition, aAction) \ 65 | do \ 66 | { \ 67 | if (!(aCondition)) \ 68 | { \ 69 | aAction; \ 70 | goto exit; \ 71 | } \ 72 | } while (0) 73 | 74 | /** 75 | * This macro calculates the number of elements in an array. 76 | * 77 | * @param[in] aArray Name of the array variable. 78 | * 79 | * @returns Number of elements in the array. 80 | * 81 | */ 82 | #define otARRAY_LENGTH(aArray) (sizeof(aArray) / sizeof(aArray[0])) 83 | 84 | #endif // CODE_UTILS_H 85 | -------------------------------------------------------------------------------- /src/OT-HAL/otPlatAlarm.c: -------------------------------------------------------------------------------- 1 | //Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | #include "openthread/platform/alarm-milli.h" 3 | #include "openthread/platform/alarm-micro.h" 4 | 5 | #include "otPlatSystemHeader.h" 6 | 7 | #include "samr21Timer.h" 8 | #include "samr21Rtc.h" 9 | 10 | #define MICRO_SECS_PER_MILLI_SEC 1000 11 | 12 | static otInstance *s_instance = NULL; 13 | 14 | static struct otPlatAlarmVars_s 15 | { 16 | otInstance *instance; 17 | 18 | bool millisAlarmArmed; 19 | bool microsAlarmArmed; 20 | 21 | }s_otPlatAlarmVars; 22 | 23 | 24 | 25 | 26 | void otPlatAlarmMilliStartAt(otInstance *a_instance, uint32_t a_t0_ms, uint32_t a_dT_ms) 27 | { 28 | s_otPlatAlarmVars.instance = a_instance; 29 | 30 | uint32_t now_ms = samr21Rtc_getTimestamp() / MICRO_SECS_PER_MILLI_SEC; 31 | 32 | uint32_t offset_ms = now_ms - a_t0_ms; 33 | 34 | s_otPlatAlarmVars.millisAlarmArmed = true; 35 | samr21Timer2_startOneshot( a_dT_ms - offset_ms); 36 | } 37 | 38 | void otPlatAlarmMicroStartAt(otInstance *a_Instance, uint32_t a_t0_ms, uint32_t a_dT_ms) 39 | { 40 | s_otPlatAlarmVars.instance = a_Instance; 41 | 42 | uint32_t now_ms = samr21Rtc_getTimestamp(); 43 | 44 | uint32_t offset_ms = now_ms - a_t0_ms; 45 | 46 | s_otPlatAlarmVars.microsAlarmArmed = true; 47 | samr21Timer1_startOneshot( a_dT_ms - ( samr21Rtc_getTimestamp() - a_t0_ms ) ); 48 | } 49 | 50 | void otPlatAlarmMilliStop(otInstance *a_Instance) 51 | { 52 | s_otPlatAlarmVars.instance = a_Instance; 53 | samr21Timer2_stop(); 54 | 55 | s_otPlatAlarmVars.millisAlarmArmed = false; 56 | } 57 | 58 | void otPlatAlarmMicroStop(otInstance *a_Instance) 59 | { 60 | s_otPlatAlarmVars.instance = a_Instance; 61 | samr21Timer1_stop(); 62 | 63 | s_otPlatAlarmVars.microsAlarmArmed = false; 64 | } 65 | 66 | uint32_t otPlatAlarmMilliGetNow(void) 67 | { 68 | return samr21Rtc_getTimestamp() / MICRO_SECS_PER_MILLI_SEC; 69 | } 70 | 71 | uint32_t otPlatAlarmMicroGetNow(void) 72 | { 73 | return samr21Rtc_getTimestamp(); 74 | } 75 | 76 | // void TCC1_Handler(){ 77 | // TCC1->INTFLAG.bit.OVF = 1; 78 | 79 | // if(s_instance){ 80 | // otPlatAlarmMicroFired(s_instance); 81 | // } 82 | // } 83 | 84 | // void TCC2_Handler(){ 85 | // TCC2->INTFLAG.bit.OVF = 1; 86 | 87 | // if(s_instance){ 88 | // otPlatAlarmMilliFired(s_instance); 89 | // } 90 | // } 91 | 92 | void samr21OtPlat_alarmInit(void) 93 | { 94 | //TCC1 Used by OT Micros Alarm 95 | samr21Timer1_init(0,true,false); // 1MHz / (2^0) -> 1us resolution 96 | //TCC2 Used by OT Millis Alarm 97 | samr21Timer2_init(7, true,false); // 1MHz / (2^7) -> ~1ms resolution 98 | } 99 | 100 | void samr21OtPlat_alarmTask(void) 101 | { 102 | if (TCC1->INTFLAG.bit.OVF) 103 | { 104 | //Clear Trigger Flag 105 | TCC1->INTFLAG.bit.OVF = 1; 106 | 107 | if(s_otPlatAlarmVars.microsAlarmArmed) 108 | { 109 | s_otPlatAlarmVars.microsAlarmArmed = false; 110 | 111 | //Inform OT 112 | otPlatAlarmMicroFired(s_otPlatAlarmVars.instance); 113 | } 114 | } 115 | 116 | if(TCC2->INTFLAG.bit.OVF) 117 | { 118 | //Clear Trigger Flag 119 | TCC2->INTFLAG.bit.OVF = 1; 120 | 121 | if(s_otPlatAlarmVars.millisAlarmArmed) 122 | { 123 | s_otPlatAlarmVars.millisAlarmArmed = false; 124 | 125 | //Inform OT 126 | otPlatAlarmMilliFired(s_otPlatAlarmVars.instance); 127 | } 128 | } 129 | } -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/gclk.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for GCLK 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_GCLK_INSTANCE_ 35 | #define _SAMR21_GCLK_INSTANCE_ 36 | 37 | /* ========== Register definition for GCLK peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */ 40 | #define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */ 41 | #define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ 42 | #define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ 43 | #define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ 44 | #else 45 | #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */ 46 | #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */ 47 | #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */ 48 | #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */ 49 | #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */ 50 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 | 52 | /* ========== Instance parameters for GCLK peripheral ========== */ 53 | #define GCLK_GENDIV_BITS 16 54 | #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators 55 | #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 56 | #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 57 | #define GCLK_NUM 37 // Number of Generic Clock Users 58 | #define GCLK_SOURCE_DFLL48M 7 59 | #define GCLK_SOURCE_FDPLL 8 60 | #define GCLK_SOURCE_GCLKGEN1 2 61 | #define GCLK_SOURCE_GCLKIN 1 62 | #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources 63 | #define GCLK_SOURCE_OSCULP32K 3 64 | #define GCLK_SOURCE_OSC8M 6 65 | #define GCLK_SOURCE_OSC32K 4 66 | #define GCLK_SOURCE_XOSC 0 67 | #define GCLK_SOURCE_XOSC32K 5 68 | 69 | #endif /* _SAMR21_GCLK_INSTANCE_ */ 70 | -------------------------------------------------------------------------------- /src/HAL/samr21Nvm.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | #include "samr21Nvm.h" 11 | 12 | 13 | #ifdef _DEBUG 14 | #include 15 | #endif 16 | 17 | void samr21Nvm_init() 18 | { 19 | PM->APBBMASK.bit.NVMCTRL_ =1; 20 | PM->AHBMASK.bit.NVMCTRL_ = 1; 21 | 22 | NVMCTRL->CTRLB.reg = 23 | NVMCTRL_CTRLB_RWS(NVMCTRL_CTRLB_RWS_HALF_Val) // Configure 2 Wait-States 24 | | NVMCTRL_CTRLB_MANW // Enable Manual Write 25 | | NVMCTRL_CTRLB_SLEEPPRM(NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val) | NVMCTRL_CTRLB_READMODE(NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val) 26 | //|NVMCTRL_CTRLB_CACHEDIS //enable vmw caching 27 | ; 28 | } 29 | 30 | void samr21Nvm_execCtrlCommand(uint8_t a_cmd) 31 | { 32 | 33 | NVMCTRL->CTRLA.reg = 34 | NVMCTRL_CTRLA_CMD(a_cmd) | NVMCTRL_CTRLA_CMDEX(NVMCTRL_CTRLA_CMDEX_KEY_Val); 35 | 36 | while (!NVMCTRL->INTFLAG.bit.READY) 37 | { 38 | #ifdef _DEBUG 39 | assert(!NVMCTRL->INTFLAG.bit.ERROR); 40 | assert(!NVMCTRL->STATUS.bit.PROGE); 41 | assert(!NVMCTRL->STATUS.bit.NVME); 42 | assert(!NVMCTRL->STATUS.bit.LOCKE); 43 | #endif 44 | } 45 | } 46 | 47 | void samr21Nvm_getIeeeAddr(uint8_t * a_ieeeAddr) 48 | { 49 | samr21Nvm_readAt(SAMR21_NVM_USER_ROW_IEEE_ADDR, a_ieeeAddr, IEEE_15_4_EXTENDED_ADDR_SIZE); 50 | } 51 | 52 | void samr21Nvm_readAt(uint32_t a_addr, uint8_t *a_buffer_p, uint32_t a_len) 53 | { 54 | for (uint32_t i = 0; i < a_len; i++) 55 | { 56 | a_buffer_p[i] = ((uint8_t *)a_addr)[i]; 57 | } 58 | } 59 | 60 | void samr21Nvm_writeWithinRow(uint32_t a_addr, uint8_t *a_data_p, uint32_t a_len) 61 | { 62 | 63 | uint32_t rowOffset = a_addr % (SAMR21_NVM_SIZE_PAGE * SAMR21_NVM_PAGES_PER_ROW); 64 | 65 | #ifdef _DEBUG 66 | assert(rowOffset + a_len <= (SAMR21_NVM_SIZE_PAGE * SAMR21_NVM_PAGES_PER_ROW)); 67 | #endif 68 | 69 | uint32_t rowBaseAddr = a_addr - rowOffset; 70 | 71 | // Copy the Row which contains the addr to be written to 72 | // The whole row has to be erased in order to write to it 73 | uint32_t copyOfRow[SAMR21_NVM_PAGES_PER_ROW * (SAMR21_NVM_SIZE_PAGE / sizeof(uint32_t))]; 74 | 75 | for (uint16_t i = 0; i < ( SAMR21_NVM_PAGES_PER_ROW * (SAMR21_NVM_SIZE_PAGE / sizeof(uint32_t ) ) ); i++) 76 | { 77 | copyOfRow[i] = *( ( uint32_t * )( rowBaseAddr + ( i * sizeof(uint32_t) ) ) ); 78 | } 79 | 80 | // Erase the row containing the data to be written 81 | NVMCTRL->ADDR.reg = rowBaseAddr >> 1; 82 | samr21Nvm_execCtrlCommand(NVMCTRL_CTRLA_CMD_ER_Val); 83 | 84 | // Modify the data in Question 85 | memcpy( ( ( uint8_t * )( copyOfRow ) + rowOffset ), a_data_p, a_len ); 86 | 87 | // Write back the modified row page by page 88 | for (uint16_t i = 0; i < SAMR21_NVM_PAGES_PER_ROW; i++) 89 | { 90 | 91 | // Clear Page Cache 92 | samr21Nvm_execCtrlCommand(NVMCTRL_CTRLA_CMD_PBC_Val); 93 | 94 | // Write changes to Page Cache (Addr is the normal memory mapped NVM-Addr) 95 | for ( uint16_t j = 0; j < ( SAMR21_NVM_SIZE_PAGE / sizeof(uint32_t ) ); j++ ) 96 | { 97 | uint32_t *tempPtr = (uint32_t *)(rowBaseAddr + (i * SAMR21_NVM_SIZE_PAGE) + j * sizeof(uint32_t)); 98 | uint32_t tempVal = copyOfRow[ ( i * ( SAMR21_NVM_SIZE_PAGE / sizeof(uint32_t) ) ) + j ]; 99 | 100 | *tempPtr = tempVal; 101 | } 102 | // Write to Page Cache to Flash 103 | samr21Nvm_execCtrlCommand(NVMCTRL_CTRLA_CMD_WP_Val); 104 | } 105 | } 106 | 107 | void samr21Nvm_eraseRowAt(uint32_t a_addr) 108 | { 109 | // Erase the row containing the addr given 110 | NVMCTRL->ADDR.reg = a_addr >> 1; 111 | samr21Nvm_execCtrlCommand(NVMCTRL_CTRLA_CMD_ER_Val); 112 | } -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "files.associations": { 3 | "alarm-milli.h": "c", 4 | "otplatsystemheader.h": "c", 5 | "entropy.h": "c", 6 | "at86rf233_bitfield.h": "c", 7 | "stdint.h": "c", 8 | "samr21trx.h": "c", 9 | "samr21rtc.h": "c", 10 | "samr21nvm.h": "c", 11 | "samr21powermanager.h": "c", 12 | "samr21nopdelay.h": "c", 13 | "samr21radio.h": "c", 14 | "samr21timer.h": "c", 15 | "string.h": "c", 16 | "802_15_4_helper.h": "c", 17 | "uart.h": "c", 18 | "samr21.h": "c", 19 | "at86rf233.h": "c", 20 | "stdbool.h": "c", 21 | "samr21aes.h": "c", 22 | "samr21radiofsm.h": "c", 23 | "stddef.h": "c", 24 | "samr21radioaddrmatch.h": "c", 25 | "samr21radioedhandler.h": "c", 26 | "samr21radiotrxregcopy.h": "c", 27 | "samr21radioirqhandler.h": "c", 28 | "samr21radiobuffer.h": "c", 29 | "samr21radioctrl.h": "c", 30 | "samr21radioparser.h": "c", 31 | "samr21radiovars.h": "c", 32 | "otultilwrapper_macframe.h": "c", 33 | "radio.h": "c", 34 | "samr21radiotxhandler.h": "c", 35 | "samr21radiorxhandler.h": "c", 36 | "soft_source_match_table.h": "c", 37 | "misc.h": "c", 38 | "type_traits": "cpp", 39 | "samr21radioaes.h": "c", 40 | "alarm-micro.h": "c", 41 | "instance.h": "c", 42 | "otutilwrapper_macframe.h": "c", 43 | "samr21radiofectrl.h": "c", 44 | "samr21usb.h": "c", 45 | "dcd.h": "c", 46 | "tusb.h": "c", 47 | "cdc_device.h": "c", 48 | "tusb_common.h": "c", 49 | "tusb_fifo.h": "c", 50 | "samr21at86rf233.h": "c", 51 | "otutilities_linkmetrics.h": "c", 52 | "otutilities_macframe.h": "c", 53 | "otutilities_sourcematch.h": "c", 54 | "code_utils.h": "c", 55 | "link_metrics.h": "c", 56 | "samr21e16a.h": "c", 57 | "samr21e18a.h": "c", 58 | "samr21g17a.h": "c", 59 | "samr21g18a.h": "c", 60 | "system_samr21.h": "c", 61 | "stat.h": "c", 62 | "samr21clock.h": "c", 63 | "samr21debugpins.h": "c", 64 | "usbh.h": "c", 65 | "usbd.h": "c", 66 | "samr21uart.h": "c", 67 | "*.tcc": "cpp", 68 | "optional": "cpp", 69 | "istream": "cpp", 70 | "ostream": "cpp", 71 | "ratio": "cpp", 72 | "system_error": "cpp", 73 | "array": "cpp", 74 | "functional": "cpp", 75 | "regex": "cpp", 76 | "tuple": "cpp", 77 | "utility": "cpp", 78 | "variant": "cpp", 79 | "expected": "cpp", 80 | "compare": "c", 81 | "cstdint": "c", 82 | "format": "c", 83 | "cstdio": "c", 84 | "*.def": "c", 85 | "*.ipp": "c", 86 | "otutilities_codeutils.h": "c", 87 | "otutilities_uart.h": "c", 88 | "samr21systick.h": "c", 89 | "fifobuffer_t.h": "c", 90 | "logging.h": "c", 91 | "samr21fectrl.h": "c" 92 | }, 93 | "cmake.configureOnOpen": false, 94 | "cortex-debug.variableUseNaturalFormat": true, 95 | "cSpell.words": [ 96 | "Framebuffer", 97 | "Pdsu", 98 | "RSSI", 99 | "SAMR", 100 | "Sercom" 101 | ], 102 | "editor.tokenColorCustomizations": { 103 | "textMateRules": [ 104 | { 105 | "scope": "googletest.failed", 106 | "settings": { 107 | "foreground": "#f00" 108 | } 109 | }, 110 | { 111 | "scope": "googletest.passed", 112 | "settings": { 113 | "foreground": "#0f0" 114 | } 115 | }, 116 | { 117 | "scope": "googletest.run", 118 | "settings": { 119 | "foreground": "#0f0" 120 | } 121 | } 122 | ] 123 | } 124 | } -------------------------------------------------------------------------------- /src/Makefile: -------------------------------------------------------------------------------- 1 | 2 | CC=../gcc-arm-none-eabi/bin/arm-none-eabi-gcc 3 | CXX=../gcc-arm-none-eabi/bin/arm-none-eabi-g++ 4 | ASM=../gcc-arm-none-eabi/bin/arm-none-eabi-as 5 | GDB=../gcc-arm-none-eabi/bin/arm-none-eabi-gdb 6 | MKDIR=mkdir 7 | 8 | MACH=cortex-m0plus 9 | 10 | OPT=-O0 11 | 12 | HAL_OUT_DIR=../out/samr21HAL 13 | OT_PLAT_HAL_OUT_DIR=../out/otPlatHAL 14 | 15 | CMSIS_DEVICE_DIR=../third_party/CMSIS/r21 16 | CMSIS_CORE_DIR=../third_party/CMSIS/core 17 | 18 | OT_INC_DIR=../openthread/include 19 | OT_PLATFORM_INC_DIR=../openthread/examples/platforms 20 | 21 | TINYUSB_INC_DIR=../third_party/tinyusb/src 22 | TINYUSB_CONF_DIR=../third_party/tinyusb_config 23 | 24 | AT86RF233_INC_DIR=../third_party/ATMEL/AT86RF233 25 | 26 | HAL_DIR=./HAL 27 | HAL_INC_DIR=./HAL/include 28 | 29 | OT_PLAT_HAL_DIR=./OT-HAL 30 | OT_PLAT_HAL_INC_DIR=./OT-HAL/include 31 | 32 | INCDIRS=\ 33 | -I. \ 34 | -I$(CMSIS_DEVICE_DIR)/include \ 35 | -I$(CMSIS_DEVICE_DIR)/source \ 36 | -I$(CMSIS_CORE_DIR) \ 37 | -I$(AT86RF233_INC_DIR) \ 38 | -I$(HAL_INC_DIR) \ 39 | -I$(OT_INC_DIR) \ 40 | -I$(TINYUSB_INC_DIR) \ 41 | -I$(TINYUSB_CONF_DIR) \ 42 | -I$(OT_PLATFORM_INC_DIR) \ 43 | -I$(OT_PLAT_HAL_INC_DIR) 44 | 45 | 46 | DEFINES= -D__SAMR21E18A__ 47 | 48 | CFLAGS= \ 49 | -c \ 50 | -g \ 51 | -mcpu=$(MACH) \ 52 | --specs=nosys.specs \ 53 | -mfloat-abi=soft \ 54 | -mthumb \ 55 | -std=gnu99 \ 56 | -Wall \ 57 | $(OPT) \ 58 | $(INCDIRS) \ 59 | $(DEFINES) 60 | 61 | all:\ 62 | samr21HAL \ 63 | otPlatHAL 64 | 65 | samr21HAL:\ 66 | $(HAL_OUT_DIR) \ 67 | $(HAL_OUT_DIR)/samr21Radio.o \ 68 | $(HAL_OUT_DIR)/samr21RadioFSM.o \ 69 | $(HAL_OUT_DIR)/samr21Timer.o \ 70 | $(HAL_OUT_DIR)/samr21NopDelay.o \ 71 | $(HAL_OUT_DIR)/samr21Rtc.o \ 72 | $(HAL_OUT_DIR)/samr21Trx.o \ 73 | $(HAL_OUT_DIR)/samr21Nvm.o \ 74 | $(HAL_OUT_DIR)/samr21Usb.o \ 75 | $(HAL_OUT_DIR)/samr21Aes.o \ 76 | $(HAL_OUT_DIR)/samr21Clock.o 77 | 78 | otPlatHAL:\ 79 | $(OT_PLAT_HAL_OUT_DIR) \ 80 | $(OT_PLAT_HAL_OUT_DIR)/otPlatAlarm.o \ 81 | $(OT_PLAT_HAL_OUT_DIR)/otPlatEntropy.o \ 82 | $(OT_PLAT_HAL_OUT_DIR)/otPlatUartUsb.o \ 83 | $(OT_PLAT_HAL_OUT_DIR)/otPlatRadio.o 84 | 85 | 86 | $(HAL_OUT_DIR): 87 | $(MKDIR) -p $@ 88 | 89 | $(HAL_OUT_DIR)/samr21Radio.o:\ 90 | $(HAL_DIR)/samr21Radio.c 91 | 92 | $(CC) $(CFLAGS) -o $@ $^ 93 | 94 | $(HAL_OUT_DIR)/samr21RadioFSM.o:\ 95 | $(HAL_DIR)/samr21RadioFSM.c 96 | 97 | $(CC) $(CFLAGS) -o $@ $^ 98 | 99 | $(HAL_OUT_DIR)/samr21Timer.o:\ 100 | $(HAL_DIR)/samr21Timer.c 101 | 102 | $(CC) $(CFLAGS) -o $@ $^ 103 | 104 | $(HAL_OUT_DIR)/samr21NopDelay.o:\ 105 | $(HAL_DIR)/samr21NopDelay.c 106 | 107 | $(CC) $(CFLAGS) -o $@ $^ 108 | 109 | $(HAL_OUT_DIR)/samr21Rtc.o:\ 110 | $(HAL_DIR)/samr21Rtc.c 111 | 112 | $(CC) $(CFLAGS) -o $@ $^ 113 | 114 | $(HAL_OUT_DIR)/samr21Trx.o:\ 115 | $(HAL_DIR)/samr21Trx.c 116 | 117 | $(CC) $(CFLAGS) -o $@ $^ 118 | 119 | $(HAL_OUT_DIR)/samr21Nvm.o:\ 120 | $(HAL_DIR)/samr21Nvm.c 121 | 122 | $(CC) $(CFLAGS) -o $@ $^ 123 | 124 | $(HAL_OUT_DIR)/samr21Usb.o:\ 125 | $(HAL_DIR)/samr21Usb.c 126 | 127 | $(CC) $(CFLAGS) -o $@ $^ 128 | 129 | $(HAL_OUT_DIR)/samr21Clock.o:\ 130 | $(HAL_DIR)/samr21Clock.c 131 | 132 | $(CC) $(CFLAGS) -o $@ $^ 133 | 134 | $(HAL_OUT_DIR)/samr21Aes.o:\ 135 | $(HAL_DIR)/samr21Aes.c 136 | 137 | $(CC) $(CFLAGS) -o $@ $^ 138 | 139 | 140 | $(OT_PLAT_HAL_OUT_DIR): 141 | $(MKDIR) -p $@ 142 | 143 | $(OT_PLAT_HAL_OUT_DIR)/otPlatAlarm.o:\ 144 | $(OT_PLAT_HAL_DIR)/otPlatAlarm.c 145 | 146 | $(CC) $(CFLAGS) -o $@ $^ 147 | 148 | $(OT_PLAT_HAL_OUT_DIR)/otPlatEntropy.o:\ 149 | $(OT_PLAT_HAL_DIR)/otPlatEntropy.c 150 | 151 | $(CC) $(CFLAGS) -o $@ $^ 152 | 153 | $(OT_PLAT_HAL_OUT_DIR)/otPlatSystem.o:\ 154 | $(OT_PLAT_HAL_DIR)/otPlatSystem.c 155 | 156 | $(CC) $(CFLAGS) -o $@ $^ 157 | 158 | $(OT_PLAT_HAL_OUT_DIR)/otPlatUartUsb.o:\ 159 | $(OT_PLAT_HAL_DIR)/otPlatUartUsb.c 160 | 161 | $(CC) $(CFLAGS) -o $@ $^ 162 | 163 | $(OT_PLAT_HAL_OUT_DIR)/otPlatRadio.o:\ 164 | $(OT_PLAT_HAL_DIR)/otPlatRadio.c 165 | 166 | $(CC) $(CFLAGS) -o $@ $^ 167 | 168 | clean: 169 | rm -rf $(HAL_OUT_DIR) 170 | rm -rf $(OT_PLAT_HAL_OUT_DIR) 171 | 172 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/eic.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for EIC 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_EIC_INSTANCE_ 35 | #define _SAMR21_EIC_INSTANCE_ 36 | 37 | /* ========== Register definition for EIC peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */ 40 | #define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */ 41 | #define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ 42 | #define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 43 | #define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */ 44 | #define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ 45 | #define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ 46 | #define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ 47 | #define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */ 48 | #define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */ 49 | #define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */ 50 | #else 51 | #define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */ 52 | #define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */ 53 | #define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */ 54 | #define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 55 | #define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */ 56 | #define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */ 57 | #define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */ 58 | #define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */ 59 | #define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */ 60 | #define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */ 61 | #define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */ 62 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 | 64 | /* ========== Instance parameters for EIC peripheral ========== */ 65 | #define EIC_CONFIG_NUM 2 // Number of CONFIG registers 66 | #define EIC_GCLK_ID 5 // Index of Generic Clock 67 | 68 | #endif /* _SAMR21_EIC_INSTANCE_ */ 69 | -------------------------------------------------------------------------------- /src/OT-HAL/otPlatSystem.c: -------------------------------------------------------------------------------- 1 | //Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | #include "otPlatSystemHeader.h" 3 | #include "openthread/platform/misc.h" 4 | 5 | #include "samr21.h" 6 | #include "samr21Clock.h" 7 | #include "samr21Trx.h" 8 | #include "samr21Radio.h" 9 | #include "samr21FeCtrl.h" 10 | #include "samr21Rtc.h" 11 | #include "samr21Nvm.h" 12 | #include "samr21SysTick.h" 13 | #include "samr21Timer.h" 14 | #include "samr21Usb.h" 15 | #include "samr21Dma.h" 16 | #include "samr21Uart.h" 17 | 18 | #include "tusb.h" 19 | #include "tusb_config.h" 20 | 21 | 22 | static void samr21_tickleWatchdog() 23 | { 24 | #ifdef GCF_BUILD 25 | WDT->CLEAR.reg = WDT_CLEAR_CLEAR_KEY_Val; 26 | #endif 27 | } 28 | 29 | static void samr21_initIrqPriority() 30 | { 31 | //192 Lowest, 0 Highest 32 | NVIC_SetPriority(TCC0_IRQn, 192); //Unused 33 | NVIC_SetPriority(TCC1_IRQn, 5); //Used by OT Micro Alarm 34 | NVIC_SetPriority(TCC2_IRQn, 4); //Used by OT Millis Alarm 35 | NVIC_SetPriority(TC3_IRQn, 1); //Timer for DMA-Pace while uploading JIT to framebuffer 36 | NVIC_SetPriority(DMAC_IRQn, 0); //Timer for DMA-Pace while uploading to framebuffer 37 | NVIC_SetPriority(TC4_IRQn, 1); //Timer For Mac-Orchestration 38 | NVIC_SetPriority(TC5_IRQn, 0); //Critical Timer for Mac-Security Feature 39 | NVIC_SetPriority(EIC_IRQn, 2); //IRQs from AT86RF233 40 | NVIC_SetPriority(USB_IRQn, 5); //For Communication with USB-Host 41 | NVIC_SetPriority(RTC_IRQn, 4); //For timed Transmission 42 | } 43 | 44 | 45 | void otSysInit(int argc, char *argv[]) 46 | { 47 | samr21_tickleWatchdog(); 48 | samr21_initIrqPriority(); 49 | 50 | samr21Nvm_init(); 51 | 52 | #ifdef GCF_BUILD 53 | //Confirm the App Started to Bootloader 54 | uint8_t confirmedBtlFlag = 0x77; 55 | samr21Nvm_writeWithinRow(0x4FFF, &confirmedBtlFlag, sizeof(uint8_t)); 56 | #endif 57 | 58 | samr21_tickleWatchdog(); 59 | samr21Clock_enableFallbackClockTree(); //Not depending on MCLK of AT86RF233 60 | 61 | samr21_tickleWatchdog(); 62 | samr21Dma_init(); 63 | 64 | samr21_tickleWatchdog(); 65 | samr21Trx_initInterface(); //Also inits Clock Output of the AT86RF233, so we can switch to a Crystal based clock Domain 66 | 67 | #if defined(SAMR21_USE_USB_CLOCK) && (SAMR21_USE_USB_CLOCK > 0) 68 | samr21Usb_init(); 69 | samr21Clock_enableOperatingClockTree(); //Depending on receiving USB-SOF Signals 70 | #else 71 | samr21Clock_enableOperatingClockTree(); //Depending on correct output freq of AT86RF233 MCLK 72 | samr21Usb_init(); 73 | #endif 74 | 75 | samr21_tickleWatchdog(); 76 | samr21Trx_initDriver(); 77 | samr21FeCtrl_init(); 78 | 79 | samr21_tickleWatchdog(); 80 | samr21Rtc_init(); 81 | 82 | samr21_tickleWatchdog(); 83 | tusb_init(); 84 | 85 | 86 | samr21_tickleWatchdog(); 87 | samr21Uart_init(); 88 | 89 | samr21_tickleWatchdog(); 90 | samr21OtPlat_alarmInit(); 91 | } 92 | 93 | bool otSysPseudoResetWasRequested(void) 94 | { 95 | return false; 96 | } 97 | 98 | void otSysDeinit(void) 99 | { 100 | __NOP(); 101 | } 102 | 103 | void otSysProcessDrivers(otInstance *aInstance) 104 | { 105 | samr21OtPlat_uartCommTask(); 106 | samr21OtPlat_radioTick(); 107 | samr21OtPlat_alarmTask(); 108 | 109 | samr21_tickleWatchdog(); 110 | } 111 | 112 | otPlatResetReason otPlatGetResetReason(otInstance *aInstance){ 113 | switch (PM->RCAUSE.reg) 114 | { 115 | case PM_RCAUSE_POR: 116 | return OT_PLAT_RESET_REASON_POWER_ON; 117 | 118 | case PM_RCAUSE_BOD12: 119 | return OT_PLAT_RESET_REASON_FAULT; 120 | 121 | case PM_RCAUSE_BOD33: 122 | return OT_PLAT_RESET_REASON_FAULT; 123 | 124 | case PM_RCAUSE_EXT: 125 | return OT_PLAT_RESET_REASON_EXTERNAL; 126 | 127 | case PM_RCAUSE_WDT: 128 | return OT_PLAT_RESET_REASON_WATCHDOG; 129 | 130 | case PM_RCAUSE_SYST: 131 | return OT_PLAT_RESET_REASON_SOFTWARE; 132 | 133 | default: 134 | return OT_PLAT_RESET_REASON_OTHER; //TODO 135 | } 136 | } 137 | 138 | void otPlatReset(otInstance *aInstance){ 139 | NVIC_SystemReset(); 140 | } -------------------------------------------------------------------------------- /third_party/tinyusb_config/tusb_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * The MIT License (MIT) 3 | * 4 | * Copyright (c) 2019 Ha Thach (tinyusb.org) 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | * 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | * 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | * 24 | */ 25 | 26 | #ifndef _TUSB_CONFIG_H_ 27 | #define _TUSB_CONFIG_H_ 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | //--------------------------------------------------------------------+ 34 | // Board Specific Configuration 35 | //--------------------------------------------------------------------+ 36 | 37 | // RHPort number used for device can be defined by board.mk, default to port 0 38 | #ifndef BOARD_TUD_RHPORT 39 | #define BOARD_TUD_RHPORT 0 40 | #endif 41 | 42 | // RHPort max operational speed can defined by board.mk 43 | #ifndef BOARD_TUD_MAX_SPEED 44 | #define BOARD_TUD_MAX_SPEED OPT_MODE_LOW_SPEED 45 | #endif 46 | 47 | #ifndef TUP_DCD_ENDPOINT_MAX 48 | #define TUP_DCD_ENDPOINT_MAX 8 49 | #endif 50 | 51 | //-------------------------------------------------------------------- 52 | // Common Configuration 53 | //-------------------------------------------------------------------- 54 | 55 | // defined by compiler flags for flexibility 56 | #ifndef CFG_TUSB_MCU 57 | #define CFG_TUSB_MCU OPT_MCU_SAMR21 58 | #endif 59 | 60 | #ifndef CFG_TUSB_RHPORT0_MODE 61 | #define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED) 62 | #endif 63 | 64 | #ifndef CFG_TUSB_OS 65 | #define CFG_TUSB_OS OPT_OS_NONE 66 | #endif 67 | 68 | #ifndef CFG_TUSB_DEBUG 69 | #define CFG_TUSB_DEBUG 0 70 | #endif 71 | 72 | // Enable Device stack 73 | #define CFG_TUD_ENABLED 1 74 | 75 | // Default is max speed that hardware controller could support with on-chip PHY 76 | #define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED 77 | 78 | /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. 79 | * Tinyusb use follows macros to declare transferring memory so that they can be put 80 | * into those specific section. 81 | * e.g 82 | * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) 83 | * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) 84 | */ 85 | #ifndef CFG_TUSB_MEM_SECTION 86 | #define CFG_TUSB_MEM_SECTION 87 | #endif 88 | 89 | #ifndef CFG_TUSB_MEM_ALIGN 90 | #define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) 91 | #endif 92 | 93 | //-------------------------------------------------------------------- 94 | // DEVICE CONFIGURATION 95 | //-------------------------------------------------------------------- 96 | 97 | #ifndef CFG_TUD_ENDPOINT0_SIZE 98 | #define CFG_TUD_ENDPOINT0_SIZE 64 99 | #endif 100 | 101 | //------------- CLASS -------------// 102 | #define CFG_TUD_CDC 1 103 | #define CFG_TUD_MSC 0 104 | #define CFG_TUD_HID 0 105 | #define CFG_TUD_MIDI 0 106 | #define CFG_TUD_VENDOR 0 107 | 108 | // CDC FIFO size of TX and RX 109 | #define CFG_TUD_CDC_RX_BUFSIZE 1024 110 | #define CFG_TUD_CDC_TX_BUFSIZE 1024 111 | 112 | // CDC Endpoint transfer buffer size, more is faster 113 | #define CFG_TUD_CDC_EP_BUFSIZE 64 114 | 115 | #ifdef __cplusplus 116 | } 117 | #endif 118 | 119 | #endif /* _TUSB_CONFIG_H_ */ 120 | -------------------------------------------------------------------------------- /src/OT-Utils/include/otUtilities_uart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016, The OpenThread Authors. 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 3. Neither the name of the copyright holder nor the 13 | * names of its contributors may be used to endorse or promote products 14 | * derived from this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 | * POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | /** 30 | * @file 31 | * @brief 32 | * This file includes the platform abstraction for UART communication. 33 | */ 34 | 35 | #ifndef OPENTHREAD_PLATFORM_UART_H_ 36 | #define OPENTHREAD_PLATFORM_UART_H_ 37 | 38 | #include 39 | 40 | #include 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** 47 | * @addtogroup plat-uart 48 | * 49 | * @brief 50 | * This module includes the platform abstraction for UART communication. 51 | * 52 | * @{ 53 | * 54 | */ 55 | 56 | /** 57 | * Enable the UART. 58 | * 59 | * @retval OT_ERROR_NONE Successfully enabled the UART. 60 | * @retval OT_ERROR_FAILED Failed to enabled the UART. 61 | * 62 | */ 63 | otError otPlatUartEnable(void); 64 | 65 | /** 66 | * Disable the UART. 67 | * 68 | * @retval OT_ERROR_NONE Successfully disabled the UART. 69 | * @retval OT_ERROR_FAILED Failed to disable the UART. 70 | * 71 | */ 72 | otError otPlatUartDisable(void); 73 | 74 | /** 75 | * Send bytes over the UART. 76 | * 77 | * @param[in] aBuf A pointer to the data buffer. 78 | * @param[in] aBufLength Number of bytes to transmit. 79 | * 80 | * @retval OT_ERROR_NONE Successfully started transmission. 81 | * @retval OT_ERROR_FAILED Failed to start the transmission. 82 | * 83 | */ 84 | otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength); 85 | 86 | /** 87 | * Flush the outgoing transmit buffer and wait for the data to be sent. 88 | * This is called when the CLI UART interface has a full buffer but still 89 | * wishes to send more data. 90 | * 91 | * @retval OT_ERROR_NONE Flush succeeded, we can proceed to write more 92 | * data to the buffer. 93 | * 94 | * @retval OT_ERROR_NOT_IMPLEMENTED Driver does not support synchronous flush. 95 | * @retval OT_ERROR_INVALID_STATE Driver has no data to flush. 96 | */ 97 | otError otPlatUartFlush(void); 98 | 99 | /** 100 | * The UART driver calls this method to notify OpenThread that the requested bytes have been sent. 101 | * 102 | */ 103 | extern void otPlatUartSendDone(void); 104 | 105 | /** 106 | * The UART driver calls this method to notify OpenThread that bytes have been received. 107 | * 108 | * @param[in] aBuf A pointer to the received bytes. 109 | * @param[in] aBufLength The number of bytes received. 110 | * 111 | */ 112 | extern void otPlatUartReceived(const uint8_t *aBuf, uint16_t aBufLength); 113 | 114 | /** 115 | * @} 116 | * 117 | */ 118 | 119 | #ifdef __cplusplus 120 | } // extern "C" 121 | #endif 122 | 123 | #endif // OPENTHREAD_PLATFORM_UART_H_ 124 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/nvmctrl.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for NVMCTRL 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_NVMCTRL_INSTANCE_ 35 | #define _SAMR21_NVMCTRL_INSTANCE_ 36 | 37 | /* ========== Register definition for NVMCTRL peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */ 40 | #define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */ 41 | #define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ 42 | #define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 43 | #define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ 44 | #define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 45 | #define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */ 46 | #define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */ 47 | #define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */ 48 | #else 49 | #define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */ 50 | #define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */ 51 | #define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */ 52 | #define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 53 | #define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */ 54 | #define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 55 | #define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */ 56 | #define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */ 57 | #define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */ 58 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 | 60 | /* ========== Instance parameters for NVMCTRL peripheral ========== */ 61 | #define NVMCTRL_AUX0_ADDRESS 0x00804000 62 | #define NVMCTRL_AUX1_ADDRESS 0x00806000 63 | #define NVMCTRL_AUX2_ADDRESS 0x00808000 64 | #define NVMCTRL_AUX3_ADDRESS 0x0080A000 65 | #define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register 66 | #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF 67 | #define NVMCTRL_FLASH_SIZE 262144 68 | #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 69 | #define NVMCTRL_PAGE_HW 32 70 | #define NVMCTRL_PAGE_SIZE 64 71 | #define NVMCTRL_PAGE_W 16 72 | #define NVMCTRL_PMSB 3 73 | #define NVMCTRL_PSZ_BITS 6 74 | #define NVMCTRL_ROW_PAGES 4 75 | #define NVMCTRL_ROW_SIZE 256 76 | #define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030 77 | #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 78 | #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 79 | #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF 80 | 81 | #endif /* _SAMR21_NVMCTRL_INSTANCE_ */ 82 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/pm.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for PM 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_PM_INSTANCE_ 35 | #define _SAMR21_PM_INSTANCE_ 36 | 37 | /* ========== Register definition for PM peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */ 40 | #define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */ 41 | #define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */ 42 | #define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */ 43 | #define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */ 44 | #define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */ 45 | #define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */ 46 | #define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */ 47 | #define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */ 48 | #define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */ 49 | #define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ 50 | #define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */ 51 | #define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ 52 | #define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */ 53 | #else 54 | #define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */ 55 | #define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */ 56 | #define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */ 57 | #define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */ 58 | #define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */ 59 | #define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */ 60 | #define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */ 61 | #define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */ 62 | #define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */ 63 | #define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */ 64 | #define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */ 65 | #define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */ 66 | #define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */ 67 | #define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */ 68 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 | 70 | /* ========== Instance parameters for PM peripheral ========== */ 71 | #define PM_CTRL_MCSEL_DFLL48M 3 72 | #define PM_CTRL_MCSEL_GCLK 0 73 | #define PM_CTRL_MCSEL_OSC8M 1 74 | #define PM_CTRL_MCSEL_XOSC 2 75 | #define PM_PM_CLK_APB_NUM 2 76 | 77 | #endif /* _SAMR21_PM_INSTANCE_ */ 78 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/ac.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for AC 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_AC_INSTANCE_ 35 | #define _SAMR21_AC_INSTANCE_ 36 | 37 | /* ========== Register definition for AC peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */ 40 | #define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */ 41 | #define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */ 42 | #define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ 43 | #define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */ 44 | #define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ 45 | #define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */ 46 | #define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */ 47 | #define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */ 48 | #define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */ 49 | #define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */ 50 | #define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */ 51 | #define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */ 52 | #define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */ 53 | #else 54 | #define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */ 55 | #define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */ 56 | #define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */ 57 | #define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ 58 | #define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */ 59 | #define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ 60 | #define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */ 61 | #define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */ 62 | #define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */ 63 | #define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */ 64 | #define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */ 65 | #define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */ 66 | #define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */ 67 | #define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */ 68 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 | 70 | /* ========== Instance parameters for AC peripheral ========== */ 71 | #define AC_CMP_NUM 2 // Number of comparators 72 | #define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog 73 | #define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital 74 | #define AC_NUM_CMP 2 75 | #define AC_PAIRS 1 // Number of pairs of comparators 76 | 77 | #endif /* _SAMR21_AC_INSTANCE_ */ 78 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/component/pac.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Component description for PAC 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_PAC_COMPONENT_ 35 | #define _SAMR21_PAC_COMPONENT_ 36 | 37 | /* ========================================================================== */ 38 | /** SOFTWARE API DEFINITION FOR PAC */ 39 | /* ========================================================================== */ 40 | /** \addtogroup SAMR21_PAC Peripheral Access Controller */ 41 | /*@{*/ 42 | 43 | #define PAC_U2211 44 | #define REV_PAC 0x101 45 | 46 | /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ 47 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 | typedef union { 49 | struct { 50 | uint32_t :1; /*!< bit: 0 Reserved */ 51 | uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ 52 | } bit; /*!< Structure used for bit access */ 53 | uint32_t reg; /*!< Type used for register access */ 54 | } PAC_WPCLR_Type; 55 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 | 57 | #define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */ 58 | #define PAC_WPCLR_RESETVALUE 0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */ 59 | 60 | #define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */ 61 | #define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos) 62 | #define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)) 63 | #define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */ 64 | 65 | /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ 66 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 67 | typedef union { 68 | struct { 69 | uint32_t :1; /*!< bit: 0 Reserved */ 70 | uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ 71 | } bit; /*!< Structure used for bit access */ 72 | uint32_t reg; /*!< Type used for register access */ 73 | } PAC_WPSET_Type; 74 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 | 76 | #define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */ 77 | #define PAC_WPSET_RESETVALUE 0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */ 78 | 79 | #define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */ 80 | #define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos) 81 | #define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)) 82 | #define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */ 83 | 84 | /** \brief PAC hardware registers */ 85 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 86 | typedef struct { 87 | __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ 88 | __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ 89 | } Pac; 90 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 | 92 | /*@}*/ 93 | 94 | #endif /* _SAMR21_PAC_COMPONENT_ */ 95 | -------------------------------------------------------------------------------- /src/syscallRedirect.c: -------------------------------------------------------------------------------- 1 | #if defined(__GNUC__) 2 | 3 | #include 4 | #include 5 | #include 6 | 7 | /* === Prototypes =========================================================== */ 8 | 9 | int _close(int file); 10 | void _exit(int status); 11 | int _fstat(int file, struct stat *st); 12 | int _getpid(void); 13 | int _isatty(int file); 14 | int _kill(int pid, int sig); 15 | int _lseek(int file, int ptr, int dir); 16 | int _read(int file, char *ptr, int len); 17 | int _write(int file, const char *ptr, int len); 18 | 19 | /**************************************************************************//** 20 | * Close a file. 21 | * 22 | * @param[in] file File you want to close. 23 | * 24 | * @return Returns 0 when the file is closed. 25 | *****************************************************************************/ 26 | int _close(int file) 27 | { 28 | (void) file; 29 | return 0; 30 | } 31 | 32 | /**************************************************************************//** 33 | * Exit the program. 34 | * 35 | * @param[in] status The value to return to the parent process as the 36 | * exit status (not used). 37 | *****************************************************************************/ 38 | void _exit(int status) 39 | { 40 | (void) status; 41 | while (1) { 42 | } // Hang here forever... 43 | } 44 | 45 | /**************************************************************************//** 46 | * Status of an open file. 47 | * 48 | * @param[in] file Check status for this file. 49 | * 50 | * @param[in] st Status information. 51 | * 52 | * @return Returns 0 when st_mode is set to character special. 53 | *****************************************************************************/ 54 | int _fstat(int file, struct stat *st) 55 | { 56 | (void) file; 57 | (void) st; 58 | return 0; 59 | } 60 | 61 | /**************************************************************************//** 62 | * Get process ID. 63 | * 64 | * @return Return 1 when not implemented. 65 | *****************************************************************************/ 66 | int _getpid(void) 67 | { 68 | return 1; 69 | } 70 | 71 | /**************************************************************************//** 72 | * Query whether output stream is a terminal. 73 | * 74 | * @param[in] file Descriptor for the file. 75 | * 76 | * @return Returns 1 when query is done. 77 | *****************************************************************************/ 78 | int _isatty(int file) 79 | { 80 | (void) file; 81 | return 1; 82 | } 83 | 84 | /**************************************************************************//** 85 | * Send signal to process. 86 | * 87 | * @param[in] pid Process id (not used). 88 | * 89 | * @param[in] sig Signal to send (not used). 90 | *****************************************************************************/ 91 | int _kill(int pid, int sig) 92 | { 93 | (void)pid; 94 | (void)sig; 95 | return -1; 96 | } 97 | 98 | /**************************************************************************//** 99 | * Set position in a file. 100 | * 101 | * @param[in] file Descriptor for the file. 102 | * 103 | * @param[in] ptr Poiter to the argument offset. 104 | * 105 | * @param[in] dir Directory whence. 106 | * 107 | * @return Returns 0 when position is set. 108 | *****************************************************************************/ 109 | int _lseek(int file, int ptr, int dir) 110 | { 111 | (void) file; 112 | (void) ptr; 113 | (void) dir; 114 | return 0; 115 | } 116 | 117 | /**************************************************************************//** 118 | * Read from a file. 119 | * 120 | * @param[in] file Descriptor for the file you want to read from. 121 | * 122 | * @param[in] ptr Pointer to the chacaters that are beeing read. 123 | * 124 | * @param[in] len Number of characters to be read. 125 | * 126 | * @return Number of characters that have been read. 127 | *****************************************************************************/ 128 | int _read(int file, char *ptr, int len) 129 | { 130 | (void) file; 131 | (void) ptr; 132 | (void) len; 133 | 134 | return (int)0; 135 | } 136 | 137 | /**************************************************************************//** 138 | * Write to a file. 139 | * 140 | * @param[in] file Descriptor for the file you want to write to. 141 | * 142 | * @param[in] ptr Pointer to the text you want to write 143 | * 144 | * @param[in] len Number of characters to be written. 145 | * 146 | * @return Number of characters that have been written. 147 | *****************************************************************************/ 148 | int _write(int file, const char *ptr, int len) 149 | { 150 | (void) file; 151 | (void) ptr; 152 | (void) len; 153 | 154 | return (int)0; 155 | } 156 | 157 | #endif /* defined( __GNUC__ ) */ 158 | -------------------------------------------------------------------------------- /src/OT-HAL/otPlatUartUsb.c: -------------------------------------------------------------------------------- 1 | #include "otUtilities_uart.h" 2 | 3 | #include "tusb.h" 4 | #include "tusb_config.h" 5 | volatile static bool s_dtr = false; 6 | 7 | #define SIZE_WAIT_FOR_HOST_BUFFER 1024 8 | 9 | static struct 10 | { 11 | const uint8_t* pendingTxBuffer; 12 | uint16_t pendingTxBufferLength; 13 | 14 | bool current_otUartEnabled; 15 | bool current_dataTerminalReady; 16 | 17 | bool last_otUartEnabled; 18 | bool last_dataTerminalReady; 19 | 20 | bool ongoingTransmit; 21 | bool finishedTransmit; 22 | 23 | 24 | }s_otPlatUartUsbVars; 25 | 26 | 27 | #ifdef GCF_BUILD 28 | static const uint8_t s_gcfResetCommand[] = 29 | { 30 | 0xC0, //Slip END Flag 31 | 0x0B, 32 | 0x03, 33 | 0x00, 34 | 0x0C, 35 | 0x00, 36 | 0x05, 37 | 0x00, 38 | 0x26, 39 | 0x02, 40 | 0x00, 41 | 0x00, 42 | 0x00 43 | }; 44 | 45 | static uint8_t s_gcfResetCommandMatchLen = 0; 46 | 47 | #endif 48 | 49 | static void uart_receiveTask() 50 | { 51 | // Check for Available RX-Data 52 | if (tud_cdc_available()) 53 | { 54 | char buf[64]; 55 | uint32_t count = tud_cdc_read(buf, sizeof(buf)); 56 | 57 | otPlatUartReceived(buf, count); 58 | 59 | #ifdef GCF_BUILD 60 | for(uint8_t i = 0; i < count; i++){ 61 | if(buf[i] == s_gcfResetCommand[s_gcfResetCommandMatchLen]) 62 | { 63 | if(++s_gcfResetCommandMatchLen == sizeof(s_gcfResetCommand)) 64 | { 65 | otPlatReset(); 66 | } 67 | } 68 | else 69 | { 70 | s_gcfResetCommandMatchLen = 0; 71 | break; 72 | } 73 | } 74 | 75 | #endif 76 | } 77 | } 78 | 79 | static void uart_transmitTask() 80 | { 81 | if(s_otPlatUartUsbVars.current_dataTerminalReady && ( s_otPlatUartUsbVars.pendingTxBuffer != NULL ) ){ 82 | 83 | tud_cdc_write(s_otPlatUartUsbVars.pendingTxBuffer, s_otPlatUartUsbVars.pendingTxBufferLength); 84 | 85 | s_otPlatUartUsbVars.ongoingTransmit = true; 86 | s_otPlatUartUsbVars.pendingTxBuffer = NULL; 87 | s_otPlatUartUsbVars.pendingTxBufferLength = 0; 88 | 89 | tud_cdc_write_flush(); 90 | return; 91 | } 92 | 93 | if(s_otPlatUartUsbVars.ongoingTransmit && s_otPlatUartUsbVars.finishedTransmit){ 94 | 95 | s_otPlatUartUsbVars.ongoingTransmit = false; 96 | s_otPlatUartUsbVars.finishedTransmit = false; 97 | 98 | otPlatUartSendDone(); 99 | return; 100 | } 101 | 102 | if( (CFG_TUD_CDC_TX_BUFSIZE == tud_cdc_write_available()) && s_otPlatUartUsbVars.ongoingTransmit ){ 103 | 104 | s_otPlatUartUsbVars.ongoingTransmit = false; 105 | s_otPlatUartUsbVars.finishedTransmit = false; 106 | 107 | otPlatUartSendDone(); 108 | } 109 | } 110 | 111 | void samr21OtPlat_uartCommTask(){ 112 | tud_task(); 113 | 114 | s_otPlatUartUsbVars.current_dataTerminalReady = tud_cdc_connected(); 115 | uart_receiveTask(); 116 | uart_transmitTask(); 117 | 118 | 119 | s_otPlatUartUsbVars.last_dataTerminalReady = s_otPlatUartUsbVars.current_dataTerminalReady; 120 | s_otPlatUartUsbVars.last_otUartEnabled = s_otPlatUartUsbVars.current_otUartEnabled; 121 | } 122 | 123 | otError otPlatUartEnable(void) 124 | { 125 | s_otPlatUartUsbVars.last_otUartEnabled = true; 126 | return OT_ERROR_NONE; 127 | } 128 | 129 | otError otPlatUartDisable(void) 130 | { 131 | s_otPlatUartUsbVars.last_otUartEnabled = false; 132 | return OT_ERROR_NONE; 133 | } 134 | 135 | otError otPlatUartFlush(void) 136 | { 137 | while(tud_cdc_write_flush()); 138 | 139 | s_otPlatUartUsbVars.ongoingTransmit = false; 140 | s_otPlatUartUsbVars.finishedTransmit = false; 141 | 142 | otPlatUartSendDone(); 143 | 144 | return OT_ERROR_NONE; 145 | } 146 | 147 | otError otPlatUartSend(const uint8_t *a_buf_p, uint16_t a_bufLength) 148 | { 149 | if(s_otPlatUartUsbVars.ongoingTransmit){ 150 | otPlatUartFlush(); 151 | } 152 | 153 | #ifdef _DEBUG 154 | assert(s_otPlatUartUsbVars.ongoingTransmit == false); 155 | assert(s_otPlatUartUsbVars.finishedTransmit == false); 156 | #endif 157 | 158 | if( s_otPlatUartUsbVars.current_dataTerminalReady ){ 159 | tud_cdc_write(a_buf_p, a_bufLength); 160 | 161 | s_otPlatUartUsbVars.ongoingTransmit = true; 162 | 163 | tud_cdc_write_flush(); 164 | } 165 | else 166 | { 167 | s_otPlatUartUsbVars.pendingTxBuffer = a_buf_p; 168 | s_otPlatUartUsbVars.pendingTxBufferLength = a_bufLength; 169 | } 170 | 171 | return OT_ERROR_NONE; 172 | } 173 | 174 | otError otPlatWakeHost() 175 | { 176 | tud_remote_wakeup(); 177 | } -------------------------------------------------------------------------------- /test/mainGCF.c: -------------------------------------------------------------------------------- 1 | //Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | #include "samr21.h" 3 | #include 4 | #include 5 | 6 | #include "samr21Trx.h" 7 | #include "samr21Radio.h" 8 | #include "samr21Rtc.h" 9 | #include "samr21NopDelay.h" 10 | #include "samr21Timer.h" 11 | #include "samr21Nvm.h" 12 | #include "samr21Usb.h" 13 | 14 | 15 | 16 | void samr21DebugPortsInit(){ 17 | PORT->Group[0].DIRSET.reg= PORT_PA06; 18 | 19 | //Setup Mux Settings 20 | PORT->Group[0].WRCONFIG.reg = 21 | //PORT_WRCONFIG_HWSEL 22 | PORT_WRCONFIG_WRPINCFG 23 | //|PORT_WRCONFIG_WRPMUX 24 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 25 | //PORT_WRCONFIG_PULLEN 26 | //|PORT_WRCONFIG_INEN 27 | //|PORT_WRCONFIG_PMUXEN 28 | |PORT_WRCONFIG_PINMASK(PORT_PA06) //lower Halfword 29 | ; 30 | 31 | 32 | PORT->Group[0].DIRSET.reg= PORT_PA07; 33 | 34 | //Setup Mux Settings 35 | PORT->Group[0].WRCONFIG.reg = 36 | //PORT_WRCONFIG_HWSEL 37 | PORT_WRCONFIG_WRPINCFG 38 | //|PORT_WRCONFIG_WRPMUX 39 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 40 | //PORT_WRCONFIG_PULLEN 41 | //|PORT_WRCONFIG_INEN 42 | //|PORT_WRCONFIG_PMUXEN 43 | |PORT_WRCONFIG_PINMASK(PORT_PA07) //lower Halfword 44 | ; 45 | 46 | PORT->Group[0].DIRSET.reg= PORT_PA08; 47 | 48 | //Setup Mux Settings 49 | PORT->Group[0].WRCONFIG.reg = 50 | //PORT_WRCONFIG_HWSEL 51 | PORT_WRCONFIG_WRPINCFG 52 | //|PORT_WRCONFIG_WRPMUX 53 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 54 | //PORT_WRCONFIG_PULLEN 55 | //|PORT_WRCONFIG_INEN 56 | //|PORT_WRCONFIG_PMUXEN 57 | |PORT_WRCONFIG_PINMASK(PORT_PA08) //lower Halfword 58 | ; 59 | 60 | PORT->Group[0].DIRSET.reg= PORT_PA09; 61 | 62 | //Setup Mux Settings 63 | PORT->Group[0].WRCONFIG.reg = 64 | //PORT_WRCONFIG_HWSEL 65 | PORT_WRCONFIG_WRPINCFG 66 | //|PORT_WRCONFIG_WRPMUX 67 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 68 | //PORT_WRCONFIG_PULLEN 69 | //|PORT_WRCONFIG_INEN 70 | //|PORT_WRCONFIG_PMUXEN 71 | |PORT_WRCONFIG_PINMASK(PORT_PA09) //lower Halfword 72 | ; 73 | 74 | PORT->Group[0].DIRSET.reg= PORT_PA09; 75 | 76 | //Setup Mux Settings 77 | PORT->Group[0].WRCONFIG.reg = 78 | //PORT_WRCONFIG_HWSEL 79 | PORT_WRCONFIG_WRPINCFG 80 | //|PORT_WRCONFIG_WRPMUX 81 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 82 | //PORT_WRCONFIG_PULLEN 83 | //|PORT_WRCONFIG_INEN 84 | //|PORT_WRCONFIG_PMUXEN 85 | |PORT_WRCONFIG_PINMASK(PORT_PA09) //lower Halfword 86 | ; 87 | } 88 | 89 | extern AT86RF233_REG_IRQ_STATUS_t g_trxLastIrq; //from samr21trx.c 90 | 91 | int main(int argc, char const *argv[]) 92 | { 93 | samr21Nvm_init(); 94 | 95 | samr21ClockTrxSrcInit(); 96 | samr21Trx_initInterface(); 97 | 98 | samr21Trx_setupMClk(0x5); //MCLK 1MHz -> 16 Mhz 99 | samr21ClockInitAfterTrxSetup(); 100 | 101 | samr21TimerInit(); 102 | 103 | samr21DebugPortsInit(); 104 | samr21RadioInit(); 105 | 106 | samr21Usb_init(); 107 | 108 | 109 | uint64_t ieeeAddr = 0xA0A1A2A3A4A5A6A7; 110 | uint16_t shortAddr = 0xA8A9; 111 | uint16_t panId = 0xCAFE; 112 | samr21RadioSetIeeeAddr(&ieeeAddr); 113 | samr21RadioSetShortAddr(&shortAddr); 114 | samr21RadioSetPanId(&shortAddr); 115 | 116 | char halloWelt[12] = "HALLO WELT\n\r"; 117 | 118 | volatile bool keepAlive = true; 119 | volatile bool slipActive = false; 120 | 121 | char buf[64]; 122 | uint8_t len = 0; 123 | 124 | uint32_t dumbCounter = 0; 125 | 126 | while (true) 127 | { 128 | 129 | startLoop: 130 | tud_task(); 131 | 132 | if(keepAlive){ 133 | WDT->CLEAR.reg = WDT_CLEAR_CLEAR_KEY_Val; 134 | } 135 | 136 | if ( tud_cdc_available() ) 137 | { 138 | uint8_t tempChar; 139 | // read datas 140 | if(!slipActive){ 141 | tud_cdc_read(&tempChar, 1); 142 | if (tempChar == 0xC0) 143 | { 144 | slipActive = true; 145 | goto startLoop; 146 | } 147 | } 148 | 149 | tud_cdc_read(&tempChar, 1); 150 | 151 | if(tempChar != 0xC0){ 152 | buf[len++] = tempChar; 153 | goto startLoop; 154 | } 155 | 156 | if(buf[0] == 0x0B && buf[7] == 0x26){ 157 | keepAlive = false; 158 | } 159 | 160 | len = 0; 161 | slipActive = false; 162 | } 163 | 164 | if(dumbCounter++ > 0xFFFF){ 165 | dumbCounter = 0; 166 | tud_cdc_write(halloWelt, 12); 167 | tud_cdc_write_flush(); 168 | } 169 | } 170 | } 171 | -------------------------------------------------------------------------------- /src/openthread-core-r21-config.h: -------------------------------------------------------------------------------- 1 | 2 | 3 | /* 4 | * Copyright (c) 2017, The OpenThread Authors. 5 | * All rights reserved. 6 | * 7 | * Redistribution and use in source and binary forms, with or without 8 | * modification, are permitted provided that the following conditions are met: 9 | * 1. Redistributions of source code must retain the above copyright 10 | * notice, this list of conditions and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright 12 | * notice, this list of conditions and the following disclaimer in the 13 | * documentation and/or other materials provided with the distribution. 14 | * 3. Neither the name of the copyright holder nor the 15 | * names of its contributors may be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 | * POSSIBILITY OF SUCH DAMAGE. 29 | */ 30 | 31 | /** 32 | * @file 33 | * This file includes samr21 compile-time configuration constants 34 | * for OpenThread. 35 | */ 36 | 37 | #ifndef OPENTHREAD_CORE_SAMR21_CONFIG_H_ 38 | #define OPENTHREAD_CORE_SAMR21_CONFIG_H_ 39 | 40 | #include 41 | #include "platformVersion.h" 42 | 43 | extern uint32_t __d_nv_mem_start; 44 | extern uint32_t __d_nv_mem_end; 45 | 46 | #ifndef OPENTHREAD_CONFIG_THREAD_VERSION 47 | #define OPENTHREAD_CONFIG_THREAD_VERSION OT_THREAD_VERSION_1_3 48 | #endif 49 | 50 | /** 51 | * @def OPENTHREAD_CONFIG_PLATFORM_INFO 52 | * 53 | * The platform-specific string to insert into the OpenThread version string. 54 | * 55 | */ 56 | #define OPENTHREAD_CONFIG_PLATFORM_INFO "CONBEE2_RASPBEE2_0x" STR(OT_SAMR21_PLATFORM_VERSION_MAJOR) STR(OT_SAMR21_PLATFORM_VERSION_MAJOR) "0900" 57 | 58 | /** 59 | * @def OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE 60 | * 61 | * Define to 1 to enable otPlatFlash* APIs to support non-volatile storage. 62 | * 63 | * When defined to 1, the platform MUST implement the otPlatFlash* APIs instead of the otPlatSettings* APIs. 64 | * 65 | */ 66 | #define OPENTHREAD_CONFIG_PLATFORM_FLASH_API_ENABLE 1 67 | 68 | /** 69 | * @def OPENTHREAD_CONFIG_MAC_SOFTWARE_TX_SECURITY_ENABLE 70 | * 71 | * Define to 1 to enable software transmission security logic. 72 | * 73 | */ 74 | #define OPENTHREAD_CONFIG_MAC_SOFTWARE_TX_SECURITY_ENABLE 1 75 | 76 | 77 | /** 78 | * @def RADIO_CONFIG_SRC_MATCH_ENTRY_NUM 79 | * 80 | * The number of source address table entries. 81 | * 82 | */ 83 | #define RADIO_CONFIG_SRC_MATCH_ENTRY_NUM 16 84 | #define RADIO_CONFIG_SRC_MATCH_EXT_ENTRY_NUM 16 85 | 86 | /** 87 | * @def OPENTHREAD_CONFIG_DEFAULT_TRANSMIT_POWER 88 | * 89 | * The default IEEE 802.15.4 transmit power (dBm) 90 | * 91 | */ 92 | #define OPENTHREAD_CONFIG_DEFAULT_TRANSMIT_POWER 5 93 | 94 | #define OPENTHREAD_CONFIG_DUA_ENABLE 1 95 | /** 96 | * @def OPENTHREAD_CONFIG_PLATFORM_USEC_TIMER_ENABLE 97 | * 98 | * Define to 1 if you want to support microsecond timer in platform. 99 | * 100 | */ 101 | #define OPENTHREAD_CONFIG_PLATFORM_USEC_TIMER_ENABLE 1 102 | 103 | // CSL Auto Synchronization using data polling 104 | #define OPENTHREAD_CONFIG_MAC_CSL_AUTO_SYNC_ENABLE 0 105 | 106 | // CSL (Coordinated Sampled Listening) Debug 107 | #define OPENTHREAD_CONFIG_MAC_CSL_DEBUG_ENABLE 0 108 | 109 | // CSL (Coordinated Sampled Listening) Receiver 110 | #define OPENTHREAD_CONFIG_MAC_CSL_RECEIVER_ENABLE 0 111 | 112 | #define OPENTHREAD_CONFIG_DNS_CLIENT_ENABLE 1 113 | 114 | #define OPENTHREAD_CONFIG_MLR_ENABLE 0 115 | 116 | #define OPENTHREAD_CONFIG_MLE_LINK_METRICS_INITIATOR_ENABLE 0 117 | 118 | #define OPENTHREAD_CONFIG_MLE_LINK_METRICS_SUBJECT_ENABLE 0 119 | 120 | #ifndef OPENTHREAD_CONFIG_PING_SENDER_ENABLE 121 | #define OPENTHREAD_CONFIG_PING_SENDER_ENABLE 1 122 | #endif 123 | 124 | // Service Registration Protocol (SRP) Client (Thread 1.3) 125 | #define OPENTHREAD_CONFIG_SRP_CLIENT_ENABLE 1 126 | 127 | 128 | /** 129 | * @def OPENTHREAD_CONFIG_TCP_ENABLE 130 | * 131 | * Define as 1 to enable TCP. 132 | * 133 | */ 134 | #define OPENTHREAD_CONFIG_TCP_ENABLE 0 135 | 136 | /** 137 | * @def OPENTHREAD_CONFIG_STACK_VENDOR_OUI 138 | * 139 | * The Organizationally Unique Identifier for the vendor. 140 | * 141 | */ 142 | #ifndef OPENTHREAD_CONFIG_STACK_VENDOR_OUI 143 | #define OPENTHREAD_CONFIG_STACK_VENDOR_OUI 0x00212e 144 | #endif 145 | 146 | #endif // OPENTHREAD_CORE_SAMR21_CONFIG_H_ -------------------------------------------------------------------------------- /src/HAL/include/samr21Timer.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 dresden elektronik ingenieurtechnik gmbh. 3 | * All rights reserved. 4 | * 5 | * The software in this package is published under the terms of the BSD 6 | * style license a copy of which has been included with this distribution in 7 | * the LICENSE.txt file. 8 | * 9 | */ 10 | 11 | #ifndef _SAMR21_TIMER_H_ 12 | #define _SAMR21_TIMER_H_ 13 | 14 | #include 15 | #include 16 | 17 | #include "samr21.h" 18 | #include "samr21SysTick.h" 19 | 20 | /** 21 | * Inits Timer TCC0 as a oneshot or periodic Timer with a 1MHz Clk 22 | * 23 | * @param[in] divider divides down the SourceClk by 2^Value (1Mhz / 2^divider) 24 | * @param[in] oneshot if true the timer stops after it triggers once, otherwise it will wrap around 25 | * @param[in] interrupt if true the TCC0_Handler() gets called once the timer fires 26 | * 27 | */ 28 | void samr21Timer0_init(uint8_t divider, bool oneshot, bool interrupt); 29 | /** 30 | * Sets a oneshot timer on TCC0 (24 Bit) 31 | * 32 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 33 | */ 34 | void samr21Timer0_set(uint32_t timerTicks); 35 | /** 36 | * Aborts the currently running Oneshot Timer on TCC0 37 | * 38 | */ 39 | void samr21Timer0_stop(); 40 | 41 | 42 | /** 43 | * Inits Timer TCC1 as a oneshot or periodic Timer with a 1MHz Clk 44 | * 45 | * @param[in] divider divides down the SourceClk by 2^Value (1Mhz / 2^divider) 46 | * @param[in] oneshot if true the timer stops after it triggers once, otherwise it will wrap around 47 | * @param[in] interrupt if true the TCC1_Handler() gets called once the timer fires 48 | */ 49 | void samr21Timer1_init(uint8_t divider, bool oneshot, bool interrupt); 50 | /** 51 | * Sets a oneshot timer on TCC1 (24 Bit) 52 | * 53 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 54 | */ 55 | void samr21Timer1_startOneshot(uint32_t timerTicks); 56 | /** 57 | * Aborts the currently running Oneshot Timer on TCC1 58 | * 59 | */ 60 | void samr21Timer1_stop(); 61 | 62 | 63 | /** 64 | * Inits Timer TCC2 as a oneshot or periodic Timer with a 1MHz Clk 65 | * 66 | * @param[in] divider divides down the SourceClk by 2^Value (1Mhz / 2^divider) 67 | * @param[in] oneshot if true the timer stops after it triggers once, otherwise it will wrap around 68 | * @param[in] interrupt if true the TCC2_Handler() gets called once the timer fires 69 | */ 70 | void samr21Timer2_init(uint8_t divider, bool oneshot, bool interrupt); 71 | /** 72 | * Sets a oneshot timer on TCC2 (16 Bit) 73 | * 74 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 75 | */ 76 | void samr21Timer2_startOneshot(uint16_t timerTicks); 77 | /** 78 | * Aborts the currently running Oneshot Timer on TCC2 79 | * 80 | */ 81 | void samr21Timer2_stop(); 82 | 83 | 84 | /** 85 | * Inits Timer TC3 as a oneshot or periodic Timer with a 1MHz Clk 86 | * 87 | * @param[in] divider divides down the SourceClk by 2^Value (1Mhz / 2^divider) 88 | * @param[in] oneshot if true the timer stops after it triggers once, otherwise it will wrap around 89 | * @param[in] interrupt if true the TC3_Handler() gets called once the timer fires 90 | */ 91 | void samr21Timer3_init(uint8_t divider, bool oneshot, bool interrupt); 92 | 93 | /** 94 | * Sets a periodic timer on TC3 (16 Bit) 95 | * 96 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 97 | */ 98 | void samr21Timer3_setContinuousPeriod(uint16_t timerTicks); 99 | 100 | /** 101 | * Sets a oneshot timer on TC3 (16 Bit) 102 | * 103 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 104 | */ 105 | void samr21Timer3_startOneshot(uint16_t timerTicks); 106 | 107 | /** 108 | * Aborts the currently running Oneshot Timer on TC3 109 | * 110 | */ 111 | void samr21Timer3_Stop(); 112 | 113 | 114 | /** 115 | * Inits Timer TC4 as a oneshot or periodic Timer with a 1MHz Clk 116 | * 117 | * @param[in] divider divides down the SourceClk by 2^Value (1Mhz / 2^divider) 118 | * @param[in] oneshot if true the timer stops after it triggers once, otherwise it will wrap around 119 | * @param[in] interrupt if true the TC4_Handler() gets called once the timer fires 120 | */ 121 | void samr21Timer4_init(uint8_t divider, bool oneshot, bool interrupt); 122 | /** 123 | * Sets a oneshot timer on TC4 (16 Bit) 124 | * 125 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 126 | */ 127 | void samr21Timer4_startOneshot(uint16_t timerTicks); 128 | /** 129 | * Aborts the currently running Oneshot Timer on TC4 130 | * 131 | */ 132 | void samr21Timer4_stop(); 133 | 134 | /** 135 | * Inits Timer TC5 as a oneshot or periodic Timer with a 1MHz Clk 136 | * 137 | * @param[in] divider divides down the SourceClk by 2^Value (1Mhz / 2^divider) 138 | * @param[in] oneshot if true the timer stops after it triggers once, otherwise it will wrap around 139 | * @param[in] interrupt if true the TC5_Handler() gets called once the timer fires 140 | */ 141 | void samr21Timer5_init(uint8_t divider, bool oneshot, bool interrupt); 142 | /** 143 | * Sets a oneshot timer on TC5 (16 Bit) 144 | * 145 | * @param[in] timerTicks amount of TimerTicks until it the Timer fires 146 | */ 147 | void samr21Timer5_startOneshot(uint16_t timerTicks); 148 | /** 149 | * Aborts the currently running Oneshot Timer on TC5 150 | * 151 | */ 152 | void samr21Timer5_stop(); 153 | 154 | 155 | /** 156 | * Disables all Timers 157 | * Used for SoftReset 158 | * 159 | */ 160 | void samr21Timer_deinitAll(); 161 | #endif //_SAMR21_TIMER_H_ -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/component/rfctrl.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Component description for RFCTRL 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_RFCTRL_COMPONENT_ 35 | #define _SAMR21_RFCTRL_COMPONENT_ 36 | 37 | /* ========================================================================== */ 38 | /** SOFTWARE API DEFINITION FOR RFCTRL */ 39 | /* ========================================================================== */ 40 | /** \addtogroup SAMR21_RFCTRL RF233 control module */ 41 | /*@{*/ 42 | 43 | #define RFCTRL_U2233 44 | #define REV_RFCTRL 0x100 45 | 46 | /* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */ 47 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 | typedef union { 49 | struct { 50 | uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ 51 | uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ 52 | uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ 53 | uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ 54 | uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ 55 | uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ 56 | uint16_t :4; /*!< bit: 12..15 Reserved */ 57 | } bit; /*!< Structure used for bit access */ 58 | uint16_t reg; /*!< Type used for register access */ 59 | } RFCTRL_FECFG_Type; 60 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 | 62 | #define RFCTRL_FECFG_OFFSET 0x0 /**< \brief (RFCTRL_FECFG offset) Front-end control bus configuration */ 63 | #define RFCTRL_FECFG_RESETVALUE 0x0000ul /**< \brief (RFCTRL_FECFG reset_value) Front-end control bus configuration */ 64 | 65 | #define RFCTRL_FECFG_F0CFG_Pos 0 /**< \brief (RFCTRL_FECFG) Front-end control signal 0 configuration */ 66 | #define RFCTRL_FECFG_F0CFG_Msk (0x3ul << RFCTRL_FECFG_F0CFG_Pos) 67 | #define RFCTRL_FECFG_F0CFG(value) (RFCTRL_FECFG_F0CFG_Msk & ((value) << RFCTRL_FECFG_F0CFG_Pos)) 68 | #define RFCTRL_FECFG_F1CFG_Pos 2 /**< \brief (RFCTRL_FECFG) Front-end control signal 1 configuration */ 69 | #define RFCTRL_FECFG_F1CFG_Msk (0x3ul << RFCTRL_FECFG_F1CFG_Pos) 70 | #define RFCTRL_FECFG_F1CFG(value) (RFCTRL_FECFG_F1CFG_Msk & ((value) << RFCTRL_FECFG_F1CFG_Pos)) 71 | #define RFCTRL_FECFG_F2CFG_Pos 4 /**< \brief (RFCTRL_FECFG) Front-end control signal 2 configuration */ 72 | #define RFCTRL_FECFG_F2CFG_Msk (0x3ul << RFCTRL_FECFG_F2CFG_Pos) 73 | #define RFCTRL_FECFG_F2CFG(value) (RFCTRL_FECFG_F2CFG_Msk & ((value) << RFCTRL_FECFG_F2CFG_Pos)) 74 | #define RFCTRL_FECFG_F3CFG_Pos 6 /**< \brief (RFCTRL_FECFG) Front-end control signal 3 configuration */ 75 | #define RFCTRL_FECFG_F3CFG_Msk (0x3ul << RFCTRL_FECFG_F3CFG_Pos) 76 | #define RFCTRL_FECFG_F3CFG(value) (RFCTRL_FECFG_F3CFG_Msk & ((value) << RFCTRL_FECFG_F3CFG_Pos)) 77 | #define RFCTRL_FECFG_F4CFG_Pos 8 /**< \brief (RFCTRL_FECFG) Front-end control signal 4 configuration */ 78 | #define RFCTRL_FECFG_F4CFG_Msk (0x3ul << RFCTRL_FECFG_F4CFG_Pos) 79 | #define RFCTRL_FECFG_F4CFG(value) (RFCTRL_FECFG_F4CFG_Msk & ((value) << RFCTRL_FECFG_F4CFG_Pos)) 80 | #define RFCTRL_FECFG_F5CFG_Pos 10 /**< \brief (RFCTRL_FECFG) Front-end control signal 5 configuration */ 81 | #define RFCTRL_FECFG_F5CFG_Msk (0x3ul << RFCTRL_FECFG_F5CFG_Pos) 82 | #define RFCTRL_FECFG_F5CFG(value) (RFCTRL_FECFG_F5CFG_Msk & ((value) << RFCTRL_FECFG_F5CFG_Pos)) 83 | #define RFCTRL_FECFG_MASK 0x0FFFul /**< \brief (RFCTRL_FECFG) MASK Register */ 84 | 85 | /** \brief RFCTRL hardware registers */ 86 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 87 | typedef struct { 88 | __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ 89 | } Rfctrl; 90 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 | 92 | /*@}*/ 93 | 94 | #endif /* _SAMR21_RFCTRL_COMPONENT_ */ 95 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/component/hmatrixb.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Component description for HMATRIXB 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_HMATRIXB_COMPONENT_ 35 | #define _SAMR21_HMATRIXB_COMPONENT_ 36 | 37 | /* ========================================================================== */ 38 | /** SOFTWARE API DEFINITION FOR HMATRIXB */ 39 | /* ========================================================================== */ 40 | /** \addtogroup SAMR21_HMATRIXB HSB Matrix */ 41 | /*@{*/ 42 | 43 | #define HMATRIXB_I7638 44 | #define REV_HMATRIXB 0x212 45 | 46 | /* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */ 47 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 | typedef union { 49 | uint32_t reg; /*!< Type used for register access */ 50 | } HMATRIXB_PRAS_Type; 51 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 | 53 | #define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */ 54 | #define HMATRIXB_PRAS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */ 55 | 56 | #define HMATRIXB_PRAS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */ 57 | 58 | /* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */ 59 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 60 | typedef union { 61 | uint32_t reg; /*!< Type used for register access */ 62 | } HMATRIXB_PRBS_Type; 63 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 | 65 | #define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */ 66 | #define HMATRIXB_PRBS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */ 67 | 68 | #define HMATRIXB_PRBS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */ 69 | 70 | /* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */ 71 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 | typedef union { 73 | struct { 74 | uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */ 75 | } bit; /*!< Structure used for bit access */ 76 | uint32_t reg; /*!< Type used for register access */ 77 | } HMATRIXB_SFR_Type; 78 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 | 80 | #define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */ 81 | #define HMATRIXB_SFR_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */ 82 | 83 | #define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */ 84 | #define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos) 85 | #define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)) 86 | #define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */ 87 | 88 | /** \brief HmatrixbPrs hardware registers */ 89 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 90 | typedef struct { 91 | __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */ 92 | __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */ 93 | } HmatrixbPrs; 94 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 | 96 | /** \brief HMATRIXB hardware registers */ 97 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 | typedef struct { 99 | RoReg8 Reserved1[0x80]; 100 | HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */ 101 | RoReg8 Reserved2[0x10]; 102 | __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */ 103 | } Hmatrixb; 104 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 105 | 106 | /*@}*/ 107 | 108 | #endif /* _SAMR21_HMATRIXB_COMPONENT_ */ 109 | -------------------------------------------------------------------------------- /third_party/ATMEL/LINKER/samr21e18a_flash.ld: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Linker script for running in internal FLASH on the SAMR21E18A 5 | * 6 | * Copyright (c) 2015 Microchip Technology Inc. All rights reserved. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Redistribution and use in source and binary forms, with or without 13 | * modification, are permitted provided that the following conditions are met: 14 | * 15 | * 1. Redistributions of source code must retain the above copyright notice, 16 | * this list of conditions and the following disclaimer. 17 | * 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, 19 | * this list of conditions and the following disclaimer in the documentation 20 | * and/or other materials provided with the distribution. 21 | * 22 | * 3. The name of Atmel may not be used to endorse or promote products derived 23 | * from this software without specific prior written permission. 24 | * 25 | * 4. This software may only be redistributed and used in connection with an 26 | * Atmel microcontroller product. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 | * POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * \asf_license_stop 41 | * 42 | */ 43 | 44 | 45 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 46 | OUTPUT_ARCH(arm) 47 | SEARCH_DIR(.) 48 | 49 | /* Memory Spaces Definitions */ 50 | MEMORY 51 | { 52 | rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x0003EF00 53 | nvmem (r) : ORIGIN = 0x0003EF00, LENGTH = 0x00001100 54 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 55 | } 56 | 57 | /* The stack size used by the application. NOTE: you need to adjust according to your application. */ 58 | STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; 59 | 60 | /* Section Definitions */ 61 | SECTIONS 62 | { 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | _sfixed = .; 67 | KEEP(*(.vectors .vectors.*)) 68 | *(.text .text.* .gnu.linkonce.t.*) 69 | *(.glue_7t) *(.glue_7) 70 | *(.rodata .rodata* .gnu.linkonce.r.*) 71 | *(.ARM.extab* .gnu.linkonce.armextab.*) 72 | 73 | /* Support C constructors, and C destructors in both user code 74 | and the C library. This also provides support for C++ code. */ 75 | . = ALIGN(4); 76 | KEEP(*(.init)) 77 | . = ALIGN(4); 78 | __preinit_array_start = .; 79 | KEEP (*(.preinit_array)) 80 | __preinit_array_end = .; 81 | 82 | . = ALIGN(4); 83 | __init_array_start = .; 84 | KEEP (*(SORT(.init_array.*))) 85 | KEEP (*(.init_array)) 86 | __init_array_end = .; 87 | 88 | . = ALIGN(4); 89 | KEEP (*crtbegin.o(.ctors)) 90 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 91 | KEEP (*(SORT(.ctors.*))) 92 | KEEP (*crtend.o(.ctors)) 93 | 94 | . = ALIGN(4); 95 | KEEP(*(.fini)) 96 | 97 | . = ALIGN(4); 98 | __fini_array_start = .; 99 | KEEP (*(.fini_array)) 100 | KEEP (*(SORT(.fini_array.*))) 101 | __fini_array_end = .; 102 | 103 | KEEP (*crtbegin.o(.dtors)) 104 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 105 | KEEP (*(SORT(.dtors.*))) 106 | KEEP (*crtend.o(.dtors)) 107 | 108 | . = ALIGN(4); 109 | _efixed = .; /* End of text section */ 110 | } > rom 111 | 112 | /* .ARM.exidx is sorted, so has to go in its own output section. */ 113 | PROVIDE_HIDDEN (__exidx_start = .); 114 | .ARM.exidx : 115 | { 116 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 117 | } > rom 118 | PROVIDE_HIDDEN (__exidx_end = .); 119 | 120 | . = ALIGN(4); 121 | _etext = .; 122 | 123 | .nvmem : { 124 | . = ALIGN(4); 125 | _snvmem = .; 126 | } > nvmem 127 | 128 | .relocate : AT (_etext) 129 | { 130 | . = ALIGN(4); 131 | _srelocate = .; 132 | *(.ramfunc .ramfunc.*); 133 | *(.data .data.*); 134 | . = ALIGN(4); 135 | _erelocate = .; 136 | } > ram 137 | 138 | /* .bss section which is used for uninitialized data */ 139 | .bss (NOLOAD) : 140 | { 141 | . = ALIGN(4); 142 | _sbss = . ; 143 | __bss_start__ = . ; 144 | _szero = .; 145 | *(.bss .bss.*) 146 | *(COMMON) 147 | . = ALIGN(4); 148 | _ebss = . ; 149 | __bss_end__ = . ; 150 | _ezero = .; 151 | } > ram 152 | 153 | /* stack section */ 154 | .stack (NOLOAD): 155 | { 156 | . = ALIGN(8); 157 | _sstack = .; 158 | . = . + STACK_SIZE; 159 | . = ALIGN(8); 160 | _estack = .; 161 | } > ram 162 | 163 | . = ALIGN(4); 164 | end = . ; 165 | _end = . ; 166 | } 167 | -------------------------------------------------------------------------------- /third_party/ATMEL/LINKER/samr21e18a_flash copy.ld: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Linker script for running in internal FLASH on the SAMR21E18A 5 | * 6 | * Copyright (c) 2015 Microchip Technology Inc. All rights reserved. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Redistribution and use in source and binary forms, with or without 13 | * modification, are permitted provided that the following conditions are met: 14 | * 15 | * 1. Redistributions of source code must retain the above copyright notice, 16 | * this list of conditions and the following disclaimer. 17 | * 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, 19 | * this list of conditions and the following disclaimer in the documentation 20 | * and/or other materials provided with the distribution. 21 | * 22 | * 3. The name of Atmel may not be used to endorse or promote products derived 23 | * from this software without specific prior written permission. 24 | * 25 | * 4. This software may only be redistributed and used in connection with an 26 | * Atmel microcontroller product. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 | * POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * \asf_license_stop 41 | * 42 | */ 43 | 44 | 45 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 46 | OUTPUT_ARCH(arm) 47 | SEARCH_DIR(.) 48 | 49 | /* Memory Spaces Definitions */ 50 | MEMORY 51 | { 52 | rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x0003EF00 53 | nvmem (r) : ORIGIN = 0x0003EF00, LENGTH = 0x00001100 54 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 55 | } 56 | 57 | /* The stack size used by the application. NOTE: you need to adjust according to your application. */ 58 | STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; 59 | 60 | /* Section Definitions */ 61 | SECTIONS 62 | { 63 | .text : 64 | { 65 | . = ALIGN(4); 66 | _sfixed = .; 67 | KEEP(*(.vectors .vectors.*)) 68 | *(.text .text.* .gnu.linkonce.t.*) 69 | *(.glue_7t) *(.glue_7) 70 | *(.rodata .rodata* .gnu.linkonce.r.*) 71 | *(.ARM.extab* .gnu.linkonce.armextab.*) 72 | 73 | /* Support C constructors, and C destructors in both user code 74 | and the C library. This also provides support for C++ code. */ 75 | . = ALIGN(4); 76 | KEEP(*(.init)) 77 | . = ALIGN(4); 78 | __preinit_array_start = .; 79 | KEEP (*(.preinit_array)) 80 | __preinit_array_end = .; 81 | 82 | . = ALIGN(4); 83 | __init_array_start = .; 84 | KEEP (*(SORT(.init_array.*))) 85 | KEEP (*(.init_array)) 86 | __init_array_end = .; 87 | 88 | . = ALIGN(4); 89 | KEEP (*crtbegin.o(.ctors)) 90 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 91 | KEEP (*(SORT(.ctors.*))) 92 | KEEP (*crtend.o(.ctors)) 93 | 94 | . = ALIGN(4); 95 | KEEP(*(.fini)) 96 | 97 | . = ALIGN(4); 98 | __fini_array_start = .; 99 | KEEP (*(.fini_array)) 100 | KEEP (*(SORT(.fini_array.*))) 101 | __fini_array_end = .; 102 | 103 | KEEP (*crtbegin.o(.dtors)) 104 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 105 | KEEP (*(SORT(.dtors.*))) 106 | KEEP (*crtend.o(.dtors)) 107 | 108 | . = ALIGN(4); 109 | _efixed = .; /* End of text section */ 110 | } > rom 111 | 112 | /* .ARM.exidx is sorted, so has to go in its own output section. */ 113 | PROVIDE_HIDDEN (__exidx_start = .); 114 | .ARM.exidx : 115 | { 116 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 117 | } > rom 118 | PROVIDE_HIDDEN (__exidx_end = .); 119 | 120 | . = ALIGN(4); 121 | _etext = .; 122 | 123 | .nvmem : { 124 | . = ALIGN(4); 125 | _snvmem = .; 126 | } > nvmem 127 | 128 | .relocate : AT (_etext) 129 | { 130 | . = ALIGN(4); 131 | _srelocate = .; 132 | *(.ramfunc .ramfunc.*); 133 | *(.data .data.*); 134 | . = ALIGN(4); 135 | _erelocate = .; 136 | } > ram 137 | 138 | /* .bss section which is used for uninitialized data */ 139 | .bss (NOLOAD) : 140 | { 141 | . = ALIGN(4); 142 | _sbss = . ; 143 | __bss_start__ = . ; 144 | _szero = .; 145 | *(.bss .bss.*) 146 | *(COMMON) 147 | . = ALIGN(4); 148 | _ebss = . ; 149 | __bss_end__ = . ; 150 | _ezero = .; 151 | } > ram 152 | 153 | /* stack section */ 154 | .stack (NOLOAD): 155 | { 156 | . = ALIGN(8); 157 | _sstack = .; 158 | . = . + STACK_SIZE; 159 | . = ALIGN(8); 160 | _estack = .; 161 | } > ram 162 | 163 | . = ALIGN(4); 164 | end = . ; 165 | _end = . ; 166 | } 167 | -------------------------------------------------------------------------------- /src/OT-Utils/include/otUtilities_linkMetrics.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2020, The OpenThread Authors. 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 1. Redistributions of source code must retain the above copyright 8 | * notice, this list of conditions and the following disclaimer. 9 | * 2. Redistributions in binary form must reproduce the above copyright 10 | * notice, this list of conditions and the following disclaimer in the 11 | * documentation and/or other materials provided with the distribution. 12 | * 3. Neither the name of the copyright holder nor the 13 | * names of its contributors may be used to endorse or promote products 14 | * derived from this software without specific prior written permission. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 | * POSSIBILITY OF SUCH DAMAGE. 27 | */ 28 | 29 | /** 30 | * @file 31 | * @brief 32 | * This file defines the link metrics interface for OpenThread platform radio drivers. 33 | * 34 | * APIs defined in this module could be used by a platform to implement Enhanced-ACK Based Probing feature 35 | * (Probing Subject side) in its radio driver. 36 | * 37 | */ 38 | 39 | #ifndef OPENTHREAD_UTILS_LINK_METRICS_H 40 | #define OPENTHREAD_UTILS_LINK_METRICS_H 41 | 42 | #include 43 | 44 | #include "otUtilities_macFrame.h" 45 | 46 | #ifdef __cplusplus 47 | extern "C" { 48 | #endif 49 | 50 | /** 51 | * This method initializes the Link Metrics util module. 52 | * 53 | * @param[in] aNoiseFloor The noise floor used by Link Metrics. It should be set to the platform's 54 | * noise floor (measured noise floor, receiver sensitivity or a constant). 55 | * 56 | */ 57 | void otLinkMetricsInit(int8_t aNoiseFloor); 58 | 59 | /** 60 | * This method sets/clears Enhanced-ACK Based Probing for a specific Initiator. 61 | * 62 | * This method can start/stop Enhanced-ACK Based Probing for a neighbor that has the address @p aShortAddress and 63 | * @p aExtAddress. Once the Probing is started, the device would record the Link Metrics data of link layer frames 64 | * sent from that neighbor and include the data into header IE in Enhanced-ACK sent to that neighbor. 65 | * 66 | * @param[in] aShortAddress The short address of the Initiator. 67 | * @param[in] aExtAddress A pointer to the extended address of the Initiator. 68 | * @param[in] aLinkMetrics Flags specifying what metrics to query (Pdu Count would be omitted). When 69 | * @p aLinkMetrics is eqaul to `0`, this method clears the Initiator. 70 | * 71 | * @retval OT_ERROR_NONE Successfully configured the Enhanced-ACK Based Probing. 72 | * @retval OT_ERROR_INVALID_ARGS @p aExtAddress is `nullptr`. 73 | * @retval OT_ERROR_NOT_FOUND The Initiator indicated by @p aShortAddress is not found when trying to clear. 74 | * @retval OT_ERROR_NO_BUFS No more Initiator can be supported. 75 | * 76 | */ 77 | otError otLinkMetricsConfigureEnhAckProbing(otShortAddress aShortAddress, 78 | const otExtAddress *aExtAddress, 79 | otLinkMetrics aLinkMetrics); 80 | 81 | /** 82 | * This method generates the Link Metrics data (assessed for the acknowledged frame) bytes that would be included in 83 | * Vendor-Specific IE. 84 | * 85 | * This method first checks what Link Metrics are specified by the Initiator indicated by @p aMacAddress. And then 86 | * write the values to @p aData. 87 | * 88 | * @param[in] aMacAddress The Mac address of the Initiator. 89 | * @param[in] aLqi LQI value of the acknowledged frame. 90 | * @param[in] aRssi RSSI value of the acknowledged frame. 91 | * @param[out] aData A pointer to the buffer where the data would be written to. The caller should make 92 | * sure that the size of the buffer is not less than the size of Link Metrics data 93 | * configured before. 94 | * 95 | * @returns The size of data read. Would be `0` if the Initiator is not found or @p aData is invalid. 96 | * 97 | */ 98 | uint8_t otLinkMetricsEnhAckGenData(const otMacAddress *aMacAddress, uint8_t aLqi, int8_t aRssi, uint8_t *aData); 99 | 100 | /** 101 | * This method returns the data length of Enhanced-ACK Based Probing for a specific Initiator. 102 | * 103 | * @param[in] aMacAddress The Mac address of the Initiator. 104 | * 105 | * @returns The size of data. `0` if it's not configured for the Initiator. 106 | * 107 | */ 108 | uint8_t otLinkMetricsEnhAckGetDataLen(const otMacAddress *aMacAddress); 109 | 110 | #ifdef __cplusplus 111 | } // extern "C" 112 | #endif 113 | 114 | #endif // OPENTHREAD_UTILS_LINK_METRICS_H 115 | -------------------------------------------------------------------------------- /test/mainMisc.c: -------------------------------------------------------------------------------- 1 | //Author Eric Härtel @ dresden elektronik ingenieurtechnik gmbh © 2022 2 | #include "samr21.h" 3 | #include 4 | #include 5 | 6 | #include "samr21Trx.h" 7 | #include "samr21Radio.h" 8 | #include "samr21Rtc.h" 9 | #include "samr21NopDelay.h" 10 | #include "samr21Timer.h" 11 | #include "samr21Nvm.h" 12 | #include "samr21Usb.h" 13 | #include "samr21Aes.h" 14 | 15 | 16 | 17 | void samr21DebugPortsInit(){ 18 | 19 | PORT->Group[0].DIRSET.reg= PORT_PA16; 20 | 21 | //Setup Mux Settings 22 | PORT->Group[0].WRCONFIG.reg = 23 | PORT_WRCONFIG_HWSEL 24 | |PORT_WRCONFIG_WRPINCFG 25 | |PORT_WRCONFIG_WRPMUX 26 | |PORT_WRCONFIG_PMUX(MUX_PA16H_GCLK_IO2) 27 | //PORT_WRCONFIG_PULLEN 28 | //|PORT_WRCONFIG_INEN 29 | |PORT_WRCONFIG_PMUXEN 30 | |PORT_WRCONFIG_PINMASK(PORT_PA16 >> 16) //upper Halfword 31 | ; 32 | 33 | PORT->Group[0].DIRSET.reg= PORT_PA06; 34 | 35 | //Setup Mux Settings 36 | PORT->Group[0].WRCONFIG.reg = 37 | //PORT_WRCONFIG_HWSEL 38 | PORT_WRCONFIG_WRPINCFG 39 | //|PORT_WRCONFIG_WRPMUX 40 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 41 | //PORT_WRCONFIG_PULLEN 42 | //|PORT_WRCONFIG_INEN 43 | //|PORT_WRCONFIG_PMUXEN 44 | |PORT_WRCONFIG_PINMASK(PORT_PA06) //lower Halfword 45 | ; 46 | 47 | 48 | PORT->Group[0].DIRSET.reg= PORT_PA07; 49 | 50 | //Setup Mux Settings 51 | PORT->Group[0].WRCONFIG.reg = 52 | //PORT_WRCONFIG_HWSEL 53 | PORT_WRCONFIG_WRPINCFG 54 | //|PORT_WRCONFIG_WRPMUX 55 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 56 | //PORT_WRCONFIG_PULLEN 57 | //|PORT_WRCONFIG_INEN 58 | //|PORT_WRCONFIG_PMUXEN 59 | |PORT_WRCONFIG_PINMASK(PORT_PA07) //lower Halfword 60 | ; 61 | 62 | PORT->Group[0].DIRSET.reg= PORT_PA08; 63 | 64 | //Setup Mux Settings 65 | PORT->Group[0].WRCONFIG.reg = 66 | //PORT_WRCONFIG_HWSEL 67 | PORT_WRCONFIG_WRPINCFG 68 | //|PORT_WRCONFIG_WRPMUX 69 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 70 | //PORT_WRCONFIG_PULLEN 71 | //|PORT_WRCONFIG_INEN 72 | //|PORT_WRCONFIG_PMUXEN 73 | |PORT_WRCONFIG_PINMASK(PORT_PA08) //lower Halfword 74 | ; 75 | 76 | PORT->Group[0].DIRSET.reg= PORT_PA09; 77 | 78 | //Setup Mux Settings 79 | PORT->Group[0].WRCONFIG.reg = 80 | //PORT_WRCONFIG_HWSEL 81 | PORT_WRCONFIG_WRPINCFG 82 | //|PORT_WRCONFIG_WRPMUX 83 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 84 | //PORT_WRCONFIG_PULLEN 85 | //|PORT_WRCONFIG_INEN 86 | //|PORT_WRCONFIG_PMUXEN 87 | |PORT_WRCONFIG_PINMASK(PORT_PA09) //lower Halfword 88 | ; 89 | 90 | PORT->Group[0].DIRSET.reg= PORT_PA09; 91 | 92 | //Setup Mux Settings 93 | PORT->Group[0].WRCONFIG.reg = 94 | //PORT_WRCONFIG_HWSEL 95 | PORT_WRCONFIG_WRPINCFG 96 | //|PORT_WRCONFIG_WRPMUX 97 | //|PORT_WRCONFIG_PMUX(MUX_PC16F_GCLK_IO1) 98 | //PORT_WRCONFIG_PULLEN 99 | //|PORT_WRCONFIG_INEN 100 | //|PORT_WRCONFIG_PMUXEN 101 | |PORT_WRCONFIG_PINMASK(PORT_PA09) //lower Halfword 102 | ; 103 | } 104 | 105 | extern AT86RF233_REG_IRQ_STATUS_t g_trxLastIrq; //from samr21trx.c 106 | volatile bool tempLock = false; 107 | 108 | int main(int argc, char const *argv[]) 109 | { 110 | samr21Nvm_init(); 111 | samr21ClockTrxSrcInit(); 112 | samr21Trx_initInterface(); 113 | 114 | samr21Trx_setupMClk(0x5); //MCLK 1MHz -> 16 Mhz 115 | samr21ClockInitAfterTrxSetup(); 116 | 117 | samr21TimerInit(); 118 | 119 | samr21DebugPortsInit(); 120 | samr21RadioInit(); 121 | 122 | samr21Usb_init(); 123 | 124 | uint64_t ieeeAddr = samr21Nvm_getIeeeAddr(); 125 | uint16_t shortAddr = 0xA8A9; 126 | uint16_t panId = 0xCAFE; 127 | samr21RadioSetIeeeAddr(&ieeeAddr); 128 | samr21RadioSetShortAddr(&shortAddr); 129 | samr21RadioSetPanId(&shortAddr); 130 | samr21RadioChangeChannel(13); 131 | 132 | 133 | char edDone[23] = "\n\rED on Ch.:[ ] = -"; 134 | char edFailed[23] = "\n\rED on Ch.:[ ] FAILED"; 135 | 136 | 137 | // Time to connect to the USB CDC DT 138 | for(uint32_t i = 0; i < 0xFFFF; i++){ 139 | samr21UsbEchoTask(); 140 | } 141 | 142 | uint8_t key[AES_BLOCK_SIZE] = { 143 | 0x5a, 0x69, 0x67, 0x42, 0x65, 0x65, 0x41, 0x6c, 0x6c, 0x69, 0x61, 0x6e, 0x63, 0x65, 0x30, 0x39 144 | }; 145 | 146 | uint8_t input[AES_BLOCK_SIZE] = { 147 | 0xAA, 0xAA, 0xAA, 0xAA, 148 | 0xAA, 0xAA, 0xAA, 0xAA, 149 | 0xAA, 0xAA, 0xAA, 0xAA, 150 | 0xAA, 0xAA, 0xAA, 0xAA 151 | }; 152 | 153 | uint8_t output[AES_BLOCK_SIZE] = {0}; 154 | 155 | samr21AesKeySetup(key); 156 | 157 | while (true) 158 | { 159 | samr21Timer0_set(1500); 160 | tempLock=true; 161 | while (tempLock); 162 | 163 | uint8_t inout[AES_BLOCK_SIZE]; 164 | memcpy(inout, input, AES_BLOCK_SIZE); 165 | 166 | PORT->Group[0].OUTSET.reg = PORT_PA06; 167 | samr21AesEcbEncryptBlocking(inout); 168 | PORT->Group[0].OUTCLR.reg = PORT_PA06; 169 | 170 | samr21Timer1_startOneshot(500); 171 | tempLock=true; 172 | while (tempLock); 173 | } 174 | } 175 | 176 | 177 | 178 | void TCC0_Handler(){ 179 | TCC0->INTFLAG.bit.OVF = 1; 180 | tempLock=false; 181 | } 182 | 183 | void TCC1_Handler(){ 184 | TCC1->INTFLAG.bit.OVF = 1; 185 | tempLock=false; 186 | } 187 | -------------------------------------------------------------------------------- /third_party/ATMEL/LINKER/samr21e18a_flash_gcf_offset.ld: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Linker script for running in internal FLASH on the SAMR21E18A 5 | * 6 | * Copyright (c) 2015 Microchip Technology Inc. All rights reserved. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Redistribution and use in source and binary forms, with or without 13 | * modification, are permitted provided that the following conditions are met: 14 | * 15 | * 1. Redistributions of source code must retain the above copyright notice, 16 | * this list of conditions and the following disclaimer. 17 | * 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, 19 | * this list of conditions and the following disclaimer in the documentation 20 | * and/or other materials provided with the distribution. 21 | * 22 | * 3. The name of Atmel may not be used to endorse or promote products derived 23 | * from this software without specific prior written permission. 24 | * 25 | * 4. This software may only be redistributed and used in connection with an 26 | * Atmel microcontroller product. 27 | * 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 | * POSSIBILITY OF SUCH DAMAGE. 39 | * 40 | * \asf_license_stop 41 | * 42 | */ 43 | 44 | 45 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 46 | OUTPUT_ARCH(arm) 47 | SEARCH_DIR(.) 48 | 49 | /* Memory Spaces Definitions */ 50 | MEMORY 51 | { 52 | vec_rom (rx) : ORIGIN = 0x00005000, LENGTH = 0x00000100 53 | reserved_pds (r) : ORIGIN = 0x00005100, LENGTH = 0x00004000 54 | reserved_crc (r) : ORIGIN = 0x00009100, LENGTH = 0x00000100 55 | rom (rx) : ORIGIN = 0x00009200, LENGTH = 0x00035D00 56 | nvmem (r) : ORIGIN = 0x0003EF00, LENGTH = 0x00000E00 57 | reserved_nvmem (r) : ORIGIN = 0x0003FD00, LENGTH = 0x00000300 58 | ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 59 | } 60 | 61 | /* The stack size used by the application. NOTE: you need to adjust according to your application. */ 62 | STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; 63 | 64 | /* Section Definitions */ 65 | SECTIONS 66 | { 67 | .vectors : { 68 | . = ALIGN(4); 69 | _sfixed = .; 70 | KEEP(*(.vectors .vectors.*)) 71 | } > vec_rom 72 | 73 | .text : 74 | { 75 | . = ALIGN(4); 76 | *(.text .text.* .gnu.linkonce.t.*) 77 | *(.glue_7t) *(.glue_7) 78 | *(.rodata .rodata* .gnu.linkonce.r.*) 79 | *(.ARM.extab* .gnu.linkonce.armextab.*) 80 | 81 | /* Support C constructors, and C destructors in both user code 82 | and the C library. This also provides support for C++ code. */ 83 | . = ALIGN(4); 84 | KEEP(*(.init)) 85 | . = ALIGN(4); 86 | __preinit_array_start = .; 87 | KEEP (*(.preinit_array)) 88 | __preinit_array_end = .; 89 | 90 | . = ALIGN(4); 91 | __init_array_start = .; 92 | KEEP (*(SORT(.init_array.*))) 93 | KEEP (*(.init_array)) 94 | __init_array_end = .; 95 | 96 | . = ALIGN(4); 97 | KEEP (*crtbegin.o(.ctors)) 98 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 99 | KEEP (*(SORT(.ctors.*))) 100 | KEEP (*crtend.o(.ctors)) 101 | 102 | . = ALIGN(4); 103 | KEEP(*(.fini)) 104 | 105 | . = ALIGN(4); 106 | __fini_array_start = .; 107 | KEEP (*(.fini_array)) 108 | KEEP (*(SORT(.fini_array.*))) 109 | __fini_array_end = .; 110 | 111 | KEEP (*crtbegin.o(.dtors)) 112 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 113 | KEEP (*(SORT(.dtors.*))) 114 | KEEP (*crtend.o(.dtors)) 115 | 116 | . = ALIGN(4); 117 | _efixed = .; /* End of text section */ 118 | } > rom 119 | 120 | /* .ARM.exidx is sorted, so has to go in its own output section. */ 121 | PROVIDE_HIDDEN (__exidx_start = .); 122 | .ARM.exidx : 123 | { 124 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 125 | } > rom 126 | PROVIDE_HIDDEN (__exidx_end = .); 127 | 128 | . = ALIGN(4); 129 | _etext = .; 130 | 131 | .nvmem : { 132 | . = ALIGN(4); 133 | _snvmem = .; 134 | } > nvmem 135 | 136 | 137 | .relocate : AT (_etext) 138 | { 139 | . = ALIGN(4); 140 | _srelocate = .; 141 | *(.ramfunc .ramfunc.*); 142 | *(.data .data.*); 143 | . = ALIGN(4); 144 | _erelocate = .; 145 | } > ram 146 | 147 | /* .bss section which is used for uninitialized data */ 148 | .bss (NOLOAD) : 149 | { 150 | . = ALIGN(4); 151 | _sbss = . ; 152 | __bss_start__ = . ; 153 | _szero = .; 154 | *(.bss .bss.*) 155 | *(COMMON) 156 | . = ALIGN(4); 157 | _ebss = . ; 158 | __bss_end__ = . ; 159 | _ezero = .; 160 | } > ram 161 | 162 | /* stack section */ 163 | .stack (NOLOAD): 164 | { 165 | . = ALIGN(8); 166 | _sstack = .; 167 | . = . + STACK_SIZE; 168 | . = ALIGN(8); 169 | _estack = .; 170 | } > ram 171 | 172 | . = ALIGN(4); 173 | end = . ; 174 | _end = . ; 175 | } 176 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/adc.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for ADC 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_ADC_INSTANCE_ 35 | #define _SAMR21_ADC_INSTANCE_ 36 | 37 | /* ========== Register definition for ADC peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ 40 | #define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ 41 | #define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ 42 | #define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ 43 | #define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ 44 | #define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ 45 | #define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ 46 | #define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ 47 | #define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ 48 | #define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ 49 | #define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ 50 | #define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ 51 | #define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ 52 | #define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ 53 | #define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ 54 | #define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ 55 | #define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ 56 | #define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ 57 | #define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ 58 | #define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ 59 | #else 60 | #define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ 61 | #define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ 62 | #define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ 63 | #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ 64 | #define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ 65 | #define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ 66 | #define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ 67 | #define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ 68 | #define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ 69 | #define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ 70 | #define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ 71 | #define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ 72 | #define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ 73 | #define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ 74 | #define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ 75 | #define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ 76 | #define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ 77 | #define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ 78 | #define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ 79 | #define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ 80 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 | 82 | /* ========== Instance parameters for ADC peripheral ========== */ 83 | #define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger 84 | #define ADC_EXTCHANNEL_MSB 19 // Number of external channels 85 | #define ADC_GCLK_ID 30 // Index of Generic Clock 86 | #define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield 87 | #define ADC_RESULT_MSB 15 // Size of Result 88 | 89 | #endif /* _SAMR21_ADC_INSTANCE_ */ 90 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/dsu.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for DSU 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_DSU_INSTANCE_ 35 | #define _SAMR21_DSU_INSTANCE_ 36 | 37 | /* ========== Register definition for DSU peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ 40 | #define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ 41 | #define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ 42 | #define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ 43 | #define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ 44 | #define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ 45 | #define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ 46 | #define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ 47 | #define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ 48 | #define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 49 | #define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 50 | #define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ 51 | #define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ 52 | #define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ 53 | #define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ 54 | #define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ 55 | #define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ 56 | #define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ 57 | #define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ 58 | #define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ 59 | #define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ 60 | #define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ 61 | #else 62 | #define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ 63 | #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ 64 | #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ 65 | #define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ 66 | #define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ 67 | #define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ 68 | #define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ 69 | #define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ 70 | #define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ 71 | #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 72 | #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 73 | #define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ 74 | #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ 75 | #define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ 76 | #define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ 77 | #define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ 78 | #define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ 79 | #define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ 80 | #define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ 81 | #define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ 82 | #define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ 83 | #define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ 84 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 | 86 | /* ========== Instance parameters for DSU peripheral ========== */ 87 | #define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register 88 | 89 | #endif /* _SAMR21_DSU_INSTANCE_ */ 90 | -------------------------------------------------------------------------------- /third_party/CMSIS/r21/include/instance/mtb.h: -------------------------------------------------------------------------------- 1 | /** 2 | * \file 3 | * 4 | * \brief Instance description for MTB 5 | * 6 | * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 | * 8 | * \asf_license_start 9 | * 10 | * \page License 11 | * 12 | * Subject to your compliance with these terms, you may use Microchip 13 | * software and any derivatives exclusively with Microchip products. 14 | * It is your responsibility to comply with third party license terms applicable 15 | * to your use of third party software (including open source software) that 16 | * may accompany Microchip software. 17 | * 18 | * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 | * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 | * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 | * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 | * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 | * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 | * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 | * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 | * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 | * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 | * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 | * 30 | * \asf_license_stop 31 | * 32 | */ 33 | 34 | #ifndef _SAMR21_MTB_INSTANCE_ 35 | #define _SAMR21_MTB_INSTANCE_ 36 | 37 | /* ========== Register definition for MTB peripheral ========== */ 38 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 | #define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */ 40 | #define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */ 41 | #define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */ 42 | #define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */ 43 | #define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ 44 | #define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ 45 | #define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ 46 | #define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ 47 | #define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ 48 | #define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ 49 | #define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ 50 | #define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ 51 | #define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */ 52 | #define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */ 53 | #define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */ 54 | #define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */ 55 | #define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */ 56 | #define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */ 57 | #define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */ 58 | #define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */ 59 | #define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */ 60 | #define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */ 61 | #define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */ 62 | #define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */ 63 | #define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */ 64 | #else 65 | #define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */ 66 | #define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */ 67 | #define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */ 68 | #define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */ 69 | #define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */ 70 | #define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */ 71 | #define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */ 72 | #define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */ 73 | #define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */ 74 | #define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */ 75 | #define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */ 76 | #define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */ 77 | #define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */ 78 | #define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */ 79 | #define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */ 80 | #define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */ 81 | #define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */ 82 | #define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */ 83 | #define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */ 84 | #define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */ 85 | #define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */ 86 | #define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */ 87 | #define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */ 88 | #define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */ 89 | #define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */ 90 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 | 92 | 93 | #endif /* _SAMR21_MTB_INSTANCE_ */ 94 | --------------------------------------------------------------------------------