├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── ip ├── nobuild.mk ├── pcpi_v1_0 │ ├── pcpi.xml │ └── pcpi_rtl.xml ├── picobram_if │ ├── PicoBram.xml │ └── PicoBram_rtl.xml ├── picobridge │ ├── component.xml │ ├── picobram_if_bridge.v │ └── xgui │ │ └── PicoBramBridge_v1_0.tcl ├── picorv32_axi │ ├── component.xml │ ├── makefile │ └── xgui │ │ └── picorv32_axi_v1_0.tcl └── picorv32_bram │ ├── component.xml │ ├── makefile │ └── xgui │ ├── picorv32_axi_v1_0.tcl │ └── picorv32_bram_v1_0.tcl ├── notebooks ├── README.md ├── examples │ ├── PicoRV32 Processor BRAM-Memory Processor Demo.ipynb │ ├── PicoRV32 Processor Mixed-Memory Processor Demo.ipynb │ └── README.md └── tutorial │ ├── 0-How-To-RISC-V.ipynb │ ├── 1-Downloading-And-Configuring.ipynb │ ├── 2-Creating-A-Bitstream.ipynb │ ├── 3-Compiling-RISC-V-GCC-Toolchain.ipynb │ ├── 4-Packaging-An-Overlay.ipynb │ └── pictures │ ├── Edit_interface.PNG │ ├── Port_Mapping.PNG │ ├── add_sources.png │ ├── adding_sources.png │ ├── create_new_ip_customization.png │ ├── create_new_ip_identification.png │ ├── create_new_ip_location.png │ ├── create_new_ip_package.png │ ├── create_new_ip_ports.png │ ├── create_new_ip_splash.png │ ├── custom_repository.png │ ├── new_project.png │ ├── overlay_jupyter.png │ ├── overlay_linux.png │ ├── overlay_windows.PNG │ ├── part_selection.png │ ├── riscv_all.png │ ├── riscv_axi_bram.png │ ├── riscv_bram.png │ ├── riscv_bram_size.png │ ├── riscv_diff.png │ ├── riscv_export.png │ ├── riscv_gpio.png │ ├── riscv_map.png │ ├── riscv_multiple_axi.png │ ├── riscv_multiple_interconnect.png │ ├── riscv_multiple_map.png │ ├── riscv_non_axi.png │ ├── riscv_picorv32.png │ ├── riscv_picorv32_1.png │ ├── riscv_picorv32_2.png │ ├── riscv_pl_interconnect.png │ ├── riscv_ps_interconnect.png │ ├── riscv_tcl.png │ ├── riscv_wiring.png │ ├── vivado_add_source_picorv32.png │ ├── vivado_add_sources.png │ ├── vivado_block_diagram_add_ip.png │ ├── vivado_block_diagram_address_map.png │ ├── vivado_block_diagram_export.png │ ├── vivado_block_diagram_hier_bram.png │ ├── vivado_block_diagram_hier_new_picorv32.png │ ├── vivado_block_diagram_hier_wired.png │ ├── vivado_block_diagram_initial.png │ ├── vivado_create_address_map.png │ ├── vivado_create_new_ip_customization.png │ ├── vivado_create_new_ip_identification.png │ ├── vivado_create_new_ip_location.png │ ├── vivado_create_new_ip_package.png │ ├── vivado_create_new_ip_ports.png │ ├── vivado_create_new_ip_splash.png │ ├── vivado_custom_repository.png │ ├── vivado_new_project.png │ ├── vivado_part_selection.png │ ├── vivado_project_done.png │ ├── vivado_project_manager_tutorial.png │ ├── vivado_project_manager_tutorial_bd.png │ └── vivado_welcome.png ├── riscvonpynq ├── Overlay.py ├── PYNQ-Z1.xdc ├── Processor.py ├── Program.py ├── README.md ├── __init__.py ├── build.mk ├── build.tcl ├── magic │ ├── Magic.py │ ├── README.md │ └── __init__.py └── picorv32 │ ├── README.md │ ├── __init__.py │ ├── axi │ ├── .Xil │ │ └── README.md │ ├── README.md │ ├── __init__.py │ ├── build │ │ ├── __init__.py │ │ ├── init.S │ │ ├── makefile │ │ └── picorv32.ld │ ├── makefile │ ├── picorv32.bit │ ├── picorv32.hwh │ ├── picorv32.py │ └── picorv32.tcl │ ├── bram │ ├── .Xil │ │ └── README.md │ ├── README.md │ ├── __init__.py │ ├── build │ │ ├── __init__.py │ │ ├── init.S │ │ ├── makefile │ │ └── picorv32.ld │ ├── makefile │ ├── picorv32.bit │ ├── picorv32.hwh │ ├── picorv32.py │ └── picorv32.tcl │ └── tut │ ├── README.md │ ├── gold │ ├── __init__.py │ ├── build │ │ ├── __init__.py │ │ ├── init.S │ │ ├── makefile │ │ └── picorv32.ld │ ├── tutorial.bit │ ├── tutorial.py │ └── tutorial.tcl │ ├── makefile │ └── tutorial.tcl └── setup.py /.gitignore: -------------------------------------------------------------------------------- 1 | # Byte-compiled / optimized / DLL files 2 | __pycache__/ 3 | *.py[cod] 4 | *$py.class 5 | 6 | # C extensions 7 | *.so 8 | 9 | # Distribution / packaging 10 | .Python 11 | develop-eggs/ 12 | dist/ 13 | downloads/ 14 | eggs/ 15 | .eggs/ 16 | lib/ 17 | lib64/ 18 | parts/ 19 | sdist/ 20 | var/ 21 | wheels/ 22 | *.egg-info/ 23 | .installed.cfg 24 | *.egg 25 | MANIFEST 26 | 27 | # PyInstaller 28 | # Usually these files are written by a python script from a template 29 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 30 | *.manifest 31 | *.spec 32 | 33 | # Installer logs 34 | pip-log.txt 35 | pip-delete-this-directory.txt 36 | 37 | # Unit test / coverage reports 38 | htmlcov/ 39 | .tox/ 40 | .coverage 41 | .coverage.* 42 | .cache 43 | nosetests.xml 44 | coverage.xml 45 | *.cover 46 | .hypothesis/ 47 | .pytest_cache/ 48 | 49 | # Translations 50 | *.mo 51 | *.pot 52 | 53 | # Django stuff: 54 | *.log 55 | local_settings.py 56 | db.sqlite3 57 | 58 | # Flask stuff: 59 | instance/ 60 | .webassets-cache 61 | 62 | # Scrapy stuff: 63 | .scrapy 64 | 65 | # Sphinx documentation 66 | docs/_build/ 67 | 68 | # PyBuilder 69 | target/ 70 | 71 | # Jupyter Notebook 72 | .ipynb_checkpoints 73 | 74 | # pyenv 75 | .python-version 76 | 77 | # celery beat schedule file 78 | celerybeat-schedule 79 | 80 | # SageMath parsed files 81 | *.sage.py 82 | 83 | # Environments 84 | .env 85 | .venv 86 | env/ 87 | venv/ 88 | ENV/ 89 | env.bak/ 90 | venv.bak/ 91 | 92 | # Spyder project settings 93 | .spyderproject 94 | .spyproject 95 | 96 | # Rope project settings 97 | .ropeproject 98 | 99 | # mkdocs documentation 100 | /site 101 | 102 | # mypy 103 | .mypy_cache/ 104 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "picorv32"] 2 | path = picorv32 3 | url = https://github.com/cliffordwolf/picorv32 4 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------- 2 | Copyright (c) 2018, The Regents of the University of California All 3 | rights reserved. 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are 7 | met: 8 | 9 | * Redistributions of source code must retain the above copyright 10 | notice, this list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above 13 | copyright notice, this list of conditions and the following 14 | disclaimer in the documentation and/or other materials provided 15 | with the distribution. 16 | 17 | * Neither the name of The Regents of the University of California 18 | nor the names of its contributors may be used to endorse or 19 | promote products derived from this software without specific 20 | prior written permission. 21 | 22 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | DAMAGE. 34 | ---------------------------------------------------------------------- -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V-On-PYNQ 2 | 3 | This repository demonstrates a library for evaluating RISC-V Projects 4 | from the paper "Everyone's a Critic: A Tool for Evaluating RISC-V 5 | Projects". 6 | 7 | This repository is a python package for the PYNQ 2.1+ distribution on 8 | the PYNQ-Z1 board. You can install this package by running the following command: 9 | 10 | ``` bash 11 | 12 | sudo -H pip3.6 install https://github.com/drichmond/RISC-V-On-PYNQ/ 13 | 14 | ``` 15 | 16 | This will install: 17 | 18 | - The `riscvonpynq` Python package. 19 | 20 | - A RISC-V-Tutorial folder with notebooks describing how to add new 21 | processor overlays 22 | 23 | - A RISC-V-Demo folder with notebooks demonstrating how to interact 24 | with existing processor overlays 25 | 26 | ## `riscvonpynq` Package 27 | 28 | The `riscvonpynq` package contains: 29 | 30 | - An Overlay Driver (a subclass of `pynq.Overlay`). It extends the 31 | Overlay functionality by adding the location of an Overlay class to 32 | the bitstream search path. 33 | 34 | - Jupyter Notebook Magics. This allows Jupyter Notebook Cells to 35 | compile C/C++ and Assembly programs for for RISC-V Processor 36 | Overlays. Users write `main` and can pass arguments as Numpy types. 37 | 38 | - A RISC-V Program Class. This class allows programs to be manipulated 39 | and compiled from Python using pre-existing build files for a processor. 40 | 41 | - Processor drivers (a subclass of `pynq.DefaultHierarchy`). These 42 | drivers allow users to upload binaries, run programs, and read 43 | RISC-V Processor Memory. 44 | 45 | There are two RISC-V Processor Drivers: One driver for RISC-V 46 | Processors with BRAM-only Memory, and one driver for RISC-V Processors 47 | with BRAM and DDR Mixed Memory. 48 | 49 | More examples and demonstrations are available in the notebooks 50 | installed by this package. 51 | 52 | ## RISC-V-Tutorial Notebooks 53 | 54 | The RISC-V Tutorial Notebooks are a set of notebooks describing how to 55 | set up the RISC-V Toolchain, and then build RISC-V processor 56 | overlays. There are five notebooks: 57 | 58 | 1. [Downloading Dependencies](notebooks/tutorial/1-Downloading-And-Configuring.ipynb) 59 | 2. [Creating a FPGA Bitstream](notebooks/tutorial/2-Creating-A-Bitstream.ipynb) 60 | 3. [Compiling the RISC-V GCC Toolchain](notebooks/tutorial/3-Compiling-RISC-V-GCC-Toolchain.ipynb) 61 | 4. [Packaging a RISC-V Overlay](notebooks/tutorial/4-Packaging-An-Overlay.ipynb) 62 | 63 | Completing these notebooks require: 64 | 65 | 1. A PYNQ-Z1 with a 16 GB MicroSD Card 66 | 2. A Host (Windows or Linux) with Vivado 2017.4 67 | 3. An Internet Connection on both computers 68 | 69 | ## RISC-V-Demo Notebooks 70 | 71 | The RISC-V Demonstration notebooks show examples of existing processor 72 | overlays. We provide two example overlays using processors from one 73 | RISC-V Processor Projects. 74 | 75 | - RISC-V [PicoRV32](https://github.com/cliffordwolf/picorv32) AXI Demo 76 | - RISC-V [PicoRV32](https://github.com/cliffordwolf/picorv32) BRAM Demo 77 | 78 | Each notebook demonstrates how to upload programs using the Jupyter 79 | Notebook Magics we have provided. Each processor has a set of build 80 | files (a makefile, init.S file for initialization, and a .ld linker 81 | script) and we briefly describe these in each notebook. 82 | 83 | We have internally tested other processors and will be adding them as 84 | we clean up the code. 85 | 86 | **We welcome pull requests!** 87 | 88 | 89 | 90 | -------------------------------------------------------------------------------- /ip/nobuild.mk: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (c) 2017, Xilinx, Inc. 3 | # All rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are met: 7 | # 8 | # 1. Redistributions of source code must retain the above copyright notice, 9 | # this list of conditions and the following disclaimer. 10 | # 11 | # 2. Redistributions in binary form must reproduce the above copyright 12 | # notice, this list of conditions and the following disclaimer in the 13 | # documentation and/or other materials provided with the distribution. 14 | # 15 | # 3. Neither the name of the copyright holder nor the names of its 16 | # contributors may be used to endorse or promote products derived from 17 | # this software without specific prior written permission. 18 | # 19 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 | # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 | # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 | # CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 | # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 | # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 | # OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 | # WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 | # OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 | # ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | # 31 | ############################################################################### 32 | all: 33 | 34 | clean: 35 | rm -rf *.cache *.hw 36 | -------------------------------------------------------------------------------- /ip/pcpi_v1_0/pcpi.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | cliffordwolf 4 | ip 5 | pcpi 6 | 1.0 7 | false 8 | false 9 | 1 10 | 1 11 | 12 | -------------------------------------------------------------------------------- /ip/pcpi_v1_0/pcpi_rtl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | cliffordwolf 4 | ip 5 | pcpi_rtl 6 | 1.0 7 | 8 | 9 | 10 | pcpi_rs1 11 | Source Register 1 12 | 13 | 14 | true 15 | 16 | 17 | required 18 | 32 19 | 20 | 21 | required 22 | 32 23 | in 24 | 25 | 26 | 27 | 28 | pcpi_rs2 29 | required 30 | 31 | 32 | true 33 | 34 | 35 | required 36 | 32 37 | 38 | 39 | required 40 | 32 41 | in 42 | 43 | 44 | 45 | 46 | pcpi_insn 47 | PCPI Instruction 48 | 49 | 50 | true 51 | 52 | 53 | required 54 | 32 55 | 56 | 57 | required 58 | 32 59 | in 60 | 61 | 62 | 63 | 64 | pcpi_valid 65 | Command Valid 66 | 67 | 68 | required 69 | 1 70 | 71 | 72 | required 73 | 1 74 | in 75 | 76 | 77 | 78 | 79 | pcpi_rd 80 | required 81 | 82 | 83 | true 84 | 85 | 86 | required 87 | 32 88 | in 89 | 90 | 91 | required 92 | 32 93 | 94 | 95 | 96 | 97 | pcpi_wr 98 | Write 99 | 100 | 101 | required 102 | 1 103 | in 104 | 105 | 106 | required 107 | 1 108 | 109 | 110 | 111 | 112 | pcpi_ready 113 | Ready 114 | 115 | 116 | required 117 | 1 118 | in 119 | 120 | 121 | required 122 | 1 123 | 124 | 125 | 126 | 127 | pcpi_wait 128 | Wait 129 | 130 | 131 | required 132 | 1 133 | in 134 | 135 | 136 | required 137 | 1 138 | 139 | 140 | 141 | 142 | 143 | -------------------------------------------------------------------------------- /ip/picobram_if/PicoBram.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | cliffordwolf 4 | ip 5 | PicoBram 6 | 1.0 7 | false 8 | false 9 | 10 | 1 11 | 1 12 | 13 | -------------------------------------------------------------------------------- /ip/picobram_if/PicoBram_rtl.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | cliffordwolf 4 | ip 5 | PicoBram_rtl 6 | 1.0 7 | 8 | 9 | 10 | WDATA 11 | WDATA 12 | Data Out Bus 13 | 14 | 15 | true 16 | 17 | 18 | 19 | in 20 | 21 | 22 | 23 | 24 | RDATA 25 | RDATA 26 | Data In Bus 27 | 28 | 29 | true 30 | 31 | 32 | in 33 | 34 | 35 | 36 | 37 | 38 | ADDR 39 | ADDR 40 | Address Signal 41 | 42 | 43 | true 44 | 45 | 46 | required 47 | 48 | 49 | required 50 | in 51 | 52 | 53 | 54 | 55 | WSTRB 56 | Write Byte-Enables 57 | 58 | 59 | required 60 | 1 61 | 62 | 63 | required 64 | 1 65 | in 66 | 67 | 68 | 69 | 70 | VALID 71 | Master Address Valid 72 | 73 | 74 | required 75 | 1 76 | 77 | 78 | required 79 | 1 80 | in 81 | 82 | 83 | 84 | 85 | READY 86 | Slave Data Valid 87 | 88 | 89 | required 90 | 1 91 | in 92 | 93 | 94 | required 95 | 1 96 | 97 | 98 | 99 | 100 | INSTR 101 | Instruction Read 102 | 103 | 104 | 1 105 | 106 | 107 | 1 108 | in 109 | 110 | 111 | 112 | 113 | READ 114 | Master Read Signal 115 | 116 | 117 | 1 118 | 119 | 120 | 1 121 | in 122 | 123 | 124 | 125 | 126 | WRITE 127 | Master Write Signal 128 | 129 | 130 | 1 131 | 132 | 133 | 1 134 | in 135 | 136 | 137 | 138 | 139 | 140 | -------------------------------------------------------------------------------- /ip/picobridge/picobram_if_bridge.v: -------------------------------------------------------------------------------- 1 | module PicoBramBridge 2 | #( parameter [31:0] C_DELAY = 1, 3 | parameter [0:0] C_USE_LOOKAHEAD = 0, 4 | parameter [31:0] C_ADDR_WIDTH = 32 5 | ) 6 | ( 7 | input CLK, 8 | input RSTN, 9 | 10 | input MEM_VALID, 11 | input MEM_INSTR, 12 | output MEM_READY, 13 | 14 | input [31:0] MEM_ADDR, 15 | input [31:0] MEM_WDATA, 16 | input [ 3:0] MEM_WSTRB, 17 | output [31:0] MEM_RDATA, 18 | 19 | // Look-Ahead Interface 20 | input MEM_LA_READ, 21 | input MEM_LA_WRITE, 22 | input [31:0] MEM_LA_ADDR, 23 | input [31:0] MEM_LA_WDATA, 24 | input [ 3:0] MEM_LA_WSTRB, 25 | 26 | output [C_ADDR_WIDTH-1:0] BRAM_ADDR, 27 | output BRAM_CLK, 28 | output [31:0] BRAM_DIN, 29 | input [31:0] BRAM_DOUT, 30 | output BRAM_EN, 31 | output BRAM_RST, 32 | output [3:0] BRAM_WE 33 | ); 34 | 35 | reg [C_DELAY-1:0] rDelay; 36 | wire [C_DELAY:0] wDelay; 37 | 38 | assign wDelay = {rDelay, MEM_VALID}; 39 | 40 | always @(posedge CLK) begin 41 | if (RSTN & ~(MEM_VALID & MEM_READY)) begin 42 | rDelay <= wDelay[C_DELAY-1:0]; 43 | end else begin 44 | rDelay <= 0; 45 | end 46 | end 47 | 48 | assign BRAM_ADDR = C_USE_LOOKAHEAD ? MEM_LA_ADDR : MEM_ADDR; 49 | assign BRAM_CLK = CLK; 50 | assign BRAM_DIN = C_USE_LOOKAHEAD ? MEM_LA_WDATA : MEM_WDATA; 51 | assign BRAM_EN = C_USE_LOOKAHEAD ? 52 | MEM_LA_WRITE | MEM_LA_READ | MEM_VALID : 53 | wDelay[C_DELAY-1:0] != 0; 54 | 55 | assign BRAM_RST = ~RSTN; 56 | assign BRAM_WE = C_USE_LOOKAHEAD ? MEM_LA_WSTRB & {4{MEM_LA_WRITE}} : 57 | MEM_WSTRB; 58 | 59 | assign MEM_RDATA = BRAM_DOUT; 60 | assign MEM_READY = C_USE_LOOKAHEAD ? wDelay[C_DELAY - 1] : wDelay[C_DELAY]; 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /ip/picobridge/xgui/PicoBramBridge_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "C_DELAY" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "C_USE_LOOKAHEAD" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.C_ADDR_WIDTH { PARAM_VALUE.C_ADDR_WIDTH } { 13 | # Procedure called to update C_ADDR_WIDTH when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.C_ADDR_WIDTH { PARAM_VALUE.C_ADDR_WIDTH } { 17 | # Procedure called to validate C_ADDR_WIDTH 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.C_DELAY { PARAM_VALUE.C_DELAY } { 22 | # Procedure called to update C_DELAY when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.C_DELAY { PARAM_VALUE.C_DELAY } { 26 | # Procedure called to validate C_DELAY 27 | return true 28 | } 29 | 30 | proc update_PARAM_VALUE.C_USE_LOOKAHEAD { PARAM_VALUE.C_USE_LOOKAHEAD } { 31 | # Procedure called to update C_USE_LOOKAHEAD when any of the dependent parameters in the arguments change 32 | } 33 | 34 | proc validate_PARAM_VALUE.C_USE_LOOKAHEAD { PARAM_VALUE.C_USE_LOOKAHEAD } { 35 | # Procedure called to validate C_USE_LOOKAHEAD 36 | return true 37 | } 38 | 39 | 40 | proc update_MODELPARAM_VALUE.C_DELAY { MODELPARAM_VALUE.C_DELAY PARAM_VALUE.C_DELAY } { 41 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 42 | set_property value [get_property value ${PARAM_VALUE.C_DELAY}] ${MODELPARAM_VALUE.C_DELAY} 43 | } 44 | 45 | proc update_MODELPARAM_VALUE.C_USE_LOOKAHEAD { MODELPARAM_VALUE.C_USE_LOOKAHEAD PARAM_VALUE.C_USE_LOOKAHEAD } { 46 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 47 | set_property value [get_property value ${PARAM_VALUE.C_USE_LOOKAHEAD}] ${MODELPARAM_VALUE.C_USE_LOOKAHEAD} 48 | } 49 | 50 | proc update_MODELPARAM_VALUE.C_ADDR_WIDTH { MODELPARAM_VALUE.C_ADDR_WIDTH PARAM_VALUE.C_ADDR_WIDTH } { 51 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 52 | set_property value [get_property value ${PARAM_VALUE.C_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_ADDR_WIDTH} 53 | } 54 | 55 | -------------------------------------------------------------------------------- /ip/picorv32_axi/makefile: -------------------------------------------------------------------------------- 1 | include ../nobuild.mk 2 | -------------------------------------------------------------------------------- /ip/picorv32_axi/xgui/picorv32_axi_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "BARREL_SHIFTER" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "CATCH_ILLINSN" -parent ${Page_0} 8 | ipgui::add_param $IPINST -name "CATCH_MISALIGN" -parent ${Page_0} 9 | ipgui::add_param $IPINST -name "COMPRESSED_ISA" -parent ${Page_0} 10 | ipgui::add_param $IPINST -name "ENABLE_COUNTERS" -parent ${Page_0} 11 | ipgui::add_param $IPINST -name "ENABLE_COUNTERS64" -parent ${Page_0} 12 | ipgui::add_param $IPINST -name "ENABLE_DIV" -parent ${Page_0} 13 | ipgui::add_param $IPINST -name "ENABLE_FAST_MUL" -parent ${Page_0} 14 | ipgui::add_param $IPINST -name "ENABLE_IRQ" -parent ${Page_0} 15 | ipgui::add_param $IPINST -name "ENABLE_IRQ_QREGS" -parent ${Page_0} 16 | ipgui::add_param $IPINST -name "ENABLE_IRQ_TIMER" -parent ${Page_0} 17 | ipgui::add_param $IPINST -name "ENABLE_MUL" -parent ${Page_0} 18 | ipgui::add_param $IPINST -name "ENABLE_PCPI" -parent ${Page_0} 19 | ipgui::add_param $IPINST -name "ENABLE_REGS_16_31" -parent ${Page_0} 20 | ipgui::add_param $IPINST -name "ENABLE_REGS_DUALPORT" -parent ${Page_0} 21 | ipgui::add_param $IPINST -name "ENABLE_TRACE" -parent ${Page_0} 22 | ipgui::add_param $IPINST -name "LATCHED_IRQ" -parent ${Page_0} 23 | ipgui::add_param $IPINST -name "MASKED_IRQ" -parent ${Page_0} 24 | ipgui::add_param $IPINST -name "PROGADDR_IRQ" -parent ${Page_0} 25 | ipgui::add_param $IPINST -name "PROGADDR_RESET" -parent ${Page_0} 26 | ipgui::add_param $IPINST -name "REGS_INIT_ZERO" -parent ${Page_0} 27 | ipgui::add_param $IPINST -name "STACKADDR" -parent ${Page_0} 28 | ipgui::add_param $IPINST -name "TWO_CYCLE_ALU" -parent ${Page_0} 29 | ipgui::add_param $IPINST -name "TWO_CYCLE_COMPARE" -parent ${Page_0} 30 | ipgui::add_param $IPINST -name "TWO_STAGE_SHIFT" -parent ${Page_0} 31 | 32 | 33 | } 34 | 35 | proc update_PARAM_VALUE.BARREL_SHIFTER { PARAM_VALUE.BARREL_SHIFTER } { 36 | # Procedure called to update BARREL_SHIFTER when any of the dependent parameters in the arguments change 37 | } 38 | 39 | proc validate_PARAM_VALUE.BARREL_SHIFTER { PARAM_VALUE.BARREL_SHIFTER } { 40 | # Procedure called to validate BARREL_SHIFTER 41 | return true 42 | } 43 | 44 | proc update_PARAM_VALUE.CATCH_ILLINSN { PARAM_VALUE.CATCH_ILLINSN } { 45 | # Procedure called to update CATCH_ILLINSN when any of the dependent parameters in the arguments change 46 | } 47 | 48 | proc validate_PARAM_VALUE.CATCH_ILLINSN { PARAM_VALUE.CATCH_ILLINSN } { 49 | # Procedure called to validate CATCH_ILLINSN 50 | return true 51 | } 52 | 53 | proc update_PARAM_VALUE.CATCH_MISALIGN { PARAM_VALUE.CATCH_MISALIGN } { 54 | # Procedure called to update CATCH_MISALIGN when any of the dependent parameters in the arguments change 55 | } 56 | 57 | proc validate_PARAM_VALUE.CATCH_MISALIGN { PARAM_VALUE.CATCH_MISALIGN } { 58 | # Procedure called to validate CATCH_MISALIGN 59 | return true 60 | } 61 | 62 | proc update_PARAM_VALUE.COMPRESSED_ISA { PARAM_VALUE.COMPRESSED_ISA } { 63 | # Procedure called to update COMPRESSED_ISA when any of the dependent parameters in the arguments change 64 | } 65 | 66 | proc validate_PARAM_VALUE.COMPRESSED_ISA { PARAM_VALUE.COMPRESSED_ISA } { 67 | # Procedure called to validate COMPRESSED_ISA 68 | return true 69 | } 70 | 71 | proc update_PARAM_VALUE.ENABLE_COUNTERS { PARAM_VALUE.ENABLE_COUNTERS } { 72 | # Procedure called to update ENABLE_COUNTERS when any of the dependent parameters in the arguments change 73 | } 74 | 75 | proc validate_PARAM_VALUE.ENABLE_COUNTERS { PARAM_VALUE.ENABLE_COUNTERS } { 76 | # Procedure called to validate ENABLE_COUNTERS 77 | return true 78 | } 79 | 80 | proc update_PARAM_VALUE.ENABLE_COUNTERS64 { PARAM_VALUE.ENABLE_COUNTERS64 } { 81 | # Procedure called to update ENABLE_COUNTERS64 when any of the dependent parameters in the arguments change 82 | } 83 | 84 | proc validate_PARAM_VALUE.ENABLE_COUNTERS64 { PARAM_VALUE.ENABLE_COUNTERS64 } { 85 | # Procedure called to validate ENABLE_COUNTERS64 86 | return true 87 | } 88 | 89 | proc update_PARAM_VALUE.ENABLE_DIV { PARAM_VALUE.ENABLE_DIV } { 90 | # Procedure called to update ENABLE_DIV when any of the dependent parameters in the arguments change 91 | } 92 | 93 | proc validate_PARAM_VALUE.ENABLE_DIV { PARAM_VALUE.ENABLE_DIV } { 94 | # Procedure called to validate ENABLE_DIV 95 | return true 96 | } 97 | 98 | proc update_PARAM_VALUE.ENABLE_FAST_MUL { PARAM_VALUE.ENABLE_FAST_MUL } { 99 | # Procedure called to update ENABLE_FAST_MUL when any of the dependent parameters in the arguments change 100 | } 101 | 102 | proc validate_PARAM_VALUE.ENABLE_FAST_MUL { PARAM_VALUE.ENABLE_FAST_MUL } { 103 | # Procedure called to validate ENABLE_FAST_MUL 104 | return true 105 | } 106 | 107 | proc update_PARAM_VALUE.ENABLE_IRQ { PARAM_VALUE.ENABLE_IRQ } { 108 | # Procedure called to update ENABLE_IRQ when any of the dependent parameters in the arguments change 109 | } 110 | 111 | proc validate_PARAM_VALUE.ENABLE_IRQ { PARAM_VALUE.ENABLE_IRQ } { 112 | # Procedure called to validate ENABLE_IRQ 113 | return true 114 | } 115 | 116 | proc update_PARAM_VALUE.ENABLE_IRQ_QREGS { PARAM_VALUE.ENABLE_IRQ_QREGS } { 117 | # Procedure called to update ENABLE_IRQ_QREGS when any of the dependent parameters in the arguments change 118 | } 119 | 120 | proc validate_PARAM_VALUE.ENABLE_IRQ_QREGS { PARAM_VALUE.ENABLE_IRQ_QREGS } { 121 | # Procedure called to validate ENABLE_IRQ_QREGS 122 | return true 123 | } 124 | 125 | proc update_PARAM_VALUE.ENABLE_IRQ_TIMER { PARAM_VALUE.ENABLE_IRQ_TIMER } { 126 | # Procedure called to update ENABLE_IRQ_TIMER when any of the dependent parameters in the arguments change 127 | } 128 | 129 | proc validate_PARAM_VALUE.ENABLE_IRQ_TIMER { PARAM_VALUE.ENABLE_IRQ_TIMER } { 130 | # Procedure called to validate ENABLE_IRQ_TIMER 131 | return true 132 | } 133 | 134 | proc update_PARAM_VALUE.ENABLE_MUL { PARAM_VALUE.ENABLE_MUL } { 135 | # Procedure called to update ENABLE_MUL when any of the dependent parameters in the arguments change 136 | } 137 | 138 | proc validate_PARAM_VALUE.ENABLE_MUL { PARAM_VALUE.ENABLE_MUL } { 139 | # Procedure called to validate ENABLE_MUL 140 | return true 141 | } 142 | 143 | proc update_PARAM_VALUE.ENABLE_PCPI { PARAM_VALUE.ENABLE_PCPI } { 144 | # Procedure called to update ENABLE_PCPI when any of the dependent parameters in the arguments change 145 | } 146 | 147 | proc validate_PARAM_VALUE.ENABLE_PCPI { PARAM_VALUE.ENABLE_PCPI } { 148 | # Procedure called to validate ENABLE_PCPI 149 | return true 150 | } 151 | 152 | proc update_PARAM_VALUE.ENABLE_REGS_16_31 { PARAM_VALUE.ENABLE_REGS_16_31 } { 153 | # Procedure called to update ENABLE_REGS_16_31 when any of the dependent parameters in the arguments change 154 | } 155 | 156 | proc validate_PARAM_VALUE.ENABLE_REGS_16_31 { PARAM_VALUE.ENABLE_REGS_16_31 } { 157 | # Procedure called to validate ENABLE_REGS_16_31 158 | return true 159 | } 160 | 161 | proc update_PARAM_VALUE.ENABLE_REGS_DUALPORT { PARAM_VALUE.ENABLE_REGS_DUALPORT } { 162 | # Procedure called to update ENABLE_REGS_DUALPORT when any of the dependent parameters in the arguments change 163 | } 164 | 165 | proc validate_PARAM_VALUE.ENABLE_REGS_DUALPORT { PARAM_VALUE.ENABLE_REGS_DUALPORT } { 166 | # Procedure called to validate ENABLE_REGS_DUALPORT 167 | return true 168 | } 169 | 170 | proc update_PARAM_VALUE.ENABLE_TRACE { PARAM_VALUE.ENABLE_TRACE } { 171 | # Procedure called to update ENABLE_TRACE when any of the dependent parameters in the arguments change 172 | } 173 | 174 | proc validate_PARAM_VALUE.ENABLE_TRACE { PARAM_VALUE.ENABLE_TRACE } { 175 | # Procedure called to validate ENABLE_TRACE 176 | return true 177 | } 178 | 179 | proc update_PARAM_VALUE.LATCHED_IRQ { PARAM_VALUE.LATCHED_IRQ } { 180 | # Procedure called to update LATCHED_IRQ when any of the dependent parameters in the arguments change 181 | } 182 | 183 | proc validate_PARAM_VALUE.LATCHED_IRQ { PARAM_VALUE.LATCHED_IRQ } { 184 | # Procedure called to validate LATCHED_IRQ 185 | return true 186 | } 187 | 188 | proc update_PARAM_VALUE.MASKED_IRQ { PARAM_VALUE.MASKED_IRQ } { 189 | # Procedure called to update MASKED_IRQ when any of the dependent parameters in the arguments change 190 | } 191 | 192 | proc validate_PARAM_VALUE.MASKED_IRQ { PARAM_VALUE.MASKED_IRQ } { 193 | # Procedure called to validate MASKED_IRQ 194 | return true 195 | } 196 | 197 | proc update_PARAM_VALUE.PROGADDR_IRQ { PARAM_VALUE.PROGADDR_IRQ } { 198 | # Procedure called to update PROGADDR_IRQ when any of the dependent parameters in the arguments change 199 | } 200 | 201 | proc validate_PARAM_VALUE.PROGADDR_IRQ { PARAM_VALUE.PROGADDR_IRQ } { 202 | # Procedure called to validate PROGADDR_IRQ 203 | return true 204 | } 205 | 206 | proc update_PARAM_VALUE.PROGADDR_RESET { PARAM_VALUE.PROGADDR_RESET } { 207 | # Procedure called to update PROGADDR_RESET when any of the dependent parameters in the arguments change 208 | } 209 | 210 | proc validate_PARAM_VALUE.PROGADDR_RESET { PARAM_VALUE.PROGADDR_RESET } { 211 | # Procedure called to validate PROGADDR_RESET 212 | return true 213 | } 214 | 215 | proc update_PARAM_VALUE.REGS_INIT_ZERO { PARAM_VALUE.REGS_INIT_ZERO } { 216 | # Procedure called to update REGS_INIT_ZERO when any of the dependent parameters in the arguments change 217 | } 218 | 219 | proc validate_PARAM_VALUE.REGS_INIT_ZERO { PARAM_VALUE.REGS_INIT_ZERO } { 220 | # Procedure called to validate REGS_INIT_ZERO 221 | return true 222 | } 223 | 224 | proc update_PARAM_VALUE.STACKADDR { PARAM_VALUE.STACKADDR } { 225 | # Procedure called to update STACKADDR when any of the dependent parameters in the arguments change 226 | } 227 | 228 | proc validate_PARAM_VALUE.STACKADDR { PARAM_VALUE.STACKADDR } { 229 | # Procedure called to validate STACKADDR 230 | return true 231 | } 232 | 233 | proc update_PARAM_VALUE.TWO_CYCLE_ALU { PARAM_VALUE.TWO_CYCLE_ALU } { 234 | # Procedure called to update TWO_CYCLE_ALU when any of the dependent parameters in the arguments change 235 | } 236 | 237 | proc validate_PARAM_VALUE.TWO_CYCLE_ALU { PARAM_VALUE.TWO_CYCLE_ALU } { 238 | # Procedure called to validate TWO_CYCLE_ALU 239 | return true 240 | } 241 | 242 | proc update_PARAM_VALUE.TWO_CYCLE_COMPARE { PARAM_VALUE.TWO_CYCLE_COMPARE } { 243 | # Procedure called to update TWO_CYCLE_COMPARE when any of the dependent parameters in the arguments change 244 | } 245 | 246 | proc validate_PARAM_VALUE.TWO_CYCLE_COMPARE { PARAM_VALUE.TWO_CYCLE_COMPARE } { 247 | # Procedure called to validate TWO_CYCLE_COMPARE 248 | return true 249 | } 250 | 251 | proc update_PARAM_VALUE.TWO_STAGE_SHIFT { PARAM_VALUE.TWO_STAGE_SHIFT } { 252 | # Procedure called to update TWO_STAGE_SHIFT when any of the dependent parameters in the arguments change 253 | } 254 | 255 | proc validate_PARAM_VALUE.TWO_STAGE_SHIFT { PARAM_VALUE.TWO_STAGE_SHIFT } { 256 | # Procedure called to validate TWO_STAGE_SHIFT 257 | return true 258 | } 259 | 260 | 261 | proc update_MODELPARAM_VALUE.ENABLE_COUNTERS { MODELPARAM_VALUE.ENABLE_COUNTERS PARAM_VALUE.ENABLE_COUNTERS } { 262 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 263 | set_property value [get_property value ${PARAM_VALUE.ENABLE_COUNTERS}] ${MODELPARAM_VALUE.ENABLE_COUNTERS} 264 | } 265 | 266 | proc update_MODELPARAM_VALUE.ENABLE_COUNTERS64 { MODELPARAM_VALUE.ENABLE_COUNTERS64 PARAM_VALUE.ENABLE_COUNTERS64 } { 267 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 268 | set_property value [get_property value ${PARAM_VALUE.ENABLE_COUNTERS64}] ${MODELPARAM_VALUE.ENABLE_COUNTERS64} 269 | } 270 | 271 | proc update_MODELPARAM_VALUE.ENABLE_REGS_16_31 { MODELPARAM_VALUE.ENABLE_REGS_16_31 PARAM_VALUE.ENABLE_REGS_16_31 } { 272 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 273 | set_property value [get_property value ${PARAM_VALUE.ENABLE_REGS_16_31}] ${MODELPARAM_VALUE.ENABLE_REGS_16_31} 274 | } 275 | 276 | proc update_MODELPARAM_VALUE.ENABLE_REGS_DUALPORT { MODELPARAM_VALUE.ENABLE_REGS_DUALPORT PARAM_VALUE.ENABLE_REGS_DUALPORT } { 277 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 278 | set_property value [get_property value ${PARAM_VALUE.ENABLE_REGS_DUALPORT}] ${MODELPARAM_VALUE.ENABLE_REGS_DUALPORT} 279 | } 280 | 281 | proc update_MODELPARAM_VALUE.TWO_STAGE_SHIFT { MODELPARAM_VALUE.TWO_STAGE_SHIFT PARAM_VALUE.TWO_STAGE_SHIFT } { 282 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 283 | set_property value [get_property value ${PARAM_VALUE.TWO_STAGE_SHIFT}] ${MODELPARAM_VALUE.TWO_STAGE_SHIFT} 284 | } 285 | 286 | proc update_MODELPARAM_VALUE.BARREL_SHIFTER { MODELPARAM_VALUE.BARREL_SHIFTER PARAM_VALUE.BARREL_SHIFTER } { 287 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 288 | set_property value [get_property value ${PARAM_VALUE.BARREL_SHIFTER}] ${MODELPARAM_VALUE.BARREL_SHIFTER} 289 | } 290 | 291 | proc update_MODELPARAM_VALUE.TWO_CYCLE_COMPARE { MODELPARAM_VALUE.TWO_CYCLE_COMPARE PARAM_VALUE.TWO_CYCLE_COMPARE } { 292 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 293 | set_property value [get_property value ${PARAM_VALUE.TWO_CYCLE_COMPARE}] ${MODELPARAM_VALUE.TWO_CYCLE_COMPARE} 294 | } 295 | 296 | proc update_MODELPARAM_VALUE.TWO_CYCLE_ALU { MODELPARAM_VALUE.TWO_CYCLE_ALU PARAM_VALUE.TWO_CYCLE_ALU } { 297 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 298 | set_property value [get_property value ${PARAM_VALUE.TWO_CYCLE_ALU}] ${MODELPARAM_VALUE.TWO_CYCLE_ALU} 299 | } 300 | 301 | proc update_MODELPARAM_VALUE.COMPRESSED_ISA { MODELPARAM_VALUE.COMPRESSED_ISA PARAM_VALUE.COMPRESSED_ISA } { 302 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 303 | set_property value [get_property value ${PARAM_VALUE.COMPRESSED_ISA}] ${MODELPARAM_VALUE.COMPRESSED_ISA} 304 | } 305 | 306 | proc update_MODELPARAM_VALUE.CATCH_MISALIGN { MODELPARAM_VALUE.CATCH_MISALIGN PARAM_VALUE.CATCH_MISALIGN } { 307 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 308 | set_property value [get_property value ${PARAM_VALUE.CATCH_MISALIGN}] ${MODELPARAM_VALUE.CATCH_MISALIGN} 309 | } 310 | 311 | proc update_MODELPARAM_VALUE.CATCH_ILLINSN { MODELPARAM_VALUE.CATCH_ILLINSN PARAM_VALUE.CATCH_ILLINSN } { 312 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 313 | set_property value [get_property value ${PARAM_VALUE.CATCH_ILLINSN}] ${MODELPARAM_VALUE.CATCH_ILLINSN} 314 | } 315 | 316 | proc update_MODELPARAM_VALUE.ENABLE_PCPI { MODELPARAM_VALUE.ENABLE_PCPI PARAM_VALUE.ENABLE_PCPI } { 317 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 318 | set_property value [get_property value ${PARAM_VALUE.ENABLE_PCPI}] ${MODELPARAM_VALUE.ENABLE_PCPI} 319 | } 320 | 321 | proc update_MODELPARAM_VALUE.ENABLE_MUL { MODELPARAM_VALUE.ENABLE_MUL PARAM_VALUE.ENABLE_MUL } { 322 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 323 | set_property value [get_property value ${PARAM_VALUE.ENABLE_MUL}] ${MODELPARAM_VALUE.ENABLE_MUL} 324 | } 325 | 326 | proc update_MODELPARAM_VALUE.ENABLE_FAST_MUL { MODELPARAM_VALUE.ENABLE_FAST_MUL PARAM_VALUE.ENABLE_FAST_MUL } { 327 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 328 | set_property value [get_property value ${PARAM_VALUE.ENABLE_FAST_MUL}] ${MODELPARAM_VALUE.ENABLE_FAST_MUL} 329 | } 330 | 331 | proc update_MODELPARAM_VALUE.ENABLE_DIV { MODELPARAM_VALUE.ENABLE_DIV PARAM_VALUE.ENABLE_DIV } { 332 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 333 | set_property value [get_property value ${PARAM_VALUE.ENABLE_DIV}] ${MODELPARAM_VALUE.ENABLE_DIV} 334 | } 335 | 336 | proc update_MODELPARAM_VALUE.ENABLE_IRQ { MODELPARAM_VALUE.ENABLE_IRQ PARAM_VALUE.ENABLE_IRQ } { 337 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 338 | set_property value [get_property value ${PARAM_VALUE.ENABLE_IRQ}] ${MODELPARAM_VALUE.ENABLE_IRQ} 339 | } 340 | 341 | proc update_MODELPARAM_VALUE.ENABLE_IRQ_QREGS { MODELPARAM_VALUE.ENABLE_IRQ_QREGS PARAM_VALUE.ENABLE_IRQ_QREGS } { 342 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 343 | set_property value [get_property value ${PARAM_VALUE.ENABLE_IRQ_QREGS}] ${MODELPARAM_VALUE.ENABLE_IRQ_QREGS} 344 | } 345 | 346 | proc update_MODELPARAM_VALUE.ENABLE_IRQ_TIMER { MODELPARAM_VALUE.ENABLE_IRQ_TIMER PARAM_VALUE.ENABLE_IRQ_TIMER } { 347 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 348 | set_property value [get_property value ${PARAM_VALUE.ENABLE_IRQ_TIMER}] ${MODELPARAM_VALUE.ENABLE_IRQ_TIMER} 349 | } 350 | 351 | proc update_MODELPARAM_VALUE.ENABLE_TRACE { MODELPARAM_VALUE.ENABLE_TRACE PARAM_VALUE.ENABLE_TRACE } { 352 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 353 | set_property value [get_property value ${PARAM_VALUE.ENABLE_TRACE}] ${MODELPARAM_VALUE.ENABLE_TRACE} 354 | } 355 | 356 | proc update_MODELPARAM_VALUE.REGS_INIT_ZERO { MODELPARAM_VALUE.REGS_INIT_ZERO PARAM_VALUE.REGS_INIT_ZERO } { 357 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 358 | set_property value [get_property value ${PARAM_VALUE.REGS_INIT_ZERO}] ${MODELPARAM_VALUE.REGS_INIT_ZERO} 359 | } 360 | 361 | proc update_MODELPARAM_VALUE.MASKED_IRQ { MODELPARAM_VALUE.MASKED_IRQ PARAM_VALUE.MASKED_IRQ } { 362 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 363 | set_property value [get_property value ${PARAM_VALUE.MASKED_IRQ}] ${MODELPARAM_VALUE.MASKED_IRQ} 364 | } 365 | 366 | proc update_MODELPARAM_VALUE.LATCHED_IRQ { MODELPARAM_VALUE.LATCHED_IRQ PARAM_VALUE.LATCHED_IRQ } { 367 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 368 | set_property value [get_property value ${PARAM_VALUE.LATCHED_IRQ}] ${MODELPARAM_VALUE.LATCHED_IRQ} 369 | } 370 | 371 | proc update_MODELPARAM_VALUE.PROGADDR_RESET { MODELPARAM_VALUE.PROGADDR_RESET PARAM_VALUE.PROGADDR_RESET } { 372 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 373 | set_property value [get_property value ${PARAM_VALUE.PROGADDR_RESET}] ${MODELPARAM_VALUE.PROGADDR_RESET} 374 | } 375 | 376 | proc update_MODELPARAM_VALUE.PROGADDR_IRQ { MODELPARAM_VALUE.PROGADDR_IRQ PARAM_VALUE.PROGADDR_IRQ } { 377 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 378 | set_property value [get_property value ${PARAM_VALUE.PROGADDR_IRQ}] ${MODELPARAM_VALUE.PROGADDR_IRQ} 379 | } 380 | 381 | proc update_MODELPARAM_VALUE.STACKADDR { MODELPARAM_VALUE.STACKADDR PARAM_VALUE.STACKADDR } { 382 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 383 | set_property value [get_property value ${PARAM_VALUE.STACKADDR}] ${MODELPARAM_VALUE.STACKADDR} 384 | } 385 | 386 | -------------------------------------------------------------------------------- /ip/picorv32_bram/makefile: -------------------------------------------------------------------------------- 1 | include ../nobuild.mk 2 | -------------------------------------------------------------------------------- /ip/picorv32_bram/xgui/picorv32_axi_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "BARREL_SHIFTER" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "CATCH_ILLINSN" -parent ${Page_0} 8 | ipgui::add_param $IPINST -name "CATCH_MISALIGN" -parent ${Page_0} 9 | ipgui::add_param $IPINST -name "COMPRESSED_ISA" -parent ${Page_0} 10 | ipgui::add_param $IPINST -name "ENABLE_COUNTERS" -parent ${Page_0} 11 | ipgui::add_param $IPINST -name "ENABLE_COUNTERS64" -parent ${Page_0} 12 | ipgui::add_param $IPINST -name "ENABLE_DIV" -parent ${Page_0} 13 | ipgui::add_param $IPINST -name "ENABLE_FAST_MUL" -parent ${Page_0} 14 | ipgui::add_param $IPINST -name "ENABLE_IRQ" -parent ${Page_0} 15 | ipgui::add_param $IPINST -name "ENABLE_IRQ_QREGS" -parent ${Page_0} 16 | ipgui::add_param $IPINST -name "ENABLE_IRQ_TIMER" -parent ${Page_0} 17 | ipgui::add_param $IPINST -name "ENABLE_MUL" -parent ${Page_0} 18 | ipgui::add_param $IPINST -name "ENABLE_PCPI" -parent ${Page_0} 19 | ipgui::add_param $IPINST -name "ENABLE_REGS_16_31" -parent ${Page_0} 20 | ipgui::add_param $IPINST -name "ENABLE_REGS_DUALPORT" -parent ${Page_0} 21 | ipgui::add_param $IPINST -name "ENABLE_TRACE" -parent ${Page_0} 22 | ipgui::add_param $IPINST -name "LATCHED_IRQ" -parent ${Page_0} 23 | ipgui::add_param $IPINST -name "MASKED_IRQ" -parent ${Page_0} 24 | ipgui::add_param $IPINST -name "PROGADDR_IRQ" -parent ${Page_0} 25 | ipgui::add_param $IPINST -name "PROGADDR_RESET" -parent ${Page_0} 26 | ipgui::add_param $IPINST -name "REGS_INIT_ZERO" -parent ${Page_0} 27 | ipgui::add_param $IPINST -name "STACKADDR" -parent ${Page_0} 28 | ipgui::add_param $IPINST -name "TWO_CYCLE_ALU" -parent ${Page_0} 29 | ipgui::add_param $IPINST -name "TWO_CYCLE_COMPARE" -parent ${Page_0} 30 | ipgui::add_param $IPINST -name "TWO_STAGE_SHIFT" -parent ${Page_0} 31 | 32 | 33 | } 34 | 35 | proc update_PARAM_VALUE.BARREL_SHIFTER { PARAM_VALUE.BARREL_SHIFTER } { 36 | # Procedure called to update BARREL_SHIFTER when any of the dependent parameters in the arguments change 37 | } 38 | 39 | proc validate_PARAM_VALUE.BARREL_SHIFTER { PARAM_VALUE.BARREL_SHIFTER } { 40 | # Procedure called to validate BARREL_SHIFTER 41 | return true 42 | } 43 | 44 | proc update_PARAM_VALUE.CATCH_ILLINSN { PARAM_VALUE.CATCH_ILLINSN } { 45 | # Procedure called to update CATCH_ILLINSN when any of the dependent parameters in the arguments change 46 | } 47 | 48 | proc validate_PARAM_VALUE.CATCH_ILLINSN { PARAM_VALUE.CATCH_ILLINSN } { 49 | # Procedure called to validate CATCH_ILLINSN 50 | return true 51 | } 52 | 53 | proc update_PARAM_VALUE.CATCH_MISALIGN { PARAM_VALUE.CATCH_MISALIGN } { 54 | # Procedure called to update CATCH_MISALIGN when any of the dependent parameters in the arguments change 55 | } 56 | 57 | proc validate_PARAM_VALUE.CATCH_MISALIGN { PARAM_VALUE.CATCH_MISALIGN } { 58 | # Procedure called to validate CATCH_MISALIGN 59 | return true 60 | } 61 | 62 | proc update_PARAM_VALUE.COMPRESSED_ISA { PARAM_VALUE.COMPRESSED_ISA } { 63 | # Procedure called to update COMPRESSED_ISA when any of the dependent parameters in the arguments change 64 | } 65 | 66 | proc validate_PARAM_VALUE.COMPRESSED_ISA { PARAM_VALUE.COMPRESSED_ISA } { 67 | # Procedure called to validate COMPRESSED_ISA 68 | return true 69 | } 70 | 71 | proc update_PARAM_VALUE.ENABLE_COUNTERS { PARAM_VALUE.ENABLE_COUNTERS } { 72 | # Procedure called to update ENABLE_COUNTERS when any of the dependent parameters in the arguments change 73 | } 74 | 75 | proc validate_PARAM_VALUE.ENABLE_COUNTERS { PARAM_VALUE.ENABLE_COUNTERS } { 76 | # Procedure called to validate ENABLE_COUNTERS 77 | return true 78 | } 79 | 80 | proc update_PARAM_VALUE.ENABLE_COUNTERS64 { PARAM_VALUE.ENABLE_COUNTERS64 } { 81 | # Procedure called to update ENABLE_COUNTERS64 when any of the dependent parameters in the arguments change 82 | } 83 | 84 | proc validate_PARAM_VALUE.ENABLE_COUNTERS64 { PARAM_VALUE.ENABLE_COUNTERS64 } { 85 | # Procedure called to validate ENABLE_COUNTERS64 86 | return true 87 | } 88 | 89 | proc update_PARAM_VALUE.ENABLE_DIV { PARAM_VALUE.ENABLE_DIV } { 90 | # Procedure called to update ENABLE_DIV when any of the dependent parameters in the arguments change 91 | } 92 | 93 | proc validate_PARAM_VALUE.ENABLE_DIV { PARAM_VALUE.ENABLE_DIV } { 94 | # Procedure called to validate ENABLE_DIV 95 | return true 96 | } 97 | 98 | proc update_PARAM_VALUE.ENABLE_FAST_MUL { PARAM_VALUE.ENABLE_FAST_MUL } { 99 | # Procedure called to update ENABLE_FAST_MUL when any of the dependent parameters in the arguments change 100 | } 101 | 102 | proc validate_PARAM_VALUE.ENABLE_FAST_MUL { PARAM_VALUE.ENABLE_FAST_MUL } { 103 | # Procedure called to validate ENABLE_FAST_MUL 104 | return true 105 | } 106 | 107 | proc update_PARAM_VALUE.ENABLE_IRQ { PARAM_VALUE.ENABLE_IRQ } { 108 | # Procedure called to update ENABLE_IRQ when any of the dependent parameters in the arguments change 109 | } 110 | 111 | proc validate_PARAM_VALUE.ENABLE_IRQ { PARAM_VALUE.ENABLE_IRQ } { 112 | # Procedure called to validate ENABLE_IRQ 113 | return true 114 | } 115 | 116 | proc update_PARAM_VALUE.ENABLE_IRQ_QREGS { PARAM_VALUE.ENABLE_IRQ_QREGS } { 117 | # Procedure called to update ENABLE_IRQ_QREGS when any of the dependent parameters in the arguments change 118 | } 119 | 120 | proc validate_PARAM_VALUE.ENABLE_IRQ_QREGS { PARAM_VALUE.ENABLE_IRQ_QREGS } { 121 | # Procedure called to validate ENABLE_IRQ_QREGS 122 | return true 123 | } 124 | 125 | proc update_PARAM_VALUE.ENABLE_IRQ_TIMER { PARAM_VALUE.ENABLE_IRQ_TIMER } { 126 | # Procedure called to update ENABLE_IRQ_TIMER when any of the dependent parameters in the arguments change 127 | } 128 | 129 | proc validate_PARAM_VALUE.ENABLE_IRQ_TIMER { PARAM_VALUE.ENABLE_IRQ_TIMER } { 130 | # Procedure called to validate ENABLE_IRQ_TIMER 131 | return true 132 | } 133 | 134 | proc update_PARAM_VALUE.ENABLE_MUL { PARAM_VALUE.ENABLE_MUL } { 135 | # Procedure called to update ENABLE_MUL when any of the dependent parameters in the arguments change 136 | } 137 | 138 | proc validate_PARAM_VALUE.ENABLE_MUL { PARAM_VALUE.ENABLE_MUL } { 139 | # Procedure called to validate ENABLE_MUL 140 | return true 141 | } 142 | 143 | proc update_PARAM_VALUE.ENABLE_PCPI { PARAM_VALUE.ENABLE_PCPI } { 144 | # Procedure called to update ENABLE_PCPI when any of the dependent parameters in the arguments change 145 | } 146 | 147 | proc validate_PARAM_VALUE.ENABLE_PCPI { PARAM_VALUE.ENABLE_PCPI } { 148 | # Procedure called to validate ENABLE_PCPI 149 | return true 150 | } 151 | 152 | proc update_PARAM_VALUE.ENABLE_REGS_16_31 { PARAM_VALUE.ENABLE_REGS_16_31 } { 153 | # Procedure called to update ENABLE_REGS_16_31 when any of the dependent parameters in the arguments change 154 | } 155 | 156 | proc validate_PARAM_VALUE.ENABLE_REGS_16_31 { PARAM_VALUE.ENABLE_REGS_16_31 } { 157 | # Procedure called to validate ENABLE_REGS_16_31 158 | return true 159 | } 160 | 161 | proc update_PARAM_VALUE.ENABLE_REGS_DUALPORT { PARAM_VALUE.ENABLE_REGS_DUALPORT } { 162 | # Procedure called to update ENABLE_REGS_DUALPORT when any of the dependent parameters in the arguments change 163 | } 164 | 165 | proc validate_PARAM_VALUE.ENABLE_REGS_DUALPORT { PARAM_VALUE.ENABLE_REGS_DUALPORT } { 166 | # Procedure called to validate ENABLE_REGS_DUALPORT 167 | return true 168 | } 169 | 170 | proc update_PARAM_VALUE.ENABLE_TRACE { PARAM_VALUE.ENABLE_TRACE } { 171 | # Procedure called to update ENABLE_TRACE when any of the dependent parameters in the arguments change 172 | } 173 | 174 | proc validate_PARAM_VALUE.ENABLE_TRACE { PARAM_VALUE.ENABLE_TRACE } { 175 | # Procedure called to validate ENABLE_TRACE 176 | return true 177 | } 178 | 179 | proc update_PARAM_VALUE.LATCHED_IRQ { PARAM_VALUE.LATCHED_IRQ } { 180 | # Procedure called to update LATCHED_IRQ when any of the dependent parameters in the arguments change 181 | } 182 | 183 | proc validate_PARAM_VALUE.LATCHED_IRQ { PARAM_VALUE.LATCHED_IRQ } { 184 | # Procedure called to validate LATCHED_IRQ 185 | return true 186 | } 187 | 188 | proc update_PARAM_VALUE.MASKED_IRQ { PARAM_VALUE.MASKED_IRQ } { 189 | # Procedure called to update MASKED_IRQ when any of the dependent parameters in the arguments change 190 | } 191 | 192 | proc validate_PARAM_VALUE.MASKED_IRQ { PARAM_VALUE.MASKED_IRQ } { 193 | # Procedure called to validate MASKED_IRQ 194 | return true 195 | } 196 | 197 | proc update_PARAM_VALUE.PROGADDR_IRQ { PARAM_VALUE.PROGADDR_IRQ } { 198 | # Procedure called to update PROGADDR_IRQ when any of the dependent parameters in the arguments change 199 | } 200 | 201 | proc validate_PARAM_VALUE.PROGADDR_IRQ { PARAM_VALUE.PROGADDR_IRQ } { 202 | # Procedure called to validate PROGADDR_IRQ 203 | return true 204 | } 205 | 206 | proc update_PARAM_VALUE.PROGADDR_RESET { PARAM_VALUE.PROGADDR_RESET } { 207 | # Procedure called to update PROGADDR_RESET when any of the dependent parameters in the arguments change 208 | } 209 | 210 | proc validate_PARAM_VALUE.PROGADDR_RESET { PARAM_VALUE.PROGADDR_RESET } { 211 | # Procedure called to validate PROGADDR_RESET 212 | return true 213 | } 214 | 215 | proc update_PARAM_VALUE.REGS_INIT_ZERO { PARAM_VALUE.REGS_INIT_ZERO } { 216 | # Procedure called to update REGS_INIT_ZERO when any of the dependent parameters in the arguments change 217 | } 218 | 219 | proc validate_PARAM_VALUE.REGS_INIT_ZERO { PARAM_VALUE.REGS_INIT_ZERO } { 220 | # Procedure called to validate REGS_INIT_ZERO 221 | return true 222 | } 223 | 224 | proc update_PARAM_VALUE.STACKADDR { PARAM_VALUE.STACKADDR } { 225 | # Procedure called to update STACKADDR when any of the dependent parameters in the arguments change 226 | } 227 | 228 | proc validate_PARAM_VALUE.STACKADDR { PARAM_VALUE.STACKADDR } { 229 | # Procedure called to validate STACKADDR 230 | return true 231 | } 232 | 233 | proc update_PARAM_VALUE.TWO_CYCLE_ALU { PARAM_VALUE.TWO_CYCLE_ALU } { 234 | # Procedure called to update TWO_CYCLE_ALU when any of the dependent parameters in the arguments change 235 | } 236 | 237 | proc validate_PARAM_VALUE.TWO_CYCLE_ALU { PARAM_VALUE.TWO_CYCLE_ALU } { 238 | # Procedure called to validate TWO_CYCLE_ALU 239 | return true 240 | } 241 | 242 | proc update_PARAM_VALUE.TWO_CYCLE_COMPARE { PARAM_VALUE.TWO_CYCLE_COMPARE } { 243 | # Procedure called to update TWO_CYCLE_COMPARE when any of the dependent parameters in the arguments change 244 | } 245 | 246 | proc validate_PARAM_VALUE.TWO_CYCLE_COMPARE { PARAM_VALUE.TWO_CYCLE_COMPARE } { 247 | # Procedure called to validate TWO_CYCLE_COMPARE 248 | return true 249 | } 250 | 251 | proc update_PARAM_VALUE.TWO_STAGE_SHIFT { PARAM_VALUE.TWO_STAGE_SHIFT } { 252 | # Procedure called to update TWO_STAGE_SHIFT when any of the dependent parameters in the arguments change 253 | } 254 | 255 | proc validate_PARAM_VALUE.TWO_STAGE_SHIFT { PARAM_VALUE.TWO_STAGE_SHIFT } { 256 | # Procedure called to validate TWO_STAGE_SHIFT 257 | return true 258 | } 259 | 260 | 261 | proc update_MODELPARAM_VALUE.ENABLE_COUNTERS { MODELPARAM_VALUE.ENABLE_COUNTERS PARAM_VALUE.ENABLE_COUNTERS } { 262 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 263 | set_property value [get_property value ${PARAM_VALUE.ENABLE_COUNTERS}] ${MODELPARAM_VALUE.ENABLE_COUNTERS} 264 | } 265 | 266 | proc update_MODELPARAM_VALUE.ENABLE_COUNTERS64 { MODELPARAM_VALUE.ENABLE_COUNTERS64 PARAM_VALUE.ENABLE_COUNTERS64 } { 267 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 268 | set_property value [get_property value ${PARAM_VALUE.ENABLE_COUNTERS64}] ${MODELPARAM_VALUE.ENABLE_COUNTERS64} 269 | } 270 | 271 | proc update_MODELPARAM_VALUE.ENABLE_REGS_16_31 { MODELPARAM_VALUE.ENABLE_REGS_16_31 PARAM_VALUE.ENABLE_REGS_16_31 } { 272 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 273 | set_property value [get_property value ${PARAM_VALUE.ENABLE_REGS_16_31}] ${MODELPARAM_VALUE.ENABLE_REGS_16_31} 274 | } 275 | 276 | proc update_MODELPARAM_VALUE.ENABLE_REGS_DUALPORT { MODELPARAM_VALUE.ENABLE_REGS_DUALPORT PARAM_VALUE.ENABLE_REGS_DUALPORT } { 277 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 278 | set_property value [get_property value ${PARAM_VALUE.ENABLE_REGS_DUALPORT}] ${MODELPARAM_VALUE.ENABLE_REGS_DUALPORT} 279 | } 280 | 281 | proc update_MODELPARAM_VALUE.TWO_STAGE_SHIFT { MODELPARAM_VALUE.TWO_STAGE_SHIFT PARAM_VALUE.TWO_STAGE_SHIFT } { 282 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 283 | set_property value [get_property value ${PARAM_VALUE.TWO_STAGE_SHIFT}] ${MODELPARAM_VALUE.TWO_STAGE_SHIFT} 284 | } 285 | 286 | proc update_MODELPARAM_VALUE.BARREL_SHIFTER { MODELPARAM_VALUE.BARREL_SHIFTER PARAM_VALUE.BARREL_SHIFTER } { 287 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 288 | set_property value [get_property value ${PARAM_VALUE.BARREL_SHIFTER}] ${MODELPARAM_VALUE.BARREL_SHIFTER} 289 | } 290 | 291 | proc update_MODELPARAM_VALUE.TWO_CYCLE_COMPARE { MODELPARAM_VALUE.TWO_CYCLE_COMPARE PARAM_VALUE.TWO_CYCLE_COMPARE } { 292 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 293 | set_property value [get_property value ${PARAM_VALUE.TWO_CYCLE_COMPARE}] ${MODELPARAM_VALUE.TWO_CYCLE_COMPARE} 294 | } 295 | 296 | proc update_MODELPARAM_VALUE.TWO_CYCLE_ALU { MODELPARAM_VALUE.TWO_CYCLE_ALU PARAM_VALUE.TWO_CYCLE_ALU } { 297 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 298 | set_property value [get_property value ${PARAM_VALUE.TWO_CYCLE_ALU}] ${MODELPARAM_VALUE.TWO_CYCLE_ALU} 299 | } 300 | 301 | proc update_MODELPARAM_VALUE.COMPRESSED_ISA { MODELPARAM_VALUE.COMPRESSED_ISA PARAM_VALUE.COMPRESSED_ISA } { 302 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 303 | set_property value [get_property value ${PARAM_VALUE.COMPRESSED_ISA}] ${MODELPARAM_VALUE.COMPRESSED_ISA} 304 | } 305 | 306 | proc update_MODELPARAM_VALUE.CATCH_MISALIGN { MODELPARAM_VALUE.CATCH_MISALIGN PARAM_VALUE.CATCH_MISALIGN } { 307 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 308 | set_property value [get_property value ${PARAM_VALUE.CATCH_MISALIGN}] ${MODELPARAM_VALUE.CATCH_MISALIGN} 309 | } 310 | 311 | proc update_MODELPARAM_VALUE.CATCH_ILLINSN { MODELPARAM_VALUE.CATCH_ILLINSN PARAM_VALUE.CATCH_ILLINSN } { 312 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 313 | set_property value [get_property value ${PARAM_VALUE.CATCH_ILLINSN}] ${MODELPARAM_VALUE.CATCH_ILLINSN} 314 | } 315 | 316 | proc update_MODELPARAM_VALUE.ENABLE_PCPI { MODELPARAM_VALUE.ENABLE_PCPI PARAM_VALUE.ENABLE_PCPI } { 317 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 318 | set_property value [get_property value ${PARAM_VALUE.ENABLE_PCPI}] ${MODELPARAM_VALUE.ENABLE_PCPI} 319 | } 320 | 321 | proc update_MODELPARAM_VALUE.ENABLE_MUL { MODELPARAM_VALUE.ENABLE_MUL PARAM_VALUE.ENABLE_MUL } { 322 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 323 | set_property value [get_property value ${PARAM_VALUE.ENABLE_MUL}] ${MODELPARAM_VALUE.ENABLE_MUL} 324 | } 325 | 326 | proc update_MODELPARAM_VALUE.ENABLE_FAST_MUL { MODELPARAM_VALUE.ENABLE_FAST_MUL PARAM_VALUE.ENABLE_FAST_MUL } { 327 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 328 | set_property value [get_property value ${PARAM_VALUE.ENABLE_FAST_MUL}] ${MODELPARAM_VALUE.ENABLE_FAST_MUL} 329 | } 330 | 331 | proc update_MODELPARAM_VALUE.ENABLE_DIV { MODELPARAM_VALUE.ENABLE_DIV PARAM_VALUE.ENABLE_DIV } { 332 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 333 | set_property value [get_property value ${PARAM_VALUE.ENABLE_DIV}] ${MODELPARAM_VALUE.ENABLE_DIV} 334 | } 335 | 336 | proc update_MODELPARAM_VALUE.ENABLE_IRQ { MODELPARAM_VALUE.ENABLE_IRQ PARAM_VALUE.ENABLE_IRQ } { 337 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 338 | set_property value [get_property value ${PARAM_VALUE.ENABLE_IRQ}] ${MODELPARAM_VALUE.ENABLE_IRQ} 339 | } 340 | 341 | proc update_MODELPARAM_VALUE.ENABLE_IRQ_QREGS { MODELPARAM_VALUE.ENABLE_IRQ_QREGS PARAM_VALUE.ENABLE_IRQ_QREGS } { 342 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 343 | set_property value [get_property value ${PARAM_VALUE.ENABLE_IRQ_QREGS}] ${MODELPARAM_VALUE.ENABLE_IRQ_QREGS} 344 | } 345 | 346 | proc update_MODELPARAM_VALUE.ENABLE_IRQ_TIMER { MODELPARAM_VALUE.ENABLE_IRQ_TIMER PARAM_VALUE.ENABLE_IRQ_TIMER } { 347 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 348 | set_property value [get_property value ${PARAM_VALUE.ENABLE_IRQ_TIMER}] ${MODELPARAM_VALUE.ENABLE_IRQ_TIMER} 349 | } 350 | 351 | proc update_MODELPARAM_VALUE.ENABLE_TRACE { MODELPARAM_VALUE.ENABLE_TRACE PARAM_VALUE.ENABLE_TRACE } { 352 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 353 | set_property value [get_property value ${PARAM_VALUE.ENABLE_TRACE}] ${MODELPARAM_VALUE.ENABLE_TRACE} 354 | } 355 | 356 | proc update_MODELPARAM_VALUE.REGS_INIT_ZERO { MODELPARAM_VALUE.REGS_INIT_ZERO PARAM_VALUE.REGS_INIT_ZERO } { 357 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 358 | set_property value [get_property value ${PARAM_VALUE.REGS_INIT_ZERO}] ${MODELPARAM_VALUE.REGS_INIT_ZERO} 359 | } 360 | 361 | proc update_MODELPARAM_VALUE.MASKED_IRQ { MODELPARAM_VALUE.MASKED_IRQ PARAM_VALUE.MASKED_IRQ } { 362 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 363 | set_property value [get_property value ${PARAM_VALUE.MASKED_IRQ}] ${MODELPARAM_VALUE.MASKED_IRQ} 364 | } 365 | 366 | proc update_MODELPARAM_VALUE.LATCHED_IRQ { MODELPARAM_VALUE.LATCHED_IRQ PARAM_VALUE.LATCHED_IRQ } { 367 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 368 | set_property value [get_property value ${PARAM_VALUE.LATCHED_IRQ}] ${MODELPARAM_VALUE.LATCHED_IRQ} 369 | } 370 | 371 | proc update_MODELPARAM_VALUE.PROGADDR_RESET { MODELPARAM_VALUE.PROGADDR_RESET PARAM_VALUE.PROGADDR_RESET } { 372 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 373 | set_property value [get_property value ${PARAM_VALUE.PROGADDR_RESET}] ${MODELPARAM_VALUE.PROGADDR_RESET} 374 | } 375 | 376 | proc update_MODELPARAM_VALUE.PROGADDR_IRQ { MODELPARAM_VALUE.PROGADDR_IRQ PARAM_VALUE.PROGADDR_IRQ } { 377 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 378 | set_property value [get_property value ${PARAM_VALUE.PROGADDR_IRQ}] ${MODELPARAM_VALUE.PROGADDR_IRQ} 379 | } 380 | 381 | proc update_MODELPARAM_VALUE.STACKADDR { MODELPARAM_VALUE.STACKADDR PARAM_VALUE.STACKADDR } { 382 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 383 | set_property value [get_property value ${PARAM_VALUE.STACKADDR}] ${MODELPARAM_VALUE.STACKADDR} 384 | } 385 | 386 | -------------------------------------------------------------------------------- /notebooks/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/drichmond/RISC-V-On-PYNQ/9eba461cd98ace8bb36caafef2680e1fab8b7b3a/notebooks/README.md -------------------------------------------------------------------------------- /notebooks/examples/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/drichmond/RISC-V-On-PYNQ/9eba461cd98ace8bb36caafef2680e1fab8b7b3a/notebooks/examples/README.md -------------------------------------------------------------------------------- /notebooks/tutorial/0-How-To-RISC-V.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": {}, 6 | "source": [ 7 | "# How to Use a RISC-V Processor in PYNQ\n", 8 | "\n", 9 | "Welcome! This tutorial will walk you through the steps of creating a RISC-V Processor overlay. This guide has five parts:\n", 10 | "\n", 11 | "1. [Downloading Dependencies](1-Downloading-And-Configuring.ipynb)\n", 12 | "2. [Creating a FPGA Bitstream](2-Creating-A-Bitstream.ipynb)\n", 13 | "3. [Compiling the RISC-V GCC Toolchain](3-Compiling-RISC-V-GCC-Toolchain.ipynb)\n", 14 | "4. [Packaging a RISC-V Overlay](4-Packaging-An-Overlay.ipynb)\n", 15 | "\n", 16 | "At the end of this guide you will know how to:\n", 17 | "\n", 18 | "1. Package a RISC-V Processor as a Vivado IP\n", 19 | "2. Create a RISC-V Processor Bitstream in Vivado IP Integrator\n", 20 | "3. Compile the RISC-V GCC Toolchain\n", 21 | "4. Package, Install, and Load a custom PYNQ overlay\n", 22 | "5. Use an IPython Magic to Compile C/C++ or Assembly code. \n", 23 | "\n", 24 | "In summary once you have finished this guide, you can apply the same steps to any RISC-V processor implementation with standard interfaces like, BRAM, LMB, AXI4, AXI4Lite, Avalon, AHB and Wishbone." 25 | ] 26 | }, 27 | { 28 | "cell_type": "markdown", 29 | "metadata": {}, 30 | "source": [ 31 | "## Getting Started\n", 32 | "\n", 33 | "To complete this guide you will need a PYNQ board and a host computer. Both should have an internet connection, but only the host requires it.\n", 34 | "\n", 35 | "To test the internet connection on your host click on the following link to navigate to the [PYNQ Documentation Website](pynq.rtfd.io)\n", 36 | "\n", 37 | "To test the internet connection on your PYNQ board run the following cell. " 38 | ] 39 | }, 40 | { 41 | "cell_type": "code", 42 | "execution_count": null, 43 | "metadata": {}, 44 | "outputs": [], 45 | "source": [ 46 | "!ping xilinx.com -c 10" 47 | ] 48 | }, 49 | { 50 | "cell_type": "markdown", 51 | "metadata": {}, 52 | "source": [ 53 | "## A Stylistc Note:\n", 54 | "\n", 55 | "Instructions to be run on your host computer will be in `monospace font`. An example is shown below." 56 | ] 57 | }, 58 | { 59 | "cell_type": "markdown", 60 | "metadata": { 61 | "collapsed": true 62 | }, 63 | "source": [ 64 | "Run the following command in your host computer's terminal: \n", 65 | "\n", 66 | " git clone https://github.com/octocat/Spoon-Knife\n", 67 | " \n", 68 | "This will clone the tutorial git repository from GitHub to your host computer. \n", 69 | "\n", 70 | "In Windows, the same command can be run in [Cygwin](https://cygwin.com/index.html) with git installed." 71 | ] 72 | }, 73 | { 74 | "cell_type": "markdown", 75 | "metadata": {}, 76 | "source": [ 77 | "Instructions that will be run on your PYNQ board will be in Jupyter Notebook cells like in the following example. Executing the following cell will run on your PYNQ board" 78 | ] 79 | }, 80 | { 81 | "cell_type": "code", 82 | "execution_count": null, 83 | "metadata": {}, 84 | "outputs": [], 85 | "source": [ 86 | "!git clone https://github.com/octocat/Spoon-Knife /home/xilinx/Spoon-Knife" 87 | ] 88 | } 89 | ], 90 | "metadata": { 91 | "kernelspec": { 92 | "display_name": "Python 3", 93 | "language": "python", 94 | "name": "python3" 95 | }, 96 | "language_info": { 97 | "codemirror_mode": { 98 | "name": "ipython", 99 | "version": 3 100 | }, 101 | "file_extension": ".py", 102 | "mimetype": "text/x-python", 103 | "name": "python", 104 | "nbconvert_exporter": "python", 105 | "pygments_lexer": "ipython3", 106 | "version": "3.6.0" 107 | } 108 | }, 109 | "nbformat": 4, 110 | "nbformat_minor": 2 111 | } 112 | -------------------------------------------------------------------------------- /notebooks/tutorial/1-Downloading-And-Configuring.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": { 6 | "collapsed": true 7 | }, 8 | "source": [ 9 | "# Downloading Dependencies and Configuring your Environment\n", 10 | "\n", 11 | "In this step we will download tools, clone sources from GitHub, and configure your environment.Some of the steps will require downloading packages to your host computer while some will be downloaded to your PYNQ board. These will be used in the remainder of this Tutorial. \n", 12 | "\n", 13 | "As stated in the introduction, this guide demonstrates installation on a Linux host computer, but these instructions can also be followed on a Windows host computer using Cygwin. Where the Windows instructions differ, this tutorial will make every effort to highlight the difference. " 14 | ] 15 | }, 16 | { 17 | "cell_type": "markdown", 18 | "metadata": {}, 19 | "source": [ 20 | "# Host Dependencies\n", 21 | "\n", 22 | "You will need to install the following programs on your host computer:\n", 23 | "\n", 24 | " 1. Git [(Windows & Linux Tutorial)](https://www.atlassian.com/git/tutorials/install-git)\n", 25 | " 2. Xilinx Vivado WebPack 2017.4 [(Windows & Linux Tutorial - See Chapter 3)](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug973-vivado-release-notes-install-license.pdf)\n", 26 | " 3. Cygwin (Windows only, [Tutorial](http://www.mcclean-cooper.com/valentino/cygwin_install/))\n", 27 | "\n", 28 | "## Repositories\n", 29 | " \n", 30 | "Once these tools are installed you need to clone the following repositories on your host computer. These will clone the RISC-V-On-PYNQ, picorv32, and riscv-gnu-toolchain repositories. We have cloned these directories to `/home/xilinx` on our host machine. \n", 31 | "\n", 32 | "On Linux, run these commands from a terminal. On Windows you can use Cygwin (with git installed) or use the Git Bash shell.\n", 33 | "\n", 34 | "This command clones the git repository containing these notebooks, source files, and the PicoRV32 Processor to your host machine:\n", 35 | "\n", 36 | " git clone --recursive https://github.com/drichmond/RISC-V-On-PYNQ ~/PYNQ-RISC-V\n", 37 | " \n", 38 | "**Optional:** If you wish, you can also clone the RISC-V cross compiler source to your host machine. This will take substantially less time to build than on the PYNQ board, but will require moving programs from your host to the PYNQ board. \n", 39 | "\n", 40 | " git clone --recursive https://github.com/riscv/riscv-gnu-toolchain ~/riscv-gnu-toolchain" 41 | ] 42 | }, 43 | { 44 | "cell_type": "markdown", 45 | "metadata": {}, 46 | "source": [ 47 | "# PYNQ Dependencies\n", 48 | "\n", 49 | "First, check that your PYNQ board has an internet connection. Run the following cell to test the internet connection on your PYNQ board. You should see 10 responses from xilinx.com. If you do not see 10 responses then check your PYNQ Board's internet connection and try again. " 50 | ] 51 | }, 52 | { 53 | "cell_type": "code", 54 | "execution_count": null, 55 | "metadata": { 56 | "scrolled": true 57 | }, 58 | "outputs": [], 59 | "source": [ 60 | "!ping xilinx.com -c 10 " 61 | ] 62 | }, 63 | { 64 | "cell_type": "markdown", 65 | "metadata": {}, 66 | "source": [ 67 | "## PYNQ Image V2.0\n", 68 | "\n", 69 | "If you are using the PYNQ Image v2.0 SD Card you must update the repository list. \n", 70 | "\n", 71 | "Run the following cell to update your APT sources list. It will check if you are running PYNQ Image v2.0 and update your repository list if necessary. " 72 | ] 73 | }, 74 | { 75 | "cell_type": "code", 76 | "execution_count": null, 77 | "metadata": {}, 78 | "outputs": [], 79 | "source": [ 80 | "REVISION = !cat /home/xilinx/REVISION\n", 81 | "if('Release 2017_08_17 8123713' == REVISION[0]):\n", 82 | "\n", 83 | " !sed -i 's/ubuntu-ports/ubuntu/' /etc/apt/sources.list.d/multistrap-wily.list\n", 84 | " !sed -i 's/ports/old-releases/' /etc/apt/sources.list.d/multistrap-wily.list\n", 85 | "\n", 86 | " !apt update\n", 87 | "else:\n", 88 | " print(\"PYNQ is Up-To-Date!\")" 89 | ] 90 | }, 91 | { 92 | "cell_type": "markdown", 93 | "metadata": {}, 94 | "source": [ 95 | "# Downloading Dependencies\n", 96 | "\n", 97 | "Now that we have verified that the PYNQ board is connected to the internet, and we have updated the APT sources we can download and install dependencies. \n", 98 | "\n", 99 | "Run the following cell to install the dependencies using apt:" 100 | ] 101 | }, 102 | { 103 | "cell_type": "code", 104 | "execution_count": null, 105 | "metadata": {}, 106 | "outputs": [], 107 | "source": [ 108 | "!apt -y install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev git" 109 | ] 110 | }, 111 | { 112 | "cell_type": "markdown", 113 | "metadata": {}, 114 | "source": [ 115 | "## PYNQ Board Repositories\n", 116 | "\n", 117 | "You will need two source repositories on your PYNQ board. \n", 118 | "\n", 119 | "### RISC-V Gnu Toolchain\n", 120 | "\n", 121 | "First, we need the sources from RISC-V GNU Toolchain. We will build these tools in [Compiling the RISC-V GCC Toolchain and Building it on your PYNQ Board](3-Compiling-RISC-V-GCC-Toolchain).\n", 122 | "\n", 123 | "The this cell downloads the tools from the [RISC-V Tools Project](https://github.com/riscv/riscv-tools). This cell depends heavily on the speed of your internet connection and can take hours. " 124 | ] 125 | }, 126 | { 127 | "cell_type": "code", 128 | "execution_count": null, 129 | "metadata": {}, 130 | "outputs": [], 131 | "source": [ 132 | "!git clone --recursive https://github.com/riscv/riscv-gnu-toolchain /home/xilinx/riscv-gnu-toolchain" 133 | ] 134 | }, 135 | { 136 | "cell_type": "markdown", 137 | "metadata": {}, 138 | "source": [ 139 | "The clone of riscv-qemu might fail. This is fine. Verify that the rest of the repository was cloned successfully by running the following cell:" 140 | ] 141 | }, 142 | { 143 | "cell_type": "code", 144 | "execution_count": null, 145 | "metadata": {}, 146 | "outputs": [], 147 | "source": [ 148 | "!ls -lh /home/xilinx/riscv-gnu-toolchain" 149 | ] 150 | }, 151 | { 152 | "cell_type": "markdown", 153 | "metadata": {}, 154 | "source": [ 155 | "### RISC-V On PYNQ\n", 156 | "\n", 157 | "Second, you will want a clone of the RISC-V-On-PYNQ repository on your PYNQ board. \n", 158 | "\n", 159 | "Run the following cell to clone this repository:" 160 | ] 161 | }, 162 | { 163 | "cell_type": "code", 164 | "execution_count": null, 165 | "metadata": {}, 166 | "outputs": [], 167 | "source": [ 168 | "!git clone --recursive https://github.com/drichmond/RISC-V-On-PYNQ /home/xilinx/RISC-V-On-PYNQ" 169 | ] 170 | }, 171 | { 172 | "cell_type": "markdown", 173 | "metadata": { 174 | "collapsed": true 175 | }, 176 | "source": [ 177 | "That's it! You are now ready to move on to the next steps:\n", 178 | "\n", 179 | "- [Creating a FPGA Bitstream](2-Creating-A-Bitstream.ipynb)\n", 180 | "\n", 181 | "- [Compiling the RISC-V GCC Toolchain](3-Compiling-RISC-V-GCC-Toolchain.ipynb)\n", 182 | "\n", 183 | "These steps can be completed in parallel and must be finished before progressing." 184 | ] 185 | } 186 | ], 187 | "metadata": { 188 | "kernelspec": { 189 | "display_name": "Python 3", 190 | "language": "python", 191 | "name": "python3" 192 | }, 193 | "language_info": { 194 | "codemirror_mode": { 195 | "name": "ipython", 196 | "version": 3 197 | }, 198 | "file_extension": ".py", 199 | "mimetype": "text/x-python", 200 | "name": "python", 201 | "nbconvert_exporter": "python", 202 | "pygments_lexer": "ipython3", 203 | "version": "3.6.0" 204 | } 205 | }, 206 | "nbformat": 4, 207 | "nbformat_minor": 2 208 | } 209 | -------------------------------------------------------------------------------- /notebooks/tutorial/3-Compiling-RISC-V-GCC-Toolchain.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "markdown", 5 | "metadata": { 6 | "collapsed": true 7 | }, 8 | "source": [ 9 | "# Compiling the RISC-V GCC Toolchain on your PYNQ Board\n", 10 | "\n", 11 | "This notebook describes the steps to compile the RISC-V GCC Toolchain on your PYNQ Board. This depends on the steps in **[Downloading Dependencies](1-Downloading-And-Configuring.ipynb)**. You must complete the steps in that notebook before attempting this notebook.\n", 12 | "\n", 13 | "This notebook is run entirely on a PYNQ board. The cells within this notebook will take several hours to finish - so be patient. On the bright side, this notebook can (and should) be run in parallel with the host-based **[Creating a FPGA Bitstream](2-Creating-A-Bitstream.ipynb)**.\n", 14 | "\n", 15 | "These cells are based on the instructions provided in the [riscv-gnu-toolchain repository](https://github.com/riscv/riscv-gnu-toolchain)" 16 | ] 17 | }, 18 | { 19 | "cell_type": "markdown", 20 | "metadata": {}, 21 | "source": [ 22 | "# Verifying the riscv-gnu-toolchain Repository\n", 23 | "\n", 24 | "You must have the riscv-gnu-toolchain repository cloned in order for this notebook to run. The following cell checks for the existence of the riscv-gnu-toolchain git repository in the `/home/xilinx` folder on the PYNQ board.\n", 25 | "\n", 26 | "If these commands fail return to **[Downloading Dependencies and Configuring your Environment](1-Downloading-And-Configuring.ipynb)** and re-run the steps there." 27 | ] 28 | }, 29 | { 30 | "cell_type": "code", 31 | "execution_count": 1, 32 | "metadata": {}, 33 | "outputs": [ 34 | { 35 | "name": "stdout", 36 | "output_type": "stream", 37 | "text": [ 38 | "total 328K\r\n", 39 | "drwxr-xr-x 16 root root 4.0K Nov 16 21:21 build-binutils-newlib\r\n", 40 | "drwxr-xr-x 11 root root 4.0K Nov 16 22:39 build-gcc-newlib-stage1\r\n", 41 | "drwxr-xr-x 13 root root 4.0K Nov 17 05:26 build-gcc-newlib-stage2\r\n", 42 | "drwxr-xr-x 4 root root 4.0K Nov 17 01:51 build-newlib\r\n", 43 | "-rw-r--r-- 1 root root 9.3K Nov 16 20:51 config.log\r\n", 44 | "-rwxr-xr-x 1 root root 25K Nov 16 20:51 config.status\r\n", 45 | "-rwxr-xr-x 1 root root 129K Nov 16 18:46 configure\r\n", 46 | "-rw-r--r-- 1 root root 5.2K Nov 16 18:46 configure.ac\r\n", 47 | "-rw-r--r-- 1 root root 41K Nov 16 18:46 LICENSE\r\n", 48 | "drwxr-xr-x 3 root root 4.0K Nov 16 18:46 linux-headers\r\n", 49 | "-rw-r--r-- 1 root root 20K Nov 16 20:51 Makefile\r\n", 50 | "-rw-r--r-- 1 root root 20K Nov 16 18:46 Makefile.in\r\n", 51 | "-rw-r--r-- 1 root root 4.1K Nov 16 18:46 README.md\r\n", 52 | "drwxr-xr-x 2 root root 4.0K Nov 16 18:46 regression\r\n", 53 | "drwxr-xr-x 22 root root 4.0K Nov 16 19:00 riscv-binutils-gdb\r\n", 54 | "drwxr-xr-x 8 root root 4.0K Nov 16 19:00 riscv-dejagnu\r\n", 55 | "drwxr-xr-x 37 root root 4.0K Nov 16 19:58 riscv-gcc\r\n", 56 | "drwxr-xr-x 69 root root 4.0K Nov 16 20:09 riscv-glibc\r\n", 57 | "drwxr-xr-x 9 root root 4.0K Nov 16 20:11 riscv-newlib\r\n", 58 | "drwxr-xr-x 3 root root 4.0K Nov 16 18:46 scripts\r\n", 59 | "drwxr-xr-x 2 root root 4.0K Nov 17 05:56 stamps\r\n", 60 | "drwxr-xr-x 7 root root 4.0K Nov 16 18:46 test\r\n" 61 | ] 62 | } 63 | ], 64 | "source": [ 65 | "!ls -lh /home/xilinx/riscv-gnu-toolchain" 66 | ] 67 | }, 68 | { 69 | "cell_type": "markdown", 70 | "metadata": {}, 71 | "source": [ 72 | "# Building the RISC-V Tools\n", 73 | "\n", 74 | "Now that we've met all our dependencies, we need to compile and install the tools. In the next two cells we build, and then install the tools. \n", 75 | "\n", 76 | "Once the tools have been compiled you will need to modify the Linux environment PATH variable and then reboot your board in order for the change to take effect. Once you can, we verify the tools and complete the notebook.\n", 77 | "\n", 78 | "If you want to monitor the progress of your compilation you can read the config.log and build.log file that is generated during. You can read the logs by opening [cnfig.log](cnfig.log) and [build.log](build.log) by clicking the links or by opening them in the [Jupyter Browser](.). Update the logs by running refresh periodically.\n", 79 | "\n", 80 | "Alternatively, you can also view the logs by opening a terminal by clicking [here](../../../terminals/42) or by navigating to (**Jupyter Home** > **New** > **Terminal**) and then running the commands: \n", 81 | " \n", 82 | " less /home/xilinx/jupyter_notebooks/RISC-V-Tutorial/config.log\n", 83 | "\n", 84 | "or\n", 85 | "\n", 86 | " less /home/xilinx/jupyter_notebooks/RISC-V-Tutorial/build.log" 87 | ] 88 | }, 89 | { 90 | "cell_type": "code", 91 | "execution_count": 2, 92 | "metadata": {}, 93 | "outputs": [ 94 | { 95 | "name": "stdout", 96 | "output_type": "stream", 97 | "text": [ 98 | "Configuration successful!\n" 99 | ] 100 | } 101 | ], 102 | "source": [ 103 | "from subprocess import run, PIPE, Popen\n", 104 | "\n", 105 | "cnfig_log = open(\"cnfig.log\",\"w\")\n", 106 | "cnfig_err = open(\"cnfig.err\",\"w\")\n", 107 | "\n", 108 | "ret = run([\"./configure\", \"--prefix=/opt/riscv32im\", \"--with-arch=rv32im\"], \n", 109 | " cwd=\"/home/xilinx/riscv-gnu-toolchain/\",\n", 110 | " stdout=cnfig_log, stderr=cnfig_err)\n", 111 | "cnfig_log.close()\n", 112 | "cnfig_err.close()\n", 113 | "\n", 114 | "if(ret.returncode != 0):\n", 115 | " print(\"There was an error while configuring the RISCV Toolchain. See the config.err and config.log file\")\n", 116 | "else:\n", 117 | " print(\"Configuration successful!\")" 118 | ] 119 | }, 120 | { 121 | "cell_type": "code", 122 | "execution_count": 2, 123 | "metadata": {}, 124 | "outputs": [ 125 | { 126 | "name": "stdout", 127 | "output_type": "stream", 128 | "text": [ 129 | "Compile successful!\n" 130 | ] 131 | } 132 | ], 133 | "source": [ 134 | "build_log = open(\"build.log\",\"w\")\n", 135 | "build_err = open(\"build.err\",\"w\") \n", 136 | "ret = run([\"make\"], \n", 137 | " cwd=\"/home/xilinx/riscv-gnu-toolchain/\",\n", 138 | " stdout=build_log, stderr=build_err)\n", 139 | "build_log.close()\n", 140 | "build_err.close()\n", 141 | "\n", 142 | "if(ret.returncode != 0):\n", 143 | " print(\"There was an error while compiling the RISCV Toolchain. See the build.err and build.log file\")\n", 144 | "else:\n", 145 | " print(\"Compile successful!\")" 146 | ] 147 | }, 148 | { 149 | "cell_type": "markdown", 150 | "metadata": {}, 151 | "source": [ 152 | "# Modifying PATH\n", 153 | "\n", 154 | "Now that the tools have been installed we need to add them to the PATH variable so that they can be run from Jupyter Notebooks and the command line. To do this we will modify the `/etc/environment` file using the cell below.\n", 155 | "\n", 156 | "If the PATH already contains the folder with the RISC-V GCC binaries this command will succeed but make no changes.\n" 157 | ] 158 | }, 159 | { 160 | "cell_type": "code", 161 | "execution_count": 3, 162 | "metadata": {}, 163 | "outputs": [ 164 | { 165 | "name": "stdout", 166 | "output_type": "stream", 167 | "text": [ 168 | "Updating /etc/environment file... done\n" 169 | ] 170 | } 171 | ], 172 | "source": [ 173 | "import os\n", 174 | "path = os.environ['PATH'].split()\n", 175 | "riscv_path = '/opt/riscv32im/bin'\n", 176 | "if(riscv_path not in path):\n", 177 | " print('Updating /etc/environment file... ',end=\"\")\n", 178 | " !sed -i 's/PATH=\\\"\\(.*\\)\\\"/PATH=\\\"\\/opt\\/riscv32im\\/bin:\\1\\\"/' /etc/environment\n", 179 | " print('done')\n", 180 | "else:\n", 181 | " print(\"/etc/environment file already updated\")" 182 | ] 183 | }, 184 | { 185 | "cell_type": "markdown", 186 | "metadata": {}, 187 | "source": [ 188 | "# Reboot...\n", 189 | "\n", 190 | "Reboot your board once the cell above has run. When your board finishes rebooting refresh this page and proceed to the next cell." 191 | ] 192 | }, 193 | { 194 | "cell_type": "code", 195 | "execution_count": 4, 196 | "metadata": { 197 | "collapsed": true 198 | }, 199 | "outputs": [], 200 | "source": [ 201 | "!shutdown -r now" 202 | ] 203 | }, 204 | { 205 | "cell_type": "markdown", 206 | "metadata": {}, 207 | "source": [ 208 | "# Verify Installation\n", 209 | "\n", 210 | "\n", 211 | "The following cell verifies that the RISC-V Toolchain has been successfully installed. If you see an error message, make sure that your toolchain compiliation completed succesffully.\n" 212 | ] 213 | }, 214 | { 215 | "cell_type": "code", 216 | "execution_count": 1, 217 | "metadata": {}, 218 | "outputs": [ 219 | { 220 | "name": "stdout", 221 | "output_type": "stream", 222 | "text": [ 223 | "riscv32-unknown-elf-gcc (GCC) 7.1.1 20170509\r\n", 224 | "Copyright (C) 2017 Free Software Foundation, Inc.\r\n", 225 | "This is free software; see the source for copying conditions. There is NO\r\n", 226 | "warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\r\n", 227 | "\r\n" 228 | ] 229 | } 230 | ], 231 | "source": [ 232 | "!riscv32-unknown-elf-gcc --version" 233 | ] 234 | } 235 | ], 236 | "metadata": { 237 | "kernelspec": { 238 | "display_name": "Python 3", 239 | "language": "python", 240 | "name": "python3" 241 | }, 242 | "language_info": { 243 | "codemirror_mode": { 244 | "name": "ipython", 245 | "version": 3 246 | }, 247 | "file_extension": ".py", 248 | "mimetype": "text/x-python", 249 | "name": "python", 250 | "nbconvert_exporter": "python", 251 | "pygments_lexer": "ipython3", 252 | "version": "3.6.0" 253 | } 254 | }, 255 | "nbformat": 4, 256 | "nbformat_minor": 2 257 | } 258 | -------------------------------------------------------------------------------- /notebooks/tutorial/pictures/Edit_interface.PNG: -------------------------------------------------------------------------------- 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conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | import os, inspect, pynq 36 | from .magic.Magic import Magic 37 | 38 | __author__ = "Dustin Richmond" 39 | __copyright__ = "Copyright 2018, The Regents of the University of California" 40 | 41 | class Overlay(pynq.Overlay): 42 | """The Overlay class wraps the pynq.Overlay class with an updated 43 | __init__ method. The new __init__ method modifies the PYNQ Overlay 44 | Search Path to include the folder of the class definition. 45 | 46 | """ 47 | def __get_path(self): 48 | """Get the directory path of this file, or the directory path of the 49 | class that inherits from this class. 50 | 51 | """ 52 | # Get file path of the current class (i.e. /opt/python3.6/<...>/stream.py) 53 | file_path = os.path.abspath(inspect.getfile(inspect.getmodule(self))) 54 | # Get directory path of the current class (i.e. /opt/python3.6/<...>/stream/) 55 | return os.path.dirname(file_path) 56 | 57 | def __init__(self, bitfile, **kwargs): 58 | """Return a new Overlay object, with an amended search path. 59 | 60 | The following lines enable a PYNQ-Like API for Overlays. For 61 | example, without these lines you cannot call 62 | streamOverlay('stream.bit') if stream.bit is not in the PYNQ 63 | package. because stream.bit is not on the bitstream search 64 | path. 65 | 66 | This class fixes that by searching the location of subclass 67 | definition if an absolute path is not provided. 68 | 69 | Parameters 70 | ---------- 71 | bitfile : str 72 | The bitstream name or absolute path as a string. 73 | download : boolean or None 74 | Whether the overlay should be downloaded. If None then the 75 | overlay will be downloaded if it isn't already loaded. 76 | 77 | Note 78 | ---- 79 | This class requires a Vivado '.tcl' file to be next to bitstream file 80 | with same name (e.g. base.bit and base.tcl). 81 | 82 | """ 83 | if(not os.path.isabs(bitfile)): 84 | bitfile = os.path.join(self.__get_path(), bitfile) 85 | super().__init__(bitfile, **kwargs) 86 | 87 | -------------------------------------------------------------------------------- /riscvonpynq/PYNQ-Z1.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | ############################################################################### 35 | 36 | ##Buttons 37 | set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {pb_i[0]}] 38 | set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {pb_i[1]}] 39 | set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {pb_i[2]}] 40 | set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports {pb_i[3]}] 41 | 42 | ##LEDs 43 | set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports {led_o[0]}] 44 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {led_o[1]}] 45 | set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {led_o[2]}] 46 | set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports {led_o[3]}] 47 | 48 | ##Arduino shield digital io ar_shield 49 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[0]}] 50 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[1]}] 51 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[2]}] 52 | set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[3]}] 53 | set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[4]}] 54 | 55 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[5]}] 56 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[6]}] 57 | set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[7]}] 58 | set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[8]}] 59 | set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[9]}] 60 | 61 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[10]}] 62 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[11]}] 63 | set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[12]}] 64 | set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[13]}] 65 | set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[14]}] 66 | 67 | set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[15]}] 68 | set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[16]}] 69 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[17]}] 70 | set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[18]}] 71 | set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports {arduino_gpio_tri_io[19]}] 72 | set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports arduino_iic_scl_io] 73 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports arduino_iic_sda_io] 74 | set_property PULLUP true [get_ports arduino_iic_scl_io] 75 | set_property PULLUP true [get_ports arduino_iic_sda_io] 76 | set_property PULLUP true [get_ports {arduino_gpio_tri_io[*]}] 77 | 78 | ##pmod Header JA 79 | set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[1]}] 80 | set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[0]}] 81 | set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[3]}] 82 | set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[2]}] 83 | set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[5]}] 84 | set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[4]}] 85 | set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[7]}] 86 | set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports {pmodJA_gpio_tri_io[6]}] 87 | set_property PULLUP true [get_ports {pmodJA_gpio_tri_io[2]}] 88 | set_property PULLUP true [get_ports {pmodJA_gpio_tri_io[3]}] 89 | set_property PULLUP true [get_ports {pmodJA_gpio_tri_io[6]}] 90 | set_property PULLUP true [get_ports {pmodJA_gpio_tri_io[7]}] 91 | 92 | ##pmod Header JB 93 | set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[1]}] 94 | set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[0]}] 95 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[3]}] 96 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[2]}] 97 | set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[5]}] 98 | set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[4]}] 99 | set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[7]}] 100 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {pmodJB_gpio_tri_io[6]}] 101 | set_property PULLUP true [get_ports {pmodJB_gpio_tri_io[2]}] 102 | set_property PULLUP true [get_ports {pmodJB_gpio_tri_io[3]}] 103 | set_property PULLUP true [get_ports {pmodJB_gpio_tri_io[6]}] 104 | set_property PULLUP true [get_ports {pmodJB_gpio_tri_io[7]}] 105 | -------------------------------------------------------------------------------- /riscvonpynq/Processor.py: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------- 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | import pynq, os, enum, numpy as np, time 36 | from pynq import Xlnk 37 | 38 | __author__ = "Dustin Richmond" 39 | __copyright__ = "Copyright 2018, The Regents of the University of California" 40 | 41 | class Processor(pynq.DefaultHierarchy): 42 | """Parent Hierarchy driver for RISC-V Processors 43 | 44 | Facilitates loading user programs on to RISC-V Processors. 45 | 46 | Note 47 | ---- 48 | In order to be recognized as a RISC-V Processor hierarchy, three 49 | conditions must be met: First, there must be a PS-Memory-Mapped 50 | Block RAM Controller where the name matches the variable 51 | _bram. Second, the hierarchy name (fullpath) must equal the 52 | variable _name. Finally, there must be a GPIO port with the name 53 | _reset_name. 54 | 55 | Subclasses of this module are responsible for setting _name (The 56 | name of the Hierarchy), _bits (Processor bit-width), _proc 57 | (Processor Type Name) 58 | 59 | """ 60 | _reset_name = 'riscv_resetn' 61 | _bram = 'psBramController' 62 | _name = None 63 | _bits = None 64 | _proc = None 65 | 66 | @classmethod 67 | def checkhierarchy(cls, description): 68 | return ((cls._bram in description['ip'].keys()) and 69 | (cls._name == description['fullpath']) and 70 | (cls._reset_name in description['gpio'])) 71 | 72 | def __init__(self, build_path, reset_value, description, *args): 73 | """Return a new Processor object. 74 | 75 | Parameters 76 | ---------- 77 | build_path : str 78 | Path to the RISC-V build files for this processor 79 | 80 | reset_value : int 81 | Value to be written (0 or 1) to the GPIO pin to reset the 82 | RISC-V procesor. 83 | 84 | description : dict 85 | Dictionary describing this processor. 86 | 87 | """ 88 | super().__init__(description, *args) 89 | 90 | if(reset_value not in {1, 0}): 91 | raise ValueError(f'reset_value must be 0 or 1, not {reset_value}') 92 | 93 | self.__reset_value = reset_value 94 | self.__nreset_value = int(not(reset_value)) 95 | 96 | self.__resetPin = self.__getattr__(self._reset_name) 97 | self.__reset_s = None 98 | self._reset() 99 | 100 | self._mem = self.__getattr__(self._bram) 101 | self._stkidx = self._mem.mmio.length 102 | self._memstr = description['ip'][self._bram]['fullpath'] 103 | self.__clear_argptrs() 104 | 105 | self.__loaded = False 106 | self.__build_path = build_path 107 | 108 | @property 109 | def name(self): 110 | """ Return the name of the RISC-V Processor Hierarchy""" 111 | return self._name 112 | 113 | @property 114 | def stkptr(self): 115 | """ Return the memory size in Bytes of the desired stack pointer""" 116 | return self._stkidx 117 | 118 | @property 119 | def build_path(self): 120 | """ Return the path to the build directory for this RISC-V Processor""" 121 | return self.__build_path 122 | 123 | @property 124 | def proc(self): 125 | """Return the name of the RISC-V Processor IP RISC-V Processor 126 | Hierarchy""" 127 | return self._proc 128 | 129 | @property 130 | def bits(self): 131 | """Return the bit width of the RISC-V Processor IP""" 132 | return self._bits 133 | 134 | def _reset(self): 135 | """Put the RISC-V Processor into the reset state""" 136 | self.__reset_s = self.__reset_value 137 | self.__resetPin.write(self.__reset_value) 138 | 139 | def _nreset(self): 140 | """Remove the RISC-V Processor from the reset state 141 | 142 | Note 143 | ---- 144 | This method will raise a RuntimeError if the processor is not 145 | in the reset state; this means the processor is not in the 146 | reset state or its state is undefined. 147 | 148 | """ 149 | 150 | if(self.__reset_s != self.__reset_value): 151 | raise RuntimeError("Processor not in reset state!") 152 | else: 153 | self.__reset_s = self.__nreset_value 154 | self.__resetPin.write(self.__nreset_value) 155 | 156 | def _validate(self, *args): 157 | """Validate that all arguments are numpy types. 158 | 159 | Note 160 | ---- 161 | This method will raise a TypeError if an argument is not an 162 | instance of np.ndarray, or np.generic. 163 | 164 | """ 165 | for a in args: 166 | if(not isinstance(a, (np.ndarray, np.generic))): 167 | raise TypeError(f'Argument {type(a)} not a numpy type') 168 | 169 | def __clear_argptrs(self): 170 | """Reset all of the pointers used to pass arguments to a RISC-V 171 | Processor 172 | 173 | Note 174 | ---- 175 | 176 | argv_buf : np.ndarray 177 | A buffer for a list of pointers to arguments that is used 178 | for argv in the call to the main method 179 | 180 | argv_ptr : int 181 | Physical address of the argv buffer in the RISC-V memory 182 | space. 183 | 184 | arg_bufs : list 185 | List of np.ndarrays with argument data 186 | 187 | arg_ptrs : list 188 | List of pointers to each buffer in arg_bufs from the 189 | perspective of the RISC-V Processor memory space. 190 | 191 | """ 192 | self.__argv_buf = None 193 | self.__argv_ptr = None 194 | self.__arg_bufs = None 195 | self.__arg_ptrs = None 196 | 197 | def run(self, prog, *args): 198 | """Run a given program on the RISC-V Processor, and block until the 199 | program terminates. 200 | 201 | Parameters 202 | ---------- 203 | prog : riscvonpynq.Program 204 | A Program class from the riscvonpynq library that wraps a 205 | user program 206 | 207 | args : tuple 208 | Arguments to pass to the main method of the program 209 | 210 | """ 211 | self.launch(prog, *args) 212 | self.irq.wait() 213 | return self.land() 214 | 215 | def launch(self, prog, *args): 216 | """Launch a given program on the RISC-V Processor, and return while 217 | the program executes. 218 | 219 | Parameters 220 | ---------- 221 | prog : riscvonpynq.Program 222 | A Program class from the riscvonpynq library that wraps a 223 | user program 224 | 225 | args : tuple 226 | Arguments to pass to the main method of the program 227 | 228 | """ 229 | path = prog.build(self) 230 | self._load(path, *args) 231 | self._nreset() 232 | 233 | def _load(self, bin_path, *args): 234 | """Load a program into the memory space of the RISC-V Processor and 235 | load its arguments 236 | 237 | Parameters 238 | ---------- 239 | bin_path : str 240 | Path of the binary file to be loaded 241 | 242 | args : tuple 243 | Arguments to pass to the main method of the program 244 | 245 | """ 246 | if(self.__loaded): 247 | raise RuntimeError('Processor already loaded!') 248 | 249 | pynq.PL.load_ip_data(self._memstr, bin_path) 250 | 251 | binname = np.fromstring(bin_path + '\0', np.int8) 252 | self.__args = (binname, *args) 253 | bs = self._alloc_args(self.__args) 254 | 255 | self.__argv_buf = bs[0] 256 | self.__argv_ptr = bs[1] 257 | self.__arg_bufs = bs[2] 258 | self.__arg_ptrs = bs[3] 259 | 260 | argc = len(self.__arg_bufs) 261 | argv = self.__argv_ptr 262 | self._mem.write(self._stkidx - 4, argc) 263 | try: 264 | self._mem.write(self._stkidx - 8, argv) 265 | except ValueError: 266 | self._mem.write(self._stkidx - 8, int(argv)) 267 | self.__loaded = True 268 | 269 | def land(self): 270 | """Terminate execution on a RISC-V Processor, unload the program and 271 | arguments, and return the program's return value (if it terminated). 272 | 273 | Note 274 | ---- 275 | Any modified data in the program argument buffers will be 276 | copied back to the original buffer (if applicable) by _unload() 277 | 278 | """ 279 | self._reset() 280 | self._unload() 281 | return self._retval 282 | 283 | def _unload(self): 284 | """Unload a program from a RISC-V Processor: Copy any modified 285 | argument data back to the processor memory space and 286 | deallocate any buffers. 287 | 288 | """ 289 | if(not self.__loaded): 290 | raise RuntimeError('Processor not loaded!') 291 | self._copyout_args(self.__arg_bufs, self.__args) 292 | self._dealloc_args(self.__arg_bufs, self.__args, self.__argv_buf) 293 | self.__clear_argptrs() 294 | self.__loaded = False 295 | 296 | def _copyout_args(self, arg_bufs, args): 297 | """Copy argument data back to the processor memory space 298 | 299 | """ 300 | self._validate(*args) 301 | for (dest, src) in zip(args, arg_bufs): 302 | if isinstance(dest, pynq.xlnk.ContiguousArray): 303 | pass 304 | elif(isinstance(dest, np.ndarray)): 305 | np.copyto(dest, src) 306 | else: 307 | dest = src 308 | 309 | @property 310 | def _retval(self): 311 | """Get the return value of a program from the RISC-V Processor's 312 | stack. 313 | 314 | """ 315 | return np.int32(np.uint32(self._mem.read(self._stkidx - 4))) 316 | 317 | class MixedProcessor(Processor): 318 | """Subclass Hierarchy driver for RISC-V Processors with mixed DDR/BRAM 319 | memory spaces 320 | 321 | Facilitates loading user programs on to RISC-V Processors. 322 | 323 | """ 324 | def __init__(self, build_path, reset_value, description, *args): 325 | """Return a new MixedProcessor object. 326 | 327 | Parameters 328 | ---------- 329 | build_path : str 330 | Path to the RISC-V build files for this processor 331 | 332 | reset_value : int 333 | Value to be written (0 or 1) to the GPIO pin to reset the 334 | RISC-V procesor. 335 | 336 | description : dict 337 | Dictionary describing this processor. 338 | 339 | """ 340 | super().__init__(build_path, reset_value, description, *args) 341 | self.__xlnk = Xlnk() 342 | 343 | def _dealloc_args(self, arg_bufs, args, argv_buf): 344 | """Dealloc any CMA Arrays allocated by this class, but do not 345 | deallocate CMA Arrays allocated by the user 346 | 347 | Parameters 348 | ---------- 349 | arg_bufs : list 350 | List of np.ndarrays with argument data in the RISC-V 351 | Processor memory space 352 | 353 | args : tuple 354 | Tuple of np.ndarrays with argument data in the PS memory 355 | space. 356 | 357 | argv_buf : pynq.xlnk.ContiguousArray 358 | Buffer containing pointers to each buffer in arg_bufs 359 | 360 | Note 361 | ---- 362 | If a buffer in args is an instance of 363 | pynq.xlnk.ContiguousArray this means it was allocated by the 364 | user and will not be deallocated 365 | 366 | """ 367 | self._validate(*args) 368 | [ None if isinstance(a, pynq.xlnk.ContiguousArray) 369 | else cma.freebuffer() 370 | for (cma, a) in zip(arg_bufs, args) ] 371 | argv_buf.freebuffer() 372 | 373 | def _alloc_args(self, args): 374 | """Allocate CMA Arrays to hold any user-provided arguments. 375 | 376 | Parameters 377 | ---------- 378 | args : tuple 379 | Tuple of np.ndarrays with argument data in the PS memory 380 | space. 381 | 382 | Note 383 | ---- 384 | If a buffer in args is an instance of 385 | pynq.xlnk.ContiguousArray this means it was allocated by the 386 | user and will not be allocated/copied 387 | 388 | """ 389 | self._validate(*args) 390 | arg_bufs = [a if isinstance(a, pynq.xlnk.ContiguousArray) 391 | else (self.__xlnk.cma_array(1, a.dtype) if isinstance(a, np.generic) 392 | else self.__xlnk.cma_array(a.shape, a.dtype)) 393 | for a in args] 394 | [None if isinstance(src, pynq.xlnk.ContiguousArray) 395 | else np.copyto(dest, src) 396 | for (dest, src) in zip(arg_bufs, args)] 397 | argv_buf = self.__xlnk.cma_array(len(args), np.uint32) 398 | argv_ptr = self.__xlnk.cma_get_phy_addr(argv_buf.pointer) 399 | arg_ptrs = [self.__xlnk.cma_get_phy_addr(pya.pointer) for pya in arg_bufs] 400 | argv_buf[:] = arg_ptrs 401 | return (argv_buf, argv_ptr, arg_bufs, arg_ptrs) 402 | 403 | class BramProcessor(Processor): 404 | """Subclass Hierarchy driver for RISC-V Processors with mixed DDR/BRAM 405 | memory spaces 406 | 407 | Facilitates loading user programs on to RISC-V Processors. 408 | 409 | """ 410 | def __init__(self, build_path, reset_value, description, *args): 411 | """Return a new BramProcessor object. 412 | 413 | Parameters 414 | ---------- 415 | build_path : str 416 | Path to the RISC-V build files for this processor 417 | 418 | reset_value : int 419 | Value to be written (0 or 1) to the GPIO pin to reset the 420 | RISC-V procesor. 421 | 422 | description : dict 423 | Dictionary describing this processor. 424 | 425 | Note 426 | ---- 427 | Since the Processor isn't connected to DDR we divide the BRAM 428 | memory in half, and use the "Upper" half for arguments 429 | (see __argptr and _stkidx) 430 | 431 | """ 432 | super().__init__(build_path, reset_value, description, *args) 433 | self._stkidx = np.uint32(self._mem.mmio.length / 2 ) 434 | self.__argptr = np.uint32(self._mem.mmio.array.nbytes / 2) 435 | 436 | def _dealloc_args(self, *args): 437 | """Dealloc any Arrays allocated by this class 438 | 439 | Note 440 | ---- 441 | Since the BRAM is contiguous, and allocation is tracked by 442 | __argptr, we simply reset __argptr 443 | 444 | """ 445 | self.__argptr = np.uint32(self._mem.mmio.array.nbytes / 2) 446 | 447 | def _alloc_buf(self, c, ty): 448 | """Allocate a buffer in the RISC-V Processor memory space 449 | 450 | Parameters 451 | ---------- 452 | c : int 453 | Number of elements (or count) to allocate in buffer 454 | 455 | ty : type 456 | Underlying type to allocate for the buffer. 457 | 458 | """ 459 | mem = self._mem.mmio.array 460 | ptr = np.uint32(self.__argptr) 461 | buf = np.frombuffer(mem, count = c, dtype=ty, offset = ptr) 462 | l = np.uint32((buf.itemsize * c + mem.itemsize - 1) / mem.itemsize)*mem.itemsize 463 | self.__argptr += np.uint32(l) 464 | return (ptr, buf) 465 | 466 | def _alloc_args(self, args): 467 | """Allocate space in the BRAMN to hold any user-provided arguments. 468 | 469 | Parameters 470 | ---------- 471 | args : tuple 472 | Tuple of np.ndarrays with argument data in the PS memory 473 | space. 474 | 475 | """ 476 | self._validate(*args) 477 | arg_ptrs, arg_bufs = zip(*[ self._alloc_buf(arg.size, arg.dtype) 478 | for arg in args ]) 479 | argv_ptr, argv_buf = self._alloc_buf(len(args), np.uint32) 480 | [ np.copyto(dest, src) for (dest, src) in zip(arg_bufs, args) ] 481 | argv_buf[:] = arg_ptrs 482 | return (argv_buf, argv_ptr, arg_bufs, arg_ptrs) 483 | 484 | class LmbProcessor(BramProcessor): 485 | """Subclass Hierarchy driver for RISC-V Processors with mixed BRAM 486 | memory spaces 487 | 488 | Facilitates loading user programs on to RISC-V Processors. 489 | 490 | """ 491 | pass 492 | -------------------------------------------------------------------------------- /riscvonpynq/Program.py: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------- 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | import os, enum, tempfile, time, shutil 36 | from subprocess import run, PIPE 37 | 38 | class Lang(enum.Enum): 39 | """An Enum for tracking supported programming languages""" 40 | 41 | C = 1 42 | CPP = 2 43 | ASM = 3 44 | 45 | class Program: 46 | """Representation of a RISC-V program. 47 | 48 | Attributes 49 | ---------- 50 | name: str 51 | Name of this program, used to derive the bin name, and source 52 | file name. 53 | 54 | """ 55 | 56 | def __init__(self, path, name, lang): 57 | """Return a new Program object 58 | 59 | Parameters 60 | ---------- 61 | path: str 62 | Path to the directory containing the body of the program 63 | 64 | name: str 65 | Filename of the program to be compiled (sans extension) 66 | 67 | lang: Lang 68 | Enum representing the source language 69 | """ 70 | 71 | if not os.path.isdir(path): 72 | raise IOError(f"File {path} not found!") 73 | self.__path = path 74 | if lang == Lang.C: 75 | src_name = f'{name}.c' 76 | elif lang == Lang.ASM: 77 | src_name = f'{name}.S' 78 | elif lang == Lang.CPP: 79 | src_name = f'{name}.cpp' 80 | else: 81 | raise RuntimeError(f'Must specify language: {[l for l in Lang]}') 82 | src_file = os.path.join(path, src_name) 83 | if(not os.path.isfile(src_file)): 84 | raise RuntimeError(f'File {src_file} could not be found') 85 | self.__bin_name = f'{name}.bin' 86 | self.__src_name = src_name 87 | self.__name = name 88 | 89 | self.__compiled = False 90 | 91 | @property 92 | def name(self): 93 | return self.__name 94 | 95 | def __compile_bin(self, proc): 96 | """Create a compile bin file with the RISC-V program 97 | 98 | Parameters 99 | ---------- 100 | path: str 101 | Path to the directory 102 | 103 | Note 104 | ---- 105 | If you want to sneak in extra INCLUDE or CFLAGS directives to 106 | the makefile, this is the place to do it. Just define them as 107 | STKPTR is defined below. 108 | 109 | """ 110 | bin_path = os.path.join(self.__path, self.__bin_name) 111 | make_args = ['make', "-C", proc.build_path, bin_path, 112 | f'STKPTR={proc.stkptr}'] 113 | result = run(make_args, stdout=PIPE, stderr=PIPE) 114 | if result.returncode: 115 | raise RuntimeError(result.stderr.decode()) 116 | 117 | def build(self, proc): 118 | """Compile this Program into a bin file. 119 | 120 | Parameters 121 | ---------- 122 | proc: riscvonpynq.Processor 123 | A processor object to compile this program for 124 | 125 | Returns 126 | ------- 127 | path : str 128 | Path of the compiled binary 129 | 130 | """ 131 | self.__compile_bin(proc) 132 | self.__compiled = True 133 | return os.path.join(self.__path, self.__bin_name) 134 | -------------------------------------------------------------------------------- /riscvonpynq/README.md: -------------------------------------------------------------------------------- 1 | # RISC-V.complete 2 | 3 | This folder contains the verified output files that should be generated when you 4 | follow the instructions in the How-To-RISC-V tutorial. You can install the 5 | tutorial on your PYNQ board by following the instructions in the parent 6 | directory. 7 | 8 | It contains the following files and folders: 9 | 10 | - README.md: This file. 11 | 12 | - vivado: A folder containing the Vivado source and constraint files for 13 | implementing the tutorial on the PYNQ-Z1 board. 14 | 15 | - ip: A folder containing a custom interface definition for PCPI and the 16 | picorv32 RISC-V processor IP for Vivado IP Integrator 17 | 18 | - ip/picorv32: A Vivado IP block encapuslating the picorv32 RISC-V processor. 19 | 20 | - riscv.tcl: A complete tcl for generating the riscv.bit file with a picorv32 21 | RISC-V processor instantiated, configured, and connected.. The script creates 22 | a Vivado 2017.1 project titled **riscv** and instantiates a Zynq 7000 PS with 23 | the correct settings for the PYNQ-Z1 board. 24 | 25 | - notebooks: A placeholder for notebooks. This file contains a RISC-V makefile, 26 | Hex-Converter script, and a Linker script. It should be moved onto your PYNQ 27 | board as described in the tutorial. 28 | 29 | - riscv.bit: A FPGA bit file with the picorv32 RISC-V processor instantiated, 30 | configured, and connected. 31 | 32 | 33 | -------------------------------------------------------------------------------- /riscvonpynq/__init__.py: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------- 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | from . import picorv32 36 | from . import magic 37 | from . import Program 38 | from . import Overlay 39 | from . import Processor 40 | -------------------------------------------------------------------------------- /riscvonpynq/build.mk: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------- 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | TARGETS=sweep synth single 36 | all: single 37 | 38 | clean: 39 | $(foreach IP,$(IPS), PART=$(PART) $(MAKE) -C $(IP_PATH)/$(IP) clean;) 40 | rm -rf $(DESIGN) *.jou *.log 41 | 42 | ip: 43 | $(foreach IP,$(IPS), PART=$(PART) $(MAKE) -C $(IP_PATH)/$(IP);) 44 | 45 | .PHONY: $(DESIGN) 46 | 47 | $(TARGETS): $(DESIGN) ip $(BUILD_PATH)/$(BOARD).xdc $(DESIGN).tcl 48 | vivado -mode batch -source $(BUILD_PATH)/build.tcl -tclargs $(DESIGN) \ 49 | $@ $(PART) $(BOARD) $(IP_PATH) 50 | cp ./$(DESIGN)/$(DESIGN).srcs/sources_1/bd/$(DESIGN)/hw_handoff/$(DESIGN).hwh $(DESIGN).hwh 51 | 52 | results: 53 | grep Slack vivado.log > sweep.log 54 | vivado -mode batch $(DESIGN)/$(DESIGN).xpr -source $(BUILD_PATH)/resources.tcl -tclargs $(DESIGN) 55 | -------------------------------------------------------------------------------- /riscvonpynq/build.tcl: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------- 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | 36 | # This file is a script for building Overlay Designs in various 37 | # ways. It can be used to synthesize a design (run_type = synth), 38 | # binary search to find a maximum frequency (run_type = sweep), or run 39 | # a single compilation (run_type) = single. It can handle multiple 40 | # boards, parts. It also handles IP directories. 41 | # The arguments are as follows: 42 | # 1. Name of the Overlay without the .tcl extension 43 | # 2. Run type (synth, single, or sweep) 44 | # 3. Xilinx Part (e.g. xc7z020clg400-1) 45 | # 4. Board Name (e.g PYNQ-Z1) 46 | # 5. IP Directories (list of paths). 47 | set argc [llength $argv] 48 | set run_type "single" 49 | set target "" 50 | set part "" 51 | set board "" 52 | set board_dir "../../" 53 | set ip_dirs "" 54 | if { $argc != 0 } { 55 | if { $argc <= 4 } { 56 | puts "" 57 | set errmsg "Expected at least three arguments: Name of Overlay \ 58 | (e.g. riscv), run type (e.g sweep, single, or synth), part \ 59 | (e.g. xc7z020clg400-1), and board (e.g PYNQ-Z1)" 60 | catch {common::send_msg_id "PYNQ-000" "ERROR" $errmsg} 61 | return 1 62 | } 63 | 64 | set target [lindex $argv 0] 65 | if { [file exists $target.tcl] == 0 } { 66 | puts "" 67 | set errmsg "Could not find file: $target.tcl. \ 68 | The makefile must be co-located with $target.tcl, or \ 69 | $target is incorrect" 70 | catch {common::send_msg_id "PYNQ-000" "ERROR" $errmsg} 71 | return 1 72 | } 73 | 74 | set run_arg [lindex $argv 1] 75 | if { $run_arg == "sweep"} { 76 | set run_type "sweep" 77 | } elseif {$run_arg == "single"} { 78 | set run_type "single" 79 | } elseif {$run_arg == "synth"} { 80 | set run_type "synth" 81 | } else { 82 | puts "" 83 | set errmsg "Unknown argument value $run_arg. Valid values are \ 84 | \"single\", \"sweep\" and \"synth\"" 85 | catch {common::send_msg_id "PYNQ-000" "ERROR" $errmsg} 86 | return 1 87 | } 88 | 89 | set part [lindex $argv 2] 90 | create_project $target $target -part $part 91 | 92 | set board [lindex $argv 3] 93 | set board_xdc $board_dir/$board.xdc 94 | if { [file exists $board_xdc] == 0 } { 95 | puts "" 96 | set errmsg "Could not find file: $board_dir/$board.xdc" 97 | catch {common::send_msg_id "PYNQ-000" "ERROR" $errmsg} 98 | return 1 99 | } 100 | 101 | # In order to compile the Block Diagram design (in a .tcl file), we need to add 102 | # the directory containing the IP to the Vivado search path. 103 | set ip_dirs [lrange $argv 4 end] 104 | puts $ip_dirs 105 | set_property ip_repo_paths $ip_dirs [current_project] 106 | update_ip_catalog 107 | } 108 | 109 | # Build the Vivado Block Diagram design 110 | set design_name $target 111 | create_bd_design $design_name 112 | current_bd_design $design_name 113 | source $target.tcl 114 | create_root_design "" 115 | 116 | # Create top level file 117 | make_wrapper -files [get_files ./$target/$target.srcs/sources_1/bd/$target/$target.bd] -top 118 | 119 | # Add top level file to project 120 | add_files -norecurse ./$target/$target.srcs/sources_1/bd/$target/hdl/$target\_wrapper.v 121 | update_compile_order -fileset sources_1 122 | 123 | # Mark top level file as top level 124 | set_property top $target\_wrapper [current_fileset] 125 | update_compile_order -fileset sources_1 126 | 127 | # Add board design contraints file 128 | add_files -fileset constrs_1 -norecurse $board_xdc 129 | update_compile_order -fileset sources_1 130 | 131 | # If $run_type is "sweep" run a simple binary search by modifying the 132 | # Clock Wizard IP to change the target clock frequency. The script 133 | # expects the IP name to match the value in clk_name. 134 | if { ${run_type} eq "sweep" } { 135 | set clk_name subprocessorClk 136 | set min 0 137 | set max 400 138 | set pass 0 139 | while {($max - $min) > .5} { 140 | set tgt [ expr {double($max + $min)/2} ] 141 | puts "Testing Target Frequency: $tgt" 142 | set_property CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $tgt [get_bd_cells $clk_name] 143 | reset_run synth_1 144 | launch_runs impl_1 -jobs 4 -quiet 145 | wait_on_run impl_1 146 | open_run impl_1 147 | set mult [ get_property CONFIG.MMCM_CLKFBOUT_MULT_F [get_bd_cells $clk_name]] 148 | set div [ get_property CONFIG.MMCM_CLKOUT0_DIVIDE_F [get_bd_cells $clk_name]] 149 | set clkin [ get_property CONFIG.PRIM_IN_FREQ [get_bd_cells $clk_name]] 150 | set actual_freq [ expr $clkin * $mult / $div ] 151 | set slack [ get_property SLACK [get_timing_paths]] 152 | puts "Timing Slack @ $actual_freq: $slack" 153 | if {$slack > 0} { 154 | set min $tgt 155 | set pass $actual_freq 156 | write_bitstream -force $target.bit 157 | } else { 158 | set max $tgt 159 | } 160 | close_design 161 | } 162 | archive_project 163 | puts "Maximum frequency: $pass" 164 | } elseif { ${run_type} eq "synth" } { 165 | launch_runs synth_1 -jobs 4 166 | wait_on_run synth_1 167 | } else { 168 | launch_runs impl_1 -to_step write_bitstream -jobs 4 169 | wait_on_run impl_1 170 | file copy -force ./$target/$target.runs/impl_1/$target\_wrapper.bit $target.bit 171 | } 172 | 173 | 174 | 175 | -------------------------------------------------------------------------------- /riscvonpynq/magic/Magic.py: -------------------------------------------------------------------------------- 1 | # ---------------------------------------------------------------------- 2 | # Copyright (c) 2018, The Regents of the University of California All 3 | # rights reserved. 4 | # 5 | # Redistribution and use in source and binary forms, with or without 6 | # modification, are permitted provided that the following conditions are 7 | # met: 8 | # 9 | # * Redistributions of source code must retain the above copyright 10 | # notice, this list of conditions and the following disclaimer. 11 | # 12 | # * Redistributions in binary form must reproduce the above 13 | # copyright notice, this list of conditions and the following 14 | # disclaimer in the documentation and/or other materials provided 15 | # with the distribution. 16 | # 17 | # * Neither the name of The Regents of the University of California 18 | # nor the names of its contributors may be used to endorse or 19 | # promote products derived from this software without specific 20 | # prior written permission. 21 | # 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT, 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 | # DAMAGE. 34 | # ---------------------------------------------------------------------- 35 | from IPython.core.magic import cell_magic, Magics, magics_class 36 | from IPython import get_ipython 37 | from IPython.display import display, HTML 38 | from IPython.display import display_javascript 39 | 40 | from ..Program import Program 41 | from ..Program import Lang 42 | import tempfile, os 43 | 44 | class _DataHolder: 45 | """Wrapper class for accessing the local variables in the user 46 | namespace 47 | 48 | """ 49 | pass 50 | 51 | @magics_class 52 | class Magic(Magics): 53 | """An iPython Magics class for compiling RISC-V source inside of a 54 | Jupyter Notebook. 55 | 56 | To run a Magic from inside Jupyter Notebooks import Magic 57 | and use the two magics: %%riscvc (for C Source) and %%riscvasm 58 | (for RISC-V Assembly) and %%riscvcpp (for C++ Source) 59 | 60 | """ 61 | def name2obj(self, name): 62 | """Query the local namespace with a name and return an object with 63 | that name (if it exists) 64 | 65 | Parameters 66 | ---------- 67 | name: str 68 | Object name to query the local namespace for 69 | 70 | """ 71 | _proxy = _DataHolder() 72 | exec('_proxy.obj = {}'.format(name), locals(), self.shell.user_ns) 73 | return _proxy.obj 74 | 75 | @cell_magic 76 | def riscvc(self, line, cell): 77 | """Compile a iPython/Jupyter Notebooks cell with C source and return a 78 | Program representing its compilation. 79 | 80 | Parameters 81 | ---------- 82 | line: str 83 | First line of a magics cell. The line should contain the 84 | name of the program to add to the namespace, and the 85 | target processor object in the local namespace 86 | 87 | cell: str 88 | string representation of the RISC-V source in a 89 | iPython/Jupyter Notebook cell following the first line 90 | 91 | """ 92 | try: 93 | program_name, processor_name = line.split(' ') 94 | except: 95 | return HTML('
Usage: %%riscvc program_name processor_name')
 96 | 
 97 |         src_name = f'{program_name}.c'
 98 | 
 99 |         return self.__build(src_name, program_name, processor_name, Lang.C, cell)
100 | 
101 |     @cell_magic
102 |     def riscvasm(self, line, cell):
103 |         """Compile a iPython/Jupyter Notebooks cell with Assembly source and return a
104 |         Program representing its compilation.
105 | 
106 |         Parameters
107 |         ----------
108 |         line: str
109 |             First line of a magics cell. The line should contain the
110 |             name of the program to add to the namespace, and the
111 |             target processor object in the local namespace
112 | 
113 |         cell: str
114 |             string representation of the RISC-V source in a
115 |             iPython/Jupyter Notebook cell following the first line
116 | 
117 |         """
118 |         try:
119 |             program_name, processor_name = line.split(' ')
120 |         except:
121 |             return HTML('
Usage: %%riscvasm program_name processor_name')
122 | 
123 |         src_name = f'{program_name}.S'
124 | 
125 |         return self.__build(src_name, program_name, processor_name, Lang.ASM, cell)
126 | 
127 |     @cell_magic
128 |     def riscvcpp(self, line, cell):
129 |         """Compile a iPython/Jupyter Notebooks cell with C++ source and return
130 |         a Program representing its compilation.
131 | 
132 |         Parameters
133 |         ----------
134 |         line: str
135 |             First line of a magics cell. The line should contain the
136 |             name of the program to add to the namespace, and the name of
137 |             the processor in the namespace
138 | 
139 |         cell: str
140 |             string representation of the RISC-V source in a
141 |             iPython/Jupyter Notebook cell following the first line
142 | 
143 |         """
144 |         try:
145 |             program_name, processor_name = line.split(' ')
146 |         except:
147 |             return HTML('
Usage: %%riscvcpp program_name processor_name')
148 | 
149 |         src_name = f'{program_name}.cpp'
150 | 
151 |         return self.__build(src_name, program_name, processor_name, Lang.CPP, cell)
152 | 
153 |     def __build(self, src_name, program_name, processor_name, lang, cell):
154 |         tempdir = tempfile.mkdtemp()
155 |         with open(os.path.join(tempdir, src_name), 'w') as f:
156 |             f.write(cell)
157 | 
158 |         try:
159 |             processor = self.name2obj(processor_name)
160 |         except KeyError:
161 |             raise RuntimeError(f'Could not find variable {processor_name} in'
162 |                                ' namespace')
163 |         try:
164 |             program = Program(tempdir, program_name, lang)
165 |             program.build(processor)
166 |         except RuntimeError as r:
167 |             return HTML('
Compilation of program {} FAILED\n {} 
'
168 |                         .format(program_name, r.args[0]))
169 |         self.shell.user_ns.update({program_name: program})
170 |         return HTML('
Compilation of program {} SUCCEEDED
'
171 |                     .format(program_name))
172 | 
173 | jsc = '''
174 | require(['notebook/js/codecell'], function(codecell) {
175 |   codecell.CodeCell.options_default.highlight_modes['magic_text/x-csrc'] = {'reg':[/^%%riscvc/]};
176 |   Jupyter.notebook.events.one('kernel_ready.Kernel', function(){
177 |       Jupyter.notebook.get_cells().map(function(cell){
178 |           if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;
179 |   });
180 | });
181 | '''
182 | 
183 | jsasm = '''
184 | require(['notebook/js/codecell'], function(codecell) {
185 |   codecell.CodeCell.options_default.highlight_modes['magic_text/x-asmx'] = {'reg':[/^%%riscvasm/]};
186 |   Jupyter.notebook.events.one('kernel_ready.Kernel', function(){
187 |       Jupyter.notebook.get_cells().map(function(cell){
188 |           if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;
189 |   });
190 | });
191 | '''
192 | 
193 | jscpp = '''
194 | require(['notebook/js/codecell'], function(codecell) {
195 |   codecell.CodeCell.options_default.highlight_modes['magic_text/x-c++src'] = {'reg':[/^%%riscvcpp/]};
196 |   Jupyter.notebook.events.one('kernel_ready.Kernel', function(){
197 |       Jupyter.notebook.get_cells().map(function(cell){
198 |           if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;
199 |   });
200 | });
201 | '''
202 | 
203 | instance = get_ipython()
204 | 
205 | if instance:
206 |     instance.register_magics(Magic)
207 |     display_javascript(jsasm, raw=True)
208 |     display_javascript(jsc, raw=True)
209 |     display_javascript(jscpp, raw=True)
210 |     
211 | 


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/riscvonpynq/magic/__init__.py:
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 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | from . import Magic
36 | 


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/riscvonpynq/picorv32/__init__.py:
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 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | from . import axi
36 | from . import bram
37 | 


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/riscvonpynq/picorv32/axi/__init__.py:
--------------------------------------------------------------------------------
 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | from . import picorv32
36 | from . import build
37 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/axi/build/__init__.py:
--------------------------------------------------------------------------------
 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/axi/build/init.S:
--------------------------------------------------------------------------------
 1 | // ----------------------------------------------------------------------
 2 | // Copyright (c) 2018, The Regents of the University of California All
 3 | // rights reserved.
 4 | //
 5 | // Redistribution and use in source and binary forms, with or without
 6 | // modification, are permitted provided that the following conditions are
 7 | // met:
 8 | //
 9 | //     * Redistributions of source code must retain the above copyright
10 | //       notice, this list of conditions and the following disclaimer.
11 | //
12 | //     * Redistributions in binary form must reproduce the above
13 | //       copyright notice, this list of conditions and the following
14 | //       disclaimer in the documentation and/or other materials provided
15 | //       with the distribution.
16 | //
17 | //     * Neither the name of The Regents of the University of California
18 | //       nor the names of its contributors may be used to endorse or
19 | //       promote products derived from this software without specific
20 | //       prior written permission.
21 | //
22 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | // DAMAGE.
34 | // ----------------------------------------------------------------------
35 | _init:
36 | 	li x0,0
37 | 	li x1,0
38 | 	li x2,STKPTR
39 | 	li x3,0	
40 | 	li x4,0	
41 | 	li x5,0	
42 | 	li x6,0	
43 | 	li x7,0	
44 | 	li x8,0	
45 | 	li x9,0	
46 | 	lw a0,-4(sp)
47 | 	lw a1,-8(sp)
48 | 	li x12,0
49 | 	li x13,0
50 | 	li x14,0
51 | 	li x15,0
52 | 	li x16,0
53 | 	li x17,0
54 | 	li x18,0
55 | 	li x19,0
56 | 	li x20,0
57 | 	li x21,0
58 | 	li x22,0
59 | 	li x23,0
60 | 	li x24,0
61 | 	li x25,0
62 | 	li x26,0
63 | 	li x27,0
64 | 	li x28,0
65 | 	li x29,0
66 | 	li x30,0
67 | 	li x31,0
68 | 	jal main
69 | 	sw a1, -8(sp)
70 | 	sw a0, -4(sp)
71 | _end:	 
72 | 	ebreak
73 | 	// j _end
74 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/axi/build/makefile:
--------------------------------------------------------------------------------
 1 | STKPTR ?= 0x10000
 2 | all: $(TARGET).bin
 3 | 
 4 | init.o: init.S
 5 | 	@echo "Building object file $@ for $<"
 6 | 	riscv32-unknown-elf-gcc -c -Qn -DSTKPTR=$(STKPTR) -march=rv32im \
 7 | 		-o $@ -Os --std=c99 $< 
 8 | 
 9 | %.elf: init.o %.o
10 | 	@echo "Combining object files $< to produce $@"
11 | 	riscv32-unknown-elf-gcc -Os -ffreestanding -nostdlib -o $@ \
12 | 		-Wl,-Bstatic,-T,picorv32.ld \
13 | 		$^ -lgcc -march=rv32im 
14 | 
15 | %.o: %.c 
16 | 	@echo "Building object file $@ for $<"
17 | 	riscv32-unknown-elf-gcc -c -Qn -march=rv32im -o $@ -Os --std=c99 $< 
18 | 
19 | %.o: %.cpp
20 | 	@echo "Building object file $@ for $<"
21 | 	riscv32-unknown-elf-g++ -c -Qn -march=rv32im -o $@ -Os $< 
22 | 
23 | %.o: %.S
24 | 	@echo "Building object file $@ for $<"
25 | 	riscv32-unknown-elf-gcc -c -Qn -DSTKPTR=$(STKPTR) -march=rv32im \
26 | 		-o $@ -Os --std=c99 $< 
27 | 
28 | %.bin: %.elf
29 | 	@echo "Converting .elf file $< into $@"
30 | 	riscv32-unknown-elf-objcopy -O binary $< $@
31 | 
32 | # Use .PRECIOUS to keep elf files so that objdump can be run (for debugging)
33 | .PRECIOUS: %.elf %.o
34 | 
35 | clean:
36 | 	rm -rf *.hex *.bin *.elf *.o
37 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/axi/build/picorv32.ld:
--------------------------------------------------------------------------------
 1 | /* ----------------------------------------------------------------------
 2 | // Copyright (c) 2018, The Regents of the University of California All
 3 | // rights reserved.
 4 | //
 5 | // Redistribution and use in source and binary forms, with or without
 6 | // modification, are permitted provided that the following conditions are
 7 | // met:
 8 | //
 9 | //     * Redistributions of source code must retain the above copyright
10 | //       notice, this list of conditions and the following disclaimer.
11 | //
12 | //     * Redistributions in binary form must reproduce the above
13 | //       copyright notice, this list of conditions and the following
14 | //       disclaimer in the documentation and/or other materials provided
15 | //       with the distribution.
16 | //
17 | //     * Neither the name of The Regents of the University of California
18 | //       nor the names of its contributors may be used to endorse or
19 | //       promote products derived from this software without specific
20 | //       prior written permission.
21 | //
22 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | // DAMAGE.
34 | // ---------------------------------------------------------------------- */
35 | MEMORY {
36 | 	mem : ORIGIN = 0x00000000, LENGTH = 0x00010000
37 | }
38 | 
39 | SECTIONS {
40 | 	.memory : {
41 | 		. = 0x000000;
42 | 		_init*(.text);
43 | 		trap_vector*(.text);
44 | 		*(.text);
45 | 		*(*);
46 | 		end = .;
47 | 	} > mem
48 | }
49 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/axi/makefile:
--------------------------------------------------------------------------------
 1 | ###############################################################################
 2 | #  Copyright (c) 2017, Xilinx, Inc.
 3 | #  All rights reserved.
 4 | #
 5 | #  Redistribution and use in source and binary forms, with or without
 6 | #  modification, are permitted provided that the following conditions are met:
 7 | #
 8 | #  1.  Redistributions of source code must retain the above copyright notice,
 9 | #     this list of conditions and the following disclaimer.
10 | #
11 | #  2.  Redistributions in binary form must reproduce the above copyright
12 | #      notice, this list of conditions and the following disclaimer in the
13 | #      documentation and/or other materials provided with the distribution.
14 | #
15 | #  3.  Neither the name of the copyright holder nor the names of its
16 | #      contributors may be used to endorse or promote products derived from
17 | #      this software without specific prior written permission.
18 | #
19 | #  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 | #  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | #  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 | #  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 | #  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 | #  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 | #  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 | #  OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 | #  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 | #  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 | #  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 | #
31 | ###############################################################################
32 | BUILD_PATH=../../
33 | BOARD_PATH=$(BUILD_PATH)
34 | IP_PATH=../../../ip/
35 | BOARD=PYNQ-Z1
36 | PART=xc7z020clg400-1
37 | DESIGN=picorv32
38 | IPS=picorv32_axi
39 | 
40 | include $(BUILD_PATH)/build.mk
41 | 


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/riscvonpynq/picorv32/axi/picorv32.py:
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  1 | # ----------------------------------------------------------------------
  2 | # Copyright (c) 2018, The Regents of the University of California All
  3 | # rights reserved.
  4 | #
  5 | # Redistribution and use in source and binary forms, with or without
  6 | # modification, are permitted provided that the following conditions are
  7 | # met:
  8 | #
  9 | #     * Redistributions of source code must retain the above copyright
 10 | #       notice, this list of conditions and the following disclaimer.
 11 | #
 12 | #     * Redistributions in binary form must reproduce the above
 13 | #       copyright notice, this list of conditions and the following
 14 | #       disclaimer in the documentation and/or other materials provided
 15 | #       with the distribution.
 16 | #
 17 | #     * Neither the name of The Regents of the University of California
 18 | #       nor the names of its contributors may be used to endorse or
 19 | #       promote products derived from this software without specific
 20 | #       prior written permission.
 21 | #
 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 33 | # DAMAGE.
 34 | # ----------------------------------------------------------------------
 35 | from riscvonpynq.Overlay import Overlay
 36 | from riscvonpynq.Processor import MixedProcessor
 37 | 
 38 | import os, inspect
 39 | 
 40 | class Overlay(Overlay):
 41 |     """Overlay driver for the PicoRV32 AXI Overlay
 42 | 
 43 |     Note
 44 |     ----
 45 |     This class definition must be co-located with the .tcl and .bit
 46 |     file for the overlay for the search path modifications in
 47 |     riscvonpynq.Overlay to work. __init__ in riscvonpynq.Overlay uses
 48 |     the path of this file to search for the .bit file using the
 49 |     inspect package.
 50 | 
 51 |     """
 52 |     pass
 53 | 
 54 | class Processor(MixedProcessor):
 55 |     """Hierarchy driver for the PicoRV32 AXI Processor
 56 | 
 57 |     Note
 58 |     ----
 59 |     In order to be recognized as a RISC-V Processor hierarchy, three
 60 |     conditions must be met: First, there must be a PS-Memory-Mapped
 61 |     Block RAM Controller where the name matches the variable
 62 |     _bram. Second, the hierarchy name (fullpath) must equal the
 63 |     variable _name. Finally, there must be a GPIO port with the name
 64 |     _reset_name.
 65 | 
 66 |     Subclasses of this module are responsible for setting _name (The
 67 |     name of the Hierarchy), _bits (Processor bit-width), _proc
 68 |     (Processor Type Name)
 69 | 
 70 |     This class must be placed in a known location relative to the
 71 |     build files for this processor. The relative path can be modified
 72 |     in __get_path.
 73 | 
 74 |     """
 75 |     _name = 'picoAxiProcessor'
 76 |     _proc = 'picorv32'
 77 |     _bits = 32
 78 | 
 79 |     @classmethod
 80 |     def checkhierarchy(cls, description):
 81 |         return super().checkhierarchy(description)
 82 | 
 83 |     def __get_path(self):
 84 |         """Get the directory path of this file, or the directory path of the
 85 |         class that inherits from this class.
 86 | 
 87 |         """
 88 |         # Get file path of the current class (i.e. /opt/python3.6/<...>/stream.py)
 89 |         file_path = os.path.abspath(inspect.getfile(inspect.getmodule(self)))
 90 |         # Get directory path of the current class (i.e. /opt/python3.6/<...>/stream/)
 91 |         return os.path.dirname(file_path)
 92 | 
 93 |     def __init__(self, description, *args):
 94 |         """Return a new Processor object. 
 95 | 
 96 |         Parameters
 97 |         ----------
 98 |         description : dict
 99 |             Dictionary describing this processor.
100 | 
101 |         """
102 |         build_path = os.path.join(self.__get_path(), "build")
103 |         reset_value = 0
104 |         super().__init__(build_path, reset_value, description, *args)
105 | 


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/riscvonpynq/picorv32/bram/__init__.py:
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 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | from . import picorv32
36 | from . import build
37 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/bram/build/__init__.py:
--------------------------------------------------------------------------------
 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/bram/build/init.S:
--------------------------------------------------------------------------------
 1 | // ----------------------------------------------------------------------
 2 | // Copyright (c) 2018, The Regents of the University of California All
 3 | // rights reserved.
 4 | //
 5 | // Redistribution and use in source and binary forms, with or without
 6 | // modification, are permitted provided that the following conditions are
 7 | // met:
 8 | //
 9 | //     * Redistributions of source code must retain the above copyright
10 | //       notice, this list of conditions and the following disclaimer.
11 | //
12 | //     * Redistributions in binary form must reproduce the above
13 | //       copyright notice, this list of conditions and the following
14 | //       disclaimer in the documentation and/or other materials provided
15 | //       with the distribution.
16 | //
17 | //     * Neither the name of The Regents of the University of California
18 | //       nor the names of its contributors may be used to endorse or
19 | //       promote products derived from this software without specific
20 | //       prior written permission.
21 | //
22 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | // DAMAGE.
34 | // ----------------------------------------------------------------------
35 | _init:
36 | 	li x0,0
37 | 	li x1,0
38 | 	li x2,STKPTR
39 | 	li x3,0	
40 | 	li x4,0	
41 | 	li x5,0	
42 | 	li x6,0	
43 | 	li x7,0	
44 | 	li x8,0	
45 | 	li x9,0	
46 | 	lw a0,-4(sp)
47 | 	lw a1,-8(sp)
48 | 	li x12,0
49 | 	li x13,0
50 | 	li x14,0
51 | 	li x15,0
52 | 	li x16,0
53 | 	li x17,0
54 | 	li x18,0
55 | 	li x19,0
56 | 	li x20,0
57 | 	li x21,0
58 | 	li x22,0
59 | 	li x23,0
60 | 	li x24,0
61 | 	li x25,0
62 | 	li x26,0
63 | 	li x27,0
64 | 	li x28,0
65 | 	li x29,0
66 | 	li x30,0
67 | 	li x31,0
68 | 	jal main
69 | 	sw a1, -8(sp)
70 | 	sw a0, -4(sp)
71 | _end:	 
72 | 	ebreak
73 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/bram/build/makefile:
--------------------------------------------------------------------------------
 1 | STKPTR ?= 0x8000
 2 | all: $(TARGET).bin
 3 | 
 4 | init.o: init.S
 5 | 	@echo "Building object file $@ for $<"
 6 | 	riscv32-unknown-elf-gcc -c -Qn -DSTKPTR=$(STKPTR) -march=rv32im \
 7 | 		-o $@ -Os --std=c99 $< 
 8 | 
 9 | %.elf: init.o %.o 
10 | 	@echo "Combining object files $< to produce $@"
11 | 	riscv32-unknown-elf-gcc -Os -ffreestanding -nostdlib -o $@ \
12 | 		-Wl,-Bstatic,-T,picorv32.ld \
13 | 		$^ -lgcc -march=rv32im 
14 | 
15 | %.o: %.c 
16 | 	@echo "Building object file $@ for $<"
17 | 	riscv32-unknown-elf-gcc -c -Qn -march=rv32im -o $@ -Os --std=c99 $< 
18 | 
19 | %.o: %.cpp
20 | 	@echo "Building object file $@ for $<"
21 | 	riscv32-unknown-elf-g++ -c -Qn -march=rv32im -o $@ -Os $< 
22 | 
23 | %.o: %.S
24 | 	@echo "Building object file $@ for $<"
25 | 	riscv32-unknown-elf-gcc -c -Qn -DSTKPTR=$(STKPTR) -march=rv32im \
26 | 		-o $@ -Os --std=c99 $< 
27 | 
28 | %.bin: %.elf
29 | 	@echo "Converting .elf file $< into $@"
30 | 	riscv32-unknown-elf-objcopy -O binary $< $@
31 | 
32 | # Use .PRECIOUS to keep elf files so that objdump can be run (for debugging)
33 | .PRECIOUS: %.elf %.o
34 | 
35 | clean:
36 | 	rm -rf *.hex *.bin *.elf *.o
37 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/bram/build/picorv32.ld:
--------------------------------------------------------------------------------
 1 | /* ----------------------------------------------------------------------
 2 | // Copyright (c) 2018, The Regents of the University of California All
 3 | // rights reserved.
 4 | //
 5 | // Redistribution and use in source and binary forms, with or without
 6 | // modification, are permitted provided that the following conditions are
 7 | // met:
 8 | //
 9 | //     * Redistributions of source code must retain the above copyright
10 | //       notice, this list of conditions and the following disclaimer.
11 | //
12 | //     * Redistributions in binary form must reproduce the above
13 | //       copyright notice, this list of conditions and the following
14 | //       disclaimer in the documentation and/or other materials provided
15 | //       with the distribution.
16 | //
17 | //     * Neither the name of The Regents of the University of California
18 | //       nor the names of its contributors may be used to endorse or
19 | //       promote products derived from this software without specific
20 | //       prior written permission.
21 | //
22 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | // DAMAGE.
34 | // ---------------------------------------------------------------------- */
35 | MEMORY {
36 | 	mem : ORIGIN = 0x00000000, LENGTH = 0x00008000
37 | }
38 | 
39 | SECTIONS {
40 | 	.memory : {
41 | 		. = 0x000000;
42 | 		_init*(.text);
43 | 		trap_vector*(.text);
44 | 		*(.text);
45 | 		*(*);
46 | 		end = .;
47 | 	} > mem
48 | }
49 | 


--------------------------------------------------------------------------------
/riscvonpynq/picorv32/bram/makefile:
--------------------------------------------------------------------------------
 1 | ###############################################################################
 2 | #  Copyright (c) 2017, Xilinx, Inc.
 3 | #  All rights reserved.
 4 | #
 5 | #  Redistribution and use in source and binary forms, with or without
 6 | #  modification, are permitted provided that the following conditions are met:
 7 | #
 8 | #  1.  Redistributions of source code must retain the above copyright notice,
 9 | #     this list of conditions and the following disclaimer.
10 | #
11 | #  2.  Redistributions in binary form must reproduce the above copyright
12 | #      notice, this list of conditions and the following disclaimer in the
13 | #      documentation and/or other materials provided with the distribution.
14 | #
15 | #  3.  Neither the name of the copyright holder nor the names of its
16 | #      contributors may be used to endorse or promote products derived from
17 | #      this software without specific prior written permission.
18 | #
19 | #  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 | #  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | #  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 | #  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 | #  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 | #  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 | #  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 | #  OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 | #  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 | #  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 | #  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 | #
31 | ###############################################################################
32 | BUILD_PATH=../../
33 | BOARD_PATH=$(BUILD_PATH)
34 | IP_PATH=../../../ip/
35 | BOARD=PYNQ-Z1
36 | PART=xc7z020clg400-1
37 | DESIGN=picorv32
38 | IPS=picorv32_bram
39 | 
40 | include $(BUILD_PATH)/build.mk
41 | 


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/riscvonpynq/picorv32/bram/picorv32.bit:
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/riscvonpynq/picorv32/bram/picorv32.py:
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  1 | # ----------------------------------------------------------------------
  2 | # Copyright (c) 2018, The Regents of the University of California All
  3 | # rights reserved.
  4 | #
  5 | # Redistribution and use in source and binary forms, with or without
  6 | # modification, are permitted provided that the following conditions are
  7 | # met:
  8 | #
  9 | #     * Redistributions of source code must retain the above copyright
 10 | #       notice, this list of conditions and the following disclaimer.
 11 | #
 12 | #     * Redistributions in binary form must reproduce the above
 13 | #       copyright notice, this list of conditions and the following
 14 | #       disclaimer in the documentation and/or other materials provided
 15 | #       with the distribution.
 16 | #
 17 | #     * Neither the name of The Regents of the University of California
 18 | #       nor the names of its contributors may be used to endorse or
 19 | #       promote products derived from this software without specific
 20 | #       prior written permission.
 21 | #
 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 33 | # DAMAGE.
 34 | # ----------------------------------------------------------------------
 35 | from riscvonpynq.Overlay import Overlay
 36 | from riscvonpynq.Processor import BramProcessor
 37 | import os, inspect
 38 | 
 39 | class Overlay(Overlay):
 40 |     """Overlay driver for the PicoRV32 bram Overlay
 41 | 
 42 |     Note
 43 |     ----
 44 |     This class definition must be co-located with the .tcl and .bit
 45 |     file for the overlay for the search path modifications in
 46 |     riscvonpynq.Overlay to work. __init__ in riscvonpynq.Overlay uses
 47 |     the path of this file to search for the .bit file using the
 48 |     inspect package.
 49 | 
 50 |     """
 51 |     pass
 52 | 
 53 | class Processor(BramProcessor):
 54 |     """Hierarchy driver for the PicoRV32 BRAM Processor
 55 | 
 56 |     Note
 57 |     ----
 58 |     In order to be recognized as a RISC-V Processor hierarchy, three
 59 |     conditions must be met: First, there must be a PS-Memory-Mapped
 60 |     Block RAM Controller where the name matches the variable
 61 |     _bram. Second, the hierarchy name (fullpath) must equal the
 62 |     variable _name. Finally, there must be a GPIO port with the name
 63 |     _reset_name.
 64 | 
 65 |     Subclasses of this module are responsible for setting _name (The
 66 |     name of the Hierarchy), _bits (Processor bit-width), _proc
 67 |     (Processor Type Name)
 68 | 
 69 |     This class must be placed in a known location relative to the
 70 |     build files for this processor. The relative path can be modified
 71 |     in __get_path.
 72 | 
 73 |     """
 74 |     _name = 'picoBramProcessor'
 75 |     _proc = 'picorv32'
 76 |     _bits = 32
 77 | 
 78 |     @classmethod
 79 |     def checkhierarchy(cls, description):
 80 |         return super().checkhierarchy(description)
 81 | 
 82 |     def __get_path(self):
 83 |         """Get the directory path of this file, or the directory path of the
 84 |         class that inherits from this class.
 85 | 
 86 |         """
 87 |         # Get file path of the current class (i.e. /opt/python3.6/<...>/stream.py)
 88 |         file_path = os.path.abspath(inspect.getfile(inspect.getmodule(self)))
 89 |         # Get directory path of the current class (i.e. /opt/python3.6/<...>/stream/)
 90 |         return os.path.dirname(file_path)
 91 | 
 92 |     def __init__(self, description, *args):
 93 |         """Return a new Processor object. 
 94 | 
 95 |         Parameters
 96 |         ----------
 97 |         description : dict
 98 |             Dictionary describing this processor.
 99 | 
100 |         """
101 |         build_path = os.path.join(self.__get_path(), "build")
102 |         reset_value = 0
103 |         super().__init__(build_path, reset_value, description, *args)
104 |     
105 | 


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/riscvonpynq/picorv32/tut/README.md:
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https://raw.githubusercontent.com/drichmond/RISC-V-On-PYNQ/9eba461cd98ace8bb36caafef2680e1fab8b7b3a/riscvonpynq/picorv32/tut/README.md


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/riscvonpynq/picorv32/tut/gold/__init__.py:
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1 | from . import tutorial
2 | from . import build
3 | 


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/riscvonpynq/picorv32/tut/gold/build/__init__.py:
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 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | 


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/riscvonpynq/picorv32/tut/gold/build/init.S:
--------------------------------------------------------------------------------
 1 | // ----------------------------------------------------------------------
 2 | // Copyright (c) 2018, The Regents of the University of California All
 3 | // rights reserved.
 4 | //
 5 | // Redistribution and use in source and binary forms, with or without
 6 | // modification, are permitted provided that the following conditions are
 7 | // met:
 8 | //
 9 | //     * Redistributions of source code must retain the above copyright
10 | //       notice, this list of conditions and the following disclaimer.
11 | //
12 | //     * Redistributions in binary form must reproduce the above
13 | //       copyright notice, this list of conditions and the following
14 | //       disclaimer in the documentation and/or other materials provided
15 | //       with the distribution.
16 | //
17 | //     * Neither the name of The Regents of the University of California
18 | //       nor the names of its contributors may be used to endorse or
19 | //       promote products derived from this software without specific
20 | //       prior written permission.
21 | //
22 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | // DAMAGE.
34 | // ----------------------------------------------------------------------
35 | _init:
36 | 	li x0,0
37 | 	li x1,0
38 | 	li x2,STKPTR
39 | 	li x3,0	
40 | 	li x4,0	
41 | 	li x5,0	
42 | 	li x6,0	
43 | 	li x7,0	
44 | 	li x8,0	
45 | 	li x9,0	
46 | 	lw a0,-4(sp)
47 | 	lw a1,-8(sp)
48 | 	li x12,0
49 | 	li x13,0
50 | 	li x14,0
51 | 	li x15,0
52 | 	li x16,0
53 | 	li x17,0
54 | 	li x18,0
55 | 	li x19,0
56 | 	li x20,0
57 | 	li x21,0
58 | 	li x22,0
59 | 	li x23,0
60 | 	li x24,0
61 | 	li x25,0
62 | 	li x26,0
63 | 	li x27,0
64 | 	li x28,0
65 | 	li x29,0
66 | 	li x30,0
67 | 	li x31,0
68 | 	jal main
69 | 	sw a1, -8(sp)
70 | 	sw a0, -4(sp)
71 | _end:	 
72 | 	ebreak
73 | 


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/riscvonpynq/picorv32/tut/gold/build/makefile:
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 1 | STKPTR ?= 0x8000
 2 | all: $(TARGET).bin
 3 | 
 4 | init.o: init.S
 5 | 	@echo "Building object file $@ for $<"
 6 | 	riscv32-unknown-elf-gcc -c -Qn -DSTKPTR=$(STKPTR) -march=rv32im \
 7 | 		-o $@ -Os --std=c99 $< 
 8 | 
 9 | %.elf: %.o init.o 
10 | 	@echo "Combining object files $< to produce $@"
11 | 	riscv32-unknown-elf-gcc -Os -ffreestanding -nostdlib -o $@ \
12 | 		-Wl,-Bstatic,-T,picorv32.ld \
13 | 		$^ -lgcc -march=rv32im 
14 | 
15 | %.o: %.c 
16 | 	@echo "Building object file $@ for $<"
17 | 	riscv32-unknown-elf-gcc -c -Qn -march=rv32im -o $@ -Os --std=c99 $< 
18 | 
19 | %.o: %.cpp
20 | 	@echo "Building object file $@ for $<"
21 | 	riscv32-unknown-elf-g++ -c -Qn -march=rv32im -o $@ -Os $< 
22 | 
23 | %.o: %.S
24 | 	@echo "Building object file $@ for $<"
25 | 	riscv32-unknown-elf-gcc -c -Qn -DSTKPTR=$(STKPTR) -march=rv32im \
26 | 		-o $@ -Os --std=c99 $< 
27 | 
28 | %.bin: %.elf
29 | 	@echo "Converting .elf file $< into $@"
30 | 	riscv32-unknown-elf-objcopy -O binary $< $@
31 | 
32 | # Use .PRECIOUS to keep elf files so that objdump can be run (for debugging)
33 | .PRECIOUS: %.elf %.o
34 | 
35 | clean:
36 | 	rm -rf *.hex *.bin *.elf *.o
37 | 


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/riscvonpynq/picorv32/tut/gold/build/picorv32.ld:
--------------------------------------------------------------------------------
 1 | /* ----------------------------------------------------------------------
 2 | // Copyright (c) 2018, The Regents of the University of California All
 3 | // rights reserved.
 4 | //
 5 | // Redistribution and use in source and binary forms, with or without
 6 | // modification, are permitted provided that the following conditions are
 7 | // met:
 8 | //
 9 | //     * Redistributions of source code must retain the above copyright
10 | //       notice, this list of conditions and the following disclaimer.
11 | //
12 | //     * Redistributions in binary form must reproduce the above
13 | //       copyright notice, this list of conditions and the following
14 | //       disclaimer in the documentation and/or other materials provided
15 | //       with the distribution.
16 | //
17 | //     * Neither the name of The Regents of the University of California
18 | //       nor the names of its contributors may be used to endorse or
19 | //       promote products derived from this software without specific
20 | //       prior written permission.
21 | //
22 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | // DAMAGE.
34 | // ---------------------------------------------------------------------- */
35 | MEMORY {
36 | 	mem : ORIGIN = 0x00000000, LENGTH = 0x00008000
37 | }
38 | 
39 | SECTIONS {
40 | 	.memory : {
41 | 		. = 0x000000;
42 | 		_init*(.text);
43 | 		trap_vector*(.text);
44 | 		*(.text);
45 | 		*(*);
46 | 		end = .;
47 | 	} > mem
48 | }
49 | 


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/riscvonpynq/picorv32/tut/gold/tutorial.bit:
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https://raw.githubusercontent.com/drichmond/RISC-V-On-PYNQ/9eba461cd98ace8bb36caafef2680e1fab8b7b3a/riscvonpynq/picorv32/tut/gold/tutorial.bit


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/riscvonpynq/picorv32/tut/gold/tutorial.py:
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  1 | # ----------------------------------------------------------------------
  2 | # Copyright (c) 2018, The Regents of the University of California All
  3 | # rights reserved.
  4 | #
  5 | # Redistribution and use in source and binary forms, with or without
  6 | # modification, are permitted provided that the following conditions are
  7 | # met:
  8 | #
  9 | #     * Redistributions of source code must retain the above copyright
 10 | #       notice, this list of conditions and the following disclaimer.
 11 | #
 12 | #     * Redistributions in binary form must reproduce the above
 13 | #       copyright notice, this list of conditions and the following
 14 | #       disclaimer in the documentation and/or other materials provided
 15 | #       with the distribution.
 16 | #
 17 | #     * Neither the name of The Regents of the University of California
 18 | #       nor the names of its contributors may be used to endorse or
 19 | #       promote products derived from this software without specific
 20 | #       prior written permission.
 21 | #
 22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
 26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
 27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 33 | # DAMAGE.
 34 | # ----------------------------------------------------------------------
 35 | from riscvonpynq.Overlay import Overlay
 36 | from riscvonpynq.Processor import BramProcessor
 37 | import os, inspect
 38 | 
 39 | class TutorialOverlay(Overlay):
 40 |     """Overlay driver for the PicoRV32 bram Overlay
 41 | 
 42 |     Note
 43 |     ----
 44 |     This class definition must be co-located with the .tcl and .bit
 45 |     file for the overlay for the search path modifications in
 46 |     riscvonpynq.Overlay to work. __init__ in riscvonpynq.Overlay uses
 47 |     the path of this file to search for the .bit file using the
 48 |     inspect package.
 49 | 
 50 |     """
 51 |     pass
 52 | 
 53 | class TutorialProcessor(BramProcessor):
 54 |     """Hierarchy driver for the PicoRV32 BRAM Processor
 55 | 
 56 |     Note
 57 |     ----
 58 |     In order to be recognized as a RISC-V Processor hierarchy, three
 59 |     conditions must be met: First, there must be a PS-Memory-Mapped
 60 |     Block RAM Controller where the name matches the variable
 61 |     _bram. Second, the hierarchy name (fullpath) must equal the
 62 |     variable _name. Finally, there must be a GPIO port with the name
 63 |     _reset_name.
 64 | 
 65 |     Subclasses of this module are responsible for setting _name (The
 66 |     name of the Hierarchy), _bits (Processor bit-width), _proc
 67 |     (Processor Type Name)
 68 | 
 69 |     This class must be placed in a known location relative to the
 70 |     build files for this processor. The relative path can be modified
 71 |     in __get_path.
 72 | 
 73 |     """
 74 |     _name = 'tutorialProcessor'
 75 |     _proc = 'picorv32'
 76 |     _bits = 32
 77 | 
 78 |     @classmethod
 79 |     def checkhierarchy(cls, description):
 80 |         return super().checkhierarchy(description)
 81 | 
 82 |     def __get_path(self):
 83 |         """Get the directory path of this file, or the directory path of the
 84 |         class that inherits from this class.
 85 | 
 86 |         """
 87 |         # Get file path of the current class (i.e. /opt/python3.6/<...>/stream.py)
 88 |         file_path = os.path.abspath(inspect.getfile(inspect.getmodule(self)))
 89 |         # Get directory path of the current class (i.e. /opt/python3.6/<...>/stream/)
 90 |         return os.path.dirname(file_path)
 91 | 
 92 |     def __init__(self, description, *args):
 93 |         """Return a new Processor object. 
 94 | 
 95 |         Parameters
 96 |         ----------
 97 |         description : dict
 98 |             Dictionary describing this processor.
 99 | 
100 |         """
101 |         build_path = os.path.join(self.__get_path(), "build")
102 |         reset_value = 0
103 |         super().__init__(build_path, reset_value, description, *args)
104 |     
105 | 


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/riscvonpynq/picorv32/tut/makefile:
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 1 | ###############################################################################
 2 | #  Copyright (c) 2017, Xilinx, Inc.
 3 | #  All rights reserved.
 4 | #
 5 | #  Redistribution and use in source and binary forms, with or without
 6 | #  modification, are permitted provided that the following conditions are met:
 7 | #
 8 | #  1.  Redistributions of source code must retain the above copyright notice,
 9 | #     this list of conditions and the following disclaimer.
10 | #
11 | #  2.  Redistributions in binary form must reproduce the above copyright
12 | #      notice, this list of conditions and the following disclaimer in the
13 | #      documentation and/or other materials provided with the distribution.
14 | #
15 | #  3.  Neither the name of the copyright holder nor the names of its
16 | #      contributors may be used to endorse or promote products derived from
17 | #      this software without specific prior written permission.
18 | #
19 | #  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 | #  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 | #  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 | #  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 | #  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 | #  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 | #  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 | #  OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 | #  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 | #  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 | #  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 | #
31 | ###############################################################################
32 | BUILD_PATH=../../
33 | BOARD_PATH=$(BUILD_PATH)
34 | IP_PATH=../../../ip/
35 | BOARD=PYNQ-Z1
36 | PART=xc7z020clg400-1
37 | DESIGN=tutorial
38 | IPS=picorv32_axi
39 | 
40 | include $(BUILD_PATH)/build.mk
41 | 


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/setup.py:
--------------------------------------------------------------------------------
 1 | # ----------------------------------------------------------------------
 2 | # Copyright (c) 2018, The Regents of the University of California All
 3 | # rights reserved.
 4 | #
 5 | # Redistribution and use in source and binary forms, with or without
 6 | # modification, are permitted provided that the following conditions are
 7 | # met:
 8 | #
 9 | #     * Redistributions of source code must retain the above copyright
10 | #       notice, this list of conditions and the following disclaimer.
11 | #
12 | #     * Redistributions in binary form must reproduce the above
13 | #       copyright notice, this list of conditions and the following
14 | #       disclaimer in the documentation and/or other materials provided
15 | #       with the distribution.
16 | #
17 | #     * Neither the name of The Regents of the University of California
18 | #       nor the names of its contributors may be used to endorse or
19 | #       promote products derived from this software without specific
20 | #       prior written permission.
21 | #
22 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26 | # UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 | # BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 | # OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 | # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31 | # TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32 | # USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 | # DAMAGE.
34 | # ----------------------------------------------------------------------
35 | from setuptools import setup, find_packages
36 | 
37 | import os
38 | 
39 | jupyter_dest = '//home/xilinx/jupyter_notebooks'
40 | notebooks_root = 'notebooks'
41 | data_files = []
42 | 
43 | # Find all of the tutorial notebooks in the tutorials_src path
44 | tutorials_src = os.path.join(notebooks_root, 'tutorial')
45 | tutorials_dest = os.path.join(jupyter_dest, 'RISC-V-Tutorial')
46 | tutorials = [os.path.join(tutorials_src, f)
47 |              for f in os.listdir(tutorials_src)
48 |              if f.endswith(".ipynb")]
49 | data_files.append((tutorials_dest, tutorials))
50 | 
51 | # Find all of the tutorial notebook pictures in the pictures_src path
52 | pictures_src = os.path.join(tutorials_src, 'pictures')
53 | pictures_dest = os.path.join(tutorials_dest, 'pictures')
54 | pictures = [os.path.join(pictures_src, f)
55 |             for f in os.listdir(pictures_src)
56 |             if f.endswith(".png")]
57 | data_files.append((pictures_dest, pictures))
58 | 
59 | examples_src = os.path.join(notebooks_root, 'examples')
60 | examples_dest = os.path.join(jupyter_dest, 'RISC-V-Examples')
61 | examples = [os.path.join(examples_src, f)
62 |              for f in os.listdir(examples_src)
63 |              if f.endswith(".ipynb")]
64 | data_files.append((examples_dest, examples))
65 | 
66 | setup(name='riscvonpynq',
67 |       version='0.1',
68 |       description="A simple package describing how to create a RISC-V FPGA bitstream\
69 |             and package it as a PYNQ overlay",
70 |       author='Dustin Richmond',
71 |       author_email='drichmond@eng.ucsd.edu',
72 |       url='https://github.com/drichmond/RISC-V-On-PYNQ/',
73 |       license='BSD-3',
74 |       data_files = data_files,
75 |       packages=find_packages(),
76 |       package_data={'':['*.bit', '*.tcl', '*.hwh', '*.S', '*.ld', 'makefile']},
77 |       install_requires=['pynq'],
78 |       dependency_links=['http://github.com/xilinx/PYNQ.git@v2.1#egg=pynq'],
79 | )
80 | 


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