├── CRC ├── crc.v ├── crc_tb.v └── crc_two.v ├── README.md ├── coder ├── coder10to4.v └── decoder4to10.v ├── d_latch ├── d_latch.v └── d_latch_tb.v ├── d_trig ├── d_trig.v └── d_trig_tb.v ├── data_encrypt ├── data_decrypt.v ├── data_encrypt.v └── data_encrypt_tb.v ├── demux1to4 ├── demux1to4.v └── demux1to4_tb.v ├── digitalTube ├── seg_display.v ├── seg_display_tb.v └── tags ├── gate_construct ├── gate_construct.v └── gate_construct_tb.v ├── jk_tirg ├── jk_trig.v └── jk_trig_tb.v ├── mux4to1 ├── mux4to1.v └── mux4to1_tb.v └── simpleExample ├── counter.v ├── function.v ├── mux.v ├── muxtwo.v └── string.v /CRC/crc.v: -------------------------------------------------------------------------------- 1 | /* 2 | 4位CRC校验 3 | 生成多项式10111 4 | */ 5 | 6 | module crc 7 | ( 8 | input i_rst_n, 9 | input i_clk, 10 | 11 | input[2:0] i_data, 12 | output[3:0] o_crc_code, 13 | 14 | output o_crc_done 15 | ); 16 | 17 | parameter GX = 5'b10111; 18 | 19 | reg[7:0] r_shift; 20 | reg[2:0] r_cnt; 21 | 22 | reg[3:0] r_crc_code; 23 | reg r_crc_done; 24 | 25 | assign o_crc_done = r_crc_done; 26 | assign o_crc_code = r_crc_code; 27 | 28 | 29 | always@( posedge i_clk, negedge i_rst_n) 30 | begin 31 | if(~i_rst_n) 32 | begin 33 | r_crc_code <= 4'b0; 34 | r_crc_done <= 1'b0; 35 | r_shift <= 8'b0; 36 | r_cnt <= 3'b0; 37 | end 38 | else 39 | if(r_cnt == 3'd3) //CRC编码完成 40 | begin 41 | //重新置0 42 | r_shift <= {1'b0, i_data, 4'b0}; 43 | r_cnt <= 3'b0; 44 | //读出结果 45 | r_crc_code <= r_shift[6:3]; 46 | r_crc_done <= 1'b1; 47 | end 48 | else 49 | begin 50 | if(r_shift[6] == 1'b1)//最高位为1则为除法 51 | begin 52 | r_shift[7:3] <= r_shift[6:2] ^ GX; 53 | r_shift[2:0] <= {r_shift[1:0], 1'b0}; 54 | end 55 | else //否则借位 56 | r_shift <= {r_shift[6:0], 1'b0}; 57 | 58 | //每计算一位，r_cnt加1 59 | r_cnt <= r_cnt + 3'd1; 60 | r_crc_done <= 1'b0; 61 | end 62 | end 63 | 64 | endmodule 65 | -------------------------------------------------------------------------------- /CRC/crc_tb.v: -------------------------------------------------------------------------------- 1 | module crc_tb; 2 | 3 | reg r_rst_n; 4 | reg r_clk; 5 | 6 | reg[2:0] r_data; 7 | 8 | wire[3:0] w_crc_code; 9 | wire w_crc_done; 10 | 11 | crc I_crc( 12 | .i_data(r_data), 13 | .i_rst_n(r_rst_n), 14 | .i_clk(r_clk), 15 | .o_crc_code(w_crc_code), 16 | .o_crc_done(w_crc_done) 17 | ); 18 | 19 | initial 20 | begin 21 | r_clk = 1'b0; 22 | forever 23 | #1 r_clk = ~r_clk; 24 | end 25 | 26 | initial 27 | begin 28 | r_rst_n = 1'b0; 29 | #10 r_rst_n = 1'b1; 30 | end 31 | 32 | initial 33 | begin 34 | r_data = 3'b0; 35 | forever 36 | #8 r_data = r_data + 3'd1; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /CRC/crc_two.v: -------------------------------------------------------------------------------- 1 | /* 2 | * 这是根据 串行CRC电路 写出的代码 3 | * 根据 串行CRC电路 可以推导出 并行CRC电路(纯组合逻辑) 4 | */ 5 | module crc_two 6 | ( 7 | input i_rst_n, 8 | input i_clk, 9 | 10 | input i_data, 11 | output o_code, 12 | output o_crc_done 13 | ); 14 | 15 | reg r_code; 16 | reg r_crc_done; 17 | 18 | reg[3:0] r_shift; 19 | reg[2:0] r_cnt; 20 | 21 | 22 | assign o_code = r_code; 23 | assign o_crc_done= r_crc_done; 24 | 25 | 26 | always@( posedge clk, negedge r_rst_n) 27 | begin 28 | if(~r_rst_n) 29 | begin 30 | r_shift <= 4'b0; 31 | r_code <= 1'b0; 32 | r_cnt <= 3'b0; 33 | r_crc_done <= 1'b0; 34 | end 35 | else 36 | begin 37 | if( r_cnt < 3'b3 ) 38 | begin 39 | r_shift[3] <= i_data ^ r_shift[0]; 40 | r_shift[2] <= i_data ^ r_shift[0] ^ r_shift[3]; 41 | r_shift[1] <= i_data ^ r_shift[0] ^ r_shift[2]; 42 | r_shift[0] <= r_shift[1]; 43 | 44 | r_cnt <= r_cnt + 3'd1; 45 | r_crc_done <= 1'b0; 46 | //这是初始的3位 47 | r_code <= i_data; 48 | end 49 | else 50 | begin 51 | if(r_cnt == 3'd6)//7位的时候结束 52 | begin 53 | r_cnt <= 3'b0; 54 | r_crc_done <= 1'b1; 55 | end 56 | else 57 | begin 58 | r_cnt <= r_cnt + 3'b1; 59 | r_crc_done <= 1'b0; 60 | end 61 | 62 | r_shift <= {1'b0, r_shift[3:1]}; 63 | r_code <= r_shift[0]; 64 | 65 | end 66 | end 67 | end 68 | 69 | endmodule 70 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # verilog 2 | 3 | pratice about verilog HDL 4 | 5 | reference: https://www.bilibili.com/video/av45427296 6 | 7 | if you want more, go to myblog: https://www.cnblogs.com/friedCoder/category/1641079.html 8 | -------------------------------------------------------------------------------- /coder/coder10to4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module coder10to4 4 | ( 5 | input[9:0] i_data, 6 | output[3:0] o_code 7 | ); 8 | 9 | //定义输出信号o_code的缓存 10 | reg[3:0] r_coder; 11 | 12 | assign o_code = r_coder; 13 | 14 | 15 | always@(*) 16 | begin 17 | case(i_data) 18 | //组合电路使用阻塞语句赋值 19 | 10'b0000000001:r_coder=4'b0001; 20 | 10'b0000000010:r_coder=4'b0010; 21 | 10'b0000000100:r_coder=4'b0011; 22 | 10'b0000001000:r_coder=4'b0100; 23 | 10'b0000010000:r_coder=4'b0101; 24 | 10'b0000100000:r_coder=4'b0110; 25 | 10'b0001000000:r_coder=4'b0111; 26 | 10'b0010000000:r_coder=4'b1000; 27 | 10'b0100000000:r_coder=4'b1001; 28 | 10'b1000000000:r_coder=4'b1010; 29 | default: r_coder=4`b0000;//添加默认分支的赋值，避免产生锁存器 30 | endcase 31 | end 32 | endmodule 33 | -------------------------------------------------------------------------------- /coder/decoder4to10.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module decoder10to4 4 | ( 5 | input[3:0] i_data, 6 | output[9:0] o_decode; 7 | ); 8 | 9 | reg[9:0] r_decode; 10 | assign o_decode = r_decode; 11 | 12 | always@(*) 13 | begin 14 | case(i_data) 15 | 4'b0001:r_decode=10'b0000000001; 16 | 4'b0010:r_decode=10'b0000000010; 17 | 4'b0011:r_decode=10'b0000000100; 18 | 4'b0100:r_decode=10'b0000001000; 19 | 4'b0101:r_decode=10'b0000010000; 20 | 4'b0110:r_decode=10'b0000100000; 21 | 4'b0111:r_decode=10'b0001000000; 22 | 4'b1000:r_decode=10'b0010000000; 23 | 4'b1001:r_decode=10'b0100000000; 24 | 4'b1010:r_decode=10'b1000000000; 25 | default:r_decode=10'b0000000000; 26 | endcase 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /d_latch/d_latch.v: -------------------------------------------------------------------------------- 1 | /* 2 | D锁存器 3 | */ 4 | 5 | `timescale 1ns/1ns 6 | 7 | module d_latch 8 | ( 9 | input i_enable, 10 | input i_d, 11 | 12 | output o_q 13 | ); 14 | 15 | reg r_q; 16 | 17 | assign o_q = r_q; 18 | 19 | always@(i_enable, i_d) //电平敏感 20 | begin 21 | if( 1'b1 == i_enable ) 22 | r_q <= i_d; 23 | end 24 | endmodule 25 | -------------------------------------------------------------------------------- /d_latch/d_latch_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module d_latch_tb; 4 | 5 | reg r_enable; 6 | reg r_d; 7 | 8 | wire w_q; 9 | 10 | 11 | d_latch I_d_latch 12 | ( 13 | .i_enable(r_enable), 14 | .i_d(r_d), 15 | .o_q(w_q) 16 | ); 17 | 18 | initial 19 | begin 20 | r_enable = 1'b0; 21 | forever 22 | #100 r_enable = ~r_enable; 23 | end 24 | 25 | 26 | initial 27 | begin 28 | r_d = 1'b0; 29 | forever 30 | #15 r_d = ~r_d; 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /d_trig/d_trig.v: -------------------------------------------------------------------------------- 1 | /* 2 | D触发器建模 3 | */ 4 | 5 | `timescale 1ns/1ns 6 | 7 | module d_trig 8 | ( 9 | input i_clk, 10 | input i_clr, 11 | input i_enable, 12 | input i_d, 13 | 14 | output o_q 15 | ); 16 | 17 | 18 | reg r_q; 19 | 20 | assign o_q = r_q; 21 | 22 | 23 | always@(posedge i_clk, posedge i_clr)//这里的逗号相当于or 24 | begin 25 | if(1'b1 == i_clr) //同步清零 26 | r_q = 1'b0; 27 | else if( i_enable == 1'b1 )//同步使能 28 | r_q <= i_d; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /d_trig/d_trig_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module d_trig_tb; 4 | 5 | reg r_clk; 6 | reg r_clr; 7 | reg r_enable; 8 | reg r_data; 9 | 10 | wire w_o; 11 | 12 | 13 | d_trig I_d_trig 14 | ( 15 | .i_clk(r_clk), 16 | .i_d(r_data), 17 | .i_clr(r_clr), 18 | .i_enable(r_enable), 19 | .o_q(w_o) 20 | ); 21 | 22 | 23 | initial 24 | begin 25 | r_clk = 1'b0; 26 | forever 27 | #10 r_clk = ~r_clk; 28 | end 29 | 30 | 31 | initial 32 | begin 33 | r_clr = 1'b1; 34 | #15 r_clr = 1'b0; 35 | end 36 | 37 | 38 | initial 39 | begin 40 | r_enable = 1'b1; 41 | #20 r_enable = 1'b0; 42 | #20 r_enable = 1'b1; 43 | end 44 | 45 | 46 | initial 47 | begin 48 | r_data = 1'b0; 49 | 50 | repeat(10) 51 | begin 52 | #2 r_data = 1'b1; 53 | #2 r_data = 1'b0; 54 | #4 r_data = 1'b1; 55 | #4 r_data = 1'b0; 56 | #2 r_data = 1'b1; 57 | end 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /data_encrypt/data_decrypt.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module data_decrypt 4 | ( 5 | input i_rst_n, 6 | input i_clk, 7 | input i_data, 8 | 9 | output o_decode 10 | ); 11 | 12 | 13 | reg[4:0] r_shift; 14 | 15 | assign o_decode = r_shift[0] ^ r_shift[2] ^ i_data; 16 | 17 | 18 | always@(posedge i_clk, negedge i_rst_n) 19 | begin 20 | if(~i_rst_n) 21 | r_shift <= 5'b0; 22 | else 23 | begin 24 | r_shift[3:0] <= r_shift[4:1]; 25 | r_shift[4] <= i_data; 26 | end 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /data_encrypt/data_encrypt.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module data_encrypt 4 | ( 5 | input i_rst_n,//低有效 6 | input i_clk, 7 | 8 | input i_data, 9 | output o_code 10 | ); 11 | 12 | reg[4:0] r_shift; 13 | 14 | assign o_code = r_shift[4]; 15 | 16 | 17 | 18 | always@(negedge i_rst_n, posedge clk ) 19 | begin 20 | if(~i_rst_n) 21 | r_shift <= 5'b0; 22 | else 23 | begin 24 | r_shift[3:0] <= r_shift[4:1]; 25 | r_shift[4] <= r_shift[0] ^ r_shift[2] ^ i_data; 26 | end 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /data_encrypt/data_encrypt_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 2 | 3 | module data_encrypt_tb; 4 | 5 | reg r_clk; 6 | reg r_rst_n; 7 | reg r_data; 8 | 9 | wire w_code; 10 | wire w_data; 11 | 12 | 13 | data_encrypt I_data_encrypt 14 | ( 15 | .i_clk(r_clk), 16 | .i_rst_n( r_rst_n), 17 | .i_data(r_data), 18 | .o_code(w_code) 19 | ); 20 | 21 | data_decrypt I_data_decrypt 22 | ( 23 | .i_clk(r_clk), 24 | .i_rst_n( r_rst_n), 25 | .i_data(w_code), 26 | .o_decode(w_data) 27 | ); 28 | 29 | initial 30 | begin 31 | r_clk = 1'b0; 32 | forever 33 | #1 r_clk = ~r_clk; 34 | end 35 | 36 | 37 | initial 38 | begin 39 | r_rst_n = 1'b0; 40 | #10 r_rst_n = 1'b1; 41 | end 42 | 43 | initial 44 | begin 45 | r_data = 1'b0; 46 | forever 47 | #2 r_data = $random % 2; 48 | end 49 | endmodule 50 | -------------------------------------------------------------------------------- /demux1to4/demux1to4.v: -------------------------------------------------------------------------------- 1 | /* 2 | 数据分配器 3 | 一个输入，4个输出 4 | */ 5 | `timescale 1ns/1ns 6 | 7 | module demux1to4 8 | ( 9 | input i_data, 10 | input[1:0] i_sel, 11 | 12 | output o_a, 13 | output o_b, 14 | output o_c, 15 | output o_d 16 | ); 17 | 18 | reg r_a; 19 | reg r_b; 20 | reg r_c; 21 | reg r_d; 22 | 23 | assign o_a = r_a; 24 | assign o_b = r_b; 25 | assign o_c = r_c; 26 | assign o_d = r_d; 27 | 28 | 29 | 30 | always@(*) 31 | begin 32 | if( i_sel == 2'b00 ) 33 | r_a = i_data; 34 | else 35 | r_a = 1'b0; 36 | end 37 | 38 | 39 | always@(*) 40 | begin 41 | if( i_sel == 2'b01 ) 42 | r_b = i_data; 43 | else 44 | r_b = 1'b0; 45 | end 46 | 47 | 48 | always@(*) 49 | begin 50 | if( i_sel == 2'b10 ) 51 | r_c = i_data; 52 | else 53 | r_c = 1'b0; 54 | end 55 | 56 | 57 | always@(*) 58 | begin 59 | if( i_sel == 2'b11 ) 60 | r_d = i_data; 61 | else 62 | r_d = 1'b0; 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /demux1to4/demux1to4_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module demux1to4_tb; 4 | 5 | reg r_data; 6 | reg[1:0] r_sel; 7 | 8 | wire w_a; 9 | wire w_b; 10 | wire w_c; 11 | wire w_d; 12 | 13 | demux1to4 I_demux1to4 14 | ( 15 | .i_data(r_data), 16 | .i_sel(r_sel), 17 | .o_a(r_a), 18 | .o_b(r_b), 19 | .o_c(r_c), 20 | .o_d(r_d) 21 | ); 22 | 23 | initial 24 | begin 25 | r_data = 1'b0; 26 | repeat(64) 27 | #2 r_data = ~r_data; 28 | end 29 | 30 | 31 | initial 32 | begin 33 | r_sel = 2'd0; 34 | repeat(4) 35 | #32 r_sel = r_sel + 4'd1; 36 | end 37 | 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /digitalTube/seg_display.v: -------------------------------------------------------------------------------- 1 | /* 2 | 七段数码管 3 | 小数点位DP 4 | */ 5 | `timescale 1ns/1ns 6 | 7 | module seg_display 8 | ( 9 | input[3:0] i_data, 10 | input i_dp, 11 | 12 | output[6:0] o_seg, 13 | output o_dp 14 | ); 15 | 16 | reg[6:0] r_seg; 17 | 18 | assign o_seg = r_seg; 19 | 20 | assign o_dp = i_dp; //小数点直接输出 21 | 22 | 23 | always@(*) 24 | begin 25 | //根据7段数码管 显示数字与对应信号关系 来编码 26 | case(i_data) 27 | 4'b0000:r_seg=7'b1111110;//显示数字0 28 | //下面类似，就不写其它情况了 29 | default:r_seg=7'b1111111;//不亮 30 | endcase 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /digitalTube/seg_display_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module seg_display_tb; 4 | 5 | reg[3:0] r_data; 6 | reg r_dp; 7 | 8 | //定义输出信号连线 9 | wire[6:0] w_seg; 10 | wire w_dp; 11 | 12 | 13 | 14 | seg_display I_seg_display 15 | ( 16 | .i_data(r_data), 17 | .i_dp(r_dp), 18 | .o_seg(w_seg), 19 | .o_dp(w_dp) 20 | ); 21 | 22 | 23 | //小数点显示激励信号 24 | initial 25 | begin 26 | r_dp=1'b0; 27 | repeat(8) //执行8次 28 | #4 r_dp = ~r_dp; 29 | end 30 | 31 | 32 | //7段数码显示激励信号 33 | initial 34 | begin 35 | r_data=4'd0; 36 | repeat(16); 37 | #2 r_data = r_data + 4'd1; 38 | end 39 | 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /digitalTube/tags: -------------------------------------------------------------------------------- 1 | !_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ 2 | !_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ 3 | !_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ 4 | !_TAG_PROGRAM_NAME Exuberant Ctags // 5 | !_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ 6 | !_TAG_PROGRAM_VERSION 5.9~svn20110310 // 7 | i_data seg_display.v /^ input[3:0] i_data,$/;" p 8 | input seg_display.v /^ input i_dp,$/;" p 9 | o_seg seg_display.v /^ output[6:0] o_seg,$/;" p 10 | output seg_display.v /^ output o_dp$/;" p 11 | r_data seg_display_tb.v /^ reg[3:0] r_data;$/;" r 12 | r_dp seg_display_tb.v /^ reg r_dp;$/;" r 13 | r_seg seg_display.v /^ reg[6:0] r_seg;$/;" r 14 | seg_display seg_display.v /^module seg_display$/;" m 15 | seg_display_tb seg_display_tb.v /^module seg_display_tb;$/;" m 16 | w_dp seg_display_tb.v /^ wire w_dp;$/;" n 17 | w_seg seg_display_tb.v /^ wire[6:0] w_seg;$/;" n 18 | -------------------------------------------------------------------------------- /gate_construct/gate_construct.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module gate_construct 4 | ( 5 | input i_a, 6 | input i_b, 7 | input i_c, 8 | input i_d, 9 | input i_e, 10 | 11 | output o_y 12 | ); 13 | 14 | //定义门电路之间的连线信号 15 | wire w_and_o; 16 | wire w_or1_o; 17 | wire w_xor_o; 18 | 19 | 20 | //实例化门电路模块 21 | and I_and(w_and_o, i_a, i_b); 22 | or I1_or(w_or1_o, i_c, i_d); 23 | xor I_xor(w_xor_o, w_and_o, w_or1_o ); 24 | or I2_or(o_y, w_xor_o, i_e); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /gate_construct/gate_construct_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module gate_construct_tb; 4 | 5 | reg r_a; 6 | reg r_b; 7 | reg r_c; 8 | reg r_d; 9 | reg r_e; 10 | 11 | reg[4:0] r_cnt; 12 | 13 | //定义输出信号连线 14 | wire w_v; 15 | 16 | //实例化 17 | gate_construct I_gate_construct_tb 18 | ( 19 | .i_a(r_a), 20 | .i_b(r_b), 21 | .i_c(r_c), 22 | .i_d(r_d), 23 | .i_e(r_e) 24 | ); 25 | 26 | 27 | initial 28 | begin 29 | r_cnt = 5'd0; 30 | forever 31 | #2 r_cnt = r_cnt + 5'd1; 32 | end 33 | 34 | always@(r_cnt) 35 | begin 36 | r_a = r_cnt[0]; 37 | r_b = r_cnt[1]; 38 | r_c = r_cnt[2]; 39 | r_d = r_cnt[3]; 40 | r_e = r_cnt[4]; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /jk_tirg/jk_trig.v: -------------------------------------------------------------------------------- 1 | /* 2 | JK触发器 3 | */ 4 | `timescale 1ns/1ns 5 | 6 | module jk_trig 7 | ( 8 | input i_clk, 9 | input i_j, 10 | input i_k, 11 | 12 | output o_q, //JK触发器正输出 13 | output o_qb //JK触发器负输出 14 | 15 | ); 16 | 17 | //模块内的r_q是没有初始值的 18 | reg r_q; 19 | 20 | assign o_q = r_q; 21 | assign o_qb = ~r_q; 22 | 23 | 24 | always@(posedge clk) 25 | begin 26 | case({i_j, i_k}) 27 | 2'b00: r_q <= r_q; 28 | 2'b01: r_q <= 1'b0; 29 | 2'b10: r_q <= 1'b1; 30 | 2'b11: r_q <= ~r_q; 31 | default: r_q <= r_q; 32 | endcase 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /jk_tirg/jk_trig_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module jk_trig_tb; 4 | 5 | reg r_clk; 6 | reg[1:0] r_cnt; 7 | 8 | wire w_q; 9 | wire w_qb; 10 | 11 | 12 | jk_trig I_jk_trig 13 | ( 14 | .i_k(r_k[1]), 15 | .i_j(r_j[0]), 16 | .i_clk(r_clk), 17 | .o_qb(w_qb), 18 | .o_q(w_q) 19 | ); 20 | 21 | initial 22 | begin 23 | r_clk = 1'd0; 24 | forever 25 | #10 r_clk = ~r_clk; 26 | end 27 | 28 | 29 | initial 30 | begin 31 | r_cnt = 2'd0; 32 | forever 33 | #20 r_cnt = r_cnt + 2'd1; 34 | 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /mux4to1/mux4to1.v: -------------------------------------------------------------------------------- 1 | /* 2 | 4选1的数据选择器 3 | */ 4 | 5 | `timescale 1ns/1ns 6 | 7 | module mux4to1 8 | ( 9 | input i_a, 10 | input i_b, 11 | input i_c, 12 | input i_d, 13 | 14 | input[1:0] i_sel, //2位的选择信号 15 | 16 | output o_data 17 | ); 18 | 19 | reg r_data; 20 | 21 | assign o_data = r_data; 22 | 23 | 24 | always@(*) 25 | begin 26 | case(i_sel) 27 | 2'b00: r_data = i_a; 28 | 2'b01: r_data = i_b; 29 | 2'b10: r_data = i_c; 30 | 2'b11: r_data = i_d; 31 | default:r_data = 1'b0; //其它情况输出0 32 | endcase 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /mux4to1/mux4to1_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module mux4to1_tb; 4 | 5 | //定义激励源 6 | reg[3:0] r_cnt; 7 | reg[1:0] r_sel; 8 | 9 | wire w_data; 10 | 11 | 12 | mux4to1 I_mux4to1 13 | ( 14 | .i_a(r_cnt[0]), 15 | .i_b(r_cnt[1]), 16 | .i_c(r_cnt[2]), 17 | .i_d(r_cnt[3]), 18 | .i_sel(r_sel), 19 | .o_data(w_data) 20 | ); 21 | 22 | 23 | initial 24 | begin 25 | r_cnt = 4'd0; 26 | repeat(64) 27 | #2 r_cnt = r_cnt + 4'd1; 28 | end 29 | 30 | 31 | initial 32 | begin 33 | r_sel = 2'd0; 34 | repeat(4) 35 | #32 r_sel = r_sel + 4'd1; 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /simpleExample/counter.v: -------------------------------------------------------------------------------- 1 | module counter(q, cout, reset, cin, clk); 2 | parameter N = 4; 3 | 4 | input reset, cin, clk; 5 | output cout; 6 | output[N:1] q; 7 | reg[N:1] q; 8 | 9 | always @(posedge clk) 10 | begin 11 | if(reset) q<=0; 12 | else 13 | q<=q+cin; 14 | end 15 | 16 | assign cout=&q && cin; 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /simpleExample/function.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ns 2 | 3 | module function_app(); 4 | parameter N = 15; 5 | parameter M = 4; 6 | 7 | reg[N:0] data_one; 8 | reg[N:0] data_two; 9 | reg[M:0] num_one; 10 | reg[M:0] num_two; 11 | 12 | task cal_num_one; 13 | input[N:0] data; 14 | output[M:0] num_one; 15 | 16 | integer i, j; 17 | begin 18 | i = 0; 19 | for(j=0; j