├── LICENSE ├── README.md ├── board_files ├── redpitaya-125-14-z20 │ └── 1.0 │ │ ├── board.xml │ │ └── preset.xml └── redpitaya-125-14 │ └── 1.0 │ ├── board.xml │ └── preset.xml ├── doc ├── DMA-transfer │ ├── MM2S_S2MM.PNG │ ├── acq.png │ ├── all_ports.PNG │ ├── assign_address.PNG │ ├── axi_dma.PNG │ ├── axi_interconnect.PNG │ ├── block_automation.PNG │ ├── clk.PNG │ ├── connection_automation.PNG │ ├── final_design.PNG │ ├── gpio.PNG │ ├── stream_ctrl.PNG │ └── zynq.PNG ├── LED-blink │ ├── LED_blink.gif │ ├── addConstraints.PNG │ ├── addModule.PNG │ ├── addSourceVivado.PNG │ ├── addSources.PNG │ ├── axiGpio.PNG │ ├── bitstreamCompleted.PNG │ ├── blockAutomation.PNG │ ├── concat.PNG │ ├── connectionAutomation.PNG │ ├── counterVhd.PNG │ ├── createBlockDesign.PNG │ ├── createPort.PNG │ ├── defaultPart.PNG │ ├── defineModule.PNG │ ├── fullDesign.PNG │ ├── hdlWrapper.PNG │ ├── ledSdc.PNG │ ├── newProject.PNG │ ├── newSource.PNG │ ├── projectSummary.PNG │ ├── projectType.PNG │ ├── slice.PNG │ ├── startVivado.PNG │ ├── zynqGpio_1.PNG │ ├── zynqGpio_2.PNG │ └── zynqPLClk.PNG ├── Setting-up-your-system │ ├── customTclCommand.PNG │ ├── tclButton.png │ └── welcome.png ├── Zynq-architecture-&-Redpitaya-125-14 │ └── Redpitaya.png ├── analog-echo │ ├── add_ip.PNG │ ├── add_offset_ctrl.PNG │ ├── all_ports.PNG │ ├── axi_gpio.PNG │ ├── connect_clk.PNG │ ├── create_port.png │ ├── final_design.PNG │ ├── hdl_wrapper.png │ ├── offset_ctrl.PNG │ └── scope.png ├── behavioural-simulation │ ├── create_tb_0.PNG │ ├── create_tb_1.PNG │ ├── run_sim.png │ ├── run_sim_tb.png │ ├── set_top.png │ ├── set_top_tb.png │ ├── start_sim_tb.png │ └── start_sim_tcl.png └── datasheet │ ├── DAC1401D125.pdf │ └── LTC2145.pdf ├── hdl ├── amplitude_ctrl.v ├── amplitude_ctrl.vhd ├── assignments │ ├── dds │ │ ├── dds_compiler_0.xci │ │ ├── dds_wrapper.v │ │ └── dds_wrapper.vhd │ ├── pwm.v │ ├── pwm.vhd │ ├── stream_dec.v │ ├── stream_dec.vhd │ ├── test_wave.v │ └── test_wave.vhd ├── counter.v ├── counter.vhd ├── offset_ctrl.v ├── offset_ctrl.vhd ├── stream_adder.v ├── stream_adder.vhd ├── stream_ctrl.v ├── stream_ctrl.vhd ├── stream_multiplier.v └── stream_multiplier.vhd ├── ip ├── AXI4-register-bank │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── axi_reg_v1_0 │ │ │ ├── data │ │ │ ├── axi_reg.mdd │ │ │ └── axi_reg.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── axi_reg.c │ │ │ ├── axi_reg.h │ │ │ └── axi_reg_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── axi_reg_v1_0_tb.sv │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── axi_reg_v1_0_hw_test.tcl │ │ │ └── design.tcl │ ├── gui │ │ └── axi_reg_v1_0.gtcl │ ├── hdl │ │ ├── axi_reg_v1_0.v │ │ └── axi_reg_v1_0_S00_AXI.v │ └── xgui │ │ └── reg_bank_v1_0.tcl ├── Redpitaya-125-14-adc │ ├── component.xml │ ├── sim │ │ ├── adc_bd.vhd │ │ └── adc_bd_ADC_0_1.vhd │ ├── src │ │ ├── ADC.vhd │ │ ├── adc_bd.vhd │ │ ├── adc_bd_ADC_0_1.vhd │ │ └── adc_bd_ooc.xdc │ └── xgui │ │ ├── adc_bd_v1_0.tcl │ │ └── adc_v1_0.tcl ├── Redpitaya-125-14-clk │ ├── component.xml │ ├── sim │ │ ├── clk_bd.vhd │ │ ├── clk_bd_clockStabilization_0_0.vhd │ │ └── clk_bd_not_gate_0_0.vhd │ ├── src │ │ ├── clk_bd.vhd │ │ ├── clk_bd_clk_wiz_0_0 │ │ │ ├── clk_bd_clk_wiz_0_0.xci │ │ │ └── clk_bd_clk_wiz_0_0.xml │ │ ├── clk_bd_clockStabilization_0_0.vhd │ │ ├── clk_bd_not_gate_0_0.vhd │ │ ├── clk_bd_ooc.xdc │ │ ├── clk_bd_proc_sys_reset_0_0 │ │ │ ├── clk_bd_proc_sys_reset_0_0.xci │ │ │ └── clk_bd_proc_sys_reset_0_0.xml │ │ ├── clk_bd_xlconstant_0_0 │ │ │ ├── clk_bd_xlconstant_0_0.xci │ │ │ └── clk_bd_xlconstant_0_0.xml │ │ ├── clk_bd_xlconstant_1_0 │ │ │ ├── clk_bd_xlconstant_1_0.xci │ │ │ └── clk_bd_xlconstant_1_0.xml │ │ ├── clockStabilization.vhd │ │ └── not_gate.vhd │ └── xgui │ │ ├── clk_bd_v1_0.tcl │ │ └── clk_v1_0.tcl └── Redpitaya-125-14-dac │ ├── component.xml │ ├── sim │ ├── dac_bd.vhd │ └── dac_bd_DAC_0_0.vhd │ ├── src │ ├── DAC.vhd │ ├── dac_bd.vhd │ ├── dac_bd_DAC_0_0.vhd │ └── dac_bd_ooc.xdc │ └── xgui │ ├── dac_bd_v1_0.tcl │ └── dac_v1_0.tcl ├── jupyter_notebooks ├── DMA_transfer.ipynb ├── LED_blink.ipynb └── analog_echo.ipynb ├── sdc └── redpitaya-125-14.xdc ├── sim ├── sim_counter.tcl ├── tb_counter.v └── tb_counter.vhd ├── sys ├── README.md ├── config_display.sh ├── config_wg.sh ├── config_xilinx_0.sh ├── config_xilinx_1.sh ├── config_xrdp.sh └── resources │ ├── boot │ └── boot.py │ ├── wg │ ├── client │ │ └── wg0.conf │ └── server │ │ └── wg0.conf │ └── xrdp │ └── xrdp-installer-1.4.6.sh └── tcl ├── upload_overlay.tcl └── write_project.tcl /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Pau Gómez 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA Notes for Scientists 2 | This repository is a collection of hands-on FPGA programming projects for scientists without (or very basic) experience in FPGA programming. The intend is to provide simple, functional and open-source examples, which incrementally incorporate new FPGA programming concepts. 3 | 4 | 5 | 6 | ## Table of contents 7 | * [Introduction](../../wiki/Introduction) 8 | * [Setting up your system (Local)](../../wiki/Setting-up-your-system) 9 | * [Setting up your system (Remote Development Servers)](../../wiki/Setting-up-your-system-(Remote-Development-Servers)) 10 | * [Redpitaya & Zynq architecture](../../wiki/Redpitaya-&-Zynq-architecture) 11 | * Tutorials: 12 | * [LED blink](../../wiki/LED-blink) 13 | * [Behavioral simulation](../../wiki/Behavioral-simulation) 14 | * [Analog echo](../../wiki/Analog-echo) 15 | * [DMA transfer](../../wiki/DMA-transfer) 16 | * [Assignments](../../wiki/Assignments) 17 | *** 18 | 19 | :information_source: Feedback, questions and proposals for new tutorials are very welcome and collected [here](https://github.com/dspsandbox/FPGA-Lectures-for-Scientists/issues). 20 | 21 | *** 22 | -------------------------------------------------------------------------------- /board_files/redpitaya-125-14-z20/1.0/board.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 1.0 4 | Redpitaya-125-14-z20 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /board_files/redpitaya-125-14/1.0/board.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 1.0 4 | Redpitaya-125-14 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /doc/DMA-transfer/MM2S_S2MM.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/MM2S_S2MM.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/acq.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/acq.png -------------------------------------------------------------------------------- /doc/DMA-transfer/all_ports.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/all_ports.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/assign_address.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/assign_address.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/axi_dma.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/axi_dma.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/axi_interconnect.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/axi_interconnect.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/block_automation.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/block_automation.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/clk.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/clk.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/connection_automation.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/connection_automation.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/final_design.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/final_design.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/gpio.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/gpio.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/stream_ctrl.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/stream_ctrl.PNG -------------------------------------------------------------------------------- /doc/DMA-transfer/zynq.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/DMA-transfer/zynq.PNG -------------------------------------------------------------------------------- /doc/LED-blink/LED_blink.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/LED_blink.gif -------------------------------------------------------------------------------- /doc/LED-blink/addConstraints.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/addConstraints.PNG -------------------------------------------------------------------------------- /doc/LED-blink/addModule.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/addModule.PNG -------------------------------------------------------------------------------- /doc/LED-blink/addSourceVivado.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/addSourceVivado.PNG -------------------------------------------------------------------------------- /doc/LED-blink/addSources.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/addSources.PNG -------------------------------------------------------------------------------- /doc/LED-blink/axiGpio.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/axiGpio.PNG -------------------------------------------------------------------------------- /doc/LED-blink/bitstreamCompleted.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/bitstreamCompleted.PNG -------------------------------------------------------------------------------- /doc/LED-blink/blockAutomation.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/blockAutomation.PNG -------------------------------------------------------------------------------- /doc/LED-blink/concat.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/concat.PNG -------------------------------------------------------------------------------- /doc/LED-blink/connectionAutomation.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/connectionAutomation.PNG -------------------------------------------------------------------------------- /doc/LED-blink/counterVhd.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/counterVhd.PNG -------------------------------------------------------------------------------- /doc/LED-blink/createBlockDesign.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/createBlockDesign.PNG -------------------------------------------------------------------------------- /doc/LED-blink/createPort.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/createPort.PNG -------------------------------------------------------------------------------- /doc/LED-blink/defaultPart.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/defaultPart.PNG -------------------------------------------------------------------------------- /doc/LED-blink/defineModule.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/defineModule.PNG -------------------------------------------------------------------------------- /doc/LED-blink/fullDesign.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/fullDesign.PNG -------------------------------------------------------------------------------- /doc/LED-blink/hdlWrapper.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/hdlWrapper.PNG -------------------------------------------------------------------------------- /doc/LED-blink/ledSdc.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/ledSdc.PNG -------------------------------------------------------------------------------- /doc/LED-blink/newProject.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/newProject.PNG -------------------------------------------------------------------------------- /doc/LED-blink/newSource.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/newSource.PNG -------------------------------------------------------------------------------- /doc/LED-blink/projectSummary.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/projectSummary.PNG -------------------------------------------------------------------------------- /doc/LED-blink/projectType.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/projectType.PNG -------------------------------------------------------------------------------- /doc/LED-blink/slice.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/slice.PNG -------------------------------------------------------------------------------- /doc/LED-blink/startVivado.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/startVivado.PNG -------------------------------------------------------------------------------- /doc/LED-blink/zynqGpio_1.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/zynqGpio_1.PNG -------------------------------------------------------------------------------- /doc/LED-blink/zynqGpio_2.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/zynqGpio_2.PNG -------------------------------------------------------------------------------- /doc/LED-blink/zynqPLClk.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/LED-blink/zynqPLClk.PNG -------------------------------------------------------------------------------- /doc/Setting-up-your-system/customTclCommand.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/Setting-up-your-system/customTclCommand.PNG -------------------------------------------------------------------------------- /doc/Setting-up-your-system/tclButton.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/Setting-up-your-system/tclButton.png -------------------------------------------------------------------------------- /doc/Setting-up-your-system/welcome.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/Setting-up-your-system/welcome.png -------------------------------------------------------------------------------- /doc/Zynq-architecture-&-Redpitaya-125-14/Redpitaya.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/Zynq-architecture-&-Redpitaya-125-14/Redpitaya.png -------------------------------------------------------------------------------- /doc/analog-echo/add_ip.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/add_ip.PNG -------------------------------------------------------------------------------- /doc/analog-echo/add_offset_ctrl.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/add_offset_ctrl.PNG -------------------------------------------------------------------------------- /doc/analog-echo/all_ports.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/all_ports.PNG -------------------------------------------------------------------------------- /doc/analog-echo/axi_gpio.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/axi_gpio.PNG -------------------------------------------------------------------------------- /doc/analog-echo/connect_clk.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/connect_clk.PNG -------------------------------------------------------------------------------- /doc/analog-echo/create_port.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/create_port.png -------------------------------------------------------------------------------- /doc/analog-echo/final_design.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/final_design.PNG -------------------------------------------------------------------------------- /doc/analog-echo/hdl_wrapper.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/hdl_wrapper.png -------------------------------------------------------------------------------- /doc/analog-echo/offset_ctrl.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/offset_ctrl.PNG -------------------------------------------------------------------------------- /doc/analog-echo/scope.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/analog-echo/scope.png -------------------------------------------------------------------------------- /doc/behavioural-simulation/create_tb_0.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/create_tb_0.PNG -------------------------------------------------------------------------------- /doc/behavioural-simulation/create_tb_1.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/create_tb_1.PNG -------------------------------------------------------------------------------- /doc/behavioural-simulation/run_sim.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/run_sim.png -------------------------------------------------------------------------------- /doc/behavioural-simulation/run_sim_tb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/run_sim_tb.png -------------------------------------------------------------------------------- /doc/behavioural-simulation/set_top.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/set_top.png -------------------------------------------------------------------------------- /doc/behavioural-simulation/set_top_tb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/set_top_tb.png -------------------------------------------------------------------------------- /doc/behavioural-simulation/start_sim_tb.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/start_sim_tb.png -------------------------------------------------------------------------------- /doc/behavioural-simulation/start_sim_tcl.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/behavioural-simulation/start_sim_tcl.png -------------------------------------------------------------------------------- /doc/datasheet/DAC1401D125.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/datasheet/DAC1401D125.pdf -------------------------------------------------------------------------------- /doc/datasheet/LTC2145.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dspsandbox/FPGA-Notes-for-Scientists/1f0b43a3957e8aafc15f31dbc803db5906b6fd3f/doc/datasheet/LTC2145.pdf -------------------------------------------------------------------------------- /hdl/amplitude_ctrl.v: -------------------------------------------------------------------------------- 1 | module amplitude_ctrl #( 2 | parameter DATA_WIDTH = 16 3 | )( 4 | input clk, 5 | input resetn, 6 | input signed [DATA_WIDTH - 1 : 0] amplitude, 7 | input signed [DATA_WIDTH - 1 : 0] data_i_tdata, 8 | input data_i_tvalid, 9 | output signed [DATA_WIDTH - 1 : 0] data_o_tdata, 10 | output reg data_o_tvalid 11 | ); 12 | reg signed [2 * DATA_WIDTH - 1 : 0] mult_reg; 13 | 14 | always @(posedge clk) begin 15 | if(resetn == 0) begin 16 | mult_reg <= 0; 17 | data_o_tvalid <= 0; 18 | end else begin 19 | mult_reg <= data_i_tdata * amplitude; 20 | data_o_tvalid <= data_i_tvalid; 21 | end 22 | end 23 | 24 | assign data_o_tdata = mult_reg[2 * DATA_WIDTH - 2 : DATA_WIDTH - 1]; 25 | 26 | endmodule -------------------------------------------------------------------------------- /hdl/amplitude_ctrl.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | 7 | entity amplitude_ctrl is 8 | Generic (DATA_WIDTH : integer := 16); 9 | Port ( clk : in STD_LOGIC; 10 | resetn : in STD_LOGIC; 11 | amplitude : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 12 | data_i_tdata : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 13 | data_i_tvalid : in STD_LOGIC; 14 | data_o_tdata : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 15 | data_o_tvalid : out STD_LOGIC); 16 | end amplitude_ctrl; 17 | 18 | architecture Behavioral of amplitude_ctrl is 19 | signal mult_reg : signed(2*DATA_WIDTH - 1 downto 0) := (others => '0'); 20 | signal valid_reg : std_logic := '0'; 21 | 22 | begin 23 | process(clk) 24 | begin 25 | if rising_edge(clk) then 26 | if resetn = '0' then 27 | mult_reg <= (others => '0'); 28 | valid_reg <= '0'; 29 | else 30 | mult_reg <= signed(data_i_tdata) * signed(amplitude); 31 | valid_reg <= data_i_tvalid; 32 | end if; 33 | end if; 34 | end process; 35 | 36 | data_o_tvalid <= valid_reg; 37 | data_o_tdata <= std_logic_vector(mult_reg(2 * DATA_WIDTH - 2 downto DATA_WIDTH - 1)); 38 | 39 | 40 | end Behavioral; 41 | -------------------------------------------------------------------------------- /hdl/assignments/dds/dds_wrapper.v: -------------------------------------------------------------------------------- 1 | module dds_wrapper( 2 | input clk, 3 | input [31 : 0] phase_off, 4 | input [31 : 0] phase_inc, 5 | input phase_clr, 6 | output signed [15 : 0] sin_tdata, 7 | output sin_tvalid, 8 | output signed [15 : 0] cos_tdata, 9 | output cos_tvalid 10 | ); 11 | 12 | 13 | wire [71 : 0] dds_i; 14 | wire [31 : 0] dds_o; 15 | 16 | dds_compiler_0 dds_compiler_0_instance ( 17 | .aclk(clk), 18 | .s_axis_phase_tvalid(1), 19 | .s_axis_phase_tdata(dds_i), 20 | .m_axis_data_tdata(dds_o) 21 | ); 22 | 23 | assign dds_i[31 : 0] = phase_inc; 24 | assign dds_i[63 : 32] = phase_off; 25 | assign dds_i[64] = phase_clr; 26 | assign dds_i[71 : 65] = 0; 27 | 28 | assign cos_tdata = dds_o[15 : 0]; 29 | assign cos_tvalid = 1; 30 | assign sin_tdata = dds_o[31 : 16]; 31 | assign sin_tvalid = 1; 32 | endmodule 33 | -------------------------------------------------------------------------------- /hdl/assignments/dds/dds_wrapper.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | entity dds_wrapper is 6 | Port ( 7 | clk : in STD_LOGIC; 8 | phase_off : in STD_LOGIC_VECTOR(31 downto 0); -- phase offset 9 | phase_inc : in STD_LOGIC_VECTOR(31 downto 0); -- phase increment 10 | phase_clr : in STD_LOGIC; -- clear phase 11 | sin_tdata : out STD_LOGIC_VECTOR(15 downto 0); 12 | sin_tvalid : out STD_LOGIC; 13 | cos_tdata : out STD_LOGIC_VECTOR(15 downto 0); 14 | cos_tvalid : out STD_LOGIC 15 | ); 16 | end dds_wrapper; 17 | 18 | 19 | architecture Behavioral of dds_wrapper is 20 | 21 | signal dds_i : STD_LOGIC_VECTOR(71 DOWNTO 0); 22 | signal dds_o : STD_LOGIC_VECTOR(31 DOWNTO 0); 23 | 24 | COMPONENT dds_compiler_0 25 | PORT ( 26 | aclk : IN STD_LOGIC; 27 | s_axis_phase_tvalid : IN STD_LOGIC; 28 | s_axis_phase_tdata : IN STD_LOGIC_VECTOR(71 DOWNTO 0); 29 | m_axis_data_tvalid : OUT STD_LOGIC; 30 | m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 31 | ); 32 | END COMPONENT; 33 | 34 | begin 35 | dds_instance : dds_compiler_0 36 | PORT MAP ( 37 | aclk => clk, 38 | s_axis_phase_tvalid => '1', 39 | s_axis_phase_tdata => dds_i, 40 | m_axis_data_tdata => dds_o 41 | ); 42 | 43 | dds_i(31 downto 0) <= phase_inc; 44 | dds_i(63 downto 32) <= phase_off; 45 | dds_i(64) <= phase_clr; 46 | dds_i(71 downto 65) <= (others => '0'); 47 | 48 | cos_tdata <= dds_o(15 downto 0); 49 | cos_tvalid <= '1'; 50 | sin_tdata <= dds_o(31 downto 16); 51 | sin_tvalid <= '1'; 52 | end Behavioral; 53 | -------------------------------------------------------------------------------- /hdl/assignments/pwm.v: -------------------------------------------------------------------------------- 1 | module pwm ( 2 | input clk, 3 | input resetn, 4 | input [31 : 0] incr_i, 5 | input [31 : 0] duty_cycle_i, 6 | output pwm_o 7 | ); 8 | 9 | reg [31 : 0] counter_reg; 10 | 11 | always @(posedge clk) begin 12 | if(resetn == 0) begin 13 | counter_reg <= 0; 14 | end else begin 15 | counter_reg <= counter_reg + incr_i; 16 | end 17 | end 18 | 19 | assign pwm_o = (counter_reg < duty_cycle_i) ? 1 : 0; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /hdl/assignments/pwm.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | entity pwm is 7 | Port ( clk : in STD_LOGIC; 8 | resetn : in STD_LOGIC; 9 | incr_i : in STD_LOGIC_VECTOR (31 downto 0); 10 | duty_cycle_i : in STD_LOGIC_VECTOR (31 downto 0); 11 | pwm_o : out STD_LOGIC); 12 | end pwm; 13 | 14 | 15 | architecture Behavioral of pwm is 16 | signal counter_reg : UNSIGNED (31 downto 0) := (others => '0'); 17 | begin 18 | process(clk) 19 | begin 20 | if rising_edge(clk) then 21 | if resetn = '0' then 22 | counter_reg <= (others => '0'); 23 | else 24 | counter_reg <= counter_reg + UNSIGNED(incr_i); 25 | end if; 26 | end if; 27 | end process; 28 | 29 | pwm_o <= '1' when counter_reg < UNSIGNED(duty_cycle_i) else 30 | '0'; 31 | end Behavioral; 32 | -------------------------------------------------------------------------------- /hdl/assignments/stream_dec.v: -------------------------------------------------------------------------------- 1 | module stream_dec #( 2 | parameter DATA_WIDTH = 16 3 | )( 4 | input clk, 5 | input resetn, 6 | input [31 : 0] dec, 7 | input [DATA_WIDTH - 1 : 0] stream_i_tdata, 8 | input stream_i_tvalid, 9 | output stream_i_tready, 10 | output [DATA_WIDTH - 1 : 0] stream_o_tdata, 11 | output stream_o_tvalid, 12 | input stream_o_tready 13 | ); 14 | 15 | reg [31 : 0] counter; 16 | 17 | always @(posedge clk) begin 18 | if(resetn == 0) begin 19 | counter <= 1; 20 | end else begin 21 | if(counter < dec) begin 22 | counter <= counter + 1; 23 | end else begin 24 | counter <= 1; 25 | end 26 | end 27 | end 28 | 29 | assign stream_o_tdata = stream_i_tdata; 30 | 31 | assign stream_o_tvalid = (counter == 1) ? stream_i_tvalid : 0; 32 | 33 | assign stream_i_tready = (counter == 1) ? stream_o_tready : 0; 34 | 35 | endmodule 36 | 37 | -------------------------------------------------------------------------------- /hdl/assignments/stream_dec.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | entity stream_dec is 7 | Generic( data_width : integer := 16); 8 | Port ( clk : in STD_LOGIC; 9 | resetn : in STD_LOGIC; 10 | dec : in STD_LOGIC_VECTOR(31 downto 0); 11 | stream_i_tdata : in STD_LOGIC_VECTOR(data_width - 1 downto 0); 12 | stream_i_tvalid : in STD_LOGIC; 13 | stream_i_tready : out STD_LOGIC; 14 | stream_o_tdata: out STD_LOGIC_VECTOR(data_width - 1 downto 0); 15 | stream_o_tvalid : out STD_LOGIC; 16 | stream_o_tready : in STD_LOGIC 17 | 18 | ); 19 | end stream_dec; 20 | 21 | architecture Behavioral of stream_dec is 22 | signal counter : UNSIGNED(31 downto 0) := (others => '0'); 23 | 24 | begin 25 | process(clk) 26 | begin 27 | if rising_edge(clk) then 28 | if resetn='0' then 29 | counter <= to_unsigned(1, counter'length); 30 | else 31 | if counter < unsigned(dec) then 32 | counter <= counter + 1; 33 | else 34 | counter <= to_unsigned(1, counter'length); 35 | end if; 36 | end if; 37 | end if; 38 | end process; 39 | 40 | stream_o_tdata <= stream_i_tdata; 41 | 42 | stream_o_tvalid <= stream_i_tvalid when (counter = 1) else 43 | '0'; 44 | 45 | stream_i_tready <= stream_o_tready when (counter = 1) else 46 | '0'; 47 | 48 | end Behavioral; 49 | 50 | -------------------------------------------------------------------------------- /hdl/assignments/test_wave.v: -------------------------------------------------------------------------------- 1 | module test_wave ( 2 | input clk, 3 | input resetn, 4 | output reg signed [15 : 0] waveform_tdata, 5 | output reg waveform_tvalid 6 | ); 7 | 8 | always @(posedge clk) begin 9 | if(resetn == 0) begin 10 | waveform_tdata <= 0; 11 | waveform_tvalid <= 0; 12 | end else begin 13 | waveform_tdata <= waveform_tdata + 1; 14 | waveform_tvalid <= 1; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /hdl/assignments/test_wave.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | 4 | -- Uncomment the following library declaration if using 5 | -- arithmetic functions with Signed or Unsigned values 6 | use IEEE.NUMERIC_STD.ALL; 7 | 8 | -- Uncomment the following library declaration if instantiating 9 | -- any Xilinx leaf cells in this code. 10 | --library UNISIM; 11 | --use UNISIM.VComponents.all; 12 | 13 | entity test_wave is 14 | Port ( 15 | clk : in STD_LOGIC; 16 | resetn : in STD_LOGIC; 17 | waveform_tdata : out STD_LOGIC_VECTOR(15 downto 0); 18 | waveform_tvalid : out STD_LOGIC 19 | ); 20 | end test_wave; 21 | 22 | architecture Behavioral of test_wave is 23 | signal counter_reg : unsigned (15 downto 0) := (others => '0'); 24 | begin 25 | process(clk) 26 | begin 27 | if rising_edge(clk) then 28 | if resetn='0' then 29 | counter_reg <= (others => '0'); 30 | else 31 | counter_reg <= counter_reg + 1; 32 | end if; 33 | end if; 34 | 35 | end process; 36 | 37 | 38 | waveform_tdata <= std_logic_vector(counter_reg); 39 | waveform_tvalid <= '1'; 40 | 41 | end Behavioral; 42 | -------------------------------------------------------------------------------- /hdl/counter.v: -------------------------------------------------------------------------------- 1 | module counter ( 2 | input clk, 3 | input resetn, 4 | input [31 : 0] incr_i, 5 | output reg [31 : 0] counter_o 6 | ); 7 | 8 | always @(posedge clk) begin 9 | if(resetn == 0) begin 10 | counter_o <= 0; 11 | end else begin 12 | counter_o <= counter_o + incr_i; 13 | end 14 | end 15 | 16 | endmodule -------------------------------------------------------------------------------- /hdl/counter.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | entity counter is 7 | Port ( clk : in STD_LOGIC; 8 | resetn : in STD_LOGIC; 9 | incr_i : in STD_LOGIC_VECTOR (31 downto 0); 10 | counter_o : out STD_LOGIC_VECTOR (31 downto 0)); 11 | end counter; 12 | 13 | 14 | architecture Behavioral of counter is 15 | signal counter_reg : UNSIGNED (31 downto 0) := (others => '0'); 16 | begin 17 | process(clk) 18 | begin 19 | if rising_edge(clk) then 20 | if resetn = '0' then 21 | counter_reg <= (others => '0'); 22 | else 23 | counter_reg <= counter_reg + UNSIGNED(incr_i); 24 | end if; 25 | end if; 26 | end process; 27 | 28 | counter_o <= STD_LOGIC_VECTOR(counter_reg); 29 | end Behavioral; 30 | -------------------------------------------------------------------------------- /hdl/offset_ctrl.v: -------------------------------------------------------------------------------- 1 | module offset_ctrl #( 2 | parameter DATA_WIDTH = 16 3 | )( 4 | input clk, 5 | input resetn, 6 | input signed [DATA_WIDTH - 1 : 0] offset, 7 | input signed [DATA_WIDTH - 1 : 0] data_i_tdata, 8 | input data_i_tvalid, 9 | output reg signed [DATA_WIDTH - 1 : 0] data_o_tdata, 10 | output reg data_o_tvalid 11 | ); 12 | 13 | always @(posedge clk) begin 14 | if(resetn == 0) begin 15 | data_o_tdata <= 0; 16 | data_o_tvalid <= 0; 17 | end else begin 18 | data_o_tdata <= data_i_tdata + offset; 19 | data_o_tvalid <= data_i_tvalid; 20 | end 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /hdl/offset_ctrl.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | 7 | entity offset_ctrl is 8 | Generic (DATA_WIDTH : integer := 16); 9 | Port ( clk : in STD_LOGIC; 10 | resetn : in STD_LOGIC; 11 | offset : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 12 | data_i_tdata : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 13 | data_i_tvalid : in STD_LOGIC; 14 | data_o_tdata : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 15 | data_o_tvalid : out STD_LOGIC); 16 | end offset_ctrl; 17 | 18 | architecture Behavioral of offset_ctrl is 19 | signal sum_reg : signed(DATA_WIDTH - 1 downto 0) := (others => '0'); 20 | signal valid_reg : std_logic := '0'; 21 | 22 | begin 23 | process(clk) 24 | begin 25 | if rising_edge(clk) then 26 | if resetn = '0' then 27 | sum_reg <= (others => '0'); 28 | valid_reg <= '0'; 29 | else 30 | sum_reg <= signed(data_i_tdata) + signed(offset); 31 | valid_reg <= data_i_tvalid; 32 | end if; 33 | end if; 34 | end process; 35 | 36 | data_o_tvalid <= valid_reg; 37 | data_o_tdata <= std_logic_vector(sum_reg); 38 | 39 | 40 | end Behavioral; 41 | -------------------------------------------------------------------------------- /hdl/stream_adder.v: -------------------------------------------------------------------------------- 1 | module stream_adder #( 2 | parameter DATA_WIDTH = 16 3 | )( 4 | input clk, 5 | input resetn, 6 | input signed [DATA_WIDTH - 1 : 0] data_0_i_tdata, 7 | input data_0_i_tvalid, 8 | input signed [DATA_WIDTH - 1 : 0] data_1_i_tdata, 9 | input data_1_i_tvalid, 10 | output reg signed [DATA_WIDTH - 1 : 0] data_o_tdata, 11 | output reg data_o_tvalid 12 | ); 13 | 14 | always @(posedge clk) begin 15 | if(resetn == 0) begin 16 | data_o_tdata <= 0; 17 | data_o_tvalid <= 0; 18 | end else begin 19 | data_o_tdata <= data_0_i_tdata + data_1_i_tdata; 20 | data_o_tvalid <= data_0_i_tvalid & data_1_i_tvalid; 21 | end 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /hdl/stream_adder.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | 7 | entity stream_adder is 8 | Generic (DATA_WIDTH : integer := 16); 9 | Port ( clk : in STD_LOGIC; 10 | resetn : in STD_LOGIC; 11 | data_0_i_tdata : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 12 | data_0_i_tvalid : in STD_LOGIC; 13 | data_1_i_tdata : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 14 | data_1_i_tvalid : in STD_LOGIC; 15 | data_o_tdata : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 16 | data_o_tvalid : out STD_LOGIC); 17 | end stream_adder; 18 | 19 | architecture Behavioral of stream_adder is 20 | signal sum_reg : signed(DATA_WIDTH - 1 downto 0) := (others => '0'); 21 | signal valid_reg : std_logic := '0'; 22 | 23 | begin 24 | process(clk) 25 | begin 26 | if rising_edge(clk) then 27 | if resetn = '0' then 28 | sum_reg <= (others => '0'); 29 | valid_reg <= '0'; 30 | else 31 | sum_reg <= signed(data_0_i_tdata) + signed(data_1_i_tdata); 32 | valid_reg <= data_0_i_tvalid and data_1_i_tvalid; 33 | end if; 34 | end if; 35 | end process; 36 | 37 | data_o_tvalid <= valid_reg; 38 | data_o_tdata <= std_logic_vector(sum_reg); 39 | 40 | 41 | end Behavioral; -------------------------------------------------------------------------------- /hdl/stream_ctrl.v: -------------------------------------------------------------------------------- 1 | module stream_ctrl #( 2 | parameter DATA_WIDTH = 16 3 | )( 4 | input clk, 5 | input resetn, 6 | input [31 : 0] samples, 7 | input trig, 8 | input [DATA_WIDTH - 1 : 0] stream_i_tdata, 9 | input stream_i_tvalid, 10 | output stream_i_tready, 11 | output [DATA_WIDTH - 1 : 0] stream_o_tdata, 12 | output stream_o_tvalid, 13 | output stream_o_tlast, 14 | input stream_o_tready 15 | ); 16 | 17 | localparam [0:0] IDLE=0, RUNNING=1; 18 | reg state; 19 | reg [31 : 0] counter; 20 | reg trig_old; 21 | 22 | 23 | 24 | always @(posedge clk) begin 25 | if (resetn == 0) begin 26 | state <= IDLE; 27 | counter <= 0; 28 | trig_old <= 0; 29 | end else begin 30 | case(state) 31 | IDLE: begin 32 | counter <= 0; 33 | if((trig == 1) && (trig_old == 0)) begin 34 | state <= RUNNING; 35 | end 36 | end 37 | 38 | RUNNING: begin 39 | if((stream_i_tvalid == 1) && (stream_o_tready == 1)) begin 40 | counter <= counter + 1; 41 | if(counter == (samples - 1)) begin 42 | state <= IDLE; 43 | end 44 | end 45 | end 46 | endcase 47 | 48 | trig_old <= trig; 49 | end 50 | end 51 | 52 | assign stream_o_tdata = stream_i_tdata; 53 | 54 | assign stream_o_tvalid = (state == RUNNING) ? stream_i_tvalid : 0; 55 | 56 | assign stream_i_tready = (state == RUNNING) ? stream_o_tready : 0; 57 | 58 | assign stream_o_tlast = ((state == RUNNING) && (counter == (samples - 1))) ? 1 : 0; 59 | 60 | endmodule 61 | 62 | 63 | -------------------------------------------------------------------------------- /hdl/stream_ctrl.vhd: -------------------------------------------------------------------------------- 1 | 2 | library IEEE; 3 | use IEEE.STD_LOGIC_1164.ALL; 4 | use IEEE.NUMERIC_STD.ALL; 5 | 6 | 7 | entity stream_ctrl is 8 | Generic( DATA_WIDTH : integer := 16); 9 | Port ( clk : in STD_LOGIC; 10 | resetn : in STD_LOGIC; 11 | samples : in STD_LOGIC_VECTOR(31 downto 0); 12 | trig : in STD_LOGIC; 13 | stream_i_tdata : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 14 | stream_i_tvalid : in STD_LOGIC; 15 | stream_i_tready : out STD_LOGIC; 16 | stream_o_tdata: out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); 17 | stream_o_tvalid : out STD_LOGIC; 18 | stream_o_tlast : out STD_LOGIC; 19 | stream_o_tready : in STD_LOGIC 20 | 21 | ); 22 | end stream_ctrl; 23 | 24 | architecture Behavioral of stream_ctrl is 25 | type STATE_TYPE is (IDLE, RUNNING); 26 | signal state : STATE_TYPE := IDLE; 27 | signal counter : UNSIGNED(31 downto 0) := (others => '0'); 28 | signal trig_old : STD_LOGIC := '0'; 29 | 30 | begin 31 | process(clk) 32 | begin 33 | if rising_edge(clk) then 34 | if resetn='0' then 35 | state <= IDLE; 36 | counter <= (others => '0'); 37 | trig_old <= '0'; 38 | else 39 | 40 | case state is 41 | when IDLE => 42 | counter <= (others => '0'); 43 | if trig = '1' and trig_old = '0' then 44 | state <= RUNNING; 45 | end if; 46 | 47 | when RUNNING => 48 | if stream_i_tvalid = '1' and stream_o_tready = '1' then 49 | counter <= counter + 1; 50 | if counter = (unsigned(samples) - 1) then 51 | state <= IDLE; 52 | end if; 53 | end if; 54 | end case; 55 | 56 | trig_old <= trig; 57 | 58 | end if; 59 | end if; 60 | end process; 61 | 62 | stream_o_tdata <= stream_i_tdata; 63 | 64 | stream_o_tvalid <= stream_i_tvalid when state = RUNNING else 65 | '0'; 66 | 67 | stream_i_tready <= stream_o_tready when state = RUNNING else 68 | '0'; 69 | 70 | stream_o_tlast <= '1' when (state = RUNNING) and (counter = (unsigned(samples) - 1)) else 71 | '0'; 72 | 73 | end Behavioral; 74 | 75 | 76 | -------------------------------------------------------------------------------- /hdl/stream_multiplier.v: -------------------------------------------------------------------------------- 1 | module stream_multiplier #( 2 | parameter DATA_WIDTH = 16 3 | )( 4 | input clk, 5 | input resetn, 6 | input signed [DATA_WIDTH - 1 : 0] data_0_i_tdata, 7 | input data_0_i_tvalid, 8 | input signed [DATA_WIDTH - 1 : 0] data_1_i_tdata, 9 | input data_1_i_tvalid, 10 | output signed [DATA_WIDTH - 1 : 0] data_o_tdata, 11 | output reg data_o_tvalid 12 | ); 13 | 14 | reg signed [2 * DATA_WIDTH - 1 : 0] mult_reg; 15 | 16 | always @(posedge clk) begin 17 | if(resetn == 0) begin 18 | mult_reg <= 0; 19 | data_o_tvalid <= 0; 20 | end else begin 21 | mult_reg <= data_0_i_tdata * data_1_i_tdata; 22 | data_o_tvalid <= data_0_i_tvalid & data_1_i_tvalid; 23 | end 24 | end 25 | 26 | assign data_o_tdata = mult_reg[2 * DATA_WIDTH - 2 : DATA_WIDTH - 1]; 27 | 28 | endmodule -------------------------------------------------------------------------------- /hdl/stream_multiplier.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | 7 | entity stream_multiplier is 8 | Generic (DATA_WIDTH : integer := 16); 9 | Port ( clk : in STD_LOGIC; 10 | resetn : in STD_LOGIC; 11 | amplitude : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 12 | data_0_i_tdata : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 13 | data_0_i_tvalid : in STD_LOGIC; 14 | data_1_i_tdata : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 15 | data_1_i_tvalid : in STD_LOGIC; 16 | data_o_tdata : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); 17 | data_o_tvalid : out STD_LOGIC); 18 | end stream_multiplier; 19 | 20 | architecture Behavioral of stream_multiplier is 21 | signal mult_reg : signed(2*DATA_WIDTH - 1 downto 0) := (others => '0'); 22 | signal valid_reg : std_logic := '0'; 23 | 24 | begin 25 | process(clk) 26 | begin 27 | if rising_edge(clk) then 28 | if resetn = '0' then 29 | mult_reg <= (others => '0'); 30 | valid_reg <= '0'; 31 | else 32 | mult_reg <= signed(data_0_i_tdata) * signed(data_1_i_tdata); 33 | valid_reg <= data_0_i_tvalid and data_1_i_tvalid; 34 | end if; 35 | end if; 36 | end process; 37 | 38 | data_o_tvalid <= valid_reg; 39 | data_o_tdata <= std_logic_vector(mult_reg(2 * DATA_WIDTH - 2 downto DATA_WIDTH - 1)); 40 | 41 | 42 | end Behavioral; -------------------------------------------------------------------------------- /ip/AXI4-register-bank/bd/bd.tcl: -------------------------------------------------------------------------------- 1 | 2 | proc init { cellpath otherInfo } { 3 | 4 | set cell_handle [get_bd_cells $cellpath] 5 | set all_busif [get_bd_intf_pins $cellpath/*] 6 | set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] 7 | set full_sbusif_list [list ] 8 | 9 | foreach busif $all_busif { 10 | if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { 11 | set busif_param_list [list] 12 | set busif_name [get_property NAME $busif] 13 | if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { 14 | continue 15 | } 16 | foreach tparam $axi_standard_param_list { 17 | lappend busif_param_list "C_${busif_name}_${tparam}" 18 | } 19 | bd::mark_propagate_only $cell_handle $busif_param_list 20 | } 21 | } 22 | } 23 | 24 | 25 | proc pre_propagate {cellpath otherInfo } { 26 | 27 | set cell_handle [get_bd_cells $cellpath] 28 | set all_busif [get_bd_intf_pins $cellpath/*] 29 | set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] 30 | 31 | foreach busif $all_busif { 32 | if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { 33 | continue 34 | } 35 | if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { 36 | continue 37 | } 38 | 39 | set busif_name [get_property NAME $busif] 40 | foreach tparam $axi_standard_param_list { 41 | set busif_param_name "C_${busif_name}_${tparam}" 42 | 43 | set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] 44 | set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] 45 | 46 | if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { 47 | if { $val_on_cell != "" } { 48 | set_property CONFIG.${tparam} $val_on_cell $busif 49 | } 50 | } 51 | } 52 | } 53 | } 54 | 55 | 56 | proc propagate {cellpath otherInfo } { 57 | 58 | set cell_handle [get_bd_cells $cellpath] 59 | set all_busif [get_bd_intf_pins $cellpath/*] 60 | set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] 61 | 62 | foreach busif $all_busif { 63 | if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { 64 | continue 65 | } 66 | if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { 67 | continue 68 | } 69 | 70 | set busif_name [get_property NAME $busif] 71 | foreach tparam $axi_standard_param_list { 72 | set busif_param_name "C_${busif_name}_${tparam}" 73 | 74 | set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] 75 | set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] 76 | 77 | if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { 78 | #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. 79 | if { $val_on_cell_intf_pin != "" } { 80 | set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle 81 | } 82 | } 83 | } 84 | } 85 | } 86 | 87 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/drivers/axi_reg_v1_0/data/axi_reg.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER axi_reg 6 | OPTION supported_peripherals = (axi_reg); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = axi_reg; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/drivers/axi_reg_v1_0/data/axi_reg.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "axi_reg" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/drivers/axi_reg_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling axi_reg..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/drivers/axi_reg_v1_0/src/axi_reg.c: -------------------------------------------------------------------------------- 1 | 2 | 3 | /***************************** Include Files *******************************/ 4 | #include "axi_reg.h" 5 | 6 | /************************** Function Definitions ***************************/ 7 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/drivers/axi_reg_v1_0/src/axi_reg.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef AXI_REG_H 3 | #define AXI_REG_H 4 | 5 | 6 | /****************** Include Files ********************/ 7 | #include "xil_types.h" 8 | #include "xstatus.h" 9 | 10 | #define AXI_REG_S00_AXI_SLV_REG0_OFFSET 0 11 | #define AXI_REG_S00_AXI_SLV_REG1_OFFSET 4 12 | #define AXI_REG_S00_AXI_SLV_REG2_OFFSET 8 13 | #define AXI_REG_S00_AXI_SLV_REG3_OFFSET 12 14 | #define AXI_REG_S00_AXI_SLV_REG4_OFFSET 16 15 | #define AXI_REG_S00_AXI_SLV_REG5_OFFSET 20 16 | #define AXI_REG_S00_AXI_SLV_REG6_OFFSET 24 17 | #define AXI_REG_S00_AXI_SLV_REG7_OFFSET 28 18 | #define AXI_REG_S00_AXI_SLV_REG8_OFFSET 32 19 | #define AXI_REG_S00_AXI_SLV_REG9_OFFSET 36 20 | #define AXI_REG_S00_AXI_SLV_REG10_OFFSET 40 21 | #define AXI_REG_S00_AXI_SLV_REG11_OFFSET 44 22 | #define AXI_REG_S00_AXI_SLV_REG12_OFFSET 48 23 | #define AXI_REG_S00_AXI_SLV_REG13_OFFSET 52 24 | #define AXI_REG_S00_AXI_SLV_REG14_OFFSET 56 25 | #define AXI_REG_S00_AXI_SLV_REG15_OFFSET 60 26 | #define AXI_REG_S00_AXI_SLV_REG16_OFFSET 64 27 | #define AXI_REG_S00_AXI_SLV_REG17_OFFSET 68 28 | #define AXI_REG_S00_AXI_SLV_REG18_OFFSET 72 29 | #define AXI_REG_S00_AXI_SLV_REG19_OFFSET 76 30 | #define AXI_REG_S00_AXI_SLV_REG20_OFFSET 80 31 | #define AXI_REG_S00_AXI_SLV_REG21_OFFSET 84 32 | #define AXI_REG_S00_AXI_SLV_REG22_OFFSET 88 33 | #define AXI_REG_S00_AXI_SLV_REG23_OFFSET 92 34 | #define AXI_REG_S00_AXI_SLV_REG24_OFFSET 96 35 | #define AXI_REG_S00_AXI_SLV_REG25_OFFSET 100 36 | #define AXI_REG_S00_AXI_SLV_REG26_OFFSET 104 37 | #define AXI_REG_S00_AXI_SLV_REG27_OFFSET 108 38 | #define AXI_REG_S00_AXI_SLV_REG28_OFFSET 112 39 | #define AXI_REG_S00_AXI_SLV_REG29_OFFSET 116 40 | #define AXI_REG_S00_AXI_SLV_REG30_OFFSET 120 41 | #define AXI_REG_S00_AXI_SLV_REG31_OFFSET 124 42 | 43 | 44 | /**************************** Type Definitions *****************************/ 45 | /** 46 | * 47 | * Write a value to a AXI_REG register. A 32 bit write is performed. 48 | * If the component is implemented in a smaller width, only the least 49 | * significant data is written. 50 | * 51 | * @param BaseAddress is the base address of the AXI_REGdevice. 52 | * @param RegOffset is the register offset from the base to write to. 53 | * @param Data is the data written to the register. 54 | * 55 | * @return None. 56 | * 57 | * @note 58 | * C-style signature: 59 | * void AXI_REG_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) 60 | * 61 | */ 62 | #define AXI_REG_mWriteReg(BaseAddress, RegOffset, Data) \ 63 | Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) 64 | 65 | /** 66 | * 67 | * Read a value from a AXI_REG register. A 32 bit read is performed. 68 | * If the component is implemented in a smaller width, only the least 69 | * significant data is read from the register. The most significant data 70 | * will be read as 0. 71 | * 72 | * @param BaseAddress is the base address of the AXI_REG device. 73 | * @param RegOffset is the register offset from the base to write to. 74 | * 75 | * @return Data is the data from the register. 76 | * 77 | * @note 78 | * C-style signature: 79 | * u32 AXI_REG_mReadReg(u32 BaseAddress, unsigned RegOffset) 80 | * 81 | */ 82 | #define AXI_REG_mReadReg(BaseAddress, RegOffset) \ 83 | Xil_In32((BaseAddress) + (RegOffset)) 84 | 85 | /************************** Function Prototypes ****************************/ 86 | /** 87 | * 88 | * Run a self-test on the driver/device. Note this may be a destructive test if 89 | * resets of the device are performed. 90 | * 91 | * If the hardware system is not built correctly, this function may never 92 | * return to the caller. 93 | * 94 | * @param baseaddr_p is the base address of the AXI_REG instance to be worked on. 95 | * 96 | * @return 97 | * 98 | * - XST_SUCCESS if all self-test code passed 99 | * - XST_FAILURE if any self-test code failed 100 | * 101 | * @note Caching must be turned off for this function to work. 102 | * @note Self test may fail if data memory and device are not on the same bus. 103 | * 104 | */ 105 | XStatus AXI_REG_Reg_SelfTest(void * baseaddr_p); 106 | 107 | #endif // AXI_REG_H 108 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/drivers/axi_reg_v1_0/src/axi_reg_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "axi_reg.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the AXI_REGinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus AXI_REG_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | AXI_REG_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( AXI_REG_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/example_designs/bfm_design/design.tcl: -------------------------------------------------------------------------------- 1 | proc create_ipi_design { offsetfile design_name } { 2 | create_bd_design $design_name 3 | open_bd_design $design_name 4 | 5 | # Create Clock and Reset Ports 6 | set ACLK [ create_bd_port -dir I -type clk ACLK ] 7 | set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK 8 | set ARESETN [ create_bd_port -dir I -type rst ARESETN ] 9 | set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN 10 | set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK 11 | 12 | # Create instance: axi_reg_0, and set properties 13 | set axi_reg_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axi_reg:1.0 axi_reg_0] 14 | 15 | # Create instance: master_0, and set properties 16 | set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip master_0] 17 | set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {MASTER} ] $master_0 18 | 19 | # Create interface connections 20 | connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI ] [get_bd_intf_pins axi_reg_0/S00_AXI] 21 | 22 | # Create port connections 23 | connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/ACLK] [get_bd_pins axi_reg_0/S00_AXI_ACLK] 24 | connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/ARESETN] [get_bd_pins axi_reg_0/S00_AXI_ARESETN] 25 | set_property target_simulator XSim [current_project] 26 | set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1] 27 | 28 | # Auto assign address 29 | assign_bd_address 30 | 31 | # Copy all address to interface_address.vh file 32 | set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] 33 | upvar 1 $offsetfile offset_file 34 | set offset_file "${bd_path}/axi_reg_v1_0_tb_include.svh" 35 | set fp [open $offset_file "w"] 36 | puts $fp "`ifndef axi_reg_v1_0_tb_include_vh_" 37 | puts $fp "`define axi_reg_v1_0_tb_include_vh_\n" 38 | puts $fp "//Configuration current bd names" 39 | puts $fp "`define BD_NAME ${design_name}" 40 | puts $fp "`define BD_INST_NAME ${design_name}_i" 41 | puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" 42 | puts $fp "//Configuration address parameters" 43 | 44 | puts $fp "`endif" 45 | close $fp 46 | } 47 | 48 | set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores xilinx.com:user:axi_reg:1.0]]]] 49 | set test_bench_file ${ip_path}/example_designs/bfm_design/axi_reg_v1_0_tb.sv 50 | set interface_address_vh_file "" 51 | 52 | # Set IP Repository and Update IP Catalogue 53 | set repo_paths [get_property ip_repo_paths [current_fileset]] 54 | if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { 55 | set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] 56 | update_ip_catalog 57 | } 58 | 59 | set design_name "" 60 | set all_bd {} 61 | set all_bd_files [get_files *.bd -quiet] 62 | foreach file $all_bd_files { 63 | set file_name [string range $file [expr {[string last "/" $file] + 1}] end] 64 | set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] 65 | lappend all_bd $bd_name 66 | } 67 | 68 | for { set i 1 } { 1 } { incr i } { 69 | set design_name "axi_reg_v1_0_bfm_${i}" 70 | if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { 71 | break 72 | } 73 | } 74 | 75 | create_ipi_design interface_address_vh_file ${design_name} 76 | validate_bd_design 77 | 78 | set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] 79 | import_files -force -norecurse $wrapper_file 80 | 81 | set_property SOURCE_SET sources_1 [get_filesets sim_1] 82 | import_files -fileset sim_1 -norecurse -force $test_bench_file 83 | remove_files -quiet -fileset sim_1 axi_reg_v1_0_tb_include.vh 84 | import_files -fileset sim_1 -norecurse -force $interface_address_vh_file 85 | set_property top axi_reg_v1_0_tb [get_filesets sim_1] 86 | set_property top_lib {} [get_filesets sim_1] 87 | set_property top_file {} [get_filesets sim_1] 88 | launch_simulation -simset sim_1 -mode behavioral 89 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/example_designs/debug_hw_design/axi_reg_v1_0_hw_test.tcl: -------------------------------------------------------------------------------- 1 | # Runtime Tcl commands to interact with - axi_reg_v1_0 2 | 3 | # Sourcing design address info tcl 4 | set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd 5 | source ${bd_path}/axi_reg_v1_0_include.tcl 6 | 7 | # jtag axi master interface hardware name, change as per your design. 8 | set jtag_axi_master hw_axi_1 9 | set ec 0 10 | 11 | # hw test script 12 | # Delete all previous axis transactions 13 | if { [llength [get_hw_axi_txns -quiet]] } { 14 | delete_hw_axi_txn [get_hw_axi_txns -quiet] 15 | } 16 | 17 | 18 | # Test all lite slaves. 19 | set wdata_1 abcd1234 20 | 21 | # Test: S00_AXI 22 | # Create a write transaction at s00_axi_addr address 23 | create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 24 | # Create a read transaction at s00_axi_addr address 25 | create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr 26 | # Initiate transactions 27 | run_hw_axi r_s00_axi_addr 28 | run_hw_axi w_s00_axi_addr 29 | run_hw_axi r_s00_axi_addr 30 | set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] 31 | # Compare read data 32 | if { $rdata_tmp == $wdata_1 } { 33 | puts "Data comparison test pass for - S00_AXI" 34 | } else { 35 | puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" 36 | inc ec 37 | } 38 | 39 | # Check error flag 40 | if { $ec == 0 } { 41 | puts "PTGEN_TEST: PASSED!" 42 | } else { 43 | puts "PTGEN_TEST: FAILED!" 44 | } 45 | 46 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/example_designs/debug_hw_design/design.tcl: -------------------------------------------------------------------------------- 1 | 2 | proc create_ipi_design { offsetfile design_name } { 3 | 4 | create_bd_design $design_name 5 | open_bd_design $design_name 6 | 7 | # Create and configure Clock/Reset 8 | create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 9 | create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 10 | 11 | #Constraints will be provided manually while pin planning. 12 | create_bd_port -dir I -type rst reset_rtl 13 | set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] 14 | connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] 15 | connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] 16 | set external_reset_port reset_rtl 17 | create_bd_port -dir I -type clk clock_rtl 18 | connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] 19 | set external_clock_port clock_rtl 20 | 21 | #Avoid IPI DRC, make clock port synchronous to reset 22 | if { $external_clock_port ne "" && $external_reset_port ne "" } { 23 | set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] 24 | } 25 | 26 | # Connect other sys_reset pins 27 | connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] 28 | connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] 29 | 30 | # Create instance: axi_reg_0, and set properties 31 | set axi_reg_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:axi_reg:1.0 axi_reg_0 ] 32 | 33 | # Create instance: jtag_axi_0, and set properties 34 | set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] 35 | set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] 36 | connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] 37 | connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] 38 | 39 | # Create instance: axi_peri_interconnect, and set properties 40 | set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] 41 | connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] 42 | connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] 43 | set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect 44 | connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] 45 | connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] 46 | connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] 47 | 48 | set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect 49 | connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] 50 | connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] 51 | 52 | # Connect all clock & reset of axi_reg_0 slave interfaces.. 53 | connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins axi_reg_0/S00_AXI] 54 | connect_bd_net [get_bd_pins axi_reg_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] 55 | connect_bd_net [get_bd_pins axi_reg_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] 56 | 57 | 58 | # Auto assign address 59 | assign_bd_address 60 | 61 | # Copy all address to axi_reg_v1_0_include.tcl file 62 | set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd 63 | upvar 1 $offsetfile offset_file 64 | set offset_file "${bd_path}/axi_reg_v1_0_include.tcl" 65 | set fp [open $offset_file "w"] 66 | puts $fp "# Configuration address parameters" 67 | 68 | set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_reg_0_S00_AXI_* ]] 69 | puts $fp "set s00_axi_addr ${offset}" 70 | 71 | close $fp 72 | } 73 | 74 | # Set IP Repository and Update IP Catalogue 75 | set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores xilinx.com:user:axi_reg:1.0]]]] 76 | set hw_test_file ${ip_path}/example_designs/debug_hw_design/axi_reg_v1_0_hw_test.tcl 77 | 78 | set repo_paths [get_property ip_repo_paths [current_fileset]] 79 | if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { 80 | set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] 81 | update_ip_catalog 82 | } 83 | 84 | set design_name "" 85 | set all_bd {} 86 | set all_bd_files [get_files *.bd -quiet] 87 | foreach file $all_bd_files { 88 | set file_name [string range $file [expr {[string last "/" $file] + 1}] end] 89 | set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] 90 | lappend all_bd $bd_name 91 | } 92 | 93 | for { set i 1 } { 1 } { incr i } { 94 | set design_name "axi_reg_v1_0_hw_${i}" 95 | if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { 96 | break 97 | } 98 | } 99 | 100 | set intf_address_include_file "" 101 | create_ipi_design intf_address_include_file ${design_name} 102 | save_bd_design 103 | validate_bd_design 104 | 105 | set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] 106 | import_files -force -norecurse $wrapper_file 107 | 108 | puts "-------------------------------------------------------------------------------------------------" 109 | puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " 110 | puts " please perform following steps to test design in targeted board." 111 | puts "1. Generate bitstream" 112 | puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" 113 | puts "3. Download generated bitstream" 114 | puts "4. Run generated hardware test using below command, this invokes basic read/write operation" 115 | puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" 116 | puts " : source -notrace ${hw_test_file}" 117 | puts "-------------------------------------------------------------------------------------------------" 118 | 119 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/gui/axi_reg_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_port_width_reg_in_00_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 0} 3 | proc gen_USERPARAMETER_port_width_reg_in_01_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 1} 4 | proc gen_USERPARAMETER_port_width_reg_in_02_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 2} 5 | proc gen_USERPARAMETER_port_width_reg_in_03_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 3} 6 | proc gen_USERPARAMETER_port_width_reg_in_04_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 4} 7 | proc gen_USERPARAMETER_port_width_reg_in_05_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 5} 8 | proc gen_USERPARAMETER_port_width_reg_in_06_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 6} 9 | proc gen_USERPARAMETER_port_width_reg_in_07_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 7} 10 | proc gen_USERPARAMETER_port_width_reg_in_08_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 8} 11 | proc gen_USERPARAMETER_port_width_reg_in_09_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 9} 12 | proc gen_USERPARAMETER_port_width_reg_in_10_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 10} 13 | proc gen_USERPARAMETER_port_width_reg_in_11_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 11} 14 | proc gen_USERPARAMETER_port_width_reg_in_12_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 12} 15 | proc gen_USERPARAMETER_port_width_reg_in_13_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 13} 16 | proc gen_USERPARAMETER_port_width_reg_in_14_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 14} 17 | proc gen_USERPARAMETER_port_width_reg_in_15_ENABLEMENT {reg_in_enabled } {expr $reg_in_enabled > 15} 18 | proc gen_USERPARAMETER_port_width_reg_out_00_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 0} 19 | proc gen_USERPARAMETER_port_width_reg_out_01_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 1} 20 | proc gen_USERPARAMETER_port_width_reg_out_02_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 2} 21 | proc gen_USERPARAMETER_port_width_reg_out_03_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 3} 22 | proc gen_USERPARAMETER_port_width_reg_out_04_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 4} 23 | proc gen_USERPARAMETER_port_width_reg_out_05_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 5} 24 | proc gen_USERPARAMETER_port_width_reg_out_06_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 6} 25 | proc gen_USERPARAMETER_port_width_reg_out_07_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 7} 26 | proc gen_USERPARAMETER_port_width_reg_out_08_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 8} 27 | proc gen_USERPARAMETER_port_width_reg_out_09_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 9} 28 | proc gen_USERPARAMETER_port_width_reg_out_10_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 10} 29 | proc gen_USERPARAMETER_port_width_reg_out_11_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 11} 30 | proc gen_USERPARAMETER_port_width_reg_out_12_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 12} 31 | proc gen_USERPARAMETER_port_width_reg_out_13_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 13} 32 | proc gen_USERPARAMETER_port_width_reg_out_14_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 14} 33 | proc gen_USERPARAMETER_port_width_reg_out_15_ENABLEMENT {reg_out_enabled } {expr $reg_out_enabled > 15} 34 | -------------------------------------------------------------------------------- /ip/AXI4-register-bank/hdl/axi_reg_v1_0.v: -------------------------------------------------------------------------------- 1 | 2 | `timescale 1 ns / 1 ps 3 | 4 | module axi_reg_v1_0 # 5 | ( 6 | // Users to add parameters here 7 | 8 | // User parameters ends 9 | // Do not modify the parameters beyond this line 10 | 11 | 12 | // Parameters of Axi Slave Bus Interface S00_AXI 13 | parameter integer C_S00_AXI_DATA_WIDTH = 32, 14 | parameter integer C_S00_AXI_ADDR_WIDTH = 7, 15 | 16 | parameter integer reg_in_enabled = 1, 17 | parameter integer port_width_reg_in_00 = 32, 18 | parameter integer port_width_reg_in_01 = 32, 19 | parameter integer port_width_reg_in_02 = 32, 20 | parameter integer port_width_reg_in_03 = 32, 21 | parameter integer port_width_reg_in_04 = 32, 22 | parameter integer port_width_reg_in_05 = 32, 23 | parameter integer port_width_reg_in_06 = 32, 24 | parameter integer port_width_reg_in_07 = 32, 25 | parameter integer port_width_reg_in_08 = 32, 26 | parameter integer port_width_reg_in_09 = 32, 27 | parameter integer port_width_reg_in_10 = 32, 28 | parameter integer port_width_reg_in_11 = 32, 29 | parameter integer port_width_reg_in_12 = 32, 30 | parameter integer port_width_reg_in_13 = 32, 31 | parameter integer port_width_reg_in_14 = 32, 32 | parameter integer port_width_reg_in_15 = 32, 33 | 34 | parameter integer reg_out_enabled = 1, 35 | parameter integer port_width_reg_out_00 = 32, 36 | parameter integer port_width_reg_out_01 = 32, 37 | parameter integer port_width_reg_out_02 = 32, 38 | parameter integer port_width_reg_out_03 = 32, 39 | parameter integer port_width_reg_out_04 = 32, 40 | parameter integer port_width_reg_out_05 = 32, 41 | parameter integer port_width_reg_out_06 = 32, 42 | parameter integer port_width_reg_out_07 = 32, 43 | parameter integer port_width_reg_out_08 = 32, 44 | parameter integer port_width_reg_out_09 = 32, 45 | parameter integer port_width_reg_out_10 = 32, 46 | parameter integer port_width_reg_out_11 = 32, 47 | parameter integer port_width_reg_out_12 = 32, 48 | parameter integer port_width_reg_out_13 = 32, 49 | parameter integer port_width_reg_out_14 = 32, 50 | parameter integer port_width_reg_out_15 = 32 51 | ) 52 | ( 53 | // Ports of Axi Slave Bus Interface S00_AXI 54 | input wire s00_axi_aclk, 55 | input wire s00_axi_aresetn, 56 | input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr, 57 | input wire [2 : 0] s00_axi_awprot, 58 | input wire s00_axi_awvalid, 59 | output wire s00_axi_awready, 60 | input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata, 61 | input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb, 62 | input wire s00_axi_wvalid, 63 | output wire s00_axi_wready, 64 | output wire [1 : 0] s00_axi_bresp, 65 | output wire s00_axi_bvalid, 66 | input wire s00_axi_bready, 67 | input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr, 68 | input wire [2 : 0] s00_axi_arprot, 69 | input wire s00_axi_arvalid, 70 | output wire s00_axi_arready, 71 | output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata, 72 | output wire [1 : 0] s00_axi_rresp, 73 | output wire s00_axi_rvalid, 74 | input wire s00_axi_rready, 75 | 76 | input wire [port_width_reg_in_00 - 1 : 0] regIn00, 77 | input wire [port_width_reg_in_01 - 1 : 0] regIn01, 78 | input wire [port_width_reg_in_02 - 1 : 0] regIn02, 79 | input wire [port_width_reg_in_03 - 1 : 0] regIn03, 80 | input wire [port_width_reg_in_04 - 1 : 0] regIn04, 81 | input wire [port_width_reg_in_05 - 1 : 0] regIn05, 82 | input wire [port_width_reg_in_06 - 1 : 0] regIn06, 83 | input wire [port_width_reg_in_07 - 1 : 0] regIn07, 84 | input wire [port_width_reg_in_08 - 1 : 0] regIn08, 85 | input wire [port_width_reg_in_09 - 1 : 0] regIn09, 86 | input wire [port_width_reg_in_10 - 1 : 0] regIn10, 87 | input wire [port_width_reg_in_11 - 1 : 0] regIn11, 88 | input wire [port_width_reg_in_12 - 1 : 0] regIn12, 89 | input wire [port_width_reg_in_13 - 1 : 0] regIn13, 90 | input wire [port_width_reg_in_14 - 1 : 0] regIn14, 91 | input wire [port_width_reg_in_15 - 1 : 0] regIn15, 92 | 93 | output wire [port_width_reg_out_00 - 1 : 0] regOut00, 94 | output wire [port_width_reg_out_01 - 1 : 0] regOut01, 95 | output wire [port_width_reg_out_02 - 1 : 0] regOut02, 96 | output wire [port_width_reg_out_03 - 1 : 0] regOut03, 97 | output wire [port_width_reg_out_04 - 1 : 0] regOut04, 98 | output wire [port_width_reg_out_05 - 1 : 0] regOut05, 99 | output wire [port_width_reg_out_06 - 1 : 0] regOut06, 100 | output wire [port_width_reg_out_07 - 1 : 0] regOut07, 101 | output wire [port_width_reg_out_08 - 1 : 0] regOut08, 102 | output wire [port_width_reg_out_09 - 1 : 0] regOut09, 103 | output wire [port_width_reg_out_10 - 1 : 0] regOut10, 104 | output wire [port_width_reg_out_11 - 1 : 0] regOut11, 105 | output wire [port_width_reg_out_12 - 1 : 0] regOut12, 106 | output wire [port_width_reg_out_13 - 1 : 0] regOut13, 107 | output wire [port_width_reg_out_14 - 1 : 0] regOut14, 108 | output wire [port_width_reg_out_15 - 1 : 0] regOut15 109 | ); 110 | // Instantiation of Axi Bus Interface S00_AXI 111 | axi_reg_v1_0_S00_AXI # ( 112 | .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH), 113 | .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH), 114 | 115 | .reg_in_enabled(reg_in_enabled), 116 | .port_width_reg_in_00(port_width_reg_in_00), 117 | .port_width_reg_in_01(port_width_reg_in_01), 118 | .port_width_reg_in_02(port_width_reg_in_02), 119 | .port_width_reg_in_03(port_width_reg_in_03), 120 | .port_width_reg_in_04(port_width_reg_in_04), 121 | .port_width_reg_in_05(port_width_reg_in_05), 122 | .port_width_reg_in_06(port_width_reg_in_06), 123 | .port_width_reg_in_07(port_width_reg_in_07), 124 | .port_width_reg_in_08(port_width_reg_in_08), 125 | .port_width_reg_in_09(port_width_reg_in_09), 126 | .port_width_reg_in_10(port_width_reg_in_10), 127 | .port_width_reg_in_11(port_width_reg_in_11), 128 | .port_width_reg_in_12(port_width_reg_in_12), 129 | .port_width_reg_in_13(port_width_reg_in_13), 130 | .port_width_reg_in_14(port_width_reg_in_14), 131 | .port_width_reg_in_15(port_width_reg_in_15), 132 | 133 | .reg_out_enabled(reg_out_enabled), 134 | .port_width_reg_out_00(port_width_reg_out_00), 135 | .port_width_reg_out_01(port_width_reg_out_01), 136 | .port_width_reg_out_02(port_width_reg_out_02), 137 | .port_width_reg_out_03(port_width_reg_out_03), 138 | .port_width_reg_out_04(port_width_reg_out_04), 139 | .port_width_reg_out_05(port_width_reg_out_05), 140 | .port_width_reg_out_06(port_width_reg_out_06), 141 | .port_width_reg_out_07(port_width_reg_out_07), 142 | .port_width_reg_out_08(port_width_reg_out_08), 143 | .port_width_reg_out_09(port_width_reg_out_09), 144 | .port_width_reg_out_10(port_width_reg_out_10), 145 | .port_width_reg_out_11(port_width_reg_out_11), 146 | .port_width_reg_out_12(port_width_reg_out_12), 147 | .port_width_reg_out_13(port_width_reg_out_13), 148 | .port_width_reg_out_14(port_width_reg_out_14), 149 | .port_width_reg_out_15(port_width_reg_out_15) 150 | 151 | ) axi_reg_v1_0_S00_AXI_inst ( 152 | .S_AXI_ACLK(s00_axi_aclk), 153 | .S_AXI_ARESETN(s00_axi_aresetn), 154 | .S_AXI_AWADDR(s00_axi_awaddr), 155 | .S_AXI_AWPROT(s00_axi_awprot), 156 | .S_AXI_AWVALID(s00_axi_awvalid), 157 | .S_AXI_AWREADY(s00_axi_awready), 158 | .S_AXI_WDATA(s00_axi_wdata), 159 | .S_AXI_WSTRB(s00_axi_wstrb), 160 | .S_AXI_WVALID(s00_axi_wvalid), 161 | .S_AXI_WREADY(s00_axi_wready), 162 | .S_AXI_BRESP(s00_axi_bresp), 163 | .S_AXI_BVALID(s00_axi_bvalid), 164 | .S_AXI_BREADY(s00_axi_bready), 165 | .S_AXI_ARADDR(s00_axi_araddr), 166 | .S_AXI_ARPROT(s00_axi_arprot), 167 | .S_AXI_ARVALID(s00_axi_arvalid), 168 | .S_AXI_ARREADY(s00_axi_arready), 169 | .S_AXI_RDATA(s00_axi_rdata), 170 | .S_AXI_RRESP(s00_axi_rresp), 171 | .S_AXI_RVALID(s00_axi_rvalid), 172 | .S_AXI_RREADY(s00_axi_rready), 173 | 174 | .regIn00(regIn00), 175 | .regIn01(regIn01), 176 | .regIn02(regIn02), 177 | .regIn03(regIn03), 178 | .regIn04(regIn04), 179 | .regIn05(regIn05), 180 | .regIn06(regIn06), 181 | .regIn07(regIn07), 182 | .regIn08(regIn08), 183 | .regIn09(regIn09), 184 | .regIn10(regIn10), 185 | .regIn11(regIn11), 186 | .regIn12(regIn12), 187 | .regIn13(regIn13), 188 | .regIn14(regIn14), 189 | .regIn15(regIn15), 190 | 191 | .regOut00(regOut00), 192 | .regOut01(regOut01), 193 | .regOut02(regOut02), 194 | .regOut03(regOut03), 195 | .regOut04(regOut04), 196 | .regOut05(regOut05), 197 | .regOut06(regOut06), 198 | .regOut07(regOut07), 199 | .regOut08(regOut08), 200 | .regOut09(regOut09), 201 | .regOut10(regOut10), 202 | .regOut11(regOut11), 203 | .regOut12(regOut12), 204 | .regOut13(regOut13), 205 | .regOut14(regOut14), 206 | .regOut15(regOut15) 207 | ); 208 | 209 | // Add user logic here 210 | 211 | // User logic ends 212 | 213 | endmodule 214 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/sim/adc_bd.vhd: -------------------------------------------------------------------------------- 1 | --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------- 3 | --Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 4 | --Date : Fri May 28 08:15:09 2021 5 | --Host : 5CD010B25T running 64-bit major release (build 9200) 6 | --Command : generate_target adc_bd.bd 7 | --Design : adc_bd 8 | --Purpose : IP block netlist 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | library UNISIM; 13 | use UNISIM.VCOMPONENTS.ALL; 14 | entity adc_bd is 15 | port ( 16 | adc_data_1_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 17 | adc_data_1_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 18 | adc_data_1_tvalid : out STD_LOGIC; 19 | adc_data_2_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 20 | adc_data_2_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 21 | adc_data_2_tvalid : out STD_LOGIC; 22 | clk_125 : in STD_LOGIC; 23 | resetn : in STD_LOGIC 24 | ); 25 | attribute CORE_GENERATION_INFO : string; 26 | attribute CORE_GENERATION_INFO of adc_bd : entity is "adc_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=adc_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; 27 | attribute HW_HANDOFF : string; 28 | attribute HW_HANDOFF of adc_bd : entity is "adc_bd.hwdef"; 29 | end adc_bd; 30 | 31 | architecture STRUCTURE of adc_bd is 32 | component adc_bd_ADC_0_1 is 33 | port ( 34 | clk_125 : in STD_LOGIC; 35 | resetn : in STD_LOGIC; 36 | adc_data_1_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 37 | adc_data_2_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 38 | adc_data_1_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 39 | adc_data_2_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 40 | adc_data_1_tvalid : out STD_LOGIC; 41 | adc_data_2_tvalid : out STD_LOGIC 42 | ); 43 | end component adc_bd_ADC_0_1; 44 | signal ADC_0_adc_data_1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 45 | signal ADC_0_adc_data_1_TVALID : STD_LOGIC; 46 | signal ADC_0_adc_data_2_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 47 | signal ADC_0_adc_data_2_TVALID : STD_LOGIC; 48 | signal adc_data_1_i_1 : STD_LOGIC_VECTOR ( 13 downto 0 ); 49 | signal adc_data_2_i_1 : STD_LOGIC_VECTOR ( 13 downto 0 ); 50 | signal clk_125_1 : STD_LOGIC; 51 | signal resetn_1 : STD_LOGIC; 52 | attribute X_INTERFACE_INFO : string; 53 | attribute X_INTERFACE_INFO of adc_data_1_tvalid : signal is "xilinx.com:interface:axis:1.0 adc_data_1 TVALID"; 54 | attribute X_INTERFACE_INFO of adc_data_2_tvalid : signal is "xilinx.com:interface:axis:1.0 adc_data_2 TVALID"; 55 | attribute X_INTERFACE_INFO of clk_125 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_125 CLK"; 56 | attribute X_INTERFACE_PARAMETER : string; 57 | attribute X_INTERFACE_PARAMETER of clk_125 : signal is "XIL_INTERFACENAME CLK.CLK_125, CLK_DOMAIN adc_bd_clk_125, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000"; 58 | attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST"; 59 | attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW"; 60 | attribute X_INTERFACE_INFO of adc_data_1_tdata : signal is "xilinx.com:interface:axis:1.0 adc_data_1 TDATA"; 61 | attribute X_INTERFACE_PARAMETER of adc_data_1_tdata : signal is "XIL_INTERFACENAME adc_data_1, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 62 | attribute X_INTERFACE_INFO of adc_data_2_tdata : signal is "xilinx.com:interface:axis:1.0 adc_data_2 TDATA"; 63 | attribute X_INTERFACE_PARAMETER of adc_data_2_tdata : signal is "XIL_INTERFACENAME adc_data_2, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 64 | begin 65 | adc_data_1_i_1(13 downto 0) <= adc_data_1_i(13 downto 0); 66 | adc_data_1_tdata(15 downto 0) <= ADC_0_adc_data_1_TDATA(15 downto 0); 67 | adc_data_1_tvalid <= ADC_0_adc_data_1_TVALID; 68 | adc_data_2_i_1(13 downto 0) <= adc_data_2_i(13 downto 0); 69 | adc_data_2_tdata(15 downto 0) <= ADC_0_adc_data_2_TDATA(15 downto 0); 70 | adc_data_2_tvalid <= ADC_0_adc_data_2_TVALID; 71 | clk_125_1 <= clk_125; 72 | resetn_1 <= resetn; 73 | ADC_0: component adc_bd_ADC_0_1 74 | port map ( 75 | adc_data_1_i(13 downto 0) => adc_data_1_i_1(13 downto 0), 76 | adc_data_1_tdata(15 downto 0) => ADC_0_adc_data_1_TDATA(15 downto 0), 77 | adc_data_1_tvalid => ADC_0_adc_data_1_TVALID, 78 | adc_data_2_i(13 downto 0) => adc_data_2_i_1(13 downto 0), 79 | adc_data_2_tdata(15 downto 0) => ADC_0_adc_data_2_TDATA(15 downto 0), 80 | adc_data_2_tvalid => ADC_0_adc_data_2_TVALID, 81 | clk_125 => clk_125_1, 82 | resetn => resetn_1 83 | ); 84 | end STRUCTURE; 85 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/sim/adc_bd_ADC_0_1.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:ADC:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY adc_bd_ADC_0_1 IS 57 | PORT ( 58 | clk_125 : IN STD_LOGIC; 59 | resetn : IN STD_LOGIC; 60 | adc_data_1_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 61 | adc_data_2_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 62 | adc_data_1_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 63 | adc_data_2_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 64 | adc_data_1_tvalid : OUT STD_LOGIC; 65 | adc_data_2_tvalid : OUT STD_LOGIC 66 | ); 67 | END adc_bd_ADC_0_1; 68 | 69 | ARCHITECTURE adc_bd_ADC_0_1_arch OF adc_bd_ADC_0_1 IS 70 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 71 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF adc_bd_ADC_0_1_arch: ARCHITECTURE IS "yes"; 72 | COMPONENT ADC IS 73 | PORT ( 74 | clk_125 : IN STD_LOGIC; 75 | resetn : IN STD_LOGIC; 76 | adc_data_1_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 77 | adc_data_2_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 78 | adc_data_1_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 79 | adc_data_2_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 80 | adc_data_1_tvalid : OUT STD_LOGIC; 81 | adc_data_2_tvalid : OUT STD_LOGIC 82 | ); 83 | END COMPONENT ADC; 84 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 85 | ATTRIBUTE IP_DEFINITION_SOURCE OF adc_bd_ADC_0_1_arch: ARCHITECTURE IS "module_ref"; 86 | ATTRIBUTE X_INTERFACE_INFO : STRING; 87 | ATTRIBUTE X_INTERFACE_PARAMETER : STRING; 88 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_2_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_2 TVALID"; 89 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_1_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_1 TVALID"; 90 | ATTRIBUTE X_INTERFACE_PARAMETER OF adc_data_2_tdata: SIGNAL IS "XIL_INTERFACENAME adc_data_2, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 91 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_2_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_2 TDATA"; 92 | ATTRIBUTE X_INTERFACE_PARAMETER OF adc_data_1_tdata: SIGNAL IS "XIL_INTERFACENAME adc_data_1, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 93 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_1_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_1 TDATA"; 94 | ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0"; 95 | ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST"; 96 | BEGIN 97 | U0 : ADC 98 | PORT MAP ( 99 | clk_125 => clk_125, 100 | resetn => resetn, 101 | adc_data_1_i => adc_data_1_i, 102 | adc_data_2_i => adc_data_2_i, 103 | adc_data_1_tdata => adc_data_1_tdata, 104 | adc_data_2_tdata => adc_data_2_tdata, 105 | adc_data_1_tvalid => adc_data_1_tvalid, 106 | adc_data_2_tvalid => adc_data_2_tvalid 107 | ); 108 | END adc_bd_ADC_0_1_arch; 109 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/src/ADC.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 17.05.2021 19:40:32 6 | -- Design Name: 7 | -- Module Name: ADC - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity ADC is 35 | Port ( clk_125 : in std_logic; 36 | resetn : in std_logic; 37 | adc_data_1_i : in std_logic_vector (13 downto 0); 38 | adc_data_2_i : in std_logic_vector (13 downto 0); 39 | adc_data_1_tdata : out std_logic_vector (15 downto 0); 40 | adc_data_2_tdata : out std_logic_vector (15 downto 0); 41 | adc_data_1_tvalid : out std_logic; 42 | adc_data_2_tvalid : out std_logic 43 | ); 44 | end ADC; 45 | 46 | architecture Behavioral of ADC is 47 | signal data_1 : std_logic_vector (13 downto 0) := (others => '0'); 48 | signal data_2 : std_logic_vector (13 downto 0) := (others => '0'); 49 | signal valid : std_logic := '0'; 50 | 51 | begin 52 | process(clk_125) 53 | begin 54 | if rising_edge(clk_125) then 55 | if resetn = '0' then 56 | data_1 <= (others => '0'); 57 | data_2 <= (others => '0'); 58 | valid <= '0'; 59 | else 60 | data_1 <= adc_data_1_i; 61 | data_2 <= adc_data_2_i; 62 | valid <= '1'; 63 | end if; 64 | end if; 65 | end process; 66 | 67 | adc_data_1_tdata(15) <= data_1(13); 68 | adc_data_1_tdata(14 downto 2) <= not data_1(12 downto 0); 69 | adc_data_1_tdata(1 downto 0) <= (others => '0'); 70 | 71 | adc_data_2_tdata(15) <= data_2(13); 72 | adc_data_2_tdata(14 downto 2) <= not data_2(12 downto 0); 73 | adc_data_2_tdata(1 downto 0) <= (others => '0'); 74 | 75 | adc_data_1_tvalid <= valid; 76 | adc_data_2_tvalid <= valid; 77 | 78 | 79 | end Behavioral; 80 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/src/adc_bd.vhd: -------------------------------------------------------------------------------- 1 | --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------- 3 | --Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 4 | --Date : Fri May 28 08:15:09 2021 5 | --Host : 5CD010B25T running 64-bit major release (build 9200) 6 | --Command : generate_target adc_bd.bd 7 | --Design : adc_bd 8 | --Purpose : IP block netlist 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | library UNISIM; 13 | use UNISIM.VCOMPONENTS.ALL; 14 | entity adc_bd is 15 | port ( 16 | adc_data_1_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 17 | adc_data_1_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 18 | adc_data_1_tvalid : out STD_LOGIC; 19 | adc_data_2_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 20 | adc_data_2_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 21 | adc_data_2_tvalid : out STD_LOGIC; 22 | clk_125 : in STD_LOGIC; 23 | resetn : in STD_LOGIC 24 | ); 25 | attribute CORE_GENERATION_INFO : string; 26 | attribute CORE_GENERATION_INFO of adc_bd : entity is "adc_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=adc_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; 27 | attribute HW_HANDOFF : string; 28 | attribute HW_HANDOFF of adc_bd : entity is "adc_bd.hwdef"; 29 | end adc_bd; 30 | 31 | architecture STRUCTURE of adc_bd is 32 | component adc_bd_ADC_0_1 is 33 | port ( 34 | clk_125 : in STD_LOGIC; 35 | resetn : in STD_LOGIC; 36 | adc_data_1_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 37 | adc_data_2_i : in STD_LOGIC_VECTOR ( 13 downto 0 ); 38 | adc_data_1_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 39 | adc_data_2_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ); 40 | adc_data_1_tvalid : out STD_LOGIC; 41 | adc_data_2_tvalid : out STD_LOGIC 42 | ); 43 | end component adc_bd_ADC_0_1; 44 | signal ADC_0_adc_data_1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 45 | signal ADC_0_adc_data_1_TVALID : STD_LOGIC; 46 | signal ADC_0_adc_data_2_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 47 | signal ADC_0_adc_data_2_TVALID : STD_LOGIC; 48 | signal adc_data_1_i_1 : STD_LOGIC_VECTOR ( 13 downto 0 ); 49 | signal adc_data_2_i_1 : STD_LOGIC_VECTOR ( 13 downto 0 ); 50 | signal clk_125_1 : STD_LOGIC; 51 | signal resetn_1 : STD_LOGIC; 52 | attribute X_INTERFACE_INFO : string; 53 | attribute X_INTERFACE_INFO of adc_data_1_tvalid : signal is "xilinx.com:interface:axis:1.0 adc_data_1 TVALID"; 54 | attribute X_INTERFACE_INFO of adc_data_2_tvalid : signal is "xilinx.com:interface:axis:1.0 adc_data_2 TVALID"; 55 | attribute X_INTERFACE_INFO of clk_125 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_125 CLK"; 56 | attribute X_INTERFACE_PARAMETER : string; 57 | attribute X_INTERFACE_PARAMETER of clk_125 : signal is "XIL_INTERFACENAME CLK.CLK_125, CLK_DOMAIN adc_bd_clk_125, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000"; 58 | attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST"; 59 | attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW"; 60 | attribute X_INTERFACE_INFO of adc_data_1_tdata : signal is "xilinx.com:interface:axis:1.0 adc_data_1 TDATA"; 61 | attribute X_INTERFACE_PARAMETER of adc_data_1_tdata : signal is "XIL_INTERFACENAME adc_data_1, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 62 | attribute X_INTERFACE_INFO of adc_data_2_tdata : signal is "xilinx.com:interface:axis:1.0 adc_data_2 TDATA"; 63 | attribute X_INTERFACE_PARAMETER of adc_data_2_tdata : signal is "XIL_INTERFACENAME adc_data_2, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 64 | begin 65 | adc_data_1_i_1(13 downto 0) <= adc_data_1_i(13 downto 0); 66 | adc_data_1_tdata(15 downto 0) <= ADC_0_adc_data_1_TDATA(15 downto 0); 67 | adc_data_1_tvalid <= ADC_0_adc_data_1_TVALID; 68 | adc_data_2_i_1(13 downto 0) <= adc_data_2_i(13 downto 0); 69 | adc_data_2_tdata(15 downto 0) <= ADC_0_adc_data_2_TDATA(15 downto 0); 70 | adc_data_2_tvalid <= ADC_0_adc_data_2_TVALID; 71 | clk_125_1 <= clk_125; 72 | resetn_1 <= resetn; 73 | ADC_0: component adc_bd_ADC_0_1 74 | port map ( 75 | adc_data_1_i(13 downto 0) => adc_data_1_i_1(13 downto 0), 76 | adc_data_1_tdata(15 downto 0) => ADC_0_adc_data_1_TDATA(15 downto 0), 77 | adc_data_1_tvalid => ADC_0_adc_data_1_TVALID, 78 | adc_data_2_i(13 downto 0) => adc_data_2_i_1(13 downto 0), 79 | adc_data_2_tdata(15 downto 0) => ADC_0_adc_data_2_TDATA(15 downto 0), 80 | adc_data_2_tvalid => ADC_0_adc_data_2_TVALID, 81 | clk_125 => clk_125_1, 82 | resetn => resetn_1 83 | ); 84 | end STRUCTURE; 85 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/src/adc_bd_ADC_0_1.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:ADC:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY adc_bd_ADC_0_1 IS 57 | PORT ( 58 | clk_125 : IN STD_LOGIC; 59 | resetn : IN STD_LOGIC; 60 | adc_data_1_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 61 | adc_data_2_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 62 | adc_data_1_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 63 | adc_data_2_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 64 | adc_data_1_tvalid : OUT STD_LOGIC; 65 | adc_data_2_tvalid : OUT STD_LOGIC 66 | ); 67 | END adc_bd_ADC_0_1; 68 | 69 | ARCHITECTURE adc_bd_ADC_0_1_arch OF adc_bd_ADC_0_1 IS 70 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 71 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF adc_bd_ADC_0_1_arch: ARCHITECTURE IS "yes"; 72 | COMPONENT ADC IS 73 | PORT ( 74 | clk_125 : IN STD_LOGIC; 75 | resetn : IN STD_LOGIC; 76 | adc_data_1_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 77 | adc_data_2_i : IN STD_LOGIC_VECTOR(13 DOWNTO 0); 78 | adc_data_1_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 79 | adc_data_2_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 80 | adc_data_1_tvalid : OUT STD_LOGIC; 81 | adc_data_2_tvalid : OUT STD_LOGIC 82 | ); 83 | END COMPONENT ADC; 84 | ATTRIBUTE X_CORE_INFO : STRING; 85 | ATTRIBUTE X_CORE_INFO OF adc_bd_ADC_0_1_arch: ARCHITECTURE IS "ADC,Vivado 2020.1"; 86 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 87 | ATTRIBUTE CHECK_LICENSE_TYPE OF adc_bd_ADC_0_1_arch : ARCHITECTURE IS "adc_bd_ADC_0_1,ADC,{}"; 88 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 89 | ATTRIBUTE CORE_GENERATION_INFO OF adc_bd_ADC_0_1_arch: ARCHITECTURE IS "adc_bd_ADC_0_1,ADC,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=ADC,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; 90 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 91 | ATTRIBUTE IP_DEFINITION_SOURCE OF adc_bd_ADC_0_1_arch: ARCHITECTURE IS "module_ref"; 92 | ATTRIBUTE X_INTERFACE_INFO : STRING; 93 | ATTRIBUTE X_INTERFACE_PARAMETER : STRING; 94 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_2_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_2 TVALID"; 95 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_1_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_1 TVALID"; 96 | ATTRIBUTE X_INTERFACE_PARAMETER OF adc_data_2_tdata: SIGNAL IS "XIL_INTERFACENAME adc_data_2, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 97 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_2_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_2 TDATA"; 98 | ATTRIBUTE X_INTERFACE_PARAMETER OF adc_data_1_tdata: SIGNAL IS "XIL_INTERFACENAME adc_data_1, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 99 | ATTRIBUTE X_INTERFACE_INFO OF adc_data_1_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 adc_data_1 TDATA"; 100 | ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0"; 101 | ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST"; 102 | BEGIN 103 | U0 : ADC 104 | PORT MAP ( 105 | clk_125 => clk_125, 106 | resetn => resetn, 107 | adc_data_1_i => adc_data_1_i, 108 | adc_data_2_i => adc_data_2_i, 109 | adc_data_1_tdata => adc_data_1_tdata, 110 | adc_data_2_tdata => adc_data_2_tdata, 111 | adc_data_1_tvalid => adc_data_1_tvalid, 112 | adc_data_2_tvalid => adc_data_2_tvalid 113 | ); 114 | END adc_bd_ADC_0_1_arch; 115 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/src/adc_bd_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name clk_125 -period 8 [get_ports clk_125] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/xgui/adc_bd_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-adc/xgui/adc_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | ipgui::add_param $IPINST -name "Ch1_Enabled" 5 | ipgui::add_param $IPINST -name "Ch2_Enabled" 6 | 7 | } 8 | 9 | proc update_PARAM_VALUE.Ch1_Enabled { PARAM_VALUE.Ch1_Enabled } { 10 | # Procedure called to update Ch1_Enabled when any of the dependent parameters in the arguments change 11 | } 12 | 13 | proc validate_PARAM_VALUE.Ch1_Enabled { PARAM_VALUE.Ch1_Enabled } { 14 | # Procedure called to validate Ch1_Enabled 15 | return true 16 | } 17 | 18 | proc update_PARAM_VALUE.Ch2_Enabled { PARAM_VALUE.Ch2_Enabled } { 19 | # Procedure called to update Ch2_Enabled when any of the dependent parameters in the arguments change 20 | } 21 | 22 | proc validate_PARAM_VALUE.Ch2_Enabled { PARAM_VALUE.Ch2_Enabled } { 23 | # Procedure called to validate Ch2_Enabled 24 | return true 25 | } 26 | 27 | 28 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/sim/clk_bd.vhd: -------------------------------------------------------------------------------- 1 | --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------- 3 | --Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 4 | --Date : Thu May 27 17:07:36 2021 5 | --Host : 5CD010B25T running 64-bit major release (build 9200) 6 | --Command : generate_target clk_bd.bd 7 | --Design : clk_bd 8 | --Purpose : IP block netlist 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | library UNISIM; 13 | use UNISIM.VCOMPONENTS.ALL; 14 | entity clk_bd is 15 | port ( 16 | adc_cdcs_o : out STD_LOGIC; 17 | adc_clk_n_i : in STD_LOGIC; 18 | adc_clk_p_i : in STD_LOGIC; 19 | clk_125 : out STD_LOGIC; 20 | clk_250 : out STD_LOGIC; 21 | clk_250_m45 : out STD_LOGIC; 22 | locked : out STD_LOGIC 23 | ); 24 | attribute CORE_GENERATION_INFO : string; 25 | attribute CORE_GENERATION_INFO of clk_bd : entity is "clk_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=clk_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; 26 | attribute HW_HANDOFF : string; 27 | attribute HW_HANDOFF of clk_bd : entity is "clk_bd.hwdef"; 28 | end clk_bd; 29 | 30 | architecture STRUCTURE of clk_bd is 31 | component clk_bd_clk_wiz_0_0 is 32 | port ( 33 | clk_in1_p : in STD_LOGIC; 34 | clk_in1_n : in STD_LOGIC; 35 | clk_125 : out STD_LOGIC; 36 | locked : out STD_LOGIC; 37 | clk_250 : out STD_LOGIC; 38 | clk_250_m45 : out STD_LOGIC 39 | ); 40 | end component clk_bd_clk_wiz_0_0; 41 | component clk_bd_clockStabilization_0_0 is 42 | port ( 43 | adc_cdcs_o : out STD_LOGIC 44 | ); 45 | end component clk_bd_clockStabilization_0_0; 46 | signal adc_clk_n_i_1 : STD_LOGIC; 47 | signal adc_clk_p_i_1 : STD_LOGIC; 48 | signal clk_wiz_0_clk_125 : STD_LOGIC; 49 | signal clk_wiz_0_clk_250 : STD_LOGIC; 50 | signal clk_wiz_0_clk_250_m45 : STD_LOGIC; 51 | signal clk_wiz_0_locked : STD_LOGIC; 52 | signal clockStabilization_0_adc_cdcs_o : STD_LOGIC; 53 | attribute X_INTERFACE_INFO : string; 54 | attribute X_INTERFACE_INFO of clk_125 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_125 CLK"; 55 | attribute X_INTERFACE_PARAMETER : string; 56 | attribute X_INTERFACE_PARAMETER of clk_125 : signal is "XIL_INTERFACENAME CLK.CLK_125, CLK_DOMAIN clk_bd_clk_wiz_0_0_clk_125, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0"; 57 | attribute X_INTERFACE_INFO of clk_250 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250 CLK"; 58 | attribute X_INTERFACE_PARAMETER of clk_250 : signal is "XIL_INTERFACENAME CLK.CLK_250, CLK_DOMAIN clk_bd_clk_wiz_0_0_clk_125, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0"; 59 | attribute X_INTERFACE_INFO of clk_250_m45 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250_M45 CLK"; 60 | attribute X_INTERFACE_PARAMETER of clk_250_m45 : signal is "XIL_INTERFACENAME CLK.CLK_250_M45, CLK_DOMAIN clk_bd_clk_wiz_0_0_clk_125, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE -45.0"; 61 | begin 62 | adc_cdcs_o <= clockStabilization_0_adc_cdcs_o; 63 | adc_clk_n_i_1 <= adc_clk_n_i; 64 | adc_clk_p_i_1 <= adc_clk_p_i; 65 | clk_125 <= clk_wiz_0_clk_125; 66 | clk_250 <= clk_wiz_0_clk_250; 67 | clk_250_m45 <= clk_wiz_0_clk_250_m45; 68 | locked <= clk_wiz_0_locked; 69 | clk_wiz_0: component clk_bd_clk_wiz_0_0 70 | port map ( 71 | clk_125 => clk_wiz_0_clk_125, 72 | clk_250 => clk_wiz_0_clk_250, 73 | clk_250_m45 => clk_wiz_0_clk_250_m45, 74 | clk_in1_n => adc_clk_n_i_1, 75 | clk_in1_p => adc_clk_p_i_1, 76 | locked => clk_wiz_0_locked 77 | ); 78 | clockStabilization_0: component clk_bd_clockStabilization_0_0 79 | port map ( 80 | adc_cdcs_o => clockStabilization_0_adc_cdcs_o 81 | ); 82 | end STRUCTURE; 83 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/sim/clk_bd_clockStabilization_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:clockStabilization:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY clk_bd_clockStabilization_0_0 IS 57 | PORT ( 58 | adc_cdcs_o : OUT STD_LOGIC 59 | ); 60 | END clk_bd_clockStabilization_0_0; 61 | 62 | ARCHITECTURE clk_bd_clockStabilization_0_0_arch OF clk_bd_clockStabilization_0_0 IS 63 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 64 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF clk_bd_clockStabilization_0_0_arch: ARCHITECTURE IS "yes"; 65 | COMPONENT clockStabilization IS 66 | PORT ( 67 | adc_cdcs_o : OUT STD_LOGIC 68 | ); 69 | END COMPONENT clockStabilization; 70 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 71 | ATTRIBUTE IP_DEFINITION_SOURCE OF clk_bd_clockStabilization_0_0_arch: ARCHITECTURE IS "module_ref"; 72 | BEGIN 73 | U0 : clockStabilization 74 | PORT MAP ( 75 | adc_cdcs_o => adc_cdcs_o 76 | ); 77 | END clk_bd_clockStabilization_0_0_arch; 78 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/sim/clk_bd_not_gate_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:not_gate:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY clk_bd_not_gate_0_0 IS 57 | PORT ( 58 | bit_i : IN STD_LOGIC; 59 | bit_o : OUT STD_LOGIC 60 | ); 61 | END clk_bd_not_gate_0_0; 62 | 63 | ARCHITECTURE clk_bd_not_gate_0_0_arch OF clk_bd_not_gate_0_0 IS 64 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 65 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF clk_bd_not_gate_0_0_arch: ARCHITECTURE IS "yes"; 66 | COMPONENT not_gate IS 67 | PORT ( 68 | bit_i : IN STD_LOGIC; 69 | bit_o : OUT STD_LOGIC 70 | ); 71 | END COMPONENT not_gate; 72 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 73 | ATTRIBUTE IP_DEFINITION_SOURCE OF clk_bd_not_gate_0_0_arch: ARCHITECTURE IS "module_ref"; 74 | BEGIN 75 | U0 : not_gate 76 | PORT MAP ( 77 | bit_i => bit_i, 78 | bit_o => bit_o 79 | ); 80 | END clk_bd_not_gate_0_0_arch; 81 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd.vhd: -------------------------------------------------------------------------------- 1 | --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------- 3 | --Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 4 | --Date : Thu May 27 17:07:36 2021 5 | --Host : 5CD010B25T running 64-bit major release (build 9200) 6 | --Command : generate_target clk_bd.bd 7 | --Design : clk_bd 8 | --Purpose : IP block netlist 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | library UNISIM; 13 | use UNISIM.VCOMPONENTS.ALL; 14 | entity clk_bd is 15 | port ( 16 | adc_cdcs_o : out STD_LOGIC; 17 | adc_clk_n_i : in STD_LOGIC; 18 | adc_clk_p_i : in STD_LOGIC; 19 | clk_125 : out STD_LOGIC; 20 | clk_250 : out STD_LOGIC; 21 | clk_250_m45 : out STD_LOGIC; 22 | locked : out STD_LOGIC 23 | ); 24 | attribute CORE_GENERATION_INFO : string; 25 | attribute CORE_GENERATION_INFO of clk_bd : entity is "clk_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=clk_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; 26 | attribute HW_HANDOFF : string; 27 | attribute HW_HANDOFF of clk_bd : entity is "clk_bd.hwdef"; 28 | end clk_bd; 29 | 30 | architecture STRUCTURE of clk_bd is 31 | component clk_bd_clk_wiz_0_0 is 32 | port ( 33 | clk_in1_p : in STD_LOGIC; 34 | clk_in1_n : in STD_LOGIC; 35 | clk_125 : out STD_LOGIC; 36 | locked : out STD_LOGIC; 37 | clk_250 : out STD_LOGIC; 38 | clk_250_m45 : out STD_LOGIC 39 | ); 40 | end component clk_bd_clk_wiz_0_0; 41 | component clk_bd_clockStabilization_0_0 is 42 | port ( 43 | adc_cdcs_o : out STD_LOGIC 44 | ); 45 | end component clk_bd_clockStabilization_0_0; 46 | signal adc_clk_n_i_1 : STD_LOGIC; 47 | signal adc_clk_p_i_1 : STD_LOGIC; 48 | signal clk_wiz_0_clk_125 : STD_LOGIC; 49 | signal clk_wiz_0_clk_250 : STD_LOGIC; 50 | signal clk_wiz_0_clk_250_m45 : STD_LOGIC; 51 | signal clk_wiz_0_locked : STD_LOGIC; 52 | signal clockStabilization_0_adc_cdcs_o : STD_LOGIC; 53 | attribute X_INTERFACE_INFO : string; 54 | attribute X_INTERFACE_INFO of clk_125 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_125 CLK"; 55 | attribute X_INTERFACE_PARAMETER : string; 56 | attribute X_INTERFACE_PARAMETER of clk_125 : signal is "XIL_INTERFACENAME CLK.CLK_125, CLK_DOMAIN clk_bd_clk_wiz_0_0_clk_125, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0"; 57 | attribute X_INTERFACE_INFO of clk_250 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250 CLK"; 58 | attribute X_INTERFACE_PARAMETER of clk_250 : signal is "XIL_INTERFACENAME CLK.CLK_250, CLK_DOMAIN clk_bd_clk_wiz_0_0_clk_125, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0"; 59 | attribute X_INTERFACE_INFO of clk_250_m45 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250_M45 CLK"; 60 | attribute X_INTERFACE_PARAMETER of clk_250_m45 : signal is "XIL_INTERFACENAME CLK.CLK_250_M45, CLK_DOMAIN clk_bd_clk_wiz_0_0_clk_125, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE -45.0"; 61 | begin 62 | adc_cdcs_o <= clockStabilization_0_adc_cdcs_o; 63 | adc_clk_n_i_1 <= adc_clk_n_i; 64 | adc_clk_p_i_1 <= adc_clk_p_i; 65 | clk_125 <= clk_wiz_0_clk_125; 66 | clk_250 <= clk_wiz_0_clk_250; 67 | clk_250_m45 <= clk_wiz_0_clk_250_m45; 68 | locked <= clk_wiz_0_locked; 69 | clk_wiz_0: component clk_bd_clk_wiz_0_0 70 | port map ( 71 | clk_125 => clk_wiz_0_clk_125, 72 | clk_250 => clk_wiz_0_clk_250, 73 | clk_250_m45 => clk_wiz_0_clk_250_m45, 74 | clk_in1_n => adc_clk_n_i_1, 75 | clk_in1_p => adc_clk_p_i_1, 76 | locked => clk_wiz_0_locked 77 | ); 78 | clockStabilization_0: component clk_bd_clockStabilization_0_0 79 | port map ( 80 | adc_cdcs_o => clockStabilization_0_adc_cdcs_o 81 | ); 82 | end STRUCTURE; 83 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_clockStabilization_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:clockStabilization:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY clk_bd_clockStabilization_0_0 IS 57 | PORT ( 58 | adc_cdcs_o : OUT STD_LOGIC 59 | ); 60 | END clk_bd_clockStabilization_0_0; 61 | 62 | ARCHITECTURE clk_bd_clockStabilization_0_0_arch OF clk_bd_clockStabilization_0_0 IS 63 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 64 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF clk_bd_clockStabilization_0_0_arch: ARCHITECTURE IS "yes"; 65 | COMPONENT clockStabilization IS 66 | PORT ( 67 | adc_cdcs_o : OUT STD_LOGIC 68 | ); 69 | END COMPONENT clockStabilization; 70 | ATTRIBUTE X_CORE_INFO : STRING; 71 | ATTRIBUTE X_CORE_INFO OF clk_bd_clockStabilization_0_0_arch: ARCHITECTURE IS "clockStabilization,Vivado 2020.1"; 72 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 73 | ATTRIBUTE CHECK_LICENSE_TYPE OF clk_bd_clockStabilization_0_0_arch : ARCHITECTURE IS "clk_bd_clockStabilization_0_0,clockStabilization,{}"; 74 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 75 | ATTRIBUTE CORE_GENERATION_INFO OF clk_bd_clockStabilization_0_0_arch: ARCHITECTURE IS "clk_bd_clockStabilization_0_0,clockStabilization,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=clockStabilization,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; 76 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 77 | ATTRIBUTE IP_DEFINITION_SOURCE OF clk_bd_clockStabilization_0_0_arch: ARCHITECTURE IS "module_ref"; 78 | BEGIN 79 | U0 : clockStabilization 80 | PORT MAP ( 81 | adc_cdcs_o => adc_cdcs_o 82 | ); 83 | END clk_bd_clockStabilization_0_0_arch; 84 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_not_gate_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:not_gate:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY clk_bd_not_gate_0_0 IS 57 | PORT ( 58 | bit_i : IN STD_LOGIC; 59 | bit_o : OUT STD_LOGIC 60 | ); 61 | END clk_bd_not_gate_0_0; 62 | 63 | ARCHITECTURE clk_bd_not_gate_0_0_arch OF clk_bd_not_gate_0_0 IS 64 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 65 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF clk_bd_not_gate_0_0_arch: ARCHITECTURE IS "yes"; 66 | COMPONENT not_gate IS 67 | PORT ( 68 | bit_i : IN STD_LOGIC; 69 | bit_o : OUT STD_LOGIC 70 | ); 71 | END COMPONENT not_gate; 72 | ATTRIBUTE X_CORE_INFO : STRING; 73 | ATTRIBUTE X_CORE_INFO OF clk_bd_not_gate_0_0_arch: ARCHITECTURE IS "not_gate,Vivado 2020.1"; 74 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 75 | ATTRIBUTE CHECK_LICENSE_TYPE OF clk_bd_not_gate_0_0_arch : ARCHITECTURE IS "clk_bd_not_gate_0_0,not_gate,{}"; 76 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 77 | ATTRIBUTE CORE_GENERATION_INFO OF clk_bd_not_gate_0_0_arch: ARCHITECTURE IS "clk_bd_not_gate_0_0,not_gate,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=not_gate,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; 78 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 79 | ATTRIBUTE IP_DEFINITION_SOURCE OF clk_bd_not_gate_0_0_arch: ARCHITECTURE IS "module_ref"; 80 | BEGIN 81 | U0 : not_gate 82 | PORT MAP ( 83 | bit_i => bit_i, 84 | bit_o => bit_o 85 | ); 86 | END clk_bd_not_gate_0_0_arch; 87 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | 10 | ################################################################################ -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_xlconstant_0_0/clk_bd_xlconstant_0_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | clk_bd_xlconstant_0_0 10 | 11 | 12 | 0x1 13 | 1 14 | 1 15 | 1 16 | clk_bd_xlconstant_0_0 17 | zynq 18 | redpitaya.com:redpitaya-125-14:part0:1.0 19 | 20 | xc7z010 21 | clg400 22 | VHDL 23 | 24 | MIXED 25 | -1 26 | 27 | 28 | TRUE 29 | TRUE 30 | IP_Integrator 31 | 7 32 | TRUE 33 | . 34 | 35 | ../../ipshared 36 | 2020.1 37 | GLOBAL 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_xlconstant_0_0/clk_bd_xlconstant_0_0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | customized_ip 5 | clk_bd_xlconstant_0_0 6 | 1.0 7 | 8 | 9 | 10 | dout 11 | 12 | out 13 | 14 | 0 15 | 0 16 | 17 | 18 | 19 | std_logic_vector 20 | dummy_view 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | CONST_WIDTH 29 | Const Width 30 | 1 31 | 32 | 33 | CONST_VAL 34 | Const Val 35 | 0x1 36 | 37 | 38 | 39 | Gives a constant signed value. 40 | 41 | 42 | Component_Name 43 | clk_bd_xlconstant_0_0 44 | 45 | 46 | CONST_WIDTH 47 | Const Width 48 | 1 49 | 50 | 51 | CONST_VAL 52 | Const Val 53 | 1 54 | 55 | 56 | 57 | 58 | Constant 59 | 7 60 | 61 | 62 | 2020.1 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_xlconstant_1_0/clk_bd_xlconstant_1_0.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | clk_bd_xlconstant_1_0 10 | 11 | 12 | 0x1 13 | 1 14 | 1 15 | 1 16 | clk_bd_xlconstant_1_0 17 | zynq 18 | redpitaya.com:redpitaya-125-14:part0:1.0 19 | 20 | xc7z010 21 | clg400 22 | VHDL 23 | 24 | MIXED 25 | -1 26 | 27 | 28 | TRUE 29 | TRUE 30 | IP_Integrator 31 | 7 32 | TRUE 33 | . 34 | 35 | ../../ipshared 36 | 2020.1 37 | GLOBAL 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clk_bd_xlconstant_1_0/clk_bd_xlconstant_1_0.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | customized_ip 5 | clk_bd_xlconstant_1_0 6 | 1.0 7 | 8 | 9 | 10 | dout 11 | 12 | out 13 | 14 | 0 15 | 0 16 | 17 | 18 | 19 | std_logic_vector 20 | dummy_view 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | CONST_WIDTH 29 | Const Width 30 | 1 31 | 32 | 33 | CONST_VAL 34 | Const Val 35 | 0x1 36 | 37 | 38 | 39 | Gives a constant signed value. 40 | 41 | 42 | Component_Name 43 | clk_bd_xlconstant_1_0 44 | 45 | 46 | CONST_WIDTH 47 | Const Width 48 | 1 49 | 50 | 51 | CONST_VAL 52 | Const Val 53 | 1 54 | 55 | 56 | 57 | 58 | Constant 59 | 7 60 | 61 | 62 | 2020.1 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/clockStabilization.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 25.05.2021 08:47:58 6 | -- Design Name: 7 | -- Module Name: clockStabilization - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity clockStabilization is 35 | Port ( adc_cdcs_o : out STD_LOGIC); 36 | end clockStabilization; 37 | 38 | architecture Behavioral of clockStabilization is 39 | 40 | begin 41 | 42 | adc_cdcs_o <= '1'; 43 | 44 | end Behavioral; 45 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/src/not_gate.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 24.05.2021 14:43:37 6 | -- Design Name: 7 | -- Module Name: not_gate - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | --library UNISIM; 32 | --use UNISIM.VComponents.all; 33 | 34 | entity not_gate is 35 | Port ( bit_i : in STD_LOGIC; 36 | bit_o : out STD_LOGIC); 37 | end not_gate; 38 | 39 | architecture Behavioral of not_gate is 40 | 41 | begin 42 | 43 | bit_o <= not bit_i; 44 | 45 | end Behavioral; 46 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/xgui/clk_bd_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-clk/xgui/clk_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | 5 | } 6 | 7 | 8 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/sim/dac_bd.vhd: -------------------------------------------------------------------------------- 1 | --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------- 3 | --Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 4 | --Date : Fri May 28 08:20:46 2021 5 | --Host : 5CD010B25T running 64-bit major release (build 9200) 6 | --Command : generate_target dac_bd.bd 7 | --Design : dac_bd 8 | --Purpose : IP block netlist 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | library UNISIM; 13 | use UNISIM.VCOMPONENTS.ALL; 14 | entity dac_bd is 15 | port ( 16 | clk_125 : in STD_LOGIC; 17 | clk_250 : in STD_LOGIC; 18 | clk_250_m45 : in STD_LOGIC; 19 | dac_clk_o : out STD_LOGIC; 20 | dac_data_1_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 21 | dac_data_1_tvalid : in STD_LOGIC; 22 | dac_data_2_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 23 | dac_data_2_tvalid : in STD_LOGIC; 24 | dac_data_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); 25 | dac_rst_o : out STD_LOGIC; 26 | dac_sel_o : out STD_LOGIC; 27 | dac_wrt_o : out STD_LOGIC; 28 | resetn : in STD_LOGIC 29 | ); 30 | attribute CORE_GENERATION_INFO : string; 31 | attribute CORE_GENERATION_INFO of dac_bd : entity is "dac_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=dac_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; 32 | attribute HW_HANDOFF : string; 33 | attribute HW_HANDOFF of dac_bd : entity is "dac_bd.hwdef"; 34 | end dac_bd; 35 | 36 | architecture STRUCTURE of dac_bd is 37 | component dac_bd_DAC_0_0 is 38 | port ( 39 | clk_125 : in STD_LOGIC; 40 | clk_250 : in STD_LOGIC; 41 | clk_250_m45 : in STD_LOGIC; 42 | resetn : in STD_LOGIC; 43 | dac_data_1_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 44 | dac_data_1_tvalid : in STD_LOGIC; 45 | dac_data_2_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 46 | dac_data_2_tvalid : in STD_LOGIC; 47 | dac_data_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); 48 | dac_clk_o : out STD_LOGIC; 49 | dac_wrt_o : out STD_LOGIC; 50 | dac_sel_o : out STD_LOGIC; 51 | dac_rst_o : out STD_LOGIC 52 | ); 53 | end component dac_bd_DAC_0_0; 54 | signal DAC_0_dac_clk_o : STD_LOGIC; 55 | signal DAC_0_dac_data_o : STD_LOGIC_VECTOR ( 13 downto 0 ); 56 | signal DAC_0_dac_rst_o : STD_LOGIC; 57 | signal DAC_0_dac_sel_o : STD_LOGIC; 58 | signal DAC_0_dac_wrt_o : STD_LOGIC; 59 | signal clk_1 : STD_LOGIC; 60 | signal clk_dac_250_1 : STD_LOGIC; 61 | signal clk_dac_250_m45_1 : STD_LOGIC; 62 | signal dac_data_1_1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 63 | signal dac_data_1_1_TVALID : STD_LOGIC; 64 | signal dac_data_2_1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 65 | signal dac_data_2_1_TVALID : STD_LOGIC; 66 | signal resetn_1 : STD_LOGIC; 67 | attribute X_INTERFACE_INFO : string; 68 | attribute X_INTERFACE_INFO of clk_125 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_125 CLK"; 69 | attribute X_INTERFACE_PARAMETER : string; 70 | attribute X_INTERFACE_PARAMETER of clk_125 : signal is "XIL_INTERFACENAME CLK.CLK_125, ASSOCIATED_BUSIF dac_data_1:dac_data_2, ASSOCIATED_RESET resetn, CLK_DOMAIN dac_bd_clk, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000"; 71 | attribute X_INTERFACE_INFO of clk_250 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250 CLK"; 72 | attribute X_INTERFACE_PARAMETER of clk_250 : signal is "XIL_INTERFACENAME CLK.CLK_250, CLK_DOMAIN dac_bd_clk_dac_250, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000"; 73 | attribute X_INTERFACE_INFO of clk_250_m45 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250_M45 CLK"; 74 | attribute X_INTERFACE_PARAMETER of clk_250_m45 : signal is "XIL_INTERFACENAME CLK.CLK_250_M45, CLK_DOMAIN dac_bd_clk_dac_250_m45, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE -45"; 75 | attribute X_INTERFACE_INFO of dac_data_1_tvalid : signal is "xilinx.com:interface:axis:1.0 dac_data_1 TVALID"; 76 | attribute X_INTERFACE_INFO of dac_data_2_tvalid : signal is "xilinx.com:interface:axis:1.0 dac_data_2 TVALID"; 77 | attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST"; 78 | attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW"; 79 | attribute X_INTERFACE_INFO of dac_data_1_tdata : signal is "xilinx.com:interface:axis:1.0 dac_data_1 TDATA"; 80 | attribute X_INTERFACE_PARAMETER of dac_data_1_tdata : signal is "XIL_INTERFACENAME dac_data_1, CLK_DOMAIN dac_bd_clk, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 81 | attribute X_INTERFACE_INFO of dac_data_2_tdata : signal is "xilinx.com:interface:axis:1.0 dac_data_2 TDATA"; 82 | attribute X_INTERFACE_PARAMETER of dac_data_2_tdata : signal is "XIL_INTERFACENAME dac_data_2, CLK_DOMAIN dac_bd_clk, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 83 | begin 84 | clk_1 <= clk_125; 85 | clk_dac_250_1 <= clk_250; 86 | clk_dac_250_m45_1 <= clk_250_m45; 87 | dac_clk_o <= DAC_0_dac_clk_o; 88 | dac_data_1_1_TDATA(15 downto 0) <= dac_data_1_tdata(15 downto 0); 89 | dac_data_1_1_TVALID <= dac_data_1_tvalid; 90 | dac_data_2_1_TDATA(15 downto 0) <= dac_data_2_tdata(15 downto 0); 91 | dac_data_2_1_TVALID <= dac_data_2_tvalid; 92 | dac_data_o(13 downto 0) <= DAC_0_dac_data_o(13 downto 0); 93 | dac_rst_o <= DAC_0_dac_rst_o; 94 | dac_sel_o <= DAC_0_dac_sel_o; 95 | dac_wrt_o <= DAC_0_dac_wrt_o; 96 | resetn_1 <= resetn; 97 | DAC_0: component dac_bd_DAC_0_0 98 | port map ( 99 | clk_125 => clk_1, 100 | clk_250 => clk_dac_250_1, 101 | clk_250_m45 => clk_dac_250_m45_1, 102 | dac_clk_o => DAC_0_dac_clk_o, 103 | dac_data_1_tdata(15 downto 0) => dac_data_1_1_TDATA(15 downto 0), 104 | dac_data_1_tvalid => dac_data_1_1_TVALID, 105 | dac_data_2_tdata(15 downto 0) => dac_data_2_1_TDATA(15 downto 0), 106 | dac_data_2_tvalid => dac_data_2_1_TVALID, 107 | dac_data_o(13 downto 0) => DAC_0_dac_data_o(13 downto 0), 108 | dac_rst_o => DAC_0_dac_rst_o, 109 | dac_sel_o => DAC_0_dac_sel_o, 110 | dac_wrt_o => DAC_0_dac_wrt_o, 111 | resetn => resetn_1 112 | ); 113 | end STRUCTURE; 114 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/sim/dac_bd_DAC_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:DAC:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY dac_bd_DAC_0_0 IS 57 | PORT ( 58 | clk_125 : IN STD_LOGIC; 59 | clk_250 : IN STD_LOGIC; 60 | clk_250_m45 : IN STD_LOGIC; 61 | resetn : IN STD_LOGIC; 62 | dac_data_1_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 63 | dac_data_1_tvalid : IN STD_LOGIC; 64 | dac_data_2_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 65 | dac_data_2_tvalid : IN STD_LOGIC; 66 | dac_data_o : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); 67 | dac_clk_o : OUT STD_LOGIC; 68 | dac_wrt_o : OUT STD_LOGIC; 69 | dac_sel_o : OUT STD_LOGIC; 70 | dac_rst_o : OUT STD_LOGIC 71 | ); 72 | END dac_bd_DAC_0_0; 73 | 74 | ARCHITECTURE dac_bd_DAC_0_0_arch OF dac_bd_DAC_0_0 IS 75 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 76 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF dac_bd_DAC_0_0_arch: ARCHITECTURE IS "yes"; 77 | COMPONENT DAC IS 78 | PORT ( 79 | clk_125 : IN STD_LOGIC; 80 | clk_250 : IN STD_LOGIC; 81 | clk_250_m45 : IN STD_LOGIC; 82 | resetn : IN STD_LOGIC; 83 | dac_data_1_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 84 | dac_data_1_tvalid : IN STD_LOGIC; 85 | dac_data_2_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 86 | dac_data_2_tvalid : IN STD_LOGIC; 87 | dac_data_o : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); 88 | dac_clk_o : OUT STD_LOGIC; 89 | dac_wrt_o : OUT STD_LOGIC; 90 | dac_sel_o : OUT STD_LOGIC; 91 | dac_rst_o : OUT STD_LOGIC 92 | ); 93 | END COMPONENT DAC; 94 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 95 | ATTRIBUTE IP_DEFINITION_SOURCE OF dac_bd_DAC_0_0_arch: ARCHITECTURE IS "module_ref"; 96 | ATTRIBUTE X_INTERFACE_INFO : STRING; 97 | ATTRIBUTE X_INTERFACE_PARAMETER : STRING; 98 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_2_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_2 TVALID"; 99 | ATTRIBUTE X_INTERFACE_PARAMETER OF dac_data_2_tdata: SIGNAL IS "XIL_INTERFACENAME dac_data_2, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 100 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_2_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_2 TDATA"; 101 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_1_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_1 TVALID"; 102 | ATTRIBUTE X_INTERFACE_PARAMETER OF dac_data_1_tdata: SIGNAL IS "XIL_INTERFACENAME dac_data_1, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 103 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_1_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_1 TDATA"; 104 | ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0"; 105 | ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST"; 106 | BEGIN 107 | U0 : DAC 108 | PORT MAP ( 109 | clk_125 => clk_125, 110 | clk_250 => clk_250, 111 | clk_250_m45 => clk_250_m45, 112 | resetn => resetn, 113 | dac_data_1_tdata => dac_data_1_tdata, 114 | dac_data_1_tvalid => dac_data_1_tvalid, 115 | dac_data_2_tdata => dac_data_2_tdata, 116 | dac_data_2_tvalid => dac_data_2_tvalid, 117 | dac_data_o => dac_data_o, 118 | dac_clk_o => dac_clk_o, 119 | dac_wrt_o => dac_wrt_o, 120 | dac_sel_o => dac_sel_o, 121 | dac_rst_o => dac_rst_o 122 | ); 123 | END dac_bd_DAC_0_0_arch; 124 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/src/DAC.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 21.05.2021 08:39:37 6 | -- Design Name: 7 | -- Module Name: DAC - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | 25 | -- Uncomment the following library declaration if using 26 | -- arithmetic functions with Signed or Unsigned values 27 | --use IEEE.NUMERIC_STD.ALL; 28 | 29 | -- Uncomment the following library declaration if instantiating 30 | -- any Xilinx leaf cells in this code. 31 | library UNISIM; 32 | use UNISIM.VComponents.all; 33 | 34 | entity DAC is 35 | Port ( clk_125 : in STD_LOGIC; 36 | clk_250 : in STD_LOGIC; 37 | clk_250_m45 : in STD_LOGIC; 38 | resetn : in STD_LOGIC; 39 | dac_data_1_tdata : in STD_LOGIC_VECTOR (15 downto 0); 40 | dac_data_1_tvalid : in STD_LOGIC; 41 | dac_data_2_tdata : in STD_LOGIC_VECTOR (15 downto 0); 42 | dac_data_2_tvalid : in STD_LOGIC; 43 | dac_data_o : out STD_LOGIC_VECTOR (13 downto 0); 44 | dac_clk_o: out STD_LOGIC; 45 | dac_wrt_o: out STD_LOGIC; 46 | dac_sel_o: out STD_LOGIC; 47 | dac_rst_o: out STD_LOGIC); 48 | end DAC; 49 | 50 | architecture Behavioral of DAC is 51 | signal dac_rst : STD_LOGIC :='0'; 52 | signal dac_data_1 : STD_LOGIC_VECTOR (13 downto 0):= (13 => '0', others=>'1'); 53 | signal dac_data_2 : STD_LOGIC_VECTOR (13 downto 0):= (13 => '0', others=>'1'); 54 | begin 55 | 56 | process(clk_125) 57 | begin 58 | if rising_edge(clk_125) then 59 | if resetn='0' then 60 | dac_rst <= '1'; 61 | dac_data_1 <= (13 => '0', others=>'1'); 62 | dac_data_2 <= (13 => '0', others=>'1'); 63 | else 64 | dac_rst <= '0'; 65 | 66 | if dac_data_1_tvalid='1' then 67 | dac_data_1(13) <= dac_data_1_tdata(15); 68 | dac_data_1(12 downto 0) <= not dac_data_1_tdata(14 downto 2); 69 | end if; 70 | 71 | if dac_data_2_tvalid='1' then 72 | dac_data_2(13) <= dac_data_2_tdata(15); 73 | dac_data_2(12 downto 0) <= not dac_data_2_tdata(14 downto 2); 74 | end if; 75 | 76 | end if; 77 | end if; 78 | 79 | end process; 80 | 81 | 82 | ODDR_dac_clk : ODDR 83 | generic map( 84 | DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 85 | INIT => '0', -- Initial value for Q port ('1' or '0') 86 | SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") 87 | port map ( 88 | Q => dac_clk_o, -- 1-bit DDR output 89 | C => clk_250_m45, -- 1-bit clock input 90 | CE => '1', -- 1-bit clock enable input 91 | D1 => '0', -- 1-bit data input (positive edge) 92 | D2 => '1', -- 1-bit data input (negative edge) 93 | R => '0', -- 1-bit reset input 94 | S => '0' -- 1-bit set input 95 | ); 96 | 97 | ODDR_dac_wrt : ODDR 98 | generic map( 99 | DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 100 | INIT => '0', -- Initial value for Q port ('1' or '0') 101 | SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") 102 | port map ( 103 | Q => dac_wrt_o, -- 1-bit DDR output 104 | C => clk_250, -- 1-bit clock input 105 | CE => '1', -- 1-bit clock enable input 106 | D1 => '0', -- 1-bit data input (positive edge) 107 | D2 => '1', -- 1-bit data input (negative edge) 108 | R => '0', -- 1-bit reset input 109 | S => '0' -- 1-bit set input 110 | ); 111 | 112 | ODDR_dac_sel : ODDR 113 | generic map( 114 | DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 115 | INIT => '0', -- Initial value for Q port ('1' or '0') 116 | SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") 117 | port map ( 118 | Q => dac_sel_o, -- 1-bit DDR output 119 | C => clk_125, -- 1-bit clock input 120 | CE => '1', -- 1-bit clock enable input 121 | D1 => '1', -- 1-bit data input (positive edge) 122 | D2 => '0', -- 1-bit data input (negative edge) 123 | R => '0', -- 1-bit reset input 124 | S => '0' -- 1-bit set input 125 | ); 126 | ODDR_dac_rst : ODDR 127 | generic map( 128 | DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 129 | INIT => '0', -- Initial value for Q port ('1' or '0') 130 | SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") 131 | port map ( 132 | Q => dac_rst_o, -- 1-bit DDR output 133 | C => clk_125, -- 1-bit clock input 134 | CE => '1', -- 1-bit clock enable input 135 | D1 => dac_rst, -- 1-bit data input (positive edge) 136 | D2 => dac_rst, -- 1-bit data input (negative edge) 137 | R => '0', -- 1-bit reset input 138 | S => '0' -- 1-bit set input 139 | ); 140 | 141 | GEN_ODDR_dac_data: for i in 0 to 13 generate 142 | ODDR_dac_data : ODDR 143 | generic map( 144 | DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 145 | INIT => '0', -- Initial value for Q port ('1' or '0') 146 | SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") 147 | port map ( 148 | Q => dac_data_o(i), -- 1-bit DDR output 149 | C => clk_125, -- 1-bit clock input 150 | CE => '1', -- 1-bit clock enable input 151 | D1 => dac_data_2(i), -- 1-bit data input (positive edge) 152 | D2 => dac_data_1(i), -- 1-bit data input (negative edge) 153 | R => '0', -- 1-bit reset input 154 | S => '0' -- 1-bit set input 155 | ); 156 | end generate GEN_ODDR_dac_data; 157 | 158 | end Behavioral; 159 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/src/dac_bd.vhd: -------------------------------------------------------------------------------- 1 | --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 2 | ---------------------------------------------------------------------------------- 3 | --Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020 4 | --Date : Fri May 28 08:20:46 2021 5 | --Host : 5CD010B25T running 64-bit major release (build 9200) 6 | --Command : generate_target dac_bd.bd 7 | --Design : dac_bd 8 | --Purpose : IP block netlist 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | library UNISIM; 13 | use UNISIM.VCOMPONENTS.ALL; 14 | entity dac_bd is 15 | port ( 16 | clk_125 : in STD_LOGIC; 17 | clk_250 : in STD_LOGIC; 18 | clk_250_m45 : in STD_LOGIC; 19 | dac_clk_o : out STD_LOGIC; 20 | dac_data_1_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 21 | dac_data_1_tvalid : in STD_LOGIC; 22 | dac_data_2_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 23 | dac_data_2_tvalid : in STD_LOGIC; 24 | dac_data_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); 25 | dac_rst_o : out STD_LOGIC; 26 | dac_sel_o : out STD_LOGIC; 27 | dac_wrt_o : out STD_LOGIC; 28 | resetn : in STD_LOGIC 29 | ); 30 | attribute CORE_GENERATION_INFO : string; 31 | attribute CORE_GENERATION_INFO of dac_bd : entity is "dac_bd,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=dac_bd,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=1,numReposBlks=1,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}"; 32 | attribute HW_HANDOFF : string; 33 | attribute HW_HANDOFF of dac_bd : entity is "dac_bd.hwdef"; 34 | end dac_bd; 35 | 36 | architecture STRUCTURE of dac_bd is 37 | component dac_bd_DAC_0_0 is 38 | port ( 39 | clk_125 : in STD_LOGIC; 40 | clk_250 : in STD_LOGIC; 41 | clk_250_m45 : in STD_LOGIC; 42 | resetn : in STD_LOGIC; 43 | dac_data_1_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 44 | dac_data_1_tvalid : in STD_LOGIC; 45 | dac_data_2_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); 46 | dac_data_2_tvalid : in STD_LOGIC; 47 | dac_data_o : out STD_LOGIC_VECTOR ( 13 downto 0 ); 48 | dac_clk_o : out STD_LOGIC; 49 | dac_wrt_o : out STD_LOGIC; 50 | dac_sel_o : out STD_LOGIC; 51 | dac_rst_o : out STD_LOGIC 52 | ); 53 | end component dac_bd_DAC_0_0; 54 | signal DAC_0_dac_clk_o : STD_LOGIC; 55 | signal DAC_0_dac_data_o : STD_LOGIC_VECTOR ( 13 downto 0 ); 56 | signal DAC_0_dac_rst_o : STD_LOGIC; 57 | signal DAC_0_dac_sel_o : STD_LOGIC; 58 | signal DAC_0_dac_wrt_o : STD_LOGIC; 59 | signal clk_1 : STD_LOGIC; 60 | signal clk_dac_250_1 : STD_LOGIC; 61 | signal clk_dac_250_m45_1 : STD_LOGIC; 62 | signal dac_data_1_1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 63 | signal dac_data_1_1_TVALID : STD_LOGIC; 64 | signal dac_data_2_1_TDATA : STD_LOGIC_VECTOR ( 15 downto 0 ); 65 | signal dac_data_2_1_TVALID : STD_LOGIC; 66 | signal resetn_1 : STD_LOGIC; 67 | attribute X_INTERFACE_INFO : string; 68 | attribute X_INTERFACE_INFO of clk_125 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_125 CLK"; 69 | attribute X_INTERFACE_PARAMETER : string; 70 | attribute X_INTERFACE_PARAMETER of clk_125 : signal is "XIL_INTERFACENAME CLK.CLK_125, ASSOCIATED_BUSIF dac_data_1:dac_data_2, ASSOCIATED_RESET resetn, CLK_DOMAIN dac_bd_clk, FREQ_HZ 125000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000"; 71 | attribute X_INTERFACE_INFO of clk_250 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250 CLK"; 72 | attribute X_INTERFACE_PARAMETER of clk_250 : signal is "XIL_INTERFACENAME CLK.CLK_250, CLK_DOMAIN dac_bd_clk_dac_250, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000"; 73 | attribute X_INTERFACE_INFO of clk_250_m45 : signal is "xilinx.com:signal:clock:1.0 CLK.CLK_250_M45 CLK"; 74 | attribute X_INTERFACE_PARAMETER of clk_250_m45 : signal is "XIL_INTERFACENAME CLK.CLK_250_M45, CLK_DOMAIN dac_bd_clk_dac_250_m45, FREQ_HZ 250000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE -45"; 75 | attribute X_INTERFACE_INFO of dac_data_1_tvalid : signal is "xilinx.com:interface:axis:1.0 dac_data_1 TVALID"; 76 | attribute X_INTERFACE_INFO of dac_data_2_tvalid : signal is "xilinx.com:interface:axis:1.0 dac_data_2 TVALID"; 77 | attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST"; 78 | attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW"; 79 | attribute X_INTERFACE_INFO of dac_data_1_tdata : signal is "xilinx.com:interface:axis:1.0 dac_data_1 TDATA"; 80 | attribute X_INTERFACE_PARAMETER of dac_data_1_tdata : signal is "XIL_INTERFACENAME dac_data_1, CLK_DOMAIN dac_bd_clk, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 81 | attribute X_INTERFACE_INFO of dac_data_2_tdata : signal is "xilinx.com:interface:axis:1.0 dac_data_2 TDATA"; 82 | attribute X_INTERFACE_PARAMETER of dac_data_2_tdata : signal is "XIL_INTERFACENAME dac_data_2, CLK_DOMAIN dac_bd_clk, FREQ_HZ 125000000, HAS_TKEEP 0, HAS_TLAST 0, HAS_TREADY 0, HAS_TSTRB 0, INSERT_VIP 0, LAYERED_METADATA undef, PHASE 0.000, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0"; 83 | begin 84 | clk_1 <= clk_125; 85 | clk_dac_250_1 <= clk_250; 86 | clk_dac_250_m45_1 <= clk_250_m45; 87 | dac_clk_o <= DAC_0_dac_clk_o; 88 | dac_data_1_1_TDATA(15 downto 0) <= dac_data_1_tdata(15 downto 0); 89 | dac_data_1_1_TVALID <= dac_data_1_tvalid; 90 | dac_data_2_1_TDATA(15 downto 0) <= dac_data_2_tdata(15 downto 0); 91 | dac_data_2_1_TVALID <= dac_data_2_tvalid; 92 | dac_data_o(13 downto 0) <= DAC_0_dac_data_o(13 downto 0); 93 | dac_rst_o <= DAC_0_dac_rst_o; 94 | dac_sel_o <= DAC_0_dac_sel_o; 95 | dac_wrt_o <= DAC_0_dac_wrt_o; 96 | resetn_1 <= resetn; 97 | DAC_0: component dac_bd_DAC_0_0 98 | port map ( 99 | clk_125 => clk_1, 100 | clk_250 => clk_dac_250_1, 101 | clk_250_m45 => clk_dac_250_m45_1, 102 | dac_clk_o => DAC_0_dac_clk_o, 103 | dac_data_1_tdata(15 downto 0) => dac_data_1_1_TDATA(15 downto 0), 104 | dac_data_1_tvalid => dac_data_1_1_TVALID, 105 | dac_data_2_tdata(15 downto 0) => dac_data_2_1_TDATA(15 downto 0), 106 | dac_data_2_tvalid => dac_data_2_1_TVALID, 107 | dac_data_o(13 downto 0) => DAC_0_dac_data_o(13 downto 0), 108 | dac_rst_o => DAC_0_dac_rst_o, 109 | dac_sel_o => DAC_0_dac_sel_o, 110 | dac_wrt_o => DAC_0_dac_wrt_o, 111 | resetn => resetn_1 112 | ); 113 | end STRUCTURE; 114 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/src/dac_bd_DAC_0_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:module_ref:DAC:1.0 50 | -- IP Revision: 1 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | ENTITY dac_bd_DAC_0_0 IS 57 | PORT ( 58 | clk_125 : IN STD_LOGIC; 59 | clk_250 : IN STD_LOGIC; 60 | clk_250_m45 : IN STD_LOGIC; 61 | resetn : IN STD_LOGIC; 62 | dac_data_1_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 63 | dac_data_1_tvalid : IN STD_LOGIC; 64 | dac_data_2_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 65 | dac_data_2_tvalid : IN STD_LOGIC; 66 | dac_data_o : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); 67 | dac_clk_o : OUT STD_LOGIC; 68 | dac_wrt_o : OUT STD_LOGIC; 69 | dac_sel_o : OUT STD_LOGIC; 70 | dac_rst_o : OUT STD_LOGIC 71 | ); 72 | END dac_bd_DAC_0_0; 73 | 74 | ARCHITECTURE dac_bd_DAC_0_0_arch OF dac_bd_DAC_0_0 IS 75 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 76 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF dac_bd_DAC_0_0_arch: ARCHITECTURE IS "yes"; 77 | COMPONENT DAC IS 78 | PORT ( 79 | clk_125 : IN STD_LOGIC; 80 | clk_250 : IN STD_LOGIC; 81 | clk_250_m45 : IN STD_LOGIC; 82 | resetn : IN STD_LOGIC; 83 | dac_data_1_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 84 | dac_data_1_tvalid : IN STD_LOGIC; 85 | dac_data_2_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 86 | dac_data_2_tvalid : IN STD_LOGIC; 87 | dac_data_o : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); 88 | dac_clk_o : OUT STD_LOGIC; 89 | dac_wrt_o : OUT STD_LOGIC; 90 | dac_sel_o : OUT STD_LOGIC; 91 | dac_rst_o : OUT STD_LOGIC 92 | ); 93 | END COMPONENT DAC; 94 | ATTRIBUTE X_CORE_INFO : STRING; 95 | ATTRIBUTE X_CORE_INFO OF dac_bd_DAC_0_0_arch: ARCHITECTURE IS "DAC,Vivado 2020.1"; 96 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 97 | ATTRIBUTE CHECK_LICENSE_TYPE OF dac_bd_DAC_0_0_arch : ARCHITECTURE IS "dac_bd_DAC_0_0,DAC,{}"; 98 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 99 | ATTRIBUTE CORE_GENERATION_INFO OF dac_bd_DAC_0_0_arch: ARCHITECTURE IS "dac_bd_DAC_0_0,DAC,{x_ipProduct=Vivado 2020.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=DAC,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; 100 | ATTRIBUTE IP_DEFINITION_SOURCE : STRING; 101 | ATTRIBUTE IP_DEFINITION_SOURCE OF dac_bd_DAC_0_0_arch: ARCHITECTURE IS "module_ref"; 102 | ATTRIBUTE X_INTERFACE_INFO : STRING; 103 | ATTRIBUTE X_INTERFACE_PARAMETER : STRING; 104 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_2_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_2 TVALID"; 105 | ATTRIBUTE X_INTERFACE_PARAMETER OF dac_data_2_tdata: SIGNAL IS "XIL_INTERFACENAME dac_data_2, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 106 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_2_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_2 TDATA"; 107 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_1_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_1 TVALID"; 108 | ATTRIBUTE X_INTERFACE_PARAMETER OF dac_data_1_tdata: SIGNAL IS "XIL_INTERFACENAME dac_data_1, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; 109 | ATTRIBUTE X_INTERFACE_INFO OF dac_data_1_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 dac_data_1 TDATA"; 110 | ATTRIBUTE X_INTERFACE_PARAMETER OF resetn: SIGNAL IS "XIL_INTERFACENAME resetn, POLARITY ACTIVE_LOW, INSERT_VIP 0"; 111 | ATTRIBUTE X_INTERFACE_INFO OF resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 resetn RST"; 112 | BEGIN 113 | U0 : DAC 114 | PORT MAP ( 115 | clk_125 => clk_125, 116 | clk_250 => clk_250, 117 | clk_250_m45 => clk_250_m45, 118 | resetn => resetn, 119 | dac_data_1_tdata => dac_data_1_tdata, 120 | dac_data_1_tvalid => dac_data_1_tvalid, 121 | dac_data_2_tdata => dac_data_2_tdata, 122 | dac_data_2_tvalid => dac_data_2_tvalid, 123 | dac_data_o => dac_data_o, 124 | dac_clk_o => dac_clk_o, 125 | dac_wrt_o => dac_wrt_o, 126 | dac_sel_o => dac_sel_o, 127 | dac_rst_o => dac_rst_o 128 | ); 129 | END dac_bd_DAC_0_0_arch; 130 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/src/dac_bd_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name clk_125 -period 8 [get_ports clk_125] 10 | create_clock -name clk_250 -period 4 [get_ports clk_250] 11 | create_clock -name clk_250_m45 -period 4 [get_ports clk_250_m45] 12 | 13 | ################################################################################ -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/xgui/dac_bd_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /ip/Redpitaya-125-14-dac/xgui/dac_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | ipgui::add_param $IPINST -name "Ch1_Enabled" 5 | ipgui::add_param $IPINST -name "Ch2_Enabled" 6 | 7 | } 8 | 9 | proc update_PARAM_VALUE.Ch1_Enabled { PARAM_VALUE.Ch1_Enabled } { 10 | # Procedure called to update Ch1_Enabled when any of the dependent parameters in the arguments change 11 | } 12 | 13 | proc validate_PARAM_VALUE.Ch1_Enabled { PARAM_VALUE.Ch1_Enabled } { 14 | # Procedure called to validate Ch1_Enabled 15 | return true 16 | } 17 | 18 | proc update_PARAM_VALUE.Ch2_Enabled { PARAM_VALUE.Ch2_Enabled } { 19 | # Procedure called to update Ch2_Enabled when any of the dependent parameters in the arguments change 20 | } 21 | 22 | proc validate_PARAM_VALUE.Ch2_Enabled { PARAM_VALUE.Ch2_Enabled } { 23 | # Procedure called to validate Ch2_Enabled 24 | return true 25 | } 26 | 27 | 28 | -------------------------------------------------------------------------------- /jupyter_notebooks/LED_blink.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" 11 | }, 12 | "metadata": {}, 13 | "output_type": "display_data" 14 | }, 15 | { 16 | "data": { 17 | "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" 18 | }, 19 | "metadata": {}, 20 | "output_type": "display_data" 21 | } 22 | ], 23 | "source": [ 24 | "import pynq\n", 25 | "pynq.PL.reset()\n", 26 | "ol = pynq.Overlay(\"LED_blink.bit\")" 27 | ] 28 | }, 29 | { 30 | "cell_type": "code", 31 | "execution_count": 2, 32 | "metadata": {}, 33 | "outputs": [], 34 | "source": [ 35 | "blinkFreq = 1\n", 36 | "clkFreq = 50e6\n", 37 | "incr = int(2**32 * blinkFreq / clkFreq)\n", 38 | "\n", 39 | "#Enable counter\n", 40 | "ol.axi_gpio_0.channel1.write(val=1, mask=0x1)\n", 41 | "\n", 42 | "#Set counter increment\n", 43 | "ol.axi_gpio_0.channel2.write(val=incr, mask=0xffffffff)" 44 | ] 45 | } 46 | ], 47 | "metadata": { 48 | "kernelspec": { 49 | "display_name": "Python 3", 50 | "language": "python", 51 | "name": "python3" 52 | }, 53 | "language_info": { 54 | "codemirror_mode": { 55 | "name": "ipython", 56 | "version": 3 57 | }, 58 | "file_extension": ".py", 59 | "mimetype": "text/x-python", 60 | "name": "python", 61 | "nbconvert_exporter": "python", 62 | "pygments_lexer": "ipython3", 63 | "version": "3.7.6" 64 | } 65 | }, 66 | "nbformat": 4, 67 | "nbformat_minor": 2 68 | } 69 | -------------------------------------------------------------------------------- /jupyter_notebooks/analog_echo.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" 11 | }, 12 | "metadata": {}, 13 | "output_type": "display_data" 14 | }, 15 | { 16 | "data": { 17 | "application/javascript": "\ntry {\nrequire(['notebook/js/codecell'], function(codecell) {\n codecell.CodeCell.options_default.highlight_modes[\n 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n Jupyter.notebook.get_cells().map(function(cell){\n if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n });\n});\n} catch (e) {};\n" 18 | }, 19 | "metadata": {}, 20 | "output_type": "display_data" 21 | } 22 | ], 23 | "source": [ 24 | "import pynq\n", 25 | "pynq.PL.reset()\n", 26 | "ol = pynq.Overlay(\"analog_echo.bit\")" 27 | ] 28 | }, 29 | { 30 | "cell_type": "code", 31 | "execution_count": 2, 32 | "metadata": {}, 33 | "outputs": [], 34 | "source": [ 35 | "offset_1 = -0.50 #Volts\n", 36 | "offset_2 = +0.25 #Volts\n", 37 | "\n", 38 | "offset_1 = int(offset_1 * (2**15 - 1))\n", 39 | "offset_2 = int(offset_2 * (2**15 - 1))\n", 40 | "\n", 41 | "ol.axi_gpio_0.channel1.write(val=offset_1, mask=0xffff)\n", 42 | "ol.axi_gpio_0.channel2.write(val=offset_2, mask=0xffff)" 43 | ] 44 | }, 45 | { 46 | "cell_type": "code", 47 | "execution_count": null, 48 | "metadata": {}, 49 | "outputs": [], 50 | "source": [] 51 | } 52 | ], 53 | "metadata": { 54 | "kernelspec": { 55 | "display_name": "Python 3", 56 | "language": "python", 57 | "name": "python3" 58 | }, 59 | "language_info": { 60 | "codemirror_mode": { 61 | "name": "ipython", 62 | "version": 3 63 | }, 64 | "file_extension": ".py", 65 | "mimetype": "text/x-python", 66 | "name": "python", 67 | "nbconvert_exporter": "python", 68 | "pygments_lexer": "ipython3", 69 | "version": "3.9.13" 70 | }, 71 | "vscode": { 72 | "interpreter": { 73 | "hash": "dcd071082c88591d23e2c8aa1da83107454076a0ea29b622b71c0c444fc010b4" 74 | } 75 | } 76 | }, 77 | "nbformat": 4, 78 | "nbformat_minor": 2 79 | } 80 | -------------------------------------------------------------------------------- /sdc/redpitaya-125-14.xdc: -------------------------------------------------------------------------------- 1 | ############################################################################## 2 | # REDPITAYA-125-14 CONSTRAINTS FILE 3 | # 4 | # Simplified version of the offical .xdc file in: 5 | # https://github.com/RedPitaya/RedPitaya-FPGA/tree/master/sdc/red_pitaya.xdc 6 | ############################################################################## 7 | 8 | #### ADC 9 | ## ADC 0 data 10 | #set_property IOSTANDARD LVCMOS18 [get_ports {adc_data_1_i[*]}] 11 | #set_property IOB TRUE [get_ports {adc_data_1_i[*]}] 12 | 13 | #set_property PACKAGE_PIN Y17 [get_ports {adc_data_1_i[0]}] 14 | #set_property PACKAGE_PIN W16 [get_ports {adc_data_1_i[1]}] 15 | #set_property PACKAGE_PIN Y16 [get_ports {adc_data_1_i[2]}] 16 | #set_property PACKAGE_PIN W15 [get_ports {adc_data_1_i[3]}] 17 | #set_property PACKAGE_PIN W14 [get_ports {adc_data_1_i[4]}] 18 | #set_property PACKAGE_PIN Y14 [get_ports {adc_data_1_i[5]}] 19 | #set_property PACKAGE_PIN W13 [get_ports {adc_data_1_i[6]}] 20 | #set_property PACKAGE_PIN V12 [get_ports {adc_data_1_i[7]}] 21 | #set_property PACKAGE_PIN V13 [get_ports {adc_data_1_i[8]}] 22 | #set_property PACKAGE_PIN T14 [get_ports {adc_data_1_i[9]}] 23 | #set_property PACKAGE_PIN T15 [get_ports {adc_data_1_i[10]}] 24 | #set_property PACKAGE_PIN V15 [get_ports {adc_data_1_i[11]}] 25 | #set_property PACKAGE_PIN T16 [get_ports {adc_data_1_i[12]}] 26 | #set_property PACKAGE_PIN V16 [get_ports {adc_data_1_i[13]}] 27 | 28 | ## ADC 1 data 29 | #set_property IOSTANDARD LVCMOS18 [get_ports {adc_data_2_i[*]}] 30 | #set_property IOB TRUE [get_ports {adc_data_2_i[*]}] 31 | 32 | #set_property PACKAGE_PIN R18 [get_ports {adc_data_2_i[0]}] 33 | #set_property PACKAGE_PIN P16 [get_ports {adc_data_2_i[1]}] 34 | #set_property PACKAGE_PIN P18 [get_ports {adc_data_2_i[2]}] 35 | #set_property PACKAGE_PIN N17 [get_ports {adc_data_2_i[3]}] 36 | #set_property PACKAGE_PIN R19 [get_ports {adc_data_2_i[4]}] 37 | #set_property PACKAGE_PIN T20 [get_ports {adc_data_2_i[5]}] 38 | #set_property PACKAGE_PIN T19 [get_ports {adc_data_2_i[6]}] 39 | #set_property PACKAGE_PIN U20 [get_ports {adc_data_2_i[7]}] 40 | #set_property PACKAGE_PIN V20 [get_ports {adc_data_2_i[8]}] 41 | #set_property PACKAGE_PIN W20 [get_ports {adc_data_2_i[9]}] 42 | #set_property PACKAGE_PIN W19 [get_ports {adc_data_2_i[10]}] 43 | #set_property PACKAGE_PIN Y19 [get_ports {adc_data_2_i[11]}] 44 | #set_property PACKAGE_PIN W18 [get_ports {adc_data_2_i[12]}] 45 | #set_property PACKAGE_PIN Y18 [get_ports {adc_data_2_i[13]}] 46 | 47 | ## ADC clock 48 | #set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_*_i] 49 | #set_property PACKAGE_PIN U18 [get_ports adc_clk_p_i] 50 | #set_property PACKAGE_PIN U19 [get_ports adc_clk_n_i] 51 | 52 | ## ADC clock stabilizer 53 | #set_property IOSTANDARD LVCMOS18 [get_ports adc_cdcs_o] 54 | #set_property PACKAGE_PIN V18 [get_ports adc_cdcs_o] 55 | #set_property SLEW FAST [get_ports adc_cdcs_o] 56 | #set_property DRIVE 8 [get_ports adc_cdcs_o] 57 | 58 | 59 | #### DAC 60 | ## data 61 | #set_property IOSTANDARD LVCMOS33 [get_ports {dac_data_o[*]}] 62 | #set_property SLEW SLOW [get_ports {dac_data_o[*]}] 63 | #set_property DRIVE 4 [get_ports {dac_data_o[*]}] 64 | #set_property IOB TRUE [get_ports {dac_data_o[*]}] 65 | 66 | #set_property PACKAGE_PIN M19 [get_ports {dac_data_o[0]}] 67 | #set_property PACKAGE_PIN M20 [get_ports {dac_data_o[1]}] 68 | #set_property PACKAGE_PIN L19 [get_ports {dac_data_o[2]}] 69 | #set_property PACKAGE_PIN L20 [get_ports {dac_data_o[3]}] 70 | #set_property PACKAGE_PIN K19 [get_ports {dac_data_o[4]}] 71 | #set_property PACKAGE_PIN J19 [get_ports {dac_data_o[5]}] 72 | #set_property PACKAGE_PIN J20 [get_ports {dac_data_o[6]}] 73 | #set_property PACKAGE_PIN H20 [get_ports {dac_data_o[7]}] 74 | #set_property PACKAGE_PIN G19 [get_ports {dac_data_o[8]}] 75 | #set_property PACKAGE_PIN G20 [get_ports {dac_data_o[9]}] 76 | #set_property PACKAGE_PIN F19 [get_ports {dac_data_o[10]}] 77 | #set_property PACKAGE_PIN F20 [get_ports {dac_data_o[11]}] 78 | #set_property PACKAGE_PIN D20 [get_ports {dac_data_o[12]}] 79 | #set_property PACKAGE_PIN D19 [get_ports {dac_data_o[13]}] 80 | 81 | ## control 82 | #set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o] 83 | #set_property SLEW FAST [get_ports dac_*_o] 84 | #set_property DRIVE 8 [get_ports dac_*_o] 85 | #set_property IOB TRUE [get_ports dac_*_o] 86 | 87 | #set_property PACKAGE_PIN M17 [get_ports dac_wrt_o] 88 | #set_property PACKAGE_PIN N16 [get_ports dac_sel_o] 89 | #set_property PACKAGE_PIN M18 [get_ports dac_clk_o] 90 | #set_property PACKAGE_PIN N15 [get_ports dac_rst_o] 91 | 92 | 93 | #### PWM DAC 94 | #set_property IOSTANDARD LVCMOS18 [get_ports {dac_pwm_o[*]}] 95 | #set_property SLEW FAST [get_ports {dac_pwm_o[*]}] 96 | #set_property DRIVE 12 [get_ports {dac_pwm_o[*]}] 97 | #set_property IOB TRUE [get_ports {dac_pwm_o[*]}] 98 | 99 | #set_property PACKAGE_PIN T10 [get_ports {dac_pwm_o[0]}] 100 | #set_property PACKAGE_PIN T11 [get_ports {dac_pwm_o[1]}] 101 | #set_property PACKAGE_PIN P15 [get_ports {dac_pwm_o[2]}] 102 | #set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}] 103 | 104 | 105 | #### XADC 106 | #set_property IOSTANDARD LVCMOS33 [get_ports {vinp_i[*]}] 107 | #set_property IOSTANDARD LVCMOS33 [get_ports {vinn_i[*]}] 108 | ##AD0 109 | #set_property PACKAGE_PIN C20 [get_ports {vinp_i[1]}] 110 | #set_property PACKAGE_PIN B20 [get_ports {vinn_i[1]}] 111 | ##AD1 112 | #set_property PACKAGE_PIN E17 [get_ports {vinp_i[2]}] 113 | #set_property PACKAGE_PIN D18 [get_ports {vinn_i[2]}] 114 | ##AD8 115 | #set_property PACKAGE_PIN B19 [get_ports {vinp_i[0]}] 116 | #set_property PACKAGE_PIN A20 [get_ports {vinn_i[0]}] 117 | ##AD9 118 | #set_property PACKAGE_PIN E18 [get_ports {vinp_i[3]}] 119 | #set_property PACKAGE_PIN E19 [get_ports {vinn_i[3]}] 120 | ##V_0 121 | #set_property PACKAGE_PIN K9 [get_ports {vinp_i[4]}] 122 | #set_property PACKAGE_PIN L10 [get_ports {vinn_i[4]}] 123 | 124 | 125 | #### Expansion connector 126 | #set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_io[*]}] 127 | #set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_io[*]}] 128 | #set_property SLEW FAST [get_ports {exp_p_io[*]}] 129 | #set_property SLEW FAST [get_ports {exp_n_io[*]}] 130 | #set_property DRIVE 8 [get_ports {exp_p_io[*]}] 131 | #set_property DRIVE 8 [get_ports {exp_n_io[*]}] 132 | 133 | #set_property PACKAGE_PIN G17 [get_ports {exp_p_io[0]}] 134 | #set_property PACKAGE_PIN G18 [get_ports {exp_n_io[0]}] 135 | #set_property PACKAGE_PIN H16 [get_ports {exp_p_io[1]}] 136 | #set_property PACKAGE_PIN H17 [get_ports {exp_n_io[1]}] 137 | #set_property PACKAGE_PIN J18 [get_ports {exp_p_io[2]}] 138 | #set_property PACKAGE_PIN H18 [get_ports {exp_n_io[2]}] 139 | #set_property PACKAGE_PIN K17 [get_ports {exp_p_io[3]}] 140 | #set_property PACKAGE_PIN K18 [get_ports {exp_n_io[3]}] 141 | #set_property PACKAGE_PIN L14 [get_ports {exp_p_io[4]}] 142 | #set_property PACKAGE_PIN L15 [get_ports {exp_n_io[4]}] 143 | #set_property PACKAGE_PIN L16 [get_ports {exp_p_io[5]}] 144 | #set_property PACKAGE_PIN L17 [get_ports {exp_n_io[5]}] 145 | #set_property PACKAGE_PIN K16 [get_ports {exp_p_io[6]}] 146 | #set_property PACKAGE_PIN J16 [get_ports {exp_n_io[6]}] 147 | #set_property PACKAGE_PIN M14 [get_ports {exp_p_io[7]}] 148 | #set_property PACKAGE_PIN M15 [get_ports {exp_n_io[7]}] 149 | 150 | ##set_property PULLDOWN TRUE [get_ports {exp_p_io[0]}] 151 | ##set_property PULLDOWN TRUE [get_ports {exp_n_io[0]}] 152 | ##set_property PULLUP TRUE [get_ports {exp_p_io[7]}] 153 | ##set_property PULLUP TRUE [get_ports {exp_n_io[7]}] 154 | 155 | #set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}] 156 | #set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}] 157 | #set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}] 158 | #set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}] 159 | #set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}] 160 | #set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}] 161 | #set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}] 162 | #set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}] 163 | 164 | 165 | #### LED 166 | #set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}] 167 | #set_property SLEW SLOW [get_ports {led_o[*]}] 168 | #set_property DRIVE 4 [get_ports {led_o[*]}] 169 | 170 | #set_property PACKAGE_PIN F16 [get_ports {led_o[0]}] 171 | #set_property PACKAGE_PIN F17 [get_ports {led_o[1]}] 172 | #set_property PACKAGE_PIN G15 [get_ports {led_o[2]}] 173 | #set_property PACKAGE_PIN H15 [get_ports {led_o[3]}] 174 | #set_property PACKAGE_PIN K14 [get_ports {led_o[4]}] 175 | #set_property PACKAGE_PIN G14 [get_ports {led_o[5]}] 176 | #set_property PACKAGE_PIN J15 [get_ports {led_o[6]}] 177 | #set_property PACKAGE_PIN J14 [get_ports {led_o[7]}] 178 | 179 | 180 | #### Clock constraints 181 | #create_clock -period 8.000 -name adc_clk_p_i [get_ports adc_clk_p_i] 182 | #set_input_delay -clock adc_clk_p_i 3.400 [get_ports adc_data_*_i[*]] 183 | -------------------------------------------------------------------------------- /sim/sim_counter.tcl: -------------------------------------------------------------------------------- 1 | #Restart simulation 2 | restart 3 | 4 | #Define clock (100 MHz) 5 | add_force /counter/clk -radix hex {1 0ns} {0 5000ps} -repeat_every 10000ps 6 | 7 | #Reset core 8 | add_force /counter/resetn -radix hex 0 9 | add_force /counter/incr_i -radix hex 0 10 | 11 | #Run 50ns 12 | run 50ns 13 | 14 | #Set counter increment = 2 15 | add_force /counter/incr_i -radix hex 2 16 | 17 | #Enable core 18 | add_force /counter/resetn -radix hex 1 19 | 20 | #Run 50ns 21 | run 50ns 22 | 23 | #Set counter increment = 4 24 | add_force /counter/incr_i -radix hex 4 25 | 26 | #Run 50ns 27 | run 50ns -------------------------------------------------------------------------------- /sim/tb_counter.v: -------------------------------------------------------------------------------- 1 | module tb_counter (); 2 | 3 | reg clk; 4 | reg resetn; 5 | reg [31 : 0] incr_i; 6 | wire [31 : 0] counter_o; 7 | 8 | // connecting testbench to counter.v instance 9 | counter counter_instance( 10 | .clk(clk), 11 | .resetn(resetn), 12 | .incr_i(incr_i), 13 | .counter_o(counter_o) 14 | ); 15 | 16 | //clk (100MHz) 17 | always begin 18 | clk = 1; 19 | #5; 20 | clk = 0; 21 | #5; 22 | end 23 | 24 | //main simulation 25 | initial begin 26 | //reset core 27 | resetn <= 0; 28 | incr_i <= 0; 29 | 30 | //run 50ns 31 | #50; 32 | 33 | //set counter increment = 2 34 | incr_i <= 2; 35 | 36 | //enable core 37 | resetn <= 1; 38 | 39 | //run 50ns 40 | #50; 41 | 42 | //set counter increment = 4 43 | incr_i <= 4; 44 | 45 | //run 50ns 46 | #50; 47 | 48 | //finish 49 | $stop; 50 | end 51 | endmodule -------------------------------------------------------------------------------- /sim/tb_counter.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | use IEEE.NUMERIC_STD.ALL; 4 | 5 | 6 | entity tb_counter is 7 | end tb_counter; 8 | 9 | architecture tb of tb_counter is 10 | signal clk, resetn : std_logic; 11 | signal incr_i : std_logic_vector (31 downto 0); 12 | signal counter_o : std_logic_vector (31 downto 0); 13 | begin 14 | -- connecting testbench to counter.v instance 15 | counter_instance : entity work.counter port map (clk => clk, resetn => resetn, incr_i => incr_i, counter_o => counter_o); 16 | 17 | -- clock (100MHz) 18 | process 19 | begin 20 | clk <= '0'; 21 | wait for 5ns; 22 | clk <= '1'; 23 | wait for 5ns; 24 | end process; 25 | 26 | -- main simulation 27 | process 28 | begin 29 | -- reset 30 | resetn <= '0'; 31 | incr_i <= (others => '0'); 32 | 33 | -- run 50ns 34 | wait for 50ns; 35 | 36 | -- Set counter increment = 2 37 | incr_i <= std_logic_vector(to_unsigned(2, incr_i'length)); 38 | 39 | -- enable core 40 | resetn <= '1'; 41 | 42 | -- run 50ns 43 | wait for 50ns; 44 | 45 | -- Set counter increment = 4 46 | incr_i <= std_logic_vector(to_unsigned(4, incr_i'length)); 47 | 48 | -- run 50ns 49 | wait for 50ns; 50 | 51 | --finish 52 | wait; 53 | end process; 54 | end tb ; 55 | -------------------------------------------------------------------------------- /sys/README.md: -------------------------------------------------------------------------------- 1 | # Remote Development System (AWS EC-2 instance & FPGA) 2 | ### EC-2 Instance Specifications 3 | * AMI: Ubuntu 22.04 Server LTS 4 | * Type: c5.2xlarge 5 | * Memory: 100GB SSD 6 | * Use elastic IP to get static public IP address 7 | * Networking inbound/outbound rules: 8 | * Enable all TCP 9 | * Enable all UDP 10 | 11 | ### Configure EC 2 instance 12 | * Enter EC-2 instance 13 | ``` 14 | ssh -i ubuntu@ 15 | ``` 16 | * Clone this repository: 17 | ``` 18 | mkdir Documents 19 | cd Documents 20 | git clone https://github.com/dspsandbox/FPGA-Notes-for-Scientists 21 | ``` 22 | * Execute scripts: 23 | ``` 24 | cd FPGA-Notes-for-Scientists/sys 25 | source config_xrdp.sh 26 | source config_display.sh 27 | source config_wg.sh 28 | source config_xilinx_0.sh 29 | source config_xilinx_1.sh 30 | ``` 31 | 32 | ### Configure FPGA 33 | * Connect to the FPGA via terminal or SSH 34 | * Install Wireguard: 35 | ``` 36 | sudo apt update -y 37 | sudo apt install -y wireguard 38 | ``` 39 | 40 | * Open Wireguard wg0 configuration file: 41 | ``` 42 | sudo vi /etc/wireguard/wg0.conf 43 | ``` 44 | * Copy into it the content of [resources/wg/client/wg0.conf](resources/wg/client/wg0.conf). Change Enpoint IP (X.X.X.X) with the \ of EC-2 instance. 45 | 46 | * Enable and restart Wireguard service: 47 | ``` 48 | sudo systemctl enable wg-quick@wg0.service 49 | sudo systemctl restart wg-quick@wg0.service 50 | ``` 51 | -------------------------------------------------------------------------------- /sys/config_display.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | gsettings set org.gnome.desktop.background picture-uri '' 3 | gsettings set org.gnome.desktop.background picture-uri-dark '' 4 | gsettings reset org.gnome.desktop.background color-shading-type 5 | gsettings set org.gnome.desktop.background primary-color '#bd4e55' 6 | -------------------------------------------------------------------------------- /sys/config_wg.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | sudo apt update -y 3 | sudo apt install -y wireguard 4 | sudo cp resources/wg/server/wg0.conf /etc/wireguard/wg0.conf 5 | sudo chown -R root:root /etc/wireguard/ 6 | sudo chmod -R og-rwx /etc/wireguard/ 7 | sudo systemctl enable wg-quick@wg0.service 8 | sudo systemctl restart wg-quick@wg0.service -------------------------------------------------------------------------------- /sys/config_xilinx_0.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | XILINX_DOWNLOAD_DIR=/tmp/xilinx_download 4 | XILINX_INSTALLATION_DIR=~/Xilinx 5 | 6 | # #Prerequisites (see https://support.xilinx.com/s/article/63794?language=en_US) and gcc compiler for simulation 7 | sudo apt install -y libtinfo5 libncurses5 gcc 8 | 9 | #Vivado installation (assuming standalone installer installer.tar.gz located at $XILINX_DOWNLOAD_DIR) 10 | cd $XILINX_DOWNLOAD_DIR 11 | tar -xf installer.tar.gz 12 | sudo rm installer.tar.gz 13 | cd Vivado_* 14 | ./xsetup --agree 3rdPartyEULA,XilinxEULA --batch Install --edition "Vivado ML Standard" --product "Vivado" --location $XILINX_INSTALLATION_DIR 15 | 16 | #Remove tmp folder 17 | cd /. 18 | sudo rm -r $XILINX_DOWNLOAD_DIR -------------------------------------------------------------------------------- /sys/config_xilinx_1.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | XILINX_INSTALLATION_DIR=~/Xilinx 4 | 5 | #Remove XIC 6 | rm -r $XILINX_INSTALLATION_DIR/xic 7 | 8 | #Remove desktop icons 9 | rm ~/Desktop/*.desktop 10 | 11 | #Replace path for LD_LIBRARY_PATH in upload_overlay.tcl (resolve OpenSSL error) 12 | sed -i '/^exec/ {s#^#set ::env(LD_LIBRARY_PATH) "/usr/bin/openssl"\n#}' ../tcl/upload_overlay.tcl 13 | 14 | #Copy board files 15 | cp -r ../board_files $XILINX_INSTALLATION_DIR/Vivado/*/data/boards -------------------------------------------------------------------------------- /sys/config_xrdp.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | LNX_USER=ubuntu 3 | LNX_PWD=top_secret 4 | 5 | #XRDP Server 6 | sudo apt update -y 7 | sudo apt install -y ubuntu-desktop 8 | sudo dpkg --configure -a 9 | source resources/xrdp/xrdp-installer-* 10 | 11 | #Firefox 12 | sudo apt install firefox 13 | 14 | #Update password 15 | echo "$LNX_USER:$LNX_PWD" | sudo chpasswd 16 | 17 | -------------------------------------------------------------------------------- /sys/resources/boot/boot.py: -------------------------------------------------------------------------------- 1 | import re 2 | import os 3 | 4 | server_ip = "X.X.X.X" #CHANGE TO SERVER IP 5 | 6 | wg_config_path = "/etc/wireguard/wg0.conf" 7 | 8 | with open(wg_config_path, "r") as f: 9 | wg_config = f.read() 10 | 11 | pattern = r"Endpoint = ([0-9a-zA-Z.]+):51820\s*#CHANGE TO SERVER IP" 12 | replacement = f"Endpoint = {server_ip}:51820 #CHANGE TO SERVER IP" 13 | wg_config = re.sub(pattern, replacement, wg_config) 14 | 15 | with open(wg_config_path, "w") as f: 16 | f.write(wg_config) 17 | 18 | os.system(f"sudo systemctl restart wg-quick@wg0") 19 | -------------------------------------------------------------------------------- /sys/resources/wg/client/wg0.conf: -------------------------------------------------------------------------------- 1 | [Interface] 2 | Address = 10.0.0.2/24 3 | PrivateKey = UKx/QCmXndUDn1ozxOjDpnyWjHrWNIooSEBZFRvz2Hs= 4 | ListenPort = 21841 5 | 6 | [Peer] 7 | PublicKey = li9ZrctznJLgaHPPDE1LZUzBb5NBYSJeho90phxhAGY= 8 | Endpoint = X.X.X.X:51820 #CHANGE TO SERVER IP 9 | AllowedIPs = 10.0.0.1/24 10 | PersistentKeepalive = 25 11 | -------------------------------------------------------------------------------- /sys/resources/wg/server/wg0.conf: -------------------------------------------------------------------------------- 1 | [Interface] 2 | Address = 10.0.0.1/24 3 | PrivateKey = YMD13QOreLWr1xa8Z6S/dOgtZzKuXBHA06p94gksX3w= 4 | ListenPort = 51820 5 | 6 | [Peer] 7 | PublicKey = 35yU86hMjm0lIch9dyPxVHbDVxmOB4iNxZo3mlw5rVU= 8 | AllowedIPs = 10.0.0.2/32 9 | -------------------------------------------------------------------------------- /tcl/upload_overlay.tcl: -------------------------------------------------------------------------------- 1 | ############################# 2 | # PARAMETERS 3 | ############################# 4 | set ip 10.0.0.2 5 | set user xilinx 6 | ############################# 7 | cd [get_property DIRECTORY [current_project]] 8 | set projName [get_property NAME [current_project]] 9 | set topDesignName [string map {"_wrapper" ""} [get_property top [current_fileset]]] 10 | set overlay_dir overlay/$projName 11 | file delete -force $overlay_dir 12 | file mkdir $overlay_dir 13 | puts $overlay_dir 14 | file copy -force [glob $projName.runs/impl_1/*.bit] $overlay_dir/$projName.bit 15 | file copy -force [glob $projName.*/sources_1/bd/$topDesignName/hw_handoff/*.hwh] $overlay_dir/$projName.hwh 16 | write_bd_tcl -force $overlay_dir/$projName.tcl 17 | exec scp -r $overlay_dir $user@$ip:/home/xilinx/pynq/overlays 18 | puts "\nOverlay \"$projName\" successfully uploaded to: \n$user@$ip:/home/xilinx/pynq/overlays/$projName" 19 | -------------------------------------------------------------------------------- /tcl/write_project.tcl: -------------------------------------------------------------------------------- 1 | #Get paths 2 | set project_name [current_project] 3 | set project_path [file normalize [get_property directory $project_name]/..] 4 | set output_path "${project_path}/project.tcl" 5 | 6 | # Remove top module checkpoints 7 | set top_name [get_property top [current_fileset]] 8 | set filter_expr "NAME =~ \"*${top_name}.dcp\"" 9 | set dcp_files [get_files -filter $filter_expr] 10 | foreach dcp_file $dcp_files { 11 | remove_files $dcp_file 12 | } 13 | 14 | 15 | #Write project 16 | write_project_tcl -force $output_path 17 | 18 | #Convert absolute to relative paths 19 | set fp [open $output_path r] 20 | set file_data [read $fp] 21 | close $fp 22 | 23 | #For windows 24 | # set abs_path_list [regex -inline -all "C:/\[^\n\"\]*" $file_data] 25 | 26 | #For linux 27 | set abs_path_list [regex -inline -all "/home/\[^\n\"\]*" $file_data] 28 | 29 | foreach abs_path $abs_path_list { 30 | puts $abs_path 31 | set rel_path [exec python -c "import os; os.chdir('${project_path}'); print(os.path.relpath('${abs_path}'))"] 32 | regsub -all "\\\\" $rel_path "/" rel_path 33 | regsub -all $abs_path $file_data $rel_path file_data 34 | } 35 | 36 | #Append number to project directory name if default project directory already exists 37 | regsub -all "create_project \\$\{_xil_proj_name_\} \./\\$\{_xil_proj_name_\}" $file_data "create_project \${_xil_proj_name_} ./\${_xil_proj_dir_name_}" file_data 38 | set file_data "set _xil_proj_dir_name_ ${project_name} \nset i 0 \nwhile {\[file exist \${_xil_proj_dir_name_}\]} {\n set _xil_proj_dir_name_ ${project_name}_\${i}\n set i \[expr {\${i} + 1}\]\n}\n${file_data}" 39 | 40 | set fp [open $output_path w] 41 | puts $fp $file_data 42 | close $fp 43 | 44 | puts "\nWrite project completed. Output path: ${output_path}" --------------------------------------------------------------------------------