├── .gitignore ├── BoardInit_AXI ├── bd │ └── bd.tcl ├── component.xml ├── drivers │ └── BoardInit_AXI_v1_0 │ │ ├── data │ │ ├── BoardInit_AXI.mdd │ │ └── BoardInit_AXI.tcl │ │ └── src │ │ ├── BoardInit_AXI.c │ │ ├── BoardInit_AXI.h │ │ ├── BoardInit_AXI_selftest.c │ │ └── Makefile ├── example_designs │ ├── bfm_design │ │ ├── BoardInit_AXI_v1_0_tb.v │ │ └── design.tcl │ └── debug_hw_design │ │ ├── BoardInit_AXI_v1_0_hw_test.tcl │ │ └── design.tcl ├── hdl │ ├── BoardInit_AXI_v1_0.v │ └── BoardInit_AXI_v1_0_S00_AXI.v └── xgui │ └── BoardInit_AXI_v1_0.tcl ├── Connector ├── ColorBin2Channels │ ├── component.xml │ ├── srcs │ │ └── ColorBin2Channels.v │ └── xgui │ │ └── ColorBin2Channels_v1_0.tcl ├── ColorGray2Channels │ ├── component.xml │ ├── srcs │ │ └── ColorGray2Channels.v │ └── xgui │ │ └── ColorGray2Channels_v1_0.tcl ├── ColorRGB16toRGB24 │ ├── component.xml │ ├── srcs │ │ └── ColorRGB16toRGB24.v │ └── xgui │ │ └── ColorRGB16toRGB24_v1_0.tcl ├── ColorRGB24toVGA │ ├── component.xml │ ├── srcs │ │ └── ColorRGB24toVGA.v │ └── xgui │ │ └── ColorRGB24toVGA_v1_0.tcl ├── DataCombin2 │ ├── component.xml │ ├── srcs │ │ └── DataCombin2.v │ └── xgui │ │ └── DataCombin2_v1_0.tcl ├── DataCombin3 │ ├── component.xml │ ├── srcs │ │ └── DataCombin3.v │ └── xgui │ │ └── DataCombin3_v1_0.tcl ├── DataDelay │ ├── component.xml │ ├── srcs │ │ └── DataDelay.v │ └── xgui │ │ └── DataDelay_v1_0.tcl ├── DataSplit4 │ ├── component.xml │ ├── srcs │ │ └── DataSplit4.v │ └── xgui │ │ └── DataSplit4_v1_0.tcl ├── DataWidthConvert │ ├── component.xml │ ├── srcs │ │ └── DataWidthConvert.v │ └── xgui │ │ ├── DataWidthConvert_v1_0.tcl │ │ └── DataWidthConvert_v1_0.tcl~ ├── Mux2 │ ├── component.xml │ ├── srcs │ │ └── Mux2.v │ └── xgui │ │ └── Mux2_v1_0.tcl ├── Mux4 │ ├── component.xml │ ├── srcs │ │ └── Mux4.v │ └── xgui │ │ └── Mux4_v1_0.tcl ├── Mux8 │ ├── component.xml │ ├── srcs │ │ └── Mux8.v │ └── xgui │ │ └── Mux8_v1_0.tcl └── Or8 │ ├── component.xml │ ├── srcs │ └── Or8.v │ └── xgui │ └── Or8_v1_0.tcl ├── Generator ├── CountGenerator │ ├── CountGenerator.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── CountGenerator.v │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ └── CountGenerator_v1_0.gtcl │ │ │ └── xgui │ │ │ └── CountGenerator_v1_0.tcl │ └── CountGenerator.xpr ├── FrameController │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── FrameController.cr.mti │ │ ├── FrameController.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── FrameController.srcs │ │ │ ├── component.xml │ │ │ ├── component.xml~ │ │ │ ├── gui │ │ │ │ └── FrameController_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ ├── import │ │ │ │ │ └── BRam8x512x512_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── FrameController_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── FrameController.v │ │ │ └── xgui │ │ │ │ └── FrameController_v1_0.tcl │ │ └── FrameController.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ └── SimResCheck │ │ ├── compare.py │ │ └── convert.py ├── FrameController2 │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── FrameController2.cr.mti │ │ ├── FrameController2.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── FrameController2.srcs │ │ │ ├── component.xml │ │ │ ├── component.xml~ │ │ │ ├── gui │ │ │ │ └── FrameController2_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ ├── import │ │ │ │ │ └── BRam8x512x512_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── FrameController2_TB.sv │ │ │ ├── sources_1 │ │ │ │ ├── ip │ │ │ │ │ └── Multiplier12x12FR2 │ │ │ │ │ │ ├── Multiplier12x12FR2.xci │ │ │ │ │ │ └── Multiplier12x12FR2_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── FrameController2.v │ │ │ └── xgui │ │ │ │ ├── FrameController2_v1_0.tcl │ │ │ │ └── FrameController2_v1_0.tcl~ │ │ └── FrameController2.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ └── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py ├── RowsGenerator │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── RowsGenerator.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── RowsGenerator.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── RowsGenerator_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── RowsGenerator_TB.sv │ │ │ ├── sources_1 │ │ │ │ ├── ip │ │ │ │ │ ├── Fifo12xWidthRows │ │ │ │ │ │ └── Fifo12xWidthRows.xci │ │ │ │ │ ├── Fifo1xWidthRows │ │ │ │ │ │ └── Fifo1xWidthRows.xci │ │ │ │ │ ├── Fifo4xWidthRows │ │ │ │ │ │ └── Fifo4xWidthRows.xci │ │ │ │ │ └── Fifo8xWidthRows │ │ │ │ │ │ ├── Fifo8xWidthRows.xci │ │ │ │ │ │ └── Fifo8xWidthRows_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── RowsGenerator.v │ │ │ └── xgui │ │ │ │ └── RowsGenerator_v1_0.tcl │ │ └── RowsGenerator.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ └── convert.py │ └── SoftwareSim │ │ ├── RowsGenerator.py │ │ └── sim.py └── WindowGenerator │ ├── .gitignore │ ├── FunSimForHDL │ ├── Run.do │ ├── RunOver.do │ ├── WindowGenerator.cr.mti │ └── WindowGenerator.mpf │ ├── HDL │ ├── WindowGenerator.srcs │ │ ├── component.xml │ │ ├── gui │ │ │ └── WindowGenerator_v1_0.gtcl │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── WindowGenerator_TB.sv │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── WindowGenerator.v │ │ └── xgui │ │ │ └── WindowGenerator_v1_0.tcl │ └── WindowGenerator.xpr │ ├── HDLSimDataGen │ ├── RowsGenerator.py │ └── create.py │ ├── ImageForTest │ └── conf.json │ ├── README.md │ ├── SimResCheck │ ├── compare.py │ └── convert.py │ └── SoftwareSim │ ├── RowsGenerator.py │ ├── WindowGenerator.py │ └── sim.py ├── Geometry ├── Crop │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── Crop.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── Crop.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── Crop_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── Crop_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── Crop.v │ │ │ └── xgui │ │ │ │ └── Crop_v1_0.tcl │ │ └── Crop.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── Mirror │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── Mirror.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── Mirror.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── Mirror_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── Mirror_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── Mirror.v │ │ │ └── xgui │ │ │ │ └── Mirror_v1_0.tcl │ │ └── Mirror.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── Pan │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── Pan.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── Pan.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── Pan_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ ├── import │ │ │ │ │ └── True2Comp.v │ │ │ │ └── new │ │ │ │ │ └── Pan_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── Pan.v │ │ │ └── xgui │ │ │ │ └── Pan_v1_0.tcl │ │ └── Pan.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── Rotate │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── Rotate.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── Rotate.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── Rotate_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ ├── import │ │ │ │ │ ├── BRam8x512x512_funcsim.v │ │ │ │ │ ├── FrameController.v │ │ │ │ │ ├── FrameController2.v │ │ │ │ │ └── Multiplier12x12FR2_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── Rotate_TB.sv │ │ │ ├── sources_1 │ │ │ │ ├── ip │ │ │ │ │ └── Multiplier13Sx20SRTT │ │ │ │ │ │ ├── Multiplier13Sx20SRTT.xci │ │ │ │ │ │ └── Multiplier13Sx20SRTT_funcsim.v │ │ │ │ └── new │ │ │ │ │ ├── CosLUT.dat │ │ │ │ │ ├── CosLUT.v │ │ │ │ │ ├── FixedRoundSigned.v │ │ │ │ │ ├── FixedRoundSigned2.v │ │ │ │ │ ├── Rotate.v │ │ │ │ │ ├── SinLUT.dat │ │ │ │ │ ├── SinLUT.v │ │ │ │ │ └── sin_cos_gen.py │ │ │ └── xgui │ │ │ │ └── Rotate_v1_0.tcl │ │ └── Rotate.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── Scale │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── Run.do │ │ ├── RunOver.do │ │ └── Scale.mpf │ ├── HDL │ │ ├── Scale.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── Scale_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ ├── import │ │ │ │ │ ├── BRam8x512x512_funcsim.v │ │ │ │ │ ├── FrameController.v │ │ │ │ │ ├── FrameController2.v │ │ │ │ │ └── Multiplier12x12FR2_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── Scale_TB.sv │ │ │ ├── sources_1 │ │ │ │ ├── ip │ │ │ │ │ └── Multiplier12x24SCL │ │ │ │ │ │ ├── Multiplier12x24SCL.xci │ │ │ │ │ │ └── Multiplier12x24SCL_funcsim.v │ │ │ │ └── new │ │ │ │ │ ├── FixedRoundUnsigned.v │ │ │ │ │ └── Scale.v │ │ │ └── xgui │ │ │ │ └── Scale_v1_0.tcl │ │ └── Scale.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py └── Shear │ ├── .gitignore │ ├── FunSimForHDL │ ├── Run.do │ ├── RunOver.do │ └── Shear.mpf │ ├── HDL │ ├── Shear.srcs │ │ ├── component.xml │ │ ├── gui │ │ │ └── Shear_v1_0.gtcl │ │ ├── sim_1 │ │ │ ├── import │ │ │ │ ├── BRam8x512x512_funcsim.v │ │ │ │ ├── FrameController.v │ │ │ │ ├── FrameController2.v │ │ │ │ ├── Multiplier12x12FR2_funcsim.v │ │ │ │ └── True2Comp.v │ │ │ └── new │ │ │ │ └── Shear_TB.sv │ │ ├── sources_1 │ │ │ ├── ip │ │ │ │ └── Multiplier12x25SSHR │ │ │ │ │ ├── Multiplier12x25SSHR.xci │ │ │ │ │ └── Multiplier12x25SSHR_funcsim.v │ │ │ └── new │ │ │ │ ├── FixedRoundSigned.v │ │ │ │ ├── FixedRoundSigned1.v │ │ │ │ └── Shear.v │ │ └── xgui │ │ │ └── Shear_v1_0.tcl │ └── Shear.xpr │ ├── HDLSimDataGen │ └── create.py │ ├── ImageForTest │ └── conf.json │ ├── README.md │ ├── SimResCheck │ ├── compare.py │ ├── compare_report.txt │ ├── compare_report_table.txt │ └── convert.py │ └── SoftwareSim │ └── sim.py ├── InOut ├── Bram8x320x240 │ ├── component.xml │ ├── src │ │ ├── BlcokRam8x320x240 │ │ │ └── BlcokRam8x320x240.xci │ │ └── Bram8x320x240.v │ └── xgui │ │ └── Bram8x320x240_v1_0.tcl ├── Cam │ ├── component.xml │ ├── src │ │ └── camCap.v │ └── xgui │ │ └── camCap_v1_0.tcl ├── IIC_Ctrl │ ├── component.xml │ ├── src │ │ ├── I2C_Controller.v │ │ ├── I2C_OV7670_RGB565_Config.v │ │ └── IICctrl.v │ └── xgui │ │ └── IICctrl_v1_0.tcl └── VGA640x480 │ ├── component.xml │ ├── srcs │ └── VGA640x480.v │ └── xgui │ ├── VGA640x480_v1_0.tcl │ └── VGA640x480_v1_0.tcl~ ├── LICENSE ├── LocalFilter ├── ErosionDilationBin │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── ErosionDilationBin.cr.mti │ │ ├── ErosionDilationBin.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── ErosionDilationBin.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── ErosionDilationBin_v1_1.gtcl │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── ErosionDilationBin_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── ErosionDilationBin.v │ │ │ └── xgui │ │ │ │ └── ErosionDilationBin_v1_0.tcl │ │ └── ErosionDilationBin.xpr │ ├── HDLSimDataGen │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── sim.py ├── MatchTemplateBin │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── MatchTemplateBin.cr.mti │ │ ├── MatchTemplateBin.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── MatchTemplateBin.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── MatchTemplateBin_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── MatchTemplateBin.v │ │ │ └── xgui │ │ │ │ └── MatchTemplateBin_v1_0.tcl │ │ └── MatchTemplateBin.xpr │ ├── HDLSimDataGen │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── sim.py ├── MeanFilter │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── MeanFilter.cr.mti │ │ ├── MeanFilter.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── MeanFilter.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── MeanFilter_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── MeanFilter_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── MeanFilter.v │ │ │ └── xgui │ │ │ │ └── MeanFilter_v1_0.tcl │ │ └── MeanFilter.xpr │ ├── HDLSimDataGen │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── sim.py ├── RankFilter │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── RankFifter.cr.mti │ │ ├── RankFifter.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── RankFilter.srcs │ │ │ ├── component.xml │ │ │ ├── gui │ │ │ │ └── RankFifter_v1_0.gtcl │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── RankFilter_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ ├── Encoder.v │ │ │ │ │ ├── RankFilter.v │ │ │ │ │ └── generate.py │ │ │ └── xgui │ │ │ │ └── RankFifter_v1_0.tcl │ │ └── RankFilter.xpr │ ├── HDLSimDataGen │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ ├── compare_report.txt │ │ ├── compare_report_table.txt │ │ └── convert.py │ └── SoftwareSim │ │ ├── RowsGenerator.py │ │ ├── WindowGenerator.py │ │ └── sim.py └── ThresholdLocal │ ├── .gitignore │ ├── FunSimForHDL │ ├── Run.do │ ├── RunOver.do │ ├── ThresholdLocal.cr.mti │ └── ThresholdLocal.mpf │ ├── HDL │ ├── ThresholdLocal.srcs │ │ ├── component.xml │ │ ├── gui │ │ │ └── ThresholdLocal_v1_0.gtcl │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── ThresholdLocal_TB.sv │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── ThresholdLocal.v │ │ └── xgui │ │ │ └── ThresholdLocal_v1_0.tcl │ └── ThresholdLocal.xpr │ ├── HDLSimDataGen │ ├── MeanFilter.py │ ├── RankFilter.py │ ├── RowsGenerator.py │ ├── WindowGenerator.py │ └── create.py │ ├── ImageForTest │ └── conf.json │ ├── README.md │ ├── SimResCheck │ ├── compare.py │ ├── compare_report.txt │ ├── compare_report_table.txt │ └── convert.py │ └── SoftwareSim │ ├── MeanFilter.py │ ├── RankFilter.py │ ├── RowsGenerator.py │ ├── WindowGenerator.py │ └── sim.py ├── Point ├── ColorReversal │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── ColorReversa.cr.mti │ │ ├── ColorReversa.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── ColorReversal.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── ColorReversal_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── ColorReversal.v │ │ │ └── xgui │ │ │ │ └── ColorReversal_v1_0.tcl │ │ └── ColorReversal.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── ContrastTransform │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── ContrastTransform.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── ContrastTransform.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── ContrastTransform_TB.sv │ │ │ ├── sources_1 │ │ │ │ ├── ip │ │ │ │ │ └── Multiplier12x24CT │ │ │ │ │ │ ├── Multiplier12x24CT.xci │ │ │ │ │ │ └── Multiplier12x24CT_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── ContrastTransform.v │ │ │ └── xgui │ │ │ │ └── ContrastTransform_v1_0.tcl │ │ └── ContrastTransform.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── Graying │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── Graying.cr.mti │ │ ├── Graying.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── Graying.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ │ └── new │ │ │ │ │ └── Graying_TB.sv │ │ │ ├── sources_1 │ │ │ │ ├── ip │ │ │ │ │ ├── MultiplierBluex0d114 │ │ │ │ │ │ ├── MultiplierBluex0d114.xci │ │ │ │ │ │ └── MultiplierBluex0d114_funcsim.v │ │ │ │ │ ├── MultiplierGreenx0d587 │ │ │ │ │ │ ├── MultiplierGreenx0d587.xci │ │ │ │ │ │ └── MultiplierGreenx0d587_funcsim.v │ │ │ │ │ └── MultiplierRedx0d299 │ │ │ │ │ │ ├── MultiplierRedx0d299.xci │ │ │ │ │ │ └── MultiplierRedx0d299_funcsim.v │ │ │ │ └── new │ │ │ │ │ └── Graying.v │ │ │ └── xgui │ │ │ │ └── Graying_v1_0.tcl │ │ └── Graying.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py ├── LightnessTransform │ ├── .gitignore │ ├── FunSimForHDL │ │ ├── LightnessTransform.cr.mti │ │ ├── LightnessTransform.mpf │ │ ├── Run.do │ │ └── RunOver.do │ ├── HDL │ │ ├── LightnessTransform.srcs │ │ │ ├── component.xml │ │ │ ├── sim_1 │ │ │ │ ├── import │ │ │ │ │ └── True2Comp.v │ │ │ │ └── new │ │ │ │ │ └── LightnessTransform_TB.sv │ │ │ ├── sources_1 │ │ │ │ └── new │ │ │ │ │ └── LightnessTransform.v │ │ │ └── xgui │ │ │ │ └── LightnessTransform_v1_0.tcl │ │ └── LightnessTransform.xpr │ ├── HDLSimDataGen │ │ └── create.py │ ├── ImageForTest │ │ └── conf.json │ ├── README.md │ ├── SimResCheck │ │ ├── compare.py │ │ └── convert.py │ └── SoftwareSim │ │ └── sim.py └── Threshold │ ├── .gitignore │ ├── FunSimForHDL │ ├── Run.do │ ├── RunOver.do │ ├── Threshold.cr.mti │ └── Threshold.mpf │ ├── HDL │ ├── Threshold.srcs │ │ ├── component.xml │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── Threshold_TB.sv │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── Threshold.v │ │ └── xgui │ │ │ └── Threshold_v1_0.tcl │ └── Threshold.xpr │ ├── HDLSimDataGen │ └── create.py │ ├── ImageForTest │ └── conf.json │ ├── README.md │ ├── SimResCheck │ ├── compare.py │ └── convert.py │ └── SoftwareSim │ └── sim.py ├── README.md └── TestOnBoard ├── Geometry ├── .gitignore ├── ForBuild │ ├── Constraints.xdc │ └── Main.c └── build.tcl ├── LocalFilter ├── .gitignore ├── ForBuild │ ├── Constraints.xdc │ └── Main.c └── build.tcl ├── Point ├── .gitignore ├── ForBuild │ ├── Constraints.xdc │ └── Main.c └── build.tcl └── README.md /BoardInit_AXI/drivers/BoardInit_AXI_v1_0/data/BoardInit_AXI.mdd: -------------------------------------------------------------------------------- 1 | 2 | 3 | OPTION psf_version = 2.1; 4 | 5 | BEGIN DRIVER BoardInit_AXI 6 | OPTION supported_peripherals = (BoardInit_AXI); 7 | OPTION copyfiles = all; 8 | OPTION VERSION = 1.0; 9 | OPTION NAME = BoardInit_AXI; 10 | END DRIVER 11 | -------------------------------------------------------------------------------- /BoardInit_AXI/drivers/BoardInit_AXI_v1_0/data/BoardInit_AXI.tcl: -------------------------------------------------------------------------------- 1 | 2 | 3 | proc generate {drv_handle} { 4 | xdefine_include_file $drv_handle "xparameters.h" "BoardInit_AXI" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" 5 | } 6 | -------------------------------------------------------------------------------- /BoardInit_AXI/drivers/BoardInit_AXI_v1_0/src/BoardInit_AXI_selftest.c: -------------------------------------------------------------------------------- 1 | 2 | /***************************** Include Files *******************************/ 3 | #include "BoardInit_AXI.h" 4 | #include "xparameters.h" 5 | #include "stdio.h" 6 | #include "xil_io.h" 7 | 8 | /************************** Constant Definitions ***************************/ 9 | #define READ_WRITE_MUL_FACTOR 0x10 10 | 11 | /************************** Function Definitions ***************************/ 12 | /** 13 | * 14 | * Run a self-test on the driver/device. Note this may be a destructive test if 15 | * resets of the device are performed. 16 | * 17 | * If the hardware system is not built correctly, this function may never 18 | * return to the caller. 19 | * 20 | * @param baseaddr_p is the base address of the BOARDINIT_AXIinstance to be worked on. 21 | * 22 | * @return 23 | * 24 | * - XST_SUCCESS if all self-test code passed 25 | * - XST_FAILURE if any self-test code failed 26 | * 27 | * @note Caching must be turned off for this function to work. 28 | * @note Self test may fail if data memory and device are not on the same bus. 29 | * 30 | */ 31 | XStatus BOARDINIT_AXI_Reg_SelfTest(void * baseaddr_p) 32 | { 33 | u32 baseaddr; 34 | int write_loop_index; 35 | int read_loop_index; 36 | int Index; 37 | 38 | baseaddr = (u32) baseaddr_p; 39 | 40 | xil_printf("******************************\n\r"); 41 | xil_printf("* User Peripheral Self Test\n\r"); 42 | xil_printf("******************************\n\n\r"); 43 | 44 | /* 45 | * Write to user logic slave module register(s) and read back 46 | */ 47 | xil_printf("User logic slave module test...\n\r"); 48 | 49 | for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) 50 | BOARDINIT_AXI_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); 51 | for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) 52 | if ( BOARDINIT_AXI_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ 53 | xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); 54 | return XST_FAILURE; 55 | } 56 | 57 | xil_printf(" - slave register write/read passed\n\n\r"); 58 | 59 | return XST_SUCCESS; 60 | } 61 | -------------------------------------------------------------------------------- /BoardInit_AXI/drivers/BoardInit_AXI_v1_0/src/Makefile: -------------------------------------------------------------------------------- 1 | COMPILER= 2 | ARCHIVER= 3 | CP=cp 4 | COMPILER_FLAGS= 5 | EXTRA_COMPILER_FLAGS= 6 | LIB=libxil.a 7 | 8 | RELEASEDIR=../../../lib 9 | INCLUDEDIR=../../../include 10 | INCLUDES=-I./. -I${INCLUDEDIR} 11 | 12 | INCLUDEFILES=*.h 13 | LIBSOURCES=*.c 14 | OUTS = *.o 15 | 16 | libs: 17 | echo "Compiling BoardInit_AXI..." 18 | $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) 19 | $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 20 | make clean 21 | 22 | include: 23 | ${CP} $(INCLUDEFILES) $(INCLUDEDIR) 24 | 25 | clean: 26 | rm -rf ${OUTS} 27 | -------------------------------------------------------------------------------- /BoardInit_AXI/example_designs/debug_hw_design/BoardInit_AXI_v1_0_hw_test.tcl: -------------------------------------------------------------------------------- 1 | # Runtime Tcl commands to interact with - BoardInit_AXI_v1_0 2 | 3 | # Sourcing design address info tcl 4 | set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd 5 | source ${bd_path}/BoardInit_AXI_v1_0_include.tcl 6 | 7 | # jtag axi master interface hardware name, change as per your design. 8 | set jtag_axi_master hw_axi_1 9 | set ec 0 10 | 11 | # hw test script 12 | # Delete all previous axis transactions 13 | if { [llength [get_hw_axi_txns -quiet]] } { 14 | delete_hw_axi_txn [get_hw_axi_txns -quiet] 15 | } 16 | 17 | 18 | # Test all lite slaves. 19 | set wdata_1 abcd1234 20 | 21 | # Test: S00_AXI 22 | # Create a write transaction at s00_axi_addr address 23 | create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 24 | # Create a read transaction at s00_axi_addr address 25 | create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr 26 | # Initiate transactions 27 | run_hw_axi r_s00_axi_addr 28 | run_hw_axi w_s00_axi_addr 29 | run_hw_axi r_s00_axi_addr 30 | set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] 31 | # Compare read data 32 | if { $rdata_tmp == $wdata_1 } { 33 | puts "Data comparison test pass for - S00_AXI" 34 | } else { 35 | puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" 36 | inc ec 37 | } 38 | 39 | # Check error flag 40 | if { $ec == 0 } { 41 | puts "PTGEN_TEST: PASSED!" 42 | } else { 43 | puts "PTGEN_TEST: FAILED!" 44 | } 45 | 46 | -------------------------------------------------------------------------------- /Connector/ColorBin2Channels/srcs/ColorBin2Channels.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | ColorBin2Channels 7 | 8 | :Function 9 | Covert Bin to more channels. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-12 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | 53 | module ColorBin2Channels( 54 | b, 55 | channels 56 | ); 57 | 58 | parameter color_width = 8; 59 | parameter color_channels = 3; 60 | 61 | input b; 62 | output[color_channels * color_width - 1 : 0] channels; 63 | 64 | genvar i; 65 | generate 66 | `define h (i + 1) * color_width - 1 67 | `define l i * color_width 68 | for (i = 0; i < color_channels; i = i + 1) begin: channel 69 | assign channels[`h : `l] = b ? {color_width{1'b1}} : {color_width{1'b0}}; 70 | end 71 | `undef h 72 | `undef l 73 | 74 | endgenerate 75 | 76 | endmodule -------------------------------------------------------------------------------- /Connector/ColorGray2Channels/srcs/ColorGray2Channels.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | ColorGray2Channels 7 | 8 | :Function 9 | Covert Gray-scale to Channels. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-12 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | 53 | module ColorGray2Channels( 54 | gray, 55 | channels 56 | ); 57 | 58 | parameter color_width = 8; 59 | parameter color_channels = 3; 60 | 61 | input[color_width - 1 : 0] gray; 62 | output[color_channels * color_width - 1 : 0] channels; 63 | 64 | genvar i; 65 | generate 66 | `define h (i + 1) * color_width - 1 67 | `define l i * color_width 68 | for (i = 0; i < color_channels; i = i + 1) begin: channel 69 | assign channels[`h : `l] = gray; 70 | end 71 | `undef h 72 | `undef l 73 | 74 | endgenerate 75 | 76 | endmodule -------------------------------------------------------------------------------- /Connector/ColorRGB16toRGB24/srcs/ColorRGB16toRGB24.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | ColorRGB16toRGB24 7 | 8 | :Function 9 | Covert 16bits-RGB to 24bits-RGB. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-12 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | module ColorRGB16toRGB24( 53 | input[15 : 0] rgb16, 54 | output[23 : 0] rgb24 55 | ); 56 | 57 | assign rgb24[23 : 16] = {rgb16[15 : 11], rgb16[15 : 13]}; 58 | assign rgb24[15:8] = {rgb16[10 : 5], rgb16[10 : 9]}; 59 | assign rgb24[7:0] = {rgb16[4 : 0], rgb16[4 : 2]}; 60 | 61 | endmodule -------------------------------------------------------------------------------- /Connector/ColorRGB16toRGB24/xgui/ColorRGB16toRGB24_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Ports [ipgui::add_page $IPINST -name "Ports"] 6 | set_property tooltip {Ports} ${Ports} 7 | ipgui::add_static_text $IPINST -name "Discriptions" -parent ${Ports} -text { 8 | 9 | rgb16: 10 | 11 | unsigned. 12 | 13 | Description: Binary data. 14 | 15 | Range : 15 : 0 16 | 17 | 18 | 19 | rgb24: 20 | 21 | unsigned. 22 | 23 | Description: RGB data. 24 | 25 | Range: 23 : 0} 26 | 27 | #Adding Page 28 | set Help [ipgui::add_page $IPINST -name "Help"] 29 | set_property tooltip {Help} ${Help} 30 | ipgui::add_static_text $IPINST -name "Copyright" -parent ${Help} -text {Homepage for this project: 31 | 32 | http://fil.dtysky.moe 33 | 34 | 35 | 36 | Sources for this project: 37 | 38 | https://github.com/dtysky/FPGA-Imaging-Library 39 | 40 | 41 | 42 | My e-mail: 43 | 44 | dtysky@outlook.com 45 | 46 | 47 | 48 | My blog: 49 | 50 | http://dtysky.moe 51 | 52 | 53 | 54 | Copyright 2015, Tianyu Dai(dtysky). All Rights Reserved. 55 | 56 | This project is free software and released under the GNU Lesser General Public License (LGPL).} 57 | 58 | 59 | } 60 | 61 | proc update_PARAM_VALUE.color_width { PARAM_VALUE.color_width } { 62 | # Procedure called to update color_width when any of the dependent parameters in the arguments change 63 | } 64 | 65 | proc validate_PARAM_VALUE.color_width { PARAM_VALUE.color_width } { 66 | # Procedure called to validate color_width 67 | return true 68 | } 69 | 70 | 71 | proc update_MODELPARAM_VALUE.color_width { MODELPARAM_VALUE.color_width PARAM_VALUE.color_width } { 72 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 73 | set_property value [get_property value ${PARAM_VALUE.color_width}] ${MODELPARAM_VALUE.color_width} 74 | } -------------------------------------------------------------------------------- /Connector/ColorRGB24toVGA/srcs/ColorRGB24toVGA.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | ColorRGB24toVGA 7 | 8 | :Function 9 | Covert 24bits-RGB to VGA. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-12 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | 53 | module ColorRGB24toVGA( 54 | input[23:0] rgb24, 55 | output[15:0] vga 56 | ); 57 | 58 | assign vga[15:11] = rgb24[23:19]; 59 | assign vga[10:5] = rgb24[15:10]; 60 | assign vga[4:0] = rgb24[7:3]; 61 | 62 | endmodule -------------------------------------------------------------------------------- /Connector/ColorRGB24toVGA/xgui/ColorRGB24toVGA_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Ports [ipgui::add_page $IPINST -name "Ports"] 6 | set_property tooltip {Ports} ${Ports} 7 | ipgui::add_static_text $IPINST -name "Discriptions" -parent ${Ports} -text { 8 | 9 | rgb24: 10 | 11 | unsigned. 12 | 13 | Description: 24bits-RGB data. 14 | 15 | Range : 23 : 0 16 | 17 | 18 | 19 | vga: 20 | 21 | unsigned. 22 | 23 | Description: VGA data. 24 | 25 | Range: 15 : 0} 26 | 27 | #Adding Page 28 | set Help [ipgui::add_page $IPINST -name "Help"] 29 | set_property tooltip {Help} ${Help} 30 | ipgui::add_static_text $IPINST -name "Copyright" -parent ${Help} -text {Homepage for this project: 31 | 32 | http://fil.dtysky.moe 33 | 34 | 35 | 36 | Sources for this project: 37 | 38 | https://github.com/dtysky/FPGA-Imaging-Library 39 | 40 | 41 | 42 | My e-mail: 43 | 44 | dtysky@outlook.com 45 | 46 | 47 | 48 | My blog: 49 | 50 | http://dtysky.moe 51 | 52 | 53 | 54 | Copyright 2015, Tianyu Dai(dtysky). All Rights Reserved. 55 | 56 | This project is free software and released under the GNU Lesser General Public License (LGPL).} 57 | 58 | 59 | } -------------------------------------------------------------------------------- /Connector/DataCombin2/srcs/DataCombin2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: DataCombin2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DataCombin2(i0, i1, o); 24 | 25 | parameter data_width = 1; 26 | 27 | input[data_width - 1 : 0] i0, i1; 28 | output[2 * data_width - 1 : 0] o; 29 | 30 | assign o = {i1, i0}; 31 | 32 | endmodule -------------------------------------------------------------------------------- /Connector/DataCombin2/xgui/DataCombin2_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 12 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 16 | # Procedure called to validate data_width 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /Connector/DataCombin3/srcs/DataCombin3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: DataCombin3 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DataCombin3(i0, i1, i2, o); 24 | 25 | parameter data_width = 1; 26 | 27 | input[data_width - 1 : 0] i0, i1, i2; 28 | output[3 * data_width - 1 : 0] o; 29 | 30 | assign o = {i2, i1, i0}; 31 | 32 | endmodule -------------------------------------------------------------------------------- /Connector/DataCombin3/xgui/DataCombin3_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 12 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 16 | # Procedure called to validate data_width 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /Connector/DataDelay/srcs/DataDelay.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: DataDelay 8 | // Module Name: DataDelay 9 | // Project Name: Image processing project 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DataDelay(clk, in_data, out_data); 24 | 25 | parameter data_width = 8; 26 | parameter delay = 1; 27 | 28 | input clk; 29 | input[data_width - 1 : 0] in_data; 30 | output[data_width - 1 : 0] out_data; 31 | 32 | genvar i; 33 | generate 34 | for (i = 0; i < delay; i = i + 1) begin : pip 35 | reg[data_width - 1 : 0] tmp; 36 | if(i == 0) begin 37 | always @(posedge clk) 38 | tmp <= in_data; 39 | end else begin 40 | always @(posedge clk) 41 | tmp <= pip[i - 1].tmp; 42 | end 43 | end 44 | 45 | assign out_data = pip[delay - 1].tmp; 46 | 47 | endgenerate 48 | 49 | 50 | endmodule -------------------------------------------------------------------------------- /Connector/DataDelay/xgui/DataDelay_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "delay" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 13 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 17 | # Procedure called to validate data_width 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.delay { PARAM_VALUE.delay } { 22 | # Procedure called to update delay when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.delay { PARAM_VALUE.delay } { 26 | # Procedure called to validate delay 27 | return true 28 | } 29 | 30 | 31 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 32 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 33 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 34 | } 35 | 36 | proc update_MODELPARAM_VALUE.delay { MODELPARAM_VALUE.delay PARAM_VALUE.delay } { 37 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 38 | set_property value [get_property value ${PARAM_VALUE.delay}] ${MODELPARAM_VALUE.delay} 39 | } 40 | 41 | -------------------------------------------------------------------------------- /Connector/DataSplit4/srcs/DataSplit4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: DataSplit4 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DataSplit4(i, o0, o1, o2, o3); 24 | 25 | parameter data_width = 1; 26 | 27 | input[4 * data_width - 1 : 0] i; 28 | output[data_width - 1 : 0] o0, o1, o2, o3; 29 | 30 | assign o0 = i[1 * data_width - 1 : 0 * data_width]; 31 | assign o1 = i[2 * data_width - 1 : 1 * data_width]; 32 | assign o2 = i[3 * data_width - 1 : 2 * data_width]; 33 | assign o3 = i[4 * data_width - 1 : 3 * data_width]; 34 | 35 | endmodule -------------------------------------------------------------------------------- /Connector/DataSplit4/xgui/DataSplit4_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 12 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 16 | # Procedure called to validate data_width 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /Connector/DataWidthConvert/srcs/DataWidthConvert.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: DataWidthConvert 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DataWidthConvert(i, o); 24 | 25 | parameter data_width_in = 32; 26 | parameter data_width_out = 4; 27 | 28 | input[data_width_in - 1 : 0] i; 29 | output[data_width_out - 1 : 0] o; 30 | 31 | generate 32 | if(data_width_in >= data_width_out) begin 33 | assign o = i[data_width_in - 1 : 0]; 34 | end else begin 35 | assign o = {{data_width_out - data_width_in{1'b0}} ,i}; 36 | end 37 | endgenerate 38 | endmodule -------------------------------------------------------------------------------- /Connector/DataWidthConvert/xgui/DataWidthConvert_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width_in" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "data_width_out" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.data_width_in { PARAM_VALUE.data_width_in } { 13 | # Procedure called to update data_width_in when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.data_width_in { PARAM_VALUE.data_width_in } { 17 | # Procedure called to validate data_width_in 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.data_width_out { PARAM_VALUE.data_width_out } { 22 | # Procedure called to update data_width_out when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.data_width_out { PARAM_VALUE.data_width_out } { 26 | # Procedure called to validate data_width_out 27 | return true 28 | } 29 | 30 | 31 | proc update_MODELPARAM_VALUE.data_width_in { MODELPARAM_VALUE.data_width_in PARAM_VALUE.data_width_in } { 32 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 33 | set_property value [get_property value ${PARAM_VALUE.data_width_in}] ${MODELPARAM_VALUE.data_width_in} 34 | } 35 | 36 | proc update_MODELPARAM_VALUE.data_width_out { MODELPARAM_VALUE.data_width_out PARAM_VALUE.data_width_out } { 37 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 38 | set_property value [get_property value ${PARAM_VALUE.data_width_out}] ${MODELPARAM_VALUE.data_width_out} 39 | } 40 | 41 | -------------------------------------------------------------------------------- /Connector/DataWidthConvert/xgui/DataWidthConvert_v1_0.tcl~: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width_in" -parent ${Page_0} 7 | ipgui::add_param $IPINST -name "data_width_out" -parent ${Page_0} 8 | 9 | 10 | } 11 | 12 | proc update_PARAM_VALUE.data_width_in { PARAM_VALUE.data_width_in } { 13 | # Procedure called to update data_width_in when any of the dependent parameters in the arguments change 14 | } 15 | 16 | proc validate_PARAM_VALUE.data_width_in { PARAM_VALUE.data_width_in } { 17 | # Procedure called to validate data_width_in 18 | return true 19 | } 20 | 21 | proc update_PARAM_VALUE.data_width_out { PARAM_VALUE.data_width_out } { 22 | # Procedure called to update data_width_out when any of the dependent parameters in the arguments change 23 | } 24 | 25 | proc validate_PARAM_VALUE.data_width_out { PARAM_VALUE.data_width_out } { 26 | # Procedure called to validate data_width_out 27 | return true 28 | } 29 | 30 | 31 | proc update_MODELPARAM_VALUE.data_width_in { MODELPARAM_VALUE.data_width_in PARAM_VALUE.data_width_in } { 32 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 33 | set_property value [get_property value ${PARAM_VALUE.data_width_in}] ${MODELPARAM_VALUE.data_width_in} 34 | } 35 | 36 | proc update_MODELPARAM_VALUE.data_width_out { MODELPARAM_VALUE.data_width_out PARAM_VALUE.data_width_out } { 37 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 38 | set_property value [get_property value ${PARAM_VALUE.data_width_out}] ${MODELPARAM_VALUE.data_width_out} 39 | } 40 | 41 | -------------------------------------------------------------------------------- /Connector/Mux2/srcs/Mux2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: Mux2 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Mux2(sel, i0, i1, o); 24 | 25 | parameter data_width = 8; 26 | 27 | input sel; 28 | input[data_width - 1 : 0] i0; 29 | input[data_width - 1 : 0] i1; 30 | output[data_width - 1 : 0] o; 31 | 32 | assign o = sel == 0 ? i0 : i1; 33 | 34 | endmodule -------------------------------------------------------------------------------- /Connector/Mux2/xgui/Mux2_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 12 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 16 | # Procedure called to validate data_width 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /Connector/Mux4/srcs/Mux4.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: Mux4 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Mux4(sel, i0, i1, i2, i3, o); 24 | 25 | parameter data_width = 8; 26 | 27 | input[1 : 0] sel; 28 | input[data_width - 1 : 0] i0; 29 | input[data_width - 1 : 0] i1; 30 | input[data_width - 1 : 0] i2; 31 | input[data_width - 1 : 0] i3; 32 | output[data_width - 1 : 0] o; 33 | 34 | reg[data_width - 1 : 0] reg_o; 35 | 36 | always @(*) begin 37 | case (sel) 38 | 0 : reg_o <= i0; 39 | 1 : reg_o <= i1; 40 | 2 : reg_o <= i2; 41 | 3 : reg_o <= i3; 42 | default : /* default */; 43 | endcase 44 | end 45 | 46 | assign o = reg_o; 47 | 48 | endmodule -------------------------------------------------------------------------------- /Connector/Mux4/xgui/Mux4_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 12 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 16 | # Procedure called to validate data_width 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /Connector/Mux8/srcs/Mux8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: None 4 | // Engineer: Dai Tianyu (dtysky) 5 | // 6 | // Create Date: 2015/04/07 18:01:07 7 | // Design Name: 8 | // Module Name: Mux8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Mux8(sel, i0, i1, i2, i3, i4, i5, i6, i7, o); 24 | 25 | parameter data_width = 8; 26 | 27 | input[2 : 0] sel; 28 | input[data_width - 1 : 0] i0; 29 | input[data_width - 1 : 0] i1; 30 | input[data_width - 1 : 0] i2; 31 | input[data_width - 1 : 0] i3; 32 | input[data_width - 1 : 0] i4; 33 | input[data_width - 1 : 0] i5; 34 | input[data_width - 1 : 0] i6; 35 | input[data_width - 1 : 0] i7; 36 | output[data_width - 1 : 0] o; 37 | 38 | reg[data_width - 1 : 0] reg_o; 39 | 40 | always @(*) begin 41 | case (sel) 42 | 0 : reg_o <= i0; 43 | 1 : reg_o <= i1; 44 | 2 : reg_o <= i2; 45 | 3 : reg_o <= i3; 46 | 4 : reg_o <= i4; 47 | 5 : reg_o <= i5; 48 | 6 : reg_o <= i6; 49 | 7 : reg_o <= i7; 50 | default : /* default */; 51 | endcase 52 | end 53 | 54 | assign o = reg_o; 55 | 56 | endmodule -------------------------------------------------------------------------------- /Connector/Mux8/xgui/Mux8_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | set Page_0 [ipgui::add_page $IPINST -name "Page 0"] 6 | ipgui::add_param $IPINST -name "data_width" -parent ${Page_0} 7 | 8 | 9 | } 10 | 11 | proc update_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 12 | # Procedure called to update data_width when any of the dependent parameters in the arguments change 13 | } 14 | 15 | proc validate_PARAM_VALUE.data_width { PARAM_VALUE.data_width } { 16 | # Procedure called to validate data_width 17 | return true 18 | } 19 | 20 | 21 | proc update_MODELPARAM_VALUE.data_width { MODELPARAM_VALUE.data_width PARAM_VALUE.data_width } { 22 | # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value 23 | set_property value [get_property value ${PARAM_VALUE.data_width}] ${MODELPARAM_VALUE.data_width} 24 | } 25 | 26 | -------------------------------------------------------------------------------- /Connector/Or8/srcs/Or8.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/02/05 18:01:07 7 | // Design Name: 8 | // Module Name: Or8 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependenrgb24es: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Or8(i0, i1, i2, i3, i4, i5, i6, i7, o); 24 | 25 | input i0; 26 | input i1; 27 | input i2; 28 | input i3; 29 | input i4; 30 | input i5; 31 | input i6; 32 | input i7; 33 | output o; 34 | 35 | assign o = {i0, i1, i2, i3, i4, i5, i6, i7} == 0 ? 0 : 1; 36 | 37 | endmodule -------------------------------------------------------------------------------- /Connector/Or8/xgui/Or8_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /Generator/CountGenerator/CountGenerator.srcs/sources_1/new/gui/CountGenerator_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Generator/FrameController/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /Generator/FrameController/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.FrameController_TB 2 | run -all -------------------------------------------------------------------------------- /Generator/FrameController/HDL/FrameController.srcs/gui/FrameController_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_addr_width_VALUE {im_width im_height addr_width } { 3 | if {[expr log($im_width * $im_height)/log(2)] > [expr int(log($im_width * $im_height)/log(2))] } { 4 | set ${addr_width} [expr int(log($im_width * $im_height)/log(2)) + 1] 5 | } else { 6 | set ${addr_width} [expr int(log($im_width * $im_height)/log(2))] 7 | } 8 | 9 | } 10 | -------------------------------------------------------------------------------- /Generator/FrameController/HDLSimDataGen/create.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image 4 | import os, json 5 | from ctypes import * 6 | user32 = windll.LoadLibrary('user32.dll') 7 | MessageBox = lambda x:user32.MessageBoxA(0, x, 'Error', 0) 8 | 9 | FileFormat = ['.jpg', '.bmp'] 10 | Conf = json.load(open('../ImageForTest/conf.json', 'r'))['conf'] 11 | 12 | def show_error(e): 13 | MessageBox(e) 14 | exit(0) 15 | 16 | def name_format(root, name, ex, conf): 17 | return name 18 | 19 | def conf_format(im, conf): 20 | return '' 21 | 22 | def color_format(mode, color): 23 | color = [color] 24 | res = '' 25 | for c in color: 26 | tmp = bin(c)[2:] 27 | for i in xrange(10 - len(bin(c))): 28 | tmp = '0' + tmp 29 | res += tmp 30 | return res 31 | 32 | def create_dat(im, conf): 33 | data_src = im.getdata() 34 | xsize, ysize = im.size 35 | data_res = '' 36 | for color in data_src: 37 | data_res += color_format(im.mode, color) + '\n' 38 | return data_res[:-1] 39 | 40 | FileAll = [] 41 | for root,dirs,files in os.walk('../ImageForTest'): 42 | for f in files: 43 | name, ex=os.path.splitext(f) 44 | if ex in FileFormat: 45 | FileAll.append((root+'/', name, ex)) 46 | dat_index = '' 47 | for root, name, ex in FileAll: 48 | im_src = Image.open(root + name + ex) 49 | xsize, ysize = im_src.size 50 | for c in Conf: 51 | dat_res = open('../FunSimForHDL/%s.dat' \ 52 | % name_format(root, name, ex, c), 'w') 53 | dat_res.write('%d\n%d\n' % (xsize, ysize)) 54 | dat_res.write('%s' % conf_format(im_src, c)) 55 | dat_res.write(create_dat(im_src, c)) 56 | dat_index += '%s' % name_format(root, name, ex, c) 57 | dat_index += '\n' 58 | dat_res.close() 59 | dat_index = dat_index[:-1] 60 | dat_index_f = open('../FunSimForHDL/imgindex.dat','w') 61 | dat_index_f.write(dat_index) 62 | dat_index_f.close() -------------------------------------------------------------------------------- /Generator/FrameController/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | "default" 4 | ] 5 | } -------------------------------------------------------------------------------- /Generator/FrameController/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Generator/FrameController/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /Generator/FrameController2/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/* 5 | !HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v 6 | !HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2.xci 7 | FunSimForHDL/* 8 | !FunSimForHDL/*.mpf 9 | !FunSimForHDL/*.mti 10 | !FunSimForHDL/*.do 11 | !FunSimForHDL/*.md 12 | *.pyc -------------------------------------------------------------------------------- /Generator/FrameController2/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.FrameController2_TB 2 | run -all -------------------------------------------------------------------------------- /Generator/FrameController2/HDL/FrameController2.srcs/gui/FrameController2_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | proc gen_USERPARAMETER_addr_width_VALUE {im_width im_height addr_width } { 18 | if {[expr log($im_width * $im_height)/log(2)] > [expr int(log($im_width * $im_height)/log(2))] } { 19 | set ${addr_width} [expr int(log($im_width * $im_height)/log(2)) + 1] 20 | } else { 21 | set ${addr_width} [expr int(log($im_width * $im_height)/log(2))] 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /Generator/FrameController2/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | "default" 4 | ] 5 | } -------------------------------------------------------------------------------- /Generator/FrameController2/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support Gray-scale and 512x512 images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Generator/FrameController2/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1 : 1000000.000000 4 | 2 : 1000000.000000 5 | 3 : 1000000.000000 6 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /Generator/FrameController2/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
123Total
1000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /Generator/FrameController2/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /Generator/RowsGenerator/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc 9 | HDL/RowsGenerator.srcs/sources_1/ip/Fifo8xWidthRows/* 10 | !HDL/RowsGenerator.srcs/sources_1/ip/Fifo8xWidthRows/Fifo8xWidthRows.xci 11 | !HDL/RowsGenerator.srcs/sources_1/ip/Fifo8xWidthRows/Fifo8xWidthRows_funcsim.v 12 | HDL/RowsGenerator.srcs/sources_1/ip/Fifo1xWidthRows/* 13 | !HDL/RowsGenerator.srcs/sources_1/ip/Fifo1xWidthRows/Fifo1xWidthRows.xci 14 | HDL/RowsGenerator.srcs/sources_1/ip/Fifo4xWidthRows/* 15 | !HDL/RowsGenerator.srcs/sources_1/ip/Fifo4xWidthRows/Fifo4xWidthRows.xci 16 | HDL/RowsGenerator.srcs/sources_1/ip/Fifo12xWidthRows/* 17 | !HDL/RowsGenerator.srcs/sources_1/ip/Fifo12xWidthRows/Fifo12xWidthRows.xci 18 | SimResCheck/* 19 | !SimResCheck/*.py -------------------------------------------------------------------------------- /Generator/RowsGenerator/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.RowsGenerator_TB 2 | run -all -------------------------------------------------------------------------------- /Generator/RowsGenerator/HDL/RowsGenerator.srcs/gui/RowsGenerator_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_width_bits } { 3 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 4 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 5 | } else { 6 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /Generator/RowsGenerator/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | {"width": 3}, 4 | {"width": 5} 5 | ] 6 | } -------------------------------------------------------------------------------- /Generator/RowsGenerator/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support 512xN, Gray-scale and binary images and conf['width'] only can be 3 and 5 !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.7 and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configurations for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Generator/RowsGenerator/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.dat' % name 10 | 11 | def convert(data, fo): 12 | mode = data[2].strip() 13 | if mode == 'L': 14 | rsize = len(data[3].strip()) / 8 15 | cszie = 8 16 | else: 17 | rsize = len(data[3].strip()) 18 | cszie = 1 19 | fo.write('Showed row1 -> rowN\nBut the lowest color_width-bits of this are the first row !\n\n') 20 | for p in data[3:]: 21 | data_res = '' 22 | for i in xrange(rsize): 23 | j = rsize - 1 - i 24 | data_res += '%d ' % eval('0b' + p[j * cszie : (j + 1) * cszie]) 25 | fo.write('%s\n' % data_res[:-1]) 26 | 27 | FileAll = [] 28 | for root, dirs, files in os.walk('../FunSimForHDL'): 29 | for f in files: 30 | name, ex=os.path.splitext(f) 31 | if ex in FileFormat: 32 | FileAll.append((root+'/', name, ex)) 33 | for root, name, ex in FileAll: 34 | dat_src = open(root + name + ex) 35 | data_src = dat_src.readlines() 36 | convert(data_src, open(name_format(root, name, ex), 'w')) 37 | dat_src.close() -------------------------------------------------------------------------------- /Generator/WindowGenerator/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc 9 | SimResCheck/* 10 | !SimResCheck/*.py -------------------------------------------------------------------------------- /Generator/WindowGenerator/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.WindowGenerator_TB 2 | run -all -------------------------------------------------------------------------------- /Generator/WindowGenerator/FunSimForHDL/WindowGenerator.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/WindowGenerator.srcs/sim_1/new/WindowGenerator_TB.sv {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Master/Generator/WindowGenerator/HDL/WindowGenerator.srcs/sim_1/new/WindowGenerator_TB.sv 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module CLOCK 4 | -- Compiling interface TBInterface 5 | -- Compiling module WindowGenerator_TB 6 | 7 | Top level modules: 8 | WindowGenerator_TB 9 | 10 | } {} {}} 11 | -------------------------------------------------------------------------------- /Generator/WindowGenerator/HDL/WindowGenerator.srcs/gui/WindowGenerator_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_window_width_half_VALUE {window_width_half window_width } { 3 | set ${window_width_half} [expr int($window_width/2)] 4 | } 5 | -------------------------------------------------------------------------------- /Generator/WindowGenerator/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | {"width": 3}, 4 | {"width": 5} 5 | ] 6 | } -------------------------------------------------------------------------------- /Generator/WindowGenerator/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support 512xN, Gray-scale and binary images and conf['width'] only can be 3 and 5 !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.7 and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configurations for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Generator/WindowGenerator/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os, math 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.dat' % name 10 | 11 | def convert(data, fo): 12 | mode = data[2].strip() 13 | if mode == 'L': 14 | wsize = int(math.sqrt(len(data[3].strip()) / 8)) 15 | cszie = 8 16 | else: 17 | wsize = int(math.sqrt(len(data[3].strip()))) 18 | cszie = 1 19 | for p in data[3:]: 20 | data_res = '' 21 | x = 0 22 | for i in xrange(wsize * wsize): 23 | j = wsize * wsize - 1 - i 24 | data_res += '%d ' % eval('0b' + p[j * cszie : (j + 1) * cszie]) 25 | if x == wsize - 1: 26 | x = 0 27 | data_res = data_res[:-1] + '\n' 28 | else: 29 | x += 1 30 | fo.write('%s\n' % data_res) 31 | 32 | FileAll = [] 33 | for root, dirs, files in os.walk('../FunSimForHDL'): 34 | for f in files: 35 | name, ex=os.path.splitext(f) 36 | if ex in FileFormat: 37 | FileAll.append((root+'/', name, ex)) 38 | for root, name, ex in FileAll: 39 | dat_src = open(root + name + ex) 40 | data_src = dat_src.readlines() 41 | convert(data_src, open(name_format(root, name, ex), 'w')) 42 | dat_src.close() -------------------------------------------------------------------------------- /Generator/WindowGenerator/SoftwareSim/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /Geometry/Crop/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/* 5 | !HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2_funcsim.v 6 | !HDL/FrameController2.srcs/sources_1/ip/Multiplier12x12FR2/Multiplier12x12FR2.xci 7 | FunSimForHDL/* 8 | !FunSimForHDL/*.mpf 9 | !FunSimForHDL/*.mti 10 | !FunSimForHDL/*.do 11 | !FunSimForHDL/*.md 12 | *.pyc -------------------------------------------------------------------------------- /Geometry/Crop/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.Crop_TB 2 | run -all -------------------------------------------------------------------------------- /Geometry/Crop/HDL/Crop.srcs/gui/Crop_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Geometry/Crop/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "top" : 20, 5 | "bottom" : 492, 6 | "left" : 20, 7 | "right" : 492 8 | }, 9 | { 10 | "top" : 100, 11 | "bottom" : 402, 12 | "left" : 200, 13 | "right" : 302 14 | } 15 | ] 16 | } -------------------------------------------------------------------------------- /Geometry/Crop/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB/Gray-scale and 512x512 images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Geometry/Crop/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Geometry/Crop/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-100x402x200x302 : 1000000.000000 4 | 1-20x492x20x492 : 1000000.000000 5 | 2-100x402x200x302 : 1000000.000000 6 | 2-20x492x20x492 : 1000000.000000 7 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /Geometry/Crop/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
1-100x402x200x3021-20x492x20x4922-100x402x200x3022-20x492x20x492Total
1000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /Geometry/Crop/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | mode = data[2].strip() 13 | xsize, ysize = int(data[0]), int(data[1]) 14 | im_res = Image.new(mode, (xsize, ysize)) 15 | data_res = list(im_res.getdata()) 16 | for p in data[3:]: 17 | if mode == 'RGB': 18 | x, y, r, g, b = p.strip().split(' ') 19 | data_res[int(y) * xsize + int(x)] = (int(r), int(g), int(b)) 20 | else: 21 | x, y, g = p.strip().split(' ') 22 | data_res[int(y) * xsize + int(x)] = int(g) 23 | im_res.putdata(data_res) 24 | return im_res 25 | 26 | FileAll = [] 27 | for root, dirs, files in os.walk('../FunSimForHDL'): 28 | for f in files: 29 | name, ex=os.path.splitext(f) 30 | if ex in FileFormat: 31 | FileAll.append((root+'/', name, ex)) 32 | for root, name, ex in FileAll: 33 | dat_src = open(root + name + ex) 34 | data_src = dat_src.readlines() 35 | convert(data_src).save(name_format(root, name, ex)) 36 | dat_src.close() -------------------------------------------------------------------------------- /Geometry/Mirror/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | !FunSimForHDL/*.md 9 | *.pyc -------------------------------------------------------------------------------- /Geometry/Mirror/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.Mirror_TB 2 | run -all -------------------------------------------------------------------------------- /Geometry/Mirror/HDL/Mirror.srcs/gui/Mirror_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Geometry/Mirror/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "mode" : "Horizontal" 5 | }, 6 | { 7 | "mode" : "Vertical" 8 | }, 9 | { 10 | "mode" : "All" 11 | } 12 | ] 13 | } -------------------------------------------------------------------------------- /Geometry/Mirror/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB/Gray-scale and 512x512 images, and the conf["mode"] just support "Horizontal", "Vertical" and "All" !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Geometry/Mirror/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Geometry/Mirror/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-All : 1000000.000000 4 | 1-Horizontal : 1000000.000000 5 | 1-Vertical : 1000000.000000 6 | 2-All : 1000000.000000 7 | 2-Horizontal : 1000000.000000 8 | 2-Vertical : 1000000.000000 9 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /Geometry/Mirror/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 |
1-All1-Horizontal1-Vertical2-All2-Horizontal2-VerticalTotal
1000000.001000000.001000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /Geometry/Mirror/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | mode = data[2].strip() 13 | xsize, ysize = int(data[0]), int(data[1]) 14 | im_res = Image.new(mode, (xsize, ysize)) 15 | data_res = list(im_res.getdata()) 16 | for p in data[3:]: 17 | if mode == 'RGB': 18 | x, y, r, g, b = p.strip().split(' ') 19 | data_res[int(y) * xsize + int(x)] = (int(r), int(g), int(b)) 20 | else: 21 | x, y, g = p.strip().split(' ') 22 | data_res[int(y) * xsize + int(x)] = int(g) 23 | im_res.putdata(data_res) 24 | return im_res 25 | 26 | FileAll = [] 27 | for root, dirs, files in os.walk('../FunSimForHDL'): 28 | for f in files: 29 | name, ex=os.path.splitext(f) 30 | if ex in FileFormat: 31 | FileAll.append((root+'/', name, ex)) 32 | for root, name, ex in FileAll: 33 | dat_src = open(root + name + ex) 34 | data_src = dat_src.readlines() 35 | convert(data_src).save(name_format(root, name, ex)) 36 | dat_src.close() -------------------------------------------------------------------------------- /Geometry/Pan/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | !FunSimForHDL/*.md 9 | *.pyc -------------------------------------------------------------------------------- /Geometry/Pan/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.Pan_TB 2 | run -all -------------------------------------------------------------------------------- /Geometry/Pan/HDL/Pan.srcs/gui/Pan_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Geometry/Pan/HDL/Pan.srcs/sim_1/import/True2Comp.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | True2Comp 7 | 8 | :Function 9 | Convert true code to complemental code. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-01 19 | 20 | Copyright (C) 2015 Dai Tianyu (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://ifl.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | 53 | module True2Comp( 54 | true, 55 | complement); 56 | 57 | parameter data_channel = 1; 58 | parameter data_width = 17; 59 | 60 | input[data_channel * data_width - 1 : 0] true; 61 | output[data_channel * data_width - 1 : 0] complement; 62 | 63 | genvar i; 64 | generate 65 | `define h (i + 1) * data_width - 1 66 | `define l i * data_width 67 | for (i = 0; i < data_channel; i = i + 1) begin 68 | assign complement[`h : `l] = true[`h] == 0 ? 69 | true[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1}; 70 | end 71 | `undef h 72 | `undef l 73 | endgenerate 74 | endmodule -------------------------------------------------------------------------------- /Geometry/Pan/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "xoffset" : -100, 5 | "yoffset" : 100 6 | }, 7 | { 8 | "xoffset" : 200, 9 | "yoffset" : -50 10 | } 11 | ] 12 | } -------------------------------------------------------------------------------- /Geometry/Pan/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB/Gray-scale and 512x512 images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Geometry/Pan/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Geometry/Pan/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1--100x100 : 1000000.000000 4 | 1-200x-50 : 1000000.000000 5 | 2--100x100 : 1000000.000000 6 | 2-200x-50 : 1000000.000000 7 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /Geometry/Pan/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
1--100x1001-200x-502--100x1002-200x-50Total
1000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /Geometry/Pan/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | mode = data[2].strip() 13 | xsize, ysize = int(data[0]), int(data[1]) 14 | im_res = Image.new(mode, (xsize, ysize)) 15 | data_res = list(im_res.getdata()) 16 | for p in data[3:]: 17 | if mode == 'RGB': 18 | x, y, r, g, b = p.strip().split(' ') 19 | data_res[int(y) * xsize + int(x)] = (int(r), int(g), int(b)) 20 | else: 21 | x, y, g = p.strip().split(' ') 22 | data_res[int(y) * xsize + int(x)] = int(g) 23 | im_res.putdata(data_res) 24 | return im_res 25 | 26 | FileAll = [] 27 | for root, dirs, files in os.walk('../FunSimForHDL'): 28 | for f in files: 29 | name, ex=os.path.splitext(f) 30 | if ex in FileFormat: 31 | FileAll.append((root+'/', name, ex)) 32 | for root, name, ex in FileAll: 33 | dat_src = open(root + name + ex) 34 | data_src = dat_src.readlines() 35 | convert(data_src).save(name_format(root, name, ex)) 36 | dat_src.close() -------------------------------------------------------------------------------- /Geometry/Rotate/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | !FunSimForHDL/*.md 9 | *.pyc 10 | HDL/Rotate.srcs/sources_1/ip/Multiplier13Sx20SRTT/* 11 | !HDL/Rotate.srcs/sources_1/ip/Multiplier13Sx20SRTT/Multiplier13Sx20SRTT.xci 12 | !HDL/Rotate.srcs/sources_1/ip/Multiplier13Sx20SRTT/Multiplier13Sx20SRTT_funcsim.v -------------------------------------------------------------------------------- /Geometry/Rotate/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.Rotate_TB 2 | run -all -------------------------------------------------------------------------------- /Geometry/Rotate/HDL/Rotate.srcs/gui/Rotate_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Geometry/Rotate/HDL/Rotate.srcs/sim_1/import/BRam8x512x512_funcsim.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | module BRam8x512x512( 3 | clka, 4 | wea, 5 | addra, 6 | dina, 7 | clkb, 8 | addrb, 9 | doutb); 10 | input clka; 11 | input [0:0]wea; 12 | input [17:0]addra; 13 | input [7:0]dina; 14 | input clkb; 15 | input [17:0]addrb; 16 | output reg [7:0]doutb; 17 | 18 | reg[7 : 0] mem[0 : 2 ** 18 - 1]; 19 | always @(posedge clka) begin 20 | if(wea) 21 | mem[addra] <= dina; 22 | else 23 | mem[addra] <= mem[addra]; 24 | end 25 | 26 | always @(posedge clkb) 27 | doutb <= mem[addrb]; 28 | 29 | endmodule -------------------------------------------------------------------------------- /Geometry/Rotate/HDL/Rotate.srcs/sources_1/new/sin_cos_gen.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | # Generateing LUTs for sin and cos. 3 | from math import sin, cos, radians 4 | 5 | # Convert num(1sign-1bit.18bis) to 20bits fixed binary decimal 6 | def format_d(num): 7 | r, d = format(num, 'f').split('.') 8 | r = '0' + r[0] if len(r) == 1 else '1' + r[1] 9 | d = float('0.' + d) 10 | res = '' 11 | for i in xrange(18): 12 | d = d * 2 13 | res += '1' if d >= 1 else '0' 14 | d = d - 1 if d >= 1 else d 15 | res = r[1] + res 16 | if r[0] == '1': 17 | if eval(res) == 0: 18 | res = '0' 19 | else: 20 | res = bin(2 ** 19 - eval('0b' + res))[2:] 21 | for i in xrange(19 - len(res)): 22 | res = '0' + res 23 | res = r[0] + res 24 | if res == '10000000000000000000': 25 | res = '00000000000000000000' 26 | return res 27 | 28 | fo = open('SinLUT.dat', 'w') 29 | fo.write('module SinLUT(angle, value);\n') 30 | fo.write('\tinput[8 : 0] angle;\n') 31 | fo.write('\toutput[19 : 0] value;\n') 32 | fo.write('\treg[19 : 0] reg_value;\n') 33 | fo.write('\tassign value = reg_value;\n') 34 | fo.write('\talways@(*) begin\n') 35 | fo.write('\t\tcase(angle)\n') 36 | for i in xrange(360): 37 | fo.write("\t\t\t%d : reg_value <= 20'b%s;\n" % (i, format_d(sin(radians(i))))) 38 | fo.write('\t\t\tdefault: reg_value <= 0;\n') 39 | fo.write('\t\tendcase\n') 40 | fo.write('\tend\n') 41 | fo.write('endmodule') 42 | 43 | fo = open('CosLUT.dat', 'w') 44 | fo.write('module CosLUT(angle, value);\n') 45 | fo.write('\tinput[8 : 0] angle;\n') 46 | fo.write('\toutput[19 : 0] value;\n') 47 | fo.write('\treg[19 : 0] reg_value;\n') 48 | fo.write('\tassign value = reg_value;\n') 49 | fo.write('\talways@(*) begin\n') 50 | fo.write('\t\tcase(angle)\n') 51 | for i in xrange(360): 52 | fo.write("\t\t\t%d : reg_value <= 20'b%s;\n" % (i, format_d(cos(radians(i))))) 53 | fo.write('\t\t\tdefault: reg_value <= 0;\n') 54 | fo.write('\t\tendcase\n') 55 | fo.write('\tend\n') 56 | fo.write('endmodule') -------------------------------------------------------------------------------- /Geometry/Rotate/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "angle" : 45 5 | }, 6 | { 7 | "angle" : 131 8 | }, 9 | { 10 | "angle" : 270 11 | } 12 | ] 13 | } -------------------------------------------------------------------------------- /Geometry/Rotate/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support Gray-scale and 512x512 images, and angle for simulations for this module just supports 0 - 359 !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Geometry/Rotate/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Geometry/Rotate/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-131 : 1000000.000000 4 | 1-270 : 54.894846 5 | 1-45 : 1000000.000000 6 | Totle : 666684.964949 -------------------------------------------------------------------------------- /Geometry/Rotate/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
1-1311-2701-45Total
1000000.0054.891000000.00666684.96
-------------------------------------------------------------------------------- /Geometry/Rotate/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | xsize, ysize = int(data[0]), int(data[1]) 13 | data_res = [] 14 | for p in data[2:]: 15 | data_res.append(int(p)) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /Geometry/Scale/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | !FunSimForHDL/*.md 9 | *.pyc 10 | HDL/Scale.srcs/sources_1/ip/Multiplier12x24SCL/* 11 | !HDL/Scale.srcs/sources_1/ip/Multiplier12x24SCL/Multiplier12x24SCL.xci 12 | !HDL/Scale.srcs/sources_1/ip/Multiplier12x24SCL/Multiplier12x24SCL_funcsim.v -------------------------------------------------------------------------------- /Geometry/Scale/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.Scale_TB 2 | run -all -------------------------------------------------------------------------------- /Geometry/Scale/HDL/Scale.srcs/gui/Scale_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Geometry/Scale/HDL/Scale.srcs/sim_1/import/BRam8x512x512_funcsim.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | module BRam8x512x512( 3 | clka, 4 | wea, 5 | addra, 6 | dina, 7 | clkb, 8 | addrb, 9 | doutb); 10 | input clka; 11 | input [0:0]wea; 12 | input [17:0]addra; 13 | input [7:0]dina; 14 | input clkb; 15 | input [17:0]addrb; 16 | output reg [7:0]doutb; 17 | 18 | reg[7 : 0] mem[0 : 2 ** 18 - 1]; 19 | always @(posedge clka) begin 20 | if(wea) 21 | mem[addra] <= dina; 22 | else 23 | mem[addra] <= mem[addra]; 24 | end 25 | 26 | always @(posedge clkb) 27 | doutb <= mem[addrb]; 28 | 29 | endmodule -------------------------------------------------------------------------------- /Geometry/Scale/HDL/Scale.srcs/sources_1/new/FixedRoundUnsigned.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | FixedRoundUnsigned 7 | 8 | :Function 9 | Round for unsigned fixed number. 10 | Give the first output after 1 cycle. 11 | 12 | :Module 13 | Main module 14 | 15 | :Version 16 | 1.0 17 | 18 | :Modified 19 | 2015-05-16 20 | 21 | Copyright (C) 2015 Tianyu Dai (dtysky) 22 | 23 | This library is free software; you can redistribute it and/or 24 | modify it under the terms of the GNU Lesser General Public 25 | License as published by the Free Software Foundation; either 26 | version 2.1 of the License, or (at your option) any later version. 27 | 28 | This library is distributed in the hope that it will be useful, 29 | but WITHOUT ANY WARRANTY; without even the implied warranty of 30 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 31 | Lesser General Public License for more details. 32 | 33 | You should have received a copy of the GNU Lesser General Public 34 | License along with this library; if not, write to the Free Software 35 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 36 | 37 | Homepage for this project: 38 | http://fil.dtysky.moe 39 | 40 | Sources for this project: 41 | https://github.com/dtysky/FPGA-Imaging-Library 42 | 43 | My e-mail: 44 | dtysky@outlook.com 45 | 46 | My blog: 47 | http://dtysky.moe 48 | 49 | */ 50 | `timescale 1ns / 1ps 51 | 52 | module FixedRoundUnsigned( 53 | clk, 54 | fixed_num, 55 | rounded_num 56 | ); 57 | 58 | parameter num_width = 42; 59 | parameter fixed_pos = 16; 60 | 61 | input clk; 62 | input [num_width - 1 : 0] fixed_num; 63 | output [num_width - fixed_pos - 1 : 0] rounded_num; 64 | 65 | reg [num_width - fixed_pos - 1 : 0] reg_rounded_num; 66 | 67 | assign rounded_num = reg_rounded_num; 68 | 69 | always @(posedge clk) 70 | reg_rounded_num <= fixed_num[fixed_pos - 1] == 0 ? 71 | fixed_num[num_width -1 : fixed_pos] : 72 | fixed_num[num_width -1 : fixed_pos] + 1; 73 | 74 | endmodule -------------------------------------------------------------------------------- /Geometry/Scale/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "xscale" : 1.97, 5 | "yscale" : 0.213 6 | }, 7 | { 8 | "xscale" : 0.391, 9 | "yscale" : 2.17 10 | }, 11 | { 12 | "xscale" : 0.4, 13 | "yscale" : 0.4 14 | } 15 | ] 16 | } -------------------------------------------------------------------------------- /Geometry/Scale/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support Gray-scale and 512x512 images, and scales for simulations for this module just supports 0.x - 63.x !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Geometry/Scale/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-pipeline-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Geometry/Scale/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-0.391x2.17 : 1000000.000000 4 | 1-0.4x0.4 : 1000000.000000 5 | 1-1.97x0.213 : 1000000.000000 6 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /Geometry/Scale/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
1-0.391x2.171-0.4x0.41-1.97x0.213Total
1000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /Geometry/Scale/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | xsize, ysize = int(data[0]), int(data[1]) 13 | data_res = [] 14 | for p in data[2:]: 15 | data_res.append(int(p)) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /Geometry/Shear/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | !FunSimForHDL/*.md 9 | *.pyc 10 | HDL/Shear.srcs/sources_1/ip/Multiplier12x25SSHR/* 11 | !HDL/Shear.srcs/sources_1/ip/Multiplier12x25SSHR/Multiplier12x25SSHR.xci 12 | !HDL/Shear.srcs/sources_1/ip/Multiplier12x25SSHR/Multiplier12x25SSHR_funcsim.v -------------------------------------------------------------------------------- /Geometry/Shear/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.Shear_TB 2 | run -all -------------------------------------------------------------------------------- /Geometry/Shear/HDL/Shear.srcs/gui/Shear_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_im_width_bits_VALUE {im_width im_height im_width_bits } { 3 | if {$im_width > $im_height } { 4 | if {[expr log($im_width)/log(2)] > [expr int(log($im_width)/log(2))] } { 5 | set ${im_width_bits} [expr int(log($im_width)/log(2)) + 1] 6 | } else { 7 | set ${im_width_bits} [expr int(log($im_width)/log(2))] 8 | } 9 | } else { 10 | if {[expr log($im_height)/log(2)] > [expr int(log($im_height)/log(2))] } { 11 | set ${im_width_bits} [expr int(log($im_height)/log(2)) + 1] 12 | } else { 13 | set ${im_width_bits} [expr int(log($im_height)/log(2))] 14 | } 15 | } 16 | } 17 | -------------------------------------------------------------------------------- /Geometry/Shear/HDL/Shear.srcs/sim_1/import/BRam8x512x512_funcsim.v: -------------------------------------------------------------------------------- 1 | `timescale 1 ps / 1 ps 2 | module BRam8x512x512( 3 | clka, 4 | wea, 5 | addra, 6 | dina, 7 | clkb, 8 | addrb, 9 | doutb); 10 | input clka; 11 | input [0:0]wea; 12 | input [17:0]addra; 13 | input [7:0]dina; 14 | input clkb; 15 | input [17:0]addrb; 16 | output reg [7:0]doutb; 17 | 18 | reg[7 : 0] mem[0 : 2 ** 18 - 1]; 19 | always @(posedge clka) begin 20 | if(wea) 21 | mem[addra] <= dina; 22 | else 23 | mem[addra] <= mem[addra]; 24 | end 25 | 26 | always @(posedge clkb) 27 | doutb <= mem[addrb]; 28 | 29 | endmodule -------------------------------------------------------------------------------- /Geometry/Shear/HDL/Shear.srcs/sim_1/import/True2Comp.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | True2Comp 7 | 8 | :Function 9 | Convert true code to complemental code. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-01 19 | 20 | Copyright (C) 2015 Dai Tianyu (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://ifl.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | 53 | module True2Comp( 54 | true, 55 | complement); 56 | 57 | parameter data_channel = 1; 58 | parameter data_width = 17; 59 | 60 | input[data_channel * data_width - 1 : 0] true; 61 | output[data_channel * data_width - 1 : 0] complement; 62 | 63 | genvar i; 64 | generate 65 | `define h (i + 1) * data_width - 1 66 | `define l i * data_width 67 | for (i = 0; i < data_channel; i = i + 1) begin 68 | assign complement[`h : `l] = true[`h] == 0 ? 69 | true[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1}; 70 | end 71 | `undef h 72 | `undef l 73 | endgenerate 74 | endmodule -------------------------------------------------------------------------------- /Geometry/Shear/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "ush" : 0.5, 5 | "vsh" : 0.5 6 | }, 7 | { 8 | "ush" : -1.671, 9 | "vsh" : 0.539 10 | }, 11 | { 12 | "ush" : 0.824, 13 | "vsh" : -1.793 14 | } 15 | ] 16 | } -------------------------------------------------------------------------------- /Geometry/Shear/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support Gray-scale and 512x512 images, and shs for simulations for this module just supports -63.x - 63.x !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Geometry/Shear/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Geometry/Shear/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1--1.671x0.539 : 52.357439 4 | 1-0.5x0.5 : 52.378843 5 | 1-0.824x-1.793 : 1000000.000000 6 | Totle : 333368.245427 -------------------------------------------------------------------------------- /Geometry/Shear/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 |
1--1.671x0.5391-0.5x0.51-0.824x-1.793Total
52.3652.381000000.00333368.25
-------------------------------------------------------------------------------- /Geometry/Shear/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | xsize, ysize = int(data[0]), int(data[1]) 13 | data_res = [] 14 | for p in data[2:]: 15 | data_res.append(int(p)) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /InOut/Bram8x320x240/src/Bram8x320x240.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2014/08/30 11:01:22 7 | // Design Name: 8 | // Module Name: Bram8x320x240 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Bram8x320x240( 24 | input [7:0] dina, 25 | input [16:0] addra, 26 | input clka,wea,clkb, 27 | output [7:0] doutb, 28 | input [16:0] addrb 29 | 30 | ); 31 | 32 | BlcokRam8x320x240 u_fb( 33 | .clka ( clka), 34 | .wea (wea), 35 | .addra( addra), 36 | .dina ( dina), 37 | 38 | .clkb ( clkb), 39 | .addrb ( addrb), 40 | .doutb ( doutb) 41 | ); 42 | endmodule 43 | -------------------------------------------------------------------------------- /InOut/Bram8x320x240/xgui/Bram8x320x240_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /InOut/Cam/src/camCap.v: -------------------------------------------------------------------------------- 1 | module camCap( 2 | input pclk, 3 | input vsync, 4 | input href, 5 | input[7:0] d, 6 | output[16:0] addr, 7 | output reg[15:0] dout, 8 | output reg we, 9 | output wclk 10 | ); 11 | 12 | reg [15:0] d_latch; 13 | reg [16:0] address; 14 | reg [16:0] address_next; 15 | reg [1:0] wr_hold; 16 | reg [1:0] cnt; 17 | 18 | initial d_latch = 16'b0; 19 | initial address = 19'b0; 20 | initial address_next = 19'b0; 21 | initial wr_hold = 2'b0; 22 | initial cnt = 2'b0; 23 | 24 | assign addr = address; 25 | assign wclk = pclk; 26 | 27 | always@(posedge pclk)begin 28 | 29 | if( vsync ==1) begin 30 | 31 | address <=17'b0; 32 | address_next <= 17'b0; 33 | wr_hold <= 2'b0; 34 | cnt <= 2'b0; 35 | 36 | end else begin 37 | 38 | if(address<76800) 39 | address <= address_next; 40 | else 41 | address <= 76800; 42 | 43 | we <= wr_hold[1]; 44 | wr_hold <= {wr_hold[0] , (href &&( ! wr_hold[0])) }; 45 | d_latch <= {d_latch[7:0] , d}; 46 | 47 | if (wr_hold[1] == 1) begin 48 | address_next <= address_next+1; 49 | dout[15:0] <= d_latch[15:0]; 50 | end 51 | 52 | end; 53 | end 54 | 55 | endmodule -------------------------------------------------------------------------------- /InOut/Cam/xgui/camCap_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | ipgui::add_param $IPINST -name "Component_Name" 4 | #Adding Page 5 | ipgui::add_page $IPINST -name "Page 0" 6 | 7 | 8 | } 9 | 10 | 11 | -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/FunSimForHDL/ErosionDilationBin.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/ErosionDilationBin.srcs/sources_1/new/ErosionDilationBin.v {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/ErosionDilationBin/HDL/ErosionDilationBin.srcs/sources_1/new/ErosionDilationBin.v 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module ErosionDilationBin 4 | 5 | Top level modules: 6 | ErosionDilationBin 7 | 8 | } {} {}} ../HDL/ErosionDilationBin.srcs/sim_1/new/ErosionDilationBin_TB.sv {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/ErosionDilationBin/HDL/ErosionDilationBin.srcs/sim_1/new/ErosionDilationBin_TB.sv 9 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 10 | -- Compiling module CLOCK 11 | -- Compiling interface TBInterface 12 | -- Compiling module ErosionDilationBin_TB 13 | 14 | Top level modules: 15 | ErosionDilationBin_TB 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.ErosionDilationBin_TB 2 | run -all -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/HDL/ErosionDilationBin.srcs/gui/ErosionDilationBin_v1_1.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_pip_counter_VALUE {window_size pip_counter } { 3 | if {$window_size == 2} { 4 | set ${pip_counter} 1 5 | } elseif {$window_size == 3} { 6 | set ${pip_counter} 3 7 | } elseif {$window_size == 4} { 8 | set ${pip_counter} 4 9 | } elseif {$window_size == 5} { 10 | set ${pip_counter} 4 11 | } elseif {$window_size == 6} { 12 | set ${pip_counter} 5 13 | } elseif {$window_size == 7} { 14 | set ${pip_counter} 5 15 | } elseif {$window_size == 8} { 16 | set ${pip_counter} 6 17 | } elseif {$window_size == 9} { 18 | set ${pip_counter} 6 19 | } elseif {$window_size == 10} { 20 | set ${pip_counter} 6 21 | } elseif {$window_size == 11} { 22 | set ${pip_counter} 6 23 | } elseif {$window_size == 12} { 24 | set ${pip_counter} 7 25 | } elseif {$window_size == 13} { 26 | set ${pip_counter} 7 27 | } elseif {$window_size == 14} { 28 | set ${pip_counter} 8 29 | } elseif {$window_size == 15} { 30 | set ${pip_counter} 8 31 | } elseif {$window_size == 16} { 32 | set ${pip_counter} 8 33 | } 34 | } 35 | proc gen_USERPARAMETER_pipe_stage_VALUE {pipe_stage window_width } { 36 | set ${pipe_stage} [expr int(log(($window_width) * ($window_width))/log(2))] 37 | } 38 | -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/HDLSimDataGen/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "mode" : "Erosion", 5 | "template" : 6 | [ 7 | [1, 1, 0], 8 | [1, 1, 0], 9 | [0, 0, 0] 10 | ] 11 | }, 12 | { 13 | "mode" : "Erosion", 14 | "template" : 15 | [ 16 | [1, 1, 1], 17 | [1, 1, 1], 18 | [0, 0, 0] 19 | ] 20 | }, 21 | { 22 | "mode" : "Dilation", 23 | "template" : 24 | [ 25 | [1, 1, 0], 26 | [1, 1, 0], 27 | [0, 0, 0] 28 | ] 29 | }, 30 | { 31 | "mode" : "Dilation", 32 | "template" : 33 | [ 34 | [1, 1, 1], 35 | [1, 1, 1], 36 | [0, 0, 0] 37 | ] 38 | } 39 | ] 40 | } -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support binary images, "mode" in conf just supports "Erosion" and "Dilation", and size of "template" must equal to 3 or 5 !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-Dilation-110110000 : 1000000.000000 4 | 1-Dilation-111111000 : 1000000.000000 5 | 1-Erosion-110110000 : 1000000.000000 6 | 1-Erosion-111111000 : 1000000.000000 7 | 2-Dilation-110110000 : 1000000.000000 8 | 2-Dilation-111111000 : 1000000.000000 9 | 2-Erosion-110110000 : 1000000.000000 10 | 2-Erosion-111111000 : 1000000.000000 11 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 |
1-Dilation-1101100001-Dilation-1111110001-Erosion-1101100001-Erosion-1111110002-Dilation-1101100002-Dilation-1111110002-Erosion-1101100002-Erosion-111111000Total
1000000.001000000.001000000.001000000.001000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('1', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /LocalFilter/ErosionDilationBin/SoftwareSim/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/FunSimForHDL/MatchTemplateBin.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/MatchTemplateBin.srcs/sources_1/new/MatchTemplateBin.v {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/MatchTemplateBin/HDL/MatchTemplateBin.srcs/sources_1/new/MatchTemplateBin.v 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module MatchTemplateBin 4 | 5 | Top level modules: 6 | MatchTemplateBin 7 | 8 | } {} {}} ../HDL/MatchTemplateBin.srcs/sim_1/new/MatchTemplateBin_TB.sv {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/MatchTemplateBin/HDL/MatchTemplateBin.srcs/sim_1/new/MatchTemplateBin_TB.sv 9 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 10 | -- Compiling module CLOCK 11 | -- Compiling interface TBInterface 12 | -- Compiling module MatchTemplateBin_TB 13 | 14 | Top level modules: 15 | MatchTemplateBin_TB 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.MatchTemplateBin_TB 2 | run -all -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/HDLSimDataGen/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "template" : 5 | [ 6 | [0, 0, 0], 7 | [0, 1, 0], 8 | [0, 0, 0] 9 | ] 10 | }, 11 | { 12 | "template" : 13 | [ 14 | [1, 1, 1], 15 | [1, 1, 1], 16 | [1, 1, 1] 17 | ] 18 | } 19 | ] 20 | } -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support binary images, and size of "template" must equal to 3 or 5 !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-000010000 : 1000000.000000 4 | 1-111111111 : 1000000.000000 5 | 2-000010000 : 1000000.000000 6 | 2-111111111 : 1000000.000000 7 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
1-0000100001-1111111112-0000100002-111111111Total
1000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('1', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /LocalFilter/MatchTemplateBin/SoftwareSim/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/FunSimForHDL/MeanFilter.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/MeanFilter.srcs/sources_1/new/MeanFilter.v {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/MeanFilter/HDL/MeanFilter.srcs/sources_1/new/MeanFilter.v 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module MeanFilter 4 | 5 | Top level modules: 6 | MeanFilter 7 | 8 | } {} {}} ../HDL/MeanFilter.srcs/sim_1/new/MeanFilter_TB.sv {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/MeanFilter/HDL/MeanFilter.srcs/sim_1/new/MeanFilter_TB.sv 9 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 10 | -- Compiling module CLOCK 11 | -- Compiling interface TBInterface 12 | -- Compiling module MeanFilter_TB 13 | 14 | Top level modules: 15 | MeanFilter_TB 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.MeanFilter_TB 2 | run -all -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/HDL/MeanFilter.srcs/gui/MeanFilter_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_sum_stage_VALUE {sum_stage window_width } { 3 | set ${sum_stage} [expr int(log(($window_width) * ($window_width))/log(2))] 4 | } 5 | -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/HDLSimDataGen/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | {"window_width" : 3}, 4 | {"window_width" : 5} 5 | ] 6 | } -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support gray-scale images and conf['window_width'] only can be 3 and 5!** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-3 : 1000000.000000 4 | 1-5 : 1000000.000000 5 | 2-3 : 1000000.000000 6 | 2-5 : 1000000.000000 7 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 |
1-31-52-32-5Total
1000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /LocalFilter/MeanFilter/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /LocalFilter/MeanFilter/SoftwareSim/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/RankFilter/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /LocalFilter/RankFilter/FunSimForHDL/RankFifter.cr.mti: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /LocalFilter/RankFilter/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.RankFilter_TB 2 | run -all -------------------------------------------------------------------------------- /LocalFilter/RankFilter/HDL/RankFilter.srcs/gui/RankFifter_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_sum_stage_VALUE {sum_stage window_width } { 3 | set ${sum_stage} [expr int(log(($window_width) * ($window_width))/log(8)) + 1] 4 | } 5 | proc gen_USERPARAMETER_full_win_bits_VALUE {window_width full_win_bits } { 6 | if {[expr log($window_width * $window_width)/log(2)] > [expr int(log($window_width * $window_width)/log(2))] } { 7 | set ${full_win_bits} [expr int(log($window_width) * $window_width/log(2)) + 1] 8 | } else { 9 | set ${full_win_bits} [expr int(log($window_width * $window_width)/log(2))] 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /LocalFilter/RankFilter/HDL/RankFilter.srcs/sources_1/new/generate.py: -------------------------------------------------------------------------------- 1 | fo = open('Encoder.dat', 'w') 2 | 3 | fo.write('module Encoder(index, value);\n') 4 | fo.write('\tparameter window_width = 3;\n') 5 | fo.write('\tparameter full_win_bits = 4;\n') 6 | fo.write('\tinput[window_width * window_width - 1 : 0] index;\n') 7 | fo.write('\toutput[full_win_bits - 1 : 0] value;\n') 8 | fo.write('\treg[full_win_bits - 1 : 0] reg_value;\n') 9 | fo.write('\tassign value = reg_value;\n') 10 | fo.write('\tgenerate\n') 11 | fo.write('\t\tcase(window_width)\n') 12 | for i in xrange(2, 16): 13 | fo.write('\t\t\t%d : \n' % (i)) 14 | fo.write('\t\t\t\talways@(*) begin\n') 15 | fo.write('\t\t\t\t\tcase(index)\n') 16 | v = 1 17 | for j in xrange(i * i): 18 | fo.write('\t\t\t\t\t\t%d : reg_value <= %d;\n' % (v, j)) 19 | v = 1 << (j + 1) 20 | fo.write('\t\t\t\t\t\tdefault: reg_value <= 0;\n') 21 | fo.write('\t\t\t\t\tendcase\n') 22 | fo.write('\t\t\t\tend\n') 23 | fo.write('\t\t\tdefault : ;\n') 24 | fo.write('\t\tendcase\n') 25 | fo.write('\tendgenerate\n') 26 | fo.write('endmodule\t') -------------------------------------------------------------------------------- /LocalFilter/RankFilter/HDLSimDataGen/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/RankFilter/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "window_width" : 3, 5 | "rank" : 4 6 | }, 7 | { 8 | "window_width" : 3, 9 | "rank" : 8 10 | }, 11 | { 12 | "window_width" : 5, 13 | "rank" : 12 14 | }, 15 | { 16 | "window_width" : 5, 17 | "rank" : 24 18 | } 19 | ] 20 | } -------------------------------------------------------------------------------- /LocalFilter/RankFilter/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support gray-scale images and conf['window_width'] only can be 3 and 5!** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /LocalFilter/RankFilter/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-3-4 : 1000000.000000 4 | 1-3-8 : 1000000.000000 5 | 1-5-12 : 1000000.000000 6 | 1-5-24 : 1000000.000000 7 | 2-3-4 : 1000000.000000 8 | 2-3-8 : 1000000.000000 9 | 2-5-12 : 1000000.000000 10 | 2-5-24 : 1000000.000000 11 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /LocalFilter/RankFilter/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 |
1-3-41-3-81-5-121-5-242-3-42-3-82-5-122-5-24Total
1000000.001000000.001000000.001000000.001000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /LocalFilter/RankFilter/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /LocalFilter/RankFilter/SoftwareSim/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.ThresholdLocal_TB 2 | run -all -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/FunSimForHDL/ThresholdLocal.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/ThresholdLocal.srcs/sim_1/new/ThresholdLocal_TB.sv {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Master/LocalFilter/ThresholdLocal/HDL/ThresholdLocal.srcs/sim_1/new/ThresholdLocal_TB.sv 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module CLOCK 4 | -- Compiling interface TBInterface 5 | -- Compiling module ThresholdLocal_TB 6 | 7 | Top level modules: 8 | ThresholdLocal_TB 9 | 10 | } {} {}} 11 | -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/HDL/ThresholdLocal.srcs/gui/ThresholdLocal_v1_0.gtcl: -------------------------------------------------------------------------------- 1 | # This file is automatically written. Do not modify. 2 | proc gen_USERPARAMETER_max_delay_bits_VALUE {max_delay max_delay_bits } { 3 | if {[expr log($max_delay)/log(2)] > [expr int(log($max_delay)/log(2))] } { 4 | set ${max_delay_bits} [expr int(log($max_delay)/log(2)) + 1] 5 | } else { 6 | set ${max_delay_bits} [expr int(log($max_delay)/log(2))] 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/HDLSimDataGen/RankFilter.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | RankFilter 7 | 8 | Function 9 | Local filter - Rank filter, it always used for denoising with preserving edge. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-21 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Dai Tianyu (dtysky)' 50 | 51 | def rank_filter(window, rank): 52 | win = [] 53 | for row in window: 54 | win += row 55 | return sorted(win)[rank] -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/HDLSimDataGen/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "window_width" : 3, 5 | "filter" : "mean" 6 | }, 7 | { 8 | "window_width" : 3, 9 | "filter" : "mid" 10 | }, 11 | { 12 | "window_width" : 5, 13 | "filter" : "mean" 14 | }, 15 | { 16 | "window_width" : 5, 17 | "filter" : "mid" 18 | } 19 | ] 20 | } -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support gray-scale images and conf['filter'] only can be 'mean' and 'mid!** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/SimResCheck/compare_report.txt: -------------------------------------------------------------------------------- 1 | PSNR: 2 | 3 | 1-3-mean : 1000000.000000 4 | 1-3-mid : 1000000.000000 5 | 1-5-mean : 1000000.000000 6 | 1-5-mid : 1000000.000000 7 | 2-3-mean : 1000000.000000 8 | 2-3-mid : 1000000.000000 9 | 2-5-mean : 1000000.000000 10 | 2-5-mid : 1000000.000000 11 | Totle : 1000000.000000 -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/SimResCheck/compare_report_table.txt: -------------------------------------------------------------------------------- 1 | #### PSNR: 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 |
1-3-mean1-3-mid1-5-mean1-5-mid2-3-mean2-3-mid2-5-mean2-5-midTotal
1000000.001000000.001000000.001000000.001000000.001000000.001000000.001000000.001000000.00
-------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('1', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/SoftwareSim/RankFilter.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | RankFilter 7 | 8 | Function 9 | Local filter - Rank filter, it always used for denoising with preserving edge. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-21 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Dai Tianyu (dtysky)' 50 | 51 | def rank_filter(window, rank): 52 | win = [] 53 | for row in window: 54 | win += row 55 | return sorted(win)[rank] -------------------------------------------------------------------------------- /LocalFilter/ThresholdLocal/SoftwareSim/WindowGenerator.py: -------------------------------------------------------------------------------- 1 | """ 2 | Project 3 | FPGA-Imaging-Library 4 | 5 | Design 6 | WindowGenerator 7 | 8 | Function 9 | Generate window. 10 | 11 | Module 12 | Software simulation. 13 | 14 | Version 15 | 1.0 16 | 17 | Modified 18 | 2015-05-17 19 | 20 | Copyright (C) 2015 Tianyu Dai (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://fil.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | """ 48 | 49 | __author__ = 'Tianyu Dai (dtysky)' 50 | 51 | from PIL import Image 52 | 53 | class WindowGenerator(): 54 | """A class for creating and maintaining a window.""" 55 | def __init__(self, wsize): 56 | self.init = 0 57 | self.create(wsize) 58 | def create(self, wsize): 59 | self.enable = False 60 | self.window = [] 61 | self.wsize = wsize 62 | self.wsize_half = wsize >> 1 63 | for y in xrange(wsize): 64 | self.window.append([0 for x in xrange(wsize)]) 65 | def update(self, rows_col): 66 | if self.enable: 67 | pass 68 | elif self.init == self.wsize_half: 69 | self.enable = True 70 | else: 71 | self.init += 1 72 | window_last = list(self.window) 73 | for y in xrange(self.wsize): 74 | self.window[y].pop() 75 | self.window[y].insert(0, rows_col[y]) 76 | return window_last 77 | def is_enable(self): 78 | return self.enable -------------------------------------------------------------------------------- /Point/ColorReversal/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc 9 | HDL/LuminanceTransform.srcs/sources_1/ip/AddSub13Sx13S 10 | !HDL/LuminanceTransform.srcs/sources_1/ip/AddSub13Sx13S/AddSub13Sx13S.xci 11 | !HDL/LuminanceTransform.srcs/sources_1/ip/AddSub13Sx13S/AddSub13Sx13S_funcsim.v -------------------------------------------------------------------------------- /Point/ColorReversal/FunSimForHDL/ColorReversa.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/ColorReversal.srcs/sources_1/new/ColorReversal.v {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Point/ColorReversal/HDL/ColorReversal.srcs/sources_1/new/ColorReversal.v 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module ColorReversal 4 | 5 | Top level modules: 6 | ColorReversal 7 | 8 | } {} {}} ../HDL/ColorReversal.srcs/sim_1/new/ColorReversal_TB.sv {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Point/ColorReversal/HDL/ColorReversal.srcs/sim_1/new/ColorReversal_TB.sv 9 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 10 | -- Compiling module CLOCK 11 | -- Compiling interface TBInterface 12 | -- Compiling module ColorReversal_TB 13 | 14 | Top level modules: 15 | ColorReversal_TB 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /Point/ColorReversal/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.ColorReversal_TB 2 | run -all -------------------------------------------------------------------------------- /Point/ColorReversal/HDLSimDataGen/create.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image 4 | import os, json 5 | from ctypes import * 6 | user32 = windll.LoadLibrary('user32.dll') 7 | MessageBox = lambda x:user32.MessageBoxA(0, x, 'Error', 0) 8 | 9 | FileFormat = ['.jpg', '.bmp'] 10 | Conf = json.load(open('../ImageForTest/conf.json', 'r'))['conf'] 11 | 12 | def show_error(e): 13 | MessageBox(e) 14 | exit(0) 15 | 16 | def name_format(root, name, ex, conf): 17 | return '%s' % name 18 | 19 | def conf_format(im, conf): 20 | return '%s\n' % im.mode 21 | 22 | def color_format(mode, color): 23 | if mode == '1': 24 | return '0' if color == 0 else '1' 25 | if mode != 'RGB': 26 | color = [color] 27 | res = '' 28 | for c in color: 29 | tmp = bin(c)[2:] 30 | for i in xrange(10 - len(bin(c))): 31 | tmp = '0' + tmp 32 | res += tmp 33 | return res 34 | 35 | def create_dat(im, conf): 36 | mode = im.mode 37 | if mode not in ['RGB', 'L', '1']: 38 | show_error('This module just supports RGB, Gray-scale and binary images, check your images !') 39 | data_src = im.getdata() 40 | xsize, ysize = im.size 41 | data_res = '' 42 | for color in data_src: 43 | data_res += color_format(mode, color) + '\n' 44 | return data_res[:-1] 45 | 46 | FileAll = [] 47 | for root,dirs,files in os.walk('../ImageForTest'): 48 | for f in files: 49 | name, ex=os.path.splitext(f) 50 | if ex in FileFormat: 51 | FileAll.append((root+'/', name, ex)) 52 | dat_index = '' 53 | for root, name, ex in FileAll: 54 | im_src = Image.open(root + name + ex) 55 | xsize, ysize = im_src.size 56 | for c in Conf: 57 | dat_res = open('../FunSimForHDL/%s.dat' \ 58 | % name_format(root, name, ex, c), 'w') 59 | dat_res.write('%d\n%d\n' % (xsize, ysize)) 60 | dat_res.write('%s' % conf_format(im_src, c)) 61 | dat_res.write(create_dat(im_src, c)) 62 | dat_index += '%s' % name_format(root, name, ex, c) 63 | dat_index += '\n' 64 | dat_res.close() 65 | dat_index = dat_index[:-1] 66 | dat_index_f = open('../FunSimForHDL/imgindex.dat','w') 67 | dat_index_f.write(dat_index) 68 | dat_index_f.close() -------------------------------------------------------------------------------- /Point/ColorReversal/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | "default" 4 | ] 5 | } -------------------------------------------------------------------------------- /Point/ColorReversal/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB, Gray-scale and binary images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.7 and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configurations for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Point/ColorReversal/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | mode = data[2].strip() 13 | data_res = [] 14 | for p in data[3:]: 15 | if mode == 'RGB': 16 | p = p.split(' ') 17 | data_res.append((int(p[0]), int(p[1]), int(p[2]))) 18 | else: 19 | data_res.append(int(p)) 20 | xsize, ysize = int(data[0]), int(data[1]) 21 | im_res = Image.new(mode, (xsize, ysize)) 22 | im_res.putdata(data_res) 23 | return im_res 24 | 25 | FileAll = [] 26 | for root, dirs, files in os.walk('../FunSimForHDL'): 27 | for f in files: 28 | name, ex=os.path.splitext(f) 29 | if ex in FileFormat: 30 | FileAll.append((root+'/', name, ex)) 31 | for root, name, ex in FileAll: 32 | dat_src = open(root + name + ex) 33 | data_src = dat_src.readlines() 34 | convert(data_src).save(name_format(root, name, ex)) 35 | dat_src.close() -------------------------------------------------------------------------------- /Point/ContrastTransform/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc 9 | HDL/ContrastTransform.srcs/sources_1/ip/Multiplier12x24CT/* 10 | !HDL/ContrastTransform.srcs/sources_1/ip/Multiplier12x24CT/Multiplier12x24CT.xci 11 | !HDL/ContrastTransform.srcs/sources_1/ip/Multiplier12x24CT/Multiplier12x24CT_funcsim.v -------------------------------------------------------------------------------- /Point/ContrastTransform/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -work.glbl -L unisims_ver work.ContrastTransform_TB 2 | run -all -------------------------------------------------------------------------------- /Point/ContrastTransform/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | {"ct_scale" : 0.2}, 4 | {"ct_scale" : 3.3} 5 | ] 6 | } -------------------------------------------------------------------------------- /Point/ContrastTransform/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB and gray-scale images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Point/ContrastTransform/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | mode = data[2].strip() 13 | data_res = [] 14 | for p in data[3:]: 15 | if mode == 'RGB': 16 | p = p.split(' ') 17 | data_res.append((int(p[0]), int(p[1]), int(p[2]))) 18 | else: 19 | data_res.append(int(p)) 20 | xsize, ysize = int(data[0]), int(data[1]) 21 | im_res = Image.new(mode, (xsize, ysize)) 22 | im_res.putdata(data_res) 23 | return im_res 24 | 25 | FileAll = [] 26 | for root, dirs, files in os.walk('../FunSimForHDL'): 27 | for f in files: 28 | name, ex=os.path.splitext(f) 29 | if ex in FileFormat: 30 | FileAll.append((root+'/', name, ex)) 31 | for root, name, ex in FileAll: 32 | dat_src = open(root + name + ex) 33 | data_src = dat_src.readlines() 34 | convert(data_src).save(name_format(root, name, ex)) 35 | dat_src.close() -------------------------------------------------------------------------------- /Point/Graying/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc 9 | HDL/Graying.srcs/sources_1/ip/MultiplierRedx0d299/* 10 | !HDL/Graying.srcs/sources_1/ip/MultiplierRedx0d299/MultiplierRedx0d299.xci 11 | !HDL/Graying.srcs/sources_1/ip/MultiplierRedx0d299/MultiplierRedx0d299_funcsim.v 12 | HDL/Graying.srcs/sources_1/ip/MultiplierGreenx0d587/* 13 | !HDL/Graying.srcs/sources_1/ip/MultiplierGreenx0d587/MultiplierGreenx0d587.xci 14 | !HDL/Graying.srcs/sources_1/ip/MultiplierGreenx0d587/MultiplierGreenx0d587_funcsim.v 15 | HDL/Graying.srcs/sources_1/ip/MultiplierBluex0d114/* 16 | !HDL/Graying.srcs/sources_1/ip/MultiplierBluex0d114/MultiplierBluex0d114.xci 17 | !HDL/Graying.srcs/sources_1/ip/MultiplierBluex0d114/MultiplierBluex0d114_funcsim.v -------------------------------------------------------------------------------- /Point/Graying/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim work.glbl -L unisims_ver work.Graying_TB 2 | run -all -------------------------------------------------------------------------------- /Point/Graying/HDLSimDataGen/create.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image 4 | import os, json 5 | from ctypes import * 6 | user32 = windll.LoadLibrary('user32.dll') 7 | MessageBox = lambda x:user32.MessageBoxA(0, x, 'Error', 0) 8 | 9 | FileFormat = ['.jpg', '.bmp'] 10 | Conf = json.load(open('../ImageForTest/conf.json', 'r'))['conf'] 11 | 12 | def show_error(e): 13 | MessageBox(e) 14 | exit(0) 15 | 16 | 17 | def name_format(root, name, ex, conf): 18 | return name 19 | 20 | def conf_format(im, conf): 21 | return '' 22 | 23 | def color_format(mode, color): 24 | if mode not in ['RGB']: 25 | show_error('This module just supports RGB images, check your images !') 26 | res = '' 27 | for c in color: 28 | tmp = bin(c)[2:] 29 | for i in xrange(10 - len(bin(c))): 30 | tmp = '0' + tmp 31 | res += tmp 32 | return res 33 | 34 | def create_dat(im, conf): 35 | data_src = im.getdata() 36 | xsize, ysize = im.size 37 | data_res = '' 38 | for color in data_src: 39 | data_res += color_format(im.mode, color) + '\n' 40 | return data_res[:-1] 41 | 42 | FileAll = [] 43 | for root,dirs,files in os.walk('../ImageForTest'): 44 | for f in files: 45 | name, ex=os.path.splitext(f) 46 | if ex in FileFormat: 47 | FileAll.append((root+'/', name, ex)) 48 | dat_index = '' 49 | for root, name, ex in FileAll: 50 | im_src = Image.open(root + name + ex) 51 | xsize, ysize = im_src.size 52 | for c in Conf: 53 | dat_res = open('../FunSimForHDL/%s.dat' \ 54 | % name_format(root, name, ex, c), 'w') 55 | dat_res.write('%d\n%d\n' % (xsize, ysize)) 56 | dat_res.write('%s' % conf_format(im_src, c)) 57 | dat_res.write(create_dat(im_src, c)) 58 | dat_index += '%s' % name_format(root, name, ex, c) 59 | dat_index += '\n' 60 | dat_res.close() 61 | dat_index = dat_index[:-1] 62 | dat_index_f = open('../FunSimForHDL/imgindex.dat','w') 63 | dat_index_f.write(dat_index) 64 | dat_index_f.close() -------------------------------------------------------------------------------- /Point/Graying/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | "default" 4 | ] 5 | } -------------------------------------------------------------------------------- /Point/Graying/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Point/Graying/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Point/Graying/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('L', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /Point/LightnessTransform/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc 9 | HDL/LuminanceTransform.srcs/sources_1/ip/AddSub13Sx13S 10 | !HDL/LuminanceTransform.srcs/sources_1/ip/AddSub13Sx13S/AddSub13Sx13S.xci 11 | !HDL/LuminanceTransform.srcs/sources_1/ip/AddSub13Sx13S/AddSub13Sx13S_funcsim.v -------------------------------------------------------------------------------- /Point/LightnessTransform/FunSimForHDL/LightnessTransform.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/LightnessTransform.srcs/sim_1/new/LightnessTransform_TB.sv {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Point/LightnessTransform/HDL/LightnessTransform.srcs/sim_1/new/LightnessTransform_TB.sv 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module CLOCK 4 | -- Compiling interface TBInterface 5 | -- Compiling module LightnessTransform_TB 6 | 7 | Top level modules: 8 | LightnessTransform_TB 9 | 10 | } {} {}} ../HDL/LightnessTransform.srcs/sim_1/import/True2Comp.v {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Point/LightnessTransform/HDL/LightnessTransform.srcs/sim_1/import/True2Comp.v 11 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 12 | -- Compiling module True2Comp 13 | 14 | Top level modules: 15 | True2Comp 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /Point/LightnessTransform/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -work.glbl -L unisims_ver work.LuminanceTransform_TB 2 | run -all -------------------------------------------------------------------------------- /Point/LightnessTransform/HDL/LightnessTransform.srcs/sim_1/import/True2Comp.v: -------------------------------------------------------------------------------- 1 | /* 2 | :Project 3 | FPGA-Imaging-Library 4 | 5 | :Design 6 | True2Comp 7 | 8 | :Function 9 | Convert true code to complemental code. 10 | 11 | :Module 12 | Main module 13 | 14 | :Version 15 | 1.0 16 | 17 | :Modified 18 | 2015-05-01 19 | 20 | Copyright (C) 2015 Dai Tianyu (dtysky) 21 | 22 | This library is free software; you can redistribute it and/or 23 | modify it under the terms of the GNU Lesser General Public 24 | License as published by the Free Software Foundation; either 25 | version 2.1 of the License, or (at your option) any later version. 26 | 27 | This library is distributed in the hope that it will be useful, 28 | but WITHOUT ANY WARRANTY; without even the implied warranty of 29 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 | Lesser General Public License for more details. 31 | 32 | You should have received a copy of the GNU Lesser General Public 33 | License along with this library; if not, write to the Free Software 34 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 35 | 36 | Homepage for this project: 37 | http://ifl.dtysky.moe 38 | 39 | Sources for this project: 40 | https://github.com/dtysky/FPGA-Imaging-Library 41 | 42 | My e-mail: 43 | dtysky@outlook.com 44 | 45 | My blog: 46 | http://dtysky.moe 47 | 48 | */ 49 | 50 | `timescale 1ns / 1ps 51 | 52 | 53 | module True2Comp( 54 | true, 55 | complement); 56 | 57 | parameter data_channel = 1; 58 | parameter data_width = 17; 59 | 60 | input[data_channel * data_width - 1 : 0] true; 61 | output[data_channel * data_width - 1 : 0] complement; 62 | 63 | genvar i; 64 | generate 65 | `define h (i + 1) * data_width - 1 66 | `define l i * data_width 67 | for (i = 0; i < data_channel; i = i + 1) begin 68 | assign complement[`h : `l] = true[`h] == 0 ? 69 | true[`h : `l] : {1'b1, ~true[`h - 1 : `l] + 1}; 70 | end 71 | `undef h 72 | `undef l 73 | endgenerate 74 | endmodule -------------------------------------------------------------------------------- /Point/LightnessTransform/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | {"lm_gain" : -90}, 4 | {"lm_gain" : 100} 5 | ] 6 | } -------------------------------------------------------------------------------- /Point/LightnessTransform/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support RGB and Gray-scale images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.7 and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configurations for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Point/LightnessTransform/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | mode = data[2].strip() 13 | data_res = [] 14 | for p in data[3:]: 15 | if mode == 'RGB': 16 | p = p.split(' ') 17 | data_res.append((int(p[0]), int(p[1]), int(p[2]))) 18 | else: 19 | data_res.append(int(p)) 20 | xsize, ysize = int(data[0]), int(data[1]) 21 | im_res = Image.new(mode, (xsize, ysize)) 22 | im_res.putdata(data_res) 23 | return im_res 24 | 25 | FileAll = [] 26 | for root, dirs, files in os.walk('../FunSimForHDL'): 27 | for f in files: 28 | name, ex=os.path.splitext(f) 29 | if ex in FileFormat: 30 | FileAll.append((root+'/', name, ex)) 31 | for root, name, ex in FileAll: 32 | dat_src = open(root + name + ex) 33 | data_src = dat_src.readlines() 34 | convert(data_src).save(name_format(root, name, ex)) 35 | dat_src.close() -------------------------------------------------------------------------------- /Point/Threshold/.gitignore: -------------------------------------------------------------------------------- 1 | HDL/* 2 | !HDL/*.srcs/ 3 | !HDL/*.xpr 4 | FunSimForHDL/* 5 | !FunSimForHDL/*.mpf 6 | !FunSimForHDL/*.mti 7 | !FunSimForHDL/*.do 8 | *.pyc -------------------------------------------------------------------------------- /Point/Threshold/FunSimForHDL/RunOver.do: -------------------------------------------------------------------------------- 1 | vsim -L unisims_ver work.Threshold_TB 2 | run -all -------------------------------------------------------------------------------- /Point/Threshold/FunSimForHDL/Threshold.cr.mti: -------------------------------------------------------------------------------- 1 | ../HDL/Threshold.srcs/sources_1/new/Threshold.v {1 {vlog -work work -vopt B:/Complex_Mind/FPGA-Imaging-Library/Point/Threshold/HDL/Threshold.srcs/sources_1/new/Threshold.v 2 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 3 | -- Compiling module Threshold 4 | 5 | Top level modules: 6 | Threshold 7 | 8 | } {} {}} ../HDL/Threshold.srcs/sim_1/new/Threshold_TB.sv {1 {vlog -work work -vopt -sv B:/Complex_Mind/FPGA-Imaging-Library/Point/Threshold/HDL/Threshold.srcs/sim_1/new/Threshold_TB.sv 9 | Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012 10 | -- Compiling module CLOCK 11 | -- Compiling interface TBInterface 12 | -- Compiling module Threshold_TB 13 | 14 | Top level modules: 15 | Threshold_TB 16 | 17 | } {} {}} 18 | -------------------------------------------------------------------------------- /Point/Threshold/ImageForTest/conf.json: -------------------------------------------------------------------------------- 1 | { 2 | "conf" : [ 3 | { 4 | "mode": "Base", 5 | "th1": "128", 6 | "th2": "0" 7 | }, 8 | { 9 | "mode": "Contour", 10 | "th1": "50", 11 | "th2": "200" 12 | } 13 | ] 14 | } -------------------------------------------------------------------------------- /Point/Threshold/README.md: -------------------------------------------------------------------------------- 1 | # Wiki and Contact 2 | [Homepage for this project](http://ifl.dtysky.moe) 3 | [Sources for this project](https://github.com/dtysky/FPGA-Imaging-Library) 4 | [My e-mail](Mailto:dtysky@outlook.com) 5 | [My blog](http://dtysky.moe) 6 | 7 | # Simulations 8 | **Simulations for this module just support Gray-scale images !** 9 | 10 | ## Steps for simulations 11 | **Warning: procedures for simulation depend on python 2.x and PIL(Python Imaging Library), please get them by your self.** 12 | 13 | ### Preparing 14 | Open "ImageForTest". 15 | Put images which you want to use for simulations. 16 | Edit the "conf.json" for setting the configuration for simulations. 17 | 18 | ### Software simulation 19 | Open "SoftwareSim". 20 | Run "sim.py". 21 | Open "SimResCheck", check your results. 22 | 23 | ### Creat preparing data for functional simulation 24 | Open "HDLSimDataGen". 25 | Run "creat.py". 26 | 27 | ### Functional simulation 28 | Functional simulation just support for modelsim 10.1 up. 29 | Above all, you must compile all xilinx vivado library to modelsim. 30 | 31 | Open "FunSimForHDL". 32 | Open "ContrastTranslate.mpf" with modelsim. 33 | 34 | #### Do these: 35 | 36 | Run this commond at first time: 37 | 38 | vlib work 39 | 40 | Then, compile all your source file: 41 | 42 | modelsim gui -> Compile -> Compile all 43 | 44 | Then, run this: 45 | 46 | do Run.do 47 | 48 | If you just want to the finally result, and don't want to watch the waveform, run this: 49 | 50 | do RunOver.do 51 | 52 | ## Comparing 53 | Open "SimResCheck". 54 | Run "covert.py", then you can get the results form functional simulation. 55 | Run "compare.py" for creating a report for software simulation and functional simulation. 56 | 57 | -------------------------------------------------------------------------------- /Point/Threshold/SimResCheck/compare.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Tianyu Dai (dtysky)' 2 | 3 | from PIL import Image, ImageChops, ImageStat 4 | import os, json, re, math 5 | 6 | FileFormat = ['.jpg', '.bmp'] 7 | 8 | def name_format(root, name, ex, conf): 9 | return '%s-%s' % (name, conf['lm_gain']) 10 | 11 | def get_psnr(FileAll): 12 | psnrs = {} 13 | for name, f_pair in FileAll.items(): 14 | diffs = ImageChops.difference(\ 15 | Image.open(f_pair[0]), Image.open(f_pair[1])) 16 | stat = ImageStat.Stat(diffs) 17 | rms = sum(stat.rms) / len(stat.rms) 18 | psnr = 20.0 * math.log10(255.0 / rms) if rms != 0 else 1000*1000 19 | psnrs[name] = psnr 20 | return psnrs 21 | 22 | def compare(FileAll): 23 | psnrs = get_psnr(FileAll) 24 | psnr_t = 0 25 | res = 'PSNR:\n\n' 26 | for name in sorted(psnrs): 27 | psnr_t += psnrs[name] 28 | res += '%s : %f \n' % (name, psnrs[name]) 29 | res += 'Totle : %f ' % (psnr_t / len(psnrs)) 30 | return res 31 | 32 | def compare_table(FileAll): 33 | psnrs = get_psnr(FileAll) 34 | psnr_t = 0 35 | res = '''#### PSNR:\n\n\n''' 36 | res += '\t\n' 37 | for name in sorted(psnrs): 38 | psnr_t += psnrs[name] 39 | res += '\t\t\n' % name 40 | res += '\t\t\n' % 'Total' 41 | res += '\t\n' 42 | res += '\t\n' 43 | for name in sorted(psnrs): 44 | res += '\t\t\n' % psnrs[name] 45 | res += '\t\t\n' % (psnr_t / len(psnrs)) 46 | res += '\t\n' 47 | res += "
%s%s
%.2f%.2f
" 48 | return res 49 | 50 | FileAll = {} 51 | for root, dirs, files in os.walk('./'): 52 | for f in files: 53 | name, ex=os.path.splitext(f) 54 | if ex in FileFormat: 55 | tmp_h = re.match(r'(.*)-reqack-hdlfun', name) 56 | tmp_s = re.match(r'(.*)-soft', name) 57 | img = None 58 | if not tmp_h and not tmp_s: 59 | continue 60 | if tmp_h: 61 | img = tmp_h.group(1) 62 | if tmp_s: 63 | img = tmp_s.group(1) 64 | if img not in FileAll: 65 | FileAll[img] = [] 66 | FileAll[img].append(root + name + ex) 67 | fo = open('compare_report.txt', 'w') 68 | fo.write(compare(FileAll)) 69 | fo.close() 70 | fo = open('compare_report_table.txt', 'w') 71 | fo.write(compare_table(FileAll)) 72 | fo.close() -------------------------------------------------------------------------------- /Point/Threshold/SimResCheck/convert.py: -------------------------------------------------------------------------------- 1 | __author__ = 'Dai Tianyu (dtysky)' 2 | 3 | from PIL import Image 4 | import os 5 | 6 | FileFormat = ['.res'] 7 | 8 | def name_format(root, name, ex): 9 | return '%s-hdlfun.bmp' % name 10 | 11 | def convert(data): 12 | data_res = [] 13 | for p in data[2:]: 14 | data_res.append(int(p)) 15 | xsize, ysize = int(data[0]), int(data[1]) 16 | im_res = Image.new('1', (xsize, ysize)) 17 | im_res.putdata(data_res) 18 | return im_res 19 | 20 | FileAll = [] 21 | for root, dirs, files in os.walk('../FunSimForHDL'): 22 | for f in files: 23 | name, ex=os.path.splitext(f) 24 | if ex in FileFormat: 25 | FileAll.append((root+'/', name, ex)) 26 | for root, name, ex in FileAll: 27 | dat_src = open(root + name + ex) 28 | data_src = dat_src.readlines() 29 | convert(data_src).save(name_format(root, name, ex)) 30 | dat_src.close() -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FPGA-Imaging-Library. 2 | **An open source library for image processing on FPGA**. 3 | **一个开源的FPGA图像处理库。** 4 | 5 | *** 6 | 7 | ## Progress 8 | Version 1.0 published: 9 | 1.0版本已发布： 10 | [http://fil.dtysky.moe/](http://fil.dtysky.moe) 11 |
12 | 系列教程： 13 | [FPGA的图像处理](http://dtysky.moe/tag/fpga-imaging-library.html) 14 | 15 | *** 16 | 17 | ## What is FPGA-Imaging-Library? 18 | F-I-L is a open source library for image processing on FPGA, it already contents many useful operations, and is updating. All the operations are packaged to IPCores, and of course they follow a same and standardized interface, moreover, each of them can work on piplines-mode and req-ack mode. 19 | F-I-L是一个FPGA平台的开源的图像处理库，已经拥有了许多常用操作，并在不断更新中。这些操作被以IP核的形式进行了封装，遵循同一种规范化的接口，同时具有流水线和请求响应两种使用模式。 20 | 21 | *** 22 | 23 | ## How to use? 24 | Certainly, all IPCores have their software simulations, functional simulations and testing on board, the same folder structure and interface can make user do simulations and testing conveniently. 25 | IPCores just support xilinx vivado now. 26 | 大部分IP都拥有自己的软件仿真、功能仿真和板上测试，并且具有相同的文件结构和接口，能够让使用者很方便得进行测试和仿真。 27 | 目前IP形式只支持Xilinx的Vivado套件，不排除未来会向Quartus搬移的可能。 28 | 29 | *** 30 | 31 | ## Author 32 | **Tianyu Dai (dtysky)** 33 | **戴天宇 (dtysky)** 34 | [http://dtysky.moe](http://dtysky.moe) 35 | [dtysky@outlook.com](dtysky@outlook.com) 36 | [http://proj.dtysky.moe/](http://proj.dtysky.moe/) 37 | 38 | *** 39 | 40 | ## Copyright 41 | **Copyright © 2015, 戴天宇, Tianyu Dai (dtysky). All Rights Reserved. 42 | This project is free software and released under the** [GNU Lesser General Public License (LGPL)](https://www.gnu.org/licenses/lgpl-2.1.html). -------------------------------------------------------------------------------- /TestOnBoard/Geometry/.gitignore: -------------------------------------------------------------------------------- 1 | *.cache/ 2 | *.ioplanning/ 3 | *.runs/ 4 | *.hw/ 5 | Geometry.srcs/sources_1/ipshared/ 6 | Geometry.srcs/sources_1/bd/design_1/ip/ 7 | Geometry.sdk/* 8 | !Geometry.sdk/Geometry/ 9 | .Xil/ -------------------------------------------------------------------------------- /TestOnBoard/Geometry/ForBuild/Main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dtysky/FPGA-Imaging-Library/c8cd350dc07397be1979b51f5f99e5a7fddf98f6/TestOnBoard/Geometry/ForBuild/Main.c -------------------------------------------------------------------------------- /TestOnBoard/LocalFilter/.gitignore: -------------------------------------------------------------------------------- 1 | *.cache/ 2 | *.ioplanning/ 3 | *.runs/ 4 | *.hw/ 5 | Geometry.srcs/sources_1/ipshared/ 6 | Geometry.srcs/sources_1/bd/design_1/ip/ 7 | Geometry.sdk/* 8 | !Geometry.sdk/Geometry/ 9 | .Xil/ -------------------------------------------------------------------------------- /TestOnBoard/LocalFilter/ForBuild/Main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dtysky/FPGA-Imaging-Library/c8cd350dc07397be1979b51f5f99e5a7fddf98f6/TestOnBoard/LocalFilter/ForBuild/Main.c -------------------------------------------------------------------------------- /TestOnBoard/Point/.gitignore: -------------------------------------------------------------------------------- 1 | *.cache/ 2 | *.ioplanning/ 3 | *.runs/ 4 | *.hw/ 5 | Geometry.srcs/sources_1/ipshared/ 6 | Geometry.srcs/sources_1/bd/design_1/ip/ 7 | Geometry.sdk/* 8 | !Geometry.sdk/Geometry/ 9 | .Xil/ -------------------------------------------------------------------------------- /TestOnBoard/Point/ForBuild/Main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dtysky/FPGA-Imaging-Library/c8cd350dc07397be1979b51f5f99e5a7fddf98f6/TestOnBoard/Point/ForBuild/Main.c -------------------------------------------------------------------------------- /TestOnBoard/README.md: -------------------------------------------------------------------------------- 1 | All projects here are used for testing on board for each category, please "*.xpr" with Vivado, then: 2 | 3 | 0. Open vivado 4 | 1. Cd to your proj_path in tcl console 5 | example: cd B:/Complex_Mind/FPGA-Imaging-Library/PLv1.0/TestOnBoard/Geometry 6 | 2. Tcl Console: source bulid.tcl 7 | 3. Export Hardware 8 | 4. Lanch SDK 9 | 5. Create new application project 10 | 6. copy codes in ForBuild/Main.c to your Main.c 11 | 7. Change setting and run --------------------------------------------------------------------------------