├── Image ├── 1.png ├── 2.png ├── 3.png ├── 4.png ├── 5.jpg ├── 6.jpg └── 7.jpg ├── XUP └── Image │ ├── 2.png │ ├── 3.png │ ├── 5.jpg │ ├── 6.jpg │ └── 7.jpg ├── CPU_ON_BOARD ├── procedure.vsdx ├── buttons_function.xlsx ├── CPU_ON_BOARD.srcs │ └── sources_1 │ │ └── bd │ │ └── MIPS_CPU │ │ ├── ip │ │ └── MIPS_CPU_clk_wiz_0_0 │ │ │ ├── MIPS_CPU_clk_wiz_0_0_board.xdc │ │ │ ├── MIPS_CPU_clk_wiz_0_0_ooc.xdc │ │ │ └── MIPS_CPU_clk_wiz_0_0.xdc │ │ ├── MIPS_CPU_ooc.xdc │ │ └── hdl │ │ └── MIPS_CPU_wrapper.v └── IPCORE │ ├── ALU │ └── ALU.srcs │ │ ├── xgui │ │ └── ALU32_v1_0.tcl │ │ ├── sources_1 │ │ └── new │ │ │ ├── LOGIC.v │ │ │ ├── SHIFT.v │ │ │ ├── ALU.v │ │ │ └── MATH.v │ │ └── sim_1 │ │ └── new │ │ └── ALU_TB.sv │ ├── REGFILE │ └── REGFILE.srcs │ │ ├── xgui │ │ └── REGFILE_v1_0.tcl │ │ ├── sources_1 │ │ └── new │ │ │ └── REGFILE.v │ │ └── sim_1 │ │ └── new │ │ └── REGFILE_TB.sv │ ├── DATAPATH │ └── DATAPATH.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── DATAPATH_v1_0.tcl │ │ ├── DATAPATH.v │ │ └── ADDSUB32.v │ ├── DATA_MEM │ └── DATA_MEM.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── DATA_MEM_v1_0.tcl │ │ └── DATA_MEM.v │ ├── SHOW_ON_LED │ └── SHOW_ON_LED.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── SHOW_ON_LED_v1_0.tcl │ │ └── SHOW_ON_LED.v │ ├── CONTROL_UNIT │ └── CONTROL_UNIT.srcs │ │ ├── sim_1 │ │ └── new │ │ │ └── CONTROL_UNIT_TB.sv │ │ └── sources_1 │ │ └── new │ │ └── CONTROL_UNIT.v │ └── KEY2INST │ └── KEY2INST.srcs │ └── sim_1 │ └── new │ └── KEY2INST_TB.sv ├── CPU_FOR_SIM ├── CPU_FOR_SIM.srcs │ ├── sources_1 │ │ └── bd │ │ │ └── MIPS_CPU │ │ │ ├── ip │ │ │ ├── MIPS_CPU_clk_wiz_0_0 │ │ │ │ ├── MIPS_CPU_clk_wiz_0_0_board.xdc │ │ │ │ ├── MIPS_CPU_clk_wiz_0_0_ooc.xdc │ │ │ │ ├── MIPS_CPU_clk_wiz_0_0.xdc │ │ │ │ └── doc │ │ │ │ │ └── clk_wiz_v5_1_changelog.txt │ │ │ ├── MIPS_CPU_INST_MEM_0_1 │ │ │ │ ├── sim │ │ │ │ │ └── MIPS_CPU_INST_MEM_0_1.v │ │ │ │ ├── synth │ │ │ │ │ └── MIPS_CPU_INST_MEM_0_1.v │ │ │ │ ├── MIPS_CPU_INST_MEM_0_1.veo │ │ │ │ └── MIPS_CPU_INST_MEM_0_1.xci │ │ │ ├── MIPS_CPU_ALU32_0_1 │ │ │ │ ├── sim │ │ │ │ │ └── MIPS_CPU_ALU32_0_1.v │ │ │ │ ├── synth │ │ │ │ │ └── MIPS_CPU_ALU32_0_1.v │ │ │ │ ├── MIPS_CPU_ALU32_0_1.xci │ │ │ │ └── MIPS_CPU_ALU32_0_1.veo │ │ │ ├── MIPS_CPU_DATA_MEM_0_1 │ │ │ │ ├── sim │ │ │ │ │ └── MIPS_CPU_DATA_MEM_0_1.v │ │ │ │ ├── synth │ │ │ │ │ └── MIPS_CPU_DATA_MEM_0_1.v │ │ │ │ └── MIPS_CPU_DATA_MEM_0_1.xci │ │ │ └── MIPS_CPU_REGFILE_0_1 │ │ │ │ ├── sim │ │ │ │ └── MIPS_CPU_REGFILE_0_1.v │ │ │ │ ├── MIPS_CPU_REGFILE_0_1.xci │ │ │ │ └── synth │ │ │ │ └── MIPS_CPU_REGFILE_0_1.v │ │ │ ├── MIPS_CPU_ooc.xdc │ │ │ ├── hdl │ │ │ └── MIPS_CPU_wrapper.v │ │ │ └── ui │ │ │ └── bd_a462dba8.ui │ └── sim_1 │ │ └── new │ │ └── MIPS_CPU_TB.sv └── IPCORE │ ├── ALU │ └── ALU.srcs │ │ ├── xgui │ │ └── ALU32_v1_0.tcl │ │ ├── sources_1 │ │ └── new │ │ │ ├── LOGIC.v │ │ │ ├── SHIFT.v │ │ │ ├── ALU.v │ │ │ └── MATH.v │ │ └── sim_1 │ │ └── new │ │ └── ALU_TB.sv │ ├── REGFILE │ └── REGFILE.srcs │ │ ├── xgui │ │ └── REGFILE_v1_0.tcl │ │ ├── sources_1 │ │ └── new │ │ │ └── REGFILE.v │ │ └── sim_1 │ │ └── new │ │ └── REGFILE_TB.sv │ ├── DATAPATH │ └── DATAPATH.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── DATAPATH_v1_0.tcl │ │ ├── DATAPATH.v │ │ └── ADDSUB32.v │ ├── DATA_MEM │ └── DATA_MEM.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── DATA_MEM_v1_0.tcl │ │ └── DATA_MEM.v │ ├── INST_MEM │ └── INST_MEM.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── INST_MEM_v1_0.tcl │ │ └── INST_MEM.v │ └── CONTROL_UNIT │ └── CONTROL_UNIT.srcs │ ├── sim_1 │ └── new │ │ └── CONTROL_UNIT_TB.sv │ └── sources_1 │ └── new │ └── CONTROL_UNIT.v ├── SUB_MODULE ├── ALU │ └── ALU.srcs │ │ ├── xgui │ │ └── ALU32_v1_0.tcl │ │ ├── sources_1 │ │ └── new │ │ │ ├── LOGIC.v │ │ │ ├── SHIFT.v │ │ │ ├── ALU.v │ │ │ └── MATH.v │ │ └── sim_1 │ │ └── new │ │ └── ALU_TB.sv ├── REGFILE │ ├── REGFILE.srcs │ │ ├── xgui │ │ │ └── REGFILE_v1_0.tcl │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── REGFILE.v │ │ └── sim_1 │ │ │ └── new │ │ │ └── REGFILE_TB.sv │ └── REGFILE.xpr ├── DATAPATH │ └── DATAPATH.srcs │ │ └── sources_1 │ │ └── new │ │ ├── xgui │ │ └── DATAPATH_v1_0.tcl │ │ ├── DATAPATH.v │ │ └── ADDSUB32.v ├── DATA_MEM │ ├── DATA_MEM.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── DATA_MEM_v1_0.tcl │ │ │ └── DATA_MEM.v │ └── DATA_MEM.xpr ├── INST_MEM │ ├── INST_MEM.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── INST_MEM_v1_0.tcl │ │ │ └── INST_MEM.v │ └── INST_MEM.xpr ├── SHOW_ON_LED │ ├── SHOW_ON_LED.srcs │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── SHOW_ON_LED_v1_0.tcl │ │ │ └── SHOW_ON_LED.v │ └── SHOW_ON_LED.xpr ├── CONTROL_UNIT │ └── CONTROL_UNIT.srcs │ │ ├── sim_1 │ │ └── new │ │ │ └── CONTROL_UNIT_TB.sv │ │ └── sources_1 │ │ └── new │ │ └── CONTROL_UNIT.v └── KEY2INST │ └── KEY2INST.srcs │ └── sim_1 │ └── new │ └── KEY2INST_TB.sv ├── ProjectTcl ├── IPCatalog │ ├── ALU │ │ └── ALU.srcs │ │ │ ├── xgui │ │ │ └── ALU32_v1_0.tcl │ │ │ ├── sources_1 │ │ │ └── new │ │ │ │ ├── LOGIC.v │ │ │ │ ├── SHIFT.v │ │ │ │ ├── ALU.v │ │ │ │ └── MATH.v │ │ │ └── sim_1 │ │ │ └── new │ │ │ └── ALU_TB.sv │ ├── REGFILE │ │ └── REGFILE.srcs │ │ │ ├── xgui │ │ │ └── REGFILE_v1_0.tcl │ │ │ ├── sources_1 │ │ │ └── new │ │ │ │ └── REGFILE.v │ │ │ └── sim_1 │ │ │ └── new │ │ │ └── REGFILE_TB.sv │ ├── DATAPATH │ │ └── DATAPATH.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── DATAPATH_v1_0.tcl │ │ │ ├── DATAPATH.v │ │ │ └── ADDSUB32.v │ ├── DATA_MEM │ │ └── DATA_MEM.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── DATA_MEM_v1_0.tcl │ │ │ └── DATA_MEM.v │ ├── INST_MEM │ │ └── INST_MEM.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── INST_MEM_v1_0.tcl │ │ │ └── INST_MEM.v │ ├── SHOW_ON_LED │ │ └── SHOW_ON_LED.srcs │ │ │ └── sources_1 │ │ │ └── new │ │ │ ├── xgui │ │ │ └── SHOW_ON_LED_v1_0.tcl │ │ │ └── SHOW_ON_LED.v │ ├── CONTROL_UNIT │ │ └── CONTROL_UNIT.srcs │ │ │ ├── sim_1 │ │ │ └── new │ │ │ │ └── CONTROL_UNIT_TB.sv │ │ │ └── sources_1 │ │ │ └── new │ │ │ └── CONTROL_UNIT.v │ └── KEY2INST │ │ └── KEY2INST.srcs │ │ └── sim_1 │ │ └── new │ │ └── KEY2INST_TB.sv └── Sim │ └── MIPS_CPU_TB.sv ├── LICENSE └── README.md /Image/1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dtysky/SIMPLE_MIPS_CPU/HEAD/Image/1.png -------------------------------------------------------------------------------- /Image/2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dtysky/SIMPLE_MIPS_CPU/HEAD/Image/2.png -------------------------------------------------------------------------------- /Image/3.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dtysky/SIMPLE_MIPS_CPU/HEAD/Image/3.png -------------------------------------------------------------------------------- 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/CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/MIPS_CPU_clk_wiz_0_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/CPU_ON_BOARD.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/MIPS_CPU_clk_wiz_0_0_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /SUB_MODULE/ALU/ALU.srcs/xgui/ALU32_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/ALU/ALU.srcs/xgui/ALU32_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/ALU/ALU.srcs/xgui/ALU32_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/ALU/ALU.srcs/xgui/ALU32_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /SUB_MODULE/REGFILE/REGFILE.srcs/xgui/REGFILE_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/REGFILE/REGFILE.srcs/xgui/REGFILE_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/REGFILE/REGFILE.srcs/xgui/REGFILE_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/REGFILE/REGFILE.srcs/xgui/REGFILE_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /SUB_MODULE/DATAPATH/DATAPATH.srcs/sources_1/new/xgui/DATAPATH_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /SUB_MODULE/DATA_MEM/DATA_MEM.srcs/sources_1/new/xgui/DATA_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /SUB_MODULE/INST_MEM/INST_MEM.srcs/sources_1/new/xgui/INST_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/DATAPATH/DATAPATH.srcs/sources_1/new/xgui/DATAPATH_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/DATA_MEM/DATA_MEM.srcs/sources_1/new/xgui/DATA_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/INST_MEM/INST_MEM.srcs/sources_1/new/xgui/INST_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/DATAPATH/DATAPATH.srcs/sources_1/new/xgui/DATAPATH_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/DATA_MEM/DATA_MEM.srcs/sources_1/new/xgui/DATA_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/DATAPATH/DATAPATH.srcs/sources_1/new/xgui/DATAPATH_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/DATA_MEM/DATA_MEM.srcs/sources_1/new/xgui/DATA_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/INST_MEM/INST_MEM.srcs/sources_1/new/xgui/INST_MEM_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /SUB_MODULE/SHOW_ON_LED/SHOW_ON_LED.srcs/sources_1/new/xgui/SHOW_ON_LED_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/SHOW_ON_LED/SHOW_ON_LED.srcs/sources_1/new/xgui/SHOW_ON_LED_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/SHOW_ON_LED/SHOW_ON_LED.srcs/sources_1/new/xgui/SHOW_ON_LED_v1_0.tcl: -------------------------------------------------------------------------------- 1 | # Definitional proc to organize widgets for parameters. 2 | proc init_gui { IPINST } { 3 | set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical] 4 | set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name] 5 | } 6 | 7 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/MIPS_CPU_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | #create_clock -name clock_name -period 10 [get_ports clock_name] 10 | ################################################################################ 11 | 12 | ################################################################################ -------------------------------------------------------------------------------- /CPU_ON_BOARD/CPU_ON_BOARD.srcs/sources_1/bd/MIPS_CPU/MIPS_CPU_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | #create_clock -name clock_name -period 10 [get_ports clock_name] 10 | ################################################################################ 11 | 12 | ################################################################################ -------------------------------------------------------------------------------- /SUB_MODULE/ALU/ALU.srcs/sources_1/new/LOGIC.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: LOGIC32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module LOGIC32( 25 | input[31:0] a,b, 26 | input cmd, 27 | output[31:0] r_a,r_b 28 | ); 29 | 30 | //AND 31 | //OR 32 | assign r_a = cmd ? a|b : a&b; 33 | 34 | //XOR 35 | //LUI 36 | assign r_b = cmd ? b<<16 : a^b; 37 | 38 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/ALU/ALU.srcs/sources_1/new/LOGIC.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: LOGIC32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module LOGIC32( 25 | input[31:0] a,b, 26 | input cmd, 27 | output[31:0] r_a,r_b 28 | ); 29 | 30 | //AND 31 | //OR 32 | assign r_a = cmd ? a|b : a&b; 33 | 34 | //XOR 35 | //LUI 36 | assign r_b = cmd ? b<<16 : a^b; 37 | 38 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/ALU/ALU.srcs/sources_1/new/LOGIC.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: LOGIC32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module LOGIC32( 25 | input[31:0] a,b, 26 | input cmd, 27 | output[31:0] r_a,r_b 28 | ); 29 | 30 | //AND 31 | //OR 32 | assign r_a = cmd ? a|b : a&b; 33 | 34 | //XOR 35 | //LUI 36 | assign r_b = cmd ? b<<16 : a^b; 37 | 38 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/ALU/ALU.srcs/sources_1/new/LOGIC.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: LOGIC32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module LOGIC32( 25 | input[31:0] a,b, 26 | input cmd, 27 | output[31:0] r_a,r_b 28 | ); 29 | 30 | //AND 31 | //OR 32 | assign r_a = cmd ? a|b : a&b; 33 | 34 | //XOR 35 | //LUI 36 | assign r_b = cmd ? b<<16 : a^b; 37 | 38 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/CPU_ON_BOARD.srcs/sources_1/bd/MIPS_CPU/hdl/MIPS_CPU_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014 4 | //Date : Mon Jan 26 13:25:28 2015 5 | //Host : Dtysky running 64-bit major release (build 9200) 6 | //Command : generate_target MIPS_CPU_wrapper.bd 7 | //Design : MIPS_CPU_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module MIPS_CPU_wrapper 13 | (inclk, 14 | key, 15 | led); 16 | input inclk; 17 | input [15:0]key; 18 | output [15:0]led; 19 | 20 | wire inclk; 21 | wire [15:0]key; 22 | wire [15:0]led; 23 | 24 | MIPS_CPU MIPS_CPU_i 25 | (.inclk(inclk), 26 | .key(key), 27 | .led(led)); 28 | endmodule 29 | -------------------------------------------------------------------------------- /SUB_MODULE/SHOW_ON_LED/SHOW_ON_LED.srcs/sources_1/new/SHOW_ON_LED.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: SHOW_ON_LED 8 | // Module Name: SHOW_ON_LED 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHOW_ON_LED( 24 | input clk, 25 | input[5:0] inst_op, 26 | input[31:0] alu_r, 27 | input[15:0] button, 28 | output[15:0] led 29 | ); 30 | 31 | wire run; 32 | reg[15:0] alu_result; 33 | 34 | assign run = button[14]; 35 | assign led = run ? alu_result : button; 36 | 37 | always @(posedge clk) 38 | alu_result <= (inst_op==6'b0 && run==1'b1) ? alu_r[15:0] : alu_result; 39 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/ALU/ALU.srcs/sources_1/new/SHIFT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: SHIFT32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHIFT32( 24 | input[4:0] sa, 25 | input signed [31:0] d, 26 | input right,arith, 27 | output[31:0] sh 28 | ); 29 | 30 | reg[31:0] r_sh; 31 | 32 | always @(*) begin 33 | case ({right,arith}) 34 | 2'b00 : 35 | r_sh <= d << sa; 36 | 2'b10 : 37 | r_sh <= d >> sa; 38 | 2'b01 : 39 | r_sh <= d <<< sa; 40 | 2'b11 : 41 | r_sh <= d >>> sa; 42 | endcase 43 | end 44 | 45 | assign sh = r_sh; 46 | 47 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/ALU/ALU.srcs/sources_1/new/SHIFT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: SHIFT32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHIFT32( 24 | input[4:0] sa, 25 | input signed [31:0] d, 26 | input right,arith, 27 | output[31:0] sh 28 | ); 29 | 30 | reg[31:0] r_sh; 31 | 32 | always @(*) begin 33 | case ({right,arith}) 34 | 2'b00 : 35 | r_sh <= d << sa; 36 | 2'b10 : 37 | r_sh <= d >> sa; 38 | 2'b01 : 39 | r_sh <= d <<< sa; 40 | 2'b11 : 41 | r_sh <= d >>> sa; 42 | endcase 43 | end 44 | 45 | assign sh = r_sh; 46 | 47 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/ALU/ALU.srcs/sources_1/new/SHIFT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: SHIFT32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHIFT32( 24 | input[4:0] sa, 25 | input signed [31:0] d, 26 | input right,arith, 27 | output[31:0] sh 28 | ); 29 | 30 | reg[31:0] r_sh; 31 | 32 | always @(*) begin 33 | case ({right,arith}) 34 | 2'b00 : 35 | r_sh <= d << sa; 36 | 2'b10 : 37 | r_sh <= d >> sa; 38 | 2'b01 : 39 | r_sh <= d <<< sa; 40 | 2'b11 : 41 | r_sh <= d >>> sa; 42 | endcase 43 | end 44 | 45 | assign sh = r_sh; 46 | 47 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/SHOW_ON_LED/SHOW_ON_LED.srcs/sources_1/new/SHOW_ON_LED.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: SHOW_ON_LED 8 | // Module Name: SHOW_ON_LED 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHOW_ON_LED( 24 | input clk, 25 | input[5:0] inst_op, 26 | input[31:0] alu_r, 27 | input[15:0] button, 28 | output[15:0] led 29 | ); 30 | 31 | wire run; 32 | reg[15:0] alu_result; 33 | 34 | assign run = button[14]; 35 | assign led = run ? alu_result : button; 36 | 37 | always @(posedge clk) 38 | alu_result <= (inst_op==6'b0 && run==1'b1) ? alu_r[15:0] : alu_result; 39 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/SHOW_ON_LED/SHOW_ON_LED.srcs/sources_1/new/SHOW_ON_LED.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: SHOW_ON_LED 8 | // Module Name: SHOW_ON_LED 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHOW_ON_LED( 24 | input clk, 25 | input[5:0] inst_op, 26 | input[31:0] alu_r, 27 | input[15:0] button, 28 | output[15:0] led 29 | ); 30 | 31 | wire run; 32 | reg[15:0] alu_result; 33 | 34 | assign run = button[14]; 35 | assign led = run ? alu_result : button; 36 | 37 | always @(posedge clk) 38 | alu_result <= (inst_op==6'b0 && run==1'b1) ? alu_r[15:0] : alu_result; 39 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/ALU/ALU.srcs/sources_1/new/SHIFT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: SHIFT32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module SHIFT32( 24 | input[4:0] sa, 25 | input signed [31:0] d, 26 | input right,arith, 27 | output[31:0] sh 28 | ); 29 | 30 | reg[31:0] r_sh; 31 | 32 | always @(*) begin 33 | case ({right,arith}) 34 | 2'b00 : 35 | r_sh <= d << sa; 36 | 2'b10 : 37 | r_sh <= d >> sa; 38 | 2'b01 : 39 | r_sh <= d <<< sa; 40 | 2'b11 : 41 | r_sh <= d >>> sa; 42 | endcase 43 | end 44 | 45 | assign sh = r_sh; 46 | 47 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/Sim/MIPS_CPU_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/01/19 12:18:42 7 | // Design Name: 8 | // Module Name: MIPS_CPU_TB 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(10ns) begin 26 | clk = ~clk; 27 | end 28 | endmodule 29 | 30 | module MIPS_CPU_TB(); 31 | 32 | bit clk,reset; 33 | bit[31:0] alu_outpin,data_outpin,inst_outpin,pc_outpin; 34 | 35 | CLOCK CLOCK1(clk); 36 | MIPS_CPU_wrapper MIPS_CPU_wrapper1(alu_outpin,clk,data_outpin,inst_outpin,pc_outpin, reset); 37 | 38 | initial begin 39 | reset = 1'b0; 40 | repeat(100) @(posedge clk); 41 | reset = 1'b1; 42 | repeat(1000) @(posedge clk); 43 | reset = 1'b0; 44 | $finish; 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sim_1/new/MIPS_CPU_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2015/01/19 12:18:42 7 | // Design Name: 8 | // Module Name: MIPS_CPU_TB 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(10ns) begin 26 | clk = ~clk; 27 | end 28 | endmodule 29 | 30 | module MIPS_CPU_TB(); 31 | 32 | bit clk,reset; 33 | bit[31:0] alu_outpin,data_outpin,inst_outpin,pc_outpin; 34 | 35 | CLOCK CLOCK1(clk); 36 | MIPS_CPU_wrapper MIPS_CPU_wrapper1(alu_outpin,clk,data_outpin,inst_outpin,pc_outpin, reset); 37 | 38 | initial begin 39 | reset = 1'b0; 40 | repeat(100) @(posedge clk); 41 | reset = 1'b1; 42 | repeat(1000) @(posedge clk); 43 | reset = 1'b0; 44 | end 45 | 46 | endmodule -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | The MIT License (MIT) 2 | 3 | Copyright (c) 2015 dtysky 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | 23 | -------------------------------------------------------------------------------- /SUB_MODULE/DATA_MEM/DATA_MEM.srcs/sources_1/new/DATA_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 10:15:06 7 | // Design Name: DATA_MEM 8 | // Module Name: DATA_MEM 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATA_MEM( 24 | input[31:0] addr,data_in, 25 | input clk,we, 26 | output[31:0] data_out 27 | ); 28 | 29 | reg[31:0] ram[0:31]; 30 | 31 | always @(posedge clk) begin 32 | if(we) ram[addr[6:2]] <= data_in; 33 | end 34 | 35 | assign data_out = ram[addr[6:2]]; 36 | 37 | integer i; 38 | initial begin 39 | for (i=0;i<32;i=i+1) 40 | ram[i] = 32'b0; 41 | ram[5'h14] = 32'h000000a3; 42 | ram[5'h15] = 32'h00000027; 43 | ram[5'h16] = 32'h00000079; 44 | ram[5'h17] = 32'h00000115; 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/DATA_MEM/DATA_MEM.srcs/sources_1/new/DATA_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 10:15:06 7 | // Design Name: DATA_MEM 8 | // Module Name: DATA_MEM 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATA_MEM( 24 | input[31:0] addr,data_in, 25 | input clk,we, 26 | output[31:0] data_out 27 | ); 28 | 29 | reg[31:0] ram[0:31]; 30 | 31 | always @(posedge clk) begin 32 | if(we) ram[addr[6:2]] <= data_in; 33 | end 34 | 35 | assign data_out = ram[addr[6:2]]; 36 | 37 | integer i; 38 | initial begin 39 | for (i=0;i<32;i=i+1) 40 | ram[i] = 32'b0; 41 | ram[5'h14] = 32'h000000a3; 42 | ram[5'h15] = 32'h00000027; 43 | ram[5'h16] = 32'h00000079; 44 | ram[5'h17] = 32'h00000115; 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/DATA_MEM/DATA_MEM.srcs/sources_1/new/DATA_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 10:15:06 7 | // Design Name: DATA_MEM 8 | // Module Name: DATA_MEM 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATA_MEM( 24 | input[31:0] addr,data_in, 25 | input clk,we, 26 | output[31:0] data_out 27 | ); 28 | 29 | reg[31:0] ram[0:31]; 30 | 31 | always @(posedge clk) begin 32 | if(we) ram[addr[6:2]] <= data_in; 33 | end 34 | 35 | assign data_out = ram[addr[6:2]]; 36 | 37 | integer i; 38 | initial begin 39 | for (i=0;i<32;i=i+1) 40 | ram[i] = 32'b0; 41 | ram[5'h14] = 32'h000000a3; 42 | ram[5'h15] = 32'h00000027; 43 | ram[5'h16] = 32'h00000079; 44 | ram[5'h17] = 32'h00000115; 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/DATA_MEM/DATA_MEM.srcs/sources_1/new/DATA_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 10:15:06 7 | // Design Name: DATA_MEM 8 | // Module Name: DATA_MEM 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATA_MEM( 24 | input[31:0] addr,data_in, 25 | input clk,we, 26 | output[31:0] data_out 27 | ); 28 | 29 | reg[31:0] ram[0:31]; 30 | 31 | always @(posedge clk) begin 32 | if(we) ram[addr[6:2]] <= data_in; 33 | end 34 | 35 | assign data_out = ram[addr[6:2]]; 36 | 37 | integer i; 38 | initial begin 39 | for (i=0;i<32;i=i+1) 40 | ram[i] = 32'b0; 41 | ram[5'h14] = 32'h000000a3; 42 | ram[5'h15] = 32'h00000027; 43 | ram[5'h16] = 32'h00000079; 44 | ram[5'h17] = 32'h00000115; 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/REGFILE/REGFILE.srcs/sources_1/new/REGFILE.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/17 19:33:58 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module REGFILE( 24 | input clk,clrn, 25 | input[31:0] d, 26 | input we, 27 | input[4:0] wn,rna,rnb, 28 | output[31:0] qa,qb 29 | ); 30 | 31 | reg[31:0] reg32[31:0]; 32 | 33 | integer i; 34 | initial begin 35 | for (i=1;i<=31;i=i+1) 36 | reg32[i] = 32'b0; 37 | end 38 | 39 | always @(posedge clk or negedge clrn) begin 40 | if(~clrn) begin 41 | for (i=0;i<=31;i=i+1) 42 | reg32[i] <= 32'b0; 43 | end else if (we && wn) begin 44 | reg32[wn] <= d; 45 | end 46 | end 47 | 48 | assign qa = reg32[rna]; 49 | assign qb = reg32[rnb]; 50 | 51 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/REGFILE/REGFILE.srcs/sources_1/new/REGFILE.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/17 19:33:58 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module REGFILE( 24 | input clk,clrn, 25 | input[31:0] d, 26 | input we, 27 | input[4:0] wn,rna,rnb, 28 | output[31:0] qa,qb 29 | ); 30 | 31 | reg[31:0] reg32[31:0]; 32 | 33 | integer i; 34 | initial begin 35 | for (i=1;i<=31;i=i+1) 36 | reg32[i] = 32'b0; 37 | end 38 | 39 | always @(posedge clk or negedge clrn) begin 40 | if(~clrn) begin 41 | for (i=0;i<=31;i=i+1) 42 | reg32[i] <= 32'b0; 43 | end else if (we && wn) begin 44 | reg32[wn] <= d; 45 | end 46 | end 47 | 48 | assign qa = reg32[rna]; 49 | assign qb = reg32[rnb]; 50 | 51 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/REGFILE/REGFILE.srcs/sources_1/new/REGFILE.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/17 19:33:58 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module REGFILE( 24 | input clk,clrn, 25 | input[31:0] d, 26 | input we, 27 | input[4:0] wn,rna,rnb, 28 | output[31:0] qa,qb 29 | ); 30 | 31 | reg[31:0] reg32[31:0]; 32 | 33 | integer i; 34 | initial begin 35 | for (i=1;i<=31;i=i+1) 36 | reg32[i] = 32'b0; 37 | end 38 | 39 | always @(posedge clk or negedge clrn) begin 40 | if(~clrn) begin 41 | for (i=0;i<=31;i=i+1) 42 | reg32[i] <= 32'b0; 43 | end else if (we && wn) begin 44 | reg32[wn] <= d; 45 | end 46 | end 47 | 48 | assign qa = reg32[rna]; 49 | assign qb = reg32[rnb]; 50 | 51 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/REGFILE/REGFILE.srcs/sources_1/new/REGFILE.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/17 19:33:58 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module REGFILE( 24 | input clk,clrn, 25 | input[31:0] d, 26 | input we, 27 | input[4:0] wn,rna,rnb, 28 | output[31:0] qa,qb 29 | ); 30 | 31 | reg[31:0] reg32[31:0]; 32 | 33 | integer i; 34 | initial begin 35 | for (i=1;i<=31;i=i+1) 36 | reg32[i] = 32'b0; 37 | end 38 | 39 | always @(posedge clk or negedge clrn) begin 40 | if(~clrn) begin 41 | for (i=0;i<=31;i=i+1) 42 | reg32[i] <= 32'b0; 43 | end else if (we && wn) begin 44 | reg32[wn] <= d; 45 | end 46 | end 47 | 48 | assign qa = reg32[rna]; 49 | assign qb = reg32[rnb]; 50 | 51 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/ALU/ALU.srcs/sources_1/new/ALU.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: ALU32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module ALU32( 25 | input[31:0] a,b,aluc, 26 | output[31:0] r, 27 | output z 28 | ); 29 | 30 | reg[31:0] r_r; 31 | wire[31:0] r_shift,r_logic_andor,r_logic_xorlui,r_addsub; 32 | 33 | 34 | SHIFT32 SHITF0 (a[4:0],b,aluc[2],aluc[3],r_shift); 35 | LOGIC32 LOGIC0 (a,b,aluc[2],r_logic_andor,r_logic_xorlui); 36 | ADDSUB32 ADDSUB0 (a,b,aluc[2],r_addsub); 37 | 38 | always @(*) begin 39 | case(aluc[1:0]) 40 | 2'b00: r_r <= r_addsub; 41 | 2'b01: r_r <= r_logic_andor; 42 | 2'b10: r_r <= r_logic_xorlui; 43 | 2'b11: r_r <= r_shift; 44 | endcase 45 | end 46 | 47 | assign z = r_r==0 ? 1 : 0; 48 | assign r = r_r; 49 | 50 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/ALU/ALU.srcs/sources_1/new/ALU.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: ALU32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module ALU32( 25 | input[31:0] a,b,aluc, 26 | output[31:0] r, 27 | output z 28 | ); 29 | 30 | reg[31:0] r_r; 31 | wire[31:0] r_shift,r_logic_andor,r_logic_xorlui,r_addsub; 32 | 33 | 34 | SHIFT32 SHITF0 (a[4:0],b,aluc[2],aluc[3],r_shift); 35 | LOGIC32 LOGIC0 (a,b,aluc[2],r_logic_andor,r_logic_xorlui); 36 | ADDSUB32 ADDSUB0 (a,b,aluc[2],r_addsub); 37 | 38 | always @(*) begin 39 | case(aluc[1:0]) 40 | 2'b00: r_r <= r_addsub; 41 | 2'b01: r_r <= r_logic_andor; 42 | 2'b10: r_r <= r_logic_xorlui; 43 | 2'b11: r_r <= r_shift; 44 | endcase 45 | end 46 | 47 | assign z = r_r==0 ? 1 : 0; 48 | assign r = r_r; 49 | 50 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/ALU/ALU.srcs/sources_1/new/ALU.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: ALU32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module ALU32( 25 | input[31:0] a,b,aluc, 26 | output[31:0] r, 27 | output z 28 | ); 29 | 30 | reg[31:0] r_r; 31 | wire[31:0] r_shift,r_logic_andor,r_logic_xorlui,r_addsub; 32 | 33 | 34 | SHIFT32 SHITF0 (a[4:0],b,aluc[2],aluc[3],r_shift); 35 | LOGIC32 LOGIC0 (a,b,aluc[2],r_logic_andor,r_logic_xorlui); 36 | ADDSUB32 ADDSUB0 (a,b,aluc[2],r_addsub); 37 | 38 | always @(*) begin 39 | case(aluc[1:0]) 40 | 2'b00: r_r <= r_addsub; 41 | 2'b01: r_r <= r_logic_andor; 42 | 2'b10: r_r <= r_logic_xorlui; 43 | 2'b11: r_r <= r_shift; 44 | endcase 45 | end 46 | 47 | assign z = r_r==0 ? 1 : 0; 48 | assign r = r_r; 49 | 50 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/ALU/ALU.srcs/sources_1/new/ALU.v: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/16 18:34:13 8 | // Design Name: ALU32 9 | // Module Name: ALU32 10 | // Project Name: MIPS_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | 24 | module ALU32( 25 | input[31:0] a,b,aluc, 26 | output[31:0] r, 27 | output z 28 | ); 29 | 30 | reg[31:0] r_r; 31 | wire[31:0] r_shift,r_logic_andor,r_logic_xorlui,r_addsub; 32 | 33 | 34 | SHIFT32 SHITF0 (a[4:0],b,aluc[2],aluc[3],r_shift); 35 | LOGIC32 LOGIC0 (a,b,aluc[2],r_logic_andor,r_logic_xorlui); 36 | ADDSUB32 ADDSUB0 (a,b,aluc[2],r_addsub); 37 | 38 | always @(*) begin 39 | case(aluc[1:0]) 40 | 2'b00: r_r <= r_addsub; 41 | 2'b01: r_r <= r_logic_andor; 42 | 2'b10: r_r <= r_logic_xorlui; 43 | 2'b11: r_r <= r_shift; 44 | endcase 45 | end 46 | 47 | assign z = r_r==0 ? 1 : 0; 48 | assign r = r_r; 49 | 50 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/hdl/MIPS_CPU_wrapper.v: -------------------------------------------------------------------------------- 1 | //Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. 2 | //-------------------------------------------------------------------------------- 3 | //Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014 4 | //Date : Tue Jan 27 10:02:38 2015 5 | //Host : Dtysky running 64-bit major release (build 9200) 6 | //Command : generate_target MIPS_CPU_wrapper.bd 7 | //Design : MIPS_CPU_wrapper 8 | //Purpose : IP block netlist 9 | //-------------------------------------------------------------------------------- 10 | `timescale 1 ps / 1 ps 11 | 12 | module MIPS_CPU_wrapper 13 | (alu_pinout, 14 | clk, 15 | data_pinout, 16 | inst_pinout, 17 | pc_pinout, 18 | restet); 19 | output [31:0]alu_pinout; 20 | input clk; 21 | output [31:0]data_pinout; 22 | output [31:0]inst_pinout; 23 | output [31:0]pc_pinout; 24 | input restet; 25 | 26 | wire [31:0]alu_pinout; 27 | wire clk; 28 | wire [31:0]data_pinout; 29 | wire [31:0]inst_pinout; 30 | wire [31:0]pc_pinout; 31 | wire restet; 32 | 33 | MIPS_CPU MIPS_CPU_i 34 | (.alu_pinout(alu_pinout), 35 | .clk(clk), 36 | .data_pinout(data_pinout), 37 | .inst_pinout(inst_pinout), 38 | .pc_pinout(pc_pinout), 39 | .restet(restet)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /SUB_MODULE/INST_MEM/INST_MEM.srcs/sources_1/new/INST_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 09:26:57 7 | // Design Name: INST_MEM 8 | // Module Name: INST_MEM 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module INST_MEM( 24 | input[31:0] a, 25 | output[31:0] inst_out ); 26 | 27 | wire[31:0] rom[0:31]; 28 | 29 | assign rom[5'h0] = 32'h3c010000; 30 | assign rom[5'h1] = 32'h34240050; 31 | assign rom[5'h2] = 32'h20050004; 32 | assign rom[5'h3] = 32'h0c000018; 33 | assign rom[5'h4] = 32'hac820000; 34 | assign rom[5'h5] = 32'h8c890000; 35 | assign rom[5'h6] = 32'h01244022; 36 | assign rom[5'h7] = 32'h20050003; 37 | assign rom[5'h8] = 32'h20a5ffff; 38 | assign rom[5'h9] = 32'h34a8ffff; 39 | assign rom[5'ha] = 32'h39085555; 40 | assign rom[5'hb] = 32'h2009ffff; 41 | assign rom[5'hc] = 32'h3124ffff; 42 | assign rom[5'hd] = 32'h01493025; 43 | assign rom[5'he] = 32'h01494026; 44 | assign rom[5'hf] = 32'h01463824; 45 | assign rom[5'h10] = 32'h10a00001; 46 | assign rom[5'h11] = 32'h08000008; 47 | assign rom[5'h12] = 32'h2005ffff; 48 | assign rom[5'h13] = 32'h000543c0; 49 | assign rom[5'h14] = 32'h00084400; 50 | assign rom[5'h15] = 32'h00084403; 51 | assign rom[5'h16] = 32'h000843c2; 52 | assign rom[5'h17] = 32'h08000017; 53 | assign rom[5'h18] = 32'h00004020; 54 | assign rom[5'h19] = 32'h8c890000; 55 | assign rom[5'h1a] = 32'h20840004; 56 | assign rom[5'h1b] = 32'h01094020; 57 | assign rom[5'h1c] = 32'h20a5ffff; 58 | assign rom[5'h1d] = 32'h14a0fffb; 59 | assign rom[5'h1e] = 32'h00081000; 60 | assign rom[5'h1f] = 32'h03e00008; 61 | 62 | assign inst_out = rom[a[6:2]]; 63 | 64 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/INST_MEM/INST_MEM.srcs/sources_1/new/INST_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 09:26:57 7 | // Design Name: INST_MEM 8 | // Module Name: INST_MEM 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module INST_MEM( 24 | input[31:0] a, 25 | output[31:0] inst_out ); 26 | 27 | wire[31:0] rom[0:31]; 28 | 29 | assign rom[5'h0] = 32'h3c010000; 30 | assign rom[5'h1] = 32'h34240050; 31 | assign rom[5'h2] = 32'h20050004; 32 | assign rom[5'h3] = 32'h0c000018; 33 | assign rom[5'h4] = 32'hac820000; 34 | assign rom[5'h5] = 32'h8c890000; 35 | assign rom[5'h6] = 32'h01244022; 36 | assign rom[5'h7] = 32'h20050003; 37 | assign rom[5'h8] = 32'h20a5ffff; 38 | assign rom[5'h9] = 32'h34a8ffff; 39 | assign rom[5'ha] = 32'h39085555; 40 | assign rom[5'hb] = 32'h2009ffff; 41 | assign rom[5'hc] = 32'h3124ffff; 42 | assign rom[5'hd] = 32'h01493025; 43 | assign rom[5'he] = 32'h01494026; 44 | assign rom[5'hf] = 32'h01463824; 45 | assign rom[5'h10] = 32'h10a00001; 46 | assign rom[5'h11] = 32'h08000008; 47 | assign rom[5'h12] = 32'h2005ffff; 48 | assign rom[5'h13] = 32'h000543c0; 49 | assign rom[5'h14] = 32'h00084400; 50 | assign rom[5'h15] = 32'h00084403; 51 | assign rom[5'h16] = 32'h000843c2; 52 | assign rom[5'h17] = 32'h08000017; 53 | assign rom[5'h18] = 32'h00004020; 54 | assign rom[5'h19] = 32'h8c890000; 55 | assign rom[5'h1a] = 32'h20840004; 56 | assign rom[5'h1b] = 32'h01094020; 57 | assign rom[5'h1c] = 32'h20a5ffff; 58 | assign rom[5'h1d] = 32'h14a0fffb; 59 | assign rom[5'h1e] = 32'h00081000; 60 | assign rom[5'h1f] = 32'h03e00008; 61 | 62 | assign inst_out = rom[a[6:2]]; 63 | 64 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/INST_MEM/INST_MEM.srcs/sources_1/new/INST_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/19 09:26:57 7 | // Design Name: INST_MEM 8 | // Module Name: INST_MEM 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module INST_MEM( 24 | input[31:0] a, 25 | output[31:0] inst_out ); 26 | 27 | wire[31:0] rom[0:31]; 28 | 29 | assign rom[5'h0] = 32'h3c010000; 30 | assign rom[5'h1] = 32'h34240050; 31 | assign rom[5'h2] = 32'h20050004; 32 | assign rom[5'h3] = 32'h0c000018; 33 | assign rom[5'h4] = 32'hac820000; 34 | assign rom[5'h5] = 32'h8c890000; 35 | assign rom[5'h6] = 32'h01244022; 36 | assign rom[5'h7] = 32'h20050003; 37 | assign rom[5'h8] = 32'h20a5ffff; 38 | assign rom[5'h9] = 32'h34a8ffff; 39 | assign rom[5'ha] = 32'h39085555; 40 | assign rom[5'hb] = 32'h2009ffff; 41 | assign rom[5'hc] = 32'h3124ffff; 42 | assign rom[5'hd] = 32'h01493025; 43 | assign rom[5'he] = 32'h01494026; 44 | assign rom[5'hf] = 32'h01463824; 45 | assign rom[5'h10] = 32'h10a00001; 46 | assign rom[5'h11] = 32'h08000008; 47 | assign rom[5'h12] = 32'h2005ffff; 48 | assign rom[5'h13] = 32'h000543c0; 49 | assign rom[5'h14] = 32'h00084400; 50 | assign rom[5'h15] = 32'h00084403; 51 | assign rom[5'h16] = 32'h000843c2; 52 | assign rom[5'h17] = 32'h08000017; 53 | assign rom[5'h18] = 32'h00004020; 54 | assign rom[5'h19] = 32'h8c890000; 55 | assign rom[5'h1a] = 32'h20840004; 56 | assign rom[5'h1b] = 32'h01094020; 57 | assign rom[5'h1c] = 32'h20a5ffff; 58 | assign rom[5'h1d] = 32'h14a0fffb; 59 | assign rom[5'h1e] = 32'h00081000; 60 | assign rom[5'h1f] = 32'h03e00008; 61 | 62 | assign inst_out = rom[a[6:2]]; 63 | 64 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/CONTROL_UNIT/CONTROL_UNIT.srcs/sim_1/new/CONTROL_UNIT_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:09:04 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | 32 | module CONTROL_UNIT_TB(); 33 | 34 | class data_creat; 35 | rand bit[5:0] op,func; 36 | rand bit z; 37 | 38 | function void next(); 39 | this.randomize(); 40 | endfunction : next 41 | endclass : data_creat 42 | 43 | bit clk; 44 | bit[5:0] op,func; 45 | bit z; 46 | bit wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem; 47 | bit[3:0] aluc; 48 | bit[1:0] pcsource; 49 | 50 | data_creat dc; 51 | 52 | CLOCK CLOCK1(clk); 53 | CONTROL_UNIT C1(op,func,z,wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem,aluc,pcsource); 54 | 55 | task req_1(); 56 | @(posedge clk); 57 | dc.next(); 58 | op = dc.op; 59 | func = dc.func; 60 | z = dc.z; 61 | endtask : req_1 62 | 63 | task req_2(); 64 | @(posedge clk); 65 | dc.next(); 66 | op = 6'b000000; 67 | func = dc.func; 68 | z = dc.z; 69 | endtask : req_2 70 | 71 | task check(); 72 | @(negedge clk); 73 | $display("op = %b\nfunc = %b\nz = %b",op,func,z); 74 | $display("wreg = %b\nregrt = %b\njal = %b\nm2reg = %b\nshfit = %b\naluimm = %b\nsext = %b\nwmem = %b", 75 | wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem); 76 | $display("aluc = %b\npcsource = %b\n",aluc,pcsource); 77 | endtask : check 78 | 79 | initial begin 80 | dc=new(); 81 | repeat(100) begin 82 | req_1(); 83 | check(); 84 | end 85 | repeat(100) begin 86 | req_2(); 87 | check(); 88 | end 89 | end 90 | 91 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/CONTROL_UNIT/CONTROL_UNIT.srcs/sim_1/new/CONTROL_UNIT_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:09:04 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | 32 | module CONTROL_UNIT_TB(); 33 | 34 | class data_creat; 35 | rand bit[5:0] op,func; 36 | rand bit z; 37 | 38 | function void next(); 39 | this.randomize(); 40 | endfunction : next 41 | endclass : data_creat 42 | 43 | bit clk; 44 | bit[5:0] op,func; 45 | bit z; 46 | bit wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem; 47 | bit[3:0] aluc; 48 | bit[1:0] pcsource; 49 | 50 | data_creat dc; 51 | 52 | CLOCK CLOCK1(clk); 53 | CONTROL_UNIT C1(op,func,z,wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem,aluc,pcsource); 54 | 55 | task req_1(); 56 | @(posedge clk); 57 | dc.next(); 58 | op = dc.op; 59 | func = dc.func; 60 | z = dc.z; 61 | endtask : req_1 62 | 63 | task req_2(); 64 | @(posedge clk); 65 | dc.next(); 66 | op = 6'b000000; 67 | func = dc.func; 68 | z = dc.z; 69 | endtask : req_2 70 | 71 | task check(); 72 | @(negedge clk); 73 | $display("op = %b\nfunc = %b\nz = %b",op,func,z); 74 | $display("wreg = %b\nregrt = %b\njal = %b\nm2reg = %b\nshfit = %b\naluimm = %b\nsext = %b\nwmem = %b", 75 | wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem); 76 | $display("aluc = %b\npcsource = %b\n",aluc,pcsource); 77 | endtask : check 78 | 79 | initial begin 80 | dc=new(); 81 | repeat(100) begin 82 | req_1(); 83 | check(); 84 | end 85 | repeat(100) begin 86 | req_2(); 87 | check(); 88 | end 89 | end 90 | 91 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/CONTROL_UNIT/CONTROL_UNIT.srcs/sim_1/new/CONTROL_UNIT_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:09:04 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | 32 | module CONTROL_UNIT_TB(); 33 | 34 | class data_creat; 35 | rand bit[5:0] op,func; 36 | rand bit z; 37 | 38 | function void next(); 39 | this.randomize(); 40 | endfunction : next 41 | endclass : data_creat 42 | 43 | bit clk; 44 | bit[5:0] op,func; 45 | bit z; 46 | bit wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem; 47 | bit[3:0] aluc; 48 | bit[1:0] pcsource; 49 | 50 | data_creat dc; 51 | 52 | CLOCK CLOCK1(clk); 53 | CONTROL_UNIT C1(op,func,z,wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem,aluc,pcsource); 54 | 55 | task req_1(); 56 | @(posedge clk); 57 | dc.next(); 58 | op = dc.op; 59 | func = dc.func; 60 | z = dc.z; 61 | endtask : req_1 62 | 63 | task req_2(); 64 | @(posedge clk); 65 | dc.next(); 66 | op = 6'b000000; 67 | func = dc.func; 68 | z = dc.z; 69 | endtask : req_2 70 | 71 | task check(); 72 | @(negedge clk); 73 | $display("op = %b\nfunc = %b\nz = %b",op,func,z); 74 | $display("wreg = %b\nregrt = %b\njal = %b\nm2reg = %b\nshfit = %b\naluimm = %b\nsext = %b\nwmem = %b", 75 | wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem); 76 | $display("aluc = %b\npcsource = %b\n",aluc,pcsource); 77 | endtask : check 78 | 79 | initial begin 80 | dc=new(); 81 | repeat(100) begin 82 | req_1(); 83 | check(); 84 | end 85 | repeat(100) begin 86 | req_2(); 87 | check(); 88 | end 89 | end 90 | 91 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/CONTROL_UNIT/CONTROL_UNIT.srcs/sim_1/new/CONTROL_UNIT_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:09:04 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | 32 | module CONTROL_UNIT_TB(); 33 | 34 | class data_creat; 35 | rand bit[5:0] op,func; 36 | rand bit z; 37 | 38 | function void next(); 39 | this.randomize(); 40 | endfunction : next 41 | endclass : data_creat 42 | 43 | bit clk; 44 | bit[5:0] op,func; 45 | bit z; 46 | bit wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem; 47 | bit[3:0] aluc; 48 | bit[1:0] pcsource; 49 | 50 | data_creat dc; 51 | 52 | CLOCK CLOCK1(clk); 53 | CONTROL_UNIT C1(op,func,z,wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem,aluc,pcsource); 54 | 55 | task req_1(); 56 | @(posedge clk); 57 | dc.next(); 58 | op = dc.op; 59 | func = dc.func; 60 | z = dc.z; 61 | endtask : req_1 62 | 63 | task req_2(); 64 | @(posedge clk); 65 | dc.next(); 66 | op = 6'b000000; 67 | func = dc.func; 68 | z = dc.z; 69 | endtask : req_2 70 | 71 | task check(); 72 | @(negedge clk); 73 | $display("op = %b\nfunc = %b\nz = %b",op,func,z); 74 | $display("wreg = %b\nregrt = %b\njal = %b\nm2reg = %b\nshfit = %b\naluimm = %b\nsext = %b\nwmem = %b", 75 | wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem); 76 | $display("aluc = %b\npcsource = %b\n",aluc,pcsource); 77 | endtask : check 78 | 79 | initial begin 80 | dc=new(); 81 | repeat(100) begin 82 | req_1(); 83 | check(); 84 | end 85 | repeat(100) begin 86 | req_2(); 87 | check(); 88 | end 89 | end 90 | 91 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/REGFILE/REGFILE.srcs/sim_1/new/REGFILE_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 12:59:16 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module REGFILE_TB(); 32 | 33 | class data_creat; 34 | bit clrn; 35 | rand bit we; 36 | rand bit[4:0] wn,rna,rnb; 37 | rand bit[31:0] d; 38 | 39 | function new(); 40 | clrn=1'b1; 41 | endfunction : new 42 | 43 | function void next(); 44 | this.randomize(); 45 | endfunction : next 46 | 47 | function void clear(); 48 | clrn=1'b0; 49 | endfunction : clear 50 | 51 | endclass : data_creat 52 | 53 | bit clk,clrn; 54 | bit we; 55 | bit[4:0] wn,rna,rnb; 56 | bit[31:0] d,qa,qb; 57 | 58 | data_creat dc; 59 | CLOCK CLOCK1(clk); 60 | REGFILE REGFILE1(clk,clrn,d,we,wn,rna,rnb,qa,qb); 61 | 62 | task showreg32(); 63 | @(posedge clk); 64 | rna=4'b0; 65 | $display("clrn = %b",clrn); 66 | for (int i=0;i<32;i=i+1) begin 67 | @(posedge clk); 68 | @(posedge clk); 69 | $display("reg32[%d] = %b",rna,qa); 70 | rna=rna+1; 71 | end 72 | $display("\n"); 73 | endtask : showreg32 74 | 75 | task work(); 76 | @(posedge clk); 77 | dc.next(); 78 | clrn=dc.clrn; 79 | we<=dc.we; 80 | wn=dc.wn; 81 | rna=dc.rna; 82 | rnb=dc.rnb; 83 | d=dc.d; 84 | @(posedge clk); 85 | @(posedge clk); 86 | $display("we = %b\nwn = %d\nd = %b\nrna = %d\nrnb = %d\nqa = %b\nqb = %b",we,wn,d,rna,rnb,qa,qb); 87 | showreg32(); 88 | endtask : work 89 | 90 | task clear(); 91 | dc.clear(); 92 | clrn=dc.clrn; 93 | showreg32(); 94 | endtask : clear 95 | 96 | initial begin 97 | dc=new(); 98 | repeat(50) 99 | work(); 100 | clear(); 101 | end 102 | 103 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/REGFILE/REGFILE.srcs/sim_1/new/REGFILE_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 12:59:16 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module REGFILE_TB(); 32 | 33 | class data_creat; 34 | bit clrn; 35 | rand bit we; 36 | rand bit[4:0] wn,rna,rnb; 37 | rand bit[31:0] d; 38 | 39 | function new(); 40 | clrn=1'b1; 41 | endfunction : new 42 | 43 | function void next(); 44 | this.randomize(); 45 | endfunction : next 46 | 47 | function void clear(); 48 | clrn=1'b0; 49 | endfunction : clear 50 | 51 | endclass : data_creat 52 | 53 | bit clk,clrn; 54 | bit we; 55 | bit[4:0] wn,rna,rnb; 56 | bit[31:0] d,qa,qb; 57 | 58 | data_creat dc; 59 | CLOCK CLOCK1(clk); 60 | REGFILE REGFILE1(clk,clrn,d,we,wn,rna,rnb,qa,qb); 61 | 62 | task showreg32(); 63 | @(posedge clk); 64 | rna=4'b0; 65 | $display("clrn = %b",clrn); 66 | for (int i=0;i<32;i=i+1) begin 67 | @(posedge clk); 68 | @(posedge clk); 69 | $display("reg32[%d] = %b",rna,qa); 70 | rna=rna+1; 71 | end 72 | $display("\n"); 73 | endtask : showreg32 74 | 75 | task work(); 76 | @(posedge clk); 77 | dc.next(); 78 | clrn=dc.clrn; 79 | we<=dc.we; 80 | wn=dc.wn; 81 | rna=dc.rna; 82 | rnb=dc.rnb; 83 | d=dc.d; 84 | @(posedge clk); 85 | @(posedge clk); 86 | $display("we = %b\nwn = %d\nd = %b\nrna = %d\nrnb = %d\nqa = %b\nqb = %b",we,wn,d,rna,rnb,qa,qb); 87 | showreg32(); 88 | endtask : work 89 | 90 | task clear(); 91 | dc.clear(); 92 | clrn=dc.clrn; 93 | showreg32(); 94 | endtask : clear 95 | 96 | initial begin 97 | dc=new(); 98 | repeat(50) 99 | work(); 100 | clear(); 101 | end 102 | 103 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/REGFILE/REGFILE.srcs/sim_1/new/REGFILE_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 12:59:16 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module REGFILE_TB(); 32 | 33 | class data_creat; 34 | bit clrn; 35 | rand bit we; 36 | rand bit[4:0] wn,rna,rnb; 37 | rand bit[31:0] d; 38 | 39 | function new(); 40 | clrn=1'b1; 41 | endfunction : new 42 | 43 | function void next(); 44 | this.randomize(); 45 | endfunction : next 46 | 47 | function void clear(); 48 | clrn=1'b0; 49 | endfunction : clear 50 | 51 | endclass : data_creat 52 | 53 | bit clk,clrn; 54 | bit we; 55 | bit[4:0] wn,rna,rnb; 56 | bit[31:0] d,qa,qb; 57 | 58 | data_creat dc; 59 | CLOCK CLOCK1(clk); 60 | REGFILE REGFILE1(clk,clrn,d,we,wn,rna,rnb,qa,qb); 61 | 62 | task showreg32(); 63 | @(posedge clk); 64 | rna=4'b0; 65 | $display("clrn = %b",clrn); 66 | for (int i=0;i<32;i=i+1) begin 67 | @(posedge clk); 68 | @(posedge clk); 69 | $display("reg32[%d] = %b",rna,qa); 70 | rna=rna+1; 71 | end 72 | $display("\n"); 73 | endtask : showreg32 74 | 75 | task work(); 76 | @(posedge clk); 77 | dc.next(); 78 | clrn=dc.clrn; 79 | we<=dc.we; 80 | wn=dc.wn; 81 | rna=dc.rna; 82 | rnb=dc.rnb; 83 | d=dc.d; 84 | @(posedge clk); 85 | @(posedge clk); 86 | $display("we = %b\nwn = %d\nd = %b\nrna = %d\nrnb = %d\nqa = %b\nqb = %b",we,wn,d,rna,rnb,qa,qb); 87 | showreg32(); 88 | endtask : work 89 | 90 | task clear(); 91 | dc.clear(); 92 | clrn=dc.clrn; 93 | showreg32(); 94 | endtask : clear 95 | 96 | initial begin 97 | dc=new(); 98 | repeat(50) 99 | work(); 100 | clear(); 101 | end 102 | 103 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/REGFILE/REGFILE.srcs/sim_1/new/REGFILE_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 12:59:16 7 | // Design Name: REGFILE 8 | // Module Name: REGFILE_TB 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module REGFILE_TB(); 32 | 33 | class data_creat; 34 | bit clrn; 35 | rand bit we; 36 | rand bit[4:0] wn,rna,rnb; 37 | rand bit[31:0] d; 38 | 39 | function new(); 40 | clrn=1'b1; 41 | endfunction : new 42 | 43 | function void next(); 44 | this.randomize(); 45 | endfunction : next 46 | 47 | function void clear(); 48 | clrn=1'b0; 49 | endfunction : clear 50 | 51 | endclass : data_creat 52 | 53 | bit clk,clrn; 54 | bit we; 55 | bit[4:0] wn,rna,rnb; 56 | bit[31:0] d,qa,qb; 57 | 58 | data_creat dc; 59 | CLOCK CLOCK1(clk); 60 | REGFILE REGFILE1(clk,clrn,d,we,wn,rna,rnb,qa,qb); 61 | 62 | task showreg32(); 63 | @(posedge clk); 64 | rna=4'b0; 65 | $display("clrn = %b",clrn); 66 | for (int i=0;i<32;i=i+1) begin 67 | @(posedge clk); 68 | @(posedge clk); 69 | $display("reg32[%d] = %b",rna,qa); 70 | rna=rna+1; 71 | end 72 | $display("\n"); 73 | endtask : showreg32 74 | 75 | task work(); 76 | @(posedge clk); 77 | dc.next(); 78 | clrn=dc.clrn; 79 | we<=dc.we; 80 | wn=dc.wn; 81 | rna=dc.rna; 82 | rnb=dc.rnb; 83 | d=dc.d; 84 | @(posedge clk); 85 | @(posedge clk); 86 | $display("we = %b\nwn = %d\nd = %b\nrna = %d\nrnb = %d\nqa = %b\nqb = %b",we,wn,d,rna,rnb,qa,qb); 87 | showreg32(); 88 | endtask : work 89 | 90 | task clear(); 91 | dc.clear(); 92 | clrn=dc.clrn; 93 | showreg32(); 94 | endtask : clear 95 | 96 | initial begin 97 | dc=new(); 98 | repeat(50) 99 | work(); 100 | clear(); 101 | end 102 | 103 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/KEY2INST/KEY2INST.srcs/sim_1/new/KEY2INST_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: KEY2INST 8 | // Module Name: KEY2INST_TB 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module KEY2INST_TB(); 32 | bit clk,rst_n; 33 | bit run,load; 34 | bit[2:0] cmd; 35 | bit[1:0] select; 36 | bit[7:0] data; 37 | bit[31:0] inst_a,inst_do; 38 | bit[15:0] button; 39 | bit clrn; 40 | 41 | //ah,al,bh,bl 42 | bit[7:0] data_now[3:0]; 43 | 44 | CLOCK CLOCK1(clk); 45 | KEY2INST KEY2INST1(clk,button,inst_a,inst_do,clrn); 46 | 47 | function data_creat(); 48 | for (int i = 0; i < 4; i++) begin 49 | data_now[i] = $urandom_range(0,8'hff); 50 | end 51 | endfunction : data_creat 52 | 53 | function button_action(bit[1:0] select_now); 54 | button = {rst_n,run,load,cmd,select,data_now[select_now]}; 55 | endfunction : button_action 56 | 57 | task data_load(bit[1:0] select_now); 58 | @(posedge clk) 59 | select = select_now; 60 | button_action(select_now); 61 | @(posedge clk) 62 | load = 1'b1; 63 | button_action(select_now); 64 | @(posedge clk) 65 | load = 1'b0; 66 | button_action(select_now); 67 | endtask : data_load 68 | 69 | task check(); 70 | $display("cmd = %b",cmd); 71 | $display("data_a = %b",{data_now[0],data_now[1]}); 72 | $display("data_b = %b",{data_now[2],data_now[3]}); 73 | for (int i = 0; i < 4; i++) begin 74 | @(posedge clk) 75 | inst_a = i <<2; 76 | @(negedge clk) 77 | $display("inst_do[%d] = %b\n",i,inst_do); 78 | end 79 | endtask : check 80 | 81 | initial begin 82 | rst_n = 1'b0; 83 | run = 1'b0; 84 | load = 1'b0; 85 | repeat(10) @(posedge clk); 86 | rst_n = 1'b1; 87 | for (int i = 0; i < 8; i++) begin 88 | data_creat(); 89 | for (int j = 0; j < 4; j++) begin 90 | data_load(j); 91 | end 92 | @(posedge clk) 93 | cmd = i; 94 | run = 1'b1; 95 | button_action(0); 96 | @(posedge clk) 97 | run = 1'b0; 98 | check(); 99 | end 100 | @(posedge clk) 101 | rst_n = 1'b0; 102 | check(); 103 | end 104 | 105 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/KEY2INST/KEY2INST.srcs/sim_1/new/KEY2INST_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: KEY2INST 8 | // Module Name: KEY2INST_TB 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module KEY2INST_TB(); 32 | bit clk,rst_n; 33 | bit run,load; 34 | bit[2:0] cmd; 35 | bit[1:0] select; 36 | bit[7:0] data; 37 | bit[31:0] inst_a,inst_do; 38 | bit[15:0] button; 39 | bit clrn; 40 | 41 | //ah,al,bh,bl 42 | bit[7:0] data_now[3:0]; 43 | 44 | CLOCK CLOCK1(clk); 45 | KEY2INST KEY2INST1(clk,button,inst_a,inst_do,clrn); 46 | 47 | function data_creat(); 48 | for (int i = 0; i < 4; i++) begin 49 | data_now[i] = $urandom_range(0,8'hff); 50 | end 51 | endfunction : data_creat 52 | 53 | function button_action(bit[1:0] select_now); 54 | button = {rst_n,run,load,cmd,select,data_now[select_now]}; 55 | endfunction : button_action 56 | 57 | task data_load(bit[1:0] select_now); 58 | @(posedge clk) 59 | select = select_now; 60 | button_action(select_now); 61 | @(posedge clk) 62 | load = 1'b1; 63 | button_action(select_now); 64 | @(posedge clk) 65 | load = 1'b0; 66 | button_action(select_now); 67 | endtask : data_load 68 | 69 | task check(); 70 | $display("cmd = %b",cmd); 71 | $display("data_a = %b",{data_now[0],data_now[1]}); 72 | $display("data_b = %b",{data_now[2],data_now[3]}); 73 | for (int i = 0; i < 4; i++) begin 74 | @(posedge clk) 75 | inst_a = i <<2; 76 | @(negedge clk) 77 | $display("inst_do[%d] = %b\n",i,inst_do); 78 | end 79 | endtask : check 80 | 81 | initial begin 82 | rst_n = 1'b0; 83 | run = 1'b0; 84 | load = 1'b0; 85 | repeat(10) @(posedge clk); 86 | rst_n = 1'b1; 87 | for (int i = 0; i < 8; i++) begin 88 | data_creat(); 89 | for (int j = 0; j < 4; j++) begin 90 | data_load(j); 91 | end 92 | @(posedge clk) 93 | cmd = i; 94 | run = 1'b1; 95 | button_action(0); 96 | @(posedge clk) 97 | run = 1'b0; 98 | check(); 99 | end 100 | @(posedge clk) 101 | rst_n = 1'b0; 102 | check(); 103 | end 104 | 105 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/KEY2INST/KEY2INST.srcs/sim_1/new/KEY2INST_TB.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: KEY2INST 8 | // Module Name: KEY2INST_TB 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CLOCK ( 22 | output bit clk 23 | ); 24 | 25 | always #(100ps) begin 26 | clk = ~clk; 27 | end 28 | 29 | endmodule 30 | 31 | module KEY2INST_TB(); 32 | bit clk,rst_n; 33 | bit run,load; 34 | bit[2:0] cmd; 35 | bit[1:0] select; 36 | bit[7:0] data; 37 | bit[31:0] inst_a,inst_do; 38 | bit[15:0] button; 39 | bit clrn; 40 | 41 | //ah,al,bh,bl 42 | bit[7:0] data_now[3:0]; 43 | 44 | CLOCK CLOCK1(clk); 45 | KEY2INST KEY2INST1(clk,button,inst_a,inst_do,clrn); 46 | 47 | function data_creat(); 48 | for (int i = 0; i < 4; i++) begin 49 | data_now[i] = $urandom_range(0,8'hff); 50 | end 51 | endfunction : data_creat 52 | 53 | function button_action(bit[1:0] select_now); 54 | button = {rst_n,run,load,cmd,select,data_now[select_now]}; 55 | endfunction : button_action 56 | 57 | task data_load(bit[1:0] select_now); 58 | @(posedge clk) 59 | select = select_now; 60 | button_action(select_now); 61 | @(posedge clk) 62 | load = 1'b1; 63 | button_action(select_now); 64 | @(posedge clk) 65 | load = 1'b0; 66 | button_action(select_now); 67 | endtask : data_load 68 | 69 | task check(); 70 | $display("cmd = %b",cmd); 71 | $display("data_a = %b",{data_now[0],data_now[1]}); 72 | $display("data_b = %b",{data_now[2],data_now[3]}); 73 | for (int i = 0; i < 4; i++) begin 74 | @(posedge clk) 75 | inst_a = i <<2; 76 | @(negedge clk) 77 | $display("inst_do[%d] = %b\n",i,inst_do); 78 | end 79 | endtask : check 80 | 81 | initial begin 82 | rst_n = 1'b0; 83 | run = 1'b0; 84 | load = 1'b0; 85 | repeat(10) @(posedge clk); 86 | rst_n = 1'b1; 87 | for (int i = 0; i < 8; i++) begin 88 | data_creat(); 89 | for (int j = 0; j < 4; j++) begin 90 | data_load(j); 91 | end 92 | @(posedge clk) 93 | cmd = i; 94 | run = 1'b1; 95 | button_action(0); 96 | @(posedge clk) 97 | run = 1'b0; 98 | check(); 99 | end 100 | @(posedge clk) 101 | rst_n = 1'b0; 102 | check(); 103 | end 104 | 105 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/MIPS_CPU_clk_wiz_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # file: MIPS_CPU_clk_wiz_0_0_ooc.xdc 2 | # 3 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | ################# 51 | #DEFAULT CLOCK CONSTRAINTS 52 | 53 | ############################################################ 54 | # Clock Period Constraints # 55 | ############################################################ 56 | #create_clock -period 10.0 [get_ports clk_in1] 57 | 58 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/CPU_ON_BOARD.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/MIPS_CPU_clk_wiz_0_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | # file: MIPS_CPU_clk_wiz_0_0_ooc.xdc 2 | # 3 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | ################# 51 | #DEFAULT CLOCK CONSTRAINTS 52 | 53 | ############################################################ 54 | # Clock Period Constraints # 55 | ############################################################ 56 | #create_clock -period 10.0 [get_ports clk_in1] 57 | 58 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_INST_MEM_0_1/sim/MIPS_CPU_INST_MEM_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:INST_MEM:1.1 51 | // IP Revision: 5 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_INST_MEM_0_1 ( 57 | a, 58 | inst_out 59 | ); 60 | 61 | input wire [31 : 0] a; 62 | output wire [31 : 0] inst_out; 63 | 64 | INST_MEM inst ( 65 | .a(a), 66 | .inst_out(inst_out) 67 | ); 68 | endmodule 69 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/MIPS_CPU_clk_wiz_0_0.xdc: -------------------------------------------------------------------------------- 1 | # file: MIPS_CPU_clk_wiz_0_0.xdc 2 | # 3 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system. If required 52 | # commented constraints can be used in the top level xdc 53 | #---------------------------------------------------------------- 54 | # Connect to input port when clock capable pin is selected for input 55 | create_clock -period 10.0 [get_ports clk_in1] 56 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/CPU_ON_BOARD.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/MIPS_CPU_clk_wiz_0_0.xdc: -------------------------------------------------------------------------------- 1 | # file: MIPS_CPU_clk_wiz_0_0.xdc 2 | # 3 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | 50 | # Input clock periods. These duplicate the values entered for the 51 | # input clocks. You can use these to time your system. If required 52 | # commented constraints can be used in the top level xdc 53 | #---------------------------------------------------------------- 54 | # Connect to input port when clock capable pin is selected for input 55 | create_clock -period 10.0 [get_ports clk_in1] 56 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 57 | 58 | 59 | 60 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_INST_MEM_0_1/synth/MIPS_CPU_INST_MEM_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:INST_MEM:1.1 51 | // IP Revision: 5 52 | 53 | (* X_CORE_INFO = "INST_MEM,Vivado 2014.2" *) 54 | (* CHECK_LICENSE_TYPE = "MIPS_CPU_INST_MEM_0_1,INST_MEM,{}" *) 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_INST_MEM_0_1 ( 57 | a, 58 | inst_out 59 | ); 60 | 61 | input wire [31 : 0] a; 62 | output wire [31 : 0] inst_out; 63 | 64 | INST_MEM inst ( 65 | .a(a), 66 | .inst_out(inst_out) 67 | ); 68 | endmodule 69 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_ALU32_0_1/sim/MIPS_CPU_ALU32_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:ALU32:1.0 51 | // IP Revision: 2 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_ALU32_0_1 ( 57 | a, 58 | b, 59 | aluc, 60 | r, 61 | z 62 | ); 63 | 64 | input wire [31 : 0] a; 65 | input wire [31 : 0] b; 66 | input wire [31 : 0] aluc; 67 | output wire [31 : 0] r; 68 | output wire z; 69 | 70 | ALU32 inst ( 71 | .a(a), 72 | .b(b), 73 | .aluc(aluc), 74 | .r(r), 75 | .z(z) 76 | ); 77 | endmodule 78 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_DATA_MEM_0_1/sim/MIPS_CPU_DATA_MEM_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:DATA_MEM:1.0 51 | // IP Revision: 4 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_DATA_MEM_0_1 ( 57 | addr, 58 | data_in, 59 | clk, 60 | we, 61 | data_out 62 | ); 63 | 64 | input wire [31 : 0] addr; 65 | input wire [31 : 0] data_in; 66 | input wire clk; 67 | input wire we; 68 | output wire [31 : 0] data_out; 69 | 70 | DATA_MEM inst ( 71 | .addr(addr), 72 | .data_in(data_in), 73 | .clk(clk), 74 | .we(we), 75 | .data_out(data_out) 76 | ); 77 | endmodule 78 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_INST_MEM_0_1/MIPS_CPU_INST_MEM_0_1.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: dtysky:user:INST_MEM:1.1 50 | // IP Revision: 5 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | MIPS_CPU_INST_MEM_0_1 your_instance_name ( 58 | .a(a), // input wire [31 : 0] a 59 | .inst_out(inst_out) // output wire [31 : 0] inst_out 60 | ); 61 | // INST_TAG_END ------ End INSTANTIATION Template --------- 62 | 63 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_ALU32_0_1/synth/MIPS_CPU_ALU32_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:ALU32:1.0 51 | // IP Revision: 2 52 | 53 | (* X_CORE_INFO = "ALU32,Vivado 2014.2" *) 54 | (* CHECK_LICENSE_TYPE = "MIPS_CPU_ALU32_0_1,ALU32,{}" *) 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_ALU32_0_1 ( 57 | a, 58 | b, 59 | aluc, 60 | r, 61 | z 62 | ); 63 | 64 | input wire [31 : 0] a; 65 | input wire [31 : 0] b; 66 | input wire [31 : 0] aluc; 67 | output wire [31 : 0] r; 68 | output wire z; 69 | 70 | ALU32 inst ( 71 | .a(a), 72 | .b(b), 73 | .aluc(aluc), 74 | .r(r), 75 | .z(z) 76 | ); 77 | endmodule 78 | -------------------------------------------------------------------------------- /SUB_MODULE/DATAPATH/DATAPATH.srcs/sources_1/new/DATAPATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:56:28 7 | // Design Name: DATAPATH 8 | // Module Name: DATAPATH 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATAPATH( 24 | input clk,clrn, 25 | input alu_z, 26 | input[31:0] alu_r, 27 | output[31:0] alu_a,alu_b, 28 | output[31:0] alu_aluc, 29 | output reg_we, 30 | input[31:0] reg_qa,reg_qb, 31 | output[4:0] reg_wn,reg_rna,reg_rnb, 32 | output[31:0] reg_d, 33 | input con_wreg,con_regrt,con_jal,con_m2reg,con_shfit,con_aluimm,con_sext,con_wmem, 34 | input[3:0] con_aluc, 35 | input[1:0] con_pcsource, 36 | output[5:0] con_op,con_func, 37 | output con_z, 38 | input[31:0] inst_do, 39 | output[31:0] inst_a, 40 | input[31:0] data_do, 41 | output[31:0] data_a,data_di, 42 | output data_we, 43 | output[31:0] pc_out 44 | ); 45 | 46 | wire[4:0] rs,rt,rd,sa; 47 | wire signed [31:0] imm; 48 | wire[25:0] addr; 49 | reg[31:0] pc_i,pc_o; 50 | wire[31:0] pc_p4,pc_jump; 51 | wire[4:0] reg_dest; 52 | wire[31:0] imm_ext,reg_data_dest; 53 | 54 | initial begin 55 | pc_i = 32'b0; 56 | end 57 | 58 | assign rs = inst_do[25:21]; 59 | assign rt = inst_do[20:16]; 60 | assign rd = inst_do[15:11]; 61 | assign sa = inst_do[10:6]; 62 | assign imm = {inst_do[15:0],16'b0}; 63 | assign addr = inst_do[25:0]; 64 | assign imm_ext = con_sext ? imm>>>16 : imm>>16; 65 | 66 | assign pc_p4 = pc_o + 4; 67 | assign pc_out = pc_o; 68 | 69 | assign reg_dest = con_regrt ? rt : rd; 70 | assign reg_wn = reg_dest | {5{con_jal}}; 71 | assign reg_data_dest = con_m2reg ? data_do : alu_r; 72 | assign reg_d = con_jal ? pc_p4 : reg_data_dest; 73 | assign reg_rna = rs; 74 | assign reg_rnb = rt; 75 | assign reg_we = con_wreg; 76 | 77 | assign con_op = inst_do[31:26]; 78 | assign con_func = inst_do[5:0]; 79 | assign con_z = alu_z; 80 | 81 | assign alu_a = con_shfit ? {27'b0,sa} : reg_qa; 82 | assign alu_b = con_aluimm ? imm_ext : reg_qb; 83 | assign alu_aluc = {28'b0,con_aluc}; 84 | 85 | assign data_we = con_wmem; 86 | assign data_di = reg_qb; 87 | assign data_a = alu_r; 88 | 89 | assign inst_a = pc_o; 90 | 91 | always @(posedge clk or negedge clrn) begin 92 | if (~clrn) pc_o <= 32'b0; 93 | else pc_o <= pc_i; 94 | end 95 | 96 | ADDSUB32 ADDSUB1(pc_p4,imm_ext<<2,1'b0,pc_jump); 97 | 98 | always @(*) begin 99 | case (con_pcsource) 100 | 2'b00 : pc_i <= pc_p4; 101 | 2'b01 : pc_i <= pc_jump; 102 | 2'b10 : pc_i <= reg_qa; 103 | 2'b11 : pc_i <= {pc_p4[31:28],addr,2'b0}; 104 | default : /* default */; 105 | endcase 106 | end 107 | 108 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/DATAPATH/DATAPATH.srcs/sources_1/new/DATAPATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:56:28 7 | // Design Name: DATAPATH 8 | // Module Name: DATAPATH 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATAPATH( 24 | input clk,clrn, 25 | input alu_z, 26 | input[31:0] alu_r, 27 | output[31:0] alu_a,alu_b, 28 | output[31:0] alu_aluc, 29 | output reg_we, 30 | input[31:0] reg_qa,reg_qb, 31 | output[4:0] reg_wn,reg_rna,reg_rnb, 32 | output[31:0] reg_d, 33 | input con_wreg,con_regrt,con_jal,con_m2reg,con_shfit,con_aluimm,con_sext,con_wmem, 34 | input[3:0] con_aluc, 35 | input[1:0] con_pcsource, 36 | output[5:0] con_op,con_func, 37 | output con_z, 38 | input[31:0] inst_do, 39 | output[31:0] inst_a, 40 | input[31:0] data_do, 41 | output[31:0] data_a,data_di, 42 | output data_we, 43 | output[31:0] pc_out 44 | ); 45 | 46 | wire[4:0] rs,rt,rd,sa; 47 | wire signed [31:0] imm; 48 | wire[25:0] addr; 49 | reg[31:0] pc_i,pc_o; 50 | wire[31:0] pc_p4,pc_jump; 51 | wire[4:0] reg_dest; 52 | wire[31:0] imm_ext,reg_data_dest; 53 | 54 | initial begin 55 | pc_i = 32'b0; 56 | end 57 | 58 | assign rs = inst_do[25:21]; 59 | assign rt = inst_do[20:16]; 60 | assign rd = inst_do[15:11]; 61 | assign sa = inst_do[10:6]; 62 | assign imm = {inst_do[15:0],16'b0}; 63 | assign addr = inst_do[25:0]; 64 | assign imm_ext = con_sext ? imm>>>16 : imm>>16; 65 | 66 | assign pc_p4 = pc_o + 4; 67 | assign pc_out = pc_o; 68 | 69 | assign reg_dest = con_regrt ? rt : rd; 70 | assign reg_wn = reg_dest | {5{con_jal}}; 71 | assign reg_data_dest = con_m2reg ? data_do : alu_r; 72 | assign reg_d = con_jal ? pc_p4 : reg_data_dest; 73 | assign reg_rna = rs; 74 | assign reg_rnb = rt; 75 | assign reg_we = con_wreg; 76 | 77 | assign con_op = inst_do[31:26]; 78 | assign con_func = inst_do[5:0]; 79 | assign con_z = alu_z; 80 | 81 | assign alu_a = con_shfit ? {27'b0,sa} : reg_qa; 82 | assign alu_b = con_aluimm ? imm_ext : reg_qb; 83 | assign alu_aluc = {28'b0,con_aluc}; 84 | 85 | assign data_we = con_wmem; 86 | assign data_di = reg_qb; 87 | assign data_a = alu_r; 88 | 89 | assign inst_a = pc_o; 90 | 91 | always @(posedge clk or negedge clrn) begin 92 | if (~clrn) pc_o <= 32'b0; 93 | else pc_o <= pc_i; 94 | end 95 | 96 | ADDSUB32 ADDSUB1(pc_p4,imm_ext<<2,1'b0,pc_jump); 97 | 98 | always @(*) begin 99 | case (con_pcsource) 100 | 2'b00 : pc_i <= pc_p4; 101 | 2'b01 : pc_i <= pc_jump; 102 | 2'b10 : pc_i <= reg_qa; 103 | 2'b11 : pc_i <= {pc_p4[31:28],addr,2'b0}; 104 | default : /* default */; 105 | endcase 106 | end 107 | 108 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/DATAPATH/DATAPATH.srcs/sources_1/new/DATAPATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:56:28 7 | // Design Name: DATAPATH 8 | // Module Name: DATAPATH 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATAPATH( 24 | input clk,clrn, 25 | input alu_z, 26 | input[31:0] alu_r, 27 | output[31:0] alu_a,alu_b, 28 | output[31:0] alu_aluc, 29 | output reg_we, 30 | input[31:0] reg_qa,reg_qb, 31 | output[4:0] reg_wn,reg_rna,reg_rnb, 32 | output[31:0] reg_d, 33 | input con_wreg,con_regrt,con_jal,con_m2reg,con_shfit,con_aluimm,con_sext,con_wmem, 34 | input[3:0] con_aluc, 35 | input[1:0] con_pcsource, 36 | output[5:0] con_op,con_func, 37 | output con_z, 38 | input[31:0] inst_do, 39 | output[31:0] inst_a, 40 | input[31:0] data_do, 41 | output[31:0] data_a,data_di, 42 | output data_we, 43 | output[31:0] pc_out 44 | ); 45 | 46 | wire[4:0] rs,rt,rd,sa; 47 | wire signed [31:0] imm; 48 | wire[25:0] addr; 49 | reg[31:0] pc_i,pc_o; 50 | wire[31:0] pc_p4,pc_jump; 51 | wire[4:0] reg_dest; 52 | wire[31:0] imm_ext,reg_data_dest; 53 | 54 | initial begin 55 | pc_i = 32'b0; 56 | end 57 | 58 | assign rs = inst_do[25:21]; 59 | assign rt = inst_do[20:16]; 60 | assign rd = inst_do[15:11]; 61 | assign sa = inst_do[10:6]; 62 | assign imm = {inst_do[15:0],16'b0}; 63 | assign addr = inst_do[25:0]; 64 | assign imm_ext = con_sext ? imm>>>16 : imm>>16; 65 | 66 | assign pc_p4 = pc_o + 4; 67 | assign pc_out = pc_o; 68 | 69 | assign reg_dest = con_regrt ? rt : rd; 70 | assign reg_wn = reg_dest | {5{con_jal}}; 71 | assign reg_data_dest = con_m2reg ? data_do : alu_r; 72 | assign reg_d = con_jal ? pc_p4 : reg_data_dest; 73 | assign reg_rna = rs; 74 | assign reg_rnb = rt; 75 | assign reg_we = con_wreg; 76 | 77 | assign con_op = inst_do[31:26]; 78 | assign con_func = inst_do[5:0]; 79 | assign con_z = alu_z; 80 | 81 | assign alu_a = con_shfit ? {27'b0,sa} : reg_qa; 82 | assign alu_b = con_aluimm ? imm_ext : reg_qb; 83 | assign alu_aluc = {28'b0,con_aluc}; 84 | 85 | assign data_we = con_wmem; 86 | assign data_di = reg_qb; 87 | assign data_a = alu_r; 88 | 89 | assign inst_a = pc_o; 90 | 91 | always @(posedge clk or negedge clrn) begin 92 | if (~clrn) pc_o <= 32'b0; 93 | else pc_o <= pc_i; 94 | end 95 | 96 | ADDSUB32 ADDSUB1(pc_p4,imm_ext<<2,1'b0,pc_jump); 97 | 98 | always @(*) begin 99 | case (con_pcsource) 100 | 2'b00 : pc_i <= pc_p4; 101 | 2'b01 : pc_i <= pc_jump; 102 | 2'b10 : pc_i <= reg_qa; 103 | 2'b11 : pc_i <= {pc_p4[31:28],addr,2'b0}; 104 | default : /* default */; 105 | endcase 106 | end 107 | 108 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/DATAPATH/DATAPATH.srcs/sources_1/new/DATAPATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 16:56:28 7 | // Design Name: DATAPATH 8 | // Module Name: DATAPATH 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module DATAPATH( 24 | input clk,clrn, 25 | input alu_z, 26 | input[31:0] alu_r, 27 | output[31:0] alu_a,alu_b, 28 | output[31:0] alu_aluc, 29 | output reg_we, 30 | input[31:0] reg_qa,reg_qb, 31 | output[4:0] reg_wn,reg_rna,reg_rnb, 32 | output[31:0] reg_d, 33 | input con_wreg,con_regrt,con_jal,con_m2reg,con_shfit,con_aluimm,con_sext,con_wmem, 34 | input[3:0] con_aluc, 35 | input[1:0] con_pcsource, 36 | output[5:0] con_op,con_func, 37 | output con_z, 38 | input[31:0] inst_do, 39 | output[31:0] inst_a, 40 | input[31:0] data_do, 41 | output[31:0] data_a,data_di, 42 | output data_we, 43 | output[31:0] pc_out 44 | ); 45 | 46 | wire[4:0] rs,rt,rd,sa; 47 | wire signed [31:0] imm; 48 | wire[25:0] addr; 49 | reg[31:0] pc_i,pc_o; 50 | wire[31:0] pc_p4,pc_jump; 51 | wire[4:0] reg_dest; 52 | wire[31:0] imm_ext,reg_data_dest; 53 | 54 | initial begin 55 | pc_i = 32'b0; 56 | end 57 | 58 | assign rs = inst_do[25:21]; 59 | assign rt = inst_do[20:16]; 60 | assign rd = inst_do[15:11]; 61 | assign sa = inst_do[10:6]; 62 | assign imm = {inst_do[15:0],16'b0}; 63 | assign addr = inst_do[25:0]; 64 | assign imm_ext = con_sext ? imm>>>16 : imm>>16; 65 | 66 | assign pc_p4 = pc_o + 4; 67 | assign pc_out = pc_o; 68 | 69 | assign reg_dest = con_regrt ? rt : rd; 70 | assign reg_wn = reg_dest | {5{con_jal}}; 71 | assign reg_data_dest = con_m2reg ? data_do : alu_r; 72 | assign reg_d = con_jal ? pc_p4 : reg_data_dest; 73 | assign reg_rna = rs; 74 | assign reg_rnb = rt; 75 | assign reg_we = con_wreg; 76 | 77 | assign con_op = inst_do[31:26]; 78 | assign con_func = inst_do[5:0]; 79 | assign con_z = alu_z; 80 | 81 | assign alu_a = con_shfit ? {27'b0,sa} : reg_qa; 82 | assign alu_b = con_aluimm ? imm_ext : reg_qb; 83 | assign alu_aluc = {28'b0,con_aluc}; 84 | 85 | assign data_we = con_wmem; 86 | assign data_di = reg_qb; 87 | assign data_a = alu_r; 88 | 89 | assign inst_a = pc_o; 90 | 91 | always @(posedge clk or negedge clrn) begin 92 | if (~clrn) pc_o <= 32'b0; 93 | else pc_o <= pc_i; 94 | end 95 | 96 | ADDSUB32 ADDSUB1(pc_p4,imm_ext<<2,1'b0,pc_jump); 97 | 98 | always @(*) begin 99 | case (con_pcsource) 100 | 2'b00 : pc_i <= pc_p4; 101 | 2'b01 : pc_i <= pc_jump; 102 | 2'b10 : pc_i <= reg_qa; 103 | 2'b11 : pc_i <= {pc_p4[31:28],addr,2'b0}; 104 | default : /* default */; 105 | endcase 106 | end 107 | 108 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/CONTROL_UNIT/CONTROL_UNIT.srcs/sources_1/new/CONTROL_UNIT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 15:20:50 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CONTROL_UNIT( 22 | input[5:0] op,func, 23 | input z, 24 | output wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem, 25 | output[3:0] aluc, 26 | output[1:0] pcsource 27 | ); 28 | 29 | parameter cmd_add = 6'b100000; 30 | parameter cmd_sub = 6'b100010; 31 | parameter cmd_and = 6'b100100; 32 | parameter cmd_or = 6'b100101; 33 | parameter cmd_xor = 6'b100110; 34 | parameter cmd_sll = 6'b000000; 35 | parameter cmd_srl = 6'b000010; 36 | parameter cmd_sra = 6'b000011; 37 | parameter cmd_jr = 6'b001000; 38 | parameter cmd_addi = 6'b001000; 39 | parameter cmd_andi = 6'b001100; 40 | parameter cmd_ori = 6'b001101; 41 | parameter cmd_xori = 6'b001110; 42 | parameter cmd_lw = 6'b100011; 43 | parameter cmd_sw = 6'b101011; 44 | parameter cmd_beq = 6'b000100; 45 | parameter cmd_bne = 6'b000101; 46 | parameter cmd_lui = 6'b001111; 47 | parameter cmd_j = 6'b000010; 48 | parameter cmd_jal = 6'b000011; 49 | 50 | 51 | reg[13:0] cmd_out; 52 | 53 | always @(*) begin 54 | case (op) 55 | 6'b0 : begin 56 | case (func) 57 | cmd_add : cmd_out <= 14'b10000000000000; 58 | cmd_sub : cmd_out <= 14'b10000000100000; 59 | cmd_and : cmd_out <= 14'b10000000001000; 60 | cmd_or : cmd_out <= 14'b10000000101000; 61 | cmd_xor : cmd_out <= 14'b10000000010000; 62 | cmd_sll : cmd_out <= 14'b10001000011000; 63 | cmd_srl : cmd_out <= 14'b10001000111000; 64 | cmd_sra : cmd_out <= 14'b10001001111000; 65 | cmd_jr : cmd_out <= 14'b00000000000010; 66 | default : cmd_out <= 14'b00000000000000; 67 | endcase 68 | end 69 | cmd_addi : cmd_out <= 14'b11000110000000; 70 | cmd_andi : cmd_out <= 14'b11000100001000; 71 | cmd_ori : cmd_out <= 14'b11000100101000; 72 | cmd_xori : cmd_out <= 14'b11000100010000; 73 | cmd_lw : cmd_out <= 14'b11010110000000; 74 | cmd_sw : cmd_out <= 14'b00000110000100; 75 | cmd_beq : cmd_out <= {13'b0000001001000,z}; 76 | cmd_bne : cmd_out <= {13'b0000001001000,~z}; 77 | cmd_lui : cmd_out <= 14'b11000100110000; 78 | cmd_j : cmd_out <= 14'b00000000000011; 79 | cmd_jal : cmd_out <= 14'b10100000000011; 80 | default : cmd_out <= 14'b00000000000000; 81 | endcase 82 | end 83 | 84 | assign wreg = cmd_out[13]; 85 | assign regrt = cmd_out[12]; 86 | assign jal = cmd_out[11]; 87 | assign m2reg = cmd_out[10]; 88 | assign shfit = cmd_out[9]; 89 | assign aluimm = cmd_out[8]; 90 | assign sext = cmd_out[7]; 91 | assign aluc = cmd_out[6:3]; 92 | assign wmem = cmd_out[2]; 93 | assign pcsource = cmd_out[1:0]; 94 | 95 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_ALU32_0_1/MIPS_CPU_ALU32_0_1.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | MIPS_CPU_ALU32_0_1 10 | 11 | 12 | MIPS_CPU_ALU32_0_1 13 | artix7 14 | xc7a35t 15 | cpg236 16 | -1 17 | VERILOG 18 | MIXED 19 | TRUE 20 | TRUE 21 | d:/Spira_Heaven/0-MyWorks/MIPS_CPU/CPU_FOR_SIM 22 | 23 | TRUE 24 | 2014.2 25 | 2 26 | OUT_OF_CONTEXT 27 | . 28 | ../../../../ipshared 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/CONTROL_UNIT/CONTROL_UNIT.srcs/sources_1/new/CONTROL_UNIT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 15:20:50 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CONTROL_UNIT( 22 | input[5:0] op,func, 23 | input z, 24 | output wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem, 25 | output[3:0] aluc, 26 | output[1:0] pcsource 27 | ); 28 | 29 | parameter cmd_add = 6'b100000; 30 | parameter cmd_sub = 6'b100010; 31 | parameter cmd_and = 6'b100100; 32 | parameter cmd_or = 6'b100101; 33 | parameter cmd_xor = 6'b100110; 34 | parameter cmd_sll = 6'b000000; 35 | parameter cmd_srl = 6'b000010; 36 | parameter cmd_sra = 6'b000011; 37 | parameter cmd_jr = 6'b001000; 38 | parameter cmd_addi = 6'b001000; 39 | parameter cmd_andi = 6'b001100; 40 | parameter cmd_ori = 6'b001101; 41 | parameter cmd_xori = 6'b001110; 42 | parameter cmd_lw = 6'b100011; 43 | parameter cmd_sw = 6'b101011; 44 | parameter cmd_beq = 6'b000100; 45 | parameter cmd_bne = 6'b000101; 46 | parameter cmd_lui = 6'b001111; 47 | parameter cmd_j = 6'b000010; 48 | parameter cmd_jal = 6'b000011; 49 | 50 | 51 | reg[13:0] cmd_out; 52 | 53 | always @(*) begin 54 | case (op) 55 | 6'b0 : begin 56 | case (func) 57 | cmd_add : cmd_out <= 14'b10000000000000; 58 | cmd_sub : cmd_out <= 14'b10000000100000; 59 | cmd_and : cmd_out <= 14'b10000000001000; 60 | cmd_or : cmd_out <= 14'b10000000101000; 61 | cmd_xor : cmd_out <= 14'b10000000010000; 62 | cmd_sll : cmd_out <= 14'b10001000011000; 63 | cmd_srl : cmd_out <= 14'b10001000111000; 64 | cmd_sra : cmd_out <= 14'b10001001111000; 65 | cmd_jr : cmd_out <= 14'b00000000000010; 66 | default : cmd_out <= 14'b00000000000000; 67 | endcase 68 | end 69 | cmd_addi : cmd_out <= 14'b11000110000000; 70 | cmd_andi : cmd_out <= 14'b11000100001000; 71 | cmd_ori : cmd_out <= 14'b11000100101000; 72 | cmd_xori : cmd_out <= 14'b11000100010000; 73 | cmd_lw : cmd_out <= 14'b11010110000000; 74 | cmd_sw : cmd_out <= 14'b00000110000100; 75 | cmd_beq : cmd_out <= {13'b0000001001000,z}; 76 | cmd_bne : cmd_out <= {13'b0000001001000,~z}; 77 | cmd_lui : cmd_out <= 14'b11000100110000; 78 | cmd_j : cmd_out <= 14'b00000000000011; 79 | cmd_jal : cmd_out <= 14'b10100000000011; 80 | default : cmd_out <= 14'b00000000000000; 81 | endcase 82 | end 83 | 84 | assign wreg = cmd_out[13]; 85 | assign regrt = cmd_out[12]; 86 | assign jal = cmd_out[11]; 87 | assign m2reg = cmd_out[10]; 88 | assign shfit = cmd_out[9]; 89 | assign aluimm = cmd_out[8]; 90 | assign sext = cmd_out[7]; 91 | assign aluc = cmd_out[6:3]; 92 | assign wmem = cmd_out[2]; 93 | assign pcsource = cmd_out[1:0]; 94 | 95 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/CONTROL_UNIT/CONTROL_UNIT.srcs/sources_1/new/CONTROL_UNIT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 15:20:50 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CONTROL_UNIT( 22 | input[5:0] op,func, 23 | input z, 24 | output wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem, 25 | output[3:0] aluc, 26 | output[1:0] pcsource 27 | ); 28 | 29 | parameter cmd_add = 6'b100000; 30 | parameter cmd_sub = 6'b100010; 31 | parameter cmd_and = 6'b100100; 32 | parameter cmd_or = 6'b100101; 33 | parameter cmd_xor = 6'b100110; 34 | parameter cmd_sll = 6'b000000; 35 | parameter cmd_srl = 6'b000010; 36 | parameter cmd_sra = 6'b000011; 37 | parameter cmd_jr = 6'b001000; 38 | parameter cmd_addi = 6'b001000; 39 | parameter cmd_andi = 6'b001100; 40 | parameter cmd_ori = 6'b001101; 41 | parameter cmd_xori = 6'b001110; 42 | parameter cmd_lw = 6'b100011; 43 | parameter cmd_sw = 6'b101011; 44 | parameter cmd_beq = 6'b000100; 45 | parameter cmd_bne = 6'b000101; 46 | parameter cmd_lui = 6'b001111; 47 | parameter cmd_j = 6'b000010; 48 | parameter cmd_jal = 6'b000011; 49 | 50 | 51 | reg[13:0] cmd_out; 52 | 53 | always @(*) begin 54 | case (op) 55 | 6'b0 : begin 56 | case (func) 57 | cmd_add : cmd_out <= 14'b10000000000000; 58 | cmd_sub : cmd_out <= 14'b10000000100000; 59 | cmd_and : cmd_out <= 14'b10000000001000; 60 | cmd_or : cmd_out <= 14'b10000000101000; 61 | cmd_xor : cmd_out <= 14'b10000000010000; 62 | cmd_sll : cmd_out <= 14'b10001000011000; 63 | cmd_srl : cmd_out <= 14'b10001000111000; 64 | cmd_sra : cmd_out <= 14'b10001001111000; 65 | cmd_jr : cmd_out <= 14'b00000000000010; 66 | default : cmd_out <= 14'b00000000000000; 67 | endcase 68 | end 69 | cmd_addi : cmd_out <= 14'b11000110000000; 70 | cmd_andi : cmd_out <= 14'b11000100001000; 71 | cmd_ori : cmd_out <= 14'b11000100101000; 72 | cmd_xori : cmd_out <= 14'b11000100010000; 73 | cmd_lw : cmd_out <= 14'b11010110000000; 74 | cmd_sw : cmd_out <= 14'b00000110000100; 75 | cmd_beq : cmd_out <= {13'b0000001001000,z}; 76 | cmd_bne : cmd_out <= {13'b0000001001000,~z}; 77 | cmd_lui : cmd_out <= 14'b11000100110000; 78 | cmd_j : cmd_out <= 14'b00000000000011; 79 | cmd_jal : cmd_out <= 14'b10100000000011; 80 | default : cmd_out <= 14'b00000000000000; 81 | endcase 82 | end 83 | 84 | assign wreg = cmd_out[13]; 85 | assign regrt = cmd_out[12]; 86 | assign jal = cmd_out[11]; 87 | assign m2reg = cmd_out[10]; 88 | assign shfit = cmd_out[9]; 89 | assign aluimm = cmd_out[8]; 90 | assign sext = cmd_out[7]; 91 | assign aluc = cmd_out[6:3]; 92 | assign wmem = cmd_out[2]; 93 | assign pcsource = cmd_out[1:0]; 94 | 95 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/CONTROL_UNIT/CONTROL_UNIT.srcs/sources_1/new/CONTROL_UNIT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/18 15:20:50 7 | // Design Name: CONTROL_UNIT 8 | // Module Name: CONTROL_UNIT 9 | // Project Name: MISP_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CONTROL_UNIT( 22 | input[5:0] op,func, 23 | input z, 24 | output wreg,regrt,jal,m2reg,shfit,aluimm,sext,wmem, 25 | output[3:0] aluc, 26 | output[1:0] pcsource 27 | ); 28 | 29 | parameter cmd_add = 6'b100000; 30 | parameter cmd_sub = 6'b100010; 31 | parameter cmd_and = 6'b100100; 32 | parameter cmd_or = 6'b100101; 33 | parameter cmd_xor = 6'b100110; 34 | parameter cmd_sll = 6'b000000; 35 | parameter cmd_srl = 6'b000010; 36 | parameter cmd_sra = 6'b000011; 37 | parameter cmd_jr = 6'b001000; 38 | parameter cmd_addi = 6'b001000; 39 | parameter cmd_andi = 6'b001100; 40 | parameter cmd_ori = 6'b001101; 41 | parameter cmd_xori = 6'b001110; 42 | parameter cmd_lw = 6'b100011; 43 | parameter cmd_sw = 6'b101011; 44 | parameter cmd_beq = 6'b000100; 45 | parameter cmd_bne = 6'b000101; 46 | parameter cmd_lui = 6'b001111; 47 | parameter cmd_j = 6'b000010; 48 | parameter cmd_jal = 6'b000011; 49 | 50 | 51 | reg[13:0] cmd_out; 52 | 53 | always @(*) begin 54 | case (op) 55 | 6'b0 : begin 56 | case (func) 57 | cmd_add : cmd_out <= 14'b10000000000000; 58 | cmd_sub : cmd_out <= 14'b10000000100000; 59 | cmd_and : cmd_out <= 14'b10000000001000; 60 | cmd_or : cmd_out <= 14'b10000000101000; 61 | cmd_xor : cmd_out <= 14'b10000000010000; 62 | cmd_sll : cmd_out <= 14'b10001000011000; 63 | cmd_srl : cmd_out <= 14'b10001000111000; 64 | cmd_sra : cmd_out <= 14'b10001001111000; 65 | cmd_jr : cmd_out <= 14'b00000000000010; 66 | default : cmd_out <= 14'b00000000000000; 67 | endcase 68 | end 69 | cmd_addi : cmd_out <= 14'b11000110000000; 70 | cmd_andi : cmd_out <= 14'b11000100001000; 71 | cmd_ori : cmd_out <= 14'b11000100101000; 72 | cmd_xori : cmd_out <= 14'b11000100010000; 73 | cmd_lw : cmd_out <= 14'b11010110000000; 74 | cmd_sw : cmd_out <= 14'b00000110000100; 75 | cmd_beq : cmd_out <= {13'b0000001001000,z}; 76 | cmd_bne : cmd_out <= {13'b0000001001000,~z}; 77 | cmd_lui : cmd_out <= 14'b11000100110000; 78 | cmd_j : cmd_out <= 14'b00000000000011; 79 | cmd_jal : cmd_out <= 14'b10100000000011; 80 | default : cmd_out <= 14'b00000000000000; 81 | endcase 82 | end 83 | 84 | assign wreg = cmd_out[13]; 85 | assign regrt = cmd_out[12]; 86 | assign jal = cmd_out[11]; 87 | assign m2reg = cmd_out[10]; 88 | assign shfit = cmd_out[9]; 89 | assign aluimm = cmd_out[8]; 90 | assign sext = cmd_out[7]; 91 | assign aluc = cmd_out[6:3]; 92 | assign wmem = cmd_out[2]; 93 | assign pcsource = cmd_out[1:0]; 94 | 95 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/ALU/ALU.srcs/sim_1/new/ALU_TB.sv: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/17 13:37:41 8 | // Design Name: ALU 9 | // Module Name: ALU_TB 10 | // Project Name: MISP_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | module CLOCK ( 23 | output bit clk 24 | ); 25 | 26 | always #(100ps) begin 27 | clk = ~clk; 28 | end 29 | 30 | endmodule 31 | 32 | 33 | 34 | module ALU_TB(); 35 | 36 | class data_creat; 37 | rand bit[31:0] a,b; 38 | rand bit[3:0] cmd; 39 | bit suc; 40 | constraint test { 41 | (cmd != 4'b1011); 42 | } 43 | 44 | function new(int seed); 45 | this.srandom(seed); 46 | suc=this.randomize(); 47 | endfunction : new 48 | 49 | function void next(); 50 | suc=this.randomize(); 51 | endfunction : next 52 | 53 | endclass : data_creat; 54 | 55 | bit clk; 56 | CLOCK CLOCK1 (clk); 57 | data_creat dc; 58 | 59 | bit[31:0] a,b,aluc,r; 60 | bit z; 61 | 62 | ALU32 ALU0(a,b,aluc,r,z); 63 | 64 | task req(); 65 | @(posedge clk); 66 | dc.next(); 67 | a=dc.a; 68 | b=dc.b; 69 | aluc={28'b0,dc.cmd}; 70 | endtask : req 71 | 72 | task check(); 73 | @(negedge clk); 74 | case (aluc[2:0]) 75 | 3'b000 : begin 76 | $display("cmd = add\n"); 77 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 78 | end 79 | 3'b100 : begin 80 | $display("cmd = sub\n"); 81 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 82 | end 83 | 3'b001 : begin 84 | $display("cmd = and\n"); 85 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 86 | end 87 | 3'b101 : begin 88 | $display("cmd = or\n"); 89 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 90 | end 91 | 3'b010 : begin 92 | $display("cmd = xor\n"); 93 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 94 | end 95 | 3'b110 : begin 96 | $display("cmd = lui\n"); 97 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 98 | end 99 | 3'b011 : begin 100 | $display("cmd = sll\n"); 101 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 102 | end 103 | 3'b111 : begin 104 | if (aluc[3]==1'b0) begin 105 | $display("cmd = srl\n"); 106 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 107 | end 108 | else begin 109 | $display("cmd = sra\n"); 110 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 111 | end 112 | end 113 | default : /* default */; 114 | endcase 115 | endtask : check 116 | 117 | initial begin 118 | dc=new(200); 119 | repeat(100) begin 120 | req(); 121 | check(); 122 | end 123 | end 124 | 125 | endmodule 126 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/ALU/ALU.srcs/sim_1/new/ALU_TB.sv: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/17 13:37:41 8 | // Design Name: ALU 9 | // Module Name: ALU_TB 10 | // Project Name: MISP_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | module CLOCK ( 23 | output bit clk 24 | ); 25 | 26 | always #(100ps) begin 27 | clk = ~clk; 28 | end 29 | 30 | endmodule 31 | 32 | 33 | 34 | module ALU_TB(); 35 | 36 | class data_creat; 37 | rand bit[31:0] a,b; 38 | rand bit[3:0] cmd; 39 | bit suc; 40 | constraint test { 41 | (cmd != 4'b1011); 42 | } 43 | 44 | function new(int seed); 45 | this.srandom(seed); 46 | suc=this.randomize(); 47 | endfunction : new 48 | 49 | function void next(); 50 | suc=this.randomize(); 51 | endfunction : next 52 | 53 | endclass : data_creat; 54 | 55 | bit clk; 56 | CLOCK CLOCK1 (clk); 57 | data_creat dc; 58 | 59 | bit[31:0] a,b,aluc,r; 60 | bit z; 61 | 62 | ALU32 ALU0(a,b,aluc,r,z); 63 | 64 | task req(); 65 | @(posedge clk); 66 | dc.next(); 67 | a=dc.a; 68 | b=dc.b; 69 | aluc={28'b0,dc.cmd}; 70 | endtask : req 71 | 72 | task check(); 73 | @(negedge clk); 74 | case (aluc[2:0]) 75 | 3'b000 : begin 76 | $display("cmd = add\n"); 77 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 78 | end 79 | 3'b100 : begin 80 | $display("cmd = sub\n"); 81 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 82 | end 83 | 3'b001 : begin 84 | $display("cmd = and\n"); 85 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 86 | end 87 | 3'b101 : begin 88 | $display("cmd = or\n"); 89 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 90 | end 91 | 3'b010 : begin 92 | $display("cmd = xor\n"); 93 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 94 | end 95 | 3'b110 : begin 96 | $display("cmd = lui\n"); 97 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 98 | end 99 | 3'b011 : begin 100 | $display("cmd = sll\n"); 101 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 102 | end 103 | 3'b111 : begin 104 | if (aluc[3]==1'b0) begin 105 | $display("cmd = srl\n"); 106 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 107 | end 108 | else begin 109 | $display("cmd = sra\n"); 110 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 111 | end 112 | end 113 | default : /* default */; 114 | endcase 115 | endtask : check 116 | 117 | initial begin 118 | dc=new(200); 119 | repeat(100) begin 120 | req(); 121 | check(); 122 | end 123 | end 124 | 125 | endmodule 126 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_INST_MEM_0_1/MIPS_CPU_INST_MEM_0_1.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | MIPS_CPU_INST_MEM_0_1 10 | 11 | 12 | MIPS_CPU_INST_MEM_0_1 13 | artix7 14 | xc7a35t 15 | cpg236 16 | -1 17 | VERILOG 18 | MIXED 19 | TRUE 20 | TRUE 21 | d:/Spira_Heaven/0-MyWorks/MIPS_CPU/CPU_FOR_SIM 22 | 23 | TRUE 24 | 2014.2 25 | 5 26 | OUT_OF_CONTEXT 27 | . 28 | ../../../../ipshared 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/ALU/ALU.srcs/sim_1/new/ALU_TB.sv: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/17 13:37:41 8 | // Design Name: ALU 9 | // Module Name: ALU_TB 10 | // Project Name: MISP_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | module CLOCK ( 23 | output bit clk 24 | ); 25 | 26 | always #(100ps) begin 27 | clk = ~clk; 28 | end 29 | 30 | endmodule 31 | 32 | 33 | 34 | module ALU_TB(); 35 | 36 | class data_creat; 37 | rand bit[31:0] a,b; 38 | rand bit[3:0] cmd; 39 | bit suc; 40 | constraint test { 41 | (cmd != 4'b1011); 42 | } 43 | 44 | function new(int seed); 45 | this.srandom(seed); 46 | suc=this.randomize(); 47 | endfunction : new 48 | 49 | function void next(); 50 | suc=this.randomize(); 51 | endfunction : next 52 | 53 | endclass : data_creat; 54 | 55 | bit clk; 56 | CLOCK CLOCK1 (clk); 57 | data_creat dc; 58 | 59 | bit[31:0] a,b,aluc,r; 60 | bit z; 61 | 62 | ALU32 ALU0(a,b,aluc,r,z); 63 | 64 | task req(); 65 | @(posedge clk); 66 | dc.next(); 67 | a=dc.a; 68 | b=dc.b; 69 | aluc={28'b0,dc.cmd}; 70 | endtask : req 71 | 72 | task check(); 73 | @(negedge clk); 74 | case (aluc[2:0]) 75 | 3'b000 : begin 76 | $display("cmd = add\n"); 77 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 78 | end 79 | 3'b100 : begin 80 | $display("cmd = sub\n"); 81 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 82 | end 83 | 3'b001 : begin 84 | $display("cmd = and\n"); 85 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 86 | end 87 | 3'b101 : begin 88 | $display("cmd = or\n"); 89 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 90 | end 91 | 3'b010 : begin 92 | $display("cmd = xor\n"); 93 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 94 | end 95 | 3'b110 : begin 96 | $display("cmd = lui\n"); 97 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 98 | end 99 | 3'b011 : begin 100 | $display("cmd = sll\n"); 101 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 102 | end 103 | 3'b111 : begin 104 | if (aluc[3]==1'b0) begin 105 | $display("cmd = srl\n"); 106 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 107 | end 108 | else begin 109 | $display("cmd = sra\n"); 110 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 111 | end 112 | end 113 | default : /* default */; 114 | endcase 115 | endtask : check 116 | 117 | initial begin 118 | dc=new(200); 119 | repeat(100) begin 120 | req(); 121 | check(); 122 | end 123 | end 124 | 125 | endmodule 126 | -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/ALU/ALU.srcs/sim_1/new/ALU_TB.sv: -------------------------------------------------------------------------------- 1 | //Author : dtysky 2 | `timescale 1ns / 1ps 3 | ////////////////////////////////////////////////////////////////////////////////// 4 | // Company: Xilinx 5 | // Engineer: dtysky 6 | // 7 | // Create Date: 2015/01/17 13:37:41 8 | // Design Name: ALU 9 | // Module Name: ALU_TB 10 | // Project Name: MISP_CPU 11 | // Target Devices: 12 | // Tool Versions: 13 | // Description: 14 | // 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | module CLOCK ( 23 | output bit clk 24 | ); 25 | 26 | always #(100ps) begin 27 | clk = ~clk; 28 | end 29 | 30 | endmodule 31 | 32 | 33 | 34 | module ALU_TB(); 35 | 36 | class data_creat; 37 | rand bit[31:0] a,b; 38 | rand bit[3:0] cmd; 39 | bit suc; 40 | constraint test { 41 | (cmd != 4'b1011); 42 | } 43 | 44 | function new(int seed); 45 | this.srandom(seed); 46 | suc=this.randomize(); 47 | endfunction : new 48 | 49 | function void next(); 50 | suc=this.randomize(); 51 | endfunction : next 52 | 53 | endclass : data_creat; 54 | 55 | bit clk; 56 | CLOCK CLOCK1 (clk); 57 | data_creat dc; 58 | 59 | bit[31:0] a,b,aluc,r; 60 | bit z; 61 | 62 | ALU32 ALU0(a,b,aluc,r,z); 63 | 64 | task req(); 65 | @(posedge clk); 66 | dc.next(); 67 | a=dc.a; 68 | b=dc.b; 69 | aluc={28'b0,dc.cmd}; 70 | endtask : req 71 | 72 | task check(); 73 | @(negedge clk); 74 | case (aluc[2:0]) 75 | 3'b000 : begin 76 | $display("cmd = add\n"); 77 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 78 | end 79 | 3'b100 : begin 80 | $display("cmd = sub\n"); 81 | $display("a = %d\nb = %d\nr = %d\nz = %b\n",signed'(a),signed'(b),signed'(r),z); 82 | end 83 | 3'b001 : begin 84 | $display("cmd = and\n"); 85 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 86 | end 87 | 3'b101 : begin 88 | $display("cmd = or\n"); 89 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 90 | end 91 | 3'b010 : begin 92 | $display("cmd = xor\n"); 93 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 94 | end 95 | 3'b110 : begin 96 | $display("cmd = lui\n"); 97 | $display("a = %b\nb = %b\nr = %b\nz = %b\n",a,b,r,z); 98 | end 99 | 3'b011 : begin 100 | $display("cmd = sll\n"); 101 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 102 | end 103 | 3'b111 : begin 104 | if (aluc[3]==1'b0) begin 105 | $display("cmd = srl\n"); 106 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 107 | end 108 | else begin 109 | $display("cmd = sra\n"); 110 | $display("a = %d\nb = %b\nr = %b\nz = %b\n",a[4:0],b,r,z); 111 | end 112 | end 113 | default : /* default */; 114 | endcase 115 | endtask : check 116 | 117 | initial begin 118 | dc=new(200); 119 | repeat(100) begin 120 | req(); 121 | check(); 122 | end 123 | end 124 | 125 | endmodule 126 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_DATA_MEM_0_1/synth/MIPS_CPU_DATA_MEM_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:DATA_MEM:1.0 51 | // IP Revision: 4 52 | 53 | (* X_CORE_INFO = "DATA_MEM,Vivado 2014.2" *) 54 | (* CHECK_LICENSE_TYPE = "MIPS_CPU_DATA_MEM_0_1,DATA_MEM,{}" *) 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_DATA_MEM_0_1 ( 57 | addr, 58 | data_in, 59 | clk, 60 | we, 61 | data_out 62 | ); 63 | 64 | input wire [31 : 0] addr; 65 | input wire [31 : 0] data_in; 66 | input wire clk; 67 | input wire we; 68 | output wire [31 : 0] data_out; 69 | 70 | DATA_MEM inst ( 71 | .addr(addr), 72 | .data_in(data_in), 73 | .clk(clk), 74 | .we(we), 75 | .data_out(data_out) 76 | ); 77 | endmodule 78 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ui/bd_a462dba8.ui: -------------------------------------------------------------------------------- 1 | { 2 | comment_0: "Project Homepage: 3 | https://github.com/dtysky/SIMPLE_MIPS_CPU", 4 | commentid: "comment_0|", 5 | fillcolor_comment_0: "", 6 | font_comment_0: "27", 7 | guistr: "# # String gsaved with Nlview version 6.4-r1 2014-02-28 bk=1.3047 VDI=34 GEI=35 GUI=JA:1.6 8 | # -string -flagsOSRD 9 | preplace port clk -pg 1 -y 20 -defaultsOSRD 10 | preplace port restet -pg 1 -y 40 -defaultsOSRD 11 | preplace portBus data_pinout -pg 1 -y 320 -defaultsOSRD 12 | preplace portBus pc_pinout -pg 1 -y 390 -defaultsOSRD 13 | preplace portBus alu_pinout -pg 1 -y 360 -defaultsOSRD 14 | preplace portBus inst_pinout -pg 1 -y 340 -defaultsOSRD 15 | preplace inst REGFILE_0 -pg 1 -lvl 3 -y 370 -defaultsOSRD 16 | preplace inst DATA_MEM_0 -pg 1 -lvl 3 -y 600 -defaultsOSRD 17 | preplace inst CONTROL_UNIT_0 -pg 1 -lvl 1 -y 420 -defaultsOSRD 18 | preplace inst INST_MEM_0 -pg 1 -lvl 3 -y 740 -defaultsOSRD 19 | preplace inst ALU32_0 -pg 1 -lvl 3 -y 160 -defaultsOSRD 20 | preplace inst DATAPATH_0 -pg 1 -lvl 2 -y 560 -defaultsOSRD 21 | preplace inst clk_wiz_0 -pg 1 -lvl 1 -y 160 -defaultsOSRD 22 | preplace netloc DATAPATH_0_reg_d 1 2 1 860 23 | preplace netloc CONTROL_UNIT_0_m2reg 1 1 1 390 24 | preplace netloc REGFILE_0_qa 1 1 3 500 260 NJ 260 1420 25 | preplace netloc DATAPATH_0_reg_we 1 2 1 840 26 | preplace netloc DATAPATH_0_con_z 1 0 3 110 560 NJ 340 780 27 | preplace netloc CONTROL_UNIT_0_regrt 1 1 1 420 28 | preplace netloc REGFILE_0_qb 1 1 3 520 310 NJ 490 1420 29 | preplace netloc DATAPATH_0_data_we 1 2 1 940 30 | preplace netloc DATAPATH_0_alu_aluc 1 2 1 830 31 | preplace netloc ALU32_0_r 1 1 3 480 90 NJ 90 1440 32 | preplace netloc DATA_MEM_0_data_out 1 1 3 490 300 NJ 480 1430 33 | preplace netloc DATAPATH_0_inst_a 1 2 1 840 34 | preplace netloc CONTROL_UNIT_0_aluimm 1 1 1 370 35 | preplace netloc CONTROL_UNIT_0_jal 1 1 1 410 36 | preplace netloc INST_MEM_0_inst_out 1 1 3 520 780 NJ 690 1450 37 | preplace netloc restet_1 1 0 3 NJ 220 450 290 NJ 38 | preplace netloc DATAPATH_0_data_di 1 2 1 930 39 | preplace netloc DATAPATH_0_con_func 1 0 3 110 280 NJ 330 790 40 | preplace netloc CONTROL_UNIT_0_sext 1 1 1 360 41 | preplace netloc CONTROL_UNIT_0_shfit 1 1 1 380 42 | preplace netloc clk_1 1 0 1 110 43 | preplace netloc DATAPATH_0_reg_rna 1 2 1 880 44 | preplace netloc DATAPATH_0_alu_a 1 2 1 810 45 | preplace netloc clk_wiz_0_clk_out1 1 1 2 470 280 900 46 | preplace netloc DATAPATH_0_pc_out 1 2 2 920 500 NJ 47 | preplace netloc DATAPATH_0_reg_rnb 1 2 1 910 48 | preplace netloc DATAPATH_0_alu_b 1 2 1 820 49 | preplace netloc DATAPATH_0_con_op 1 0 3 100 270 NJ 320 800 50 | preplace netloc CONTROL_UNIT_0_pcsource 1 1 1 330 51 | preplace netloc CONTROL_UNIT_0_wmem 1 1 1 350 52 | preplace netloc DATAPATH_0_data_a 1 2 1 910 53 | preplace netloc DATAPATH_0_reg_wn 1 2 1 850 54 | preplace netloc CONTROL_UNIT_0_aluc 1 1 1 340 55 | preplace netloc ALU32_0_z 1 1 3 510 230 NJ 230 1420 56 | preplace netloc CONTROL_UNIT_0_wreg 1 1 1 430 57 | preplace cgraphic comment_0 place abs 80 818 textcolor 6 linecolor 3 linewidth 0 58 | levelinfo -pg 1 80 220 650 1300 1470 59 | ", 60 | linecolor_comment_0: "", 61 | textcolor_comment_0: "#ff0000", 62 | } 63 | 0 -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_ALU32_0_1/MIPS_CPU_ALU32_0_1.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: dtysky:user:ALU32:1.0 50 | // IP Revision: 2 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | MIPS_CPU_ALU32_0_1 your_instance_name ( 58 | .a(a), // input wire [31 : 0] a 59 | .b(b), // input wire [31 : 0] b 60 | .aluc(aluc), // input wire [31 : 0] aluc 61 | .r(r), // output wire [31 : 0] r 62 | .z(z) // output wire z 63 | ); 64 | // INST_TAG_END ------ End INSTANTIATION Template --------- 65 | 66 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_REGFILE_0_1/sim/MIPS_CPU_REGFILE_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:REGFILE:1.0 51 | // IP Revision: 6 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_REGFILE_0_1 ( 57 | clk, 58 | clrn, 59 | d, 60 | we, 61 | wn, 62 | rna, 63 | rnb, 64 | qa, 65 | qb 66 | ); 67 | 68 | input wire clk; 69 | input wire clrn; 70 | input wire [31 : 0] d; 71 | input wire we; 72 | input wire [4 : 0] wn; 73 | input wire [4 : 0] rna; 74 | input wire [4 : 0] rnb; 75 | output wire [31 : 0] qa; 76 | output wire [31 : 0] qb; 77 | 78 | REGFILE inst ( 79 | .clk(clk), 80 | .clrn(clrn), 81 | .d(d), 82 | .we(we), 83 | .wn(wn), 84 | .rna(rna), 85 | .rnb(rnb), 86 | .qa(qa), 87 | .qb(qb) 88 | ); 89 | endmodule 90 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_REGFILE_0_1/MIPS_CPU_REGFILE_0_1.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | MIPS_CPU_REGFILE_0_1 10 | 11 | 12 | MIPS_CPU_REGFILE_0_1 13 | artix7 14 | xc7a35t 15 | cpg236 16 | -1 17 | VERILOG 18 | MIXED 19 | TRUE 20 | TRUE 21 | d:/Spira_Heaven/0-MyWorks/MIPS_CPU/CPU_FOR_SIM;d:/spira_heaven/0-myworks/mips_cpu/cpu_for_sim/ipcore/datapath/datapath.srcs/sources_1/new;d:/spira_heaven/0-myworks/mips_cpu/cpu_for_sim/ipcore/regfile/regfile.srcs 22 | 23 | TRUE 24 | 2014.2 25 | 6 26 | OUT_OF_CONTEXT 27 | . 28 | ../../../../ipshared 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /SUB_MODULE/ALU/ALU.srcs/sources_1/new/MATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_REGFILE_0_1/synth/MIPS_CPU_REGFILE_0_1.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: dtysky:user:REGFILE:1.0 51 | // IP Revision: 6 52 | 53 | (* X_CORE_INFO = "REGFILE,Vivado 2014.2" *) 54 | (* CHECK_LICENSE_TYPE = "MIPS_CPU_REGFILE_0_1,REGFILE,{}" *) 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module MIPS_CPU_REGFILE_0_1 ( 57 | clk, 58 | clrn, 59 | d, 60 | we, 61 | wn, 62 | rna, 63 | rnb, 64 | qa, 65 | qb 66 | ); 67 | 68 | input wire clk; 69 | input wire clrn; 70 | input wire [31 : 0] d; 71 | input wire we; 72 | input wire [4 : 0] wn; 73 | input wire [4 : 0] rna; 74 | input wire [4 : 0] rnb; 75 | output wire [31 : 0] qa; 76 | output wire [31 : 0] qb; 77 | 78 | REGFILE inst ( 79 | .clk(clk), 80 | .clrn(clrn), 81 | .d(d), 82 | .we(we), 83 | .wn(wn), 84 | .rna(rna), 85 | .rnb(rnb), 86 | .qa(qa), 87 | .qb(qb) 88 | ); 89 | endmodule 90 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/ALU/ALU.srcs/sources_1/new/MATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/ALU/ALU.srcs/sources_1/new/MATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/ALU/ALU.srcs/sources_1/new/MATH.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /SUB_MODULE/DATAPATH/DATAPATH.srcs/sources_1/new/ADDSUB32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /CPU_FOR_SIM/IPCORE/DATAPATH/DATAPATH.srcs/sources_1/new/ADDSUB32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /CPU_ON_BOARD/IPCORE/DATAPATH/DATAPATH.srcs/sources_1/new/ADDSUB32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /ProjectTcl/IPCatalog/DATAPATH/DATAPATH.srcs/sources_1/new/ADDSUB32.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: Xilinx 4 | // Engineer: dtysky 5 | // 6 | // Create Date: 2015/01/16 18:34:13 7 | // Design Name: ALU32 8 | // Module Name: ADDSUB32 9 | // Project Name: MIPS_CPU 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ADD( 22 | input a,b,c, 23 | output g,p,s 24 | ); 25 | 26 | assign s = a ^ b ^ c; 27 | assign g = a & b; 28 | assign p = a | b; 29 | 30 | endmodule 31 | 32 | module G_P( 33 | input[1:0] g,p, 34 | input c_in, 35 | output g_out,p_out,c_out 36 | ); 37 | 38 | assign g_out = g[1] | p[1] & g[0]; 39 | assign p_out = p[1] & p[0]; 40 | assign c_out = g[0] | p[0] & c_in; 41 | 42 | endmodule 43 | 44 | // module ADDSUB32( 45 | // input[31:0] a,b; 46 | // input sub; 47 | // output[31:0] s 48 | // ); 49 | 50 | // wire[31:0] g,p; 51 | // wire[31:0] s; 52 | 53 | // generate 54 | // genvar i; 55 | // for (i=0;i<16;i=i+1) 56 | // begin : ADD 57 | 58 | // end 59 | // endgenerate 60 | 61 | // endmodule 62 | 63 | module CLA2 ( 64 | input[1:0] a,b, 65 | input c_in, 66 | output g_out,p_out, 67 | output[1:0] s 68 | ); 69 | 70 | wire[1:0] g,p; 71 | wire c_out; 72 | 73 | ADD ADD0 (a[0],b[0],c_in,g[0],p[0],s[0]); 74 | ADD ADD1 (a[1],b[1],c_out,g[1],p[1],s[1]); 75 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 76 | 77 | endmodule 78 | 79 | module CLA4 ( 80 | input[3:0] a,b, 81 | input c_in, 82 | output g_out,p_out, 83 | output[3:0] s 84 | ); 85 | 86 | wire[1:0] g,p; 87 | wire c_out; 88 | 89 | CLA2 CLA20 (a[1:0],b[1:0],c_in,g[0],p[0],s[1:0]); 90 | CLA2 CLA21 (a[3:2],b[3:2],c_out,g[1],p[1],s[3:2]); 91 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 92 | 93 | endmodule 94 | 95 | module CLA8 ( 96 | input[7:0] a,b, 97 | input c_in, 98 | output g_out,p_out, 99 | output[7:0] s 100 | ); 101 | 102 | wire[1:0] g,p; 103 | wire c_out; 104 | 105 | CLA4 CLA40 (a[3:0],b[3:0],c_in,g[0],p[0],s[3:0]); 106 | CLA4 CLA41 (a[7:4],b[7:4],c_out,g[1],p[1],s[7:4]); 107 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 108 | 109 | endmodule 110 | 111 | module CLA16 ( 112 | input[15:0] a,b, 113 | input c_in, 114 | output g_out,p_out, 115 | output[15:0] s 116 | ); 117 | 118 | wire[1:0] g,p; 119 | wire c_out; 120 | 121 | CLA8 CLA80 (a[7:0],b[7:0],c_in,g[0],p[0],s[7:0]); 122 | CLA8 CLA81 (a[15:8],b[15:8],c_out,g[1],p[1],s[15:8]); 123 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 124 | 125 | endmodule 126 | 127 | module CLA32 ( 128 | input[31:0] a,b, 129 | input c_in, 130 | output[31:0] s 131 | ); 132 | 133 | wire[1:0] g,p; 134 | wire c_out; 135 | 136 | CLA16 CLA160 (a[15:0],b[15:0],c_in,g[0],p[0],s[15:0]); 137 | CLA16 CLA161 (a[31:16],b[31:16],c_out,g[1],p[1],s[31:16]); 138 | G_P G_P0 (g,p,c_in,g_out,p_out,c_out); 139 | 140 | endmodule 141 | 142 | module ADDSUB32( 143 | input[31:0] a,b, 144 | input sub, 145 | output[31:0] s 146 | ); 147 | 148 | CLA32 CLA320(a,b^{32{sub}},sub,s); 149 | 150 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SIMPLE_MIPS_CPU 2 |

A simple MIPS CPU, 32bits, designed with verilogHDL, bulit on xilinx vivado.

3 |

Design for Southeast University : Subject "Computer Organization and Design".

4 | 5 | *** 6 | 7 | **CPU for simulation----100%.** 8 | **CPU on board----100%.** 9 | **ProjectTcl.----100%.** 10 | 11 | **ALU----100%.** 12 | **REGFILE----100%.** 13 | **CONTROL_UNIT----100%.** 14 | **DATAPATH----100%.** 15 | 16 | Files and Descriptions: 17 | ===== 18 | 19 | Sub modules(SUB_MODULE): 20 | ----------- 21 | **ALU（ALU\ALU.srcs）:** 22 | 1. ALU.v: ALU 23 | 2. LOGIC.v: AND/OR/XOR/LUI 24 | 3. MATH.v: ADD/SUB 25 | 4. SHIFT.v: SLL,SRL,SRA 26 | 5. ALU_TB.sv: TestBench for ALU. 27 | 28 | **REGFILE（REGFILE\REGFILE.srcs）:** 29 | 1. REGFILE.v: REGFILE 30 | 2. REGFILE_TB.sv: TestBench for REGFILE. 31 | 32 | **CONTROL_UNIT（CONTROL_UNIT\CONTROL_UNIT.srcs）:** 33 | 1. CONTROL_UNIT.v: CONTROL_UNIT 34 | 2. CONTROL_UNIT_TB.sv: TestBench for CONTROL_UNIT. 35 | 36 | **DATAPATH（DATAPATH\DATAPATH.srcs）:** 37 | 1. DATAPATH.v: DATAPATH 38 | 2. ADDSUB32.v: For processing next pc address when jump. 39 | 40 | **INST_MEM（INST_MEM\INST_MEM.srcs）:** 41 | 1. INST_MEM.v: A list which has some inst, for test. 42 | 43 | **DATA_MEM（DATA_MEM\DATA_MEM.srcs）:** 44 | 1. DATA_MEM.v: A ram, for test. 45 | 46 | **KEY2INST（KEY2INST\KEY2INST.srcs）:** 47 | 1. KEY2INST.v: Convert keys' states to CPU instruction. 48 | 2. KEY2INST_TB.sv: TestBench for KEY2INST. 49 | 50 | **SHOW_ON_LED（SHOW_ON_LED\SHOW_ON_LED.srcs）:** 51 | 1. SHOW_ON_LED.v: Show result or keys' state on leds. 52 | 53 | ProjectTcl(ProjectTcl): 54 | ----------- 55 | **Tcl projects, you can source run_on_board.tcl or simulation.tcl in "ProjectTcl/Tcl" to build a new project, then all will be done.** 56 | 57 | CPU for simulation(CPU_FOR_SIM): 58 | ----------- 59 | **A project for function sim, use some instructs and data which are predefined.** 60 | **IPCORE(IPCORE\\):** 61 | Sub modules are here. 62 | 63 | **CPU_FOR_SIM.srcs:** 64 | 1. MIPS_CPU_TB.sv: TestBench for function simulation. 65 | 2. MIPS_CPU.bd: CPU board. 66 | 67 | ![](Image/1.png) 68 | ![](Image/2.png) 69 | 70 | CPU on board.(CPU_ON_BOARD): 71 | ----------- 72 | **A project for testing on board, you can input cmd by keys, then leds willshow the result.** 73 | **The function of buttons and leds are here:** 74 | ![](Image/3.png) 75 | 76 | **IPCORE(IPCORE\\):** 77 | Sub modules are here. 78 | 79 | **CPU_ON_BOARD.srcs:** 80 | 1. MIPS_CPU.xdc: Constraints file for Basys3 board. 81 | 2. MIPS_CPU.bd: CPU board. 82 | 83 | ![](Image/4.png) 84 | 85 | An exmple: 86 | 87 | 1. Reset: 88 | ![](Image/5.jpg) 89 | 90 | 2. Set data_b high 8bits to "00000001": 91 | ![](Image/6.jpg) 92 | 93 | 3. Run, get result = "0000000100000000" + "0000000000000000"= "0000000100000000": 94 | ![](Image/7.jpg) 95 | 96 | AUTHOR 97 | --- 98 | **Dai Tianyu(dtysky)** 99 | [http://dtysky.github.io](http://dtysky.github.io) 100 | [dtysky@outlook.com](dtysky@outlook.com) 101 | [http://github.com/dtysky](http://github.com/dtysky) 102 | 103 | Copyright 104 | --- 105 | Copyright © 2014, Dai Tianyu(dtysky). All Rights Reserved. 106 | This project is free software and released under the [MIT License (MIT)](http://mit-license.org/). -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_DATA_MEM_0_1/MIPS_CPU_DATA_MEM_0_1.xci: -------------------------------------------------------------------------------- 1 | 2 | 3 | xilinx.com 4 | xci 5 | unknown 6 | 1.0 7 | 8 | 9 | MIPS_CPU_DATA_MEM_0_1 10 | 11 | 12 | MIPS_CPU_DATA_MEM_0_1 13 | artix7 14 | xc7a35t 15 | cpg236 16 | -1 17 | VERILOG 18 | MIXED 19 | TRUE 20 | TRUE 21 | d:/Spira_Heaven/0-MyWorks/MIPS_CPU/CPU_FOR_SIM;d:/spira_heaven/0-myworks/mips_cpu/cpu_for_sim/ipcore/datapath/datapath.srcs/sources_1/new;d:/spira_heaven/0-myworks/mips_cpu/cpu_for_sim/ipcore/control_unit/control_unit.srcs;d:/spira_heaven/0-myworks/mips_cpu/cpu_for_sim/ipcore/data_mem/data_mem.srcs/sources_1/new 22 | 23 | TRUE 24 | 2014.2 25 | 4 26 | OUT_OF_CONTEXT 27 | . 28 | ../../../../ipshared 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /SUB_MODULE/INST_MEM/INST_MEM.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 35 | 36 | 37 | 38 | 39 | 41 | 42 | 43 | 44 | 45 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /SUB_MODULE/SHOW_ON_LED/SHOW_ON_LED.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 35 | 36 | 37 | 38 | 39 | 41 | 42 | 43 | 44 | 45 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /SUB_MODULE/DATA_MEM/DATA_MEM.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 35 | 36 | 37 | 38 | 39 | 41 | 42 | 43 | 44 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | Vivado Synthesis Defaults 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | Vivado Implementation Defaults 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | -------------------------------------------------------------------------------- /CPU_FOR_SIM/CPU_FOR_SIM.srcs/sources_1/bd/MIPS_CPU/ip/MIPS_CPU_clk_wiz_0_0/doc/clk_wiz_v5_1_changelog.txt: -------------------------------------------------------------------------------- 1 | 2014.2: 2 | * Version 5.1 (Rev. 3) 3 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 4 | 5 | 2014.1: 6 | * Version 5.1 (Rev. 2) 7 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 8 | * Internal device family name change, no functional changes 9 | 10 | 2013.4: 11 | * Version 5.1 (Rev. 1) 12 | * Added support for Ultrascale devices 13 | * Updated Board Flow GUI to select the clock interfaces 14 | * Fixed issue with Stub file parameter error for BUFR output driver 15 | 16 | 2013.3: 17 | * Version 5.1 18 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 19 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 20 | * Fixed precision issues between displayed and actual frequencies 21 | * Added tool tips to GUI 22 | * Added Jitter and Phase error values to IP properties 23 | * Added support for Cadence IES and Synopsys VCS simulators 24 | * Reduced warnings in synthesis and simulation 25 | * Enhanced support for IP Integrator 26 | 27 | 2013.2: 28 | * Version 5.0 (Rev. 1) 29 | * Fixed issue with clock constraints for multiple instances of clocking wizard 30 | * Updated Life-Cycle status of devices 31 | 32 | 2013.1: 33 | * Version 5.0 34 | * Lower case ports for Verilog 35 | * Added Safe Clock Startup and Clock Sequencing 36 | 37 | (c) Copyright 2008 - 2014 Xilinx, Inc. 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