├── .gitignore ├── README.md ├── clock_div ├── clock_div.v ├── clock_div_tb.v ├── complie.do ├── modelsim.ini ├── sim.do ├── transcript └── vlog.opt ├── clock_gating ├── clock_gating.v ├── clock_gating_tb.v ├── complie.do └── sim.do ├── parallel_serial_switch ├── complie1.do ├── parallel_to_serial.v ├── parallel_to_serial_tb.v ├── serial_to_parallel _tb.v ├── serial_to_parallel.v ├── sim2.do └── transcript └── uvm_template ├── RTL └── dut.sv └── Verification ├── sim ├── clean.bat ├── dut.f ├── filelist.f ├── run.bat ├── sim.do └── wave_open.bat └── tb ├── base_test.sv ├── my_agent.sv ├── my_case0.sv ├── my_case1.sv ├── my_driver.sv ├── my_env.sv ├── my_if.sv ├── my_model.sv ├── my_monitor.sv ├── my_scoreboard.sv ├── my_sequencer.sv ├── my_transaction.sv ├── testbench.sv └── top_tb.sv /.gitignore: -------------------------------------------------------------------------------- 1 | *.qws 2 | *.qsf 3 | *.inc 4 | *.bak 5 | *.ipinfo 6 | *.pl 7 | *.rpt 8 | *.wlf 9 | work 10 | db 11 | simulation 12 | output_files 13 | incremental_db 14 | 15 | *.rar 16 | eth 17 | pipelined_fft_64 18 | fir_filter 19 | I2C 20 | 21 | # #添加 22 | # !.gitignore 23 | # #uart 24 | # !UART 25 | # !UART/RTL/* 26 | # !UART/DOC/* 27 | # !UART/BENCH/* 28 | # !UART/RTL 29 | # !UART/DOC 30 | # !UART/BENCH 31 | # !UART/*.qdf 32 | # !UART/*.do 33 | # !UART/*.bat 34 | # #I2C 35 | # !I2C 36 | # !I2C/RTL 37 | # !I2C/DOC 38 | # !I2C/BENCH 39 | # !I2C/*.qdf 40 | # !I2C/*.do 41 | # !I2C/*.bat -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # my_verilog_projects 2 | 数字IC经典项目代码，使用quartus+modelsim仿真. 3 | 4 | clk_div、clk_gating、parallel_serial_switch是最简单的DEMO，用于熟悉语法和EDA。 5 | 6 | uvm_template提供了一个基本的UVM环境，可用于学习UVM验证。 7 | -------------------------------------------------------------------------------- /clock_div/clock_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dumpo/my_verilog_projects/c2db9636a569f1683e6c537c8d5a010fc58e35ad/clock_div/clock_div.v -------------------------------------------------------------------------------- /clock_div/clock_div_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module DUT(output clk_out1,output clk_out2,output clk_out3); 3 | reg rst; 4 | reg clk; 5 | 6 | 7 | 8 | initial 9 | begin 10 | rst<=1; 11 | clk<=0; 12 | #15 13 | rst<=0; 14 | #1000 $stop; 15 | end 16 | 17 | always #10 clk<=~clk; 18 | 19 | Odd_Divider div3(clk,~rst,clk_out3); 20 | clock_div1 div1(rst,clk,clk_out1); 21 | clock_div2 div2(rst,clk,clk_out2); 22 | endmodule -------------------------------------------------------------------------------- /clock_div/complie.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dumpo/my_verilog_projects/c2db9636a569f1683e6c537c8d5a010fc58e35ad/clock_div/complie.do -------------------------------------------------------------------------------- /clock_div/modelsim.ini: -------------------------------------------------------------------------------- 1 | ; vsim modelsim.ini file 2 | [Version] 3 | INIVersion = "2020.1" 4 | 5 | ; Copyright 1991-2020 Mentor Graphics Corporation 6 | ; 7 | ; All Rights Reserved. 8 | ; 9 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 10 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. 11 | ; 12 | 13 | [Library] 14 | others = D:/questasim64_2020.1/win64/../modelsim.ini 15 | ; 16 | ; VITAL concerns: 17 | ; 18 | ; The library ieee contains (among other packages) the packages of the 19 | ; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use 20 | ; the physical library ieee (recommended), or use the physical library 21 | ; vital2000, but not both. The design can use logical library ieee and/or 22 | ; vital2000 as long as each of these maps to the same physical library, either 23 | ; ieee or vital2000. 24 | ; 25 | ; A design using the 1995 version of the VITAL packages, whether or not 26 | ; it also uses the 2000 version of the VITAL packages, must have logical library 27 | ; name ieee mapped to physical library vital1995. (A design cannot use library 28 | ; vital1995 directly because some packages in this library use logical name ieee 29 | ; when referring to the other packages in the library.) The design source 30 | ; should use logical name ieee when referring to any packages there except the 31 | ; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical 32 | ; name vital2000 (mapped to physical library vital2000) to refer to those 33 | ; packages. 34 | ; ieee = $MODEL_TECH/../vital1995 35 | ; 36 | ; For compatiblity with previous releases, logical library name vital2000 maps 37 | ; to library vital2000 (a different library than library ieee, containing the 38 | ; same packages). 39 | ; A design should not reference VITAL from both the ieee library and the 40 | ; vital2000 library because the vital packages are effectively different. 41 | ; A design that references both the ieee and vital2000 libraries must have 42 | ; both logical names ieee and vital2000 mapped to the same library, either of 43 | ; these: 44 | ; $MODEL_TECH/../ieee 45 | ; $MODEL_TECH/../vital2000 46 | ; 47 | 48 | ; added mapping for ADMS 49 | 50 | ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release 51 | ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release 52 | ;mvc_lib = $MODEL_TECH/../mvc_lib 53 | 54 | ; Automatically perform logical->physical mapping for physical libraries that 55 | ; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/'). 56 | ; The tail of the filesystem path name is chosen as the logical library name. 57 | ; For example, in the command "vopt -L ./path/to/lib1 -o opttop top", 58 | ; vopt automatically performs the mapping "lib1 -> ./path/to/lib1". 59 | ; See the User Manual for more details. 60 | ; 61 | ; AutoLibMapping = 0 62 | 63 | [DefineOptionset] 64 | ; Define optionset entries for the various compilers, vmake, and vsim. 65 | ; These option sets can be used with the "-optionset " syntax. 66 | ; i.e. 67 | ; vlog -optionset COMPILEDEBUG top.sv 68 | ; vsim -optionset UVMDEBUG my_top 69 | ; 70 | ; Following are some useful examples. 71 | 72 | ; define a vsim optionset for uvm debugging 73 | UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop 74 | 75 | ; define a vopt optionset for debugging 76 | VOPTDEBUG = +acc -debugdb 77 | 78 | [encryption] 79 | ; For vencrypt and vhencrypt. 80 | 81 | ; Controls whether to encrypt whole files by ignoring all protect directives 82 | ; (except "viewport" and "interface_viewport") that are present in the input. 83 | ; The default is 0, use embedded protect directives to control the encryption. 84 | ; Set this to 1 to encrypt whole files by ignoring embedded protect directives. 85 | ; wholefile = 0 86 | 87 | ; Sets the data_method to use for the symmetric session key. 88 | ; The session key is a symmetric key that is randomly generated for each 89 | ; protected region (envelope) and is the heart of all encryption. This is used 90 | ; to set the length of the session key to generate and use when encrypting the 91 | ; HDL text. Supported values are aes128, aes192, and aes256. 92 | ; data_method = aes128 93 | 94 | ; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption 95 | ; "recipe" comprising an optional common block, at least one tool block (which 96 | ; contains the key public key), and the text to be encrypted. The common block 97 | ; and any of the tool blocks may contain rights in the form of the "control" 98 | ; directive. The text to be encrypted is specified either by setting 99 | ; "wholefile" to 1 or by embedding protect "begin" and "end" directives in 100 | ; the input HDL files. 101 | 102 | ; Common recipe specification file. This file is optional. Its presence will 103 | ; require at least one "toolblock" to be specified. 104 | ; Directives such as "author" "author_info" and "data_method", 105 | ; as well as the common block license specification, go in this file. 106 | ; common = 107 | 108 | ; Tool block specification recipe(s). Public key file with optional tool block 109 | ; file name. May be multiply-defined; at least one tool block is required if 110 | ; a recipe is being specified. 111 | ; Key file is a file name with no extension (.deprecated or .active will be 112 | ; supplied by the encryption tool). 113 | ; Rights file name is optional. 114 | ; toolblock = [,]{:[,]} 115 | 116 | ; Location of directory containing recipe files. 117 | ; The default location is in the product installation directory. 118 | ; keyring = $MODEL_TECH/../keyring 119 | 120 | ; Enable encryption statistics. Specify one or more arguments: 121 | ; [all,none,time,cmd,msg,perf,verbose,list] 122 | ; Add '-' to disable specific statistics. Default is [cmd,msg]. 123 | Stats = cmd,msg 124 | 125 | [vcom] 126 | ; VHDL93 variable selects language version as the default. 127 | ; Default is VHDL-2002. 128 | ; Value of 0 or 1987 for VHDL-1987. 129 | ; Value of 1 or 1993 for VHDL-1993. 130 | ; Default or value of 2 or 2002 for VHDL-2002. 131 | ; Value of 3 or 2008 for VHDL-2008 132 | ; Value of 4 or ams99 for VHDL-AMS-1999 133 | ; Value of 5 or ams07 for VHDL-AMS-2007 134 | VHDL93 = 2002 135 | 136 | ; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. 137 | ; ignoreStandardRealVector = 1 138 | 139 | ; Show source line containing error. Default is off. 140 | ; Show_source = 1 141 | 142 | ; Turn off unbound-component warnings. Default is on. 143 | ; Show_Warning1 = 0 144 | 145 | ; Turn off process-without-a-wait-statement warnings. Default is on. 146 | ; Show_Warning2 = 0 147 | 148 | ; Turn off null-range warnings. Default is on. 149 | ; Show_Warning3 = 0 150 | 151 | ; Turn off no-space-in-time-literal warnings. Default is on. 152 | ; Show_Warning4 = 0 153 | 154 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 155 | ; Show_Warning5 = 0 156 | 157 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 158 | ; Optimize_1164 = 0 159 | 160 | ; Enable compiler statistics. Specify one or more arguments: 161 | ; [all,none,time,cmd,msg,perf,verbose,list] 162 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 163 | ; Stats = time,cmd,msg 164 | 165 | ; Turn on resolving of ambiguous function overloading in favor of the 166 | ; "explicit" function declaration (not the one automatically created by 167 | ; the compiler for each type declaration). Default is off. 168 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 169 | ; will match the behavior of synthesis tools. 170 | Explicit = 1 171 | 172 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 173 | ; NoVital = 1 174 | 175 | ; Turn off VITAL compliance checking. Default is checking on. 176 | ; NoVitalCheck = 1 177 | 178 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 179 | ; IgnoreVitalErrors = 1 180 | 181 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 182 | ; Show_VitalChecksWarnings = 0 183 | 184 | ; Turn off PSL assertion warning messages. Default is to show warnings. 185 | ; Show_PslChecksWarnings = 0 186 | 187 | ; Enable parsing of embedded PSL assertions. Default is enabled. 188 | ; EmbeddedPsl = 0 189 | 190 | ; Keep silent about case statement static warnings. 191 | ; Default is to give a warning. 192 | ; NoCaseStaticError = 1 193 | 194 | ; Keep silent about warnings caused by aggregates that are not locally static. 195 | ; Default is to give a warning. 196 | ; NoOthersStaticError = 1 197 | 198 | ; Treat as errors: 199 | ; case statement static warnings 200 | ; warnings caused by aggregates that are not locally static 201 | ; Overrides NoCaseStaticError, NoOthersStaticError settings. 202 | ; PedanticErrors = 1 203 | 204 | ; Turn off inclusion of debugging info within design units. 205 | ; Default is to include debugging info. 206 | ; NoDebug = 1 207 | 208 | ; Turn off "Loading..." messages. Default is messages on. 209 | ; Quiet = 1 210 | 211 | ; Turn on some limited synthesis rule compliance checking. Checks only: 212 | ; -- signals used (read) by a process must be in the sensitivity list 213 | ; CheckSynthesis = 1 214 | 215 | ; Activate optimizations on expressions that do not involve signals, 216 | ; waits, or function/procedure/task invocations. Default is off. 217 | ; ScalarOpts = 1 218 | 219 | ; Turns on lint-style checking. 220 | ; Show_Lint = 1 221 | 222 | ; Require the user to specify a configuration for all bindings, 223 | ; and do not generate a compile time default binding for the 224 | ; component. This will result in an elaboration error of 225 | ; 'component not bound' if the user fails to do so. Avoids the rare 226 | ; issue of a false dependency upon the unused default binding. 227 | ; RequireConfigForAllDefaultBinding = 1 228 | 229 | ; Perform default binding at compile time. 230 | ; Default is to do default binding at load time. 231 | ; BindAtCompile = 1; 232 | 233 | ; Inhibit range checking on subscripts of arrays. Range checking on 234 | ; scalars defined with subtypes is inhibited by default. 235 | ; NoIndexCheck = 1 236 | 237 | ; Inhibit range checks on all (implicit and explicit) assignments to 238 | ; scalar objects defined with subtypes. 239 | ; NoRangeCheck = 1 240 | 241 | ; Set the prefix to be honored for synthesis/coverage pragma recognition. 242 | ; Default is "". 243 | ; AddPragmaPrefix = "" 244 | 245 | ; Ignore synthesis and coverage pragmas with this prefix. 246 | ; Default is "". 247 | ; IgnorePragmaPrefix = "" 248 | 249 | ; Turn on code coverage in VHDL design units. Default is off. 250 | ; Coverage = sbceft 251 | 252 | ; Turn off code coverage in VHDL subprograms. Default is on. 253 | ; CoverSub = 0 254 | 255 | ; Automatically exclude VHDL case statement OTHERS choice branches. 256 | ; This includes OTHERS choices in selected signal assigment statements. 257 | ; Default is to not exclude. 258 | ; CoverExcludeDefault = 1 259 | 260 | ; Control compiler and VOPT optimizations that are allowed when 261 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 262 | ; CoverOpt = 3 263 | 264 | ; Turn on or off clkOpt optimization for code coverage. Default is on. 265 | ; CoverClkOpt = 1 266 | 267 | ; Turn on or off clkOpt optimization builtins for code coverage. Default is on. 268 | ; CoverClkOptBuiltins = 0 269 | 270 | ; Inform code coverage optimizations to respect VHDL 'H' and 'L' 271 | ; values on signals in conditions and expressions, and to not automatically 272 | ; convert them to '1' and '0'. Default is to not convert. 273 | ; CoverRespectHandL = 0 274 | 275 | ; Increase or decrease the maximum number of rows allowed in a UDP table 276 | ; implementing a VHDL condition coverage or expression coverage expression. 277 | ; More rows leads to a longer compile time, but more expressions covered. 278 | ; CoverMaxUDPRows = 192 279 | 280 | ; Increase or decrease the maximum number of input patterns that are present 281 | ; in FEC table. This leads to a longer compile time with more expressions 282 | ; covered with FEC metric. 283 | ; CoverMaxFECRows = 192 284 | 285 | ; Increase or decrease the limit on the size of expressions and conditions 286 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 287 | ; to higher compile, optimize and simulation time, but more expressions and 288 | ; conditions are considered for coverage in the design. FecUdpEffort can 289 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 290 | ; 1 - (low) Only small expressions and conditions considered for coverage. 291 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 292 | ; 3 - (high) Very large expressions and conditions considered for coverage. 293 | ; The default setting is 1 (low). 294 | ; FecUdpEffort = 1 295 | 296 | ; Enable or disable Focused Expression Coverage analysis for conditions and 297 | ; expressions. Focused Expression Coverage data is provided by default when 298 | ; expression and/or condition coverage is active. 299 | ; CoverFEC = 0 300 | 301 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 302 | ; UDP Coverage data is disabled by default when expression and/or condition 303 | ; coverage is active. 304 | ; CoverUDP = 1 305 | 306 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 307 | ; Disabling this would convert non-masking conditions in FEC tables to matching 308 | ; input patterns. 309 | ; CoverREC = 1 310 | 311 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 312 | ; for expression/condition coverage. 313 | ; NOTE: Enabling this may have a negative impact on simulation performance. 314 | ; CoverExpandReductionPrefix = 0 315 | 316 | ; Enable or disable short circuit evaluation of conditions and expressions when 317 | ; condition or expression coverage is active. Short circuit evaluation is enabled 318 | ; by default. 319 | ; CoverShortCircuit = 0 320 | 321 | ; Enable code coverage reporting of code that has been optimized away. 322 | ; The default is not to report. 323 | ; CoverReportCancelled = 1 324 | 325 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 326 | ; Default is no deglitching. 327 | ; CoverDeglitchOn = 1 328 | 329 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 330 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 331 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 332 | ; CoverDeglitchPeriod = 0 333 | 334 | ; Use this directory for compiler temporary files instead of "work/_temp" 335 | ; CompilerTempDir = /tmp 336 | 337 | ; Set this to cause the compilers to force data to be committed to disk 338 | ; when the files are closed. 339 | ; SyncCompilerFiles = 1 340 | 341 | ; Add VHDL-AMS declarations to package STANDARD 342 | ; Default is not to add 343 | ; AmsStandard = 1 344 | 345 | ; Range and length checking will be performed on array indices and discrete 346 | ; ranges, and when violations are found within subprograms, errors will be 347 | ; reported. Default is to issue warnings for violations, because subprograms 348 | ; may not be invoked. 349 | ; NoDeferSubpgmCheck = 0 350 | 351 | ; Turn ON detection of FSMs having single bit current state variable. 352 | ; FsmSingle = 1 353 | 354 | ; Turn off reset state transitions in FSM. 355 | ; FsmResetTrans = 0 356 | 357 | ; Turn ON detection of FSM Implicit Transitions. 358 | ; FsmImplicitTrans = 1 359 | 360 | ; Controls whether or not to show immediate assertions with constant expressions 361 | ; in GUI/report/UCDB etc. By default, immediate assertions with constant 362 | ; expressions are shown in GUI/report/UCDB etc. This does not affect 363 | ; evaluation of immediate assertions. 364 | ; ShowConstantImmediateAsserts = 0 365 | 366 | ; Controls how VHDL basic identifiers are stored with the design unit. 367 | ; Does not make the language case-sensitive, affects only how declarations 368 | ; declared with basic identifiers have their names stored and printed 369 | ; (in the GUI, examine, etc.). 370 | ; Default is to preserve the case as originally depicted in the VHDL source. 371 | ; Value of 0 indicates to change all basic identifiers to lower case. 372 | ; PreserveCase = 0 373 | 374 | ; For Configuration Declarations, controls the effect that USE clauses have 375 | ; on visibility inside the configuration items being configured. If 1 376 | ; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, 377 | ; extend the visibility of objects made visible through USE clauses into nested 378 | ; component configurations. 379 | ; OldVHDLConfigurationVisibility = 0 380 | 381 | ; Allows VHDL configuration declarations to be in a different library from 382 | ; the corresponding configured entity. Default is to not allow this for 383 | ; stricter LRM-compliance. 384 | ; SeparateConfigLibrary = 1; 385 | 386 | ; Determine how mode OUT subprogram parameters of type array and record are treated. 387 | ; If 0 (the default), then only VHDL 2008 will do this initialization. 388 | ; If 1, always initialize the mode OUT parameter to its default value. 389 | ; If 2, do not initialize the mode OUT out parameter. 390 | ; Note that prior to release 10.1, all language versions did not initialize mode 391 | ; OUT array and record type parameters, unless overridden here via this mechanism. 392 | ; In release 10.1 and later, only files compiled with VHDL 2008 will cause this 393 | ; initialization, unless overridden here. 394 | ; InitOutCompositeParam = 0 395 | 396 | ; Generate symbols debugging database in only some special cases to save on 397 | ; the number of files in the library. For other design-units, this database is 398 | ; generated on-demand in vsim. 399 | ; Default is to to generate debugging database for all design-units. 400 | ; SmartDbgSym = 1 401 | 402 | ; Enable or disable automatic creation of missing libraries. 403 | ; Default is 1 (enabled) 404 | ; CreateLib = 1 405 | 406 | ; Describe compilation options according to matching file patterns. 407 | ; File pattern * matches all printing characters other than '/'. 408 | ; File pattern **/x matches all paths containing file/directory x. 409 | ; File pattern x/** matches all paths beginning at directory x. 410 | ; FileOptMap = (**/*.vhd => -2008); 411 | 412 | ; Describe library targets of compilation according to matching file patterns. 413 | ; LibMap = (**/*.vhd => work); 414 | 415 | NoDebug = 0 416 | CheckSynthesis = 0 417 | NoVitalCheck = 0 418 | Optimize_1164 = 1 419 | NoVital = 0 420 | Quiet = 0 421 | Show_source = 0 422 | DisableOpt = 1 423 | ZeroIn = 0 424 | CoverageNoSub = 0 425 | NoCoverage = 1 426 | CoverCells = 0 427 | CoverExcludeDefault = 0 428 | CoverFEC = 1 429 | CoverShortCircuit = 1 430 | CoverOpt = 3 431 | Show_Warning1 = 1 432 | Show_Warning2 = 1 433 | Show_Warning3 = 1 434 | Show_Warning4 = 1 435 | Show_Warning5 = 1 436 | [vlog] 437 | ; Turn off inclusion of debugging info within design units. 438 | ; Default is to include debugging info. 439 | ; NoDebug = 1 440 | 441 | ; Turn off "Loading..." messages. Default is messages on. 442 | ; Quiet = 1 443 | 444 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 445 | ; Default is off. 446 | ; Hazard = 1 447 | 448 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 449 | ; insensitivity for module names. Default is no conversion. 450 | ; UpCase = 1 451 | 452 | ; Activate optimizations on expressions that do not involve signals, 453 | ; waits, or function/procedure/task invocations. Default is off. 454 | ; ScalarOpts = 1 455 | 456 | ; Turns on lint-style checking. 457 | ; Show_Lint = 1 458 | 459 | ; Show source line containing error. Default is off. 460 | ; Show_source = 1 461 | 462 | ; Turn on bad option warning. Default is off. 463 | ; Show_BadOptionWarning = 1 464 | 465 | ; Revert back to IEEE 1364-1995 syntax, default is 0 (off). 466 | ; vlog95compat = 1 467 | 468 | ; Turn off PSL warning messages. Default is to show warnings. 469 | ; Show_PslChecksWarnings = 0 470 | 471 | ; Enable parsing of embedded PSL assertions. Default is enabled. 472 | ; EmbeddedPsl = 0 473 | 474 | ; Enable compiler statistics. Specify one or more arguments: 475 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 476 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 477 | ; Stats = time,cmd,msg 478 | 479 | ; Set the threshold for automatically identifying sparse Verilog memories. 480 | ; A memory with total size in bytes equal to or more than the sparse memory 481 | ; threshold gets marked as sparse automatically, unless specified otherwise 482 | ; in source code or by the +nosparse commandline option of vlog or vopt. 483 | ; The default is 1M. (i.e. memories with total size equal 484 | ; to or greater than 1Mb are marked as sparse) 485 | ; SparseMemThreshold = 1048576 486 | 487 | ; Set the prefix to be honored for synthesis and coverage pragma recognition. 488 | ; Default is "". 489 | ; AddPragmaPrefix = "" 490 | 491 | ; Ignore synthesis and coverage pragmas with this prefix. 492 | ; Default is "". 493 | ; IgnorePragmaPrefix = "" 494 | 495 | ; Set the option to treat all files specified in a vlog invocation as a 496 | ; single compilation unit. The default value is set to 0 which will treat 497 | ; each file as a separate compilation unit as specified in the P1800 draft standard. 498 | ; MultiFileCompilationUnit = 1 499 | 500 | ; Turn on code coverage in Verilog design units. Default is off. 501 | ; Coverage = sbceft 502 | 503 | ; Automatically exclude Verilog case statement default branches. 504 | ; Default is to not automatically exclude defaults. 505 | ; CoverExcludeDefault = 1 506 | 507 | ; Increase or decrease the maximum number of rows allowed in a UDP table 508 | ; implementing a VHDL condition coverage or expression coverage expression. 509 | ; More rows leads to a longer compile time, but more expressions covered. 510 | ; CoverMaxUDPRows = 192 511 | 512 | ; Increase or decrease the maximum number of input patterns that are present 513 | ; in FEC table. This leads to a longer compile time with more expressions 514 | ; covered with FEC metric. 515 | ; CoverMaxFECRows = 192 516 | 517 | ; Enable Multi Bit Expression Coverage in a Design, If design has expression with 518 | ; multi bit operands, this option enables its Expression Coverage. 519 | ; The default value is 0. 520 | ; CoverFecMultiBit = 1 521 | 522 | ; Increase or decrease the limit on the size of expressions and conditions 523 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 524 | ; to higher compile, optimize and simulation time, but more expressions and 525 | ; conditions are considered for coverage in the design. FecUdpEffort can 526 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 527 | ; 1 - (low) Only small expressions and conditions considered for coverage. 528 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 529 | ; 3 - (high) Very large expressions and conditions considered for coverage. 530 | ; The default setting is 1 (low). 531 | ; FecUdpEffort = 1 532 | 533 | ; Enable or disable Focused Expression Coverage analysis for conditions and 534 | ; expressions. Focused Expression Coverage data is provided by default when 535 | ; expression and/or condition coverage is active. 536 | ; CoverFEC = 0 537 | 538 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 539 | ; UDP Coverage data is disabled by default when expression and/or condition 540 | ; coverage is active. 541 | ; CoverUDP = 1 542 | 543 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 544 | ; Disabling this would convert non-masking conditions in FEC tables to matching 545 | ; input patterns. 546 | ; CoverREC = 1 547 | 548 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 549 | ; for expression/condition coverage. 550 | ; NOTE: Enabling this may have a negative impact on simulation performance. 551 | ; CoverExpandReductionPrefix = 0 552 | 553 | ; Enable or disable short circuit evaluation of conditions and expressions when 554 | ; condition or expression coverage is active. Short circuit evaluation is enabled 555 | ; by default. 556 | ; CoverShortCircuit = 0 557 | 558 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 559 | ; Default is no deglitching. 560 | ; CoverDeglitchOn = 1 561 | 562 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 563 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 564 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 565 | ; CoverDeglitchPeriod = 0 566 | 567 | ; Turn on code coverage in VLOG `celldefine modules, modules containing 568 | ; specify blocks, and modules included using vlog -v and -y. Default is off. 569 | ; CoverCells = 1 570 | 571 | ; Enable code coverage reporting of code that has been optimized away. 572 | ; The default is not to report. 573 | ; CoverReportCancelled = 1 574 | 575 | ; Control compiler and VOPT optimizations that are allowed when 576 | ; code coverage is on. This is a number from 0 to 5, with the following 577 | ; meanings (the default is 3): 578 | ; 5 -- All allowable optimizations are on. 579 | ; 4 -- Turn off removing unreferenced code. 580 | ; 3 -- Turn off process, always block and if statement merging. 581 | ; 2 -- Turn off expression optimization, converting primitives 582 | ; to continuous assignments, VHDL subprogram inlining. 583 | ; and VHDL clkOpt (converting FF's to builtins). 584 | ; 1 -- Turn off continuous assignment optimizations and clock suppression. 585 | ; 0 -- Turn off Verilog module inlining and VHDL arch inlining. 586 | ; HOWEVER, if fsm coverage is turned on, optimizations will be forced to 587 | ; level 3, with also turning off converting primitives to continuous assigns. 588 | ; CoverOpt = 3 589 | 590 | ; Specify the override for the default value of "cross_num_print_missing" 591 | ; option for the Cross in Covergroups. If not specified then LRM default 592 | ; value of 0 (zero) is used. This is a compile time option. 593 | ; SVCrossNumPrintMissingDefault = 0 594 | 595 | ; Setting following to 1 would cause creation of variables which 596 | ; would represent the value of Coverpoint expressions. This is used 597 | ; in conjunction with "SVCoverpointExprVariablePrefix" option 598 | ; in the modelsim.ini 599 | ; EnableSVCoverpointExprVariable = 0 600 | 601 | ; Specify the override for the prefix used in forming the variable names 602 | ; which represent the Coverpoint expressions. This is used in conjunction with 603 | ; "EnableSVCoverpointExprVariable" option of the modelsim.ini 604 | ; The default prefix is "expr". 605 | ; The variable name is 606 | ; variable name => _ 607 | ; SVCoverpointExprVariablePrefix = expr 608 | 609 | ; Override for the default value of the SystemVerilog covergroup, 610 | ; coverpoint, and cross option.goal (defined to be 100 in the LRM). 611 | ; NOTE: It does not override specific assignments in SystemVerilog 612 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" 613 | ; in the [vsim] section can override this value. 614 | ; SVCovergroupGoalDefault = 100 615 | 616 | ; Override for the default value of the SystemVerilog covergroup, 617 | ; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) 618 | ; NOTE: It does not override specific assignments in SystemVerilog 619 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" 620 | ; in the [vsim] section can override this value. 621 | ; SVCovergroupTypeGoalDefault = 100 622 | 623 | ; Specify the override for the default value of "strobe" option for the 624 | ; Covergroup Type. This is a compile time option which forces "strobe" to 625 | ; a user specified default value and supersedes SystemVerilog specified 626 | ; default value of '0'(zero). NOTE: This can be overriden by a runtime 627 | ; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. 628 | ; SVCovergroupStrobeDefault = 0 629 | 630 | ; Specify the override for the default value of "per_instance" option for the 631 | ; Covergroup variables. This is a compile time option which forces "per_instance" 632 | ; to a user specified default value and supersedes SystemVerilog specified 633 | ; default value of '0'(zero). 634 | ; SVCovergroupPerInstanceDefault = 0 635 | 636 | ; Specify the override for the default value of "get_inst_coverage" option for the 637 | ; Covergroup variables. This is a compile time option which forces 638 | ; "get_inst_coverage" to a user specified default value and supersedes 639 | ; SystemVerilog specified default value of '0'(zero). 640 | ; SVCovergroupGetInstCoverageDefault = 0 641 | 642 | ; 643 | ; A space separated list of resource libraries that contain precompiled 644 | ; packages. The behavior is identical to using the "-L" switch. 645 | ; 646 | ; LibrarySearchPath = [ ...] 647 | LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact 648 | 649 | ; The behavior is identical to the "-mixedansiports" switch. Default is off. 650 | ; MixedAnsiPorts = 1 651 | 652 | ; Enable SystemVerilog 3.1a $typeof() function. Default is off. 653 | ; EnableTypeOf = 1 654 | 655 | ; Only allow lower case pragmas. Default is disabled. 656 | ; AcceptLowerCasePragmaOnly = 1 657 | 658 | ; Set the maximum depth permitted for a recursive include file nesting. 659 | ; IncludeRecursionDepthMax = 5 660 | 661 | ; Turn ON detection of FSMs having single bit current state variable. 662 | ; FsmSingle = 1 663 | 664 | ; Turn off reset state transitions in FSM. 665 | ; FsmResetTrans = 0 666 | 667 | ; Turn off detections of FSMs having x-assignment. 668 | ; FsmXAssign = 0 669 | 670 | ; Turn ON detection of FSM Implicit Transitions. 671 | ; FsmImplicitTrans = 1 672 | 673 | ; List of file suffixes which will be read as SystemVerilog. White space 674 | ; in extensions can be specified with a back-slash: "\ ". Back-slashes 675 | ; can be specified with two consecutive back-slashes: "\\"; 676 | ; SvFileSuffixes = sv svp svh 677 | 678 | ; This setting is the same as the vlog -sv command line switch. 679 | ; Enables SystemVerilog features and keywords when true (1). 680 | ; When false (0), the rules of IEEE Std 1364-2005 are followed and 681 | ; SystemVerilog keywords are ignored. 682 | ; Svlog = 0 683 | 684 | ; Prints attribute placed upon SV packages during package import 685 | ; when true (1). The attribute will be ignored when this 686 | ; entry is false (0). The attribute name is "package_load_message". 687 | ; The value of this attribute is a string literal. 688 | ; Default is true (1). 689 | ; PrintSVPackageLoadingAttribute = 1 690 | 691 | ; Do not show immediate assertions with constant expressions in 692 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 693 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 694 | ; evaluation of immediate assertions. 695 | ; ShowConstantImmediateAsserts = 0 696 | 697 | ; Controls if untyped parameters that are initialized with values greater 698 | ; than 2147483647 are mapped to generics of type INTEGER or ignored. 699 | ; If mapped to VHDL Integers, values greater than 2147483647 700 | ; are mapped to negative values. 701 | ; Default is to map these parameter to generic of type INTEGER 702 | ; ForceUnsignedToVHDLInteger = 1 703 | 704 | ; Enable AMS wreal (wired real) extensions. Default is 0. 705 | ; WrealType = 1 706 | 707 | ; Controls SystemVerilog Language Extensions. These options enable 708 | ; some non-LRM compliant behavior. 709 | ; SvExtensions = [+|-][,[+|-]*] 710 | 711 | ; Generate symbols debugging database in only some special cases to save on 712 | ; the number of files in the library. For other design-units, this database is 713 | ; generated on-demand in vsim. 714 | ; Default is to to generate debugging database for all design-units. 715 | ; SmartDbgSym = 1 716 | 717 | ; Controls how $unit library entries are named. Valid options are: 718 | ; "file" (generate name based on the first file on the command line) 719 | ; "du" (generate name based on first design unit following an item 720 | ; found in $unit scope) 721 | ; CUAutoName = file 722 | 723 | ; Enable or disable automatic creation of missing libraries. 724 | ; Default is 1 (enabled) 725 | ; CreateLib = 1 726 | 727 | vlog95compat = 0 728 | Vlog01Compat = 0 729 | Svlog = 0 730 | CoverCells = 0 731 | CoverExcludeDefault = 0 732 | CoverFEC = 1 733 | CoverShortCircuit = 1 734 | CoverOpt = 3 735 | OptionFile = D:/research/my_verilog_projects/clock_div/vlog.opt 736 | Quiet = 0 737 | Show_source = 0 738 | NoDebug = 0 739 | Hazard = 0 740 | UpCase = 0 741 | DisableOpt = 1 742 | ZeroIn = 0 743 | [sccom] 744 | ; Enable use of SCV include files and library. Default is off. 745 | ; UseScv = 1 746 | 747 | ; Add C++ compiler options to the sccom command line by using this variable. 748 | ; CppOptions = -g 749 | 750 | ; Use custom C++ compiler located at this path rather than the default path. 751 | ; The path should point directly at a compiler executable. 752 | ; CppPath = /usr/bin/g++ 753 | 754 | ; Specify the compiler version from the list of support GNU compilers. 755 | ; examples 4.7.4, 5.3.0 756 | ; CppInstall = 5.3.0 757 | 758 | ; Enable verbose messages from sccom. Default is off. 759 | ; SccomVerbose = 1 760 | 761 | ; sccom logfile. Default is no logfile. 762 | ; SccomLogfile = sccom.log 763 | 764 | ; Enable use of SC_MS include files and library. Default is off. 765 | ; UseScMs = 1 766 | 767 | ; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. 768 | ; Sc22Mode = 1 769 | 770 | ; Enable compiler statistics. Specify one or more arguments: 771 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 772 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 773 | ; Stats = time,cmd,msg 774 | 775 | ; Enable or disable automatic creation of missing libraries. 776 | ; Default is 1 (enabled) 777 | ; CreateLib = 1 778 | 779 | ; Enable use of UVMC library. Default is off. 780 | ; UseUvmc = 1 781 | 782 | [vopt] 783 | ; Turn on code coverage in vopt. Default is off. 784 | ; Coverage = sbceft 785 | 786 | ; enable or disable param saving in UCDB. 787 | ; CoverageSaveParam = 0 788 | 789 | ; Control compiler optimizations that are allowed when 790 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 791 | ; CoverOpt = 3 792 | 793 | ; Controls set of CoverConstructs that are being considered for Coverage 794 | ; Collection. 795 | ; Some of Valid options are: default,set1,set2 796 | ; Covermode = default 797 | 798 | ; Controls set of HDL cover constructs that would be considered(or not considered) 799 | ; for Coverage Collection. (Default corresponds to covermode default). 800 | ; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs". 801 | ; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva 802 | 803 | ; Increase or decrease the maximum number of rows allowed in a UDP table 804 | ; implementing a VHDL condition coverage or expression coverage expression. 805 | ; More rows leads to a longer compile time, but more expressions covered. 806 | ; CoverMaxUDPRows = 192 807 | 808 | ; Increase or decrease the maximum number of input patterns that are present 809 | ; in FEC table. This leads to a longer compile time with more expressions 810 | ; covered with FEC metric. 811 | ; CoverMaxFECRows = 192 812 | 813 | ; Enable Multi Bit Expression Coverage in a Design, If design has expression with 814 | ; multi bit operands, this option enables its Expression Coverage. 815 | ; The default value is 0. 816 | ; CoverFecMultiBit = 1 817 | 818 | ; Increase or decrease the limit on the size of expressions and conditions 819 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 820 | ; to higher compile, optimize and simulation time, but more expressions and 821 | ; conditions are considered for coverage in the design. FecUdpEffort can 822 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 823 | ; 1 - (low) Only small expressions and conditions considered for coverage. 824 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 825 | ; 3 - (high) Very large expressions and conditions considered for coverage. 826 | ; The default setting is 1 (low). 827 | ; FecUdpEffort = 1 828 | 829 | ; Enable code coverage reporting of code that has been optimized away. 830 | ; The default is not to report. 831 | ; CoverReportCancelled = 1 832 | 833 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 834 | ; Default is no deglitching. 835 | ; CoverDeglitchOn = 1 836 | 837 | ; Enable compiler statistics. Specify one or more arguments: 838 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 839 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 840 | ; Stats = time,cmd,msg 841 | 842 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 843 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 844 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 845 | ; CoverDeglitchPeriod = 0 846 | 847 | ; Do not show immediate assertions with constant expressions in 848 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 849 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 850 | ; evaluation of immediate assertions. 851 | ; ShowConstantImmediateAsserts = 0 852 | 853 | ; Set the maximum number of iterations permitted for a generate loop. 854 | ; Restricting this permits the implementation to recognize infinite 855 | ; generate loops. 856 | ; GenerateLoopIterationMax = 100000 857 | 858 | ; Set the maximum depth permitted for a recursive generate instantiation. 859 | ; Restricting this permits the implementation to recognize infinite 860 | ; recursions. 861 | ; GenerateRecursionDepthMax = 200 862 | 863 | ; Set the number of processes created during the code generation phase. 864 | ; By default a heuristic is used to set this value. This may be set to 0 865 | ; to disable this feature completely. 866 | ; ParallelJobs = 0 867 | 868 | ; Controls SystemVerilog Language Extensions. These options enable 869 | ; some non-LRM compliant behavior. 870 | ; SvExtensions = [+|-][,[+|-]*] 871 | 872 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 873 | ; This gives global visibility to all symbols in the shared objects, 874 | ; meaning that subsequently loaded shared objects can bind to symbols 875 | ; in the global shared objects. The list of shared objects should 876 | ; be whitespace delimited. This option is not supported on the 877 | ; Windows or AIX platforms. 878 | ; GlobalSharedObjectList = example1.so example2.so example3.so 879 | 880 | ; Disable SystemVerilog elaboration system task messages 881 | ; IgnoreSVAInfo = 1 882 | ; IgnoreSVAWarning = 1 883 | ; IgnoreSVAError = 1 884 | ; IgnoreSVAFatal = 1 885 | 886 | ; Enable or disable automatic creation of missing libraries. 887 | ; Default is 1 (enabled) 888 | ; CreateLib = 1 889 | 890 | [vsim] 891 | ; vopt flow 892 | ; Set to turn on automatic optimization of a design. 893 | ; Default is on 894 | VoptFlow = 1 895 | 896 | ; Simulator resolution 897 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 898 | Resolution = ns 899 | 900 | ; Disable certain code coverage exclusions automatically. 901 | ; Assertions and FSM are exluded from the code coverage by default 902 | ; Set AutoExclusionsDisable = fsm to enable code coverage for fsm 903 | ; Set AutoExclusionsDisable = assertions to enable code coverage for assertions 904 | ; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions 905 | ; Or specify comma or space separated list 906 | ;AutoExclusionsDisable = fsm,assertions 907 | 908 | ; User time unit for run commands 909 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 910 | ; unit specified for Resolution. For example, if Resolution is 100ps, 911 | ; then UserTimeUnit defaults to ps. 912 | ; Should generally be set to default. 913 | UserTimeUnit = default 914 | 915 | ; Default run length 916 | RunLength = 100 917 | 918 | ; Maximum iterations that can be run without advancing simulation time 919 | IterationLimit = 10000000 920 | 921 | ; Specify libraries to be searched for precompiled modules 922 | ; LibrarySearchPath = [ ...] 923 | 924 | ; Set XPROP assertion fail limit. Default is 5. 925 | ; Any positive integer, -1 for infinity. 926 | ; XpropAssertionLimit = 5 927 | 928 | ; Control PSL and Verilog Assume directives during simulation 929 | ; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts 930 | ; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts 931 | ; SimulateAssumeDirectives = 1 932 | 933 | ; Control the simulation of PSL and SVA 934 | ; These switches can be overridden by the vsim command line switches: 935 | ; -psl, -nopsl, -sva, -nosva. 936 | ; Set SimulatePSL = 0 to disable PSL simulation 937 | ; Set SimulatePSL = 1 to enable PSL simulation (default) 938 | ; SimulatePSL = 1 939 | ; Set SimulateSVA = 0 to disable SVA simulation 940 | ; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) 941 | ; SimulateSVA = 1 942 | 943 | ; Control SVA and VHDL immediate assertion directives during simulation 944 | ; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts 945 | ; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts 946 | ; SimulateImmedAsserts = 1 947 | 948 | ; License feature mappings for Verilog and VHDL 949 | ; qhsimvh Single language VHDL license 950 | ; qhsimvl Single language Verilog license 951 | ; msimhdlsim Language neutral license for either Verilog or VHDL 952 | ; msimhdlmix Second language only, language neutral license for either 953 | ; Verilog or VHDL 954 | ; 955 | ; Directives to license manager can be set either as single value or as 956 | ; space separated multi-values: 957 | ; vhdl Immediately checkout and hold a VHDL license (i.e., one of 958 | ; qhsimvh, msimhdlsim, or msimhdlmix) 959 | ; vlog Immediately checkout and hold a Verilog license (i.e., one of 960 | ; qhsimvl, msimhdlsim, or msimhdlmix) 961 | ; plus Immediately checkout and hold a VHDL license and a Verilog license 962 | ; noqueue Do not wait in the license queue when a license is not available 963 | ; viewsim Try for viewer license but accept simulator license(s) instead 964 | ; of queuing for viewer license (PE ONLY) 965 | ; noviewer Disable checkout of msimviewer license feature (PE ONLY) 966 | ; noslvhdl Disable checkout of qhsimvh license feature 967 | ; noslvlog Disable checkout of qhsimvl license feature 968 | ; nomix Disable checkout of msimhdlmix license feature 969 | ; nolnl Disable checkout of msimhdlsim license feature 970 | ; mixedonly Disable checkout of qhsimvh and qhsimvl license features 971 | ; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features 972 | ; 973 | ; Examples (remove ";" comment character to activate licensing directives): 974 | ; Single directive: 975 | ; License = plus 976 | ; Multi-directive (Note: space delimited directives): 977 | ; License = noqueue plus 978 | 979 | ; Severity level of a VHDL assertion message or of a SystemVerilog severity system task 980 | ; which will cause a running simulation to stop. 981 | ; VHDL assertions and SystemVerilog severity system task that occur with the 982 | ; given severity or higher will cause a running simulation to stop. 983 | ; This value is ignored during elaboration. 984 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 985 | BreakOnAssertion = 3 986 | 987 | ; Severity level of a tool message which will cause a running simulation to 988 | ; stop. This value is ignored during elaboration. Default is to not break. 989 | ; 0 = Note 1 = Warning 2 = Error 3 = Fatal 990 | ;BreakOnMessage = 2 991 | 992 | ; The class debug feature enables more visibility and tracking of class instances 993 | ; during simulation. By default this feature is disabled (0). To enable this 994 | ; feature set ClassDebug to 1. 995 | ; ClassDebug = 1 996 | 997 | ; Message Format conversion specifications: 998 | ; %S - Severity Level of message/assertion 999 | ; %R - Text of message 1000 | ; %T - Time of message 1001 | ; %D - Delta value (iteration number) of Time 1002 | ; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected 1003 | ; %i - Instance/Region/Signal pathname with Process name (if available) 1004 | ; %I - shorthand for one of these: 1005 | ; " %K: %i" 1006 | ; " %K: %i File: %F" (when path is not Process or Signal) 1007 | ; except that the %i in this case does not report the Process name 1008 | ; %O - Process name 1009 | ; %P - Instance/Region path without leaf process 1010 | ; %F - File name 1011 | ; %L - Line number; if assertion message, then line number of assertion or, if 1012 | ; assertion is in a subprogram, line from which the call is made 1013 | ; %u - Design unit name in form library.primary 1014 | ; %U - Design unit name in form library.primary(secondary) 1015 | ; %% - The '%' character itself 1016 | ; 1017 | ; If specific format for Severity Level is defined, use that format. 1018 | ; Else, for a message that occurs during elaboration: 1019 | ; -- Failure/Fatal message in VHDL region that is not a Process, and in 1020 | ; certain non-VHDL regions, uses MessageFormatBreakLine; 1021 | ; -- Failure/Fatal message otherwise uses MessageFormatBreak; 1022 | ; -- Note/Warning/Error message uses MessageFormat. 1023 | ; Else, for a message that occurs during runtime and triggers a breakpoint because 1024 | ; of the BreakOnAssertion setting: 1025 | ; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; 1026 | ; -- otherwise uses MessageFormatBreak. 1027 | ; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. 1028 | ; 1029 | ; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" 1030 | ; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" 1031 | ; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 1032 | ; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 1033 | ; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 1034 | ; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" 1035 | ; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 1036 | ; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 1037 | 1038 | ; Error File - alternate file for storing error messages 1039 | ; ErrorFile = error.log 1040 | 1041 | ; Simulation Breakpoint messages 1042 | ; This flag controls the display of function names when reporting the location 1043 | ; where the simulator stops because of a breakpoint or fatal error. 1044 | ; Example with function name: # Break in Process ctr at counter.vhd line 44 1045 | ; Example without function name: # Break at counter.vhd line 44 1046 | ; Default value is 1. 1047 | ShowFunctions = 1 1048 | 1049 | ; Default radix for all windows and commands. 1050 | ; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned 1051 | ; Flags may be one of: enumnumeric, showbase, wreal 1052 | DefaultRadix = hexadecimal 1053 | DefaultRadixFlags = showbase 1054 | ; Set to 1 for make the signal_force VHDL and Verilog functions use the 1055 | ; default radix when processing the force value. Prior to 10.2 signal_force 1056 | ; used the default radix, now it always uses symbolic unless value explicitly indicates base 1057 | ;SignalForceFunctionUseDefaultRadix = 0 1058 | 1059 | ; VSIM Startup command 1060 | ; Startup = do startup.do 1061 | 1062 | ; VSIM Shutdown file 1063 | ; Filename to save u/i formats and configurations. 1064 | ; ShutdownFile = restart.do 1065 | ; To explicitly disable auto save: 1066 | ; ShutdownFile = --disable-auto-save 1067 | 1068 | ; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. 1069 | ; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. 1070 | ; BatchMode = 1 1071 | 1072 | ; File for saving command transcript when -batch option used 1073 | ; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero 1074 | ; default is unset so command transcript only goes to stdout for better performance 1075 | ; BatchTranscriptFile = transcript 1076 | 1077 | ; File for saving command transcript, this option is ignored when -batch option is used 1078 | TranscriptFile = transcript 1079 | 1080 | ; Transcript file long line wrapping mode(s) 1081 | ; mode == 0 :: no wrapping, line recorded as is 1082 | ; mode == 1 :: wrap at first whitespace after WSColumn 1083 | ; or at Column. 1084 | ; mode == 2 :: wrap as above, but add continuation 1085 | ; character ('\') at end of each wrapped line 1086 | ; 1087 | ; WrapMode = 0 1088 | ; WrapColumn = 30000 1089 | ; WrapWSColumn = 27000 1090 | 1091 | ; File for saving command history 1092 | ; CommandHistory = cmdhist.log 1093 | 1094 | ; Specify whether paths in simulator commands should be described 1095 | ; in VHDL or Verilog format. 1096 | ; For VHDL, PathSeparator = / 1097 | ; For Verilog, PathSeparator = . 1098 | ; Must not be the same character as DatasetSeparator. 1099 | PathSeparator = / 1100 | 1101 | ; Specify the dataset separator for fully rooted contexts. 1102 | ; The default is ':'. For example: sim:/top 1103 | ; Must not be the same character as PathSeparator. 1104 | DatasetSeparator = : 1105 | 1106 | ; Specify a unique path separator for the Signal Spy set of functions. 1107 | ; The default will be to use the PathSeparator variable. 1108 | ; Must not be the same character as DatasetSeparator. 1109 | ; SignalSpyPathSeparator = / 1110 | 1111 | ; Used to control parsing of HDL identifiers input to the tool. 1112 | ; This includes CLI commands, vsim/vopt/vlog/vcom options, 1113 | ; string arguments to FLI/VPI/DPI calls, etc. 1114 | ; If set to 1, accept either Verilog escaped Id syntax or 1115 | ; VHDL extended id syntax, regardless of source language. 1116 | ; If set to 0, the syntax of the source language must be used. 1117 | ; Each identifier in a hierarchical name may need different syntax, 1118 | ; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or 1119 | ; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" 1120 | ; GenerousIdentifierParsing = 1 1121 | 1122 | ; Disable VHDL assertion messages 1123 | ; IgnoreNote = 1 1124 | ; IgnoreWarning = 1 1125 | ; IgnoreError = 1 1126 | ; IgnoreFailure = 1 1127 | 1128 | ; Disable SystemVerilog assertion messages 1129 | ; IgnoreSVAInfo = 1 1130 | ; IgnoreSVAWarning = 1 1131 | ; IgnoreSVAError = 1 1132 | ; IgnoreSVAFatal = 1 1133 | 1134 | ; Do not print any additional information from Severity System tasks. 1135 | ; Only the message provided by the user is printed along with severity 1136 | ; information. 1137 | ; SVAPrintOnlyUserMessage = 1; 1138 | 1139 | ; Default force kind. May be freeze, drive, deposit, or default 1140 | ; or in other terms, fixed, wired, or charged. 1141 | ; A value of "default" will use the signal kind to determine the 1142 | ; force kind, drive for resolved signals, freeze for unresolved signals 1143 | ; DefaultForceKind = freeze 1144 | 1145 | ; Control the iteration of events when a VHDL signal is forced to a value 1146 | ; This flag can be set to honour the signal update event in next iteration, 1147 | ; the default is to update and propagate in the same iteration. 1148 | ; ForceSigNextIter = 1 1149 | 1150 | ; Enable simulation statistics. Specify one or more arguments: 1151 | ; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] 1152 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 1153 | ; Stats = time,cmd,msg 1154 | 1155 | ; If zero, open files when elaborated; otherwise, open files on 1156 | ; first read or write. Default is 0. 1157 | ; DelayFileOpen = 1 1158 | 1159 | ; Control VHDL files opened for write. 1160 | ; 0 = Buffered, 1 = Unbuffered 1161 | UnbufferedOutput = 0 1162 | 1163 | ; Control the number of VHDL files open concurrently. 1164 | ; This number should always be less than the current ulimit 1165 | ; setting for max file descriptors. 1166 | ; 0 = unlimited 1167 | ConcurrentFileLimit = 40 1168 | 1169 | ; If nonzero, close files as soon as there is either an explicit call to 1170 | ; file_close, or when the file variable's scope is closed. When zero, a 1171 | ; file opened in append mode is not closed in case it is immediately 1172 | ; reopened in append mode; otherwise, the file will be closed at the 1173 | ; point it is reopened. 1174 | ; AppendClose = 1 1175 | 1176 | ; Control the number of hierarchical regions displayed as 1177 | ; part of a signal name shown in the Wave window. 1178 | ; A value of zero tells VSIM to display the full name. 1179 | ; The default is 0. 1180 | ; WaveSignalNameWidth = 0 1181 | 1182 | ; Turn off warnings when changing VHDL constants and generics 1183 | ; Default is 1 to generate warning messages 1184 | ; WarnConstantChange = 0 1185 | 1186 | ; Turn off warnings from accelerated versions of the std_logic_arith, 1187 | ; std_logic_unsigned, and std_logic_signed packages. 1188 | ; StdArithNoWarnings = 1 1189 | 1190 | ; Turn off warnings from accelerated versions of the IEEE numeric_std 1191 | ; and numeric_bit packages. 1192 | ; NumericStdNoWarnings = 1 1193 | 1194 | ; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names 1195 | ; in the design hierarchy. 1196 | ; This style is controlled by the value of the GenerateFormat 1197 | ; value described next. Default is to use new-style names, which 1198 | ; comprise the generate statement label, '(', the value of the generate 1199 | ; parameter, and a closing ')'. 1200 | ; Set this to 1 to use old-style names. 1201 | ; OldVhdlForGenNames = 1 1202 | 1203 | ; Control the format of the old-style VHDL FOR generate statement region 1204 | ; name for each iteration. Do not quote the value. 1205 | ; The format string here must contain the conversion codes %s and %d, 1206 | ; in that order, and no other conversion codes. The %s represents 1207 | ; the generate statement label; the %d represents the generate parameter value 1208 | ; at a particular iteration (this is the position number if the generate parameter 1209 | ; is of an enumeration type). Embedded whitespace is allowed (but discouraged); 1210 | ; leading and trailing whitespace is ignored. 1211 | ; Application of the format must result in a unique region name over all 1212 | ; loop iterations for a particular immediately enclosing scope so that name 1213 | ; lookup can function properly. The default is %s__%d. 1214 | ; GenerateFormat = %s__%d 1215 | 1216 | ; Enable more efficient logging of VHDL Variables. 1217 | ; Logging VHDL variables without this enabled, while possible, is very 1218 | ; inefficient. Enabling this will provide a more efficient logging methodology 1219 | ; at the expense of more memory usage. By default this feature is disabled (0). 1220 | ; To enabled this feature, set this variable to 1. 1221 | ; VhdlVariableLogging = 1 1222 | 1223 | ; Enable logging of VHDL access type variables and their designated objects. 1224 | ; This setting will allow both variables of an access type ("access variables") 1225 | ; and their designated objects ("access objects") to be logged. Logging a 1226 | ; variable of an access type will automatically also cause the designated 1227 | ; object(s) of that variable to be logged as the simulation progresses. 1228 | ; Further, enabling this allows access objects to be logged by name. By default 1229 | ; this feature is disabled (0). To enable this feature, set this variable to 1. 1230 | ; Enabling this will automatically enable the VhdlVariableLogging feature also. 1231 | ; AccessObjDebug = 1 1232 | 1233 | ; Make each VHDL package in a PDU has its own separate copy of the package instead 1234 | ; of sharing the package between PDUs. The default is to share packages. 1235 | ; To ensure that each PDU has its own set of packages, set this variable to 1. 1236 | ; VhdlSeparatePduPackage = 1 1237 | 1238 | ; Specify whether checkpoint files should be compressed. 1239 | ; The default is 1 (compressed). 1240 | ; CheckpointCompressMode = 0 1241 | 1242 | ; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. 1243 | ; Use custom gcc compiler located at this path rather than the default path. 1244 | ; The path should point directly at a compiler executable. 1245 | ; DpiCppPath = /bin/gcc 1246 | ; 1247 | ; Specify the compiler version from the list of support GNU compilers. 1248 | ; examples 4.7.4, 5.3.0 1249 | ; DpiCppInstall = 5.3.0 1250 | 1251 | ; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. 1252 | ; The term "out-of-the-blue" refers to SystemVerilog export function calls 1253 | ; made from C functions that don't have the proper context setup 1254 | ; (as is the case when running under "DPI-C" import functions). 1255 | ; When this is enabled, one can call a DPI export function 1256 | ; (but not task) from any C code. 1257 | ; the setting of this variable can be one of the following values: 1258 | ; 0 : dpioutoftheblue call is disabled (default) 1259 | ; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. 1260 | ; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. 1261 | ; DpiOutOfTheBlue = 1 1262 | 1263 | ; Specify whether continuous assignments are run before other normal priority 1264 | ; processes scheduled in the same iteration. This event ordering minimizes race 1265 | ; differences between optimized and non-optimized designs, and is the default 1266 | ; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set 1267 | ; ImmediateContinuousAssign to 0. 1268 | ; The default is 1 (enabled). 1269 | ; ImmediateContinuousAssign = 0 1270 | 1271 | ; List of dynamically loaded objects for Verilog PLI applications 1272 | ; Veriuser = veriuser.sl 1273 | 1274 | ; Which default VPI object model should the tool conform to? 1275 | ; The 1364 modes are Verilog-only, for backwards compatibility with older 1276 | ; libraries, and SystemVerilog objects are not available in these modes. 1277 | ; 1278 | ; In the absence of a user-specified default, the tool default is the 1279 | ; latest available LRM behavior. 1280 | ; Options for PliCompatDefault are: 1281 | ; VPI_COMPATIBILITY_VERSION_1364v1995 1282 | ; VPI_COMPATIBILITY_VERSION_1364v2001 1283 | ; VPI_COMPATIBILITY_VERSION_1364v2005 1284 | ; VPI_COMPATIBILITY_VERSION_1800v2005 1285 | ; VPI_COMPATIBILITY_VERSION_1800v2008 1286 | ; 1287 | ; Synonyms for each string are also recognized: 1288 | ; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) 1289 | ; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) 1290 | ; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) 1291 | ; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) 1292 | ; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) 1293 | 1294 | 1295 | ; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 1296 | 1297 | ; Specify whether the Verilog system task $fopen or vpi_mcd_open() 1298 | ; will create directories that do not exist when opening the file 1299 | ; in "a" or "w" mode. 1300 | ; The default is 0 (do not create non-existent directories) 1301 | ; CreateDirForFileAccess = 1 1302 | 1303 | ; Specify default options for the restart command. Options can be one 1304 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions 1305 | ; DefaultRestartOptions = -force 1306 | 1307 | 1308 | ; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. 1309 | ; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe. 1310 | ; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". 1311 | ; The list of options must be delimited by commas, without spaces or tabs. 1312 | ; 1313 | ; Some examples 1314 | ; To turn on all available UVM-aware debug features: 1315 | ; UVMControl = all 1316 | ; To turn on the struct window, mesage logging, and transaction logging: 1317 | ; UVMControl = struct,msglog,trlog 1318 | ; To turn on all options except certe: 1319 | ; UVMControl = all,-certe 1320 | ; To completely disable all UVM-aware debug functionality: 1321 | ; UVMControl = disable 1322 | 1323 | ; Specify the WildcardFilter setting. 1324 | ; A space separated list of object types to be excluded when performing 1325 | ; wildcard matches with log, wave, etc commands. The default value for this variable is: 1326 | ; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" 1327 | ; See "Using the WildcardFilter Preference Variable" in the documentation for 1328 | ; details on how to use this variable and for descriptions of the filter types. 1329 | WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile 1330 | 1331 | ; Specify the WildcardSizeThreshold setting. 1332 | ; This integer setting specifies the size at which objects will be excluded when 1333 | ; performing wildcard matches with log, wave, etc commands. Objects of size equal 1334 | ; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard 1335 | ; matches. The size is a simple calculation of number of bits or items in the object. 1336 | ; The default value is 8k (8192). Setting this value to 0 will disable the checking 1337 | ; of object size against this threshold and allow all objects of any size to be logged. 1338 | WildcardSizeThreshold = 8192 1339 | 1340 | ; Specify whether warning messages are output when objects are filtered out due to the 1341 | ; WildcardSizeThreshold. The default is 0 (no messages generated). 1342 | WildcardSizeThresholdVerbose = 0 1343 | 1344 | ; Turn on (1) or off (0) WLF file compression. 1345 | ; The default is 1 (compress WLF file). 1346 | ; WLFCompress = 0 1347 | 1348 | ; Specify whether to save all design hierarchy (1) in the WLF file 1349 | ; or only regions containing logged signals (0). 1350 | ; The default is 0 (save only regions with logged signals). 1351 | ; WLFSaveAllRegions = 1 1352 | 1353 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 1354 | ; to the specified amount of simulation time. When the limit is exceeded 1355 | ; the earliest times get truncated from the file. 1356 | ; If both time and size limits are specified the most restrictive is used. 1357 | ; UserTimeUnits are used if time units are not specified. 1358 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 1359 | ; WLFTimeLimit = 0 1360 | 1361 | ; WLF file size limit. Limit WLF file size, as closely as possible, 1362 | ; to the specified number of megabytes. If both time and size limits 1363 | ; are specified then the most restrictive is used. 1364 | ; The default is 0 (no limit). 1365 | ; WLFSizeLimit = 1000 1366 | 1367 | ; Specify whether or not a WLF file should be deleted when the 1368 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 1369 | ; The default is 0 (do not delete WLF file when simulation ends). 1370 | ; WLFDeleteOnQuit = 1 1371 | 1372 | ; Specify whether or not a WLF file should be optimized during 1373 | ; simulation. If set to 0, the WLF file will not be optimized. 1374 | ; The default is 1, optimize the WLF file. 1375 | ; WLFOptimize = 0 1376 | 1377 | ; Specify the name of the WLF file. 1378 | ; The default is vsim.wlf 1379 | ; WLFFilename = vsim.wlf 1380 | 1381 | ; Specify whether to lock the WLF file. 1382 | ; Locking the file prevents other invocations of ModelSim/Questa tools from 1383 | ; inadvertently overwriting the WLF file. 1384 | ; The default is 1, lock the WLF file. 1385 | ; WLFFileLock = 0 1386 | 1387 | ; Specify the update interval for the WLF file in live simulation. 1388 | ; The interval is given in seconds. 1389 | ; The value is the smallest interval between WLF file updates. The WLF file 1390 | ; will be flushed (updated) after (at least) the interval has elapsed, ensuring 1391 | ; that the data is correct when viewed from a separate viewer. 1392 | ; A value of 0 means that no updating will occur. 1393 | ; The default value is 10 seconds. 1394 | ; WLFUpdateInterval = 10 1395 | 1396 | ; Specify the WLF cache size limit for WLF files. 1397 | ; The value is given in megabytes. A value of 0 turns off the cache. 1398 | ; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). 1399 | ; On Windows, the default value is 1000 (megabytes) to help to avoid filling 1400 | ; process memory. 1401 | ; WLFSimCacheSize allows a different cache size to be set for a live simulation 1402 | ; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize 1403 | ; is not set, it defaults to the WLFCacheSize value. 1404 | ; WLFCacheSize = 2000 1405 | ; WLFSimCacheSize = 500 1406 | 1407 | ; Specify the WLF file event collapse mode. 1408 | ; 0 = Preserve all events and event order. (same as -wlfnocollapse) 1409 | ; 1 = Only record values of logged objects at the end of a simulator iteration. 1410 | ; (same as -wlfcollapsedelta) 1411 | ; 2 = Only record values of logged objects at the end of a simulator time step. 1412 | ; (same as -wlfcollapsetime) 1413 | ; The default is 1. 1414 | ; WLFCollapseMode = 0 1415 | 1416 | ; Specify whether WLF file logging can use threads on multi-processor machines. 1417 | ; If 0, no threads will be used; if 1, threads will be used if the system has 1418 | ; more than one processor. 1419 | ; WLFUseThreads = 1 1420 | 1421 | ; Specify the size of objects that will trigger "large object" messages 1422 | ; at log/wave/list time. The size calculation of the object is the same as that 1423 | ; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. 1424 | ; Setting LargeObjectSize to 0 will disable these messages. 1425 | ; LargeObjectSize = 500000 1426 | 1427 | ; Specify the depth of stack frames returned by $stacktrace([level]). 1428 | ; This depth will be picked up when the optional 'level' argument 1429 | ; is not specified or its value is not a positive integer. 1430 | ; StackTraceDepth = 100 1431 | 1432 | ; Turn on/off undebuggable SystemC type warnings. Default is on. 1433 | ; ShowUndebuggableScTypeWarning = 0 1434 | 1435 | ; Turn on/off unassociated SystemC name warnings. Default is off. 1436 | ; ShowUnassociatedScNameWarning = 1 1437 | 1438 | ; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. 1439 | ; ScShowIeeeDeprecationWarnings = 1 1440 | 1441 | ; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. 1442 | ; For SystemC-2.3.2 the valid values are 0,1 and 2 1443 | ; 0 = SC_SIGNAL_WRITE_CHECK_DISABLE_ 1444 | ; 1 = SC_SIGNAL_WRITE_CHECK_DEFAULT_ 1445 | ; 2 = SC_SIGNAL_WRITE_CHECK_CONFLICT_ 1446 | ; For SystemC-2.2 the valid values are 0 and 1 1447 | ; 0 = DISABLE 1448 | ; 1 = ENABLE 1449 | ; ScEnableScSignalWriteCheck = 1 1450 | 1451 | ; Set SystemC default time unit. 1452 | ; Set to fs, ps, ns, us, ms, or sec with optional 1453 | ; prefix of 1, 10, or 100. The default is 1 ns. 1454 | ; The ScTimeUnit value is honored if it is coarser than Resolution. 1455 | ; If ScTimeUnit is finer than Resolution, it is set to the value 1456 | ; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, 1457 | ; then the default time unit will be 1 ns. However if Resolution 1458 | ; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. 1459 | ScTimeUnit = ns 1460 | 1461 | ; Set SystemC sc_main stack size. The stack size is set as an integer 1462 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1463 | ; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends 1464 | ; on the amount of data on the sc_main() stack and the memory required 1465 | ; to succesfully execute the longest function call chain of sc_main(). 1466 | ScMainStackSize = 10 Mb 1467 | 1468 | ; Set SystemC thread stack size. The stack size is set as an integer 1469 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1470 | ; Gb(Giga-byte). The stack size for sc_thread depends 1471 | ; on the amount of data on the sc_thread stack and the memory required 1472 | ; to succesfully execute the thread. 1473 | ; ScStackSize = 1 Mb 1474 | 1475 | ; Turn on/off execution of remainder of sc_main upon quitting the current 1476 | ; simulation session. If the cumulative length of sc_main() in terms of 1477 | ; simulation time units is less than the length of the current simulation 1478 | ; run upon quit or restart, sc_main() will be in the middle of execution. 1479 | ; This switch gives the option to execute the remainder of sc_main upon 1480 | ; quitting simulation. The drawback of not running sc_main till the end 1481 | ; is memory leaks for objects created by sc_main. If on, the remainder of 1482 | ; sc_main will be executed ignoring all delays. This may cause the simulator 1483 | ; to crash if the code in sc_main is dependent on some simulation state. 1484 | ; Default is on. 1485 | ScMainFinishOnQuit = 1 1486 | 1487 | ; Enable calling of the DPI export taks/functions from the 1488 | ; SystemC start_of_simulation() callback. 1489 | ; The default is off. 1490 | ; EnableDpiSosCb = 1 1491 | 1492 | 1493 | ; Set the SCV relationship name that will be used to identify phase 1494 | ; relations. If the name given to a transactor relation matches this 1495 | ; name, the transactions involved will be treated as phase transactions 1496 | ScvPhaseRelationName = mti_phase 1497 | 1498 | ; Customize the vsim kernel shutdown behavior at the end of the simulation. 1499 | ; Some common causes of the end of simulation are $finish (implicit or explicit), 1500 | ; sc_stop(), tf_dofinish(), and assertion failures. 1501 | ; This should be set to "ask", "exit", or "stop". The default is "ask". 1502 | ; "ask" -- In batch mode, the vsim kernel will abruptly exit. 1503 | ; In GUI mode, a dialog box will pop up and ask for user confirmation 1504 | ; whether or not to quit the simulation. 1505 | ; "stop" -- Cause the simulation to stay loaded in memory. This can make some 1506 | ; post-simulation tasks easier. 1507 | ; "exit" -- The simulation will abruptly exit without asking for any confirmation. 1508 | ; "final" -- Run SystemVerilog final blocks then behave as "stop". 1509 | ; Note: This variable can be overridden with the vsim "-onfinish" command line switch. 1510 | OnFinish = ask 1511 | 1512 | ; Print pending deferred assertion messages. 1513 | ; Deferred assertion messages may be scheduled after the $finish in the same 1514 | ; time step. Deferred assertions scheduled to print after the $finish are 1515 | ; printed before exiting with severity level NOTE since it's not known whether 1516 | ; the assertion is still valid due to being printed in the active region 1517 | ; instead of the reactive region where they are normally printed. 1518 | ; OnFinishPendingAssert = 1; 1519 | 1520 | ; Print "simstats" result. Default is 0. 1521 | ; 0 == do not print simstats 1522 | ; 1 == print at end of simulation 1523 | ; 2 == print at end of each run command and end of simulation 1524 | ; PrintSimStats = 1 1525 | 1526 | ; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages 1527 | ; AssertFile = assert.log 1528 | 1529 | ; Enable assertion counts. Default is off. 1530 | ; AssertionCounts = 1 1531 | 1532 | ; Run simulator in assertion debug mode. Default is off. 1533 | ; AssertionDebug = 1 1534 | 1535 | ; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. 1536 | ; AssertionEnable = 0 1537 | 1538 | ; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. 1539 | ; Any positive integer, -1 for infinity. 1540 | ; AssertionLimit = 1 1541 | 1542 | ; Turn on/off concurrent assertion pass log. Default is off. 1543 | ; Assertion pass logging is only enabled when assertion is browseable 1544 | ; and assertion debug is enabled. 1545 | ; AssertionPassLog = 1 1546 | 1547 | ; Turn on/off PSL concurrent assertion fail log. Default is on. 1548 | ; The flag does not affect SVA 1549 | ; AssertionFailLog = 0 1550 | 1551 | ; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. 1552 | ; AssertionFailLocalVarLog = 0 1553 | 1554 | ; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. 1555 | ; 0 = Continue 1 = Break 2 = Exit 1556 | ; AssertionFailAction = 1 1557 | 1558 | ; Enable the active thread monitor in the waveform display when assertion debug is enabled. 1559 | ; AssertionActiveThreadMonitor = 1 1560 | 1561 | ; Control how many waveform rows will be used for displaying the active threads. Default is 5. 1562 | ; AssertionActiveThreadMonitorLimit = 5 1563 | 1564 | ; Assertion thread limit after which assertion would be killed/switched off. 1565 | ; The default is -1 (unlimited). If the number of threads for an assertion go 1566 | ; beyond this limit, the assertion would be either switched off or killed. This 1567 | ; limit applies to only assert directives. 1568 | ;AssertionThreadLimit = -1 1569 | 1570 | ; Action to be taken once the assertion thread limit is reached. Default 1571 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1572 | ; threads are terminated and no new attempts are started. In case of off, the 1573 | ; existing attempts keep on evaluating but no new attempts are started. This 1574 | ; variable applies to only assert directives. 1575 | ;AssertionThreadLimitAction = kill 1576 | 1577 | ; Cover thread limit after which cover would be killed/switched off. 1578 | ; The default is -1 (unlimited). If the number of threads for a cover go 1579 | ; beyond this limit, the cover would be either switched off or killed. This 1580 | ; limit applies to only cover directives. 1581 | ;CoverThreadLimit = -1 1582 | 1583 | ; Action to be taken once the cover thread limit is reached. Default 1584 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1585 | ; threads are terminated and no new attempts are started. In case of off, the 1586 | ; existing attempts keep on evaluating but no new attempts are started. This 1587 | ; variable applies to only cover directives. 1588 | ;CoverThreadLimitAction = kill 1589 | 1590 | 1591 | ; By default immediate assertions do not participate in Assertion Coverage calculations 1592 | ; unless they are executed. This switch causes all immediate assertions in the design 1593 | ; to participate in Assertion Coverage calculations, whether attempted or not. 1594 | ; UnattemptedImmediateAssertions = 0 1595 | 1596 | ; By default immediate covers participate in Coverage calculations 1597 | ; whether they are attempted or not. This switch causes all unattempted 1598 | ; immediate covers in the design to stop participating in Coverage 1599 | ; calculations. 1600 | ; UnattemptedImmediateCovers = 0 1601 | 1602 | ; By default pass action block is not executed for assertions on vacuous 1603 | ; success. The following variable is provided to enable execution of 1604 | ; pass action block on vacuous success. The following variable is only effective 1605 | ; if the user does not disable pass action block execution by using either 1606 | ; system tasks or CLI. Also there is a performance penalty for enabling 1607 | ; the following variable. 1608 | ;AssertionEnableVacuousPassActionBlock = 1 1609 | 1610 | ; As per strict 1850-2005 PSL LRM, an always property can either pass 1611 | ; or fail. However, by default, Questa reports multiple passes and 1612 | ; multiple fails on top always/never property (always/never operator 1613 | ; is the top operator under Verification Directive). The reason 1614 | ; being that Questa reports passes and fails on per attempt of the 1615 | ; top always/never property. Use the following flag to instruct 1616 | ; Questa to strictly follow LRM. With this flag, all assert/never 1617 | ; directives will start an attempt once at start of simulation. 1618 | ; The attempt can either fail, match or match vacuously. 1619 | ; For e.g. if always is the top operator under assert, the always will 1620 | ; keep on checking the property at every clock. If the property under 1621 | ; always fails, the directive will be considered failed and no more 1622 | ; checking will be done for that directive. A top always property, 1623 | ; if it does not fail, will show a pass at end of simulation. 1624 | ; The default value is '0' (i.e. zero is off). For example: 1625 | ; PslOneAttempt = 1 1626 | 1627 | ; Specify the number of clock ticks to represent infinite clock ticks. 1628 | ; This affects eventually!, until! and until_!. If at End of Simulation 1629 | ; (EOS) an active strong-property has not clocked this number of 1630 | ; clock ticks then neither pass or fail (vacuous match) is returned 1631 | ; else respective fail/pass is returned. The default value is '0' (zero) 1632 | ; which effectively does not check for clock tick condition. For example: 1633 | ; PslInfinityThreshold = 5000 1634 | 1635 | ; Control how many thread start times will be preserved for ATV viewing for a given assertion 1636 | ; instance. Default is -1 (ALL). 1637 | ; ATVStartTimeKeepCount = -1 1638 | 1639 | ; Turn on/off code coverage 1640 | ; CodeCoverage = 0 1641 | 1642 | ; This option applies to condition and expression coverage UDP tables. It 1643 | ; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. 1644 | ; If this option is used and a match occurs in more than one row in the UDP table, 1645 | ; none of the counts for all matching rows is incremented. By default, counts are 1646 | ; incremented for all matching rows. 1647 | ; CoverCountAll = 1 1648 | 1649 | ; Turn off automatic inclusion of VHDL integers in toggle coverage. Default 1650 | ; is to include them. 1651 | ; ToggleNoIntegers = 1 1652 | 1653 | ; Set the maximum number of values that are collected for toggle coverage of 1654 | ; VHDL integers. Default is 100; 1655 | ; ToggleMaxIntValues = 100 1656 | 1657 | ; Set the maximum number of values that are collected for toggle coverage of 1658 | ; Verilog real. Default is 100; 1659 | ; ToggleMaxRealValues = 100 1660 | 1661 | ; Turn on automatic inclusion of Verilog integers in toggle coverage, except 1662 | ; for enumeration types. Default is to include them. 1663 | ; ToggleVlogIntegers = 0 1664 | 1665 | ; Turn on automatic inclusion of Verilog real type in toggle coverage, except 1666 | ; for shortreal types. Default is to not include them. 1667 | ; ToggleVlogReal = 1 1668 | 1669 | ; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays 1670 | ; and VHDL arrays-of-arrays in toggle coverage. 1671 | ; Default is to not include them. 1672 | ; ToggleFixedSizeArray = 1 1673 | 1674 | ; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, 1675 | ; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. 1676 | ; This leads to a longer simulation time with bigger arrays covered with toggle coverage. 1677 | ; Default is 1024. 1678 | ; ToggleMaxFixedSizeArray = 1024 1679 | 1680 | ; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized 1681 | ; one-dimensional packed vectors for toggle coverage. Default is 0. 1682 | ; TogglePackedAsVec = 0 1683 | 1684 | ; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for 1685 | ; toggle coverage. Default is 0. 1686 | ; ToggleVlogEnumBits = 0 1687 | 1688 | ; Turn off automatic inclusion of VHDL records in toggle coverage. 1689 | ; Default is to include them. 1690 | ; ToggleVHDLRecords = 0 1691 | 1692 | ; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. 1693 | ; For unlimited width, set to 0. 1694 | ; ToggleWidthLimit = 128 1695 | 1696 | ; Limit the counts that are tracked for toggle coverage. When all edges for a bit have 1697 | ; reached this count, further activity on the bit is ignored. Default is 1. 1698 | ; For unlimited counts, set to 0. 1699 | ; ToggleCountLimit = 1 1700 | 1701 | ; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. 1702 | ; Following is the toggle coverage calculation criteria based on extended toggle mode: 1703 | ; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). 1704 | ; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. 1705 | ; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. 1706 | ; ExtendedToggleMode = 3 1707 | 1708 | ; Enable toggle statistics collection only for ports. Default is 0. 1709 | ; TogglePortsOnly = 1 1710 | 1711 | ; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has 1712 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1713 | ; Default is 1. For unlimited counts, set to 0. 1714 | ; NOTE: Changing this value from its default value may affect simulation performance. 1715 | ; FecCountLimit = 1 1716 | 1717 | ; Limit the counts that are tracked for UDP Coverage. When a bin has 1718 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1719 | ; Default is 1. For unlimited counts, set to 0. 1720 | ; NOTE: Changing this value from its default value may affect simulation performance. 1721 | ; UdpCountLimit = 1 1722 | 1723 | ; Control toggle coverage deglitching period. A period of 0, eliminates delta 1724 | ; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either 1725 | ; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 1726 | ; ToggleDeglitchPeriod = 10.0ps 1727 | 1728 | ; Turn on/off all PSL/SVA cover directive enables. Default is on. 1729 | ; CoverEnable = 0 1730 | 1731 | ; Turn on/off PSL/SVA cover log. Default is off "0". 1732 | ; CoverLog = 1 1733 | 1734 | ; Set "at_least" value for all PSL/SVA cover directives. Default is 1. 1735 | ; CoverAtLeast = 2 1736 | 1737 | ; Set "limit" value for all PSL/SVA cover directives. Default is -1. 1738 | ; Any positive integer, -1 for infinity. 1739 | ; CoverLimit = 1 1740 | 1741 | ; Specify the coverage database filename. 1742 | ; Default is "" (i.e. database is NOT automatically saved on close). 1743 | ; UCDBFilename = vsim.ucdb 1744 | 1745 | ; Specify the maximum limit for the number of Cross (bin) products reported 1746 | ; in XML and UCDB report against a Cross. A warning is issued if the limit 1747 | ; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this 1748 | ; setting. 1749 | ; MaxReportRhsSVCrossProducts = 1000 1750 | 1751 | ; Specify the override for the "auto_bin_max" option for the Covergroups. 1752 | ; If not specified then value from Covergroup "option" is used. 1753 | ; SVCoverpointAutoBinMax = 64 1754 | 1755 | ; Specify the override for the value of "cross_num_print_missing" 1756 | ; option for the Cross in Covergroups. If not specified then value 1757 | ; specified in the "option.cross_num_print_missing" is used. This 1758 | ; is a runtime option. NOTE: This overrides any "cross_num_print_missing" 1759 | ; value specified by user in source file and any SVCrossNumPrintMissingDefault 1760 | ; specified in modelsim.ini. 1761 | ; SVCrossNumPrintMissing = 0 1762 | 1763 | ; Specify whether to use the value of "cross_num_print_missing" 1764 | ; option in report and GUI for the Cross in Covergroups. If not specified then 1765 | ; cross_num_print_missing is ignored for creating reports and displaying 1766 | ; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". 1767 | ; UseSVCrossNumPrintMissing = 0 1768 | 1769 | ; Specify the threshold of Coverpoint wildcard bin value range size, above which 1770 | ; a warning will be triggered. The default is 4K -- 12 wildcard bits. 1771 | ; SVCoverpointWildCardBinValueSizeWarn = 4096 1772 | 1773 | ; Specify the override for the value of "strobe" option for the 1774 | ; Covergroup Type. If not specified then value in "type_option.strobe" 1775 | ; will be used. This is runtime option which forces "strobe" to 1776 | ; user specified value and supersedes user specified values in the 1777 | ; SystemVerilog Code. NOTE: This also overrides the compile time 1778 | ; default value override specified using "SVCovergroupStrobeDefault" 1779 | ; SVCovergroupStrobe = 0 1780 | 1781 | ; Override for explicit assignments in source code to "option.goal" of 1782 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1783 | ; default value of "option.goal" (defined to be 100 in the SystemVerilog 1784 | ; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". 1785 | ; SVCovergroupGoal = 100 1786 | 1787 | ; Override for explicit assignments in source code to "type_option.goal" of 1788 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1789 | ; default value of "type_option.goal" (defined to be 100 in the SystemVerilog 1790 | ; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". 1791 | ; SVCovergroupTypeGoal = 100 1792 | 1793 | ; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() 1794 | ; builtin functions, and report. This setting changes the default values of 1795 | ; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 1796 | ; behavior if explicit assignments are not made on option.get_inst_coverage and 1797 | ; type_option.merge_instances by the user. There are two vsim command line 1798 | ; options, -cvg63 and -nocvg63 to override this setting from vsim command line. 1799 | ; The default value of this variable from release 6.6 onwards is 0. This default 1800 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1801 | ; SVCovergroup63Compatibility = 0 1802 | 1803 | ; Enforce the default behavior of covergroup get_coverage() builtin function, GUI 1804 | ; and report. This variable sets the default value of type_option.merge_instances. 1805 | ; There are two vsim command line options, -cvgmergeinstances and 1806 | ; -nocvgmergeinstances to override this setting from vsim command line. 1807 | ; The default value of this variable, -1 (don't care), allows the tool to determine 1808 | ; the effective value, based on factors related to capacity and optimization. 1809 | ; The type_option.merge_instances appears in the GUI and coverage reports as either 1810 | ; auto(1) or auto(0), depending on whether the effective value was determined to 1811 | ; be a 1 or a 0. 1812 | ; SVCovergroupMergeInstancesDefault = -1 1813 | 1814 | ; Enable or disable generation of more detailed information about the sampling 1815 | ; of covergroup, cross, and coverpoints. It provides the details of the number 1816 | ; of times the covergroup instance and type were sampled, as well as details 1817 | ; about why covergroup, cross and coverpoint were not covered. A non-zero value 1818 | ; is to enable this feature. 0 is to disable this feature. Default is 0 1819 | ; SVCovergroupSampleInfo = 0 1820 | 1821 | ; Specify the maximum number of Coverpoint bins in whole design for 1822 | ; all Covergroups. 1823 | ; MaxSVCoverpointBinsDesign = 2147483648 1824 | 1825 | ; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins 1826 | ; MaxSVCoverpointBinsInst = 1048576 1827 | 1828 | ; Specify the maximum number of Cross bins in whole design for 1829 | ; all Covergroups. 1830 | ; MaxSVCrossBinsDesign = 2147483648 1831 | 1832 | ; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins 1833 | ; MaxSVCrossBinsInst = 67108864 1834 | 1835 | ; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. 1836 | ; By default, this variable is set 0, in which case option.no_collect setting will take effect. 1837 | ; If this variable is set to 1, all zero-weight coverage items will not be saved. 1838 | ; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting 1839 | ; of this variable. 1840 | ; CvgZWNoCollect = 1 1841 | 1842 | ; Specify a space delimited list of double quoted TCL style 1843 | ; regular expressions which will be matched against the text of all messages. 1844 | ; If any regular expression is found to be contained within any message, the 1845 | ; status for that message will not be propagated to the UCDB TESTSTATUS. 1846 | ; If no match is detected, then the status will be propagated to the 1847 | ; UCDB TESTSTATUS. More than one such regular expression text is allowed, 1848 | ; and each message text is compared for each regular expression in the list. 1849 | ; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" 1850 | 1851 | ; Set weight for all PSL/SVA cover directives. Default is 1. 1852 | ; CoverWeight = 2 1853 | 1854 | ; Check vsim plusargs. Default is 0 (off). 1855 | ; 0 = Don't check plusargs 1856 | ; 1 = Warning on unrecognized plusarg 1857 | ; 2 = Error and exit on unrecognized plusarg 1858 | ; CheckPlusargs = 1 1859 | 1860 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 1861 | ; This gives global visibility to all symbols in the shared objects, 1862 | ; meaning that subsequently loaded shared objects can bind to symbols 1863 | ; in the global shared objects. The list of shared objects should 1864 | ; be whitespace delimited. This option is not supported on the 1865 | ; Windows or AIX platforms. 1866 | ; GlobalSharedObjectList = example1.so example2.so example3.so 1867 | 1868 | ; Generate the stub definitions for the undefined symbols in the shared libraries being 1869 | ; loaded in the simulation. When this flow is turned on, the undefined symbols will not 1870 | ; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. 1871 | ; The valid arguments are: on, off, verbose. 1872 | ; on : turn on the automatic generation of stub definitions. 1873 | ; off: turn off the flow. The undefined symbols will trigger an immediate load failure. 1874 | ; verbose: Turn on the flow and report the undefined symbols for each shared library. 1875 | ; NOTE: This variable can be overriden with vsim switch "-undefsyms". 1876 | ; The default is on. 1877 | ; 1878 | ; UndefSyms = off 1879 | 1880 | ; Enable the support for checkpointing foreign C++ libraries. 1881 | ; The valid arguments are: 1 and 0. 1882 | ; 1 : turn on the support 1883 | ; 0 : turn off the support (default) 1884 | ; This option is not supported on the Windows platforms. 1885 | ; 1886 | ; AllowCheckpointCpp = 1 1887 | 1888 | ; Initial seed for the random number generator of the root thread (SystemVerilog). 1889 | ; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. 1890 | ; The default value is 0. 1891 | ; Sv_Seed = 0 1892 | 1893 | ; Specify the solver "engine" that vsim will select for constrained random 1894 | ; generation. 1895 | ; Valid values are: 1896 | ; "auto" - automatically select the best engine for the current 1897 | ; constraint scenario 1898 | ; "bdd" - evaluate all constraint scenarios using the BDD solver engine 1899 | ; "act" - evaluate all constraint scenarios using the ACT solver engine 1900 | ; While the BDD solver engine is generally efficient with constraint scenarios 1901 | ; involving bitwise logical relationships, the ACT solver engine can exhibit 1902 | ; superior performance with constraint scenarios involving large numbers of 1903 | ; random variables related via arithmetic operators (+, *, etc). 1904 | ; NOTE: This variable can be overridden with the vsim "-solveengine" command 1905 | ; line switch. 1906 | ; The default value is "auto". 1907 | ; SolveEngine = auto 1908 | 1909 | ; Specifies the maximum size that a dynamic array may be resized to by the 1910 | ; solver. If the solver attempts to resize a dynamic array to a size greater 1911 | ; than the specified limit, the solver will abort with an error. 1912 | ; The default value is 10000. A value of 0 indicates no limit. 1913 | ; SolveArrayResizeMax = 10000 1914 | 1915 | ; Specify error message severity when randomize() and randomize(null) failures 1916 | ; are detected. 1917 | ; 1918 | ; Integer value up to two digits are allowed with each digit having the following legal values: 1919 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1920 | ; 1921 | ; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents 1922 | ; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit) 1923 | ; represents the setting for randomize(null) calls. 1924 | ; 1925 | ; 2) When a single digit value is used, the setting is applied to both normal randomize() call 1926 | ; and randomize(null) call. 1927 | ; 1928 | ; Example: Fatal error for randomize() failures and NO error for randomize(null) failures 1929 | ; -solvefailseverity=40 1930 | ; 1931 | ; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is 1932 | ; enabled, a constraint contradiction report will be displayed for randomize() calls that 1933 | ; have a message severity >= warning (i.e. constraint contradiction reports will not be 1934 | ; generated for randomize() calls having a "no error" severity level) 1935 | ; 1936 | ; NOTE: This variable can be overridden with the vsim "-solvefailseverity" command 1937 | ; line switch. 1938 | ; 1939 | ; The default is 1 (warning). 1940 | ; SolveFailSeverity = 1 1941 | 1942 | ; Error message severity for suppressible errors that are detected in a 1943 | ; solve/before constraint. 1944 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1945 | ; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" 1946 | ; command line switch. 1947 | ; The default is 3 (failure). 1948 | ; SolveBeforeErrorSeverity = 3 1949 | 1950 | ; Error message severity for suppressible errors that are related to 1951 | ; solve engine capacity limits 1952 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1953 | ; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity" 1954 | ; command line switch. 1955 | ; The default is 3 (failure). 1956 | ; SolveEngineErrorSeverity = 3 1957 | 1958 | ; Enable/disable constraint conflicts on randomize() failure 1959 | ; Valid values: 1960 | ; 0 - disable solvefaildebug 1961 | ; 1 - basic debug (no performance penalty) 1962 | ; 2 - enhanced debug (runtime performance penalty) 1963 | ; 1964 | ; NOTE: SolveFailSeverity can affect the behavior of SolveFailDebug. When SolveFailDebug is 1965 | ; enabled, a constraint contradiction report will be displayed for randomize() calls that 1966 | ; have a message severity >= warning (i.e. constraint contradiction reports will not be 1967 | ; generated for randomize() calls having a "no error" severity level) 1968 | ; 1969 | ; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command 1970 | ; line switch. 1971 | ; 1972 | ; The default is 1 (basic debug). 1973 | ; SolveFailDebug = 1 1974 | 1975 | ; Upon encountering a randomize() failure, generate a simplified testcase that 1976 | ; will reproduce the failure. Optionally output the testcase to a file. 1977 | ; Testcases for 'no-solution' failures will only be produced if SolveFailDebug 1978 | ; is enabled (see above). 1979 | ; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" 1980 | ; command line switch. 1981 | ; The default is OFF (do not generate a testcase). To enable testcase 1982 | ; generation, uncomment this variable. To redirect testcase generation to a 1983 | ; file, specify the name of the output file. 1984 | ; SolveFailTestcase = 1985 | 1986 | ; Specify solver timeout threshold (in seconds). randomize() will fail if the 1987 | ; CPU time required to evaluate any randset exceeds the specified timeout. 1988 | ; The default value is 500. A value of 0 will disable timeout failures. 1989 | ; SolveTimeout = 500 1990 | 1991 | ; Specify the maximum size of the solution graph generated by the BDD solver. 1992 | ; This value can be used to force the BDD solver to abort the evaluation of a 1993 | ; complex constraint scenario that cannot be evaluated with finite memory. 1994 | ; This value is specified in 1000s of nodes. 1995 | ; The default value is 10000. A value of 0 indicates no limit. 1996 | ; SolveGraphMaxSize = 10000 1997 | 1998 | ; Specify the maximum number of evaluations that may be performed on the 1999 | ; solution graph by the BDD solver. This value can be used to force the BDD 2000 | ; solver to abort the evaluation of a complex constraint scenario that cannot 2001 | ; be evaluated in finite time. This value is specified in 10000s of evaluations. 2002 | ; The default value is 10000. A value of 0 indicates no limit. 2003 | ; SolveGraphMaxEval = 10000 2004 | 2005 | ; Specify random sequence compatiblity with a prior release. This 2006 | ; option is used to get the same random sequences during simulation as 2007 | ; as a prior release. Only prior releases with the same major version 2008 | ; as the current release are allowed. 2009 | ; NOTE: Only those random sequence changes due to solver optimizations are 2010 | ; reverted by this variable. Random sequence changes due to solver bugfixes 2011 | ; cannot be un-done. 2012 | ; NOTE: This variable can be overridden with the vsim "-solverev" command 2013 | ; line switch. 2014 | ; Default value set to "" (no compatibility). 2015 | ; SolveRev = 2016 | 2017 | ; Environment variable expansion of command line arguments has been depricated 2018 | ; in favor shell level expansion. Universal environment variable expansion 2019 | ; inside -f files is support and continued support for MGC Location Maps provide 2020 | ; alternative methods for handling flexible pathnames. 2021 | ; The following line may be uncommented and the value set to 1 to re-enable this 2022 | ; deprecated behavior. The default value is 0. 2023 | ; DeprecatedEnvironmentVariableExpansion = 0 2024 | 2025 | ; Specify the memory threshold for the System Verilog garbage collector. 2026 | ; The value is the number of megabytes of class objects that must accumulate 2027 | ; before the garbage collector is run. 2028 | ; The GCThreshold setting is used when class debug mode is disabled to allow 2029 | ; less frequent garbage collection and better simulation performance. 2030 | ; The GCThresholdClassDebug setting is used when class debug mode is enabled 2031 | ; to allow for more frequent garbage collection. 2032 | ; GCThreshold = 100 2033 | ; GCThresholdClassDebug = 5 2034 | 2035 | ; Turn on/off collapsing of bus ports in VCD dumpports output 2036 | DumpportsCollapse = 1 2037 | 2038 | ; Location of Multi-Level Verification Component (MVC) installation. 2039 | ; The default location is the product installation directory. 2040 | MvcHome = $MODEL_TECH/.. 2041 | 2042 | ; Location of InFact installation. The default is $MODEL_TECH/../../infact 2043 | ; 2044 | ; InFactHome = $MODEL_TECH/../../infact 2045 | 2046 | ; Initialize SystemVerilog enums using the base type's default value 2047 | ; instead of the leftmost value. 2048 | ; EnumBaseInit = 1 2049 | 2050 | ; Suppress file type registration. 2051 | ; SuppressFileTypeReg = 1 2052 | 2053 | ; Enable/disable non-LRM compliant SystemVerilog language extensions. 2054 | ; Valid extensions are: 2055 | ; altdpiheader - Alternative style function signature generated in DPI header", 2056 | ; cfce - generate an error if $cast fails as a function 2057 | ; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h') 2058 | ; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks 2059 | ; expdfmt - enable format string extensions for $display/$sformatf 2060 | ; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi) 2061 | ; fmtcap - prints capital hex digits with %X/%H in display calls 2062 | ; iddp - ignore DPI disable protocol check 2063 | ; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h") 2064 | ; noexptc - ignore DPI export type name overloading check 2065 | ; realrand - support randomize() with real variables and constraints (Default) 2066 | ; SvExtensions = [+|-][,[+|-]*] 2067 | 2068 | ; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions. 2069 | ; Valid extensions are: 2070 | ; arraymode - consider rand_mode of unpacked array field independently from its elements 2071 | ; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles (Default) 2072 | ; funcback - enable function backtracking (ACT only) 2073 | ; genmodseedfix - enable LRM-compliant seeding of module/interface instances under for-generate blocks (Default) 2074 | ; nodist - interpret 'dist' constraint as 'inside' (ACT only) 2075 | ; noorder - ignore solve/before ordering constraints (ACT only) 2076 | ; pathseed - enable unique seeding of module instances based on hierarchical path name 2077 | ; promotedist - promote priority of 'dist' constraint if LHS has no solve/before 2078 | ; randindex - allow random index in constraint (Default) 2079 | ; randstruct - consider all fields of unpacked structs as 'rand' 2080 | ; skew - skew randomize results (ACT only) 2081 | ; strictstab - strict random stability 2082 | ; SvRandExtensions = [+|-][,[+|-]*] 2083 | 2084 | ; Controls the formatting of '%p' and '%P' conversion specification, used in $display 2085 | ; and similar system tasks. 2086 | ; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. 2087 | ; The 'I' flag when present causes relevant data types to be expanded and indented into 2088 | ; a more readable format. 2089 | ; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). 2090 | ; 2. SVPrettyPrintFlags=L limits the output to lines. 2091 | ; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). 2092 | ; 3. SVPrettyPrintFlags=C limits the output to characters. 2093 | ; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). 2094 | ; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes 2095 | ; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). 2096 | ; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes 2097 | ; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). 2098 | ; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . 2099 | ; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). 2100 | ; 7. SVPrettyPrintFlags=R shows the output of specifier %p as per the specifed radix. 2101 | ; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)). 2102 | ; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format. 2103 | ; 8. Items 1-7 above can be combined as a comma separated list. 2104 | ; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb) 2105 | ; SVPrettyPrintFlags=I4S 2106 | 2107 | [lmc] 2108 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software 2109 | libsm = $MODEL_TECH/libsm.sl 2110 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) 2111 | ; libsm = $MODEL_TECH/libsm.dll 2112 | ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) 2113 | ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl 2114 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 2115 | ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 2116 | ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) 2117 | ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so 2118 | ; Logic Modeling's SmartModel SWIFT software (Windows NT) 2119 | ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll 2120 | ; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) 2121 | ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so 2122 | ; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) 2123 | ; libswift = $LMC_HOME/lib/linux.lib/libswift.so 2124 | 2125 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software 2126 | libhm = $MODEL_TECH/libhm.sl 2127 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) 2128 | ; libhm = $MODEL_TECH/libhm.dll 2129 | ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) 2130 | ; libsfi = /lib/hp700/libsfi.sl 2131 | ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) 2132 | ; libsfi = /lib/rs6000/libsfi.a 2133 | ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) 2134 | ; libsfi = /lib/sun4.solaris/libsfi.so 2135 | ; Logic Modeling's hardware modeler SFI software (Windows NT) 2136 | ; libsfi = /lib/pcnt/lm_sfi.dll 2137 | ; Logic Modeling's hardware modeler SFI software (Linux) 2138 | ; libsfi = /lib/linux/libsfi.so 2139 | 2140 | [msg_system] 2141 | ; Change a message severity or suppress a message. 2142 | ; The format is: = [,...] 2143 | ; suppress can be used to achieve +nowarn functionality 2144 | ; The format is: suppress = ,,[,,...] 2145 | ; Examples: 2146 | suppress = 8780 ;an explanation can be had by running: verror 8780 2147 | ; note = 3009 2148 | ; warning = 3033 2149 | ; error = 3010,3016 2150 | ; fatal = 3016,3033 2151 | ; suppress = 3009,3016,3601 2152 | ; suppress = 3009,CNNODP,3601,TFMPC 2153 | ; suppress = 8683,8684 2154 | ; The command verror can be used to get the complete 2155 | ; description of a message. 2156 | 2157 | ; Control transcripting of Verilog display system task messages and 2158 | ; PLI/FLI print function call messages. The system tasks include 2159 | ; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They 2160 | ; also include the analogous file I/O tasks that write to STDOUT 2161 | ; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, 2162 | ; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default 2163 | ; is to have messages appear only in the transcript. The other 2164 | ; settings are to send messages to the wlf file only (messages that 2165 | ; are recorded in the wlf file can be viewed in the MsgViewer) or 2166 | ; to both the transcript and the wlf file. The valid values are 2167 | ; tran {transcript only (default)} 2168 | ; wlf {wlf file only} 2169 | ; both {transcript and wlf file} 2170 | ; displaymsgmode = tran 2171 | 2172 | ; Control transcripting of elaboration/runtime messages not 2173 | ; addressed by the displaymsgmode setting. The default is to 2174 | ; have messages appear only in the transcript. The other settings 2175 | ; are to send messages to the wlf file only (messages that are 2176 | ; recorded in the wlf file can be viewed in the MsgViewer) or to both 2177 | ; the transcript and the wlf file. The valid values are 2178 | ; tran {transcript only (default)} 2179 | ; wlf {wlf file only} 2180 | ; both {transcript and wlf file} 2181 | ; msgmode = tran 2182 | 2183 | ; Controls number of displays of a particluar message 2184 | ; default value is 5 2185 | ; MsgLimitCount = 5 2186 | 2187 | [utils] 2188 | ; Default Library Type (while creating a library with "vlib") 2189 | ; 0 - legacy library using subdirectories for design units 2190 | ; 2 - flat library 2191 | ; DefaultLibType = 2 2192 | 2193 | ; Flat Library Page Size (while creating a library with "vlib") 2194 | ; Set the size in bytes for flat library file pages. Libraries containing 2195 | ; very large files may benefit from a larger value. 2196 | ; FlatLibPageSize = 8192 2197 | 2198 | ; Flat Library Page Cleanup Percentage (while creating a library with "vlib") 2199 | ; Set the percentage of total pages deleted before library cleanup can occur. 2200 | ; This setting is applied together with FlatLibPageDeleteThreshold. 2201 | ; FlatLibPageDeletePercentage = 50 2202 | 2203 | ; Flat Library Page Cleanup Threshold (while creating a library with "vlib") 2204 | ; Set the number of pages deleted before library cleanup can occur. 2205 | ; This setting is applied together with FlatLibPageDeletePercentage. 2206 | ; FlatLibPageDeleteThreshold = 1000 2207 | 2208 | -------------------------------------------------------------------------------- /clock_div/sim.do: -------------------------------------------------------------------------------- 1 | onbreak resume 2 | onerror resume 3 | vsim -voptargs=+acc work.DUT 4 | #vsim 5 | add wave * 6 | add wave -position insertpoint \ 7 | sim:/DUT/div1/clk_n \ 8 | sim:/DUT/div1/clk_p \ 9 | sim:/DUT/div1/cnt1 \ 10 | sim:/DUT/div1/cnt2 11 | run -all -------------------------------------------------------------------------------- /clock_div/transcript: -------------------------------------------------------------------------------- 1 | # Reading pref.tcl 2 | # // Questa Sim-64 3 | # // Version 2020.1 win64 Jan 28 2020 4 | # // 5 | # // Copyright 1991-2020 Mentor Graphics Corporation 6 | # // All Rights Reserved. 7 | # // 8 | # // QuestaSim and its associated documentation contain trade 9 | # // secrets and commercial or financial information that are the property of 10 | # // Mentor Graphics Corporation and are privileged, confidential, 11 | # // and exempt from disclosure under the Freedom of Information Act, 12 | # // 5 U.S.C. Section 552. Furthermore, this information 13 | # // is prohibited from disclosure under the Trade Secrets Act, 14 | # // 18 U.S.C. Section 1905. 15 | # // 16 | do complie.do 17 | # ** Warning: (vlib-34) Library already exists at "work". 18 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 19 | # Start time: 16:36:16 on Mar 26,2021 20 | # vlog -reportprogress 300 clock_div.v 21 | # -- Compiling module clock_div1 22 | # -- Compiling module Odd_Divider 23 | # -- Compiling module clock_div2 24 | # 25 | # Top level modules: 26 | # clock_div1 27 | # Odd_Divider 28 | # clock_div2 29 | # End time: 16:36:16 on Mar 26,2021, Elapsed time: 0:00:00 30 | # Errors: 0, Warnings: 0 31 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 32 | # Start time: 16:36:16 on Mar 26,2021 33 | # vlog -reportprogress 300 clock_div_tb.v 34 | # -- Compiling module DUT 35 | # 36 | # Top level modules: 37 | # DUT 38 | # End time: 16:36:16 on Mar 26,2021, Elapsed time: 0:00:00 39 | # Errors: 0, Warnings: 0 40 | do sim.do 41 | # vsim -voptargs="+acc" work.DUT 42 | # Start time: 16:36:22 on Mar 26,2021 43 | # ** Note: (vsim-8009) Loading existing optimized design _opt2 44 | # Loading work.DUT(fast) 45 | # Loading work.Odd_Divider(fast) 46 | # Loading work.clock_div1(fast) 47 | # Loading work.clock_div2(fast) 48 | # ** Note: $stop : clock_div_tb.v(14) 49 | # Time: 1015 ns Iteration: 0 Instance: /DUT 50 | # Break in Module DUT at clock_div_tb.v line 14 51 | do sim.do 52 | # End time: 16:39:42 on Mar 26,2021, Elapsed time: 0:03:20 53 | # Errors: 0, Warnings: 0 54 | # vsim -voptargs="+acc" work.DUT 55 | # Start time: 16:39:42 on Mar 26,2021 56 | # ** Note: (vsim-8009) Loading existing optimized design _opt2 57 | # Loading work.DUT(fast) 58 | # Loading work.Odd_Divider(fast) 59 | # Loading work.clock_div1(fast) 60 | # Loading work.clock_div2(fast) 61 | # ** Note: $stop : clock_div_tb.v(14) 62 | # Time: 1015 ns Iteration: 0 Instance: /DUT 63 | # Break in Module DUT at clock_div_tb.v line 14 64 | add wave -position insertpoint \ 65 | sim:/DUT/div1/cnt1 \ 66 | sim:/DUT/div1/cnt2 67 | # End time: 16:53:03 on Mar 26,2021, Elapsed time: 0:13:21 68 | # Errors: 0, Warnings: 0 69 | -------------------------------------------------------------------------------- /clock_div/vlog.opt: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /clock_gating/clock_gating.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:29:10 03/02/2021 7 | // Design Name: 8 | // Module Name: clock_delay 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 上电后，延迟1S再允许时钟，保证芯片上电时序正常。 13 | //Clock_EN 只在时钟低电平时才切换，确保不出现毛刺 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module clock_delay( 22 | input rst, 23 | input clk_in, 24 | output clk_out 25 | ); 26 | 27 | reg carry; 28 | reg [12:0] cnt1; 29 | reg [13:0] cnt2; 30 | reg clk_EN; 31 | reg cnt_EN; 32 | 33 | 34 | always@(posedge clk_in) begin 35 | if(rst) begin 36 | cnt1<=0; 37 | carry<=0; 38 | end 39 | else if(cnt1==13'd50) begin 40 | cnt1<=0; 41 | carry<=1; 42 | end 43 | else begin 44 | cnt1<=cnt1+1; 45 | carry<=0; 46 | end 47 | end 48 | 49 | always@(posedge clk_in) begin 50 | if(rst) begin 51 | cnt2<=0; 52 | cnt_EN<=0; 53 | end 54 | else if(cnt2==14'd10) begin 55 | cnt2<=0; 56 | cnt_EN<=1; 57 | end 58 | else if(carry) begin 59 | cnt2<=cnt2+1; 60 | end 61 | else cnt_EN<=cnt_EN; 62 | end 63 | 64 | always@(cnt_EN or clk_in) 65 | if(!clk_in) clk_EN=cnt_EN; 66 | 67 | assign clk_out=clk_in&clk_EN; 68 | endmodule 69 | -------------------------------------------------------------------------------- /clock_gating/clock_gating_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 14:29:10 03/02/2021 7 | // Design Name: 8 | // Module Name: clock_delay 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 上电后，延迟1S再允许时钟，保证芯片上电时序正常。 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module clock_delay_tb(); 22 | reg clk_in; 23 | reg rst; 24 | wire clk_out; 25 | 26 | 27 | initial begin 28 | clk_in=0; 29 | rst=1; 30 | #40 31 | rst=0; 32 | #100000 33 | $finish; 34 | end 35 | 36 | 37 | always #10 clk_in<=~clk_in; 38 | clock_delay u1(.clk_in(clk_in),.clk_out(clk_out),.rst(rst)); 39 | endmodule 40 | -------------------------------------------------------------------------------- /clock_gating/complie.do: -------------------------------------------------------------------------------- 1 | vlib work 2 | vlog clock_gating.v 3 | vlog clock_gating_tb.v 4 | -------------------------------------------------------------------------------- /clock_gating/sim.do: -------------------------------------------------------------------------------- 1 | onbreak resume 2 | onerror resume 3 | vsim -voptargs=+acc work.clock_delay_tb 4 | add wave -position insertpoint \ 5 | sim:/clock_delay_tb/u1/rst \ 6 | sim:/clock_delay_tb/u1/clk_in \ 7 | sim:/clock_delay_tb/u1/clk_out \ 8 | sim:/clock_delay_tb/u1/carry \ 9 | sim:/clock_delay_tb/u1/cnt1 \ 10 | sim:/clock_delay_tb/u1/cnt2 \ 11 | sim:/clock_delay_tb/u1/clk_EN 12 | run -all -------------------------------------------------------------------------------- /parallel_serial_switch/complie1.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dumpo/my_verilog_projects/c2db9636a569f1683e6c537c8d5a010fc58e35ad/parallel_serial_switch/complie1.do -------------------------------------------------------------------------------- /parallel_serial_switch/parallel_to_serial.v: -------------------------------------------------------------------------------- 1 | module parallel_to_serial 2 | ( 3 | rst_n,load,clk,in,out 4 | ); 5 | 6 | 7 | parameter WEIDTH=8; 8 | input [WEIDTH-1:0] in; 9 | input rst_n; 10 | input load; 11 | input clk; 12 | output reg out; 13 | reg [2:0] cnt; 14 | reg [WEIDTH-1:0] in_reg; 15 | 16 | always@(posedge clk or negedge rst_n) begin 17 | if(!rst_n) begin 18 | in_reg<=8'b0; 19 | out<=0; 20 | end 21 | else if(load) in_reg<=in; 22 | else begin 23 | case(cnt) 24 | 0:out<=in_reg[0]; 25 | 1:out<=in_reg[1]; 26 | 2:out<=in_reg[2]; 27 | 3:out<=in_reg[3]; 28 | 4:out<=in_reg[4]; 29 | 5:out<=in_reg[5]; 30 | 6:out<=in_reg[6]; 31 | 7:out<=in_reg[7]; 32 | default:out<=out; 33 | endcase 34 | end 35 | end 36 | 37 | always@(posedge clk or negedge rst_n) begin 38 | if(!rst_n) 39 | cnt<=0; 40 | else if(cnt==WEIDTH-1) 41 | cnt<=0; 42 | else 43 | cnt<=cnt+1; 44 | 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /parallel_serial_switch/parallel_to_serial_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module DUT1(output out ); 3 | reg clk; 4 | reg rst_n; 5 | reg [7:0] in; 6 | reg load; 7 | initial begin 8 | rst_n=0; 9 | clk=0; 10 | load=0; 11 | #50 12 | rst_n=1; 13 | in=8'd4; 14 | load=1; 15 | #30 16 | load=0; 17 | 18 | #200 19 | load=1; 20 | in=8'd127; 21 | #30 22 | load=0; 23 | 24 | #200 25 | load=1; 26 | in=8'd255; 27 | #30 28 | load=0; 29 | #200 30 | $stop; 31 | 32 | end 33 | 34 | always#10 35 | clk<=~clk; 36 | parallel_to_serial u1(rst_n,load,clk,in,out); 37 | endmodule -------------------------------------------------------------------------------- /parallel_serial_switch/serial_to_parallel _tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | module DUT2(output [7:0] out ); 3 | reg clk; 4 | reg rst_n; 5 | reg in; 6 | initial begin 7 | rst_n=0; 8 | clk=0; 9 | 10 | #50 11 | rst_n=1; 12 | in=0; 13 | 14 | #20 15 | in=1; 16 | 17 | #20 18 | 19 | in=1; 20 | #20 21 | in=0; 22 | 23 | #20 24 | in=1; 25 | 26 | #20 27 | in=0; 28 | #20 29 | in=1; 30 | #20 31 | in=1; 32 | #200 33 | $stop; 34 | 35 | end 36 | 37 | always#10 38 | clk<=~clk; 39 | serial_to_parallel u2(rst_n,clk,in,out); 40 | endmodule -------------------------------------------------------------------------------- /parallel_serial_switch/serial_to_parallel.v: -------------------------------------------------------------------------------- 1 | module serial_to_parallel #(parameter WEIDTH=8) 2 | ( 3 | input rst_n, 4 | input clk, 5 | input data_in, 6 | output reg [WEIDTH-1:0] data_out, 7 | output done 8 | ); 9 | 10 | 11 | reg [2:0] cnt; 12 | 13 | always@(posedge clk or negedge rst_n) begin 14 | if(!rst_n) begin 15 | data_out<=8'b0; 16 | end 17 | else begin 18 | data_out<={data_out[WEIDTH-2:0],data_in}; 19 | end 20 | end 21 | 22 | 23 | endmodule -------------------------------------------------------------------------------- /parallel_serial_switch/sim2.do: -------------------------------------------------------------------------------- 1 | onbreak resume 2 | onerror resume 3 | vsim -voptargs=+acc work.DUT1 4 | #vsim 5 | add wave * 6 | run -all -------------------------------------------------------------------------------- /parallel_serial_switch/transcript: -------------------------------------------------------------------------------- 1 | # Reading pref.tcl 2 | # // Questa Sim-64 3 | # // Version 2020.1 win64 Jan 28 2020 4 | # // 5 | # // Copyright 1991-2020 Mentor Graphics Corporation 6 | # // All Rights Reserved. 7 | # // 8 | # // QuestaSim and its associated documentation contain trade 9 | # // secrets and commercial or financial information that are the property of 10 | # // Mentor Graphics Corporation and are privileged, confidential, 11 | # // and exempt from disclosure under the Freedom of Information Act, 12 | # // 5 U.S.C. Section 552. Furthermore, this information 13 | # // is prohibited from disclosure under the Trade Secrets Act, 14 | # // 18 U.S.C. Section 1905. 15 | # // 16 | do complie1.do 17 | # ** Warning: (vlib-34) Library already exists at "work". 18 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 19 | # Start time: 19:50:15 on Mar 26,2021 20 | # vlog -reportprogress 300 parallel_to_serial.v parallel_to_serial_tb.v serial_to_parallel _tb.v serial_to_parallel.v 21 | # -- Compiling module parallel_to_serial 22 | # -- Compiling module DUT1 23 | # -- Compiling module serial_to_parallel 24 | # ** Error (suppressible): serial_to_parallel.v(12): (vlog-2388) 'data_in' already declared in this scope (serial_to_parallel) at serial_to_parallel.v(5). 25 | # ** Error: serial_to_parallel.v(18): (vlog-2730) Undefined variable: 'in_reg'. 26 | # ** Error: serial_to_parallel.v(19): (vlog-2730) Undefined variable: 'out'. 27 | # ** Error: (vlog-13069) serial_to_parallel.v(23): near "default": syntax error, unexpected default. 28 | # End time: 19:50:15 on Mar 26,2021, Elapsed time: 0:00:00 29 | # Errors: 4, Warnings: 0 30 | # ** Error: D:/questasim64_2020.1/win64/vlog failed. 31 | # Error in macro ./complie1.do line 3 32 | # D:/questasim64_2020.1/win64/vlog failed. 33 | # while executing 34 | # "vlog *.v" 35 | do complie1.do 36 | # ** Warning: (vlib-34) Library already exists at "work". 37 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 38 | # Start time: 20:16:15 on Mar 26,2021 39 | # vlog -reportprogress 300 parallel_to_serial.v parallel_to_serial_tb.v serial_to_parallel _tb.v serial_to_parallel.v 40 | # -- Compiling module parallel_to_serial 41 | # -- Compiling module DUT1 42 | # ** Warning: serial_to_parallel _tb.v(2): (vlog-2275) Existing module 'DUT1' will be overwritten. 43 | # -- Compiling module DUT1 44 | # -- Compiling module serial_to_parallel 45 | # ** Error: (vlog-13069) serial_to_parallel.v(19): near "end": syntax error, unexpected end, expecting ';'. 46 | # End time: 20:16:15 on Mar 26,2021, Elapsed time: 0:00:00 47 | # Errors: 1, Warnings: 1 48 | # ** Error: D:/questasim64_2020.1/win64/vlog failed. 49 | # Error in macro ./complie1.do line 3 50 | # D:/questasim64_2020.1/win64/vlog failed. 51 | # while executing 52 | # "vlog *.v" 53 | do complie1.do 54 | # ** Warning: (vlib-34) Library already exists at "work". 55 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 56 | # Start time: 20:16:32 on Mar 26,2021 57 | # vlog -reportprogress 300 parallel_to_serial.v parallel_to_serial_tb.v serial_to_parallel _tb.v serial_to_parallel.v 58 | # -- Compiling module parallel_to_serial 59 | # -- Compiling module DUT1 60 | # ** Warning: serial_to_parallel _tb.v(2): (vlog-2275) Existing module 'DUT1' will be overwritten. 61 | # -- Compiling module DUT1 62 | # -- Compiling module serial_to_parallel 63 | # 64 | # Top level modules: 65 | # DUT1 66 | # End time: 20:16:33 on Mar 26,2021, Elapsed time: 0:00:01 67 | # Errors: 0, Warnings: 1 68 | # vsim -voptargs="+acc" work.DUT1 69 | # Start time: 20:16:33 on Mar 26,2021 70 | # ** Note: (vsim-3813) Design is being optimized due to module recompilation... 71 | # Loading work.DUT1(fast) 72 | # Loading work.serial_to_parallel(fast) 73 | # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u1'. Expected 5, found 4. 74 | # Time: 0 ps Iteration: 0 Instance: /DUT1/u1 File: serial_to_parallel _tb.v Line: 40 75 | # ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (8) for port 'data_in'. The port definition is at: serial_to_parallel.v(5). 76 | # Time: 0 ps Iteration: 0 Instance: /DUT1/u1 File: serial_to_parallel _tb.v Line: 40 77 | # ** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (1) for port 'data_out'. The port definition is at: serial_to_parallel.v(6). 78 | # Time: 0 ps Iteration: 0 Instance: /DUT1/u1 File: serial_to_parallel _tb.v Line: 40 79 | # ** Warning: (vsim-3722) serial_to_parallel _tb.v(40): [TFMPC] - Missing connection for port 'done'. 80 | # ** Note: $stop : serial_to_parallel _tb.v(34) 81 | # Time: 390 ns Iteration: 0 Instance: /DUT1 82 | # Break in Module DUT1 at serial_to_parallel _tb.v line 34 83 | do complie1.do 84 | # ** Warning: (vlib-34) Library already exists at "work". 85 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 86 | # Start time: 20:17:49 on Mar 26,2021 87 | # vlog -reportprogress 300 serial_to_parallel _tb.v serial_to_parallel.v 88 | # -- Compiling module DUT2 89 | # -- Compiling module serial_to_parallel 90 | # 91 | # Top level modules: 92 | # DUT2 93 | # End time: 20:17:49 on Mar 26,2021, Elapsed time: 0:00:00 94 | # Errors: 0, Warnings: 0 95 | # End time: 20:17:54 on Mar 26,2021, Elapsed time: 0:01:21 96 | # Errors: 0, Warnings: 4 97 | # vsim -voptargs="+acc" work.DUT2 98 | # Start time: 20:17:54 on Mar 26,2021 99 | # ** Note: (vsim-3812) Design is being optimized... 100 | # Loading work.DUT2(fast) 101 | # Loading work.serial_to_parallel(fast) 102 | # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u2'. Expected 5, found 4. 103 | # Time: 0 ps Iteration: 0 Instance: /DUT2/u2 File: serial_to_parallel _tb.v Line: 40 104 | # ** Warning: (vsim-3015) [PCDPC] - Port size (1) does not match connection size (8) for port 'data_in'. The port definition is at: serial_to_parallel.v(5). 105 | # Time: 0 ps Iteration: 0 Instance: /DUT2/u2 File: serial_to_parallel _tb.v Line: 40 106 | # ** Warning: (vsim-3015) [PCDPC] - Port size (8) does not match connection size (1) for port 'data_out'. The port definition is at: serial_to_parallel.v(6). 107 | # Time: 0 ps Iteration: 0 Instance: /DUT2/u2 File: serial_to_parallel _tb.v Line: 40 108 | # ** Warning: (vsim-3722) serial_to_parallel _tb.v(40): [TFMPC] - Missing connection for port 'done'. 109 | # ** Note: $stop : serial_to_parallel _tb.v(34) 110 | # Time: 390 ns Iteration: 0 Instance: /DUT2 111 | # Break in Module DUT2 at serial_to_parallel _tb.v line 34 112 | do complie1.do 113 | # ** Warning: (vlib-34) Library already exists at "work". 114 | # QuestaSim-64 vlog 2020.1 Compiler 2020.01 Jan 28 2020 115 | # Start time: 20:18:37 on Mar 26,2021 116 | # vlog -reportprogress 300 serial_to_parallel _tb.v serial_to_parallel.v 117 | # -- Compiling module DUT2 118 | # -- Compiling module serial_to_parallel 119 | # 120 | # Top level modules: 121 | # DUT2 122 | # End time: 20:18:37 on Mar 26,2021, Elapsed time: 0:00:00 123 | # Errors: 0, Warnings: 0 124 | # End time: 20:18:40 on Mar 26,2021, Elapsed time: 0:00:46 125 | # Errors: 0, Warnings: 4 126 | # vsim -voptargs="+acc" work.DUT2 127 | # Start time: 20:18:40 on Mar 26,2021 128 | # ** Note: (vsim-3813) Design is being optimized due to module recompilation... 129 | # Loading work.DUT2(fast) 130 | # Loading work.serial_to_parallel(fast) 131 | # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'u2'. Expected 5, found 4. 132 | # Time: 0 ps Iteration: 0 Instance: /DUT2/u2 File: serial_to_parallel _tb.v Line: 39 133 | # ** Warning: (vsim-3722) serial_to_parallel _tb.v(39): [TFMPC] - Missing connection for port 'done'. 134 | # ** UI-Msg: (vish-4014) No objects found matching '/DUT2/load'. 135 | # Executing ONERROR command at macro ./complie1.do line 12 136 | # ** Note: $stop : serial_to_parallel _tb.v(33) 137 | # Time: 390 ns Iteration: 0 Instance: /DUT2 138 | # Break in Module DUT2 at serial_to_parallel _tb.v line 33 139 | # Causality operation skipped due to absence of debug database file 140 | # End time: 20:41:02 on Mar 26,2021, Elapsed time: 0:22:22 141 | # Errors: 0, Warnings: 2 142 | -------------------------------------------------------------------------------- /uvm_template/RTL/dut.sv: -------------------------------------------------------------------------------- 1 | module dut(clk, 2 | rst_n, 3 | rxd, 4 | rx_dv, 5 | txd, 6 | tx_en); 7 | input clk; 8 | input rst_n; 9 | input[7:0] rxd; 10 | input rx_dv; 11 | output [7:0] txd; 12 | output tx_en; 13 | 14 | reg[7:0] txd; 15 | reg tx_en; 16 | 17 | always @(posedge clk) begin 18 | if(!rst_n) begin 19 | txd <= 8'b0; 20 | tx_en <= 1'b0; 21 | end 22 | else begin 23 | txd <= rxd; 24 | tx_en <= rx_dv; 25 | end 26 | end 27 | endmodule 28 | 29 | -------------------------------------------------------------------------------- /uvm_template/Verification/sim/clean.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | echo 开始清理...... 3 | del transcript 4 | del *.log 5 | del *.wlf 6 | del *.xml 7 | rd /s /Q work 8 | echo 清理完成...... 9 | @echo on 10 | pause -------------------------------------------------------------------------------- /uvm_template/Verification/sim/dut.f: -------------------------------------------------------------------------------- 1 | $WORK_AERA/RTL/dut.sv -------------------------------------------------------------------------------- /uvm_template/Verification/sim/filelist.f: -------------------------------------------------------------------------------- 1 | +incdir+$UVM_HOME/src 2 | $UVM_HOME/src/uvm_pkg.sv 3 | $WORK_AERA/Verification/tb/top_tb.sv 4 | 5 | -------------------------------------------------------------------------------- /uvm_template/Verification/sim/run.bat: -------------------------------------------------------------------------------- 1 | vsim -do sim.do -------------------------------------------------------------------------------- /uvm_template/Verification/sim/sim.do: -------------------------------------------------------------------------------- 1 | setenv WORK_AERA "D:/software/uvm_template" 2 | 3 | #testcase name 4 | set TEST "my_case0" 5 | 6 | #name related to the the dut 7 | set TOP "top_tb" 8 | set DUT_LIST "dut.f" 9 | set FILE_LIST "filelist.f" 10 | 11 | 12 | set WAVE_TOP "sim:/top_tb/*" 13 | 14 | 15 | #PLI for dump fsdb 16 | set PLI "" 17 | 18 | #the uvm 19 | set UVM_DPI_HOME D:/software/questasim64_2020.1/uvm-1.1d/win64 20 | set UVM_HOME D:/software/questasim64_2020.1/verilog_src/uvm-1.1d 21 | set WORK_HOME "D:/software/uvm_template/Verification/sim" 22 | 23 | quit -sim 24 | cd ${WORK_HOME} 25 | 26 | if [file exists work] { 27 | vdel -all 28 | } 29 | vlib work 30 | vlog -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF -f ${DUT_LIST} -f ${FILE_LIST} 31 | vsim -c +notimingchecks -t 1ps ${TOP} +UVM_TESTNAME=${TEST} +UVM_VERBOSITY=UVM_FULL -voptargs=+acc \ 32 | -solvefaildebug -uvmcontrol=all -classdebug -l sim.log -pli ${PLI} \ 33 | -sv_lib ${UVM_DPI_HOME}/uvm_dpi 34 | add log -r /* 35 | add wave ${WAVE_TOP} 36 | run -all -------------------------------------------------------------------------------- /uvm_template/Verification/sim/wave_open.bat: -------------------------------------------------------------------------------- 1 | vsim -view vsim.wlf -------------------------------------------------------------------------------- /uvm_template/Verification/tb/base_test.sv: -------------------------------------------------------------------------------- 1 | `ifndef BASE_TEST__SV 2 | `define BASE_TEST__SV 3 | 4 | class base_test extends uvm_test; 5 | 6 | my_env env; 7 | 8 | function new(string name = "base_test", uvm_component parent = null); 9 | super.new(name,parent); 10 | endfunction 11 | 12 | extern virtual function void build_phase(uvm_phase phase); 13 | extern virtual function void report_phase(uvm_phase phase); 14 | `uvm_component_utils(base_test) 15 | endclass 16 | 17 | 18 | function void base_test::build_phase(uvm_phase phase); 19 | super.build_phase(phase); 20 | env = my_env::type_id::create("env", this); 21 | endfunction 22 | 23 | function void base_test::report_phase(uvm_phase phase); 24 | uvm_report_server server; 25 | int err_num; 26 | super.report_phase(phase); 27 | 28 | server = get_report_server(); 29 | err_num = server.get_severity_count(UVM_ERROR); 30 | 31 | if (err_num != 0) begin 32 | $display("TEST CASE FAILED"); 33 | end 34 | else begin 35 | $display("TEST CASE PASSED"); 36 | end 37 | endfunction 38 | 39 | `endif 40 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_agent.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_AGENT__SV 2 | `define MY_AGENT__SV 3 | 4 | class my_agent extends uvm_agent ; 5 | my_sequencer sqr; 6 | my_driver drv; 7 | my_monitor mon; 8 | 9 | uvm_analysis_port #(my_transaction) ap; 10 | 11 | function new(string name, uvm_component parent); 12 | super.new(name, parent); 13 | endfunction 14 | 15 | extern virtual function void build_phase(uvm_phase phase); 16 | extern virtual function void connect_phase(uvm_phase phase); 17 | 18 | `uvm_component_utils(my_agent) 19 | endclass 20 | 21 | 22 | function void my_agent::build_phase(uvm_phase phase); 23 | super.build_phase(phase); 24 | if (is_active == UVM_ACTIVE) begin 25 | sqr = my_sequencer::type_id::create("sqr", this); 26 | drv = my_driver::type_id::create("drv", this); 27 | end 28 | mon = my_monitor::type_id::create("mon", this); 29 | endfunction 30 | 31 | function void my_agent::connect_phase(uvm_phase phase); 32 | super.connect_phase(phase); 33 | if (is_active == UVM_ACTIVE) begin 34 | drv.seq_item_port.connect(sqr.seq_item_export); 35 | end 36 | ap = mon.ap; 37 | endfunction 38 | 39 | `endif 40 | 41 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_case0.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_CASE0__SV 2 | `define MY_CASE0__SV 3 | class case0_sequence extends uvm_sequence #(my_transaction); 4 | my_transaction m_trans; 5 | 6 | function new(string name= "case0_sequence"); 7 | super.new(name); 8 | endfunction 9 | 10 | virtual task body(); 11 | if(starting_phase != null) 12 | starting_phase.raise_objection(this); 13 | repeat (10) begin 14 | `uvm_do(m_trans) 15 | end 16 | #100; 17 | if(starting_phase != null) 18 | starting_phase.drop_objection(this); 19 | endtask 20 | 21 | `uvm_object_utils(case0_sequence) 22 | endclass 23 | 24 | 25 | class my_case0 extends base_test; 26 | 27 | function new(string name = "my_case0", uvm_component parent = null); 28 | super.new(name,parent); 29 | endfunction 30 | extern virtual function void build_phase(uvm_phase phase); 31 | `uvm_component_utils(my_case0) 32 | endclass 33 | 34 | 35 | function void my_case0::build_phase(uvm_phase phase); 36 | super.build_phase(phase); 37 | 38 | uvm_config_db#(uvm_object_wrapper)::set(this, 39 | "env.i_agt.sqr.main_phase", 40 | "default_sequence", 41 | case0_sequence::type_id::get()); 42 | endfunction 43 | 44 | `endif 45 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_case1.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_CASE1__SV 2 | `define MY_CASE1__SV 3 | class case1_sequence extends uvm_sequence #(my_transaction); 4 | my_transaction m_trans; 5 | 6 | function new(string name= "case1_sequence"); 7 | super.new(name); 8 | endfunction 9 | 10 | virtual task body(); 11 | if(starting_phase != null) 12 | starting_phase.raise_objection(this); 13 | repeat (10) begin 14 | `uvm_do_with(m_trans, { m_trans.pload.size() == 60;}) 15 | end 16 | #100; 17 | if(starting_phase != null) 18 | starting_phase.drop_objection(this); 19 | endtask 20 | 21 | `uvm_object_utils(case1_sequence) 22 | endclass 23 | 24 | class my_case1 extends base_test; 25 | 26 | function new(string name = "my_case1", uvm_component parent = null); 27 | super.new(name,parent); 28 | endfunction 29 | 30 | extern virtual function void build_phase(uvm_phase phase); 31 | `uvm_component_utils(my_case1) 32 | endclass 33 | 34 | 35 | function void my_case1::build_phase(uvm_phase phase); 36 | super.build_phase(phase); 37 | 38 | uvm_config_db#(uvm_object_wrapper)::set(this, 39 | "env.i_agt.sqr.main_phase", 40 | "default_sequence", 41 | case1_sequence::type_id::get()); 42 | endfunction 43 | 44 | `endif 45 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_driver.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_DRIVER__SV 2 | `define MY_DRIVER__SV 3 | class my_driver extends uvm_driver#(my_transaction); 4 | 5 | virtual my_if vif; 6 | 7 | `uvm_component_utils(my_driver) 8 | function new(string name = "my_driver", uvm_component parent = null); 9 | super.new(name, parent); 10 | endfunction 11 | 12 | virtual function void build_phase(uvm_phase phase); 13 | super.build_phase(phase); 14 | if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif)) 15 | `uvm_fatal("my_driver", "virtual interface must be set for vif!!!") 16 | endfunction 17 | 18 | extern task main_phase(uvm_phase phase); 19 | extern task drive_one_pkt(my_transaction tr); 20 | endclass 21 | 22 | task my_driver::main_phase(uvm_phase phase); 23 | vif.data <= 8'b0; 24 | vif.valid <= 1'b0; 25 | while(!vif.rst_n) 26 | @(posedge vif.clk); 27 | while(1) begin 28 | seq_item_port.get_next_item(req); 29 | drive_one_pkt(req); 30 | seq_item_port.item_done(); 31 | end 32 | endtask 33 | 34 | task my_driver::drive_one_pkt(my_transaction tr); 35 | byte unsigned data_q[]; 36 | int data_size; 37 | 38 | data_size = tr.pack_bytes(data_q) / 8; 39 | `uvm_info("my_driver", "begin to drive one pkt", UVM_LOW); 40 | repeat(3) @(posedge vif.clk); 41 | for ( int i = 0; i < data_size; i++ ) begin 42 | @(posedge vif.clk); 43 | vif.valid <= 1'b1; 44 | vif.data <= data_q[i]; 45 | end 46 | 47 | @(posedge vif.clk); 48 | vif.valid <= 1'b0; 49 | `uvm_info("my_driver", "end drive one pkt", UVM_LOW); 50 | endtask 51 | 52 | 53 | `endif 54 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_env.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_ENV__SV 2 | `define MY_ENV__SV 3 | 4 | class my_env extends uvm_env; 5 | 6 | my_agent i_agt; 7 | my_agent o_agt; 8 | my_model mdl; 9 | my_scoreboard scb; 10 | 11 | uvm_tlm_analysis_fifo #(my_transaction) agt_scb_fifo; 12 | uvm_tlm_analysis_fifo #(my_transaction) agt_mdl_fifo; 13 | uvm_tlm_analysis_fifo #(my_transaction) mdl_scb_fifo; 14 | 15 | function new(string name = "my_env", uvm_component parent); 16 | super.new(name, parent); 17 | endfunction 18 | 19 | virtual function void build_phase(uvm_phase phase); 20 | super.build_phase(phase); 21 | i_agt = my_agent::type_id::create("i_agt", this); 22 | o_agt = my_agent::type_id::create("o_agt", this); 23 | i_agt.is_active = UVM_ACTIVE; 24 | o_agt.is_active = UVM_PASSIVE; 25 | mdl = my_model::type_id::create("mdl", this); 26 | scb = my_scoreboard::type_id::create("scb", this); 27 | agt_scb_fifo = new("agt_scb_fifo", this); 28 | agt_mdl_fifo = new("agt_mdl_fifo", this); 29 | mdl_scb_fifo = new("mdl_scb_fifo", this); 30 | 31 | endfunction 32 | 33 | extern virtual function void connect_phase(uvm_phase phase); 34 | 35 | `uvm_component_utils(my_env) 36 | endclass 37 | 38 | function void my_env::connect_phase(uvm_phase phase); 39 | super.connect_phase(phase); 40 | i_agt.ap.connect(agt_mdl_fifo.analysis_export); 41 | mdl.port.connect(agt_mdl_fifo.blocking_get_export); 42 | mdl.ap.connect(mdl_scb_fifo.analysis_export); 43 | scb.exp_port.connect(mdl_scb_fifo.blocking_get_export); 44 | o_agt.ap.connect(agt_scb_fifo.analysis_export); 45 | scb.act_port.connect(agt_scb_fifo.blocking_get_export); 46 | endfunction 47 | 48 | `endif 49 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_if.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_IF__SV 2 | `define MY_IF__SV 3 | 4 | interface jammer_conv_if( 5 | input logic clk, // 时钟信号 6 | input logic rst_n // 异步复位信号，低电平有效 7 | ); 8 | 9 | parameter WIDTH = 16; // 数据宽度 10 | parameter NUM = 8; // 寄存器数量 11 | 12 | logic [WIDTH-1:0] coe; // 系数输入 13 | logic coes_vld; // 系数有效信号 14 | logic sig_vld; // 信号有效信号 15 | logic last_sig; // 最后一个信号标志 16 | logic [WIDTH-1:0] sig_in; // 信号输入 17 | logic [2*WIDTH-1:0] sig_out; // 信号输出 18 | 19 | // Modport定义 20 | modport DUT ( 21 | input clk, rst_n, coe, coes_vld, sig_vld, last_sig, sig_in, 22 | output sig_out 23 | ); 24 | 25 | modport TB ( 26 | output clk, rst_n, coe, coes_vld, sig_vld, last_sig, sig_in, 27 | input sig_out 28 | ); 29 | 30 | endinterface 31 | 32 | 33 | `endif 34 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_model.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_MODEL__SV 2 | `define MY_MODEL__SV 3 | 4 | class my_model extends uvm_component; 5 | 6 | uvm_blocking_get_port #(my_transaction) port; 7 | uvm_analysis_port #(my_transaction) ap; 8 | 9 | extern function new(string name, uvm_component parent); 10 | extern function void build_phase(uvm_phase phase); 11 | extern virtual task main_phase(uvm_phase phase); 12 | 13 | `uvm_component_utils(my_model) 14 | endclass 15 | 16 | function my_model::new(string name, uvm_component parent); 17 | super.new(name, parent); 18 | endfunction 19 | 20 | function void my_model::build_phase(uvm_phase phase); 21 | super.build_phase(phase); 22 | port = new("port", this); 23 | ap = new("ap", this); 24 | endfunction 25 | 26 | task my_model::main_phase(uvm_phase phase); 27 | my_transaction tr; 28 | my_transaction new_tr; 29 | super.main_phase(phase); 30 | while(1) begin 31 | port.get(tr); 32 | new_tr = new("new_tr"); 33 | new_tr.copy(tr); 34 | `uvm_info("my_model", "get one transaction, copy and print it:", UVM_LOW) 35 | new_tr.print(); 36 | ap.write(new_tr); 37 | end 38 | endtask 39 | `endif 40 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_monitor.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_MONITOR__SV 2 | `define MY_MONITOR__SV 3 | class my_monitor extends uvm_monitor; 4 | 5 | virtual my_if vif; 6 | 7 | uvm_analysis_port #(my_transaction) ap; 8 | 9 | `uvm_component_utils(my_monitor) 10 | function new(string name = "my_monitor", uvm_component parent = null); 11 | super.new(name, parent); 12 | endfunction 13 | 14 | virtual function void build_phase(uvm_phase phase); 15 | super.build_phase(phase); 16 | if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif)) 17 | `uvm_fatal("my_monitor", "virtual interface must be set for vif!!!") 18 | ap = new("ap", this); 19 | endfunction 20 | 21 | extern task main_phase(uvm_phase phase); 22 | extern task collect_one_pkt(my_transaction tr); 23 | endclass 24 | 25 | task my_monitor::main_phase(uvm_phase phase); 26 | my_transaction tr; 27 | while(1) begin 28 | tr = new("tr"); 29 | collect_one_pkt(tr); 30 | ap.write(tr); 31 | end 32 | endtask 33 | 34 | task my_monitor::collect_one_pkt(my_transaction tr); 35 | byte unsigned data_q[$]; 36 | byte unsigned data_array[]; 37 | logic [7:0] data; 38 | logic valid = 0; 39 | int data_size; 40 | 41 | while(1) begin 42 | @(posedge vif.clk); 43 | if(vif.valid) break; 44 | end 45 | 46 | `uvm_info("my_monitor", "begin to collect one pkt", UVM_LOW); 47 | while(vif.valid) begin 48 | data_q.push_back(vif.data); 49 | @(posedge vif.clk); 50 | end 51 | data_size = data_q.size(); 52 | data_array = new[data_size]; 53 | for ( int i = 0; i < data_size; i++ ) begin 54 | data_array[i] = data_q[i]; 55 | end 56 | tr.pload = new[data_size - 18]; //da sa, e_type, crc 57 | data_size = tr.unpack_bytes(data_array) / 8; 58 | `uvm_info("my_monitor", "end collect one pkt", UVM_LOW); 59 | endtask 60 | 61 | 62 | `endif 63 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_scoreboard.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_SCOREBOARD__SV 2 | `define MY_SCOREBOARD__SV 3 | class my_scoreboard extends uvm_scoreboard; 4 | my_transaction expect_queue[$]; 5 | uvm_blocking_get_port #(my_transaction) exp_port; 6 | uvm_blocking_get_port #(my_transaction) act_port; 7 | `uvm_component_utils(my_scoreboard) 8 | 9 | extern function new(string name, uvm_component parent = null); 10 | extern virtual function void build_phase(uvm_phase phase); 11 | extern virtual task main_phase(uvm_phase phase); 12 | endclass 13 | 14 | function my_scoreboard::new(string name, uvm_component parent = null); 15 | super.new(name, parent); 16 | endfunction 17 | 18 | function void my_scoreboard::build_phase(uvm_phase phase); 19 | super.build_phase(phase); 20 | exp_port = new("exp_port", this); 21 | act_port = new("act_port", this); 22 | endfunction 23 | 24 | task my_scoreboard::main_phase(uvm_phase phase); 25 | my_transaction get_expect, get_actual, tmp_tran; 26 | bit result; 27 | 28 | super.main_phase(phase); 29 | fork 30 | while (1) begin 31 | exp_port.get(get_expect); 32 | expect_queue.push_back(get_expect); 33 | end 34 | while (1) begin 35 | act_port.get(get_actual); 36 | if(expect_queue.size() > 0) begin 37 | tmp_tran = expect_queue.pop_front(); 38 | result = get_actual.compare(tmp_tran); 39 | if(result) begin 40 | `uvm_info("my_scoreboard", "Compare SUCCESSFULLY", UVM_LOW); 41 | end 42 | else begin 43 | `uvm_error("my_scoreboard", "Compare FAILED"); 44 | $display("the expect pkt is"); 45 | tmp_tran.print(); 46 | $display("the actual pkt is"); 47 | get_actual.print(); 48 | end 49 | end 50 | else begin 51 | `uvm_error("my_scoreboard", "Received from DUT, while Expect Queue is empty"); 52 | $display("the unexpected pkt is"); 53 | get_actual.print(); 54 | end 55 | end 56 | join 57 | endtask 58 | `endif 59 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_sequencer.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_SEQUENCER__SV 2 | `define MY_SEQUENCER__SV 3 | 4 | class my_sequencer extends uvm_sequencer #(my_transaction); 5 | 6 | function new(string name, uvm_component parent); 7 | super.new(name, parent); 8 | endfunction 9 | 10 | `uvm_component_utils(my_sequencer) 11 | endclass 12 | 13 | `endif 14 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/my_transaction.sv: -------------------------------------------------------------------------------- 1 | `ifndef MY_TRANSACTION__SV 2 | `define MY_TRANSACTION__SV 3 | 4 | class my_transaction extends uvm_sequence_item; 5 | 6 | rand bit[47:0] dmac; 7 | rand bit[47:0] smac; 8 | rand bit[15:0] ether_type; 9 | rand byte pload[]; 10 | rand bit[31:0] crc; 11 | 12 | constraint pload_cons{ 13 | pload.size >= 46; 14 | pload.size <= 1500; 15 | } 16 | 17 | function bit[31:0] calc_crc(); 18 | return 32'h0; 19 | endfunction 20 | 21 | function void post_randomize(); 22 | crc = calc_crc; 23 | endfunction 24 | 25 | `uvm_object_utils_begin(my_transaction) 26 | `uvm_field_int(dmac, UVM_ALL_ON) 27 | `uvm_field_int(smac, UVM_ALL_ON) 28 | `uvm_field_int(ether_type, UVM_ALL_ON) 29 | `uvm_field_array_int(pload, UVM_ALL_ON) 30 | `uvm_field_int(crc, UVM_ALL_ON) 31 | `uvm_object_utils_end 32 | 33 | function new(string name = "my_transaction"); 34 | super.new(); 35 | endfunction 36 | 37 | endclass 38 | `endif 39 | -------------------------------------------------------------------------------- /uvm_template/Verification/tb/testbench.sv: -------------------------------------------------------------------------------- 1 | import uvm_pkg::*; 2 | `include "uvm_macros.svh" 3 | `include "interface.sv" ; 4 | `include "uvm_classes.sv" ; 5 | 6 | module testbench (); 7 | 8 | initial begin 9 | `uvm_info("testbench","hello uvm!",UVM_NONE) 10 | end 11 | 12 | endmodule -------------------------------------------------------------------------------- /uvm_template/Verification/tb/top_tb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | `include "uvm_macros.svh" 3 | 4 | import uvm_pkg::*; 5 | `include "my_if.sv" 6 | `include "my_transaction.sv" 7 | `include "my_sequencer.sv" 8 | `include "my_driver.sv" 9 | `include "my_monitor.sv" 10 | `include "my_agent.sv" 11 | `include "my_model.sv" 12 | `include "my_scoreboard.sv" 13 | `include "my_env.sv" 14 | `include "base_test.sv" 15 | `include "my_case0.sv" 16 | `include "my_case1.sv" 17 | 18 | module top_tb; 19 | 20 | reg clk; 21 | reg rst_n; 22 | reg[7:0] rxd; 23 | reg rx_dv; 24 | wire[7:0] txd; 25 | wire tx_en; 26 | 27 | my_if input_if(clk, rst_n); 28 | my_if output_if(clk, rst_n); 29 | 30 | dut my_dut(.clk(clk), 31 | .rst_n(rst_n), 32 | .rxd(input_if.data), 33 | .rx_dv(input_if.valid), 34 | .txd(output_if.data), 35 | .tx_en(output_if.valid)); 36 | 37 | initial begin 38 | clk = 0; 39 | forever begin 40 | #100 clk = ~clk; 41 | end 42 | end 43 | 44 | initial begin 45 | rst_n = 1'b0; 46 | #1000; 47 | rst_n = 1'b1; 48 | end 49 | 50 | initial begin 51 | run_test(); 52 | end 53 | 54 | initial begin 55 | uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if); 56 | uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if); 57 | uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if); 58 | end 59 | 60 | endmodule 61 | --------------------------------------------------------------------------------