├── .gitignore ├── doc_resources ├── i2s.png ├── lrck1.png └── lrck2.png ├── src ├── blockdesign │ ├── .gitignore │ ├── ip │ │ └── design_1_clk_wiz_0_1 │ │ │ ├── design_1_clk_wiz_0_1_board.xdc │ │ │ ├── design_1_clk_wiz_0_1.dcp │ │ │ ├── design_1_clk_wiz_0_1_stub.v │ │ │ ├── design_1_clk_wiz_0_1_stub.vhdl │ │ │ ├── design_1_clk_wiz_0_1_ooc.xdc │ │ │ ├── design_1_clk_wiz_0_1.xdc │ │ │ ├── design_1_clk_wiz_0_1.v │ │ │ ├── design_1_clk_wiz_0_1_clk_wiz.v │ │ │ ├── design_1_clk_wiz_0_1_sim_netlist.vhdl │ │ │ └── design_1_clk_wiz_0_1_sim_netlist.v │ ├── design_1_ooc.xdc │ ├── ui │ │ └── bd_1f5defd0.ui │ └── design_1.bd ├── design │ ├── types.vhd │ ├── square_wave.vhd │ ├── sine_wave.vhd │ ├── i2s_sender.vhd │ ├── segment_display.vhd │ ├── design_1_wrapper.vhd │ ├── sine_generator_types.vhd │ └── Nexys-4-DDR-Master.xdc └── testbench │ ├── i2s_testbench.vhd │ ├── wave │ ├── wave_testbench_behav.wcfg │ └── wave_testbench.vhd │ ├── i2s_sine │ ├── i2s_sine_testbench.vhd │ └── i2s_sine_testbench_behav.wcfg │ ├── i2s_testbench_behav.wcfg │ └── sine │ └── sine_testbench.vhd ├── .gitmodules ├── README.md └── vivado_project.tcl /.gitignore: -------------------------------------------------------------------------------- 1 | vivado_project/* 2 | -------------------------------------------------------------------------------- /doc_resources/i2s.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dwjbosman/I2S_sender/HEAD/doc_resources/i2s.png -------------------------------------------------------------------------------- /doc_resources/lrck1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dwjbosman/I2S_sender/HEAD/doc_resources/lrck1.png -------------------------------------------------------------------------------- /doc_resources/lrck2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dwjbosman/I2S_sender/HEAD/doc_resources/lrck2.png -------------------------------------------------------------------------------- /src/blockdesign/.gitignore: -------------------------------------------------------------------------------- 1 | design_1.bxml 2 | hdl 3 | ipshared 4 | design_* 5 | hw_handoff 6 | sim 7 | synth 8 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "src/design/sincos"] 2 | path = src/design/sincos 3 | url = https://github.com/jorisvr/vhdl_sincos_gen.git 4 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/dwjbosman/I2S_sender/HEAD/src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.dcp -------------------------------------------------------------------------------- /src/blockdesign/design_1_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | 3 | # This XDC is used only for OOC mode of synthesis, implementation 4 | # This constraints file contains default clock frequencies to be used during 5 | # out-of-context flows such as OOC Synthesis and Hierarchical Designs. 6 | # This constraints file is not used in normal top-down synthesis (default flow 7 | # of Vivado) 8 | ################################################################################ 9 | create_clock -name sys_clock -period 10 [get_ports sys_clock] 10 | 11 | ################################################################################ -------------------------------------------------------------------------------- /src/blockdesign/ui/bd_1f5defd0.ui: -------------------------------------------------------------------------------- 1 | { 2 | ExpandedHierarchyInLayout: "", 3 | guistr: "# # String gsaved with Nlview 6.8.5 2018-01-30 bk=1.4354 VDI=40 GEI=35 GUI=JA:1.6 TLS 4 | # -string -flagsOSRD 5 | preplace port locked_reset -pg 1 -y 40 -defaultsOSRD 6 | preplace port MCLK_gen_out -pg 1 -y 20 -defaultsOSRD 7 | preplace port clk_out -pg 1 -y -10 -defaultsOSRD 8 | preplace port sys_clock -pg 1 -y 40 -defaultsOSRD 9 | preplace port reset -pg 1 -y 20 -defaultsOSRD 10 | preplace inst clk_wiz_0 -pg 1 -lvl 1 -y 20 -defaultsOSRD 11 | preplace netloc clk_wiz_0_MCLK 1 1 2 N 20 N 12 | preplace netloc clk_wiz_0_locked 1 1 2 N 40 N 13 | preplace netloc sys_clock_1 1 0 1 -40 14 | preplace netloc clk_wiz_0_clk_out1 1 1 2 N 0 570 15 | preplace netloc reset_1 1 0 1 -40 16 | levelinfo -pg 1 -60 270 550 830 -top -410 -bot 600 17 | ", 18 | } 19 | { 20 | da_board_cnt: "3", 21 | da_clkrst_cnt: "1", 22 | } 23 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 4 | // Date : Sat Sep 15 23:16:43 2018 5 | // Host : dinne-Aspire-VN7-593G running 64-bit Ubuntu 16.04.4 LTS 6 | // Command : write_verilog -force -mode synth_stub 7 | // /home/dinne/Xilinx/projects/I2S_sender/vivado_project/vivado_project.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.v 8 | // Design : design_1_clk_wiz_0_1 9 | // Purpose : Stub declaration of top-level module interface 10 | // Device : xc7a100tcsg324-1 11 | // -------------------------------------------------------------------------------- 12 | 13 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 14 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 15 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 16 | module design_1_clk_wiz_0_1(clk_out1, clk_out2, reset, locked, clk_in1) 17 | /* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,reset,locked,clk_in1" */; 18 | output clk_out1; 19 | output clk_out2; 20 | input reset; 21 | output locked; 22 | input clk_in1; 23 | endmodule 24 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 4 | -- Date : Sat Sep 15 23:16:43 2018 5 | -- Host : dinne-Aspire-VN7-593G running 64-bit Ubuntu 16.04.4 LTS 6 | -- Command : write_vhdl -force -mode synth_stub 7 | -- /home/dinne/Xilinx/projects/I2S_sender/vivado_project/vivado_project.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_stub.vhdl 8 | -- Design : design_1_clk_wiz_0_1 9 | -- Purpose : Stub declaration of top-level module interface 10 | -- Device : xc7a100tcsg324-1 11 | -- -------------------------------------------------------------------------------- 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | entity design_1_clk_wiz_0_1 is 16 | Port ( 17 | clk_out1 : out STD_LOGIC; 18 | clk_out2 : out STD_LOGIC; 19 | reset : in STD_LOGIC; 20 | locked : out STD_LOGIC; 21 | clk_in1 : in STD_LOGIC 22 | ); 23 | 24 | end design_1_clk_wiz_0_1; 25 | 26 | architecture stub of design_1_clk_wiz_0_1 is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; 31 | begin 32 | end; 33 | -------------------------------------------------------------------------------- /src/design/types.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: i2s_types - package 6 | -- 7 | -- Additional Comments: 8 | -- https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ 9 | -- https://statics.cirrus.com/pubs/proDatasheet/CS4344-45-48_F2.pdf 10 | -- PMOD pin 1: MCLK 11 | -- PMOD pin 2 LRCK 12 | -- PMOD pin 3 SCLK 13 | -- PMOD pin 4 SDIN 14 | -- 15 | -- This packagae contains I2S sender configuration constants 16 | ---------------------------------------------------------------------------------- 17 | 18 | library IEEE; 19 | use IEEE.STD_LOGIC_1164.ALL; 20 | use IEEE.NUMERIC_STD.ALL; 21 | use ieee.math_real.all; 22 | 23 | package i2s_types_pkg is 24 | --see datasheet https://statics.cirrus.com/pubs/proDatasheet/CS4344-45-48_F2.pdf 25 | constant MCLK_FREQ : integer := 18432000; -- Hz 26 | constant MCLK_BITS : natural := integer(ceil(log2(real(MCLK_FREQ)))); 27 | 28 | -- 48Khz sample rate 29 | constant LRCK_FREQ : integer := 48000; -- MCLK/384 30 | --24 bits per LRCK phase (low = left channel, high = right channel) 31 | 32 | constant SAMPLE_WIDTH : integer := 24; 33 | subtype sample_t is signed(SAMPLE_WIDTH-1 downto 0); 34 | 35 | --exactly 2*24 bits in an LRCK frame 36 | constant SCLK_FREQ : integer := LRCK_FREQ * 2 * SAMPLE_WIDTH; 37 | 38 | --used to support debugging with optional embedded ila 39 | attribute mark_debug : string; 40 | attribute keep : string; 41 | end; 42 | 43 | package body i2s_types_pkg is 44 | 45 | 46 | end; 47 | 48 | -------------------------------------------------------------------------------- /src/testbench/i2s_testbench.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 06/19/2018 12:07:00 AM 6 | -- Design Name: 7 | -- Module Name: testbench - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | library IEEE; 22 | use IEEE.STD_LOGIC_1164.ALL; 23 | 24 | use IEEE.NUMERIC_STD.ALL; 25 | 26 | use work.i2s_types_pkg.all; 27 | 28 | entity i2s_testbench is 29 | -- Port ( ); 30 | end i2s_testbench ; 31 | 32 | architecture Behavioral of i2s_testbench is 33 | signal clock: std_logic := '0'; 34 | signal resetn: std_logic := '0'; 35 | 36 | 37 | signal MCLK: std_logic := '0'; 38 | signal SCLK: std_logic := '0'; 39 | signal SDIN: std_logic := '0'; 40 | signal LRCK: std_logic := '0'; 41 | signal wave_left: sample_t; 42 | signal wave_right: sample_t; 43 | 44 | signal shift_reg: std_logic_vector(23 downto 0); 45 | 46 | 47 | begin 48 | 49 | resetn <= '0', '1' after 100ns; 50 | clock <= not clock after 10 ns; 51 | MCLK <= not MCLK after 27.1267361111 ns; -- 18.4320 Mhz 52 | 53 | sqwv : entity work.square_wave 54 | port map ( 55 | resetn => resetn, 56 | MCLK_in => MCLK, 57 | wave_left_out => wave_left, 58 | wave_right_out => wave_right 59 | ); 60 | 61 | i2s : entity work.i2s_sender 62 | port map ( 63 | MCLK_in => MCLK, 64 | resetn => resetn, 65 | LRCK_out => LRCK, 66 | SCLK_out => SCLK, 67 | SDIN_out => SDIN, 68 | wave_left_in => wave_left, 69 | wave_right_in => wave_right 70 | ); 71 | end Behavioral; 72 | -------------------------------------------------------------------------------- /src/testbench/wave/wave_testbench_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | MCLK 32 | MCLK 33 | 34 | 35 | resetn 36 | resetn 37 | 38 | 39 | freq[19:0] 40 | freq[19:0] 41 | 42 | 43 | wave[23:0] 44 | wave[23:0] 45 | 46 | 47 | wave[23:0] 48 | wave[23:0] 49 | STYLE_ANALOG 50 | 100 51 | SIGNEDDECRADIX 52 | 53 | 54 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: design_1_clk_wiz_0_1_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 10.000 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: design_1_clk_wiz_0_1.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 10.000 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 58 | 59 | 60 | set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] 61 | -------------------------------------------------------------------------------- /src/testbench/i2s_sine/i2s_sine_testbench.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: TFG 3 | -- Engineer: D.W.J. Bosman 4 | -- 5 | -- Create Date: 06/19/2018 12:07:00 AM 6 | -- Design Name: 7 | -- Module Name: testbench - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- Test bench for Advance_Phase and Calculate_Phase_Step functions 13 | -- 14 | -- Dependencies: 15 | -- 16 | -- Revision: 17 | -- Revision 0.01 - File Created 18 | -- Additional Comments: 19 | -- 20 | ---------------------------------------------------------------------------------- 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.NUMERIC_STD.ALL; 25 | use work.types_pkg.all; 26 | use work.sine_generator_types_pkg.all; 27 | use STD.textio.all; 28 | use ieee.math_real.all; 29 | 30 | entity i2s_sine_testbench is 31 | -- Port ( ); 32 | end i2s_sine_testbench ; 33 | 34 | architecture Behavioral of i2s_sine_testbench is 35 | signal MCLK: std_logic := '0'; 36 | signal SCLK: std_logic := '0'; 37 | signal SDIN: std_logic := '0'; 38 | signal LRCK: std_logic := '0'; 39 | 40 | signal resetn: std_logic := '0'; 41 | signal freq : frequency_t; 42 | signal freq_ce: std_logic; 43 | signal wave: sample_t; 44 | 45 | 46 | /** 47 | 48 | signal iteration: unsigned(19 downto 0); 49 | signal monitor_sin : signed(23 downto 0); 50 | signal dummy_cos : signed(23 downto 0); 51 | **/ 52 | begin 53 | Report_Constants(0); 54 | 55 | resetn <= '0', '1' after 100ns; 56 | MCLK <= not MCLK after 27.1267361111 ns; -- 18.4320 Mhz 57 | 58 | wave_gen: entity work.sine_wave 59 | port map ( 60 | resetn => resetn, 61 | MCLK_in => MCLK, 62 | sample_clk_in => LRCK, 63 | freq_in => freq, 64 | freq_in_ce => freq_ce, 65 | wave_out => wave 66 | ); 67 | 68 | i2s : entity work.i2s_sender 69 | port map ( 70 | MCLK_in => MCLK, 71 | resetn => resetn, 72 | LRCK_out => LRCK, 73 | SCLK_out => SCLK, 74 | SDIN_out => SDIN, 75 | wave_left_in => wave, 76 | wave_right_in => wave 77 | ); 78 | 79 | tst_process : process(MCLK,resetn) is 80 | variable iteration: unsigned(63 downto 0); 81 | begin 82 | if resetn = '0' then -- ASynchronous reset (active low) 83 | iteration := (others => '0'); 84 | elsif (MCLK'event) and (MCLK = '1') then 85 | iteration := iteration + 1; 86 | end if; 87 | 88 | if iteration=25 then 89 | freq_ce <= '1'; 90 | -- at iteration 100 set the frequency to 440 Hz. 91 | freq <= to_unsigned(440 * POWER2_PHASE_STEP, freq'length); 92 | else 93 | freq_ce <= '0'; 94 | freq <= (others => '0'); 95 | end if; 96 | 97 | end process; 98 | 99 | end Behavioral; 100 | -------------------------------------------------------------------------------- /src/design/square_wave.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: square_wave - Behavioral 6 | -- 7 | -- Additional Comments: 8 | -- utility component which generates a square wave. Used for testing other components 9 | -- note: frequency is not accurate. 10 | -- 11 | ---------------------------------------------------------------------------------- 12 | 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | 16 | use IEEE.NUMERIC_STD.ALL; 17 | use work.i2s_types_pkg.all; 18 | use ieee.math_real.all; 19 | 20 | entity square_wave is 21 | Port ( resetn : std_logic; 22 | MCLK_in : in std_logic; 23 | wave_left_out : out sample_t; 24 | wave_right_out : out sample_t 25 | ); 26 | 27 | -- Approximate frequencies of left and right test audio signals 28 | constant WAVE_LEFT_FREQ : integer := 440; 29 | constant WAVE_RIGHT_FREQ : integer := 880; 30 | --Change square wave phase every _DIV ticks of SCLK 31 | constant WAVE_LEFT_DIV : integer := (MCLK_FREQ / (WAVE_LEFT_FREQ*2)) -1; 32 | constant WAVE_RIGHT_DIV : integer := (MCLK_FREQ / (WAVE_RIGHT_FREQ*2)) -1; 33 | 34 | --required number of bits for the dividers 35 | constant WAVE_LEFT_DIV_BITS : natural := integer(ceil(log2(real(WAVE_LEFT_DIV)))); 36 | constant WAVE_RIGHT_DIV_BITS : natural := integer(ceil(log2(real(WAVE_RIGHT_DIV)))); 37 | 38 | -- amplitude is max amplitude/8 39 | constant MAX_WAVE : sample_t := to_signed(2**(SAMPLE_WIDTH-3), SAMPLE_WIDTH)+1; 40 | 41 | end square_wave; 42 | 43 | architecture Behavioral of square_wave is 44 | subtype div_wave_left_t is unsigned(WAVE_LEFT_DIV_BITS-1 downto 0); 45 | subtype div_wave_right_t is unsigned(WAVE_RIGHT_DIV_BITS-1 downto 0); 46 | 47 | signal wave_left_cnt : div_wave_left_t; 48 | signal wave_right_cnt : div_wave_right_t; 49 | signal dummy: std_logic; 50 | begin 51 | testseq2 : process (dummy) is 52 | begin 53 | --print the dividers once 54 | report "WAVE_LEFT_DIV " & integer'image(WAVE_LEFT_DIV); 55 | report "WAVE_RIGHT_DIV " & integer'image(WAVE_RIGHT_DIV); 56 | report "WAVE_LEFT_DIV_BITS " & integer'image(WAVE_LEFT_DIV_BITS); 57 | report "WAVE_RIGHT_DIV_BITS " & integer'image(WAVE_RIGHT_DIV_BITS); 58 | 59 | end process; 60 | 61 | -- a process to generate the audio waveform 62 | waveform_process : process (MCLK_in, resetn) is --runs at Fs 63 | begin 64 | if resetn = '0' then -- ASynchronous reset (active low) 65 | wave_left_cnt <= (others => '0'); 66 | wave_right_cnt <= (others => '0'); 67 | 68 | wave_left_out <= MAX_WAVE; 69 | wave_right_out <= -MAX_WAVE; 70 | elsif (MCLK_in'event) and (MCLK_in = '1') then 71 | 72 | if wave_left_cnt = WAVE_LEFT_DIV then 73 | wave_left_cnt <= (others => '0'); 74 | wave_left_out <= -wave_left_out; 75 | else 76 | wave_left_cnt <= wave_left_cnt +1; 77 | end if; 78 | 79 | if wave_right_cnt = WAVE_RIGHT_DIV then 80 | wave_right_cnt <= (others => '0'); 81 | wave_right_out <= -wave_right_out; 82 | else 83 | wave_right_cnt <= wave_right_cnt +1; 84 | end if; 85 | end if; 86 | end process; 87 | 88 | end Behavioral; 89 | -------------------------------------------------------------------------------- /src/design/sine_wave.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: sine_wave - Behavioral 6 | -- 7 | -- Additional Comments: 8 | -- blog post: 9 | -- 10 | ---------------------------------------------------------------------------------- 11 | 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | use IEEE.NUMERIC_STD.ALL; 16 | use ieee.math_real.all; 17 | use work.i2s_types_pkg.all; 18 | use work.sine_generator_types_pkg.all; 19 | 20 | entity sine_wave is 21 | Port ( resetn : std_logic; 22 | MCLK_in : in std_logic; -- Master clock of the I2S Sender 23 | sample_clk_in : in std_logic; -- the sample clock (eg. 48kHz) 24 | 25 | freq_in_ce: in std_logic; -- if '1' freq_in will be sampled on next rising edge 26 | freq_in: in frequency_t; -- the scaled frequency (POWER2_PHASE_STEP) of the sine 27 | 28 | wave_out : out sample_t -- the generated output samples 29 | 30 | ); 31 | end sine_wave; 32 | 33 | architecture Behavioral of sine_wave is 34 | 35 | signal sin_clk_en : std_logic; 36 | signal dummy_cos : sample_t; 37 | 38 | signal phase : phase_state_t; 39 | signal phase_step: phase_step_t; 40 | begin 41 | 42 | -- Note: with taylor_order => 1 there is a sign overflow 43 | -- TODO determine required addrbits, extrabits.... 44 | gen0: entity work.sincos_gen 45 | generic map ( 46 | data_bits => sample_t'length, 47 | phase_bits => POWER2_PHASE_SPACE_BITS, 48 | phase_extrabits => 2, 49 | table_addrbits => 10, 50 | taylor_order => 2 ) 51 | port map ( 52 | clk => MCLK_in, 53 | clk_en => sin_clk_en, 54 | in_phase => phase.current, 55 | out_sin => wave_out, 56 | out_cos => dummy_cos ); 57 | 58 | --a process that updates the phase_step when a new frequency is set 59 | freq_process : process (MCLK_in, resetn) is 60 | variable phase_step_internal : phase_step_t; 61 | begin 62 | if resetn = '0' then -- ASynchronous reset (active low) 63 | phase_step_internal := ZERO_PHASE_STEP; 64 | elsif (MCLK_in'event) and (MCLK_in = '1') then 65 | if freq_in_ce = '1' then 66 | -- update phase_step_internal based on the new freq_in value 67 | Calculate_Phase_Step(freq_in,phase_step_internal); 68 | end if; 69 | end if; 70 | --assign to a signal so we can use it outside the process and debug 71 | phase_step <= phase_step_internal; 72 | end process; 73 | 74 | -- a process to generate the audio waveform 75 | waveform_process : process (sample_clk_in, resetn) is --runs at Fs 76 | variable internal_phase: phase_state_t; 77 | begin 78 | if resetn = '0' then -- ASynchronous reset (active low) 79 | internal_phase := ZERO_PHASE_STATE; 80 | sin_clk_en <= '0'; 81 | elsif (sample_clk_in'event) and (sample_clk_in = '1') then 82 | sin_clk_en <= '1'; 83 | internal_phase.step := phase_step; 84 | Advance_Phase(internal_phase); 85 | end if; 86 | --assign to signal so we can use it outside the process 87 | phase <= internal_phase; 88 | end process; 89 | end Behavioral; 90 | -------------------------------------------------------------------------------- /src/testbench/wave/wave_testbench.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: TFG 3 | -- Engineer: D.W.J. Bosman 4 | -- 5 | -- Create Date: 06/19/2018 12:07:00 AM 6 | -- Design Name: 7 | -- Module Name: testbench - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- Test bench for Advance_Phase and Calculate_Phase_Step functions 13 | -- 14 | -- Dependencies: 15 | -- 16 | -- Revision: 17 | -- Revision 0.01 - File Created 18 | -- Additional Comments: 19 | -- 20 | ---------------------------------------------------------------------------------- 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.NUMERIC_STD.ALL; 25 | use work.types_pkg.all; 26 | use work.sine_generator_types_pkg.all; 27 | use STD.textio.all; 28 | use ieee.math_real.all; 29 | 30 | entity wave_testbench is 31 | -- Port ( ); 32 | end wave_testbench ; 33 | 34 | architecture Behavioral of wave_testbench is 35 | signal MCLK: std_logic := '0'; 36 | signal resetn: std_logic := '0'; 37 | 38 | signal freq : frequency_t; 39 | signal freq_ce: std_logic; 40 | signal wave: sample_t; 41 | 42 | /** 43 | 44 | signal iteration: unsigned(19 downto 0); 45 | signal monitor_sin : signed(23 downto 0); 46 | signal dummy_cos : signed(23 downto 0); 47 | **/ 48 | begin 49 | Report_Constants(0); 50 | 51 | resetn <= '0', '1' after 100ns; 52 | MCLK <= not MCLK after 27.1267361111 ns; -- 18.4320 Mhz 53 | 54 | /** 55 | -- test the sincos generator 56 | gen0: entity work.sincos_gen 57 | generic map ( 58 | data_bits => 24, 59 | phase_bits => 20, 60 | phase_extrabits => 2, 61 | table_addrbits => 10, 62 | taylor_order => 2 ) 63 | port map ( 64 | clk => MCLK, 65 | clk_en => resetn, 66 | in_phase => iteration, 67 | out_sin => monitor_sin, 68 | out_cos => dummy_cos ); 69 | 70 | 71 | tst_process : process(MCLK,resetn) is 72 | begin 73 | if resetn = '0' then -- ASynchronous reset (active low) 74 | iteration <= (others => '0'); 75 | elsif (MCLK'event) and (MCLK = '1') then 76 | --if div_cnt = 9 then 77 | -- div_cnt <= 0; 78 | iteration <= iteration + 1; --to_unsigned(1, iteration'length); --iteration + 1; 79 | --else 80 | -- div_cnt <= div_cnt + 1; 81 | --end if; 82 | end if; 83 | end process; 84 | **/ 85 | 86 | 87 | wave_gen: entity work.sine_wave 88 | port map ( 89 | resetn => resetn, 90 | MCLK_in => MCLK, 91 | freq_in => freq, 92 | freq_in_ce => freq_ce, 93 | wave_out => wave); 94 | 95 | 96 | 97 | tst_process : process(MCLK,resetn) is 98 | variable iteration: unsigned(63 downto 0); 99 | begin 100 | if resetn = '0' then -- ASynchronous reset (active low) 101 | iteration := (others => '0'); 102 | elsif (MCLK'event) and (MCLK = '1') then 103 | iteration := iteration + 1; 104 | end if; 105 | 106 | if iteration=100 then 107 | freq_ce <= '1'; 108 | -- at iteration 100 set the frequency to 440 Hz. 109 | freq <= to_unsigned(440 * POWER2_PHASE_STEP, freq'length); 110 | else 111 | freq_ce <= '0'; 112 | freq <= (others => '0'); 113 | end if; 114 | 115 | end process; 116 | 117 | end Behavioral; 118 | -------------------------------------------------------------------------------- /src/testbench/i2s_testbench_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | clock 26 | clock 27 | 28 | 29 | resetn 30 | resetn 31 | 32 | 33 | MCLK 34 | MCLK 35 | 36 | 37 | SCLK 38 | SCLK 39 | 40 | 41 | LRCK 42 | LRCK 43 | 44 | 45 | SDIN 46 | SDIN 47 | 48 | 49 | wave_left[23:0] 50 | wave_left[23:0] 51 | BINARYRADIX 52 | 53 | 54 | wave_right[23:0] 55 | wave_right[23:0] 56 | BINARYRADIX 57 | 58 | 59 | SDIN_cnt 60 | SDIN_cnt 61 | 62 | 63 | wave_left[23:0] 64 | wave_left[23:0] 65 | 66 | 67 | wave_right[23:0] 68 | wave_right[23:0] 69 | 70 | 71 | shift_reg[23:0] 72 | shift_reg[23:0] 73 | BINARYRADIX 74 | 75 | 76 | -------------------------------------------------------------------------------- /src/testbench/i2s_sine/i2s_sine_testbench_behav.wcfg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | MCLK 28 | MCLK 29 | 30 | 31 | resetn 32 | resetn 33 | 34 | 35 | freq_ce 36 | freq_ce 37 | 38 | 39 | freq[19:0] 40 | freq[19:0] 41 | 42 | 43 | LRCK 44 | LRCK 45 | 46 | 47 | SCLK 48 | SCLK 49 | 50 | 51 | SDIN 52 | SDIN 53 | 54 | 55 | SDIN_cnt 56 | SDIN_cnt 57 | 58 | 59 | shift_reg[23:0] 60 | shift_reg[23:0] 61 | BINARYRADIX 62 | 63 | 64 | wave[23:0] 65 | wave[23:0] 66 | HEXRADIX 67 | 68 | 69 | wave[23:0] 70 | wave[23:0] 71 | STYLE_ANALOG 72 | 100 73 | SIGNEDDECRADIX 74 | 75 | 76 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1.v: -------------------------------------------------------------------------------- 1 | 2 | // file: design_1_clk_wiz_0_1.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1___100.000______0.000______50.0______122.755_____92.529 60 | // clk_out2____18.432______0.000______50.0______175.761_____92.529 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary_________100.000____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "design_1_clk_wiz_0_1,clk_wiz_v6_0_1_0_0,{component_name=design_1_clk_wiz_0_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module design_1_clk_wiz_0_1 72 | ( 73 | // Clock out ports 74 | output clk_out1, 75 | output clk_out2, 76 | // Status and control signals 77 | input reset, 78 | output locked, 79 | // Clock in ports 80 | input clk_in1 81 | ); 82 | 83 | design_1_clk_wiz_0_1_clk_wiz inst 84 | ( 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | .clk_out2(clk_out2), 88 | // Status and control signals 89 | .reset(reset), 90 | .locked(locked), 91 | // Clock in ports 92 | .clk_in1(clk_in1) 93 | ); 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /src/design/i2s_sender.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: i2s_sender - Behavioral 6 | -- 7 | -- Additional Comments: 8 | -- https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ 9 | -- https://statics.cirrus.com/pubs/proDatasheet/CS4344-45-48_F2.pdf 10 | -- 11 | ---------------------------------------------------------------------------------- 12 | 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | use IEEE.NUMERIC_STD.ALL; 16 | 17 | use work.i2s_types_pkg.all; 18 | 19 | entity i2s_sender is 20 | --wave_x_in are sampled at the rising edge of MCLK 21 | generic ( 22 | DEBUG : boolean := false 23 | ); 24 | Port ( 25 | resetn : in std_logic; 26 | MCLK_in : in std_logic; 27 | LRCK_out : out std_logic; 28 | SCLK_out : out std_logic; 29 | SDIN_out : out std_logic; 30 | wave_left_in : in sample_t; 31 | wave_right_in : in sample_t 32 | ); 33 | end i2s_sender; 34 | 35 | 36 | 37 | architecture Behavioral of i2s_sender is 38 | --Change level every _DIV ticks of MCLK 39 | constant LRCK_DIV : integer := (MCLK_FREQ / (LRCK_FREQ*2)) -1; -- 384/2 -1 = 161 40 | constant SCLK_DIV : integer := (MCLK_FREQ / (SCLK_FREQ*2)) -1; 41 | 42 | --types for various counters 43 | subtype div_LRCK_t is integer range 0 to LRCK_DIV; 44 | subtype div_SCLK_t is integer range 0 to SCLK_DIV; 45 | 46 | --count the number of MCLK ticks before toggling LRCK 47 | signal LRCK_cnt : div_LRCK_t; 48 | --count the number of MCLK ticks before toggling SCLK 49 | signal SCLK_cnt : div_SCLK_t; 50 | 51 | --wave_x_in are sampled at the rising edge of MCLK 52 | signal wave_left : sample_t := (others => '0'); 53 | signal wave_right: sample_t := (others => '0'); 54 | 55 | --Size: SAMPLE_WIDTH+1, one extra bit needed to keep last bit of previous LRCK cycle 56 | signal shift_reg: std_logic_vector(SAMPLE_WIDTH downto 0); 57 | 58 | --set optional debugging signals 59 | attribute mark_debug of shift_reg : signal is boolean'image(DEBUG); 60 | attribute keep of shift_reg : signal is boolean'image(debug); 61 | begin 62 | 63 | 64 | -- synthesis translate_off 65 | debug_process : process is 66 | begin 67 | --print the dividers when in simulation mode 68 | report "MCLK_FREQ hz " & integer'image(MCLK_FREQ); 69 | report "LRCK_FREQ hz " & integer'image(LRCK_FREQ); 70 | report "SCLK_FREQ hz " & integer'image(SCLK_FREQ); 71 | report "SAMPLE_WIDTH " & integer'image(SAMPLE_WIDTH); 72 | 73 | report "LRCK_DIV" & integer'image(LRCK_DIV); 74 | report "SCLK_DIV" & integer'image(SCLK_DIV); 75 | wait; 76 | end process; 77 | -- synthesis translate_on 78 | 79 | -- a process to generate LRCK and SCLK from MCLK 80 | i2s_clk_process : process (MCLK_in, resetn) is 81 | begin 82 | if resetn = '0' then -- ASynchronous reset (active low) 83 | LRCK_out <= '0'; 84 | SCLK_out <= '0'; 85 | 86 | LRCK_cnt <= 0; 87 | SCLK_cnt <= 0; 88 | -- SDIN_cnt <= 0; 89 | wave_left <= (others => '0'); 90 | wave_right <= (others => '0'); 91 | shift_reg <= (others => '0'); 92 | 93 | elsif MCLK_in'event and MCLK_in = '1' then -- Rising clock edge 94 | -- MCLK == 18.4320 Mhz 95 | -- LRCK = MCLK / 384 = 48khz = Fs 96 | -- SCLK = 48 * Fs = MCLK/8 97 | if LRCK_cnt = LRCK_DIV then 98 | LRCK_cnt <=0; 99 | if LRCK_out = '1' then 100 | --falling edge 101 | --assert: SCLK will go low 102 | LRCK_out <= '0'; 103 | -- load shift register for output 104 | -- keep last not yet shifted bit of previous sample. 105 | shift_reg <= shift_reg(shift_reg'HIGH-1) & std_logic_vector(wave_left); 106 | else 107 | -- rising edge 108 | --assert: SCLK will go low 109 | LRCK_out <= '1'; 110 | -- load shift register for output 111 | -- keep last not yet shifted bit of previous sample. 112 | shift_reg <= shift_reg(shift_reg'HIGH-1) & std_logic_vector(wave_right); 113 | end if; 114 | else 115 | if (SCLK_cnt = SCLK_DIV) and (SCLK_out='1') then 116 | --SCLK will go low 117 | --shift one bit to the left 118 | shift_reg <= shift_reg(shift_reg'HIGH-1 downto 0) & '0'; 119 | end if; 120 | LRCK_cnt <= LRCK_cnt + 1; 121 | end if; 122 | 123 | if SCLK_cnt = SCLK_DIV then 124 | SCLK_cnt <=0; 125 | SCLK_out <= not SCLK_out; 126 | else 127 | SCLK_cnt <= SCLK_cnt + 1; 128 | end if; 129 | 130 | --sample data 131 | wave_left <= wave_left_in; 132 | wave_right <= wave_right_in; 133 | end if; 134 | end process; 135 | 136 | SDIN_out <= shift_reg(shift_reg'HIGH); 137 | 138 | end Behavioral; 139 | -------------------------------------------------------------------------------- /src/design/segment_display.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: segment_display - Behavioral 6 | -- 7 | -- Additional Comments: 8 | -- https://pubweb.eng.utah.edu/~nmcdonal/Tutorials/BCDTutorial/BCDConversion.html 9 | -- 10 | ---------------------------------------------------------------------------------- 11 | 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | 15 | use IEEE.NUMERIC_STD.ALL; 16 | use ieee.math_real.all; 17 | use work.types_pkg.all; 18 | use work.sine_generator_types_pkg.all; 19 | 20 | 21 | --implementation of a decimal display consisting of 22 | --led 8 segement components 23 | --TODO generics 24 | entity segment_display is 25 | Port ( resetn : std_logic; 26 | CLK_in : in std_logic; 27 | value_in : in unsigned(31 downto 0); -- the scaled frequency of the sine 28 | ); 29 | end; 30 | 31 | 32 | 33 | architecture Behavioral of segment_display is 34 | signal AN : std_logic_vector(7 downto 0); 35 | signal SSEG_CA : std_logic_vector(7 downto 0); 36 | 37 | type BCD_t : is unsigned(3 downto 0); 38 | constant BCD_ZERO : BCD_t := (others=>'0'); 39 | 40 | signal BCD : array (7 downto 0) of BCD_t; 41 | begin 42 | 43 | --TODO state enum, switch statement 44 | 45 | -- a process that converts the input number to BCD representation 46 | bcd_converter: process (CLK_in, resetn) is 47 | variable bit_counter: integer range 0 to 31; 48 | variable decimal_index: integer range 0 to 7; 49 | variable BCD_build : array (7 downto 0) of BCD_t; 50 | variable BCD_current : BCD_t; 51 | variable value_build : unsigned(31 downto 0); 52 | variable state: BCD_builder_it; 53 | variable carry: std_logic; 54 | begin 55 | 56 | if resetn = '0' then -- ASynchronous reset (active low) 57 | bit_counter := 0; 58 | decimal_index :=0; 59 | BCD_build := (others => BCD_ZERO); 60 | value_build := (others => '0'); 61 | state := START; 62 | elsif (CLK_in'event) and (CLK_in = '1') then 63 | 64 | if state = START then 65 | --initialize by sampling the current value 66 | value_build := value_in; 67 | --reset current BCD representation 68 | BCD_build := (others => BCD_ZERO); 69 | bit_counter :=0; 70 | decimal_index :=0; 71 | state := DECIMALS 72 | elsif state = DECIMALS then 73 | BCD_current := BCD_build(decimal_index); 74 | if (BCD_current>=5 then 75 | BCD_current := BCD_current + 3; 76 | BCD_build(decimal_index) := BCD_current; 77 | end if; 78 | if decimal_index = 7 then 79 | state := SHIFT; 80 | else 81 | decimal_index := decimal_index + 1; 82 | end if; 83 | elsif state = SHIFT then 84 | if decimal_index>0 then 85 | -- shift bcd to the left, use carry from next BCD. 86 | carry:= BCD_build(decimal_index-1)(BCD_t'length-1); 87 | BCD_build(decimal_index) := BCD_build(decimal_index)(3 downto 1) & carry; 88 | decimal_index := decimal_index - 1; 89 | else 90 | -- first BCD, shift left and use carry from value 91 | carry:= value_build(value_build'length-1); 92 | BCD_build(decimal_index) := BCD_build(decimal_index)(3 downto 1) & carry; 93 | 94 | -- shift value left 95 | value_build := shift_left(value_build,1); 96 | if bit_counter = bitcounter'max then 97 | --all done, return the result and restart 98 | BCD <= BCD_build; 99 | state := START; 100 | else 101 | --next iteration 102 | bit_counter := bit_counter + 1; 103 | state := DECIMALS; 104 | end if; 105 | end if; 106 | end if 107 | 108 | 109 | end if; 110 | end process; 111 | 112 | 113 | -- a process that refreshes the display as fast as possible 114 | digit_process: process (CLK_in, resetn) is 115 | 116 | -- led_id: first 3 bits point the segment 117 | -- next 3 bits point to the led in the segment 118 | variable led_id : unsigned(5 downto 0); 119 | variable segment_index : integer range 0 to 7; 120 | variable led_in_segment : integer range 0 to 7; 121 | begin 122 | if resetn = '0' then -- ASynchronous reset (active low) 123 | led_id <= (others => '0'); 124 | AN <= (others => '0'); 125 | SSEG_CA <= (others => '0'); 126 | 127 | elsif (CLK_in'event) and (CLK_in = '1') then 128 | led_id := led_id + 1; 129 | 130 | segment_index := to_integer(led_id(5 downto 3)); 131 | led_in_segment := to_integer(led_id and 7); 132 | 133 | segment_value := BCD(segment_index); 134 | led_representation = value_to_led_representation(segment_value); 135 | 136 | AN <= (segment_index => '1', others=>'0'); 137 | SSEG_CS <= (led_in_segment = led_representation(led_in_segment), others => '0'); 138 | end if; 139 | end process; 140 | 141 | end Behavioral; 142 | -------------------------------------------------------------------------------- /src/design/design_1_wrapper.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: top level wrapper module 6 | -- 7 | -- Additional Comments: 8 | -- https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ 9 | -- https://statics.cirrus.com/pubs/proDatasheet/CS4344-45-48_F2.pdf 10 | -- PMOD pin 1: MCLK 11 | -- PMOD pin 2 LRCK 12 | -- PMOD pin 3 SCLK 13 | -- PMOD pin 4 SDIN 14 | -- 15 | ---------------------------------------------------------------------------------- 16 | 17 | library IEEE; 18 | use IEEE.STD_LOGIC_1164.ALL; 19 | use ieee.numeric_std.all; 20 | 21 | use work.i2s_types_pkg.all; 22 | use work.sine_generator_types_pkg.all; 23 | 24 | entity design_1_wrapper is 25 | generic( 26 | DEBUG: boolean := true 27 | ); 28 | port ( 29 | -- clk_out : out STD_LOGIC; 30 | -- locked_reset : out STD_LOGIC; 31 | CPU_RESETN : in STD_LOGIC; 32 | CLK100MHZ : in STD_LOGIC; 33 | LED: out STD_LOGIC_VECTOR(15 downto 0); 34 | 35 | SSEG_CA: out STD_LOGIC_VECTOR(7 downto 0); --8 segment display 36 | AN: out STD_LOGIC_VECTOR(7 downto 0); --8 segment display 37 | 38 | SW: in std_logic_vector(15 downto 0); -- switches 39 | 40 | -- for i2s pmod 41 | MCLK_out: out STD_LOGIC; 42 | SCLK_out: out STD_LOGIC; 43 | SDIN_out: out STD_LOGIC; 44 | LRCK_out: out STD_LOGIC 45 | ); 46 | end design_1_wrapper; 47 | 48 | architecture STRUCTURE of design_1_wrapper is 49 | 50 | component design_1 is 51 | port ( 52 | sys_clock : in STD_LOGIC; 53 | reset : in STD_LOGIC; 54 | clk_out : out STD_LOGIC; 55 | MCLK_gen_out : out STD_LOGIC; 56 | locked_reset : out STD_LOGIC 57 | ); 58 | end component design_1; 59 | 60 | signal dummy_clk: STD_LOGIC; 61 | signal n_reset: STD_LOGIC; 62 | signal MCLK : std_logic := '0'; 63 | 64 | --wave_left, right contain the result samples 65 | --from eighter sine wave or square wave based on switches 66 | signal wave_left: sample_t := (others=> '0'); 67 | signal wave_right: sample_t := (others=> '0'); 68 | 69 | 70 | --the square wave generator is just to perform basic 71 | --i2s tests, it is not frequency accurate 72 | signal wave_left_sq: sample_t := (others=> '0'); 73 | signal wave_right_sq: sample_t := (others=> '0'); 74 | 75 | --sine oscillator 76 | signal wave_sine: sample_t := (others=> '0'); 77 | signal frequency_ce: std_logic; 78 | signal frequency: frequency_t; 79 | 80 | --for sweep signal 81 | signal second_counter: unsigned(MCLK_BITS-1 downto 0) := (others=> '0'); 82 | 83 | 84 | --allow debugging using ila if DEBUG==true 85 | attribute mark_debug of MCLK_out : signal is boolean'image(DEBUG); 86 | attribute keep of MCLK_out : signal is boolean'image(DEBUG); 87 | 88 | attribute mark_debug of LRCK_out : signal is boolean'image(DEBUG); 89 | attribute keep of LRCK_out : signal is boolean'image(DEBUG); 90 | 91 | attribute mark_debug of SCLK_out : signal is boolean'image(DEBUG); 92 | attribute keep of SCLK_out : signal is boolean'image(DEBUG); 93 | 94 | attribute mark_debug of SDIN_out : signal is boolean'image(DEBUG); 95 | attribute keep of SDIN_out : signal is boolean'image(DEBUG); 96 | 97 | attribute mark_debug of wave_left : signal is boolean'image(DEBUG); 98 | attribute keep of wave_left : signal is boolean'image(DEBUG); 99 | 100 | begin 101 | 102 | --use block design 103 | design_1_i: component design_1 104 | port map ( 105 | 106 | clk_out => dummy_clk, 107 | MCLK_gen_out => MCLK, 108 | locked_reset => n_reset, 109 | reset => not CPU_RESETN, 110 | sys_clock => CLK100MHZ 111 | ); 112 | 113 | 114 | sqwv : entity work.square_wave 115 | port map ( 116 | resetn => n_reset, 117 | MCLK_in => MCLK, 118 | wave_left_out => wave_left_sq, 119 | wave_right_out => wave_right_sq 120 | ); 121 | 122 | 123 | snwv : entity work.sine_wave 124 | 125 | port map ( 126 | resetn => n_reset, 127 | MCLK_in => MCLK, 128 | freq_in => frequency, 129 | freq_in_ce => frequency_ce, 130 | sample_clk_in => LRCK_out, 131 | wave_out => wave_sine 132 | ); 133 | --switch(0..2) will set a new sine wave frequency 134 | frequency_ce <= '1' when SW(0) or SW(1) or SW(2) else '0'; 135 | 136 | -- press button 0 to get 440 hz 137 | -- press button 1 to get 880 hz 138 | -- button 2 -> sweep from 100 Hz to 100+4*255 Hz in one second 139 | -- button 3, 4 turn on square wave 140 | frequency <= to_unsigned(440 * POWER2_PHASE_STEP, frequency'length) when SW(0) else 141 | to_unsigned(880 * POWER2_PHASE_STEP, frequency'length) when SW(1) else 142 | to_unsigned(100* POWER2_PHASE_STEP, frequency'length) + 143 | resize( 144 | to_unsigned( 4 * POWER2_PHASE_STEP, frequency'length) 145 | * second_counter(second_counter'length -1 downto second_counter'length -1 -7), frequency'length 146 | ) when SW(2) else 147 | (others => '0'); 148 | 149 | --select the oscillator to output: switch (0..2) -> sine oscillator, switch(3..4) -> square wave 150 | wave_left <= wave_sine when SW(3) else 151 | wave_left_sq when SW(4) else 152 | wave_right_sq when SW(5) else 153 | (others => '0'); 154 | 155 | --for this test copy left channel to right channel 156 | wave_right <= wave_left; 157 | 158 | i2s : entity work.i2s_sender 159 | generic map ( 160 | DEBUG => true 161 | ) 162 | port map ( 163 | resetn => n_reset, 164 | MCLK_in => MCLK, 165 | SCLK_out => SCLK_out, 166 | LRCK_out => LRCK_out, 167 | SDIN_out => SDIN_out, 168 | wave_left_in => wave_left, 169 | wave_right_in => wave_right 170 | ); 171 | MCLK_out <= MCLK; 172 | 173 | --define a counter that increments every time a bit is transmitted to the DA chip 174 | led_process : process (MCLK, n_reset) is 175 | variable old: std_logic; 176 | variable cnt : unsigned(15 downto 0); 177 | begin 178 | if n_reset = '0' then -- ASynchronous reset (active low) 179 | cnt:= (others => '0'); 180 | old:= '0'; 181 | elsif MCLK'event and MCLK = '1' then -- Rising clock edge 182 | 183 | if old = SDIN_out then -- Rising clock edge 184 | else 185 | old := SDIN_out; 186 | cnt := cnt + 1; 187 | end if; 188 | end if; 189 | LED(15 downto 0) <= std_logic_vector(cnt(15 downto (15-15))); 190 | end process; 191 | 192 | counter_process : process (MCLK, n_reset) is 193 | begin 194 | if n_reset = '0' then -- ASynchronous reset (active low) 195 | second_counter <= (others=>'0'); 196 | elsif (MCLK'event) and (MCLK = '1') then 197 | if second_counter = MCLK_FREQ then 198 | second_counter <= (others=>'0'); 199 | else 200 | second_counter <= second_counter + 1; 201 | end if; 202 | end if; 203 | end process; 204 | 205 | -- turn all led segments off for now 206 | SSEG_CA <= (others => '0'); 207 | AN <= (others => '1'); 208 | 209 | end STRUCTURE; 210 | -------------------------------------------------------------------------------- /src/testbench/sine/sine_testbench.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: TFG 3 | -- Engineer: D.W.J. Bosman 4 | -- 5 | -- Create Date: 06/19/2018 12:07:00 AM 6 | -- Design Name: 7 | -- Module Name: testbench - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- Test bench for Advance_Phase and Calculate_Phase_Step functions 13 | -- 14 | -- Dependencies: 15 | -- 16 | -- Revision: 17 | -- Revision 0.01 - File Created 18 | -- Additional Comments: 19 | -- 20 | ---------------------------------------------------------------------------------- 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.NUMERIC_STD.ALL; 25 | use work.types_pkg.all; 26 | use work.sine_generator_types_pkg.all; 27 | use STD.textio.all; 28 | use ieee.math_real.all; 29 | 30 | entity sine_testbench is 31 | -- Port ( ); 32 | end sine_testbench ; 33 | 34 | architecture Behavioral of sine_testbench is 35 | signal clock: std_logic := '0'; 36 | signal resetn: std_logic := '0'; 37 | 38 | -- Test the Avnce_Phase function 39 | -- 40 | -- Run a number of iterations, each iteration increase the phase 41 | -- the phase calculated by the Advance_Phase function is compared 42 | -- to a direct calculation using float-ing pojnt. 43 | procedure Run_Phase_Steps ( 44 | variable step: in phase_step_t; 45 | variable phase_step_real: in real 46 | ) is 47 | variable phase_state : phase_state_t; 48 | variable expected_phase: real; 49 | variable diff_phase: real; 50 | variable calculated_phase: real; 51 | variable l: line; 52 | variable periods: real; 53 | begin 54 | 55 | phase_state := ZERO_PHASE_STATE; 56 | phase_state.step := step; 57 | 58 | write( l, string'("Step iterations")); 59 | writeline( output, l ); 60 | 61 | for step_iteration in 1 to 2**6 -1 loop 62 | write( l, string'("step=")); 63 | write( l, step_iteration); 64 | writeline( output, l ); 65 | 66 | Advance_Phase(phase_state); 67 | 68 | -- calculate the number of periods (2*pi == POWER2_PHASE_SPACE_SIZE) 69 | periods := (phase_step_real * step_iteration) / POWER2_PHASE_SPACE_SIZE; 70 | -- calculate the expected phase value after a step, subtract the number of periods 71 | -- to perform get the modulus POWER2_PHASE_SPACE_SIZE value. 72 | expected_phase := (phase_step_real * step_iteration) - floor(periods) * POWER2_PHASE_SPACE_SIZE; 73 | calculated_phase := real(to_integer(phase_state.current)) + real(to_integer(phase_state.current_fraction))/SAMPLE_RATE; 74 | diff_phase := expected_phase - calculated_phase; 75 | 76 | write( l, string'("expected phase=")); 77 | write( l, expected_phase); 78 | write( l, string'(" calculated phase=")); 79 | write( l, calculated_phase); 80 | write( l, string'(" diff=")); 81 | write( l, diff_phase); 82 | if (abs(diff_phase)>0.1) then 83 | write( l, string'(" phase error ")); 84 | end if; 85 | writeline( output, l ); 86 | end loop; 87 | 88 | end; 89 | 90 | begin 91 | Report_Constants(0); 92 | 93 | resetn <= '0', '1' after 100ns; 94 | clock <= not clock after 10 ns; 95 | 96 | 97 | tst_process : process is 98 | variable freq_in: frequency_t := to_unsigned(440*32+1, FREQUENCY_SCALED_BITS); 99 | variable freq_real: real; 100 | variable step: phase_step_t; 101 | 102 | variable l: line; 103 | 104 | variable phase_step_real: real; 105 | variable dec_step_real: real; 106 | variable fract_step_real: real; 107 | variable diff_dec: real; 108 | variable diff_fract: real; 109 | variable rnd: unsigned(30 downto 0) := to_unsigned(12, 31); 110 | 111 | 112 | begin 113 | wait for 100ns; 114 | 115 | step := ZERO_PHASE_STEP; 116 | 117 | -- perform the test a number of iterations 118 | -- each iteration: 119 | -- choose a random scaled frequency value 120 | -- calculate the phase step (decimal, fraction) using the Calculate_Phase_Step function 121 | -- calculate the phase step using floating point 122 | -- compare the results 123 | for iteration in 1 to 2**6 -1 loop --frequency_t'length-1 loop 124 | 125 | Rand(rnd); 126 | 127 | --freq_in := to_unsigned(freq_scaled, FREQUENCY_SCALED_BITS); 128 | freq_in := rnd(rnd'left downto rnd'left-frequency_t'length + 1); 129 | 130 | if (freq_in >= to_unsigned(MAX_FREQUENCY_SCALED,frequency_t'length)) then 131 | freq_in := to_unsigned(MAX_FREQUENCY_SCALED-1,frequency_t'length); 132 | end if; 133 | 134 | freq_real := real(to_integer(freq_in)) / POWER2_PHASE_STEP; 135 | 136 | phase_step_real := (real(POWER2_PHASE_SPACE_SIZE) / SAMPLE_RATE) * ( real(to_integer(freq_in)) / POWER2_PHASE_STEP); 137 | dec_step_real := floor(phase_step_real); 138 | fract_step_real := (phase_step_real - dec_step_real) * SAMPLE_RATE; 139 | write( l, string'("truth: f(Hz)=")); 140 | write( l, freq_real); 141 | writeline( output, l ); 142 | 143 | write( l, string'(" f_sc=")); 144 | write( l, to_integer(freq_in)); 145 | 146 | Calculate_Phase_Step(freq_in,step); 147 | 148 | diff_dec:= dec_step_real - real(to_integer(step.decimal)); 149 | diff_fract:= fract_step_real - real(to_integer(step.fraction)); 150 | 151 | 152 | write( l, string'(" p=")); 153 | write( l, phase_step_real); 154 | write( l, string'(" d=")); 155 | write( l, dec_step_real); 156 | write( l, string'(" f=")); 157 | write( l, fract_step_real); 158 | write( l, string'(" actual: d=")); 159 | write( l, to_integer(step.decimal)); 160 | write( l, string'(" f=")); 161 | write( l, to_integer(step.fraction)); 162 | write( l, string'(" dd=")); 163 | write( l, diff_dec); 164 | write( l, string'(" df=")); 165 | write( l, diff_fract); 166 | write( l, string'(" ")); 167 | 168 | if (abs(diff_dec)>0.1) then 169 | write( l, string'("dec error ")); 170 | end if; 171 | if (abs(diff_fract)>0.1) then 172 | write( l, string'("fract error ")); 173 | end if; 174 | 175 | writeline( output, l ); 176 | writeline( output, l ); 177 | 178 | if iteration = 2**6-1 then 179 | Run_Phase_Steps (step, phase_step_real); 180 | 181 | end if; 182 | 183 | wait for 10ns; 184 | end loop; 185 | 186 | 187 | 188 | 189 | wait; 190 | end process; 191 | 192 | 193 | end Behavioral; 194 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_clk_wiz.v: -------------------------------------------------------------------------------- 1 | 2 | // file: design_1_clk_wiz_0_1.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1___100.000______0.000______50.0______122.755_____92.529 60 | // clk_out2____18.432______0.000______50.0______175.761_____92.529 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary_________100.000____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | module design_1_clk_wiz_0_1_clk_wiz 70 | 71 | (// Clock in ports 72 | // Clock out ports 73 | output clk_out1, 74 | output clk_out2, 75 | // Status and control signals 76 | input reset, 77 | output locked, 78 | input clk_in1 79 | ); 80 | // Input buffering 81 | //------------------------------------ 82 | wire clk_in1_design_1_clk_wiz_0_1; 83 | wire clk_in2_design_1_clk_wiz_0_1; 84 | IBUF clkin1_ibufg 85 | (.O (clk_in1_design_1_clk_wiz_0_1), 86 | .I (clk_in1)); 87 | 88 | 89 | 90 | 91 | // Clocking PRIMITIVE 92 | //------------------------------------ 93 | 94 | // Instantiation of the MMCM PRIMITIVE 95 | // * Unused inputs are tied off 96 | // * Unused outputs are labeled unused 97 | 98 | wire clk_out1_design_1_clk_wiz_0_1; 99 | wire clk_out2_design_1_clk_wiz_0_1; 100 | wire clk_out3_design_1_clk_wiz_0_1; 101 | wire clk_out4_design_1_clk_wiz_0_1; 102 | wire clk_out5_design_1_clk_wiz_0_1; 103 | wire clk_out6_design_1_clk_wiz_0_1; 104 | wire clk_out7_design_1_clk_wiz_0_1; 105 | 106 | wire [15:0] do_unused; 107 | wire drdy_unused; 108 | wire psdone_unused; 109 | wire locked_int; 110 | wire clkfbout_design_1_clk_wiz_0_1; 111 | wire clkfbout_buf_design_1_clk_wiz_0_1; 112 | wire clkfboutb_unused; 113 | wire clkout0b_unused; 114 | wire clkout1b_unused; 115 | wire clkout2_unused; 116 | wire clkout2b_unused; 117 | wire clkout3_unused; 118 | wire clkout3b_unused; 119 | wire clkout4_unused; 120 | wire clkout5_unused; 121 | wire clkout6_unused; 122 | wire clkfbstopped_unused; 123 | wire clkinstopped_unused; 124 | wire reset_high; 125 | 126 | MMCME2_ADV 127 | #(.BANDWIDTH ("OPTIMIZED"), 128 | .CLKOUT4_CASCADE ("FALSE"), 129 | .COMPENSATION ("ZHOLD"), 130 | .STARTUP_WAIT ("FALSE"), 131 | .DIVCLK_DIVIDE (1), 132 | .CLKFBOUT_MULT_F (10.875), 133 | .CLKFBOUT_PHASE (0.000), 134 | .CLKFBOUT_USE_FINE_PS ("FALSE"), 135 | .CLKOUT0_DIVIDE_F (10.875), 136 | .CLKOUT0_PHASE (0.000), 137 | .CLKOUT0_DUTY_CYCLE (0.500), 138 | .CLKOUT0_USE_FINE_PS ("FALSE"), 139 | .CLKOUT1_DIVIDE (59), 140 | .CLKOUT1_PHASE (0.000), 141 | .CLKOUT1_DUTY_CYCLE (0.500), 142 | .CLKOUT1_USE_FINE_PS ("FALSE"), 143 | .CLKIN1_PERIOD (10.000)) 144 | mmcm_adv_inst 145 | // Output clocks 146 | ( 147 | .CLKFBOUT (clkfbout_design_1_clk_wiz_0_1), 148 | .CLKFBOUTB (clkfboutb_unused), 149 | .CLKOUT0 (clk_out1_design_1_clk_wiz_0_1), 150 | .CLKOUT0B (clkout0b_unused), 151 | .CLKOUT1 (clk_out2_design_1_clk_wiz_0_1), 152 | .CLKOUT1B (clkout1b_unused), 153 | .CLKOUT2 (clkout2_unused), 154 | .CLKOUT2B (clkout2b_unused), 155 | .CLKOUT3 (clkout3_unused), 156 | .CLKOUT3B (clkout3b_unused), 157 | .CLKOUT4 (clkout4_unused), 158 | .CLKOUT5 (clkout5_unused), 159 | .CLKOUT6 (clkout6_unused), 160 | // Input clock control 161 | .CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_1), 162 | .CLKIN1 (clk_in1_design_1_clk_wiz_0_1), 163 | .CLKIN2 (1'b0), 164 | // Tied to always select the primary input clock 165 | .CLKINSEL (1'b1), 166 | // Ports for dynamic reconfiguration 167 | .DADDR (7'h0), 168 | .DCLK (1'b0), 169 | .DEN (1'b0), 170 | .DI (16'h0), 171 | .DO (do_unused), 172 | .DRDY (drdy_unused), 173 | .DWE (1'b0), 174 | // Ports for dynamic phase shift 175 | .PSCLK (1'b0), 176 | .PSEN (1'b0), 177 | .PSINCDEC (1'b0), 178 | .PSDONE (psdone_unused), 179 | // Other control and status signals 180 | .LOCKED (locked_int), 181 | .CLKINSTOPPED (clkinstopped_unused), 182 | .CLKFBSTOPPED (clkfbstopped_unused), 183 | .PWRDWN (1'b0), 184 | .RST (reset_high)); 185 | assign reset_high = reset; 186 | 187 | assign locked = locked_int; 188 | // Clock Monitor clock assigning 189 | //-------------------------------------- 190 | // Output buffering 191 | //----------------------------------- 192 | 193 | BUFG clkf_buf 194 | (.O (clkfbout_buf_design_1_clk_wiz_0_1), 195 | .I (clkfbout_design_1_clk_wiz_0_1)); 196 | 197 | 198 | 199 | 200 | 201 | 202 | BUFG clkout1_buf 203 | (.O (clk_out1), 204 | .I (clk_out1_design_1_clk_wiz_0_1)); 205 | 206 | 207 | BUFG clkout2_buf 208 | (.O (clk_out2), 209 | .I (clk_out2_design_1_clk_wiz_0_1)); 210 | 211 | 212 | 213 | endmodule 214 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 4 | -- Date : Sat Sep 15 23:16:43 2018 5 | -- Host : dinne-Aspire-VN7-593G running 64-bit Ubuntu 16.04.4 LTS 6 | -- Command : write_vhdl -force -mode funcsim 7 | -- /home/dinne/Xilinx/projects/I2S_sender/vivado_project/vivado_project.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.vhdl 8 | -- Design : design_1_clk_wiz_0_1 9 | -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or 10 | -- synthesized. This netlist cannot be used for SDF annotated simulation. 11 | -- Device : xc7a100tcsg324-1 12 | -- -------------------------------------------------------------------------------- 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | library UNISIM; 16 | use UNISIM.VCOMPONENTS.ALL; 17 | entity design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz is 18 | port ( 19 | clk_out1 : out STD_LOGIC; 20 | clk_out2 : out STD_LOGIC; 21 | reset : in STD_LOGIC; 22 | locked : out STD_LOGIC; 23 | clk_in1 : in STD_LOGIC 24 | ); 25 | attribute ORIG_REF_NAME : string; 26 | attribute ORIG_REF_NAME of design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz : entity is "design_1_clk_wiz_0_1_clk_wiz"; 27 | end design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz; 28 | 29 | architecture STRUCTURE of design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz is 30 | signal clk_in1_design_1_clk_wiz_0_1 : STD_LOGIC; 31 | signal clk_out1_design_1_clk_wiz_0_1 : STD_LOGIC; 32 | signal clk_out2_design_1_clk_wiz_0_1 : STD_LOGIC; 33 | signal clkfbout_buf_design_1_clk_wiz_0_1 : STD_LOGIC; 34 | signal clkfbout_design_1_clk_wiz_0_1 : STD_LOGIC; 35 | signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; 36 | signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; 37 | signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; 38 | signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; 39 | signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; 40 | signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; 41 | signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; 42 | signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; 43 | signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; 44 | signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; 45 | signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; 46 | signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; 47 | signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; 48 | signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; 49 | signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); 50 | attribute BOX_TYPE : string; 51 | attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; 52 | attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; 53 | attribute CAPACITANCE : string; 54 | attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; 55 | attribute IBUF_DELAY_VALUE : string; 56 | attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; 57 | attribute IFD_DELAY_VALUE : string; 58 | attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; 59 | attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; 60 | attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; 61 | attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; 62 | begin 63 | clkf_buf: unisim.vcomponents.BUFG 64 | port map ( 65 | I => clkfbout_design_1_clk_wiz_0_1, 66 | O => clkfbout_buf_design_1_clk_wiz_0_1 67 | ); 68 | clkin1_ibufg: unisim.vcomponents.IBUF 69 | generic map( 70 | IOSTANDARD => "DEFAULT" 71 | ) 72 | port map ( 73 | I => clk_in1, 74 | O => clk_in1_design_1_clk_wiz_0_1 75 | ); 76 | clkout1_buf: unisim.vcomponents.BUFG 77 | port map ( 78 | I => clk_out1_design_1_clk_wiz_0_1, 79 | O => clk_out1 80 | ); 81 | clkout2_buf: unisim.vcomponents.BUFG 82 | port map ( 83 | I => clk_out2_design_1_clk_wiz_0_1, 84 | O => clk_out2 85 | ); 86 | mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV 87 | generic map( 88 | BANDWIDTH => "OPTIMIZED", 89 | CLKFBOUT_MULT_F => 10.875000, 90 | CLKFBOUT_PHASE => 0.000000, 91 | CLKFBOUT_USE_FINE_PS => false, 92 | CLKIN1_PERIOD => 10.000000, 93 | CLKIN2_PERIOD => 0.000000, 94 | CLKOUT0_DIVIDE_F => 10.875000, 95 | CLKOUT0_DUTY_CYCLE => 0.500000, 96 | CLKOUT0_PHASE => 0.000000, 97 | CLKOUT0_USE_FINE_PS => false, 98 | CLKOUT1_DIVIDE => 59, 99 | CLKOUT1_DUTY_CYCLE => 0.500000, 100 | CLKOUT1_PHASE => 0.000000, 101 | CLKOUT1_USE_FINE_PS => false, 102 | CLKOUT2_DIVIDE => 1, 103 | CLKOUT2_DUTY_CYCLE => 0.500000, 104 | CLKOUT2_PHASE => 0.000000, 105 | CLKOUT2_USE_FINE_PS => false, 106 | CLKOUT3_DIVIDE => 1, 107 | CLKOUT3_DUTY_CYCLE => 0.500000, 108 | CLKOUT3_PHASE => 0.000000, 109 | CLKOUT3_USE_FINE_PS => false, 110 | CLKOUT4_CASCADE => false, 111 | CLKOUT4_DIVIDE => 1, 112 | CLKOUT4_DUTY_CYCLE => 0.500000, 113 | CLKOUT4_PHASE => 0.000000, 114 | CLKOUT4_USE_FINE_PS => false, 115 | CLKOUT5_DIVIDE => 1, 116 | CLKOUT5_DUTY_CYCLE => 0.500000, 117 | CLKOUT5_PHASE => 0.000000, 118 | CLKOUT5_USE_FINE_PS => false, 119 | CLKOUT6_DIVIDE => 1, 120 | CLKOUT6_DUTY_CYCLE => 0.500000, 121 | CLKOUT6_PHASE => 0.000000, 122 | CLKOUT6_USE_FINE_PS => false, 123 | COMPENSATION => "ZHOLD", 124 | DIVCLK_DIVIDE => 1, 125 | IS_CLKINSEL_INVERTED => '0', 126 | IS_PSEN_INVERTED => '0', 127 | IS_PSINCDEC_INVERTED => '0', 128 | IS_PWRDWN_INVERTED => '0', 129 | IS_RST_INVERTED => '0', 130 | REF_JITTER1 => 0.010000, 131 | REF_JITTER2 => 0.010000, 132 | SS_EN => "FALSE", 133 | SS_MODE => "CENTER_HIGH", 134 | SS_MOD_PERIOD => 10000, 135 | STARTUP_WAIT => false 136 | ) 137 | port map ( 138 | CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_1, 139 | CLKFBOUT => clkfbout_design_1_clk_wiz_0_1, 140 | CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, 141 | CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, 142 | CLKIN1 => clk_in1_design_1_clk_wiz_0_1, 143 | CLKIN2 => '0', 144 | CLKINSEL => '1', 145 | CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, 146 | CLKOUT0 => clk_out1_design_1_clk_wiz_0_1, 147 | CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, 148 | CLKOUT1 => clk_out2_design_1_clk_wiz_0_1, 149 | CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, 150 | CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, 151 | CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, 152 | CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, 153 | CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, 154 | CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, 155 | CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, 156 | CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, 157 | DADDR(6 downto 0) => B"0000000", 158 | DCLK => '0', 159 | DEN => '0', 160 | DI(15 downto 0) => B"0000000000000000", 161 | DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), 162 | DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, 163 | DWE => '0', 164 | LOCKED => locked, 165 | PSCLK => '0', 166 | PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, 167 | PSEN => '0', 168 | PSINCDEC => '0', 169 | PWRDWN => '0', 170 | RST => reset 171 | ); 172 | end STRUCTURE; 173 | library IEEE; 174 | use IEEE.STD_LOGIC_1164.ALL; 175 | library UNISIM; 176 | use UNISIM.VCOMPONENTS.ALL; 177 | entity design_1_clk_wiz_0_1 is 178 | port ( 179 | clk_out1 : out STD_LOGIC; 180 | clk_out2 : out STD_LOGIC; 181 | reset : in STD_LOGIC; 182 | locked : out STD_LOGIC; 183 | clk_in1 : in STD_LOGIC 184 | ); 185 | attribute NotValidForBitStream : boolean; 186 | attribute NotValidForBitStream of design_1_clk_wiz_0_1 : entity is true; 187 | end design_1_clk_wiz_0_1; 188 | 189 | architecture STRUCTURE of design_1_clk_wiz_0_1 is 190 | begin 191 | inst: entity work.design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz 192 | port map ( 193 | clk_in1 => clk_in1, 194 | clk_out1 => clk_out1, 195 | clk_out2 => clk_out2, 196 | locked => locked, 197 | reset => reset 198 | ); 199 | end STRUCTURE; 200 | -------------------------------------------------------------------------------- /src/blockdesign/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018 4 | // Date : Sat Sep 15 23:16:43 2018 5 | // Host : dinne-Aspire-VN7-593G running 64-bit Ubuntu 16.04.4 LTS 6 | // Command : write_verilog -force -mode funcsim 7 | // /home/dinne/Xilinx/projects/I2S_sender/vivado_project/vivado_project.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_1/design_1_clk_wiz_0_1_sim_netlist.v 8 | // Design : design_1_clk_wiz_0_1 9 | // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified 10 | // or synthesized. This netlist cannot be used for SDF annotated simulation. 11 | // Device : xc7a100tcsg324-1 12 | // -------------------------------------------------------------------------------- 13 | `timescale 1 ps / 1 ps 14 | 15 | (* NotValidForBitStream *) 16 | module design_1_clk_wiz_0_1 17 | (clk_out1, 18 | clk_out2, 19 | reset, 20 | locked, 21 | clk_in1); 22 | output clk_out1; 23 | output clk_out2; 24 | input reset; 25 | output locked; 26 | input clk_in1; 27 | 28 | (* IBUF_LOW_PWR *) wire clk_in1; 29 | wire clk_out1; 30 | wire clk_out2; 31 | wire locked; 32 | wire reset; 33 | 34 | design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz inst 35 | (.clk_in1(clk_in1), 36 | .clk_out1(clk_out1), 37 | .clk_out2(clk_out2), 38 | .locked(locked), 39 | .reset(reset)); 40 | endmodule 41 | 42 | (* ORIG_REF_NAME = "design_1_clk_wiz_0_1_clk_wiz" *) 43 | module design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz 44 | (clk_out1, 45 | clk_out2, 46 | reset, 47 | locked, 48 | clk_in1); 49 | output clk_out1; 50 | output clk_out2; 51 | input reset; 52 | output locked; 53 | input clk_in1; 54 | 55 | wire clk_in1; 56 | wire clk_in1_design_1_clk_wiz_0_1; 57 | wire clk_out1; 58 | wire clk_out1_design_1_clk_wiz_0_1; 59 | wire clk_out2; 60 | wire clk_out2_design_1_clk_wiz_0_1; 61 | wire clkfbout_buf_design_1_clk_wiz_0_1; 62 | wire clkfbout_design_1_clk_wiz_0_1; 63 | wire locked; 64 | wire reset; 65 | wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED; 66 | wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; 67 | wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; 68 | wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; 69 | wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; 70 | wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; 71 | wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; 72 | wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED; 73 | wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED; 74 | wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED; 75 | wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED; 76 | wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED; 77 | wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED; 78 | wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED; 79 | wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED; 80 | 81 | (* BOX_TYPE = "PRIMITIVE" *) 82 | BUFG clkf_buf 83 | (.I(clkfbout_design_1_clk_wiz_0_1), 84 | .O(clkfbout_buf_design_1_clk_wiz_0_1)); 85 | (* BOX_TYPE = "PRIMITIVE" *) 86 | (* CAPACITANCE = "DONT_CARE" *) 87 | (* IBUF_DELAY_VALUE = "0" *) 88 | (* IFD_DELAY_VALUE = "AUTO" *) 89 | IBUF #( 90 | .IOSTANDARD("DEFAULT")) 91 | clkin1_ibufg 92 | (.I(clk_in1), 93 | .O(clk_in1_design_1_clk_wiz_0_1)); 94 | (* BOX_TYPE = "PRIMITIVE" *) 95 | BUFG clkout1_buf 96 | (.I(clk_out1_design_1_clk_wiz_0_1), 97 | .O(clk_out1)); 98 | (* BOX_TYPE = "PRIMITIVE" *) 99 | BUFG clkout2_buf 100 | (.I(clk_out2_design_1_clk_wiz_0_1), 101 | .O(clk_out2)); 102 | (* BOX_TYPE = "PRIMITIVE" *) 103 | MMCME2_ADV #( 104 | .BANDWIDTH("OPTIMIZED"), 105 | .CLKFBOUT_MULT_F(10.875000), 106 | .CLKFBOUT_PHASE(0.000000), 107 | .CLKFBOUT_USE_FINE_PS("FALSE"), 108 | .CLKIN1_PERIOD(10.000000), 109 | .CLKIN2_PERIOD(0.000000), 110 | .CLKOUT0_DIVIDE_F(10.875000), 111 | .CLKOUT0_DUTY_CYCLE(0.500000), 112 | .CLKOUT0_PHASE(0.000000), 113 | .CLKOUT0_USE_FINE_PS("FALSE"), 114 | .CLKOUT1_DIVIDE(59), 115 | .CLKOUT1_DUTY_CYCLE(0.500000), 116 | .CLKOUT1_PHASE(0.000000), 117 | .CLKOUT1_USE_FINE_PS("FALSE"), 118 | .CLKOUT2_DIVIDE(1), 119 | .CLKOUT2_DUTY_CYCLE(0.500000), 120 | .CLKOUT2_PHASE(0.000000), 121 | .CLKOUT2_USE_FINE_PS("FALSE"), 122 | .CLKOUT3_DIVIDE(1), 123 | .CLKOUT3_DUTY_CYCLE(0.500000), 124 | .CLKOUT3_PHASE(0.000000), 125 | .CLKOUT3_USE_FINE_PS("FALSE"), 126 | .CLKOUT4_CASCADE("FALSE"), 127 | .CLKOUT4_DIVIDE(1), 128 | .CLKOUT4_DUTY_CYCLE(0.500000), 129 | .CLKOUT4_PHASE(0.000000), 130 | .CLKOUT4_USE_FINE_PS("FALSE"), 131 | .CLKOUT5_DIVIDE(1), 132 | .CLKOUT5_DUTY_CYCLE(0.500000), 133 | .CLKOUT5_PHASE(0.000000), 134 | .CLKOUT5_USE_FINE_PS("FALSE"), 135 | .CLKOUT6_DIVIDE(1), 136 | .CLKOUT6_DUTY_CYCLE(0.500000), 137 | .CLKOUT6_PHASE(0.000000), 138 | .CLKOUT6_USE_FINE_PS("FALSE"), 139 | .COMPENSATION("ZHOLD"), 140 | .DIVCLK_DIVIDE(1), 141 | .IS_CLKINSEL_INVERTED(1'b0), 142 | .IS_PSEN_INVERTED(1'b0), 143 | .IS_PSINCDEC_INVERTED(1'b0), 144 | .IS_PWRDWN_INVERTED(1'b0), 145 | .IS_RST_INVERTED(1'b0), 146 | .REF_JITTER1(0.010000), 147 | .REF_JITTER2(0.010000), 148 | .SS_EN("FALSE"), 149 | .SS_MODE("CENTER_HIGH"), 150 | .SS_MOD_PERIOD(10000), 151 | .STARTUP_WAIT("FALSE")) 152 | mmcm_adv_inst 153 | (.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_1), 154 | .CLKFBOUT(clkfbout_design_1_clk_wiz_0_1), 155 | .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED), 156 | .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED), 157 | .CLKIN1(clk_in1_design_1_clk_wiz_0_1), 158 | .CLKIN2(1'b0), 159 | .CLKINSEL(1'b1), 160 | .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), 161 | .CLKOUT0(clk_out1_design_1_clk_wiz_0_1), 162 | .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), 163 | .CLKOUT1(clk_out2_design_1_clk_wiz_0_1), 164 | .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), 165 | .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), 166 | .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), 167 | .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED), 168 | .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED), 169 | .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED), 170 | .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED), 171 | .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED), 172 | .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 173 | .DCLK(1'b0), 174 | .DEN(1'b0), 175 | .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), 176 | .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]), 177 | .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED), 178 | .DWE(1'b0), 179 | .LOCKED(locked), 180 | .PSCLK(1'b0), 181 | .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED), 182 | .PSEN(1'b0), 183 | .PSINCDEC(1'b0), 184 | .PWRDWN(1'b0), 185 | .RST(reset)); 186 | endmodule 187 | `ifndef GLBL 188 | `define GLBL 189 | `timescale 1 ps / 1 ps 190 | 191 | module glbl (); 192 | 193 | parameter ROC_WIDTH = 100000; 194 | parameter TOC_WIDTH = 0; 195 | 196 | //-------- STARTUP Globals -------------- 197 | wire GSR; 198 | wire GTS; 199 | wire GWE; 200 | wire PRLD; 201 | tri1 p_up_tmp; 202 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 203 | 204 | wire PROGB_GLBL; 205 | wire CCLKO_GLBL; 206 | wire FCSBO_GLBL; 207 | wire [3:0] DO_GLBL; 208 | wire [3:0] DI_GLBL; 209 | 210 | reg GSR_int; 211 | reg GTS_int; 212 | reg PRLD_int; 213 | 214 | //-------- JTAG Globals -------------- 215 | wire JTAG_TDO_GLBL; 216 | wire JTAG_TCK_GLBL; 217 | wire JTAG_TDI_GLBL; 218 | wire JTAG_TMS_GLBL; 219 | wire JTAG_TRST_GLBL; 220 | 221 | reg JTAG_CAPTURE_GLBL; 222 | reg JTAG_RESET_GLBL; 223 | reg JTAG_SHIFT_GLBL; 224 | reg JTAG_UPDATE_GLBL; 225 | reg JTAG_RUNTEST_GLBL; 226 | 227 | reg JTAG_SEL1_GLBL = 0; 228 | reg JTAG_SEL2_GLBL = 0 ; 229 | reg JTAG_SEL3_GLBL = 0; 230 | reg JTAG_SEL4_GLBL = 0; 231 | 232 | reg JTAG_USER_TDO1_GLBL = 1'bz; 233 | reg JTAG_USER_TDO2_GLBL = 1'bz; 234 | reg JTAG_USER_TDO3_GLBL = 1'bz; 235 | reg JTAG_USER_TDO4_GLBL = 1'bz; 236 | 237 | assign (strong1, weak0) GSR = GSR_int; 238 | assign (strong1, weak0) GTS = GTS_int; 239 | assign (weak1, weak0) PRLD = PRLD_int; 240 | 241 | initial begin 242 | GSR_int = 1'b1; 243 | PRLD_int = 1'b1; 244 | #(ROC_WIDTH) 245 | GSR_int = 1'b0; 246 | PRLD_int = 1'b0; 247 | end 248 | 249 | initial begin 250 | GTS_int = 1'b1; 251 | #(TOC_WIDTH) 252 | GTS_int = 1'b0; 253 | end 254 | 255 | endmodule 256 | `endif 257 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | --- 2 | title: "VHDL i2s transmitter" 3 | cover: "/logos/wave.jpg" 4 | category: "Hardware" 5 | tags: 6 | - VHDL 7 | FPGA 8 | DSP 9 | date: 2018-09-14 22:00 10 | --- 11 | 12 | This summer I have been reading a book on VHDL 2008: "Effective Coding with VHDL" from Ricardo Jasinski. Although not for beginners I can recommend this book to anyone with some knowledge of FPGA's and general programming skills. To get some practical experience I obtained two dev kits: 13 | 14 | * A [Zedboard](https://reference.digilentinc.com/_media/zedboard:zedboard_ug.pdf) dev kit containing an Xilinx Zync 15 | * A [Nexys4-DDR](https://reference.digilentinc.com/_media/nexys4-ddr:nexys4ddr_rm.pdf) with Xylinx Artix-7 from Digilent 16 | 17 | Digilent also sells PMOD modules which are extension modules containing specialized IO chips. I bought the [I2S2 DA/AD board](https://reference.digilentinc.com/reference/pmod/pmodi2s2/reference-manual) with I2S interface. It can sample as well as playback audio wave data via a simple I2S protocol. It is based on the [CS4344](https://www.cirrus.com/products/cs4344-45-48/) and CS5343 chips from Cypress. In this article I focus on the CS4344 DA converter. 18 | 19 | Using the I2S board is relatively simple when compared with for example the audio chip embedded on the Zedboard. That chip supports a complex signal path with many registers. Setting one of the registers to a wrong value will quickly result in no audio output. Debugging would to take a lot of effort for a first project. The CS4344 however is very simple. It has an I2S interface and no registers to set. Even its datasheet is short :) I can simulate the VHDL on fore hand before flashing and check the output I2S waveform. If that is correct the audio chip will produce sound. 20 | 21 | The roadmap of my project is as follows: 22 | 1. First produce a square wave with a specific frequency. 23 | 2. Produce a single sine wave with a specific frequency. 24 | 3. Implement I2S AD reception and loopback to the DA output. 25 | 4. Implement an additive synthesis engine based on a bandwidth enhanced sine model. There is an interesting course on [Coursera](https://www.coursera.org/learn/audio-signal-processing/home/welcome) 26 | 5. Control the synthesis parameters from a soft core. 27 | 6. Run Linux (Yocto) on a soft core and control the synthesis engine with a Linux device driver. 28 | 29 | So I have a long way to go. In this article I will focus on step 1. 30 | 31 | # I2S 32 | 33 | How does I2S work? Have a look at the following schematic: 34 | 35 | ![I2S protocol](doc_resources/i2s.png "I2S protocol") 36 | 37 | 38 | Note that the CS4344 datasheet uses LRCK as WS and SDIN as SD. Furthermore it uses an extra clock signal MCLK. In my FPGA design I use the Xilinx Clock wizard to generate MCLK. The other signals are generated by the FPGA i2s_sender component introduced in this article. 39 | 40 | ## parameters 41 | 42 | The CS4344 datasheet shows a few examples of different clock parameters. 43 | 44 | First I defined a package for some constants: 45 | 46 | package types_pkg is 47 | constant MCLK_FREQ : integer := 18432000; in Hz 48 | -- 48Khz sample rate 49 | constant LRCK_FREQ : integer := 48000; -- MCLK/384 50 | --24 bits per LRCK phase (low = left channel, high = right channel_ 51 | constant SCLK_FREQ : integer := LRCK_FREQ*48; 52 | constant SAMPLE_WIDTH : integer := 24; 53 | 54 | subtype sample_t is signed(SAMPLE_WIDTH-1 downto 0); 55 | end; 56 | 57 | ## i2s interface 58 | 59 | The interface of the i2s_sender is as follows: 60 | 61 | entity i2s_sender is 62 | --wave_x_in are sampled at the rising edge of MCLK 63 | Port ( 64 | resetn : in std_logic; 65 | MCLK_in : in std_logic; 66 | LRCK_out : out std_logic; 67 | SCLK_out : out std_logic; 68 | SDIN_out : out std_logic; 69 | wave_left_in : in sample_t; 70 | wave_right_in : in sample_t 71 | ); 72 | end i2s_sender; 73 | 74 | The LRCK, SCLK signal and SDIN signals will be fed to the CS4344 chip. The wave_in samples must be generated by some other FPGA component. 75 | 76 | Next the logic of the i2s_sender. There are two processes. One process generates the required clocks LRCK and SCLK from MCLK. The other process generates SDIN based on SCLK. 77 | 78 | ## Generation of the clocks 79 | 80 | The clocks are generated by dividing (counting the number edges of) MCLK. 81 | 82 | ### Clock dividing 83 | 84 | For each generated clock (LRCK, SCLK) the value at which the counter should toggle a derived clock is calculated. The frequency is multiplied by 2 because there are two transition in one clock period. 85 | 86 | 87 | --Change level every _DIV ticks of MCLK 88 | constant LRCK_DIV : integer := (MCLK_FREQ / (LRCK_FREQ*2)) -1; -- 384/2 -1 = 161 89 | constant SCLK_DIV : integer := (MCLK_FREQ / (SCLK_FREQ*2)) -1; 90 | 91 | --types for various counters 92 | subtype div_LRCK_t is integer range 0 to LRCK_DIV; 93 | subtype div_SCLK_t is integer range 0 to SCLK_DIV; 94 | 95 | --count the number of MCLK ticks before toggling LRCK 96 | signal LRCK_cnt : div_LRCK_t; 97 | --count the number of MCLK ticks before toggling SCLK 98 | signal SCLK_cnt : div_SCLK_t; 99 | 100 | --count the number of SCLK periods after LRCK went low 101 | signal SDIN_cnt : integer range 0 to (SAMPLE_WIDTH*2-1); 102 | 103 | --wave_x_in are sampled at the rising edge of MCLK 104 | signal wave_left : sample_t := (others => '0'); 105 | signal wave_right: sample_t := (others => '0'); 106 | 107 | signal shift_reg: std_logic_vector(SAMPLE_WIDTH-1 downto 0); 108 | 109 | ### Counters 110 | 111 | The counters are relatively simple. The count up to the divider value and then toggle a clock. Furthermore the moment LRCK toggles is also used to set the position of SDIN to either 0 or SAMPLE_WIDTH (24). 112 | 113 | if MCLK_in'event and MCLK_in = '1' then -- Rising clock edge 114 | -- MCLK == 18.4320 Mhz 115 | -- LRCK = MCLK / 384 = 48khz = Fs 116 | -- SCLK = 48 * Fs = MCLK/8 117 | if LRCK_cnt = LRCK_DIV then 118 | LRCK_cnt <=0; 119 | if LRCK_out = '1' then 120 | --falling edge 121 | --assert: SCLK will go low 122 | LRCK_out <= '0'; 123 | SDIN_cnt <= 0; 124 | else 125 | -- rising edge 126 | --assert: SCLK will go low 127 | LRCK_out <= '1'; 128 | SDIN_cnt <= SAMPLE_WIDTH; 129 | end if; 130 | else 131 | if (SCLK_cnt = SCLK_DIV) and (SCLK_out='1') then 132 | --SCLK will go low 133 | SDIN_cnt <= SDIN_cnt + 1; 134 | end if; 135 | LRCK_cnt <= LRCK_cnt + 1; 136 | end if; 137 | 138 | if SCLK_cnt = SCLK_DIV then 139 | SCLK_cnt <=0; 140 | SCLK_out <= not SCLK_out; 141 | else 142 | SCLK_cnt <= SCLK_cnt + 1; 143 | end if; 144 | 145 | ## Generation of the SDIN signal 146 | 147 | The SDIN signal contains the bits of the input wave signal. One bit is shifted out every SCLK clock. The left sample should be shifted out when LRCK is low. The right sample is shifted out when LRCK is high. A first approach was to create a process that acts both on the rising edge of LRCK as well as the falling edge. This doesn't work however as flip flops which are used to implement the design cannot trigger on both clock edges. As a solution I now count the number of SCLK clocks after the falling edge of LRCK. 148 | 149 | * SCLK_cnt = 1..25 outputs the left sample 150 | * SCLK_cnt = 25..48 outputs the right sample 151 | * The last bit of the right channel sample is shifted out at SCLK_cnt=0 152 | * The shifted out bit is sampled by the CS4344 at the rising edge of SCLK 153 | 154 | if SCLK_out'event and SCLK_out = '0' then -- Falling clock edge 155 | if SDIN_cnt=0 then 156 | -- load shift register 157 | shift_reg <= std_logic_vector(wave_left); 158 | elsif SDIN_cnt=24 then 159 | shift_reg <= std_logic_vector(wave_right); 160 | else 161 | shift_reg <= shift_reg(shift_reg'HIGH-1 downto 0) & '0'; 162 | end if; 163 | SDIN_out <= shift_reg(shift_reg'HIGH); 164 | end if; 165 | 166 | ## Top level component 167 | 168 | For testing the top level component connects a square waveform generator to the i2s_sender. The i2s_sender output is connected to the FPGA output pins. If the PMOD modules is plugged into the JA port. The following contraints can be used for the Nexys 4 DDR dev kit. 169 | 170 | set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports MCLK_out] 171 | set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports LRCK_out] 172 | set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports SCLK_out] 173 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports SDIN_out] 174 | 175 | ## Debugging 176 | 177 | During simulation it is helpfull to print out all the calculated values to make sure that they are correct. It is also possible to view them in Vivado simulation objects pane. I added the following to i2s_sender to print out the values. 178 | 179 | debug : process (dummy) is 180 | begin 181 | --print the dividers when in simulation mode 182 | report "MCLK_FREQ hz " & integer'image(MCLK_FREQ); 183 | report "LRCK_FREQ hz " & integer'image(LRCK_FREQ); 184 | report "SCLK_FREQ hz " & integer'image(SCLK_FREQ); 185 | report "SAMPLE_WIDTH " & integer'image(SAMPLE_WIDTH); 186 | 187 | report "LRCK_DIV" & integer'image(LRCK_DIV); 188 | report "SCLK_DIV" & integer'image(SCLK_DIV); 189 | end process; 190 | 191 | During development at some point the simulation signal output seemed correct. However after synthesis no audio was output. A first debug approach was to count the number of eg. SCLK edges and connect that counter to the LEDs of the development kit. By setting the width of the counter correctly and displaying the most significant bits of the counter I was able to check if for example LRCK was indeed toggling at 48 kHz. 192 | 193 | Another approach is to add an ILA debug core to your design and connect the output pins of the designed component to the debug core. This way you can see if the synthesized design on the FPGA behaves as expected. 194 | 195 | In order to test the component I created a simple square waveform generator that generates a left channel signal at 440 Hz and a right channel signal at 880 Hz. This generator was hooked up to the i2s_sender. 196 | 197 | resetn <= '0', '1' after 100ns; 198 | clock <= not clock after 10 ns; 199 | MCLK <= not MCLK after 54.253472222222 ns; -- 18.4320 Mhz 200 | 201 | sqwv : entity work.square_wave 202 | port map ( 203 | resetn => resetn, 204 | MCLK_in => MCLK, 205 | wave_left_out => wave_left, 206 | wave_right_out => wave_right 207 | ); 208 | 209 | i2s : entity work.i2s_sender 210 | port map ( 211 | MCLK_in => MCLK, 212 | resetn => resetn, 213 | LRCK_out => LRCK, 214 | SCLK_out => SCLK, 215 | SDIN_out => SDIN, 216 | wave_left_in => wave_left, 217 | wave_right_in => wave_right 218 | ); 219 | 220 | Below outputs of the I2S waveform at the start of a new LRCK cycle (left channel) 221 | 222 | ![LRCK left channel](doc_resources/lrck1.png "LRCK left channel") 223 | 224 | Below outputs of the I2S waveform at the start of the rising edge of LRCK (right channel). 225 | 226 | ![LRCK right channel](doc_resources/lrck2.png "LRCK right channel") 227 | 228 | 229 | # Conclusion 230 | 231 | Some things I noticed while experimenting with VHDL 2008 and Xilinx Vivado: 232 | * Lack of support of some VHDL 2008 features in Vivado. 233 | * Vivado spews out a large number of warnings. It's not easy to see which warnings are important and which are not. 234 | * Eventhough simulation is running fine the synthesized result can still be wrong. 235 | * The Cypress CS4344 datasheet's I2S waveform specification is not very clear. It does not show that the last bit of the previous sample is clocked in at the first rising SCLK after LRCK phase change. 236 | 237 | The files are available on my github page. Version Control with Vivado is not trivial. I used [this approach](https://github.com/barbedo/vivado-git) to handle version control. 238 | 239 | 240 | 241 | 242 | -------------------------------------------------------------------------------- /src/blockdesign/design_1.bd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | xilinx.com 6 | BlockDiagram 7 | design_1 8 | 1.00.a 9 | 10 | 11 | isTop 12 | true 13 | 14 | 15 | 16 | 17 | CLK.SYS_CLOCK 18 | Clk 19 | Clock 20 | 21 | 22 | 23 | 24 | 25 | 26 | CLK 27 | 28 | 29 | sys_clock 30 | 31 | 32 | 33 | 34 | 35 | FREQ_HZ 36 | 100000000 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | PHASE 45 | 0.000 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | CLK_DOMAIN 54 | design_1_sys_clock 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | RST.RESET 65 | Reset 66 | Reset 67 | 68 | 69 | 70 | 71 | 72 | 73 | RST 74 | 75 | 76 | reset 77 | 78 | 79 | 80 | 81 | 82 | POLARITY 83 | ACTIVE_HIGH 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | CLK.CLK_OUT 94 | Clk 95 | Clock 96 | 97 | 98 | 99 | 100 | 101 | 102 | CLK 103 | 104 | 105 | clk_out 106 | 107 | 108 | 109 | 110 | 111 | FREQ_HZ 112 | 100000000 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | PHASE 121 | 0.0 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | CLK_DOMAIN 130 | /clk_wiz_0_clk_out1 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | CLK.MCLK_GEN_OUT 141 | Clk 142 | Clock 143 | 144 | 145 | 146 | 147 | 148 | 149 | CLK 150 | 151 | 152 | MCLK_gen_out 153 | 154 | 155 | 156 | 157 | 158 | FREQ_HZ 159 | 18432203 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | PHASE 168 | 0.0 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | CLK_DOMAIN 177 | /clk_wiz_0_clk_out1 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | BlockDiagram 191 | :vivado.xilinx.com: 192 | 193 | 194 | 195 | 196 | 197 | sys_clock 198 | 199 | in 200 | 201 | 202 | 203 | reset 204 | 205 | in 206 | 207 | 208 | 209 | locked_reset 210 | 211 | out 212 | 213 | 214 | 215 | clk_out 216 | 217 | out 218 | 219 | 220 | 221 | MCLK_gen_out 222 | 223 | out 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | xilinx.com 232 | BlockDiagram 233 | design_1_imp 234 | 1.00.a 235 | 236 | 237 | clk_wiz_0 238 | 239 | 240 | design_1_clk_wiz_0_0 241 | true 242 | 2 243 | 18.4320 244 | 1 245 | 10.875 246 | 10.875 247 | 59 248 | 122.755 249 | 92.529 250 | 175.761 251 | 92.529 252 | 253 | 254 | 255 | 256 | 257 | sys_clock_1 258 | 259 | 260 | 261 | 262 | reset_1 263 | 264 | 265 | 266 | 267 | clk_wiz_0_locked 268 | 269 | 270 | 271 | 272 | clk_wiz_0_clk_out1 273 | 274 | 275 | 276 | 277 | clk_wiz_0_MCLK 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | -------------------------------------------------------------------------------- /src/design/sine_generator_types.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: D.W.J. Bosman 3 | -- 4 | -- Create Date: 09/06/2018 11:49:12 PM 5 | -- Module Name: sine types package 6 | -- 7 | -- Additional Comments: 8 | -- This library contains constants and functions to calculate the phase step when 9 | -- generating a sine wave given a target frequency 10 | -- At design time frequency resolution and sample rate should be set 11 | ---------------------------------------------------------------------------------- 12 | 13 | 14 | library IEEE; 15 | use IEEE.STD_LOGIC_1164.ALL; 16 | use IEEE.NUMERIC_STD.ALL; 17 | use ieee.math_real.all; 18 | 19 | package sine_generator_func_pkg is 20 | -- this function allows settings constants to certain values given a condition 21 | function sel(Cond: BOOLEAN; If_True, If_False: natural) return natural; 22 | function sel(Cond: BOOLEAN; If_True, If_False: real) return real; 23 | end; 24 | 25 | package body sine_generator_func_pkg is 26 | 27 | function sel(Cond: BOOLEAN; If_True, If_False: natural) return natural is 28 | begin 29 | if (Cond = TRUE) then 30 | return(If_True); 31 | else 32 | return(If_False); 33 | end if; 34 | end function sel; 35 | 36 | function sel(Cond: BOOLEAN; If_True, If_False: real) return real is 37 | begin 38 | if (Cond = TRUE) then 39 | return(If_True); 40 | else 41 | return(If_False); 42 | end if; 43 | end function sel; 44 | end; 45 | 46 | library IEEE; 47 | use IEEE.STD_LOGIC_1164.ALL; 48 | use IEEE.NUMERIC_STD.ALL; 49 | 50 | use ieee.math_real.all; 51 | use work.i2s_types_pkg.all; 52 | use work.sine_generator_func_pkg.all; 53 | use STD.textio.all; 54 | 55 | package sine_generator_types_pkg is 56 | --parameters in this package are explained in my blog: 57 | --also a google sheets version can be found here: 58 | 59 | --these are the input parameters: 60 | constant TARGET_FREQUENCY_RESOLUTION : real := 0.05; -- Hz 61 | constant SAMPLE_RATE: natural := 48000; --Hz 62 | 63 | constant SAMPLE_RATE_BITS: natural := natural(ceil(log(real(SAMPLE_RATE))/log(2.0))); 64 | constant MAX_FREQUENCY : natural := SAMPLE_RATE/2; 65 | 66 | constant PHASE_SPACE_SIZE: natural := natural(real(SAMPLE_RATE)/TARGET_FREQUENCY_RESOLUTION); 67 | 68 | constant POWER2_PHASE_SPACE_BITS: natural := natural(ceil(log(real(PHASE_SPACE_SIZE))/log(2.0))); 69 | constant POWER2_PHASE_SPACE_SIZE: natural := 2 ** POWER2_PHASE_SPACE_BITS; 70 | 71 | -- at 0.5 FS POWER2_PHASE_SPACE_BITS-1 is the maximum step 72 | constant MAX_POWER2_PHASE_STEP_BITS : natural := POWER2_PHASE_SPACE_BITS-1; 73 | 74 | subtype phase_t is unsigned(POWER2_PHASE_SPACE_BITS-1 downto 0); 75 | subtype phase_step_decimal_t is unsigned(MAX_POWER2_PHASE_STEP_BITS-1 downto 0); 76 | subtype phase_step_fraction_t is unsigned(SAMPLE_RATE_BITS-1 downto 0); 77 | subtype phase_fraction_t is unsigned(SAMPLE_RATE_BITS+1 downto 0); 78 | 79 | type phase_step_t is record 80 | decimal : phase_step_decimal_t; 81 | fraction : phase_step_fraction_t; -- the fraction is not a decimal fraction, it is divided by sample_rate 82 | end record; 83 | 84 | type phase_state_t is record 85 | step : phase_step_t; 86 | -- the decimal part, added each step 87 | current: phase_t; 88 | -- the fractional part, if it overflows (above sample_rate) 89 | -- then the it is reset and 'current' is increased by one 90 | current_fraction: phase_fraction_t; 91 | 92 | end record; 93 | 94 | --constant to set step and state to zero 95 | constant ZERO_PHASE_STEP: phase_step_t := (decimal => (others => '0'), fraction => (others => '0')); 96 | constant ZERO_PHASE_STATE: phase_state_t := 97 | ( 98 | current => (others => '0'), 99 | current_fraction => (others => '0'), 100 | step => ( 101 | decimal => (others => '0'), 102 | fraction => (others => '0') 103 | ) 104 | ); 105 | 106 | 107 | constant PHASE_STEP_FRACTION_DIVIDER : phase_step_fraction_t := to_unsigned(SAMPLE_RATE, phase_step_fraction_t'length); 108 | 109 | constant QUANTIZED_FREQUENCY_RESOLUTION : real := real(SAMPLE_RATE) / real(POWER2_PHASE_SPACE_SIZE); 110 | constant PHASE_STEP : real := 1.0 / QUANTIZED_FREQUENCY_RESOLUTION; 111 | constant PHASE_STEP_BITS : real := log2(PHASE_STEP); 112 | 113 | constant POWER2_PHASE_STEP_BITS1: natural := natural(floor(log(PHASE_STEP)/log(2.0))); 114 | constant FREQ_RES1 : real := 1.0 / real(POWER2_PHASE_STEP_BITS1); 115 | constant POWER2_PHASE_STEP_BITS2: natural := natural(ceil(log(PHASE_STEP)/log(2.0))); 116 | constant FREQ_RES2 : real := 1.0 / real(POWER2_PHASE_STEP_BITS2); 117 | constant POWER2_PHASE_STEP_BITS1_USABLE: boolean := FREQ_RES1 < TARGET_FREQUENCY_RESOLUTION; 118 | constant POWER2_PHASE_STEP_BITS : natural := sel(POWER2_PHASE_STEP_BITS1_USABLE, POWER2_PHASE_STEP_BITS1, POWER2_PHASE_STEP_BITS2); 119 | constant POWER2_PHASE_STEP : natural := 2 ** POWER2_PHASE_STEP_BITS; 120 | 121 | -- max frequency = POWER2_PHASE_SPACE_SIZE/2 122 | constant FREQUENCY_SCALED_BITS : natural := SAMPLE_RATE_BITS -1 + POWER2_PHASE_STEP_BITS; 123 | subtype frequency_t is unsigned(FREQUENCY_SCALED_BITS-1 downto 0); 124 | 125 | constant MAX_FREQUENCY_SCALED : natural := MAX_FREQUENCY * POWER2_PHASE_STEP; 126 | 127 | constant MAX_QUANTISED_PHASE_STEP_ERROR : real := 1.0/real(MAX_FREQUENCY); 128 | constant MAX_QUANTISED_PHASE_STEP_ERROR_BITS : real := abs(log2(MAX_QUANTISED_PHASE_STEP_ERROR)); 129 | 130 | constant SCALED_PHASE_STEP_BITS : natural := natural(ceil( PHASE_STEP_BITS + MAX_QUANTISED_PHASE_STEP_ERROR_BITS)); 131 | 132 | constant PHASE_STEP_SCALING_FACTOR_BITS1 : natural := natural(floor ( MAX_QUANTISED_PHASE_STEP_ERROR_BITS )); 133 | constant PHASE_STEP_SCALING_FACTOR1: natural := 2 ** ( PHASE_STEP_SCALING_FACTOR_BITS1 ); 134 | constant SCALED_PHASE_STEP1 : natural := natural( floor( real(PHASE_STEP_SCALING_FACTOR1) * PHASE_STEP)); 135 | constant PHASE_STEP_ERROR1: real := PHASE_STEP - real(SCALED_PHASE_STEP1) / real(PHASE_STEP_SCALING_FACTOR1); 136 | constant PHASE_STEP_MAX_ERROR1: real := real(MAX_FREQUENCY) * real(PHASE_STEP_ERROR1); 137 | 138 | constant PHASE_STEP_SCALING_FACTOR_BITS2 : natural := natural(ceil ( MAX_QUANTISED_PHASE_STEP_ERROR_BITS )); 139 | constant PHASE_STEP_SCALING_FACTOR2: natural := 2 ** ( PHASE_STEP_SCALING_FACTOR_BITS2 ); 140 | constant SCALED_PHASE_STEP2 : natural := natural( floor( real(PHASE_STEP_SCALING_FACTOR2) * PHASE_STEP)); 141 | constant PHASE_STEP_ERROR2: real := PHASE_STEP - real(SCALED_PHASE_STEP2) / real(PHASE_STEP_SCALING_FACTOR2); 142 | constant PHASE_STEP_MAX_ERROR2: real := real(MAX_FREQUENCY) * real(PHASE_STEP_ERROR2); 143 | 144 | constant PHASE_STEP_SCALING_FACTOR_BITS1_USABLE: boolean := PHASE_STEP_MAX_ERROR1<1.0; 145 | constant PHASE_STEP_SCALING_FACTOR_BITS : natural := sel(PHASE_STEP_SCALING_FACTOR_BITS1_USABLE, PHASE_STEP_SCALING_FACTOR_BITS1, PHASE_STEP_SCALING_FACTOR_BITS2); 146 | constant PHASE_STEP_SCALING_FACTOR: natural := 2 ** ( PHASE_STEP_SCALING_FACTOR_BITS ); 147 | constant SCALED_PHASE_STEP : natural := natural( floor( real(PHASE_STEP_SCALING_FACTOR) * PHASE_STEP)); 148 | 149 | constant DECIMAL_DIVIDER_BITS : natural := POWER2_PHASE_STEP_BITS + PHASE_STEP_SCALING_FACTOR_BITS; 150 | 151 | 152 | -- synthesis translate_off 153 | procedure Report_Constants(constant dummy: in integer); 154 | -- synthesis translate_on 155 | 156 | 157 | --given a target frequency scaled by POWER2_PHASE_STEP the function calculates 158 | -- the required phase step at each sample 159 | procedure Calculate_Phase_Step( 160 | constant frequency_scaled: in frequency_t; 161 | variable phase_step: out phase_step_t 162 | ); 163 | 164 | --return a random value 165 | procedure Rand(variable rand_inout: inout unsigned(30 downto 0)); 166 | 167 | --update phase according to the phase.step field. 168 | procedure Advance_Phase( 169 | variable phase: inout phase_state_t); 170 | 171 | end; 172 | 173 | package body sine_generator_types_pkg is 174 | 175 | 176 | -- synthesis translate_off 177 | -- print all constants 178 | procedure Report_Constants ( constant dummy: in integer) is 179 | variable l: line; 180 | begin 181 | 182 | write( l, string'("TARGET_FREQUENCY_RESOLUTION = " )); 183 | write( l, TARGET_FREQUENCY_RESOLUTION); 184 | writeline( output, l ); 185 | 186 | write( l, string'("SAMPLE_RATE = " )); 187 | write( l, SAMPLE_RATE); 188 | writeline( output, l ); 189 | 190 | write( l, string'("MAX_FREQUENCY = " )); 191 | write( l, MAX_FREQUENCY); 192 | writeline( output, l ); 193 | 194 | write( l, string'("PHASE_SPACE_SIZE = " )); 195 | write( l, PHASE_SPACE_SIZE); 196 | writeline( output, l ); 197 | 198 | write( l, string'("POWER2_PHASE_SPACE_BITS = " )); 199 | write( l, POWER2_PHASE_SPACE_BITS); 200 | writeline( output, l ); 201 | 202 | write( l, string'("MAX_POWER2_PHASE_STEP_BITS = " )); 203 | write( l, MAX_POWER2_PHASE_STEP_BITS); 204 | writeline( output, l ); 205 | 206 | write( l, string'("POWER2_PHASE_SPACE_SIZE = " )); 207 | write( l, POWER2_PHASE_SPACE_SIZE); 208 | writeline( output, l ); 209 | 210 | write( l, string'("QUANTIZED_FREQUENCY_RESOLUTION = " )); 211 | write( l, QUANTIZED_FREQUENCY_RESOLUTION); 212 | writeline( output, l ); 213 | 214 | write( l, string'("PHASE_STEP = " )); 215 | write( l, PHASE_STEP); 216 | writeline( output, l ); 217 | 218 | write( l, string'("PHASE_STEP_BITS = " )); 219 | write( l, PHASE_STEP_BITS); 220 | writeline( output, l ); 221 | 222 | write( l, string'("POWER2_PHASE_STEP_BITS1 = " )); 223 | write( l, POWER2_PHASE_STEP_BITS1); 224 | writeline( output, l ); 225 | 226 | write( l, string'("FREQ_RES1 = " )); 227 | write( l, FREQ_RES1); 228 | writeline( output, l ); 229 | 230 | write( l, string'("POWER2_PHASE_STEP_BITS2 = " )); 231 | write( l, POWER2_PHASE_STEP_BITS2); 232 | writeline( output, l ); 233 | 234 | write( l, string'("FREQ_RES2 = " )); 235 | write( l, FREQ_RES2); 236 | writeline( output, l ); 237 | 238 | write( l, string'("POWER2_PHASE_STEP_BITS1_USABLE = " )); 239 | write( l, POWER2_PHASE_STEP_BITS1_USABLE); 240 | writeline( output, l ); 241 | 242 | write( l, string'("POWER2_PHASE_STEP_BITS = " )); 243 | write( l, POWER2_PHASE_STEP_BITS); 244 | writeline( output, l ); 245 | 246 | write( l, string'("POWER2_PHASE_STEP = " )); 247 | write( l, POWER2_PHASE_STEP); 248 | writeline( output, l ); 249 | 250 | write( l, string'("FREQUENCY_SCALED_BITS = " )); 251 | write( l, FREQUENCY_SCALED_BITS); 252 | writeline( output, l ); 253 | 254 | write( l, string'("MAX_QUANTISED_PHASE_STEP_ERROR = " )); 255 | write( l, MAX_QUANTISED_PHASE_STEP_ERROR); 256 | writeline( output, l ); 257 | 258 | write( l, string'("MAX_QUANTISED_PHASE_STEP_ERROR_BITS= " )); 259 | write( l, MAX_QUANTISED_PHASE_STEP_ERROR_BITS); 260 | writeline( output, l ); 261 | 262 | write( l, string'("SCALED_PHASE_STEP_BITS = " )); 263 | write( l, SCALED_PHASE_STEP_BITS); 264 | writeline( output, l ); 265 | 266 | write( l, string'("PHASE_STEP_SCALING_FACTOR_BITS1 = " )); 267 | write( l, PHASE_STEP_SCALING_FACTOR_BITS1); 268 | writeline( output, l ); 269 | 270 | write( l, string'("PHASE_STEP_SCALING_FACTOR1 = " )); 271 | write( l, PHASE_STEP_SCALING_FACTOR1); 272 | writeline( output, l ); 273 | 274 | write( l, string'("SCALED_PHASE_STEP1 = " )); 275 | write( l, SCALED_PHASE_STEP1); 276 | writeline( output, l ); 277 | 278 | write( l, string'("PHASE_STEP_ERROR1 = " )); 279 | write( l, PHASE_STEP_ERROR1); 280 | writeline( output, l ); 281 | 282 | write( l, string'("PHASE_STEP_MAX_ERROR1 = " )); 283 | write( l, PHASE_STEP_MAX_ERROR1); 284 | writeline( output, l ); 285 | 286 | write( l, string'("PHASE_STEP_SCALING_FACTOR_BITS2 = " )); 287 | write( l, PHASE_STEP_SCALING_FACTOR_BITS2); 288 | writeline( output, l ); 289 | 290 | write( l, string'("PHASE_STEP_SCALING_FACTOR2 = " )); 291 | write( l, PHASE_STEP_SCALING_FACTOR2); 292 | writeline( output, l ); 293 | 294 | write( l, string'("SCALED_PHASE_STEP2 = " )); 295 | write( l, SCALED_PHASE_STEP2); 296 | writeline( output, l ); 297 | 298 | write( l, string'("PHASE_STEP_ERROR2 = " )); 299 | write( l, PHASE_STEP_ERROR2); 300 | writeline( output, l ); 301 | 302 | write( l, string'("PHASE_STEP_MAX_ERROR2 = " )); 303 | write( l, PHASE_STEP_MAX_ERROR2); 304 | writeline( output, l ); 305 | 306 | write( l, string'("PHASE_STEP_SCALING_FACTOR_BITS1_USABLE= " )); 307 | write( l, PHASE_STEP_SCALING_FACTOR_BITS1_USABLE); 308 | writeline( output, l ); 309 | 310 | write( l, string'("PHASE_STEP_SCALING_FACTOR_BITS = " )); 311 | write( l, PHASE_STEP_SCALING_FACTOR_BITS); 312 | writeline( output, l ); 313 | 314 | write( l, string'("PHASE_STEP_SCALING_FACTOR = " )); 315 | write( l, PHASE_STEP_SCALING_FACTOR); 316 | writeline( output, l ); 317 | 318 | write( l, string'("SCALED_PHASE_STEP = " )); 319 | write( l, SCALED_PHASE_STEP); 320 | writeline( output, l ); 321 | 322 | write( l, string'("DECIMAL_DIVIDER_BITS = " )); 323 | write( l, DECIMAL_DIVIDER_BITS); 324 | writeline( output, l ); 325 | 326 | 327 | end Report_Constants ; 328 | -- synthesis translate_on 329 | 330 | procedure Rand(variable rand_inout: inout unsigned(30 downto 0)) is 331 | begin 332 | rand_inout := resize((rand_inout * 16807) mod 2147483647,31); 333 | end; 334 | 335 | procedure Calculate_Phase_Step( 336 | constant frequency_scaled: in frequency_t; 337 | variable phase_step: out phase_step_t) is 338 | 339 | variable scaled_phase: unsigned(SCALED_PHASE_STEP_BITS + FREQUENCY_SCALED_BITS -1 downto 0); 340 | 341 | variable phase_step_numerator_incl_decimal: unsigned(FREQUENCY_SCALED_BITS + POWER2_PHASE_SPACE_BITS - POWER2_PHASE_STEP_BITS -1 downto 0); 342 | variable decimal_scaled: unsigned(FREQUENCY_SCALED_BITS + POWER2_PHASE_SPACE_BITS - POWER2_PHASE_STEP_BITS -1 downto 0); 343 | 344 | variable l: line; 345 | begin 346 | 347 | write( l, string'("sc1_bits = " )); 348 | write( l, scaled_phase'length); 349 | writeline( output, l ); 350 | 351 | write( l, string'("decimal_bits = " )); 352 | write( l, phase_step.decimal'length); 353 | writeline( output, l ); 354 | 355 | write( l, string'("phase_step_numerator_incl_decimal_bits = " )); 356 | write( l, phase_step_numerator_incl_decimal'length); 357 | writeline( output, l ); 358 | 359 | write( l, string'("decimal_scaled_bits = " )); 360 | write( l, decimal_scaled'length); 361 | writeline( output, l ); 362 | 363 | write( l, string'("fractional_bits = " )); 364 | write( l, phase_step.fraction'length); 365 | writeline( output, l ); 366 | 367 | write( l, string'("frequency_scaled = " )); 368 | write( l, to_hstring(frequency_scaled)); 369 | writeline( output, l ); 370 | 371 | scaled_phase := resize(frequency_scaled * SCALED_PHASE_STEP, scaled_phase'length); 372 | 373 | write( l, string'("sc1 = " )); 374 | write( l, to_hstring(scaled_phase)); 375 | writeline( output, l ); 376 | 377 | phase_step.decimal := scaled_phase(DECIMAL_DIVIDER_BITS + phase_step.decimal'length -1 downto DECIMAL_DIVIDER_BITS); 378 | write( l, string'("decimal = " )); 379 | write( l, to_hstring(phase_step.decimal)); 380 | writeline( output, l ); 381 | 382 | phase_step_numerator_incl_decimal := frequency_scaled & to_unsigned(0, POWER2_PHASE_SPACE_BITS - POWER2_PHASE_STEP_BITS); 383 | 384 | write( l, string'("phase_step_numerator_incl_decimal = " )); 385 | write( l, to_hstring(phase_step_numerator_incl_decimal)); 386 | writeline( output, l ); 387 | 388 | decimal_scaled := resize(phase_step.decimal * SAMPLE_RATE, decimal_scaled'length); 389 | write( l, string'("decimal_truncated = " )); 390 | write( l, to_hstring(decimal_scaled)); 391 | writeline( output, l ); 392 | 393 | phase_step.fraction := resize( 394 | phase_step_numerator_incl_decimal(phase_step.fraction'length -1 downto 0) - decimal_scaled(phase_step.fraction'length -1 downto 0), 395 | phase_step.fraction'length); 396 | write( l, string'("fractional = " )); 397 | write( l, to_hstring(phase_step.fraction)); 398 | writeline( output, l ); 399 | 400 | if (phase_step.fraction >= PHASE_STEP_FRACTION_DIVIDER) then 401 | phase_step.fraction := phase_step.fraction - PHASE_STEP_FRACTION_DIVIDER; 402 | phase_step.decimal := phase_step.decimal + to_unsigned(1,phase_step.decimal'length); 403 | 404 | write( l, string'("wrap" )); 405 | writeline( output, l ); 406 | write( l, string'("decimal = " )); 407 | write( l, to_hstring(phase_step.decimal)); 408 | writeline( output, l ); 409 | write( l, string'("fractional = " )); 410 | write( l, to_hstring(phase_step.fraction)); 411 | writeline( output, l ); 412 | 413 | end if; 414 | 415 | end Calculate_Phase_Step; 416 | 417 | procedure Advance_Phase( 418 | variable phase: inout phase_state_t) is 419 | begin 420 | phase.current_fraction := phase.current_fraction + phase.step.fraction; 421 | if phase.current_fraction >= SAMPLE_RATE then 422 | phase.current_fraction := phase.current_fraction - to_unsigned(SAMPLE_RATE, SAMPLE_RATE_BITS); 423 | phase.current := phase.current + phase.step.decimal + 1; 424 | else 425 | phase.current := phase.current + phase.step.decimal; 426 | end if; 427 | end Advance_Phase; 428 | 429 | end; 430 | -------------------------------------------------------------------------------- /src/design/Nexys-4-DDR-Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Nexys4 DDR Rev. C 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK100MHZ] 8 | create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK100MHZ] 9 | 10 | 11 | ##Switches 12 | 13 | set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {SW[0]}] 14 | set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {SW[1]}] 15 | set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {SW[2]}] 16 | set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {SW[3]}] 17 | set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {SW[4]}] 18 | set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {SW[5]}] 19 | set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {SW[6]}] 20 | set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {SW[7]}] 21 | set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS18} [get_ports {SW[8]}] 22 | set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports {SW[9]}] 23 | set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {SW[10]}] 24 | set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {SW[11]}] 25 | set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {SW[12]}] 26 | set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {SW[13]}] 27 | set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {SW[14]}] 28 | set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {SW[15]}] 29 | 30 | 31 | ## LEDs 32 | 33 | set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {LED[0]}] 34 | set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {LED[1]}] 35 | set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {LED[2]}] 36 | set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {LED[3]}] 37 | set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {LED[4]}] 38 | set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {LED[5]}] 39 | set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {LED[6]}] 40 | set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {LED[7]}] 41 | set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {LED[8]}] 42 | set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {LED[9]}] 43 | set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {LED[10]}] 44 | set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {LED[11]}] 45 | set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {LED[12]}] 46 | set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {LED[13]}] 47 | set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {LED[14]}] 48 | set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {LED[15]}] 49 | 50 | #set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {RGB_LED_PWM_ENCODED[2]}] 51 | #set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {RGB_LED_PWM_ENCODED[1]}] 52 | #set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {RGB_LED_PWM_ENCODED[0]}] 53 | #set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b 54 | #set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g 55 | #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r 56 | 57 | 58 | ##7 segment display 59 | 60 | 61 | #set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca 62 | #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb 63 | #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc 64 | #set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd 65 | #set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce 66 | #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf 67 | #set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg 68 | #set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp 69 | 70 | set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[0]}] 71 | set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[1]}] 72 | set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[2]}] 73 | set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[3]}] 74 | set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[4]}] 75 | set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[5]}] 76 | set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[6]}] 77 | set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {SSEG_CA[7]}] 78 | 79 | set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {AN[0]}] 80 | set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {AN[1]}] 81 | set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {AN[2]}] 82 | set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {AN[3]}] 83 | set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {AN[4]}] 84 | set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {AN[5]}] 85 | set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {AN[6]}] 86 | set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {AN[7]}] 87 | 88 | 89 | ##Buttons 90 | 91 | set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports CPU_RESETN] 92 | 93 | #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc 94 | #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu 95 | #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl 96 | #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr 97 | #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd 98 | 99 | 100 | ##Pmod Headers 101 | 102 | 103 | ##Pmod Header JA 104 | 105 | 106 | set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports MCLK_out] 107 | set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports LRCK_out] 108 | set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports SCLK_out] 109 | set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports SDIN_out] 110 | #set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] 111 | #set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] 112 | #set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] 113 | #set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] 114 | 115 | 116 | ##Pmod Header JB 117 | 118 | #set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] 119 | #set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] 120 | #set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] 121 | #set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] 122 | #set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] 123 | #set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] 124 | #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] 125 | #set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] 126 | 127 | 128 | ##Pmod Header JC 129 | 130 | #set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] 131 | #set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] 132 | #set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] 133 | #set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] 134 | #set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7] 135 | #set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8] 136 | #set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] 137 | #set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] 138 | 139 | 140 | ##Pmod Header JD 141 | 142 | #set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] 143 | #set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] 144 | #set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] 145 | #set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] 146 | #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] 147 | #set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] 148 | #set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] 149 | #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] 150 | 151 | 152 | ##Pmod Header JXADC 153 | 154 | #set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] 155 | #set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] 156 | #set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] 157 | #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] 158 | #set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] 159 | #set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] 160 | #set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] 161 | #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] 162 | 163 | 164 | ##VGA Connector 165 | 166 | #set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] 167 | #set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] 168 | #set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] 169 | #set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] 170 | 171 | #set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] 172 | #set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] 173 | #set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] 174 | #set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] 175 | 176 | #set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] 177 | #set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] 178 | #set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] 179 | #set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] 180 | 181 | #set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs 182 | #set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs 183 | 184 | 185 | ##Micro SD Connector 186 | 187 | #set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset 188 | #set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd 189 | #set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck 190 | #set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd 191 | #set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] 192 | #set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] 193 | #set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] 194 | #set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] 195 | 196 | 197 | ##Accelerometer 198 | 199 | #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso 200 | #set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi 201 | #set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk 202 | #set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn 203 | #set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] 204 | #set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] 205 | 206 | 207 | ##Temperature Sensor 208 | 209 | #set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl 210 | #set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda 211 | #set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int 212 | #set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct 213 | 214 | ##Omnidirectional Microphone 215 | 216 | #set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk 217 | #set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data 218 | #set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel 219 | 220 | 221 | ##PWM Audio Amplifier 222 | 223 | #set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm 224 | #set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd 225 | 226 | 227 | ##USB-RS232 Interface 228 | 229 | #set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in 230 | #set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out 231 | #set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts 232 | #set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts 233 | 234 | ##USB HID (PS/2) 235 | 236 | #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk 237 | #set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data 238 | 239 | 240 | ##SMSC Ethernet PHY 241 | 242 | #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc 243 | #set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio 244 | #set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn 245 | #set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv 246 | #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr 247 | #set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] 248 | #set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] 249 | #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen 250 | #set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] 251 | #set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] 252 | #set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk 253 | #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn 254 | 255 | 256 | ##Quad SPI Flash 257 | 258 | #set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 259 | #set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 260 | #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 261 | #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 262 | #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn 263 | 264 | set_property CFGBVS VCCO [current_design] 265 | set_property CONFIG_VOLTAGE 3.3 [current_design] 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | connect_debug_port u_ila_0/probe2 [get_nets [list {i2s/SDIN_cnt[0]} {i2s/SDIN_cnt[1]} {i2s/SDIN_cnt[2]} {i2s/SDIN_cnt[3]} {i2s/SDIN_cnt[4]} {i2s/SDIN_cnt[5]}]] 283 | 284 | create_debug_core u_ila_0 ila 285 | set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] 286 | set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] 287 | set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] 288 | set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] 289 | set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] 290 | set_property C_INPUT_PIPE_STAGES 2 [get_debug_cores u_ila_0] 291 | set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] 292 | set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] 293 | set_property port_width 1 [get_debug_ports u_ila_0/clk] 294 | connect_debug_port u_ila_0/clk [get_nets [list design_1_i/clk_wiz_0/inst/clk_out2]] 295 | set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe0] 296 | set_property port_width 24 [get_debug_ports u_ila_0/probe0] 297 | connect_debug_port u_ila_0/probe0 [get_nets [list {i2s/shift_reg[0]} {i2s/shift_reg[1]} {i2s/shift_reg[2]} {i2s/shift_reg[3]} {i2s/shift_reg[4]} {i2s/shift_reg[5]} {i2s/shift_reg[6]} {i2s/shift_reg[7]} {i2s/shift_reg[8]} {i2s/shift_reg[9]} {i2s/shift_reg[10]} {i2s/shift_reg[11]} {i2s/shift_reg[12]} {i2s/shift_reg[13]} {i2s/shift_reg[14]} {i2s/shift_reg[15]} {i2s/shift_reg[16]} {i2s/shift_reg[17]} {i2s/shift_reg[18]} {i2s/shift_reg[19]} {i2s/shift_reg[20]} {i2s/shift_reg[21]} {i2s/shift_reg[22]} {i2s/shift_reg[23]}]] 298 | create_debug_port u_ila_0 probe 299 | set_property PROBE_TYPE DATA [get_debug_ports u_ila_0/probe1] 300 | set_property port_width 24 [get_debug_ports u_ila_0/probe1] 301 | connect_debug_port u_ila_0/probe1 [get_nets [list {wave_left[0]} {wave_left[1]} {wave_left[2]} {wave_left[3]} {wave_left[4]} {wave_left[5]} {wave_left[6]} {wave_left[7]} {wave_left[8]} {wave_left[9]} {wave_left[10]} {wave_left[11]} {wave_left[12]} {wave_left[13]} {wave_left[14]} {wave_left[15]} {wave_left[16]} {wave_left[17]} {wave_left[18]} {wave_left[19]} {wave_left[20]} {wave_left[21]} {wave_left[22]} {wave_left[23]}]] 302 | create_debug_port u_ila_0 probe 303 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] 304 | set_property port_width 1 [get_debug_ports u_ila_0/probe2] 305 | connect_debug_port u_ila_0/probe2 [get_nets [list LRCK_out_OBUF]] 306 | create_debug_port u_ila_0 probe 307 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] 308 | set_property port_width 1 [get_debug_ports u_ila_0/probe3] 309 | connect_debug_port u_ila_0/probe3 [get_nets [list MCLK_out_OBUF]] 310 | create_debug_port u_ila_0 probe 311 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] 312 | set_property port_width 1 [get_debug_ports u_ila_0/probe4] 313 | connect_debug_port u_ila_0/probe4 [get_nets [list SCLK_out_OBUF]] 314 | create_debug_port u_ila_0 probe 315 | set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] 316 | set_property port_width 1 [get_debug_ports u_ila_0/probe5] 317 | connect_debug_port u_ila_0/probe5 [get_nets [list SDIN_out_OBUF]] 318 | set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] 319 | set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] 320 | set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] 321 | connect_debug_port dbg_hub/clk [get_nets MCLK_out_OBUF] 322 | -------------------------------------------------------------------------------- /vivado_project.tcl: -------------------------------------------------------------------------------- 1 | #***************************************************************************************** 2 | # Vivado (TM) v2018.2 (64-bit) 3 | # 4 | # vivado_project.tcl: Tcl script for re-creating project 'vivado_project' 5 | # 6 | # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 7 | # 8 | # This file contains the Vivado Tcl commands for re-creating the project to the state* 9 | # when this script was generated. In order to re-create the project, please source this 10 | # file in the Vivado Tcl Shell. 11 | # 12 | # * Note that the runs in the created project will be configured the same way as the 13 | # original project, however they will not be launched automatically. To regenerate the 14 | # run results please launch the synthesis/implementation runs as needed. 15 | # 16 | #***************************************************************************************** 17 | # Set the reference directory for source file relative paths (by default the value is script directory path) 18 | set origin_dir [file dirname [info script]] 19 | 20 | # Use origin directory path location variable, if specified in the tcl shell 21 | if { [info exists ::origin_dir_loc] } { 22 | set origin_dir $::origin_dir_loc 23 | } 24 | 25 | # Set the project name 26 | set _xil_proj_name_ "vivado_project" 27 | 28 | # Use project name variable, if specified in the tcl shell 29 | if { [info exists ::user_project_name] } { 30 | set _xil_proj_name_ $::user_project_name 31 | } 32 | 33 | variable script_file 34 | set script_file "vivado_project.tcl" 35 | 36 | # Help information for this script 37 | proc help {} { 38 | variable script_file 39 | puts "\nDescription:" 40 | puts "Recreate a Vivado project from this script. The created project will be" 41 | puts "functionally equivalent to the original project for which this script was" 42 | puts "generated. The script contains commands for creating a project, filesets," 43 | puts "runs, adding/importing sources and setting properties on various objects.\n" 44 | puts "Syntax:" 45 | puts "$script_file" 46 | puts "$script_file -tclargs \[--origin_dir \]" 47 | puts "$script_file -tclargs \[--project_name \]" 48 | puts "$script_file -tclargs \[--help\]\n" 49 | puts "Usage:" 50 | puts "Name Description" 51 | puts "-------------------------------------------------------------------------" 52 | puts "\[--origin_dir \] Determine source file paths wrt this path. Default" 53 | puts " origin_dir path value is \".\", otherwise, the value" 54 | puts " that was set with the \"-paths_relative_to\" switch" 55 | puts " when this script was generated.\n" 56 | puts "\[--project_name \] Create project with the specified name. Default" 57 | puts " name is the name of the project from where this" 58 | puts " script was generated.\n" 59 | puts "\[--help\] Print help information for this script" 60 | puts "-------------------------------------------------------------------------\n" 61 | exit 0 62 | } 63 | 64 | if { $::argc > 0 } { 65 | for {set i 0} {$i < $::argc} {incr i} { 66 | set option [string trim [lindex $::argv $i]] 67 | switch -regexp -- $option { 68 | "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } 69 | "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } 70 | "--help" { help } 71 | default { 72 | if { [regexp {^-} $option] } { 73 | puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" 74 | return 1 75 | } 76 | } 77 | } 78 | } 79 | } 80 | 81 | # Set the directory path for the original project from where this script was exported 82 | set orig_proj_dir "[file normalize "$origin_dir/vivado_project"]" 83 | 84 | # Create project 85 | create_project ${_xil_proj_name_} $origin_dir/vivado_project -part xc7a100tcsg324-1 -quiet -force 86 | 87 | # Set the directory path for the new project 88 | set proj_dir [get_property directory [current_project]] 89 | 90 | # Reconstruct message rules 91 | # None 92 | 93 | # Set project properties 94 | set obj [current_project] 95 | set_property -name "default_lib" -value "xil_defaultlib" -objects $obj 96 | set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj 97 | set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj 98 | set_property -name "dsa.board_id" -value "nexys4_ddr" -objects $obj 99 | set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj 100 | set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj 101 | set_property -name "dsa.emu_dir" -value "emu" -objects $obj 102 | set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj 103 | set_property -name "dsa.flash_offset_address" -value "0" -objects $obj 104 | set_property -name "dsa.flash_size" -value "1024" -objects $obj 105 | set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj 106 | set_property -name "dsa.host_interface" -value "pcie" -objects $obj 107 | set_property -name "dsa.num_compute_units" -value "60" -objects $obj 108 | set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj 109 | set_property -name "dsa.uses_pr" -value "1" -objects $obj 110 | set_property -name "dsa.vendor" -value "xilinx" -objects $obj 111 | set_property -name "dsa.version" -value "0.0" -objects $obj 112 | set_property -name "enable_vhdl_2008" -value "1" -objects $obj 113 | set_property -name "ip_cache_permissions" -value "read write" -objects $obj 114 | set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj 115 | set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj 116 | set_property -name "part" -value "xc7a100tcsg324-1" -objects $obj 117 | set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj 118 | set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj 119 | set_property -name "simulator_language" -value "Mixed" -objects $obj 120 | set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj 121 | set_property -name "target_language" -value "VHDL" -objects $obj 122 | set_property -name "webtalk.activehdl_export_sim" -value "174" -objects $obj 123 | set_property -name "webtalk.ies_export_sim" -value "174" -objects $obj 124 | set_property -name "webtalk.modelsim_export_sim" -value "174" -objects $obj 125 | set_property -name "webtalk.questa_export_sim" -value "174" -objects $obj 126 | set_property -name "webtalk.riviera_export_sim" -value "174" -objects $obj 127 | set_property -name "webtalk.vcs_export_sim" -value "174" -objects $obj 128 | set_property -name "webtalk.xsim_export_sim" -value "174" -objects $obj 129 | set_property -name "webtalk.xsim_launch_sim" -value "393" -objects $obj 130 | set_property -name "xpm_libraries" -value "XPM_CDC" -objects $obj 131 | 132 | # Create 'sources_1' fileset (if not found) 133 | if {[string equal [get_filesets -quiet sources_1] ""]} { 134 | create_fileset -srcset sources_1 135 | } 136 | 137 | # Set IP repository paths 138 | set obj [get_filesets sources_1] 139 | set_property "ip_repo_paths" "[file normalize "$origin_dir/../../IP_sincos"]" $obj 140 | 141 | # Rebuild user ip_repo's index before adding any source files 142 | update_ip_catalog -rebuild 143 | 144 | # Set 'sources_1' fileset object 145 | set obj [get_filesets sources_1] 146 | set files [list \ 147 | [file normalize "${origin_dir}/src/blockdesign/design_1.bd"] \ 148 | [file normalize "${origin_dir}/src/design/types.vhd"] \ 149 | [file normalize "${origin_dir}/src/design/square_wave.vhd"] \ 150 | [file normalize "${origin_dir}/src/design/i2s_sender.vhd"] \ 151 | [file normalize "${origin_dir}/src/design/design_1_wrapper.vhd"] \ 152 | [file normalize "${origin_dir}/src/design/sincos/rtl/sincos_gen.vhdl"] \ 153 | [file normalize "${origin_dir}/src/design/sine_generator_types.vhd"] \ 154 | [file normalize "${origin_dir}/src/design/sine_wave.vhd"] \ 155 | ] 156 | add_files -norecurse -fileset $obj $files 157 | 158 | # Set 'sources_1' fileset file properties for remote files 159 | set file "$origin_dir/src/blockdesign/design_1.bd" 160 | set file [file normalize $file] 161 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 162 | set_property -name "registered_with_manager" -value "1" -objects $file_obj 163 | set_property -name "used_in" -value "synthesis implementation" -objects $file_obj 164 | set_property -name "used_in_simulation" -value "0" -objects $file_obj 165 | 166 | set file "$origin_dir/src/design/types.vhd" 167 | set file [file normalize $file] 168 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 169 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 170 | 171 | set file "$origin_dir/src/design/square_wave.vhd" 172 | set file [file normalize $file] 173 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 174 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 175 | 176 | set file "$origin_dir/src/design/i2s_sender.vhd" 177 | set file [file normalize $file] 178 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 179 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 180 | 181 | set file "$origin_dir/src/design/design_1_wrapper.vhd" 182 | set file [file normalize $file] 183 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 184 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 185 | set_property -name "used_in" -value "synthesis" -objects $file_obj 186 | set_property -name "used_in_simulation" -value "0" -objects $file_obj 187 | 188 | set file "$origin_dir/src/design/sincos/rtl/sincos_gen.vhdl" 189 | set file [file normalize $file] 190 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 191 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 192 | 193 | set file "$origin_dir/src/design/sine_generator_types.vhd" 194 | set file [file normalize $file] 195 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 196 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 197 | 198 | set file "$origin_dir/src/design/sine_wave.vhd" 199 | set file [file normalize $file] 200 | set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] 201 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 202 | 203 | 204 | # Set 'sources_1' fileset file properties for local files 205 | # None 206 | 207 | # Set 'sources_1' fileset properties 208 | set obj [get_filesets sources_1] 209 | set_property -name "top" -value "design_1_wrapper" -objects $obj 210 | set_property -name "top_auto_set" -value "0" -objects $obj 211 | 212 | # Create 'constrs_1' fileset (if not found) 213 | if {[string equal [get_filesets -quiet constrs_1] ""]} { 214 | create_fileset -constrset constrs_1 215 | } 216 | 217 | # Set 'constrs_1' fileset object 218 | set obj [get_filesets constrs_1] 219 | 220 | # Add/Import constrs file and set constrs file properties 221 | set file "[file normalize "$origin_dir/src/design/Nexys-4-DDR-Master.xdc"]" 222 | set file_added [add_files -norecurse -fileset $obj [list $file]] 223 | set file "$origin_dir/src/design/Nexys-4-DDR-Master.xdc" 224 | set file [file normalize $file] 225 | set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] 226 | set_property -name "file_type" -value "XDC" -objects $file_obj 227 | 228 | # Set 'constrs_1' fileset properties 229 | set obj [get_filesets constrs_1] 230 | set_property -name "target_constrs_file" -value "[file normalize "$origin_dir/src/design/Nexys-4-DDR-Master.xdc"]" -objects $obj 231 | set_property -name "target_part" -value "xc7a100tcsg324-1" -objects $obj 232 | set_property -name "target_ucf" -value "[file normalize "$origin_dir/src/design/Nexys-4-DDR-Master.xdc"]" -objects $obj 233 | 234 | # Create 'sim_1' fileset (if not found) 235 | if {[string equal [get_filesets -quiet sim_1] ""]} { 236 | create_fileset -simset sim_1 237 | } 238 | 239 | # Set 'sim_1' fileset object 240 | set obj [get_filesets sim_1] 241 | # Empty (no sources present) 242 | 243 | # Set 'sim_1' fileset properties 244 | set obj [get_filesets sim_1] 245 | 246 | # Create 'sim_i2s' fileset (if not found) 247 | if {[string equal [get_filesets -quiet sim_i2s] ""]} { 248 | create_fileset -simset sim_i2s 249 | } 250 | 251 | # Set 'sim_i2s' fileset object 252 | set obj [get_filesets sim_i2s] 253 | set files [list \ 254 | [file normalize "${origin_dir}/src/testbench/i2s_testbench.vhd"] \ 255 | [file normalize "${origin_dir}/src/testbench/i2s_testbench_behav.wcfg"] \ 256 | ] 257 | add_files -norecurse -fileset $obj $files 258 | 259 | # Set 'sim_i2s' fileset file properties for remote files 260 | set file "$origin_dir/src/testbench/i2s_testbench.vhd" 261 | set file [file normalize $file] 262 | set file_obj [get_files -of_objects [get_filesets sim_i2s] [list "*$file"]] 263 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 264 | 265 | 266 | # Set 'sim_i2s' fileset file properties for local files 267 | # None 268 | 269 | # Set 'sim_i2s' fileset properties 270 | set obj [get_filesets sim_i2s] 271 | set_property -name "top" -value "i2s_testbench" -objects $obj 272 | set_property -name "top_auto_set" -value "0" -objects $obj 273 | 274 | # Create 'sine_sim' fileset (if not found) 275 | if {[string equal [get_filesets -quiet sine_sim] ""]} { 276 | create_fileset -simset sine_sim 277 | } 278 | 279 | # Set 'sine_sim' fileset object 280 | set obj [get_filesets sine_sim] 281 | set files [list \ 282 | [file normalize "${origin_dir}/src/testbench/sine/sine_testbench.vhd"] \ 283 | ] 284 | add_files -norecurse -fileset $obj $files 285 | 286 | # Set 'sine_sim' fileset file properties for remote files 287 | set file "$origin_dir/src/testbench/sine/sine_testbench.vhd" 288 | set file [file normalize $file] 289 | set file_obj [get_files -of_objects [get_filesets sine_sim] [list "*$file"]] 290 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 291 | set_property -name "used_in" -value "simulation" -objects $file_obj 292 | set_property -name "used_in_synthesis" -value "0" -objects $file_obj 293 | 294 | 295 | # Set 'sine_sim' fileset file properties for local files 296 | # None 297 | 298 | # Set 'sine_sim' fileset properties 299 | set obj [get_filesets sine_sim] 300 | set_property -name "top" -value "sine_testbench" -objects $obj 301 | set_property -name "top_auto_set" -value "0" -objects $obj 302 | 303 | # Create 'wave_sim' fileset (if not found) 304 | if {[string equal [get_filesets -quiet wave_sim] ""]} { 305 | create_fileset -simset wave_sim 306 | } 307 | 308 | # Set 'wave_sim' fileset object 309 | set obj [get_filesets wave_sim] 310 | set files [list \ 311 | [file normalize "${origin_dir}/src/testbench/wave/wave_testbench.vhd"] \ 312 | [file normalize "${origin_dir}/src/testbench/wave/wave_testbench_behav.wcfg"] \ 313 | ] 314 | add_files -norecurse -fileset $obj $files 315 | 316 | # Set 'wave_sim' fileset file properties for remote files 317 | set file "$origin_dir/src/testbench/wave/wave_testbench.vhd" 318 | set file [file normalize $file] 319 | set file_obj [get_files -of_objects [get_filesets wave_sim] [list "*$file"]] 320 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 321 | 322 | 323 | # Set 'wave_sim' fileset file properties for local files 324 | # None 325 | 326 | # Set 'wave_sim' fileset properties 327 | set obj [get_filesets wave_sim] 328 | set_property -name "top" -value "wave_testbench" -objects $obj 329 | set_property -name "top_auto_set" -value "0" -objects $obj 330 | 331 | # Create 'sine_i2s' fileset (if not found) 332 | if {[string equal [get_filesets -quiet sine_i2s] ""]} { 333 | create_fileset -simset sine_i2s 334 | } 335 | 336 | # Set 'sine_i2s' fileset object 337 | set obj [get_filesets sine_i2s] 338 | set files [list \ 339 | [file normalize "${origin_dir}/src/testbench/i2s_sine/i2s_sine_testbench.vhd"] \ 340 | [file normalize "${origin_dir}/src/testbench/i2s_sine/i2s_sine_testbench_behav.wcfg"] \ 341 | ] 342 | add_files -norecurse -fileset $obj $files 343 | 344 | # Set 'sine_i2s' fileset file properties for remote files 345 | set file "$origin_dir/src/testbench/i2s_sine/i2s_sine_testbench.vhd" 346 | set file [file normalize $file] 347 | set file_obj [get_files -of_objects [get_filesets sine_i2s] [list "*$file"]] 348 | set_property -name "file_type" -value "VHDL 2008" -objects $file_obj 349 | 350 | 351 | # Set 'sine_i2s' fileset file properties for local files 352 | # None 353 | 354 | # Set 'sine_i2s' fileset properties 355 | set obj [get_filesets sine_i2s] 356 | set_property -name "top" -value "i2s_sine_testbench" -objects $obj 357 | set_property -name "top_auto_set" -value "0" -objects $obj 358 | 359 | # Create 'synth_1' run (if not found) 360 | if {[string equal [get_runs -quiet synth_1] ""]} { 361 | create_run -name synth_1 -part xc7a100tcsg324-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 362 | } else { 363 | set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] 364 | set_property flow "Vivado Synthesis 2018" [get_runs synth_1] 365 | } 366 | set obj [get_runs synth_1] 367 | set_property set_report_strategy_name 1 $obj 368 | set_property report_strategy {Vivado Synthesis Default Reports} $obj 369 | set_property set_report_strategy_name 0 $obj 370 | # Create 'synth_1_synth_report_utilization_0' report (if not found) 371 | if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { 372 | create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 373 | } 374 | set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] 375 | if { $obj != "" } { 376 | 377 | } 378 | set obj [get_runs synth_1] 379 | set_property -name "part" -value "xc7a100tcsg324-1" -objects $obj 380 | set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj 381 | 382 | # set the current synth run 383 | current_run -synthesis [get_runs synth_1] 384 | 385 | # Create 'impl_1' run (if not found) 386 | if {[string equal [get_runs -quiet impl_1] ""]} { 387 | create_run -name impl_1 -part xc7a100tcsg324-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 388 | } else { 389 | set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] 390 | set_property flow "Vivado Implementation 2018" [get_runs impl_1] 391 | } 392 | set obj [get_runs impl_1] 393 | set_property set_report_strategy_name 1 $obj 394 | set_property report_strategy {Vivado Implementation Default Reports} $obj 395 | set_property set_report_strategy_name 0 $obj 396 | # Create 'impl_1_init_report_timing_summary_0' report (if not found) 397 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { 398 | create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 399 | } 400 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] 401 | if { $obj != "" } { 402 | set_property -name "is_enabled" -value "0" -objects $obj 403 | 404 | } 405 | # Create 'impl_1_opt_report_drc_0' report (if not found) 406 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { 407 | create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 408 | } 409 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] 410 | if { $obj != "" } { 411 | 412 | } 413 | # Create 'impl_1_opt_report_timing_summary_0' report (if not found) 414 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { 415 | create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 416 | } 417 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] 418 | if { $obj != "" } { 419 | set_property -name "is_enabled" -value "0" -objects $obj 420 | 421 | } 422 | # Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) 423 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { 424 | create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 425 | } 426 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] 427 | if { $obj != "" } { 428 | set_property -name "is_enabled" -value "0" -objects $obj 429 | 430 | } 431 | # Create 'impl_1_place_report_io_0' report (if not found) 432 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { 433 | create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 434 | } 435 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] 436 | if { $obj != "" } { 437 | 438 | } 439 | # Create 'impl_1_place_report_utilization_0' report (if not found) 440 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { 441 | create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 442 | } 443 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] 444 | if { $obj != "" } { 445 | 446 | } 447 | # Create 'impl_1_place_report_control_sets_0' report (if not found) 448 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { 449 | create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 450 | } 451 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] 452 | if { $obj != "" } { 453 | 454 | } 455 | # Create 'impl_1_place_report_incremental_reuse_0' report (if not found) 456 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { 457 | create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 458 | } 459 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] 460 | if { $obj != "" } { 461 | set_property -name "is_enabled" -value "0" -objects $obj 462 | 463 | } 464 | # Create 'impl_1_place_report_incremental_reuse_1' report (if not found) 465 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { 466 | create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 467 | } 468 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] 469 | if { $obj != "" } { 470 | set_property -name "is_enabled" -value "0" -objects $obj 471 | 472 | } 473 | # Create 'impl_1_place_report_timing_summary_0' report (if not found) 474 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { 475 | create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 476 | } 477 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] 478 | if { $obj != "" } { 479 | set_property -name "is_enabled" -value "0" -objects $obj 480 | 481 | } 482 | # Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) 483 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { 484 | create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 485 | } 486 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] 487 | if { $obj != "" } { 488 | set_property -name "is_enabled" -value "0" -objects $obj 489 | 490 | } 491 | # Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) 492 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { 493 | create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 494 | } 495 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] 496 | if { $obj != "" } { 497 | set_property -name "is_enabled" -value "0" -objects $obj 498 | 499 | } 500 | # Create 'impl_1_route_report_drc_0' report (if not found) 501 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { 502 | create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 503 | } 504 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] 505 | if { $obj != "" } { 506 | 507 | } 508 | # Create 'impl_1_route_report_methodology_0' report (if not found) 509 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { 510 | create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 511 | } 512 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] 513 | if { $obj != "" } { 514 | 515 | } 516 | # Create 'impl_1_route_report_power_0' report (if not found) 517 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { 518 | create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 519 | } 520 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] 521 | if { $obj != "" } { 522 | 523 | } 524 | # Create 'impl_1_route_report_route_status_0' report (if not found) 525 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { 526 | create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 527 | } 528 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] 529 | if { $obj != "" } { 530 | 531 | } 532 | # Create 'impl_1_route_report_timing_summary_0' report (if not found) 533 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { 534 | create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 535 | } 536 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] 537 | if { $obj != "" } { 538 | 539 | } 540 | # Create 'impl_1_route_report_incremental_reuse_0' report (if not found) 541 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { 542 | create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 543 | } 544 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] 545 | if { $obj != "" } { 546 | 547 | } 548 | # Create 'impl_1_route_report_clock_utilization_0' report (if not found) 549 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { 550 | create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 551 | } 552 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] 553 | if { $obj != "" } { 554 | 555 | } 556 | # Create 'impl_1_route_report_bus_skew_0' report (if not found) 557 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { 558 | create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 559 | } 560 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] 561 | if { $obj != "" } { 562 | 563 | } 564 | # Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) 565 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { 566 | create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 567 | } 568 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] 569 | if { $obj != "" } { 570 | 571 | } 572 | # Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) 573 | if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { 574 | create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 575 | } 576 | set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] 577 | if { $obj != "" } { 578 | 579 | } 580 | set obj [get_runs impl_1] 581 | set_property -name "part" -value "xc7a100tcsg324-1" -objects $obj 582 | set_property -name "gen_full_bitstream" -value "0" -objects $obj 583 | set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj 584 | set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj 585 | set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj 586 | 587 | # set the current impl run 588 | current_run -implementation [get_runs impl_1] 589 | 590 | # Change current directory to project folder 591 | cd [file dirname [info script]] 592 | 593 | puts "INFO: Project created:${_xil_proj_name_}" 594 | --------------------------------------------------------------------------------