├── matlab ├── file_io │ ├── fileInsertMatrix.m │ ├── fileInsertParameters.m │ └── writeDataVHDL.m ├── hdc │ ├── addHV.m │ ├── bundleHV.m │ ├── cellularAutomaton30.m │ ├── genRandomHV.m │ ├── genSimilarHV.m │ ├── hammingDistance.m │ ├── multHV.m │ ├── permHV.m │ └── rule30.m └── initParameters.m ├── readme.md └── vhdl ├── source ├── associative_memory │ ├── associative_memory_bs_arc.vhd │ ├── associative_memory_cmb_arc.vhd │ ├── associative_memory_ent.vhd │ └── associative_memory_vs_arc.vhd ├── hdc_baseline_pkg.vhd ├── hdc_enhanced_pkg.vhd ├── hdc_ent_arc.vhd ├── hdc_pkg.vhd ├── spatial_encoder │ ├── spatial_encoder_ca_arc.vhd │ ├── spatial_encoder_ent.vhd │ ├── spatial_encoder_lut_arc.vhd │ └── spatial_encoder_man_arc.vhd ├── support_circuits │ ├── block_shift_memory_ent_arc.vhd │ ├── bundle_counter_ent_arc.vhd │ ├── cellular_automaton_ent_arc.vhd │ ├── hypervector_manipulator_ent_arc.vhd │ └── similarity_bundler_ent_arc.vhd └── temporal_encoder │ ├── temporal_encoder_b2b_arc.vhd │ ├── temporal_encoder_bc_arc.vhd │ └── temporal_encoder_ent.vhd └── templates ├── hdc_baseline_pkg_temp.vhd ├── hdc_enhanced_pkg_temp.vhd └── hdc_pkg_temp.vhd /matlab/file_io/fileInsertMatrix.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function fileInsertMatrix(outputFilename, templateFilename, insertData, insertLinePositions) 12 | % 13 | % FILEINSERTMATRIX(outputFilename, templateFilename, insertData, insertLinePositions) 14 | % writes matrix data (e.g. connectivity matrices) into a VHDL package file. 15 | % 16 | % INPUTS: 17 | % outputFilename output file name specified as character string 18 | % templateFilename template file name specified as character string 19 | % insertData matrix data 20 | % insertLinePositions positions in the file where data is inserted 21 | % 22 | 23 | outputID = fopen(outputFilename,'w'); 24 | templateID = fopen(templateFilename,'r'); 25 | 26 | linePos = 1; 27 | for i = 1:length(insertLinePositions) 28 | for j = linePos:insertLinePositions(i)-1 29 | fprintf(outputID,'%c',fgets(templateID)); 30 | end 31 | for j = 1:size(insertData{i},1) 32 | fprintf(outputID,'\t\t"'); 33 | fprintf(outputID,'%d',insertData{i}(j,:)); 34 | if j ~= size(insertData{i},1) 35 | fprintf(outputID,'",\n'); 36 | else 37 | fprintf(outputID,'"\n'); 38 | end 39 | end 40 | fgets(templateID); 41 | linePos = insertLinePositions(i)+1; 42 | end 43 | 44 | tLine = fgets(templateID); 45 | while ischar(tLine) 46 | fprintf(outputID,'%c',tLine); 47 | tLine = fgets(templateID); 48 | end 49 | 50 | fclose('all'); 51 | 52 | end -------------------------------------------------------------------------------- /matlab/file_io/fileInsertParameters.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function fileInsertParameters(outputFilename, templateFilename, insertData, insertLinePositions) 12 | % 13 | % FILEINSERTPARAMETERS(outputFilename, outputFilename, insertData, insertLinePositions) 14 | % inserts parameters (e.g. hypervector dimension) into VHDL package file. 15 | % 16 | % INPUTS: 17 | % outputFilename output file name specified as character string 18 | % templateFilename template file name specified as character string 19 | % insertData parameter data (cell array of character strings) 20 | % insertLinePositions positions in the file where data is inserted 21 | % 22 | 23 | outputID = fopen(outputFilename,'w'); 24 | templateID = fopen(templateFilename,'r'); 25 | 26 | linePos = 1; 27 | for i = 1:length(insertLinePositions) 28 | for j = linePos:insertLinePositions(i)-1 29 | fprintf(outputID,'%c',fgets(templateID)); 30 | end 31 | tempLine = fgetl(templateID); 32 | for j = 1:length(tempLine) 33 | if tempLine(j) == '=' 34 | fprintf(outputID,'%c',tempLine(1:j)); 35 | fprintf(outputID,' %s;\n',num2str(insertData{i})); 36 | break; 37 | end 38 | end 39 | linePos = insertLinePositions(i)+1; 40 | end 41 | 42 | tLine = fgets(templateID); 43 | while ischar(tLine) 44 | fprintf(outputID,'%c',tLine); 45 | tLine = fgets(templateID); 46 | end 47 | 48 | fclose('all'); 49 | 50 | end -------------------------------------------------------------------------------- /matlab/file_io/writeDataVHDL.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | % Writes all required data into the VHDL packages: 12 | % Parameters, Connectivity Matrices, Lookup Tables, Seed Vectors 13 | 14 | %% Parameters 15 | 16 | outputFilenameParameters = '../vhdl/source/hdc_pkg.vhd'; 17 | templateFilenameParameters = '../vhdl/templates/hdc_pkg_temp.vhd'; 18 | insertDataParameters = {HV_DIMENSION,... 19 | INPUT_CHANNELS,... 20 | INPUT_QUANTIZATION,... 21 | NGRAM_SIZE,... 22 | CLASSES,... 23 | BUNDLE_CHANNEL_BITS,... 24 | BUNDLE_NGRAM_BITS,... 25 | BUNDLE_NGRAM_CYCLES,... 26 | AM_BLOCK_WIDTH,... 27 | ['''' num2str(mode_train) ''''],... 28 | ['''' num2str(mode_predict) '''']}; 29 | insertPositionsParameters = [53:61 72:73]; 30 | 31 | fileInsertParameters(outputFilenameParameters,templateFilenameParameters,... 32 | insertDataParameters,insertPositionsParameters); 33 | 34 | 35 | %% Baseline Architecture Constants 36 | 37 | outputFilename_initBaseline = '../vhdl/source/hdc_baseline_pkg.vhd'; 38 | templateFilename_initBaseline = '../vhdl/templates/hdc_baseline_pkg_temp.vhd'; 39 | insertData_initBaseline = {iM,CiM}; 40 | insertPositions_initBaseline = [41,45]; 41 | 42 | fileInsertMatrix(outputFilename_initBaseline,templateFilename_initBaseline,... 43 | insertData_initBaseline,insertPositions_initBaseline); 44 | 45 | 46 | %% Improved Architecture Constants 47 | 48 | outputFilename_initImproved = '../vhdl/source/hdc_enhanced_pkg.vhd'; 49 | templateFilename_initImproved = '../vhdl/templates/hdc_enhanced_pkg_temp.vhd'; 50 | insertData_init = {NHot_LUT,iM_seedHV,CiM_seedHV,iMMatrix,CiMMatrix,bnMatrix}; 51 | insertPositions_init = 41:4:61; 52 | 53 | fileInsertMatrix(outputFilename_initImproved,templateFilename_initImproved,... 54 | insertData_init,insertPositions_init); 55 | -------------------------------------------------------------------------------- /matlab/hdc/addHV.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function HVOut = addHV(HVInArray) 12 | % 13 | % ADDHV(HVInArray) computes majority vote hypervectors, breaking ties 14 | % according to ADD_MODE. 15 | % 16 | % INPUTS: 17 | % HVInArray array of hypervectors 18 | % OUTPUTS: 19 | % HVOut majority vote of input hypervectors 20 | % 21 | 22 | global btM ADD_MODE HV_DIMENSION %#ok 23 | 24 | sArr = size(HVInArray); 25 | 26 | HVOut = zeros(1,sArr(2)); 27 | 28 | for i = 1:sArr(1) 29 | HVOut = HVOut + HVInArray(i,:); 30 | end 31 | 32 | if mod(sArr(1),2) == 1 33 | HVOut = HVOut/sArr(1); 34 | HVOut = round(HVOut); 35 | elseif mod(sArr(1),2) == 0 36 | switch ADD_MODE 37 | case 'random' 38 | HVOut = HVOut/sArr(1); 39 | % HVOut = (HVOut + genRandomHV(HV_DIMENSION))/(sArr(1)+1); 40 | for i = 1:size(HVInArray,2) 41 | if HVOut(i) == 0.5 42 | HVOut(i) = round(rand); 43 | else 44 | HVOut(i) = round(HVOut(i)); 45 | end 46 | end 47 | case 'vector' 48 | HVOut = (HVOut + btM)/(sArr(1)+1); 49 | HVOut = round(HVOut); 50 | case 'bind' 51 | HVOut = (HVOut + multHV(HVOut))/(sArr(1)+1); 52 | end 53 | 54 | end 55 | 56 | end -------------------------------------------------------------------------------- /matlab/hdc/bundleHV.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function HVOut = bundleHV(HVInArray,bundle_mode,bundle_bits) 12 | % 13 | % BUNDLEHV(HVInArray,bundle_mode,bundle_bits) bundles hypervectors according 14 | % to bundle_mode 15 | % 16 | % INPUTS: 17 | % HVInArray array of hypervectors 18 | % bundle_mode bundle mode specified as string 19 | % bundle_bits number of bits when using the bundle counter 20 | % OUTPUTS: 21 | % HVOut hypervector record 22 | % 23 | 24 | global HV_DIMENSION bnMatrix 25 | 26 | switch bundle_mode 27 | case 'golden' 28 | HVOut = addHV(HVInArray); 29 | 30 | case 'up_down_counter_random' 31 | maxValue = 2^(bundle_bits-1)-1; 32 | minValue = -2^(bundle_bits-1); 33 | 34 | Counter = zeros(1,HV_DIMENSION); 35 | for i = 1:size(HVInArray,1) 36 | for j = 1:HV_DIMENSION 37 | if HVInArray(i,j) == 1 38 | Counter(j) = min(maxValue,Counter(j)+1); 39 | else 40 | Counter(j) = max(minValue,Counter(j)-1); 41 | end 42 | end 43 | end 44 | 45 | HVOut = zeros(1,HV_DIMENSION); 46 | for i = 1:HV_DIMENSION 47 | if Counter(i) > 0 48 | HVOut(i) = 1; 49 | elseif Counter(i) < 0 50 | HVOut(i) = 0; 51 | else 52 | HVOut(i) = round(rand); 53 | end 54 | end 55 | 56 | case 'up_down_counter' 57 | maxValue = 2^(bundle_bits-1)-1; 58 | minValue = -2^(bundle_bits-1); 59 | 60 | Counter = zeros(1,HV_DIMENSION); 61 | for i = 1:HV_DIMENSION 62 | if HVInArray(1,i) == 1 63 | Counter(i) = 0; 64 | else 65 | Counter(i) = -1; 66 | end 67 | end 68 | 69 | for i = 2:size(HVInArray,1) 70 | for j = 1:HV_DIMENSION 71 | if HVInArray(i,j) == 1 72 | Counter(j) = min(maxValue,Counter(j)+1); 73 | else 74 | Counter(j) = max(minValue,Counter(j)-1); 75 | end 76 | end 77 | end 78 | 79 | HVOut = zeros(1,HV_DIMENSION); 80 | for i = 1:HV_DIMENSION 81 | if Counter(i) >= 0 82 | HVOut(i) = 1; 83 | else 84 | HVOut(i) = 0; 85 | end 86 | end 87 | 88 | case 'back_to_back_random' 89 | HVOut = HVInArray(1,:); 90 | for i = 2:size(HVInArray,1) 91 | tempSimilarHV = genSimilarHV(HVOut,round(HV_DIMENSION/i)); 92 | HVOut = addHV([HVOut;HVInArray(i,:);tempSimilarHV]); 93 | end 94 | 95 | case 'back_to_back' 96 | HVOut = HVInArray(1,:); 97 | for i = 2:size(HVInArray,1) 98 | tempSimilarHV = double(xor(HVOut,bnMatrix(i,:))); 99 | HVOut = addHV([HVOut;HVInArray(i,:);tempSimilarHV]); 100 | end 101 | end 102 | end -------------------------------------------------------------------------------- /matlab/hdc/cellularAutomaton30.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function HVOut = cellularAutomaton30(seedHV,cycles) 12 | 13 | global HV_DIMENSION 14 | 15 | HVOut = seedHV; 16 | 17 | for i = 1:cycles 18 | tempHV = HVOut; 19 | HVOut(1) = rule30([tempHV(HV_DIMENSION) tempHV(1) tempHV(2)]); 20 | HVOut(HV_DIMENSION) = rule30([tempHV(HV_DIMENSION-1) tempHV(HV_DIMENSION) tempHV(1)]); 21 | for j = 2:HV_DIMENSION-1 22 | HVOut(j) = rule30(tempHV(j-1:j+1)); 23 | end 24 | end 25 | 26 | end -------------------------------------------------------------------------------- /matlab/hdc/genRandomHV.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function randomHV = genRandomHV(D) 12 | 13 | if(mod(D,2)) 14 | disp('Dimension is odd!!'); 15 | return; 16 | end 17 | 18 | randomHV = zeros(1,D); 19 | randomIndex = randperm(D); 20 | randomHV(randomIndex(1:round(D/2))) = 1; 21 | 22 | 23 | end -------------------------------------------------------------------------------- /matlab/hdc/genSimilarHV.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function similarHV = genSimilarHV(HV,dist) 12 | % 13 | % DESCRIPTION : generates a HV with specified Hamming distance from input 14 | % HV 15 | % 16 | % INPUTS: 17 | % HV : hypervector 18 | % dist : Hamming distance 19 | % OUTPUTS: 20 | % similarHV : similar hypervector 21 | 22 | randomIndex = randperm(length(HV)); 23 | flipVec = zeros(size(HV)); 24 | flipVec(randomIndex(1:dist)) = 1; 25 | 26 | similarHV = double(xor(HV,flipVec)); 27 | 28 | end -------------------------------------------------------------------------------- /matlab/hdc/hammingDistance.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function dist = hammingDistance(HV1,HV2,normalize) 12 | 13 | if(size(HV1) ~= size(HV2)) 14 | disp('Hypervector dimension do not match!'); 15 | end 16 | 17 | distVec = double(xor(logical(HV1),logical(HV2))); 18 | dist = sum(distVec); 19 | 20 | if exist('normalize','var') 21 | if normalize 22 | dist = dist/length(HV1); 23 | end 24 | end 25 | 26 | end -------------------------------------------------------------------------------- /matlab/hdc/multHV.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function HVOut = multHV(HVInArray) 12 | 13 | HVOut = HVInArray(1,:); 14 | for i = 2:size(HVInArray,1) 15 | HVOut = double(xor(logical(HVOut),logical(HVInArray(i,:)))); 16 | end 17 | 18 | end -------------------------------------------------------------------------------- /matlab/hdc/permHV.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function HVout = permHV(HVIn,times) 12 | 13 | HVout = circshift(HVIn,times); 14 | 15 | end -------------------------------------------------------------------------------- /matlab/hdc/rule30.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | function bitOut = rule30(BitArrayIn) 12 | 13 | if (size(BitArrayIn,2) ~= 3) || (size(BitArrayIn,1) ~= 1) 14 | disp('Not a suitable neighborhood array!'); 15 | return; 16 | end 17 | 18 | switch num2str(BitArrayIn) 19 | case num2str([0 0 0]) 20 | bitOut = 0; 21 | case num2str([0 0 1]) 22 | bitOut = 1; 23 | case num2str([0 1 0]) 24 | bitOut = 1; 25 | case num2str([0 1 1]) 26 | bitOut = 1; 27 | case num2str([1 0 0]) 28 | bitOut = 1; 29 | case num2str([1 0 1]) 30 | bitOut = 0; 31 | case num2str([1 1 0]) 32 | bitOut = 0; 33 | case num2str([1 1 1]) 34 | bitOut = 0; 35 | end 36 | 37 | 38 | end -------------------------------------------------------------------------------- /matlab/initParameters.m: -------------------------------------------------------------------------------- 1 | % Copyright 2018 ETH Zurich 2 | % Copyright and related rights are licensed under the Solderpad Hardware 3 | % License, Version 0.51 (the “License”); you may not use this file except in 4 | % compliance with the License. You may obtain a copy of the License at 5 | % http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | % or agreed to in writing, software, hardware and materials distributed under 7 | % this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | % CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | % specific language governing permissions and limitations under the License. 10 | 11 | % Initalises all parameters, storages and matrices required for HDC 12 | 13 | clear all; %#ok<*CLALL> 14 | 15 | %% Define Parameters 16 | global HV_DIMENSION CLASSES INPUT_CHANNELS INPUT_QUANTIZATION... 17 | BUNDLE_CHANNEL_BITS NGRAM_SIZE BUNDLE_NGRAM_BITS BUNDLE_NGRAM_CYCLES... 18 | AM_BLOCK_WIDTH mode_train mode_predict 19 | 20 | % Adjust these parameters to your needs 21 | HV_DIMENSION = 2^10; 22 | CLASSES = 5; 23 | INPUT_CHANNELS = 4; 24 | INPUT_QUANTIZATION = 21; 25 | BUNDLE_CHANNEL_BITS = 3; 26 | NGRAM_SIZE = 3; 27 | BUNDLE_NGRAM_BITS = 5; 28 | BUNDLE_NGRAM_CYCLES = 2^5; % has to be larger than the number of training samples 29 | AM_BLOCK_WIDTH = 2^6; 30 | 31 | mode_train = 0; 32 | mode_predict = 1; 33 | 34 | %% Calculations 35 | global LABEL_WIDTH INPUT_WIDTH DISTANCE_WIDTH 36 | 37 | LABEL_WIDTH = ceil(log2(CLASSES)); 38 | INPUT_WIDTH = ceil(log2(INPUT_QUANTIZATION)); 39 | DISTANCE_WIDTH = ceil(log2(HV_DIMENSION)); 40 | 41 | %% Modes 42 | global CIM_MODE IM_MODE ADD_MODE CNTR_OVERFLOW_MODE... 43 | SPATIAL_MODE BUNDLE_CHANNEL_MODE BUNDLE_NGRAM_MODE 44 | 45 | % Change these to configure the HDC classifier. 46 | CIM_MODE = 'mapped_xor'; 47 | % IM_MODE = 'random'; 48 | IM_MODE = 'cellular_automaton'; 49 | ADD_MODE = 'random'; 50 | CNTR_OVERFLOW_MODE = 'saturate'; 51 | SPATIAL_MODE = 'add_channel'; 52 | % BUNDLE_CHANNEL_MODE = 'golden'; 53 | BUNDLE_CHANNEL_MODE = 'up_down_counter'; 54 | % BUNDLE_CHANNEL_MODE = 'back_to_back'; 55 | % BUNDLE_NGRAM_MODE = 'golden'; 56 | BUNDLE_NGRAM_MODE = 'back_to_back'; 57 | % BUNDLE_NGRAM_MODE = 'up_down_counter'; 58 | 59 | %% Seeds & Connectivity Matrices 60 | global iM_seedHV CiM_seedHV iMMatrix CiMMatrix bnMatrix 61 | 62 | iM_seedHV = genRandomHV(HV_DIMENSION); % stored in memory and used by cellular automaton 63 | CiM_seedHV = genRandomHV(HV_DIMENSION); % stored in memory 64 | 65 | iMMatrix = initiM; 66 | CiMMatrix = initCiMMatrix; 67 | bnMatrix = initbnMatrix; 68 | 69 | %% Memory 70 | global NHot_LUT iM CiM btM AM 71 | 72 | NHot_LUT = initNHot; 73 | iM = iMMatrix; 74 | CiM = initCiM; 75 | btM = genRandomHV(HV_DIMENSION); 76 | AM = zeros(CLASSES,HV_DIMENSION); 77 | 78 | %% Subfunctions 79 | function iM = initiM 80 | 81 | global INPUT_CHANNELS HV_DIMENSION iM_seedHV IM_MODE 82 | 83 | iM = zeros(INPUT_CHANNELS, HV_DIMENSION); 84 | 85 | switch IM_MODE 86 | case 'cellular_automaton' 87 | iM(1,:) = iM_seedHV; 88 | for i = 2:INPUT_CHANNELS 89 | iM(i,:) = cellularAutomaton30(iM(i-1,:),1); 90 | end 91 | case 'random' 92 | for i = 1:INPUT_CHANNELS 93 | iM(i,:) = genRandomHV(HV_DIMENSION); 94 | end 95 | end 96 | 97 | end 98 | 99 | function CiM = initCiM 100 | 101 | global HV_DIMENSION CIM_MODE INPUT_QUANTIZATION INPUT_WIDTH CiM_seedHV CiMMatrix 102 | 103 | CiM = zeros(INPUT_QUANTIZATION,HV_DIMENSION); 104 | for i = 1:size(CiM,1) 105 | CiM(i,:) = CiM_seedHV; 106 | end 107 | 108 | % nFlips = INPUT_QUANTIZATION-1; 109 | flipBits = HV_DIMENSION/2/(INPUT_QUANTIZATION-1); 110 | 111 | switch CIM_MODE 112 | case 'LUT' 113 | Ind = randperm(HV_DIMENSION); 114 | for i = 2:INPUT_QUANTIZATION 115 | for j = Ind(1:(i-1)*flipBits) 116 | if CiM(i,j) == 1 117 | CiM(i,j) = 0; 118 | elseif CiM(i,j) == 0 119 | CiM(i,j) = 1; 120 | end 121 | end 122 | end 123 | case 'direct_xor' 124 | widthVec = round(flipBits*2.^(0:INPUT_WIDTH-1)); 125 | for i = 2:INPUT_QUANTIZATION 126 | sensorBin = de2bi(i-1,INPUT_WIDTH,'right-msb'); 127 | start = 1; 128 | for j = 1:INPUT_WIDTH 129 | if sensorBin(j) == 1 130 | for k = start:start+widthVec(j)-1 131 | if CiM(i,k) == 1 132 | CiM(i,k) = 0; 133 | elseif CiM(i,k) == 0 134 | CiM(i,k) = 1; 135 | end 136 | end 137 | end 138 | start = start + widthVec(j); 139 | end 140 | end 141 | case 'mapped_xor' 142 | for i = 2:INPUT_QUANTIZATION 143 | CiM(i,:) = double(xor(CiM(i-1,:),CiMMatrix(i-1,:))); 144 | end 145 | end 146 | 147 | end 148 | 149 | function bnMatrix = initbnMatrix 150 | 151 | global BUNDLE_NGRAM_CYCLES HV_DIMENSION 152 | 153 | bnMatrix = zeros(BUNDLE_NGRAM_CYCLES,HV_DIMENSION); 154 | for i = 1:BUNDLE_NGRAM_CYCLES 155 | % randIndex = randperm(HV_DIMENSION); 156 | % bnMatrix(i,randIndex(1:round(HV_DIMENSION/i))) = 1; 157 | for j = 1:HV_DIMENSION 158 | if rand < 1/i 159 | bnMatrix(i,j) = 1; 160 | end 161 | end 162 | end 163 | 164 | end 165 | 166 | function CiMMatrix = initCiMMatrix 167 | 168 | global HV_DIMENSION INPUT_QUANTIZATION 169 | 170 | flipBits = HV_DIMENSION/2/(INPUT_QUANTIZATION-1); 171 | 172 | randIndex = randperm(HV_DIMENSION); 173 | CiMMatrix = zeros(INPUT_QUANTIZATION-1,HV_DIMENSION); 174 | for i = 1:INPUT_QUANTIZATION-1 175 | for j = randIndex(round(flipBits*(i-1))+1:round(flipBits*(i))) 176 | CiMMatrix(i,j) = 1; 177 | end 178 | end 179 | 180 | end 181 | 182 | function NHot_LUT = initNHot 183 | 184 | global INPUT_QUANTIZATION 185 | 186 | NHot_LUT = zeros(INPUT_QUANTIZATION,INPUT_QUANTIZATION-1); 187 | 188 | for i = 2:INPUT_QUANTIZATION 189 | for j = 1:i-1 190 | NHot_LUT(i,j) = 1; 191 | end 192 | end 193 | 194 | end -------------------------------------------------------------------------------- /readme.md: -------------------------------------------------------------------------------- 1 | # HDC Library for On-Chip Learning and Classification 2 | This repository provides a framework draft for an HDC classifier implementation in VHDL. The RTL model is fully synthesizable. 3 | 4 | ## Getting Started 5 | Included are: 6 | - configurable VHDL library modules for HDC learning and classification 7 | - MATLAB scripts to configure the VHDL modules 8 | 9 | ### Prerequisities 10 | To use this framework, the following software is required 11 | - MATLAB 2017b 12 | 13 | For the VHDL modules, the VHDL-2008 standard was followed. Other tools which the modules might be used with may have to be adapted to the standard. 14 | 15 | ### Folder Structure 16 | ``` 17 | . 18 | ├── matlab 19 | │   ├── file_io 20 | │   │   └── ... # Scripts for module configuration 21 | │   ├── hdc 22 | │   │   └── ... # HD computing functions 23 | │   └── initParameters.m # Script for initialization of memories, etc. 24 | └── vhdl 25 | ├── source 26 | │   ├── associative_memory 27 | │   │   └── ... # Associative memory modules 28 | │   ├── spatial_encoder 29 | │   │   └── ... # Spatial encoder modules 30 | │   ├── support_circuits 31 | │   │   └── ... # Submodules 32 | │   ├── temporal_encoder 33 | │   │ └── ... # Temporal encoder modules 34 | │ └── ... # Packages and top level modules 35 | └── templates 36 | └── ... # Templates used by MATLAB for configuration 37 | ``` 38 | 39 | ## User Guide 40 | ### Configuration 41 | The classifier architecture can be configured according to ones needs. This has to be done in the MATLAB scripts, since configuring the architecture requires to initialise multiple hypervectors and hypervector arrays, totalling several thousand bits, which can be automatically generated. To do so, follow these steps: 42 | 43 | **1.** Open MATLAB and navigate to the folder [matlab](./matlab/), execute `addpath(genpath('.'))` in the command window to make all functions and scripts accessible. 44 | 45 | --- 46 | 47 | **2.** Adjust the parameters and modes in the MATLAB file [initParameters](./matlab/initParameters.m). 48 | 49 | Following parameters have to be set to fully determine the classifier: 50 | ```matlab 51 | HV_DIMENSION 52 | CLASSES 53 | INPUT_CHANNELS 54 | INPUT_QUANTIZATION 55 | BUNDLE_CHANNEL_BITS 56 | NGRAM_SIZE 57 | BUNDLE_NGRAM_BITS 58 | BUNDLE_NGRAM_CYCLES 59 | ``` 60 | 61 | --- 62 | 63 | **3.** Make the changes effective by executing the following commands. 64 | ```matlab 65 | initParameters; 66 | writeDataVHDL; 67 | ``` 68 | The latter script writes all parameters, lookup tables, connectivity matrices, seed vectors, etc. to VHDL packages, which are part of the architectures. It uses the files in the [templates](./vhdl/templates/) folder and overwrites the values. The packages in the [source](./vhdl/source/) folder are overwritten every time `writeDataVHDL` is called. 69 | 70 | ## Paper 71 | 72 | M. Schmuck, L. Benini, A. Rahimi, "Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory". arXiv preprint: [arXiv:1807.08583](https://arxiv.org/abs/1807.08583). 73 | -------------------------------------------------------------------------------- /vhdl/source/associative_memory/associative_memory_bs_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Associative Memory 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : associative_memory_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the associative memory 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | 36 | ------------------------------------------------------------------------------- 37 | 38 | architecture bs of associative_memory is 39 | 40 | ----------------------------------------------------------------------------- 41 | -- Constants 42 | ----------------------------------------------------------------------------- 43 | constant SHIFT_CNTR_WIDTH : integer := num2bits(HV_DIMENSION+1); 44 | 45 | ----------------------------------------------------------------------------- 46 | -- Signals 47 | ----------------------------------------------------------------------------- 48 | -- Output Buffers 49 | signal LabelOut_DP, LabelOut_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 50 | signal DistanceOut_DP, DistanceOut_DN : std_logic_vector(DISTANCE_WIDTH-1 downto 0); 51 | 52 | -- Data Registers 53 | signal TrainedMemory_DP, TrainedMemory_DN : hypervector_array(0 to CLASSES-1)(0 to HV_DIMENSION-1); 54 | signal QueryHypervector_DP, QueryHypervector_DN : Hypervector(0 to HV_DIMENSION-1); 55 | signal DistanceCntrs_DP, DistanceCntrs_DN : unsigned_array(0 to CLASSES-1)(DISTANCE_WIDTH-1 downto 0); 56 | 57 | -- Control Registers 58 | type fsm_states is (idle, data_received, output_stable); 59 | signal FSM_SP, FSM_SN : fsm_states; 60 | signal ShiftCntr_SP, ShiftCntr_SN : unsigned(SHIFT_CNTR_WIDTH-1 downto 0); 61 | 62 | -- Datapath Signals 63 | signal SimilarityOut_D : std_logic_vector(0 to CLASSES-1); 64 | signal ComparatorLabelOut_D : unsigned(LABEL_WIDTH-1 downto 0); 65 | signal ComparatorDistanceOut_D : unsigned(DISTANCE_WIDTH-1 downto 0); 66 | 67 | -- Datapath Self-Control Signals 68 | signal DistanceCntrsSEN_S : std_logic_vector(0 to CLASSES-1); 69 | 70 | -- Status Signals 71 | signal ShiftComplete_S : std_logic; 72 | signal IdentifyLabel_S : std_logic_vector(0 to CLASSES-1); 73 | 74 | -- Control Signals 75 | signal OutputBuffersEN_S : std_logic; 76 | signal TrainedMemoryEN_S : std_logic_vector(0 to CLASSES-1); 77 | signal QueryHypervectorEN_S : std_logic; 78 | signal ShiftCntrEN_S : std_logic; 79 | signal ShiftCntrCLR_S : std_logic; 80 | signal DistanceCntrsEN_S : std_logic; 81 | signal DistanceCntrsCLR_S : std_logic; 82 | signal RotateMemories_S : std_logic; 83 | 84 | 85 | ----------------------------------------------------------------------------- 86 | -- Components 87 | ----------------------------------------------------------------------------- 88 | 89 | begin 90 | 91 | ----------------------------------------------------------------------------- 92 | ----------------------------------------------------------------------------- 93 | -- DATAPATH 94 | ----------------------------------------------------------------------------- 95 | ----------------------------------------------------------------------------- 96 | -- Input Signals 97 | ----------------------------------------------------------------------------- 98 | -- Trained Hypervector Memory 99 | gen_asgn_trained_memory1 : for i in 0 to CLASSES-1 generate 100 | TrainedMemory_DN(i) <= HypervectorIn_DI when RotateMemories_S = '0' else 101 | TrainedMemory_DP(i) rol 1; 102 | end generate gen_asgn_trained_memory1; 103 | 104 | -- Query Hypervector Memory 105 | QueryHypervector_DN <= HypervectorIn_DI when RotateMemories_S = '0' else 106 | QueryHypervector_DP rol 1; 107 | 108 | ----------------------------------------------------------------------------- 109 | -- Distance Calculation 110 | ----------------------------------------------------------------------------- 111 | -- Similarity 112 | gen_similarity : for i in 0 to CLASSES-1 generate 113 | SimilarityOut_D(i) <= TrainedMemory_DP(i)(TrainedMemory_DP(i)'low) xor 114 | QueryHypervector_DP(QueryHypervector_DP'low); 115 | end generate gen_similarity; 116 | 117 | -- Counters 118 | gen_counters : for i in 0 to CLASSES-1 generate 119 | DistanceCntrs_DN(i) <= DistanceCntrs_DP(i) + 1; 120 | DistanceCntrsSEN_S(i) <= SimilarityOut_D(i); 121 | end generate gen_counters; 122 | 123 | ----------------------------------------------------------------------------- 124 | -- Comparison 125 | ----------------------------------------------------------------------------- 126 | -- Comparators 127 | comb_comparators : process (DistanceCntrs_DP) 128 | variable min_temp : integer := 0; 129 | variable label_temp : integer := 0; 130 | begin -- process comb_comparators 131 | min_temp := to_integer(DistanceCntrs_DP(0)); 132 | label_temp := 0; 133 | for i in 1 to CLASSES-1 loop 134 | if to_integer(DistanceCntrs_DP(i)) < min_temp then 135 | min_temp := to_integer(DistanceCntrs_DP(i)); 136 | label_temp := i; 137 | end if; 138 | end loop; -- i 139 | ComparatorLabelOut_D <= to_unsigned(label_temp, LABEL_WIDTH); 140 | ComparatorDistanceOut_D <= to_unsigned(min_temp, DISTANCE_WIDTH); 141 | end process comb_comparators; 142 | 143 | LabelOut_DN <= std_logic_vector(ComparatorLabelOut_D); 144 | DistanceOut_DN <= std_logic_vector(ComparatorDistanceOut_D); 145 | 146 | ----------------------------------------------------------------------------- 147 | -- Output Signals 148 | ----------------------------------------------------------------------------- 149 | LabelOut_DO <= LabelOut_DP; 150 | DistanceOut_DO <= DistanceOut_DP; 151 | 152 | ----------------------------------------------------------------------------- 153 | ----------------------------------------------------------------------------- 154 | -- CONTROLLER 155 | ----------------------------------------------------------------------------- 156 | ----------------------------------------------------------------------------- 157 | -- Controller Support Circuits 158 | ----------------------------------------------------------------------------- 159 | -- Label Identification 160 | gen_label_identification : for i in 0 to CLASSES-1 generate 161 | IdentifyLabel_S(i) <= '1' when LabelIn_DI = std_logic_vector(to_unsigned(i, LABEL_WIDTH)) 162 | else '0'; 163 | end generate gen_label_identification; 164 | 165 | -- Shift Counter Comparison 166 | ShiftComplete_S <= nor(ShiftCntr_SP); 167 | 168 | -- Shift Counter 169 | ShiftCntr_SN <= ShiftCntr_SP - 1; 170 | 171 | ----------------------------------------------------------------------------- 172 | -- Finite State Machine 173 | ----------------------------------------------------------------------------- 174 | comb_fsm : process (FSM_SP, IdentifyLabel_S, ModeIn_SI, ReadyIn_SI, 175 | ShiftComplete_S, ValidIn_SI) is 176 | begin -- process comb_fsm 177 | -- Default Assignments 178 | FSM_SN <= idle; 179 | 180 | ReadyOut_SO <= '0'; 181 | ValidOut_SO <= '0'; 182 | 183 | OutputBuffersEN_S <= '0'; 184 | TrainedMemoryEN_S <= (others => '0'); 185 | QueryHypervectorEN_S <= '0'; 186 | DistanceCntrsEN_S <= '0'; 187 | DistanceCntrsCLR_S <= '0'; 188 | ShiftCntrEN_S <= '0'; 189 | ShiftCntrCLR_S <= '0'; 190 | RotateMemories_S <= '0'; 191 | 192 | -- Trainsitions and Output 193 | case FSM_SP is 194 | when idle => 195 | ReadyOut_SO <= '1'; 196 | if ValidIn_SI = '0' then 197 | FSM_SN <= idle; 198 | else 199 | if ModeIn_SI = mode_predict then 200 | FSM_SN <= data_received; 201 | QueryHypervectorEN_S <= '1'; 202 | else 203 | FSM_SN <= idle; 204 | TrainedMemoryEN_S <= IdentifyLabel_S; 205 | end if; 206 | end if; 207 | when data_received => 208 | if ShiftComplete_S = '0' then 209 | FSM_SN <= data_received; 210 | TrainedMemoryEN_S <= (others => '1'); 211 | QueryHypervectorEN_S <= '1'; 212 | DistanceCntrsEN_S <= '1'; 213 | ShiftCntrEN_S <= '1'; 214 | RotateMemories_S <= '1'; 215 | else 216 | FSM_SN <= output_stable; 217 | OutputBuffersEN_S <= '1'; 218 | DistanceCntrsCLR_S <= '1'; 219 | ShiftCntrCLR_S <= '1'; 220 | end if; 221 | when output_stable => 222 | FSM_SN <= idle when ReadyIn_SI = '1' else output_stable; 223 | ValidOut_SO <= '1'; 224 | end case; 225 | 226 | end process comb_fsm; 227 | 228 | ----------------------------------------------------------------------------- 229 | ----------------------------------------------------------------------------- 230 | -- MEMORIES 231 | ----------------------------------------------------------------------------- 232 | ----------------------------------------------------------------------------- 233 | -- Output Buffers 234 | ----------------------------------------------------------------------------- 235 | seq_output_buffers : process (Clk_CI) 236 | begin -- process seq_OutputBuffers 237 | if (rising_edge(Clk_CI)) then -- rising clock edge 238 | if Reset_RI = '1' then 239 | LabelOut_DP <= (others => '0'); 240 | DistanceOut_DP <= (others => '0'); 241 | elsif OutputBuffersEN_S = '1' then 242 | LabelOut_DP <= LabelOut_DN; 243 | DistanceOut_DP <= DistanceOut_DN; 244 | end if; 245 | end if; 246 | end process seq_output_buffers; 247 | 248 | ----------------------------------------------------------------------------- 249 | -- Data Registers 250 | ----------------------------------------------------------------------------- 251 | -- Trained Memory 252 | gen_seq_trained_memory : for i in 0 to CLASSES-1 generate 253 | seq_trained_memory : process (Clk_CI) 254 | begin -- process seq_trained_memory 255 | if (rising_edge(Clk_CI)) then -- rising clock edge 256 | if Reset_RI = '1' then 257 | TrainedMemory_DP(i) <= (others => '0'); 258 | elsif TrainedMemoryEN_S(i) = '1' then 259 | TrainedMemory_DP(i) <= TrainedMemory_DN(i); 260 | end if; 261 | end if; 262 | end process seq_trained_memory; 263 | end generate gen_seq_trained_memory; 264 | 265 | -- Query Hypervector 266 | seq_query_hypervector : process (Clk_CI) 267 | begin -- process seq_query_hypervector 268 | if (rising_edge(Clk_CI)) then -- rising clock edge 269 | if Reset_RI = '1' then 270 | QueryHypervector_DP <= (others => '0'); 271 | elsif QueryHypervectorEN_S = '1' then 272 | QueryHypervector_DP <= QueryHypervector_DN; 273 | end if; 274 | end if; 275 | end process seq_query_hypervector; 276 | 277 | -- Distance Counters 278 | gen_seq_distance_counters : for i in 0 to CLASSES-1 generate 279 | seq_distance_counters : process (Clk_CI) 280 | begin -- process seq_distance_counters 281 | if (rising_edge(Clk_CI)) then -- rising clock edge 282 | if (Reset_RI or DistanceCntrsCLR_S) = '1' then 283 | DistanceCntrs_DP(i) <= (others => '0'); 284 | elsif (DistanceCntrsEN_S and DistanceCntrsSEN_S(i)) = '1' then 285 | DistanceCntrs_DP(i) <= DistanceCntrs_DN(i); 286 | end if; 287 | end if; 288 | end process seq_distance_counters; 289 | end generate gen_seq_distance_counters; 290 | 291 | ----------------------------------------------------------------------------- 292 | -- Control Registers 293 | ----------------------------------------------------------------------------- 294 | -- Shift Counter 295 | seq_shift_cntr : process (Clk_CI) 296 | begin -- process seq_shift_cntr 297 | if (rising_edge(Clk_CI)) then -- rising clock edge 298 | if (Reset_RI or ShiftCntrCLR_S) = '1' then 299 | ShiftCntr_SP <= to_unsigned(HV_DIMENSION, SHIFT_CNTR_WIDTH); -- TODO: make sure this is the correct number to load 300 | elsif ShiftCntrEN_S = '1' then 301 | ShiftCntr_SP <= ShiftCntr_SN; 302 | end if; 303 | end if; 304 | end process seq_shift_cntr; 305 | 306 | -- Finite State Machine 307 | seq_fsm : process (Clk_CI) 308 | begin -- process seq_fsm 309 | if (rising_edge(Clk_CI)) then -- rising clock edge 310 | if Reset_RI = '1' then 311 | FSM_SP <= idle; 312 | else 313 | FSM_SP <= FSM_SN; 314 | end if; 315 | end if; 316 | end process seq_fsm; 317 | 318 | end bs; 319 | -------------------------------------------------------------------------------- /vhdl/source/associative_memory/associative_memory_cmb_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Associative Memory Optimised 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : associative_memory_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the associative memory 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | 36 | ------------------------------------------------------------------------------- 37 | 38 | architecture cmb of associative_memory is 39 | 40 | ----------------------------------------------------------------------------- 41 | -- Signals 42 | ----------------------------------------------------------------------------- 43 | -- Output Buffers 44 | signal LabelOut_DP, LabelOut_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 45 | signal DistanceOut_DP, DistanceOut_DN : std_logic_vector(DISTANCE_WIDTH-1 downto 0); 46 | 47 | -- Data Registers 48 | signal TrainedMemory_DP, TrainedMemory_DN : hypervector_array(0 to CLASSES-1)(0 to HV_DIMENSION-1); 49 | signal QueryHypervector_DP, QueryHypervector_DN : Hypervector(0 to HV_DIMENSION-1); 50 | 51 | -- Control Registers 52 | type fsm_states is (idle, distance_calculated, output_stable); 53 | signal FSM_SP, FSM_SN : fsm_states; 54 | 55 | -- Datapath Signals 56 | signal SimilarityOut_D : std_logic_vector_array(0 to CLASSES-1)(0 to HV_DIMENSION-1); 57 | signal AdderOut_D : unsigned_array(0 to CLASSES-1)(DISTANCE_WIDTH-1 downto 0); 58 | 59 | -- Datapath Self-Control Signals 60 | 61 | -- Status Signals 62 | signal IdentifyLabel_S : std_logic_vector(0 to CLASSES-1); 63 | 64 | -- Control Signals 65 | signal OutputBuffersEN_S : std_logic; 66 | signal TrainedMemoryEN_S : std_logic_vector(0 to CLASSES-1); 67 | signal QueryHypervectorEN_S : std_logic; 68 | 69 | begin 70 | 71 | ----------------------------------------------------------------------------- 72 | ----------------------------------------------------------------------------- 73 | -- DATAPATH 74 | ----------------------------------------------------------------------------- 75 | ----------------------------------------------------------------------------- 76 | -- Input Signals 77 | ----------------------------------------------------------------------------- 78 | -- Trained Hypervector Memory 79 | gen_asgn_trained_memory1 : for i in 0 to CLASSES-1 generate 80 | TrainedMemory_DN(i) <= HypervectorIn_DI; 81 | end generate gen_asgn_trained_memory1; 82 | 83 | -- Query Hypervector Memory 84 | QueryHypervector_DN <= HypervectorIn_DI; 85 | 86 | ----------------------------------------------------------------------------- 87 | -- Distance Calculation 88 | ----------------------------------------------------------------------------- 89 | -- Similarity 90 | gen_similarity : for i in 0 to CLASSES-1 generate 91 | SimilarityOut_D(i) <= TrainedMemory_DP(i) xor QueryHypervector_DP; 92 | end generate gen_similarity; 93 | 94 | -- Adders 95 | gen_adders : for i in 0 to CLASSES-1 generate 96 | comb_adders : process (SimilarityOut_D) 97 | variable sum : integer := 0; 98 | begin -- process comb_adders 99 | sum := 0; 100 | for j in 0 to HV_DIMENSION-1 loop 101 | sum := sum + logic_to_integer(SimilarityOut_D(i)(j)); 102 | end loop; -- j 103 | AdderOut_D(i) <= to_unsigned(sum, DISTANCE_WIDTH); 104 | end process comb_adders; 105 | end generate gen_adders; 106 | 107 | ----------------------------------------------------------------------------- 108 | -- Comparison 109 | ----------------------------------------------------------------------------- 110 | comb_comparators : process (AdderOut_D) 111 | variable min_temp : integer; 112 | variable label_temp : integer; 113 | begin -- process comb_comparators 114 | min_temp := to_integer(AdderOut_D(0)); 115 | label_temp := 0; 116 | for i in 1 to CLASSES-1 loop 117 | if to_integer(AdderOut_D(i)) < min_temp then 118 | min_temp := to_integer(AdderOut_D(i)); 119 | label_temp := i; 120 | end if; 121 | end loop; -- i 122 | LabelOut_DN <= std_logic_vector(to_unsigned(label_temp, LABEL_WIDTH)); 123 | DistanceOut_DN <= std_logic_vector(to_unsigned(min_temp, DISTANCE_WIDTH)); 124 | end process comb_comparators; 125 | 126 | ----------------------------------------------------------------------------- 127 | -- Output Signals 128 | ----------------------------------------------------------------------------- 129 | LabelOut_DO <= LabelOut_DP; 130 | DistanceOut_DO <= DistanceOut_DP; 131 | 132 | ----------------------------------------------------------------------------- 133 | ----------------------------------------------------------------------------- 134 | -- CONTROLLER 135 | ----------------------------------------------------------------------------- 136 | ----------------------------------------------------------------------------- 137 | -- Controller Support Circuits 138 | ----------------------------------------------------------------------------- 139 | -- Label Identification 140 | gen_label_identification : for i in 0 to CLASSES-1 generate 141 | IdentifyLabel_S(i) <= '1' when LabelIn_DI = std_logic_vector(to_unsigned(i, LABEL_WIDTH)) 142 | else '0'; 143 | end generate gen_label_identification; 144 | 145 | ----------------------------------------------------------------------------- 146 | -- Finite State Machine 147 | ----------------------------------------------------------------------------- 148 | -- TODO: controller logic 149 | comb_fsm : process (FSM_SP, IdentifyLabel_S, ModeIn_SI, ReadyIn_SI, 150 | ValidIn_SI) is 151 | begin -- process comb_fsm 152 | -- Default Assignments 153 | FSM_SN <= idle; 154 | 155 | ReadyOut_SO <= '0'; 156 | ValidOut_SO <= '0'; 157 | 158 | OutputBuffersEN_S <= '0'; 159 | TrainedMemoryEN_S <= (others => '0'); 160 | QueryHypervectorEN_S <= '0'; 161 | 162 | -- Trainsitions and Output 163 | case FSM_SP is 164 | when idle => 165 | ReadyOut_SO <= '1'; 166 | if ValidIn_SI = '0' then 167 | FSM_SN <= idle; 168 | else 169 | if ModeIn_SI = mode_train then 170 | FSM_SN <= idle; 171 | TrainedMemoryEN_S <= IdentifyLabel_S; 172 | else 173 | FSM_SN <= distance_calculated; 174 | QueryHypervectorEN_S <= '1'; 175 | end if; 176 | end if; 177 | when distance_calculated => 178 | FSM_SN <= output_stable; 179 | OutputBuffersEN_S <= '1'; 180 | when output_stable => 181 | FSM_SN <= output_stable when ReadyIn_SI = '0' else idle; 182 | ValidOut_SO <= '1'; 183 | end case; 184 | 185 | end process comb_fsm; 186 | 187 | ----------------------------------------------------------------------------- 188 | ----------------------------------------------------------------------------- 189 | -- MEMORIES 190 | ----------------------------------------------------------------------------- 191 | ----------------------------------------------------------------------------- 192 | -- Output Buffers 193 | ----------------------------------------------------------------------------- 194 | seq_output_buffers : process (Clk_CI) 195 | begin -- process seq_OutputBuffers 196 | if (rising_edge(Clk_CI)) then -- rising clock edge 197 | if Reset_RI = '1' then 198 | LabelOut_DP <= (others => '0'); 199 | DistanceOut_DP <= (others => '0'); 200 | elsif OutputBuffersEN_S = '1' then 201 | LabelOut_DP <= LabelOut_DN; 202 | DistanceOut_DP <= DistanceOut_DN; 203 | end if; 204 | end if; 205 | end process seq_output_buffers; 206 | 207 | ----------------------------------------------------------------------------- 208 | -- Data Registers 209 | ----------------------------------------------------------------------------- 210 | -- Trained Memory 211 | gen_seq_trained_memory : for i in 0 to CLASSES-1 generate 212 | seq_trained_memory : process (Clk_CI) 213 | begin -- process seq_trained_memory 214 | if (rising_edge(Clk_CI)) then -- rising clock edge 215 | if Reset_RI = '1' then 216 | TrainedMemory_DP(i) <= (others => '0'); 217 | elsif TrainedMemoryEN_S(i) = '1' then 218 | TrainedMemory_DP(i) <= TrainedMemory_DN(i); 219 | end if; 220 | end if; 221 | end process seq_trained_memory; 222 | end generate gen_seq_trained_memory; 223 | 224 | -- Query Hypervector 225 | seq_query_hypervector : process (Clk_CI) 226 | begin -- process seq_query_hypervector 227 | if (rising_edge(Clk_CI)) then -- rising clock edge 228 | if Reset_RI = '1' then 229 | QueryHypervector_DP <= (others => '0'); 230 | elsif QueryHypervectorEN_S = '1' then 231 | QueryHypervector_DP <= QueryHypervector_DN; 232 | end if; 233 | end if; 234 | end process seq_query_hypervector; 235 | 236 | ----------------------------------------------------------------------------- 237 | -- Control Registers 238 | ----------------------------------------------------------------------------- 239 | -- Finite State Machine 240 | seq_fsm : process (Clk_CI) 241 | begin -- process seq_fsm 242 | if (rising_edge(Clk_CI)) then -- rising clock edge 243 | if Reset_RI = '1' then 244 | FSM_SP <= idle; 245 | else 246 | FSM_SP <= FSM_SN; 247 | end if; 248 | end if; 249 | end process seq_fsm; 250 | 251 | end cmb; 252 | -------------------------------------------------------------------------------- /vhdl/source/associative_memory/associative_memory_ent.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Associative Memory 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : associative_memory_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the associative memory 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | 36 | ------------------------------------------------------------------------------- 37 | 38 | entity associative_memory is 39 | port ( 40 | -- Global Ports 41 | Clk_CI : in std_logic; 42 | Reset_RI : in std_logic; 43 | 44 | -- Handshake Ports 45 | ValidIn_SI : in std_logic; 46 | ReadyOut_SO : out std_logic; 47 | ReadyIn_SI : in std_logic; 48 | ValidOut_SO : out std_logic; 49 | 50 | -- Input Ports 51 | ModeIn_SI : in std_logic; 52 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 53 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 54 | 55 | -- Output Ports 56 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 57 | DistanceOut_DO : out std_logic_vector(DISTANCE_WIDTH-1 downto 0) 58 | ); 59 | end associative_memory; 60 | -------------------------------------------------------------------------------- /vhdl/source/associative_memory/associative_memory_vs_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Associative Memory Optimised 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : associative_memory_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the associative memory 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | 36 | ------------------------------------------------------------------------------- 37 | 38 | architecture vs of associative_memory is 39 | 40 | ----------------------------------------------------------------------------- 41 | -- Constants 42 | ----------------------------------------------------------------------------- 43 | constant SHIFT_CNTR_WIDTH : integer := num2bits(CLASSES+1); 44 | 45 | ----------------------------------------------------------------------------- 46 | -- Signals 47 | ----------------------------------------------------------------------------- 48 | -- Output Buffers 49 | signal LabelOut_DP, LabelOut_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 50 | signal DistanceOut_DP, DistanceOut_DN : std_logic_vector(DISTANCE_WIDTH-1 downto 0); 51 | 52 | -- Data Registers 53 | signal TrainedMemory_DP, TrainedMemory_DN : hypervector_array(0 to CLASSES-1)(0 to HV_DIMENSION-1); 54 | signal LabelMemory_DP, LabelMemory_DN : std_logic_vector_array(0 to CLASSES-1)(LABEL_WIDTH-1 downto 0); 55 | signal QueryHypervector_DP, QueryHypervector_DN : hypervector(0 to HV_DIMENSION-1); 56 | signal CompDistance_DP, CompDistance_DN : unsigned(DISTANCE_WIDTH-1 downto 0); 57 | signal CompLabel_DP, CompLabel_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 58 | 59 | -- Control Registers 60 | type fsm_states is (idle, find_min_dist, output_stable); 61 | signal FSM_SP, FSM_SN : fsm_states; 62 | signal ShiftCntr_SP, ShiftCntr_SN : unsigned(SHIFT_CNTR_WIDTH-1 downto 0); 63 | 64 | -- Datapath Signals 65 | signal SimilarityOut_D : std_logic_vector(0 to HV_DIMENSION-1); 66 | signal AdderOut_D : unsigned(DISTANCE_WIDTH-1 downto 0); 67 | 68 | -- Datapath Self-Control Signals 69 | signal CompRegisterSEN_S : std_logic; 70 | 71 | -- Status Signals 72 | signal ShiftComplete_S : std_logic; 73 | 74 | -- Control Signals 75 | signal OutputBuffersEN_S : std_logic; 76 | signal ShiftMemoryEN_S : std_logic; 77 | signal QueryHypervectorEN_S : std_logic; 78 | signal CompRegisterEN_S : std_logic; 79 | signal CompRegisterCLR_S : std_logic; 80 | signal ShiftCntrEN_S : std_logic; 81 | signal ShiftCntrCLR_S : std_logic; 82 | signal RotateMemories_S : std_logic; 83 | 84 | begin 85 | 86 | ----------------------------------------------------------------------------- 87 | ----------------------------------------------------------------------------- 88 | -- DATAPATH 89 | ----------------------------------------------------------------------------- 90 | ----------------------------------------------------------------------------- 91 | -- Input Signals 92 | ----------------------------------------------------------------------------- 93 | -- Trained & Label Memory 94 | TrainedMemory_DN(0) <= HypervectorIn_DI when RotateMemories_S = '0' else 95 | TrainedMemory_DP(TrainedMemory_DP'high); 96 | LabelMemory_DN(0) <= LabelIn_DI when RotateMemories_S = '0' else 97 | LabelMemory_DP(LabelMemory_DP'high); 98 | 99 | -- Query Hypervector Memory 100 | QueryHypervector_DN <= HypervectorIn_DI; 101 | 102 | ----------------------------------------------------------------------------- 103 | -- Trained & Label Memory Shift Register 104 | ----------------------------------------------------------------------------- 105 | -- Shift Register 106 | gen_asgn_trained_memory : for i in 1 to CLASSES-1 generate 107 | TrainedMemory_DN(i) <= TrainedMemory_DP(i-1); 108 | LabelMemory_DN(i) <= LabelMemory_DP(i-1); 109 | end generate gen_asgn_trained_memory; 110 | 111 | ----------------------------------------------------------------------------- 112 | -- Distance Calculation 113 | ----------------------------------------------------------------------------- 114 | -- Similarity 115 | SimilarityOut_D <= TrainedMemory_DP(TrainedMemory_DP'high) xor QueryHypervector_DP; 116 | 117 | -- Adders 118 | comb_adders : process (SimilarityOut_D) is 119 | variable sum : integer := 0; 120 | begin -- process comb_adders 121 | sum := 0; 122 | for i in 0 to HV_DIMENSION-1 loop 123 | sum := sum + logic_to_integer(SimilarityOut_D(i)); 124 | end loop; -- i 125 | AdderOut_D <= to_unsigned(sum, DISTANCE_WIDTH); 126 | end process comb_adders; 127 | 128 | ----------------------------------------------------------------------------- 129 | -- Comparison 130 | ----------------------------------------------------------------------------- 131 | -- Comparator Registers 132 | CompLabel_DN <= LabelMemory_DP(LabelMemory_DP'high); 133 | CompDistance_DN <= AdderOut_D; 134 | 135 | -- Comparison 136 | CompRegisterSEN_S <= CompDistance_DN ?< CompDistance_DP; 137 | 138 | -- Output Buffers 139 | LabelOut_DN <= std_logic_vector(CompLabel_DP); 140 | DistanceOut_DN <= std_logic_vector(CompDistance_DP); 141 | 142 | ----------------------------------------------------------------------------- 143 | -- Output Signals 144 | ----------------------------------------------------------------------------- 145 | LabelOut_DO <= LabelOut_DP; 146 | DistanceOut_DO <= DistanceOut_DP; 147 | 148 | ----------------------------------------------------------------------------- 149 | ----------------------------------------------------------------------------- 150 | -- CONTROLLER 151 | ----------------------------------------------------------------------------- 152 | ----------------------------------------------------------------------------- 153 | -- Controller Support Circuits 154 | ----------------------------------------------------------------------------- 155 | -- Shift Counter 156 | ShiftCntr_SN <= ShiftCntr_SP - 1; 157 | 158 | -- Shift Counter Comparison 159 | ShiftComplete_S <= nor(ShiftCntr_SP); 160 | 161 | ----------------------------------------------------------------------------- 162 | -- Finite State Machine 163 | ----------------------------------------------------------------------------- 164 | comb_fsm : process (FSM_SP, ModeIn_SI, ReadyIn_SI, ShiftComplete_S, 165 | ValidIn_SI) is 166 | begin -- process comb_fsm 167 | -- Default Assignments 168 | FSM_SN <= idle; 169 | 170 | ReadyOut_SO <= '0'; 171 | ValidOut_SO <= '0'; 172 | 173 | OutputBuffersEN_S <= '0'; 174 | ShiftMemoryEN_S <= '0'; 175 | QueryHypervectorEN_S <= '0'; 176 | CompRegisterEN_S <= '0'; 177 | CompRegisterCLR_S <= '0'; 178 | ShiftCntrEN_S <= '0'; 179 | ShiftCntrCLR_S <= '0'; 180 | RotateMemories_S <= '0'; 181 | 182 | -- Trainsitions and Output 183 | case FSM_SP is 184 | when idle => 185 | ReadyOut_SO <= '1'; 186 | if ValidIn_SI = '0' then 187 | FSM_SN <= idle; 188 | else 189 | FSM_SN <= find_min_dist when ModeIn_SI = mode_predict else idle; 190 | ShiftMemoryEN_S <= '1' when ModeIn_SI = mode_train else '0'; 191 | QueryHypervectorEN_S <= '1' when ModeIn_SI = mode_predict else '0'; 192 | end if; 193 | when find_min_dist => 194 | if ShiftComplete_S = '0' then 195 | FSM_SN <= find_min_dist; 196 | ShiftMemoryEN_S <= '1'; 197 | CompRegisterEN_S <= '1'; 198 | ShiftCntrEN_S <= '1'; 199 | RotateMemories_S <= '1'; 200 | else 201 | FSM_SN <= output_stable; 202 | OutputBuffersEN_S <= '1'; 203 | CompRegisterCLR_S <= '1'; 204 | ShiftCntrCLR_S <= '1'; 205 | end if; 206 | when output_stable => 207 | FSM_SN <= idle when ReadyIn_SI = '1' else output_stable; 208 | ValidOut_SO <= '1'; 209 | end case; 210 | 211 | end process comb_fsm; 212 | 213 | ----------------------------------------------------------------------------- 214 | ----------------------------------------------------------------------------- 215 | -- MEMORIES 216 | ----------------------------------------------------------------------------- 217 | ----------------------------------------------------------------------------- 218 | -- Output Buffers 219 | ----------------------------------------------------------------------------- 220 | seq_output_buffers : process (Clk_CI) 221 | begin -- process seq_OutputBuffers 222 | if (rising_edge(Clk_CI)) then -- rising clock edge 223 | if Reset_RI = '1' then 224 | LabelOut_DP <= (others => '0'); 225 | DistanceOut_DP <= (others => '0'); 226 | elsif OutputBuffersEN_S = '1' then 227 | LabelOut_DP <= LabelOut_DN; 228 | DistanceOut_DP <= DistanceOut_DN; 229 | end if; 230 | end if; 231 | end process seq_output_buffers; 232 | 233 | ----------------------------------------------------------------------------- 234 | -- Data Registers 235 | ----------------------------------------------------------------------------- 236 | -- Trained & Label Memory 237 | seq_trained_label_memory : process (Clk_CI) 238 | begin -- process seq_trained_label_memory 239 | if (rising_edge(Clk_CI)) then -- rising clock edge 240 | if Reset_RI = '1' then 241 | TrainedMemory_DP <= (others => (others => '0')); 242 | LabelMemory_DP <= (others => (others => '0')); 243 | elsif ShiftMemoryEN_S = '1' then 244 | TrainedMemory_DP <= TrainedMemory_DN; 245 | LabelMemory_DP <= LabelMemory_DN; 246 | end if; 247 | end if; 248 | end process seq_trained_label_memory; 249 | 250 | -- Query Hypervector 251 | seq_query_hypervector : process (Clk_CI) 252 | begin -- process seq_query_hypervector 253 | if (rising_edge(Clk_CI)) then -- rising clock edge 254 | if Reset_RI = '1' then 255 | QueryHypervector_DP <= (others => '0'); 256 | elsif QueryHypervectorEN_S = '1' then 257 | QueryHypervector_DP <= QueryHypervector_DN; 258 | end if; 259 | end if; 260 | end process seq_query_hypervector; 261 | 262 | -- Comparator Registers 263 | seq_comp_registers : process (Clk_CI) 264 | begin -- process seq_comp_registers 265 | if (rising_edge(Clk_CI)) then -- rising clock edge 266 | if (Reset_RI or CompRegisterCLR_S) = '1' then 267 | CompDistance_DP <= (others => '1'); 268 | CompLabel_DP <= (others => '0'); 269 | elsif (CompRegisterEN_S and CompRegisterSEN_S) = '1' then 270 | CompDistance_DP <= CompDistance_DN; 271 | CompLabel_DP <= CompLabel_DN; 272 | end if; 273 | end if; 274 | end process seq_comp_registers; 275 | 276 | ----------------------------------------------------------------------------- 277 | -- Control Registers 278 | ----------------------------------------------------------------------------- 279 | -- Shift Counter 280 | seq_shift_cntr : process (Clk_CI) 281 | begin -- process seq_shift_cntr 282 | if (rising_edge(Clk_CI)) then -- rising clock edge 283 | if (Reset_RI or ShiftCntrCLR_S) = '1' then 284 | ShiftCntr_SP <= to_unsigned(CLASSES, SHIFT_CNTR_WIDTH); 285 | elsif ShiftCntrEN_S = '1' then 286 | ShiftCntr_SP <= ShiftCntr_SN; 287 | end if; 288 | end if; 289 | end process seq_shift_cntr; 290 | 291 | -- Finite State Machine 292 | seq_fsm : process (Clk_CI) 293 | begin -- process seq_fsm 294 | if (rising_edge(Clk_CI)) then -- rising clock edge 295 | if Reset_RI = '1' then 296 | FSM_SP <= idle; 297 | else 298 | FSM_SP <= FSM_SN; 299 | end if; 300 | end if; 301 | end process seq_fsm; 302 | 303 | end vs; 304 | -------------------------------------------------------------------------------- /vhdl/source/hdc_ent_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Hyperdimensional Computing Classifier Entity 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : hdc_ent.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Top level entity of the HDC classifier. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | 36 | ------------------------------------------------------------------------------- 37 | 38 | entity hdc is 39 | port ( 40 | -- Global Ports 41 | Clk_CI : in std_logic; 42 | Reset_RI : in std_logic; 43 | 44 | -- Handshake Ports 45 | ValidIn_SI : in std_logic; 46 | ReadyOut_SO : out std_logic; 47 | ReadyIn_SI : in std_logic; 48 | ValidOut_SO : out std_logic; 49 | 50 | -- Input Ports 51 | ModeIn_SI : in std_logic; 52 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 53 | ChannelsIn_DI : in std_logic_vector_array(0 to INPUT_CHANNELS-1)(CHANNEL_WIDTH-1 downto 0); 54 | 55 | -- Output Ports 56 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 57 | DistanceOut_DO : out std_logic_vector(DISTANCE_WIDTH-1 downto 0) 58 | ); 59 | end hdc; 60 | 61 | ------------------------------------------------------------------------------- 62 | 63 | architecture top of hdc is 64 | 65 | ----------------------------------------------------------------------------- 66 | -- Signals 67 | ----------------------------------------------------------------------------- 68 | -- Spatial Encoder 69 | signal ModeOutS_S : std_logic; 70 | signal LabelOutS_D : std_logic_vector(LABEL_WIDTH-1 downto 0); 71 | signal HypervectorOutS_D : hypervector(0 to HV_DIMENSION-1); 72 | 73 | -- Handshake 74 | signal ValidST_S : std_logic; 75 | signal ReadyST_S : std_logic; 76 | 77 | -- Temporal Encoder 78 | signal ModeOutT_S : std_logic; 79 | signal LabelOutT_D : std_logic_vector(LABEL_WIDTH-1 downto 0); 80 | signal HypervectorOutT_D : hypervector(0 to HV_DIMENSION-1); 81 | 82 | -- Handshake 83 | signal ValidTA_S : std_logic; 84 | signal ReadyTA_S : std_logic; 85 | 86 | ----------------------------------------------------------------------------- 87 | -- Components 88 | ----------------------------------------------------------------------------- 89 | -- Spatial Encoder 90 | component spatial_encoder 91 | port ( 92 | Clk_CI : in std_logic; 93 | Reset_RI : in std_logic; 94 | ValidIn_SI : in std_logic; 95 | ReadyOut_SO : out std_logic; 96 | ReadyIn_SI : in std_logic; 97 | ValidOut_SO : out std_logic; 98 | ModeIn_SI : in std_logic; 99 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 100 | ChannelsIn_DI : in std_logic_vector_array(0 to INPUT_CHANNELS-1)(CHANNEL_WIDTH-1 downto 0); 101 | ModeOut_SO : out std_logic; 102 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 103 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1)); 104 | end component; 105 | 106 | for all : spatial_encoder use entity 107 | work.spatial_encoder(lut); 108 | -- work.spatial_encoder(ca); 109 | -- work.spatial_encoder(man); 110 | 111 | -- Temporal Encoder 112 | component temporal_encoder 113 | port ( 114 | Clk_CI : in std_logic; 115 | Reset_RI : in std_logic; 116 | ValidIn_SI : in std_logic; 117 | ReadyOut_SO : out std_logic; 118 | ReadyIn_SI : in std_logic; 119 | ValidOut_SO : out std_logic; 120 | ModeIn_SI : in std_logic; 121 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 122 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 123 | ModeOut_SO : out std_logic; 124 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 125 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1)); 126 | end component; 127 | 128 | for all : temporal_encoder use entity 129 | work.temporal_encoder(b2b); 130 | -- work.temporal_encoder(bc); 131 | 132 | -- Associative Memory 133 | component associative_memory 134 | port ( 135 | Clk_CI : in std_logic; 136 | Reset_RI : in std_logic; 137 | ValidIn_SI : in std_logic; 138 | ReadyOut_SO : out std_logic; 139 | ReadyIn_SI : in std_logic; 140 | ValidOut_SO : out std_logic; 141 | ModeIn_SI : in std_logic; 142 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 143 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 144 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 145 | DistanceOut_DO : out std_logic_vector(DISTANCE_WIDTH-1 downto 0)); 146 | end component; 147 | 148 | for all : associative_memory use entity 149 | work.associative_memory(cmb); 150 | -- work.associative_memory(vs); 151 | -- work.associative_memory(bs); 152 | 153 | begin -- top 154 | 155 | ----------------------------------------------------------------------------- 156 | -- Instantiations 157 | ----------------------------------------------------------------------------- 158 | -- Spatial Encoder 159 | i_spatial_encoder_1 : spatial_encoder 160 | port map ( 161 | Clk_CI => Clk_CI, 162 | Reset_RI => Reset_RI, 163 | ValidIn_SI => ValidIn_SI, 164 | ReadyOut_SO => ReadyOut_SO, 165 | ReadyIn_SI => ReadyST_S, 166 | ValidOut_SO => ValidST_S, 167 | ModeIn_SI => ModeIn_SI, 168 | LabelIn_DI => LabelIn_DI, 169 | ChannelsIn_DI => ChannelsIn_DI, 170 | ModeOut_SO => ModeOutS_S, 171 | LabelOut_DO => LabelOutS_D, 172 | HypervectorOut_DO => HypervectorOutS_D); 173 | 174 | -- Temporal Encoder 175 | i_temporal_encoder_1 : temporal_encoder 176 | port map ( 177 | Clk_CI => Clk_CI, 178 | Reset_RI => Reset_RI, 179 | ValidIn_SI => ValidST_S, 180 | ReadyOut_SO => ReadyST_S, 181 | ReadyIn_SI => ReadyTA_S, 182 | ValidOut_SO => ValidTA_S, 183 | ModeIn_SI => ModeOutS_S, 184 | LabelIn_DI => LabelOutS_D, 185 | HypervectorIn_DI => HypervectorOutS_D, 186 | ModeOut_SO => ModeOutT_S, 187 | LabelOut_DO => LabelOutT_D, 188 | HypervectorOut_DO => HypervectorOutT_D); 189 | 190 | -- Associative memory 191 | i_associative_memory_1 : associative_memory 192 | port map ( 193 | Clk_CI => Clk_CI, 194 | Reset_RI => Reset_RI, 195 | ValidIn_SI => ValidTA_S, 196 | ReadyOut_SO => ReadyTA_S, 197 | ReadyIn_SI => ReadyIn_SI, 198 | ValidOut_SO => ValidOut_SO, 199 | ModeIn_SI => ModeOutT_S, 200 | LabelIn_DI => LabelOutT_D, 201 | HypervectorIn_DI => HypervectorOutT_D, 202 | LabelOut_DO => LabelOut_DO, 203 | DistanceOut_DO => DistanceOut_DO); 204 | 205 | end top; 206 | -------------------------------------------------------------------------------- /vhdl/source/hdc_pkg.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------ 12 | -- Title : Hyperdimensional Computing Package 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : hdc_pkg.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-01-02 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Provides parameters and constants required for hyperdimensional 23 | -- computing classifiers. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2018 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use ieee.math_real.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | package hdc_pkg is 40 | 41 | ----------------------------------------------------------------------------- 42 | -- Data Type Declarations 43 | ----------------------------------------------------------------------------- 44 | type std_logic_vector_array is array (integer range <>) of std_logic_vector; 45 | type unsigned_array is array (integer range <>) of unsigned; 46 | type signed_array is array (integer range <>) of signed; 47 | 48 | subtype hypervector is std_logic_vector; 49 | subtype hypervector_arith is unsigned; 50 | subtype hypervector_array is std_logic_vector_array; 51 | subtype hypervector_array_arith is unsigned_array; 52 | 53 | ----------------------------------------------------------------------------- 54 | -- Function Declarations 55 | ----------------------------------------------------------------------------- 56 | function num2bits (number : integer) return integer; 57 | function logic_to_integer (logic : std_logic) return integer; 58 | 59 | ----------------------------------------------------------------------------- 60 | -- Constant Declarations 61 | ----------------------------------------------------------------------------- 62 | -- Parameters 63 | constant HV_DIMENSION : integer := 1024; 64 | constant INPUT_CHANNELS : integer := 4; 65 | constant INPUT_QUANTIZATION : integer := 21; 66 | constant NGRAM_SIZE : integer := 3; 67 | constant CLASSES : integer := 5; 68 | constant BUNDLE_CHANNELS_WIDTH : integer := 3; 69 | constant BUNDLE_NGRAMS_WIDTH : integer := 5; 70 | constant MAX_BUNDLE_CYCLES : integer := 32; 71 | constant AM_BLOCK_WIDTH : integer := 64; 72 | constant NGRAM_BUNDLER_MODE : string := "similarity"; 73 | 74 | -- Deferred Parameters 75 | constant LABEL_WIDTH : integer; 76 | constant CHANNEL_WIDTH : integer; 77 | constant DISTANCE_WIDTH : integer; 78 | constant NGRAM_WIDTH : integer; 79 | constant AM_BLOCKS : integer; 80 | 81 | -- Aliases 82 | constant mode_train : std_logic := '0'; 83 | constant mode_predict : std_logic := '1'; 84 | constant mode_store : std_logic := '0'; 85 | constant mode_shift : std_logic := '1'; 86 | constant mode_similarity : string := "similarity"; 87 | constant mode_counter : string := "counter"; 88 | 89 | end hdc_pkg; 90 | 91 | ------------------------------------------------------------------------------- 92 | 93 | package body hdc_pkg is 94 | 95 | ----------------------------------------------------------------------------- 96 | -- Function Definitions 97 | ----------------------------------------------------------------------------- 98 | function num2bits (number : integer) return integer is 99 | begin 100 | if number <= 1 then 101 | return 0; 102 | else 103 | return integer(ceil(log2(real(number)))); 104 | end if; 105 | end num2bits; 106 | 107 | function logic_to_integer (logic : std_logic) return integer is 108 | begin 109 | if logic = '1' then 110 | return 1; 111 | else 112 | return 0; 113 | end if; 114 | end logic_to_integer; 115 | 116 | ----------------------------------------------------------------------------- 117 | -- Deferred Constants 118 | ----------------------------------------------------------------------------- 119 | constant LABEL_WIDTH : integer := num2bits(CLASSES); 120 | constant CHANNEL_WIDTH : integer := num2bits(INPUT_QUANTIZATION); 121 | constant DISTANCE_WIDTH : integer := num2bits(HV_DIMENSION); 122 | constant NGRAM_WIDTH : integer := num2bits(NGRAM_SIZE); 123 | constant AM_BLOCKS : integer := HV_DIMENSION / AM_BLOCK_WIDTH; 124 | 125 | 126 | end hdc_pkg; 127 | -------------------------------------------------------------------------------- /vhdl/source/spatial_encoder/spatial_encoder_ca_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Spatial Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : spatial_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encode. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | use work.hdc_enhanced_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | architecture ca of spatial_encoder is 40 | 41 | ----------------------------------------------------------------------------- 42 | -- Constants 43 | ----------------------------------------------------------------------------- 44 | constant CYCLE_CNTR_WIDTH : integer := num2bits(INPUT_CHANNELS); 45 | constant INPUT_CHANNELS_EVEN : boolean := (INPUT_CHANNELS mod 2) = 0; 46 | 47 | ----------------------------------------------------------------------------- 48 | -- Signals 49 | ----------------------------------------------------------------------------- 50 | -- Input Buffers 51 | signal ModeIn_SP, ModeIn_SN : std_logic; 52 | signal LabelIn_DP, LabelIn_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 53 | signal ChannelsIn_DP, ChannelsIn_DN : std_logic_vector_array(0 to INPUT_CHANNELS-1)(CHANNEL_WIDTH-1 downto 0); 54 | 55 | -- Data Registers 56 | signal AdditionalFeature_DP, AdditionalFeature_DN : hypervector(0 to HV_DIMENSION-1); 57 | 58 | -- Control Registers 59 | type fsm_states is (idle, data_received, bundle_cntr_fed, channels_mapped, feature_added); 60 | signal FSM_SP, FSM_SN : fsm_states; 61 | signal CycleCntr_SP, CycleCntr_SN : unsigned(CYCLE_CNTR_WIDTH-1 downto 0); 62 | 63 | -- Datapath Signals 64 | signal SelectedChannel_D : std_logic_vector(CHANNEL_WIDTH-1 downto 0); 65 | signal ChannelNHot_D : std_logic_vector(0 to INPUT_QUANTIZATION-2); 66 | signal CIMOut_D : hypervector(0 to HV_DIMENSION-1); 67 | signal IMOut_D : hypervector(0 to HV_DIMENSION-1); 68 | signal BindChannelOut_D : hypervector(0 to HV_DIMENSION-1); 69 | signal SelectFeatureOut_D : hypervector(0 to HV_DIMENSION-1); 70 | 71 | -- Status Signals 72 | signal LastChannel_S : std_logic; 73 | 74 | -- Control Signals 75 | signal InputBuffersEN_S : std_logic; 76 | signal BundleCntrEN_S : std_logic; 77 | signal CellularAutomatonEN_S : std_logic; 78 | signal CellularAutomatonCLR_S : std_logic; 79 | signal AdditionalFeatureEN_S : std_logic; 80 | signal AdditionalFeatureCLR_S : std_logic; 81 | signal CycleCntrEN_S : std_logic; 82 | signal CycleCntrCLR_S : std_logic; 83 | 84 | signal FirstHypervector_S : std_logic; 85 | signal SelectAdditionalFeature_S : std_logic; 86 | 87 | 88 | ----------------------------------------------------------------------------- 89 | -- Components 90 | ----------------------------------------------------------------------------- 91 | component cellular_automaton is 92 | generic ( 93 | WIDTH : integer; 94 | RULE : integer; 95 | CELLULAR_AUTOMATON_SEED : std_logic_vector(0 to WIDTH-1)); 96 | port ( 97 | Clk_CI : in std_logic; 98 | Reset_RI : in std_logic; 99 | Enable_SI : in std_logic; 100 | Clear_SI : in std_logic; 101 | CellValueOut_DO : out std_logic_vector(0 to WIDTH-1)); 102 | end component cellular_automaton; 103 | 104 | component bundle_counter is 105 | generic ( 106 | WIDTH : integer); 107 | port ( 108 | Clk_CI : in std_logic; 109 | Reset_RI : in std_logic; 110 | Enable_SI : in std_logic; 111 | FirstHypervector_SI : in std_logic; 112 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 113 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1)); 114 | end component bundle_counter; 115 | 116 | begin 117 | ----------------------------------------------------------------------------- 118 | ----------------------------------------------------------------------------- 119 | -- DATAPATH 120 | ----------------------------------------------------------------------------- 121 | ----------------------------------------------------------------------------- 122 | -- Input Signals 123 | ----------------------------------------------------------------------------- 124 | ModeIn_SN <= ModeIn_SI; 125 | LabelIn_DN <= LabelIn_DI; 126 | ChannelsIn_DN <= ChannelsIn_DI; 127 | 128 | ----------------------------------------------------------------------------- 129 | -- Channel Mapping 130 | ----------------------------------------------------------------------------- 131 | SelectedChannel_D <= ChannelsIn_DP(to_integer(CycleCntr_SP)); 132 | 133 | -- N-Hot LUT 134 | ChannelNHot_D <= NHOT_LUT(to_integer(unsigned(SelectedChannel_D))); 135 | 136 | -- CIM 137 | comb_cim : process (ChannelNHot_D) 138 | begin -- process comb_cim 139 | for i in 0 to CIMOut_D'high loop 140 | CIMOut_D(i) <= CIM_SEED(i); 141 | for j in 0 to ChannelNHot_D'high loop 142 | if CIM_CONNECTIVITY_MATRIX(j)(i) = '1' then 143 | CIMOut_D(i) <= CIM_SEED(i) xor ChannelNHot_D(j); 144 | end if; 145 | end loop; -- j 146 | end loop; -- i 147 | end process comb_cim; 148 | 149 | ----------------------------------------------------------------------------- 150 | -- Channel Binding 151 | ----------------------------------------------------------------------------- 152 | -- Cellular Automaton 153 | i_cellular_automaton_1 : cellular_automaton 154 | generic map ( 155 | WIDTH => HV_DIMENSION, 156 | RULE => 30, 157 | CELLULAR_AUTOMATON_SEED => IM_SEED) 158 | port map ( 159 | Clk_CI => Clk_CI, 160 | Reset_RI => Reset_RI, 161 | Enable_SI => CellularAutomatonEN_S, 162 | Clear_SI => CellularAutomatonCLR_S, 163 | CellValueOut_DO => IMOut_D); 164 | 165 | BindChannelOut_D <= IMOut_D xor CIMOut_D; 166 | 167 | ----------------------------------------------------------------------------- 168 | -- Channel Bundling 169 | ----------------------------------------------------------------------------- 170 | gen_additional_feature : if INPUT_CHANNELS_EVEN generate 171 | AdditionalFeature_DN <= BindChannelOut_D xor AdditionalFeature_DP; 172 | SelectFeatureOut_D <= AdditionalFeature_DP when SelectAdditionalFeature_S = '1' else 173 | BindChannelOut_D; 174 | else generate 175 | SelectFeatureOut_D <= BindChannelOut_D; 176 | end generate gen_additional_feature; 177 | 178 | 179 | -- Bundling Counter 180 | i_bundle_counter_1 : bundle_counter 181 | generic map ( 182 | WIDTH => BUNDLE_CHANNELS_WIDTH) 183 | port map ( 184 | Clk_CI => Clk_CI, 185 | Reset_RI => Reset_RI, 186 | Enable_SI => BundleCntrEN_S, 187 | FirstHypervector_SI => FirstHypervector_S, 188 | HypervectorIn_DI => SelectFeatureOut_D, 189 | HypervectorOut_DO => HypervectorOut_DO); 190 | 191 | ----------------------------------------------------------------------------- 192 | -- Output Signals 193 | ----------------------------------------------------------------------------- 194 | ModeOut_SO <= ModeIn_SP; 195 | LabelOut_DO <= LabelIn_DP; 196 | 197 | ----------------------------------------------------------------------------- 198 | ----------------------------------------------------------------------------- 199 | -- CONTROLLER 200 | ----------------------------------------------------------------------------- 201 | ----------------------------------------------------------------------------- 202 | -- Controller Support Circuits 203 | ----------------------------------------------------------------------------- 204 | -- Cycle Counter 205 | CycleCntr_SN <= CycleCntr_SP+1; 206 | LastChannel_S <= '1' when to_integer(CycleCntr_SP) = INPUT_CHANNELS-1 else '0'; 207 | 208 | ----------------------------------------------------------------------------- 209 | -- Finite State Machine 210 | ----------------------------------------------------------------------------- 211 | -- There have to be two different implementations of the controller: 212 | -- - One for the case that we have an even number of channels 213 | -- - Another one for the case that we have an odd number of channels 214 | gen_comb_fsm : if INPUT_CHANNELS_EVEN generate 215 | comb_fsm : process (FSM_SP, LastChannel_S, ReadyIn_SI, ValidIn_SI) is 216 | begin -- process comb_fsm 217 | -- Default Assignments 218 | FSM_SN <= idle; 219 | 220 | ReadyOut_SO <= '0'; 221 | ValidOut_SO <= '0'; 222 | 223 | InputBuffersEN_S <= '0'; 224 | BundleCntrEN_S <= '0'; 225 | CellularAutomatonEN_S <= '0'; 226 | CellularAutomatonCLR_S <= '0'; 227 | AdditionalFeatureEN_S <= '0'; 228 | AdditionalFeatureCLR_S <= '0'; 229 | CycleCntrEN_S <= '0'; 230 | CycleCntrCLR_S <= '0'; 231 | 232 | FirstHypervector_S <= '0'; 233 | SelectAdditionalFeature_S <= '0'; 234 | 235 | -- Trainsitions and Output 236 | case FSM_SP is 237 | when idle => 238 | FSM_SN <= data_received when ValidIn_SI = '1' else idle; 239 | ReadyOut_SO <= '1'; 240 | InputBuffersEN_S <= '1' when ValidIn_SI = '1' else '0'; 241 | when data_received => 242 | FSM_SN <= bundle_cntr_fed; 243 | BundleCntrEN_S <= '1'; 244 | CellularAutomatonEN_S <= '1'; 245 | AdditionalFeatureEN_S <= '1'; 246 | CycleCntrEN_S <= '1'; 247 | FirstHypervector_S <= '1'; 248 | when bundle_cntr_fed => 249 | FSM_SN <= channels_mapped when LastChannel_S = '1' else bundle_cntr_fed; 250 | BundleCntrEN_S <= '1'; 251 | CellularAutomatonEN_S <= '1'; 252 | AdditionalFeatureEN_S <= '1' when LastChannel_S = '1' else '0'; -- erase "when ..." if additional feature should combine all channels 253 | CycleCntrEN_S <= '1'; 254 | when channels_mapped => 255 | FSM_SN <= feature_added; 256 | BundleCntrEN_S <= '1'; 257 | CellularAutomatonCLR_S <= '1'; 258 | AdditionalFeatureCLR_S <= '1'; 259 | CycleCntrCLR_S <= '1'; 260 | SelectAdditionalFeature_S <= '1'; 261 | when feature_added => 262 | FSM_SN <= idle when ReadyIn_SI = '1' else feature_added; 263 | ValidOut_SO <= '1'; 264 | end case; 265 | 266 | end process comb_fsm; 267 | ----------------------------------------------------------------------------- 268 | else generate 269 | comb_fsm : process (FSM_SP, LastChannel_S, ReadyIn_SI, ValidIn_SI) is 270 | begin -- process comb_fsm 271 | -- Default Assignments 272 | FSM_SN <= idle; 273 | 274 | ReadyOut_SO <= '0'; 275 | ValidOut_SO <= '0'; 276 | 277 | InputBuffersEN_S <= '0'; 278 | BundleCntrEN_S <= '0'; 279 | CellularAutomatonEN_S <= '0'; 280 | CellularAutomatonCLR_S <= '0'; 281 | CycleCntrEN_S <= '0'; 282 | CycleCntrCLR_S <= '0'; 283 | 284 | FirstHypervector_S <= '0'; 285 | 286 | -- Trainsitions and Output 287 | case FSM_SP is 288 | when idle => 289 | FSM_SN <= data_received when ValidIn_SI = '1' else idle; 290 | ReadyOut_SO <= '1'; 291 | InputBuffersEN_S <= '1' when ValidIn_SI = '1' else '0'; 292 | when data_received => 293 | FSM_SN <= bundle_cntr_fed; 294 | BundleCntrEN_S <= '1'; 295 | CellularAutomatonEN_S <= '1'; 296 | CycleCntrEN_S <= '1'; 297 | FirstHypervector_S <= '1'; 298 | when bundle_cntr_fed => 299 | FSM_SN <= channels_mapped when LastChannel_S = '1' else bundle_cntr_fed; 300 | BundleCntrEN_S <= '1'; 301 | if LastChannel_S = '0' then 302 | CellularAutomatonEN_S <= '1'; 303 | CycleCntrEN_S <= '1'; 304 | else 305 | CellularAutomatonCLR_S <= '1'; 306 | CycleCntrCLR_S <= '1'; 307 | end if; 308 | when channels_mapped => 309 | FSM_SN <= idle when ReadyIn_SI = '1' else channels_mapped; 310 | ValidOut_SO <= '1'; 311 | when others => 312 | null; 313 | end case; 314 | 315 | end process comb_fsm; 316 | end generate gen_comb_fsm; 317 | 318 | ----------------------------------------------------------------------------- 319 | ----------------------------------------------------------------------------- 320 | -- MEMORIES 321 | ----------------------------------------------------------------------------- 322 | ----------------------------------------------------------------------------- 323 | -- Input Buffers 324 | ----------------------------------------------------------------------------- 325 | seq_input_buffers : process (Clk_CI) 326 | begin -- process seq_InputBuffers 327 | if (rising_edge(Clk_CI)) then -- rising clock edge 328 | if Reset_RI = '1' then 329 | ModeIn_SP <= '0'; 330 | LabelIn_DP <= (others => '0'); 331 | ChannelsIn_DP <= (others => (others => '0')); 332 | elsif InputBuffersEN_S = '1' then 333 | ModeIn_SP <= ModeIn_SN; 334 | LabelIn_DP <= LabelIn_DN; 335 | ChannelsIn_DP <= ChannelsIn_DN; 336 | end if; 337 | end if; 338 | end process seq_input_buffers; 339 | 340 | ----------------------------------------------------------------------------- 341 | -- Data Registers 342 | ----------------------------------------------------------------------------- 343 | -- Additional Feature 344 | gen_seq_additional_feature : if INPUT_CHANNELS_EVEN generate 345 | seq_additional_feature : process (Clk_CI) 346 | begin -- process seq_additional_feature 347 | if (rising_edge(Clk_CI)) then -- rising clock edge 348 | if (Reset_RI or AdditionalFeatureCLR_S) = '1' then 349 | AdditionalFeature_DP <= (others => '0'); 350 | elsif AdditionalFeatureEN_S = '1' then 351 | AdditionalFeature_DP <= AdditionalFeature_DN; 352 | end if; 353 | end if; 354 | end process seq_additional_feature; 355 | end generate gen_seq_additional_feature; 356 | 357 | ----------------------------------------------------------------------------- 358 | -- Control Registers 359 | ----------------------------------------------------------------------------- 360 | -- Cycle Counter 361 | seq_cycle_counter : process (Clk_CI) 362 | begin -- process seq_cycle_counter 363 | if (rising_edge(Clk_CI)) then -- rising clock edge 364 | if (Reset_RI or CycleCntrCLR_S) = '1' then 365 | CycleCntr_SP <= (others => '0'); 366 | elsif CycleCntrEN_S = '1' then 367 | CycleCntr_SP <= CycleCntr_SN; 368 | end if; 369 | end if; 370 | end process seq_cycle_counter; 371 | 372 | -- Finite State Machine 373 | seq_fsm : process (Clk_CI) 374 | begin -- process seq_fsm 375 | if (rising_edge(Clk_CI)) then -- rising clock edge 376 | if Reset_RI = '1' then 377 | FSM_SP <= idle; 378 | else 379 | FSM_SP <= FSM_SN; 380 | end if; 381 | end if; 382 | end process seq_fsm; 383 | 384 | end ca; 385 | -------------------------------------------------------------------------------- /vhdl/source/spatial_encoder/spatial_encoder_ent.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Spatial Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : spatial_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encode. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | use work.hdc_enhanced_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | entity spatial_encoder is 40 | port ( 41 | -- Global Ports 42 | Clk_CI : in std_logic; 43 | Reset_RI : in std_logic; 44 | 45 | -- Handshake Ports 46 | ValidIn_SI : in std_logic; 47 | ReadyOut_SO : out std_logic; 48 | ReadyIn_SI : in std_logic; 49 | ValidOut_SO : out std_logic; 50 | 51 | -- Input Ports 52 | ModeIn_SI : in std_logic; 53 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 54 | ChannelsIn_DI : in std_logic_vector_array(0 to INPUT_CHANNELS-1)(CHANNEL_WIDTH-1 downto 0); 55 | 56 | -- Output Ports 57 | ModeOut_SO : out std_logic; 58 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 59 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1) 60 | ); 61 | end spatial_encoder; 62 | -------------------------------------------------------------------------------- /vhdl/source/spatial_encoder/spatial_encoder_lut_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Spatial Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : spatial_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encode. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | use work.hdc_baseline_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | architecture lut of spatial_encoder is 40 | 41 | ----------------------------------------------------------------------------- 42 | -- Signals 43 | ----------------------------------------------------------------------------- 44 | -- Input Buffers 45 | signal ModeIn_SP, ModeIn_SN : std_logic; 46 | signal LabelIn_DP, LabelIn_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 47 | signal ChannelsIn_DP, ChannelsIn_DN : std_logic_vector_array(0 to INPUT_CHANNELS-1)(CHANNEL_WIDTH-1 downto 0); 48 | 49 | -- Data Registers 50 | signal BundleChannelsOut_DP, BundleChannelsOut_DN : hypervector(0 to HV_DIMENSION-1); 51 | 52 | -- Control Registers 53 | type fsm_states is (idle, data_received, channels_mapped); 54 | signal FSM_SP, FSM_SN : fsm_states; 55 | 56 | -- Datapath Signals 57 | signal MapChannelsOut_D : hypervector_array(0 to INPUT_CHANNELS-1)(0 to HV_DIMENSION-1); 58 | signal BindChannelsOut_D : hypervector_array(0 to INPUT_CHANNELS-1)(0 to HV_DIMENSION-1); 59 | signal BundleChannelsIn_D : hypervector_array(0 to INPUT_CHANNELS-(INPUT_CHANNELS mod 2))(0 to HV_DIMENSION-1); 60 | 61 | -- Status Signals 62 | 63 | -- Control Signals 64 | signal InputBuffersEN_S : std_logic; 65 | signal BundleChannelsOutEN_S : std_logic; 66 | 67 | begin 68 | ----------------------------------------------------------------------------- 69 | ----------------------------------------------------------------------------- 70 | -- DATAPATH 71 | ----------------------------------------------------------------------------- 72 | ----------------------------------------------------------------------------- 73 | -- Input Signals 74 | ----------------------------------------------------------------------------- 75 | ModeIn_SN <= ModeIn_SI; 76 | LabelIn_DN <= LabelIn_DI; 77 | ChannelsIn_DN <= ChannelsIn_DI; 78 | 79 | ----------------------------------------------------------------------------- 80 | -- Channel Mapping 81 | ----------------------------------------------------------------------------- 82 | gen_map_cim : for i in 0 to INPUT_CHANNELS-1 generate 83 | MapChannelsOut_D(i) <= CONTINUOUS_ITEM_MEMORY(to_integer(unsigned(ChannelsIn_DP(i)))); 84 | end generate gen_map_cim; 85 | 86 | ----------------------------------------------------------------------------- 87 | -- Channel Binding 88 | ----------------------------------------------------------------------------- 89 | gen_bind_cim_im : for i in 0 to INPUT_CHANNELS-1 generate 90 | BindChannelsOut_D(i) <= MapChannelsOut_D(i) xor ITEM_MEMORY(i); 91 | end generate gen_bind_cim_im; 92 | 93 | ----------------------------------------------------------------------------- 94 | -- Channel Bundling 95 | ----------------------------------------------------------------------------- 96 | -- Additional Feature 97 | gen_combine_channels : if (INPUT_CHANNELS mod 2) = 0 generate 98 | BundleChannelsIn_D(BundleChannelsIn_D'high(1)) <= BindChannelsOut_D(0) xor BindChannelsOut_D(BindChannelsOut_D'high); 99 | end generate gen_combine_channels; 100 | BundleChannelsIn_D(0 to INPUT_CHANNELS-1) <= BindChannelsOut_D; 101 | 102 | -- Bundling 103 | BundleChannelsOut_DN <= majority(BundleChannelsIn_D); 104 | 105 | ----------------------------------------------------------------------------- 106 | -- Output Signals 107 | ----------------------------------------------------------------------------- 108 | ModeOut_SO <= ModeIn_SP; 109 | LabelOut_DO <= LabelIn_DP; 110 | HypervectorOut_DO <= BundleChannelsOut_DP; 111 | 112 | ----------------------------------------------------------------------------- 113 | ----------------------------------------------------------------------------- 114 | -- CONTROLLER 115 | ----------------------------------------------------------------------------- 116 | ----------------------------------------------------------------------------- 117 | -- Controller Support Circuits 118 | ----------------------------------------------------------------------------- 119 | 120 | 121 | ----------------------------------------------------------------------------- 122 | -- Finite State Machine 123 | ----------------------------------------------------------------------------- 124 | comb_fsm : process (FSM_SP, ReadyIn_SI, ValidIn_SI) is 125 | begin -- process comb_fsm 126 | -- Default Assignments 127 | FSM_SN <= idle; 128 | 129 | ReadyOut_SO <= '0'; 130 | ValidOut_SO <= '0'; 131 | 132 | InputBuffersEN_S <= '0'; 133 | BundleChannelsOutEN_S <= '0'; 134 | 135 | -- Trainsitions and Output 136 | case FSM_SP is 137 | when idle => 138 | FSM_SN <= idle when ValidIn_SI = '0' else data_received; 139 | ReadyOut_SO <= '1'; 140 | InputBuffersEN_S <= '1' when ValidIn_SI = '1' else '0'; 141 | when data_received => 142 | FSM_SN <= channels_mapped; 143 | BundleChannelsOutEN_S <= '1'; 144 | when channels_mapped => 145 | FSM_SN <= channels_mapped when ReadyIn_SI = '0' else idle; 146 | ValidOut_SO <= '1'; 147 | end case; 148 | 149 | end process comb_fsm; 150 | 151 | ----------------------------------------------------------------------------- 152 | ----------------------------------------------------------------------------- 153 | -- MEMORIES 154 | ----------------------------------------------------------------------------- 155 | ----------------------------------------------------------------------------- 156 | -- Input Buffers 157 | ----------------------------------------------------------------------------- 158 | seq_input_buffers : process (Clk_CI) 159 | begin -- process seq_InputBuffers 160 | if (rising_edge(Clk_CI)) then -- rising clock edge 161 | if Reset_RI = '1' then 162 | ModeIn_SP <= '0'; 163 | LabelIn_DP <= (others => '0'); 164 | ChannelsIn_DP <= (others => (others => '0')); 165 | elsif InputBuffersEN_S = '1' then 166 | ModeIn_SP <= ModeIn_SN; 167 | LabelIn_DP <= LabelIn_DN; 168 | ChannelsIn_DP <= ChannelsIn_DN; 169 | end if; 170 | end if; 171 | end process seq_input_buffers; 172 | 173 | ----------------------------------------------------------------------------- 174 | -- Data Registers 175 | ----------------------------------------------------------------------------- 176 | -- Bundled Channels Register 177 | seq_bundle_channels : process (Clk_CI) 178 | begin -- process seq_bundle_channels 179 | if (rising_edge(Clk_CI)) then -- rising clock edge 180 | if Reset_RI = '1' then 181 | BundleChannelsOut_DP <= (others => '0'); 182 | elsif BundleChannelsOutEN_S = '1' then 183 | BundleChannelsOut_DP <= BundleChannelsOut_DN; 184 | end if; 185 | end if; 186 | end process seq_bundle_channels; 187 | 188 | ----------------------------------------------------------------------------- 189 | -- Control Registers 190 | ----------------------------------------------------------------------------- 191 | -- Finite State Machine 192 | seq_fsm : process (Clk_CI) 193 | begin -- process seq_fsm 194 | if (rising_edge(Clk_CI)) then -- rising clock edge 195 | if Reset_RI = '1' then 196 | FSM_SP <= idle; 197 | else 198 | FSM_SP <= FSM_SN; 199 | end if; 200 | end if; 201 | end process seq_fsm; 202 | 203 | end lut; 204 | -------------------------------------------------------------------------------- /vhdl/source/spatial_encoder/spatial_encoder_man_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Spatial Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : spatial_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encode. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | use work.hdc_enhanced_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | architecture man of spatial_encoder is 40 | 41 | ----------------------------------------------------------------------------- 42 | -- Constants 43 | ----------------------------------------------------------------------------- 44 | constant CYCLE_CNTR_WIDTH : integer := num2bits(INPUT_CHANNELS); 45 | constant INPUT_CHANNELS_EVEN : boolean := (INPUT_CHANNELS mod 2) = 0; 46 | 47 | ----------------------------------------------------------------------------- 48 | -- Signals 49 | ----------------------------------------------------------------------------- 50 | -- Input Buffers 51 | signal ModeIn_SP, ModeIn_SN : std_logic; 52 | signal LabelIn_DP, LabelIn_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 53 | signal ChannelsIn_DP, ChannelsIn_DN : std_logic_vector_array(0 to INPUT_CHANNELS-1)(CHANNEL_WIDTH-1 downto 0); 54 | 55 | -- Data Registers 56 | signal AdditionalFeature_DP, AdditionalFeature_DN : hypervector(0 to HV_DIMENSION-1); 57 | 58 | -- Control Registers 59 | type fsm_states is (idle, data_received, bundle_cntr_fed, channels_mapped, feature_added); 60 | signal FSM_SP, FSM_SN : fsm_states; 61 | signal CycleCntr_SP, CycleCntr_SN : unsigned(CYCLE_CNTR_WIDTH-1 downto 0); 62 | signal CycleShiftReg_SP, CycleShiftReg_SN : std_logic_vector(0 to INPUT_CHANNELS-1); 63 | 64 | -- Datapath Signals 65 | signal SelectedChannel_D : std_logic_vector(CHANNEL_WIDTH-1 downto 0); 66 | signal ChannelNHot_D : std_logic_vector(0 to INPUT_QUANTIZATION-2); 67 | signal CIMOut_D : hypervector(0 to HV_DIMENSION-1); 68 | signal BindChannelOut_D : hypervector(0 to HV_DIMENSION-1); 69 | signal SelectFeatureOut_D : hypervector(0 to HV_DIMENSION-1); 70 | 71 | -- Status Signals 72 | signal LastChannel_S : std_logic; 73 | 74 | -- Control Signals 75 | signal InputBuffersEN_S : std_logic; 76 | signal BundleCntrEN_S : std_logic; 77 | signal CycleShiftRegEN_S : std_logic; 78 | signal CycleShiftRegCLR_S : std_logic; 79 | signal AdditionalFeatureEN_S : std_logic; 80 | signal AdditionalFeatureCLR_S : std_logic; 81 | signal CycleCntrEN_S : std_logic; 82 | signal CycleCntrCLR_S : std_logic; 83 | 84 | signal FirstHypervector_S : std_logic; 85 | signal SelectAdditionalFeature_S : std_logic; 86 | 87 | ----------------------------------------------------------------------------- 88 | -- Components 89 | ----------------------------------------------------------------------------- 90 | component hypervector_manipulator is 91 | generic ( 92 | WIDTH : integer; 93 | DEPTH : integer; 94 | CONNECTIVITY_MATRIX : std_logic_vector_array(0 to DEPTH-1)(0 to WIDTH-1)); 95 | port ( 96 | HypervectorIn_DI : in std_logic_vector(0 to WIDTH-1); 97 | ManipulatorIn_DI : in std_logic_vector(0 to DEPTH-1); 98 | HypervectorOut_DO : out std_logic_vector(0 to HV_DIMENSION-1)); 99 | end component hypervector_manipulator; 100 | 101 | component bundle_counter is 102 | generic ( 103 | WIDTH : integer); 104 | port ( 105 | Clk_CI : in std_logic; 106 | Reset_RI : in std_logic; 107 | Enable_SI : in std_logic; 108 | FirstHypervector_SI : in std_logic; 109 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 110 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1)); 111 | end component bundle_counter; 112 | 113 | begin 114 | ----------------------------------------------------------------------------- 115 | ----------------------------------------------------------------------------- 116 | -- DATAPATH 117 | ----------------------------------------------------------------------------- 118 | ----------------------------------------------------------------------------- 119 | -- Input Signals 120 | ----------------------------------------------------------------------------- 121 | ModeIn_SN <= ModeIn_SI; 122 | LabelIn_DN <= LabelIn_DI; 123 | ChannelsIn_DN <= ChannelsIn_DI; 124 | 125 | ----------------------------------------------------------------------------- 126 | -- Channel Mapping 127 | ----------------------------------------------------------------------------- 128 | SelectedChannel_D <= ChannelsIn_DP(to_integer(CycleCntr_SP)); 129 | 130 | -- N-Hot LUT 131 | ChannelNHot_D <= NHOT_LUT(to_integer(unsigned(SelectedChannel_D))); 132 | 133 | -- CIM 134 | i_hypervector_manipulator_1 : hypervector_manipulator 135 | generic map ( 136 | WIDTH => HV_DIMENSION, 137 | DEPTH => INPUT_QUANTIZATION-1, 138 | CONNECTIVITY_MATRIX => CIM_CONNECTIVITY_MATRIX) 139 | port map ( 140 | HypervectorIn_DI => CIM_SEED, 141 | ManipulatorIn_DI => ChannelNHot_D, 142 | HypervectorOut_DO => CIMOut_D); 143 | 144 | ----------------------------------------------------------------------------- 145 | -- Channel Binding 146 | ----------------------------------------------------------------------------- 147 | -- Item Memory 148 | i_hypervector_manipulator_2 : hypervector_manipulator 149 | generic map ( 150 | WIDTH => HV_DIMENSION, 151 | DEPTH => INPUT_CHANNELS, 152 | CONNECTIVITY_MATRIX => IM_CONNECTIVITY_MATRIX) 153 | port map ( 154 | HypervectorIn_DI => CIMOut_D, 155 | ManipulatorIn_DI => CycleShiftReg_SP, 156 | HypervectorOut_DO => BindChannelOut_D); 157 | 158 | 159 | ----------------------------------------------------------------------------- 160 | -- Channel Bundling 161 | ----------------------------------------------------------------------------- 162 | gen_additional_feature : if INPUT_CHANNELS_EVEN generate 163 | AdditionalFeature_DN <= BindChannelOut_D xor AdditionalFeature_DP; 164 | SelectFeatureOut_D <= AdditionalFeature_DP when SelectAdditionalFeature_S = '1' else 165 | BindChannelOut_D; 166 | else generate 167 | SelectFeatureOut_D <= BindChannelOut_D; 168 | end generate gen_additional_feature; 169 | 170 | -- Bundling Counter 171 | i_bundle_counter_1 : bundle_counter 172 | generic map ( 173 | WIDTH => BUNDLE_CHANNELS_WIDTH) 174 | port map ( 175 | Clk_CI => Clk_CI, 176 | Reset_RI => Reset_RI, 177 | Enable_SI => BundleCntrEN_S, 178 | FirstHypervector_SI => FirstHypervector_S, 179 | HypervectorIn_DI => SelectFeatureOut_D, 180 | HypervectorOut_DO => HypervectorOut_DO); 181 | 182 | ----------------------------------------------------------------------------- 183 | -- Output Signals 184 | ----------------------------------------------------------------------------- 185 | ModeOut_SO <= ModeIn_SP; 186 | LabelOut_DO <= LabelIn_DP; 187 | 188 | ----------------------------------------------------------------------------- 189 | ----------------------------------------------------------------------------- 190 | -- CONTROLLER 191 | ----------------------------------------------------------------------------- 192 | ----------------------------------------------------------------------------- 193 | -- Controller Support Circuits 194 | ----------------------------------------------------------------------------- 195 | -- Cycle Counter 196 | CycleCntr_SN <= CycleCntr_SP + 1; 197 | LastChannel_S <= '1' when to_integer(CycleCntr_SP) = INPUT_CHANNELS-1 else '0'; 198 | 199 | -- Cycle Shift Register 200 | CycleShiftReg_SN <= CycleShiftReg_SP srl 1; 201 | 202 | ----------------------------------------------------------------------------- 203 | -- Finite State Machine 204 | ----------------------------------------------------------------------------- 205 | -- There have to be two different implementations of the controller: 206 | -- - One for the case that we have an even number of channels 207 | -- - Another one for the case that we have an odd number of channels 208 | gen_comb_fsm : if INPUT_CHANNELS_EVEN generate 209 | comb_fsm : process (FSM_SP, LastChannel_S, ReadyIn_SI, ValidIn_SI) is 210 | begin -- process comb_fsm 211 | -- Default Assignments 212 | FSM_SN <= idle; 213 | 214 | ReadyOut_SO <= '0'; 215 | ValidOut_SO <= '0'; 216 | 217 | InputBuffersEN_S <= '0'; 218 | BundleCntrEN_S <= '0'; 219 | CycleShiftRegEN_S <= '0'; 220 | CycleShiftRegCLR_S <= '0'; 221 | AdditionalFeatureEN_S <= '0'; 222 | AdditionalFeatureCLR_S <= '0'; 223 | CycleCntrEN_S <= '0'; 224 | CycleCntrCLR_S <= '0'; 225 | 226 | FirstHypervector_S <= '0'; 227 | SelectAdditionalFeature_S <= '0'; 228 | 229 | -- Trainsitions and Output 230 | case FSM_SP is 231 | when idle => 232 | FSM_SN <= data_received when ValidIn_SI = '1' else idle; 233 | ReadyOut_SO <= '1'; 234 | InputBuffersEN_S <= '1' when ValidIn_SI = '1' else '0'; 235 | 236 | when data_received => 237 | FSM_SN <= bundle_cntr_fed; 238 | BundleCntrEN_S <= '1'; 239 | CycleShiftRegEN_S <= '1'; 240 | AdditionalFeatureEN_S <= '1'; 241 | CycleCntrEN_S <= '1'; 242 | FirstHypervector_S <= '1'; 243 | 244 | when bundle_cntr_fed => 245 | FSM_SN <= channels_mapped when LastChannel_S = '1' else bundle_cntr_fed; 246 | BundleCntrEN_S <= '1'; 247 | CycleShiftRegEN_S <= '1'; 248 | AdditionalFeatureEN_S <= '1' when LastChannel_S = '1' else '0'; -- erase "when ..." if additional feature should combine all channels 249 | CycleCntrEN_S <= '1'; 250 | 251 | when channels_mapped => 252 | FSM_SN <= feature_added; 253 | BundleCntrEN_S <= '1'; 254 | CycleShiftRegCLR_S <= '1'; 255 | AdditionalFeatureCLR_S <= '1'; 256 | CycleCntrCLR_S <= '1'; 257 | SelectAdditionalFeature_S <= '1'; 258 | 259 | when feature_added => 260 | FSM_SN <= idle when ReadyIn_SI = '1' else feature_added; 261 | ValidOut_SO <= '1'; 262 | 263 | when others => 264 | null; 265 | end case; 266 | 267 | end process comb_fsm; 268 | ----------------------------------------------------------------------------- 269 | else generate 270 | comb_fsm : process (FSM_SP, LastChannel_S, ReadyIn_SI, ValidIn_SI) is 271 | begin -- process comb_fsm 272 | -- Default Assignments 273 | FSM_SN <= idle; 274 | 275 | ReadyOut_SO <= '0'; 276 | ValidOut_SO <= '0'; 277 | 278 | InputBuffersEN_S <= '0'; 279 | BundleCntrEN_S <= '0'; 280 | CycleShiftRegEN_S <= '0'; 281 | CycleShiftRegCLR_S <= '0'; 282 | CycleCntrEN_S <= '0'; 283 | CycleCntrCLR_S <= '0'; 284 | 285 | FirstHypervector_S <= '0'; 286 | 287 | -- Trainsitions and Output 288 | case FSM_SP is 289 | when idle => 290 | FSM_SN <= data_received when ValidIn_SI = '1' else idle; 291 | ReadyOut_SO <= '1'; 292 | InputBuffersEN_S <= '1' when ValidIn_SI = '1' else '0'; 293 | 294 | when data_received => 295 | FSM_SN <= bundle_cntr_fed; 296 | BundleCntrEN_S <= '1'; 297 | CycleShiftRegEN_S <= '1'; 298 | CycleCntrEN_S <= '1'; 299 | FirstHypervector_S <= '1'; 300 | 301 | when bundle_cntr_fed => 302 | FSM_SN <= channels_mapped when LastChannel_S = '1' else bundle_cntr_fed; 303 | BundleCntrEN_S <= '1'; 304 | if LastChannel_S = '0' then 305 | CycleShiftRegEN_S <= '1'; 306 | CycleCntrEN_S <= '1'; 307 | else 308 | CycleShiftRegCLR_S <= '1'; 309 | CycleCntrCLR_S <= '1'; 310 | end if; 311 | 312 | when channels_mapped => 313 | FSM_SN <= idle when ReadyIn_SI = '1' else channels_mapped; 314 | ValidOut_SO <= '1'; 315 | 316 | when others => 317 | null; 318 | end case; 319 | 320 | end process comb_fsm; 321 | end generate gen_comb_fsm; 322 | 323 | ----------------------------------------------------------------------------- 324 | ----------------------------------------------------------------------------- 325 | -- MEMORIES 326 | ----------------------------------------------------------------------------- 327 | ----------------------------------------------------------------------------- 328 | -- Input Buffers 329 | ----------------------------------------------------------------------------- 330 | seq_input_buffers : process (Clk_CI) 331 | begin -- process seq_InputBuffers 332 | if (rising_edge(Clk_CI)) then -- rising clock edge 333 | if Reset_RI = '1' then 334 | ModeIn_SP <= '0'; 335 | LabelIn_DP <= (others => '0'); 336 | ChannelsIn_DP <= (others => (others => '0')); 337 | elsif InputBuffersEN_S = '1' then 338 | ModeIn_SP <= ModeIn_SN; 339 | LabelIn_DP <= LabelIn_DN; 340 | ChannelsIn_DP <= ChannelsIn_DN; 341 | end if; 342 | end if; 343 | end process seq_input_buffers; 344 | 345 | ----------------------------------------------------------------------------- 346 | -- Data Registers 347 | ----------------------------------------------------------------------------- 348 | -- Additional Feature 349 | gen_seq_additional_feature : if INPUT_CHANNELS_EVEN generate 350 | seq_additional_feature : process (Clk_CI) 351 | begin -- process seq_additional_feature 352 | if (rising_edge(Clk_CI)) then -- rising clock edge 353 | if (Reset_RI or AdditionalFeatureCLR_S) = '1' then 354 | AdditionalFeature_DP <= (others => '0'); 355 | elsif AdditionalFeatureEN_S = '1' then 356 | AdditionalFeature_DP <= AdditionalFeature_DN; 357 | end if; 358 | end if; 359 | end process seq_additional_feature; 360 | end generate gen_seq_additional_feature; 361 | 362 | ----------------------------------------------------------------------------- 363 | -- Control Registers 364 | ----------------------------------------------------------------------------- 365 | -- Cycle Counter 366 | seq_cycle_counter : process (Clk_CI) 367 | begin -- process seq_cycle_counter 368 | if (rising_edge(Clk_CI)) then -- rising clock edge 369 | if (Reset_RI or CycleCntrCLR_S) = '1' then 370 | CycleCntr_SP <= (others => '0'); 371 | elsif CycleCntrEN_S = '1' then 372 | CycleCntr_SP <= CycleCntr_SN; 373 | end if; 374 | end if; 375 | end process seq_cycle_counter; 376 | 377 | -- Cycle Shift Register 378 | seq_cycle_shift_reg : process (Clk_CI) 379 | begin -- process seq_cycle_shift_register 380 | if (rising_edge(Clk_CI)) then -- rising clock edge 381 | if (Reset_RI or CycleShiftRegCLR_S) = '1' then 382 | CycleShiftReg_SP <= (0 => '1', others => '0'); 383 | elsif CycleShiftRegEN_S = '1' then 384 | CycleShiftReg_SP <= CycleShiftReg_SN; 385 | end if; 386 | end if; 387 | end process seq_cycle_shift_reg; 388 | 389 | -- Finite State Machine 390 | seq_fsm : process (Clk_CI) 391 | begin -- process seq_fsm 392 | if (rising_edge(Clk_CI)) then -- rising clock edge 393 | if Reset_RI = '1' then 394 | FSM_SP <= idle; 395 | else 396 | FSM_SP <= FSM_SN; 397 | end if; 398 | end if; 399 | end process seq_fsm; 400 | 401 | end man; 402 | -------------------------------------------------------------------------------- /vhdl/source/support_circuits/block_shift_memory_ent_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Block Shift Memory 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : block_shift_memory_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Last update: 2018-01-02 21 | -- Platform : ModelSim (simulation), Vivado (synthesis) 22 | ------------------------------------------------------------------------------- 23 | -- Description: Entity and architecture of the block shift memory used in 24 | -- the associative memory. 25 | ------------------------------------------------------------------------------- 26 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 27 | ------------------------------------------------------------------------------- 28 | -- Revisions : 29 | -- Date Version Author Description 30 | -- 2018 1.0 schmucma Created 31 | ------------------------------------------------------------------------------- 32 | 33 | library ieee; 34 | use ieee.std_logic_1164.all; 35 | use ieee.numeric_std.all; 36 | use work.hdc_pkg.all; 37 | use work.hdc_enhanced_pkg.all; 38 | 39 | ------------------------------------------------------------------------------- 40 | 41 | entity block_shift_memory is 42 | generic ( 43 | WIDTH : integer := HV_DIMENSION; 44 | BLOCKS : integer := HV_DIMENSION/2 45 | ); 46 | 47 | port ( 48 | Clk_CI : in std_logic; 49 | Reset_RI : in std_logic; 50 | 51 | Enable_SI : in std_logic; 52 | Mode_SI : in std_logic; 53 | 54 | CellsIn_DI : in std_logic_vector(0 to WIDTH-1); 55 | BlockBitsOut_DO : out std_logic_vector(0 to BLOCKS-1) 56 | ); 57 | end block_shift_memory; 58 | 59 | ------------------------------------------------------------------------------- 60 | 61 | architecture behavioral of block_shift_memory is 62 | 63 | ----------------------------------------------------------------------------- 64 | -- Constants 65 | ----------------------------------------------------------------------------- 66 | constant BLOCK_WIDTH : integer := WIDTH / BLOCKS; 67 | 68 | ----------------------------------------------------------------------------- 69 | -- Signals 70 | ----------------------------------------------------------------------------- 71 | -- Data Registers 72 | signal CellMemory_DP, CellMemory_DN : std_logic_vector(0 to WIDTH-1); 73 | 74 | begin 75 | 76 | ----------------------------------------------------------------------------- 77 | -- Datapath 78 | ----------------------------------------------------------------------------- 79 | -- Cell Memory Next State 80 | comb_cell_memory : process (CellMemory_DP, CellsIn_DI, Mode_SI) is 81 | begin -- process comb_cell_memory 82 | if Mode_SI = mode_store then 83 | CellMemory_DN <= CellsIn_DI; 84 | else 85 | for j in 0 to BLOCKS-1 loop 86 | CellMemory_DN(j * BLOCK_WIDTH to (j+1) * BLOCK_WIDTH - 1) 87 | <= CellMemory_DP(j * BLOCK_WIDTH to (j+1) * BLOCK_WIDTH - 1) rol 1; 88 | end loop; -- j 89 | end if; 90 | end process comb_cell_memory; 91 | 92 | -- Outputs 93 | asgn_outputs : process (CellMemory_DP) is 94 | begin -- process asgn_outputs 95 | for j in 0 to BLOCKS-1 loop 96 | BlockBitsOut_DO(j) <= CellMemory_DP(j * BLOCK_WIDTH); 97 | end loop; -- j 98 | end process asgn_outputs; 99 | 100 | ----------------------------------------------------------------------------- 101 | -- Registers 102 | ----------------------------------------------------------------------------- 103 | -- Cell Memory 104 | seq_cell_memory : process (Clk_CI) 105 | begin -- process seq_cell_memory 106 | if (rising_edge(Clk_CI)) then -- rising clock edge 107 | if Reset_RI = '1' then 108 | CellMemory_DP <= (others => '0'); 109 | elsif Enable_SI = '1' then 110 | CellMemory_DP <= CellMemory_DN; 111 | end if; 112 | end if; 113 | end process seq_cell_memory; 114 | 115 | 116 | end behavioral; 117 | -------------------------------------------------------------------------------- /vhdl/source/support_circuits/bundle_counter_ent_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Bundle Counter 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : bundle_counter_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the bundle counter used in the 23 | -- baseline and enhanced architecture. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use work.hdc_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | entity bundle_counter is 40 | generic ( 41 | WIDTH : integer := BUNDLE_NGRAMS_WIDTH 42 | ); 43 | 44 | port ( 45 | Clk_CI : in std_logic; 46 | Reset_RI : in std_logic; 47 | 48 | Enable_SI : in std_logic; 49 | 50 | FirstHypervector_SI : in std_logic; 51 | 52 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 53 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1) 54 | ); 55 | end bundle_counter; 56 | 57 | ------------------------------------------------------------------------------- 58 | 59 | architecture behavioral of bundle_counter is 60 | -- Constants 61 | constant MAX_VALUE : signed(WIDTH-1 downto 0) := to_signed(2**(WIDTH-1)-1, WIDTH); 62 | constant MIN_VALUE : signed(WIDTH-1 downto 0) := to_signed(-2**(WIDTH-1), WIDTH); 63 | 64 | -- Signals 65 | signal BundleCounter_DP, BundleCounter_DN : signed_array(0 to HV_DIMENSION-1)(WIDTH-1 downto 0); 66 | signal CounterSEN_S : std_logic_vector(0 to HV_DIMENSION-1); 67 | 68 | begin 69 | 70 | ----------------------------------------------------------------------------- 71 | -- Datapath 72 | ----------------------------------------------------------------------------- 73 | -- Next State 74 | comb_bundle_counter : process (BundleCounter_DP, FirstHypervector_SI, HypervectorIn_DI) 75 | begin -- process comb_bundle_counter 76 | for i in 0 to HV_DIMENSION-1 loop 77 | if FirstHypervector_SI = '1' then 78 | BundleCounter_DN(i) <= (others => HypervectorIn_DI(i)); 79 | CounterSEN_S(i) <= '1'; 80 | else 81 | if HypervectorIn_DI(i) = '1' then 82 | BundleCounter_DN(i) <= BundleCounter_DP(i)-1; 83 | CounterSEN_S(i) <= '0' when BundleCounter_DP(i) = MIN_VALUE else '1'; 84 | else 85 | BundleCounter_DN(i) <= BundleCounter_DP(i)+1; 86 | CounterSEN_S(i) <= '0' when BundleCounter_DP(i) = MAX_VALUE else '1'; 87 | end if; 88 | end if; 89 | end loop; -- i 90 | end process comb_bundle_counter; 91 | 92 | -- Output 93 | asgn_output : process (BundleCounter_DP) is 94 | begin -- process asgn_output 95 | for i in 0 to HV_DIMENSION-1 loop 96 | HypervectorOut_DO(i) <= BundleCounter_DP(i)(BundleCounter_DP(i)'high); 97 | end loop; -- i 98 | end process asgn_output; 99 | 100 | ----------------------------------------------------------------------------- 101 | -- Registers 102 | ----------------------------------------------------------------------------- 103 | -- Bundle NGrams Counter 104 | -- Both Enable and Self Enable have to be set to trigger flip-flop 105 | gen_seq_bundle_counter : for i in 0 to HV_DIMENSION-1 generate 106 | seq_bundle_counter : process (Clk_CI) 107 | begin -- process seq_bundle_ngrams_cntr 108 | if (rising_edge(Clk_CI)) then -- rising clock edge 109 | if Reset_RI = '1' then 110 | BundleCounter_DP(i) <= (others => '0'); 111 | elsif (Enable_SI and CounterSEN_S(i)) = '1' then 112 | BundleCounter_DP(i) <= BundleCounter_DN(i); 113 | end if; 114 | end if; 115 | end process seq_bundle_counter; 116 | end generate gen_seq_bundle_counter; 117 | 118 | 119 | end behavioral; 120 | -------------------------------------------------------------------------------- /vhdl/source/support_circuits/cellular_automaton_ent_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Cellular Automaton 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : cellular_automaton_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the cellular automaton. Can be used 23 | -- to generate random hypervectors. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use work.hdc_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | entity cellular_automaton is 40 | generic ( 41 | WIDTH : integer := HV_DIMENSION; 42 | NEIGHBORHOOD_WIDTH : integer := 3; 43 | RULE : integer := 30; 44 | CELLULAR_AUTOMATON_SEED : std_logic_vector(0 to WIDTH-1) 45 | ); 46 | 47 | port ( 48 | Clk_CI : in std_logic; 49 | Reset_RI : in std_logic; 50 | 51 | Enable_SI : in std_logic; 52 | Clear_SI : in std_logic; 53 | 54 | CellValueOut_DO : out std_logic_vector(0 to WIDTH-1) 55 | ); 56 | end cellular_automaton; 57 | 58 | ------------------------------------------------------------------------------- 59 | 60 | architecture behavioral of cellular_automaton is 61 | 62 | -- Cellular Automaton Rule in Vector Form 63 | constant RULE_VECTOR : std_logic_vector(2**(2**NEIGHBORHOOD_WIDTH)-1 downto 0) := 64 | std_logic_vector(to_unsigned(RULE, 2**(2**NEIGHBORHOOD_WIDTH))); 65 | 66 | -- Cell Registers 67 | signal Cells_DP, Cells_DN : std_logic_vector(0 to WIDTH-1); 68 | 69 | begin 70 | 71 | ----------------------------------------------------------------------------- 72 | -- Datapath 73 | ----------------------------------------------------------------------------- 74 | -- Next State 75 | comb_ca : process (Cells_DP) is 76 | variable neighborhood : std_logic_vector(0 to NEIGHBORHOOD_WIDTH-1); 77 | begin -- process comb_ca 78 | neighborhood := (Cells_DP(Cells_DP'high) & Cells_DP(0 to 1)); 79 | Cells_DN(0) <= RULE_VECTOR(to_integer(unsigned(neighborhood))); 80 | for i in 1 to WIDTH-2 loop 81 | neighborhood := Cells_DP(i-1 to i+1); 82 | Cells_DN(i) <= RULE_VECTOR(to_integer(unsigned(neighborhood))); 83 | end loop; -- i 84 | neighborhood := (Cells_DP(Cells_DP'high-1 to Cells_DP'high) & Cells_DP(0)); 85 | Cells_DN(Cells_DN'high) <= RULE_VECTOR(to_integer(unsigned(neighborhood))); 86 | end process comb_ca; 87 | 88 | -- Output 89 | CellValueOut_DO <= Cells_DP; 90 | 91 | ----------------------------------------------------------------------------- 92 | -- Register 93 | ----------------------------------------------------------------------------- 94 | -- Cellular Automaton 95 | seq_ca : process (Clk_CI) 96 | begin -- process seq_ca 97 | if (rising_edge(Clk_CI)) then -- rising clock edge 98 | if (Reset_RI or Clear_SI) = '1' then 99 | Cells_DP <= CELLULAR_AUTOMATON_SEED; 100 | elsif Enable_SI = '1' then 101 | Cells_DP <= Cells_DN; 102 | end if; 103 | end if; 104 | end process seq_ca; 105 | 106 | 107 | end behavioral; 108 | -------------------------------------------------------------------------------- /vhdl/source/support_circuits/hypervector_manipulator_ent_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Hypervector Manipulator 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : hypervector_manipulator_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the hypervector manipulator. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | 31 | library ieee; 32 | use ieee.std_logic_1164.all; 33 | use ieee.numeric_std.all; 34 | use work.hdc_pkg.all; 35 | use work.hdc_enhanced_pkg.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | entity hypervector_manipulator is 40 | generic ( 41 | WIDTH : integer := HV_DIMENSION; 42 | DEPTH : integer; 43 | CONNECTIVITY_MATRIX : std_logic_vector_array(0 to DEPTH-1)(0 to WIDTH-1) 44 | ); 45 | 46 | port ( 47 | HypervectorIn_DI : in std_logic_vector(0 to WIDTH-1); 48 | ManipulatorIn_DI : in std_logic_vector(0 to DEPTH-1); 49 | 50 | HypervectorOut_DO : out std_logic_vector(0 to WIDTH-1) 51 | ); 52 | end hypervector_manipulator; 53 | 54 | ------------------------------------------------------------------------------- 55 | 56 | architecture behavioral of hypervector_manipulator is 57 | 58 | begin 59 | 60 | -- Manipulate Hypervector 61 | comb_manipulate_hypervector : process (HypervectorIn_DI, ManipulatorIn_DI) is 62 | variable or_column : std_logic := '0'; 63 | begin -- process comb_manipulate_hypervector 64 | for i in 0 to WIDTH-1 loop 65 | or_column := '0'; 66 | for j in 0 to DEPTH-1 loop 67 | if CONNECTIVITY_MATRIX(j)(i) = '1' then 68 | or_column := or_column or ManipulatorIn_DI(j); 69 | end if; 70 | end loop; -- j 71 | HypervectorOut_DO(i) <= HypervectorIn_DI(i) xor or_column; 72 | end loop; -- i 73 | end process comb_manipulate_hypervector; 74 | 75 | end behavioral; 76 | -------------------------------------------------------------------------------- /vhdl/source/support_circuits/similarity_bundler_ent_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Similarity Bundler 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : similarity_bundler_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the similarity bundler used in the 23 | -- enhanced architecture. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use work.hdc_pkg.all; 36 | use work.hdc_enhanced_pkg.all; 37 | 38 | ------------------------------------------------------------------------------- 39 | 40 | entity similarity_bundler is 41 | generic ( 42 | MAX_BUNDLE_CYCLES : integer := MAX_BUNDLE_CYCLES 43 | ); 44 | 45 | port ( 46 | Clk_CI : in std_logic; 47 | Reset_RI : in std_logic; 48 | 49 | BundledHypervectorEN_SI : in std_logic; 50 | 51 | CycleShiftRegEN_SI : in std_logic; 52 | CycleShiftRegCLR_SI : in std_logic; 53 | 54 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 55 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1) 56 | ); 57 | end similarity_bundler; 58 | 59 | ------------------------------------------------------------------------------- 60 | 61 | architecture behavioral of similarity_bundler is 62 | 63 | ----------------------------------------------------------------------------- 64 | -- Signals 65 | ----------------------------------------------------------------------------- 66 | -- Data Registers 67 | signal BundledHypervector_DP, BundledHypervector_DN : hypervector(0 to HV_DIMENSION-1); 68 | 69 | -- Control Registers 70 | signal CycleShiftReg_SP, CycleShiftReg_SN : std_logic_vector(0 to MAX_BUNDLE_CYCLES-1); 71 | 72 | -- Datapath Signals 73 | signal SimilarHypervector_D : hypervector(0 to HV_DIMENSION-1); 74 | 75 | ----------------------------------------------------------------------------- 76 | -- Components 77 | ----------------------------------------------------------------------------- 78 | -- Hypervector Manipulator 79 | component hypervector_manipulator is 80 | generic ( 81 | WIDTH : integer; 82 | DEPTH : integer; 83 | CONNECTIVITY_MATRIX : std_logic_vector_array(0 to DEPTH-1)(0 to WIDTH-1)); 84 | port ( 85 | HypervectorIn_DI : in std_logic_vector(0 to WIDTH-1); 86 | ManipulatorIn_DI : in std_logic_vector(0 to DEPTH-1); 87 | HypervectorOut_DO : out std_logic_vector(0 to HV_DIMENSION-1)); 88 | end component hypervector_manipulator; 89 | 90 | begin 91 | 92 | ----------------------------------------------------------------------------- 93 | -- Datapath 94 | ----------------------------------------------------------------------------- 95 | -- Cycle Shift Register 96 | CycleShiftReg_SN <= CycleShiftReg_SP srl 1; 97 | 98 | -- Similar Hypervector 99 | i_hypervector_manipulator_1 : hypervector_manipulator 100 | generic map ( 101 | WIDTH => HV_DIMENSION, 102 | DEPTH => MAX_BUNDLE_CYCLES, 103 | CONNECTIVITY_MATRIX => BUNDLE_CONNECTIVITY_MATRIX) 104 | port map ( 105 | HypervectorIn_DI => BundledHypervector_DP, 106 | ManipulatorIn_DI => CycleShiftReg_SP, 107 | HypervectorOut_DO => SimilarHypervector_D); 108 | 109 | -- Majority 110 | comb_majority : process (BundledHypervector_DP, HypervectorIn_DI, SimilarHypervector_D) is 111 | variable sum : integer := 0; 112 | begin -- process comb_majority 113 | for i in 0 to HV_DIMENSION-1 loop 114 | -- sum := logic_to_integer(BundledHypervector_DP(i)) 115 | -- + logic_to_integer(HypervectorIn_DI(i)) 116 | -- + logic_to_integer(SimilarHypervector_D(i)); 117 | -- BundledHypervector_DN(i) <= '1' when sum > 1 else '0'; 118 | BundledHypervector_DN(i) <= 119 | (BundledHypervector_DP(i) and HypervectorIn_DI(i)) or 120 | (BundledHypervector_DP(i) and SimilarHypervector_D(i)) or 121 | (HypervectorIn_DI(i) and SimilarHypervector_D(i)); 122 | end loop; -- i 123 | end process comb_majority; 124 | 125 | -- Output 126 | HypervectorOut_DO <= BundledHypervector_DP; 127 | 128 | ----------------------------------------------------------------------------- 129 | -- Registers 130 | ----------------------------------------------------------------------------- 131 | -- Cycle Shift Register 132 | seq_cycle_shift_register : process (Clk_CI) 133 | begin -- process seq_cycle_shift_register 134 | if (rising_edge(Clk_CI)) then -- rising clock edge 135 | if (Reset_RI or CycleShiftRegCLR_SI) = '1' then 136 | CycleShiftReg_SP <= (0 => '1', others => '0'); 137 | elsif CycleShiftRegEN_SI = '1' then 138 | CycleShiftReg_SP <= CycleShiftReg_SN; 139 | end if; 140 | end if; 141 | end process seq_cycle_shift_register; 142 | 143 | -- Bundled Hypervector 144 | seq_bundled_hypervector : process (Clk_CI) 145 | begin -- process seq_bundled_hypervector 146 | if (rising_edge(Clk_CI)) then -- rising clock edge 147 | if Reset_RI = '1' then 148 | BundledHypervector_DP <= (others => '0'); 149 | elsif BundledHypervectorEN_SI = '1' then 150 | BundledHypervector_DP <= BundledHypervector_DN; 151 | end if; 152 | end if; 153 | end process seq_bundled_hypervector; 154 | 155 | 156 | end behavioral; 157 | -------------------------------------------------------------------------------- /vhdl/source/temporal_encoder/temporal_encoder_b2b_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Temporal Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : temporal_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encoder. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | -- Abbreviations: 31 | -- *N : Only if NGRAM > 1 32 | -- *B : Only if Bundle Counter is used 33 | -- *S : Only if Similarity Counter is used 34 | ------------------------------------------------------------------------------- 35 | 36 | library ieee; 37 | use ieee.std_logic_1164.all; 38 | use ieee.numeric_std.all; 39 | use work.hdc_pkg.all; 40 | 41 | ------------------------------------------------------------------------------- 42 | 43 | architecture b2b of temporal_encoder is 44 | 45 | ----------------------------------------------------------------------------- 46 | -- Constants 47 | ----------------------------------------------------------------------------- 48 | constant FILL_NGRAM_COUNTER_WIDTH : integer := num2bits(NGRAM_SIZE); 49 | 50 | ----------------------------------------------------------------------------- 51 | -- Signals 52 | ----------------------------------------------------------------------------- 53 | -- Input Buffers 54 | signal ModeIn_SP, ModeIn_SN : std_logic; 55 | signal LabelIn_DP, LabelIn_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 56 | 57 | -- Data Registers 58 | -- - Array starts at 1 to illustrate the latency (t-1, t-2, etc...) 59 | signal NGram_DP, NGram_DN : hypervector_array(1 to NGRAM_SIZE-1)(0 to HV_DIMENSION-1); -- *N 60 | 61 | -- Control Registers 62 | type fsm_states is (idle, forward_training, accept_input, forward_query); 63 | signal FSM_SP, FSM_SN : fsm_states; 64 | signal FillNGramCntr_SP, FillNGramCntr_SN : unsigned(FILL_NGRAM_COUNTER_WIDTH-1 downto 0); -- *N 65 | 66 | -- Datapath Signals 67 | signal BindNGramOut_D : hypervector(0 to HV_DIMENSION-1); 68 | 69 | -- Status Signals 70 | signal ModeChange_S : std_logic; 71 | signal LabelChange_S : std_logic; 72 | signal NGramFull_S : std_logic; -- *N 73 | 74 | -- Control Signals 75 | signal InputBuffersEN_S : std_logic; 76 | signal NGramEN_S : std_logic; -- *N 77 | signal BundledHypervectorEN_S : std_logic; 78 | signal CycleShiftRegEN_S : std_logic; 79 | signal CycleShiftRegCLR_S : std_logic; 80 | signal FillNGramCntrEN_S : std_logic; -- *N 81 | signal FillNGramCntrCLR_S : std_logic; -- *N 82 | 83 | ----------------------------------------------------------------------------- 84 | -- Components 85 | ----------------------------------------------------------------------------- 86 | component similarity_bundler is 87 | generic ( 88 | MAX_BUNDLE_CYCLES : integer); 89 | port ( 90 | Clk_CI : in std_logic; 91 | Reset_RI : in std_logic; 92 | BundledHypervectorEN_SI : in std_logic; 93 | CycleShiftRegEN_SI : in std_logic; 94 | CycleShiftRegCLR_SI : in std_logic; 95 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 96 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1)); 97 | end component similarity_bundler; 98 | 99 | begin 100 | 101 | ----------------------------------------------------------------------------- 102 | ----------------------------------------------------------------------------- 103 | -- DATAPATH 104 | ----------------------------------------------------------------------------- 105 | ----------------------------------------------------------------------------- 106 | -- Input Signals 107 | ----------------------------------------------------------------------------- 108 | ModeIn_SN <= ModeIn_SI; 109 | LabelIn_DN <= LabelIn_DI; 110 | 111 | ----------------------------------------------------------------------------- 112 | -- NGram 113 | ----------------------------------------------------------------------------- 114 | -- NGram Permutation 115 | gen_asgn_ngram_1 : if NGRAM_SIZE > 1 generate 116 | NGram_DN(1) <= HypervectorIn_DI ror 1; 117 | gen_asgn_ngram_2 : for i in 2 to NGRAM_SIZE-1 generate 118 | NGram_DN(i) <= NGram_DP(i-1) ror 1; 119 | end generate gen_asgn_ngram_2; 120 | end generate gen_asgn_ngram_1; 121 | 122 | -- NGram Binding 123 | gen_comb_bind_ngram : if NGRAM_SIZE > 1 generate 124 | comb_bind_ngram : process (HypervectorIn_DI, NGram_DP) is 125 | variable result : hypervector(0 to HV_DIMENSION-1) := (others => '0'); 126 | begin -- process comb_bind_ngram 127 | result := HypervectorIn_DI; 128 | for i in 1 to NGRAM_SIZE-1 loop 129 | result := result xor NGram_DP(i); 130 | end loop; -- i 131 | BindNGramOut_D <= result; 132 | end process comb_bind_ngram; 133 | else generate 134 | BindNGramOut_D <= HypervectorIn_DI; 135 | end generate gen_comb_bind_ngram; 136 | 137 | -- NGram Bundling 138 | i_similarity_bundler_1 : similarity_bundler 139 | generic map ( 140 | MAX_BUNDLE_CYCLES => MAX_BUNDLE_CYCLES) 141 | port map ( 142 | Clk_CI => Clk_CI, 143 | Reset_RI => Reset_RI, 144 | BundledHypervectorEN_SI => BundledHypervectorEN_S, 145 | CycleShiftRegEN_SI => CycleShiftRegEN_S, 146 | CycleShiftRegCLR_SI => CycleShiftRegCLR_S, 147 | HypervectorIn_DI => BindNGramOut_D, 148 | HypervectorOut_DO => HypervectorOut_DO); 149 | 150 | ----------------------------------------------------------------------------- 151 | -- Output Signals 152 | ----------------------------------------------------------------------------- 153 | ModeOut_SO <= ModeIn_SP; 154 | LabelOut_DO <= LabelIn_DP; 155 | 156 | ----------------------------------------------------------------------------- 157 | ----------------------------------------------------------------------------- 158 | -- CONTROLLER 159 | ----------------------------------------------------------------------------- 160 | ----------------------------------------------------------------------------- 161 | -- Controller Support Circuits 162 | ----------------------------------------------------------------------------- 163 | -- Label Comparison 164 | ModeChange_S <= '1' when ModeIn_SI /= ModeIn_SP else '0'; 165 | LabelChange_S <= '1' when LabelIn_DI /= LabelIn_DP else '0'; 166 | 167 | -- NGram Filling Counter 168 | gen_ngram_filling_cntr : if NGRAM_SIZE > 1 generate 169 | NGramFull_S <= nor(FillNGramCntr_SP); 170 | FillNGramCntr_SN <= FillNGramCntr_SP - 1; 171 | end generate gen_ngram_filling_cntr; 172 | 173 | ----------------------------------------------------------------------------- 174 | -- Finite State Machine 175 | ----------------------------------------------------------------------------- 176 | -- We need two different implementations of the controller: 177 | -- - One for the case NGram: N = 1 178 | -- - One for the case N > 1 179 | 180 | gen_comb_fsm : if NGRAM_SIZE = 1 generate 181 | comb_fsm : process (FSM_SP, LabelChange_S, ModeChange_S, ModeIn_SI, 182 | ReadyIn_SI, ValidIn_SI) is 183 | begin -- process comb_fsm 184 | -- Default Assignments 185 | FSM_SN <= idle; 186 | 187 | ReadyOut_SO <= '0'; 188 | ValidOut_SO <= '0'; 189 | 190 | InputBuffersEN_S <= '0'; 191 | BundledHypervectorEN_S <= '0'; 192 | CycleShiftRegEN_S <= '0'; 193 | CycleShiftRegCLR_S <= '0'; 194 | 195 | -- Trainsitions and Output 196 | case FSM_SP is 197 | when idle => 198 | if ValidIn_SI = '0' then 199 | FSM_SN <= idle; 200 | ReadyOut_SO <= '1'; 201 | else 202 | if ModeIn_SI = mode_train then 203 | if ModeChange_S = '0' then 204 | if LabelChange_S = '0' then 205 | FSM_SN <= idle; 206 | ReadyOut_SO <= '1'; 207 | InputBuffersEN_S <= '1'; 208 | BundledHypervectorEN_S <= '1'; 209 | CycleShiftRegEN_S <= '1'; 210 | else 211 | FSM_SN <= forward_training when ReadyIn_SI = '0' else accept_input; 212 | ValidOut_SO <= '1'; 213 | CycleShiftRegCLR_S <= '1'; 214 | end if; 215 | else 216 | FSM_SN <= idle; 217 | ReadyOut_SO <= '1'; 218 | InputBuffersEN_S <= '1'; 219 | BundledHypervectorEN_S <= '1'; 220 | CycleShiftRegEN_S <= '1'; 221 | end if; 222 | else 223 | if ModeChange_S = '0' then 224 | FSM_SN <= forward_query; 225 | ReadyOut_SO <= '1'; 226 | InputBuffersEN_S <= '1'; 227 | BundledHypervectorEN_S <= '1'; 228 | else 229 | FSM_SN <= forward_training when ReadyIn_SI = '0' else accept_input; 230 | ValidOut_SO <= '1'; 231 | CycleShiftRegCLR_S <= '1'; 232 | end if; 233 | end if; 234 | end if; 235 | 236 | when forward_training => 237 | ValidOut_SO <= '1'; 238 | if ReadyIn_SI = '0' then 239 | FSM_SN <= forward_training; 240 | else 241 | FSM_SN <= idle when ModeIn_SI = mode_train else forward_query; 242 | ReadyOut_SO <= '1'; 243 | InputBuffersEN_S <= '1'; 244 | BundledHypervectorEN_S <= '1'; 245 | CycleShiftRegEN_S <= '1' when ModeIn_SI = mode_train else '0'; 246 | end if; 247 | 248 | when accept_input => 249 | FSM_SN <= idle when ModeIn_SI = mode_train else forward_query; 250 | ReadyOut_SO <= '1'; 251 | InputBuffersEN_S <= '1'; 252 | BundledHypervectorEN_S <= '1'; 253 | CycleShiftRegEN_S <= '1' when ModeIn_SI = mode_train else '0'; 254 | 255 | when forward_query => 256 | FSM_SN <= forward_query when ReadyIn_SI = '0' else idle; 257 | ValidOut_SO <= '1'; 258 | when others => 259 | null; 260 | end case; 261 | end process comb_fsm; 262 | --------------------------------------------------------------------------- 263 | else generate 264 | comb_fsm : process (FSM_SP, LabelChange_S, ModeChange_S, ModeIn_SI, 265 | NGramFull_S, ReadyIn_SI, ValidIn_SI) is 266 | begin -- process comb_fsm 267 | -- Default Assignments 268 | FSM_SN <= idle; 269 | 270 | ReadyOut_SO <= '0'; 271 | ValidOut_SO <= '0'; 272 | 273 | InputBuffersEN_S <= '0'; 274 | NGramEN_S <= '0'; 275 | BundledHypervectorEN_S <= '0'; 276 | CycleShiftRegEN_S <= '0'; 277 | CycleShiftRegCLR_S <= '0'; 278 | FillNGramCntrEN_S <= '0'; 279 | FillNGramCntrCLR_S <= '0'; 280 | 281 | -- Trainsitions and Output 282 | case FSM_SP is 283 | when idle => 284 | if ValidIn_SI = '0' then 285 | FSM_SN <= idle; 286 | ReadyOut_SO <= '1'; 287 | else 288 | if ModeIn_SI = mode_train then 289 | if ModeChange_S = '0' then 290 | if LabelChange_S = '0' then 291 | FSM_SN <= idle; 292 | ReadyOut_SO <= '1'; 293 | InputBuffersEN_S <= '1'; 294 | NGramEN_S <= '1'; 295 | BundledHypervectorEN_S <= '1' when NGramFull_S = '1' else '0'; 296 | CycleShiftRegEN_S <= '1' when NGramFull_S = '1' else '0'; 297 | FillNGramCntrEN_S <= '1' when NGramFull_S = '0' else '0'; 298 | else 299 | FSM_SN <= forward_training when ReadyIn_SI = '0' else accept_input; 300 | ValidOut_SO <= '1'; 301 | CycleShiftRegCLR_S <= '1'; 302 | FillNGramCntrCLR_S <= '1'; 303 | end if; 304 | else 305 | FSM_SN <= idle; 306 | ReadyOut_SO <= '1'; 307 | InputBuffersEN_S <= '1'; 308 | NGramEN_S <= '1'; 309 | FillNGramCntrEN_S <= '1'; 310 | end if; 311 | else 312 | if ModeChange_S = '0' then 313 | FSM_SN <= forward_query; 314 | ReadyOut_SO <= '1'; 315 | InputBuffersEN_S <= '1'; 316 | NGramEN_S <= '1'; 317 | BundledHypervectorEN_S <= '1'; 318 | else 319 | FSM_SN <= forward_training when ReadyIn_SI = '0' else accept_input; 320 | ValidOut_SO <= '1'; 321 | CycleShiftRegCLR_S <= '1'; 322 | FillNGramCntrCLR_S <= '1'; 323 | end if; 324 | end if; 325 | end if; 326 | 327 | when forward_training => 328 | ValidOut_SO <= '1'; 329 | if ReadyIn_SI = '0' then 330 | FSM_SN <= forward_training; 331 | else 332 | FSM_SN <= idle when ModeIn_SI = mode_train else forward_query; 333 | ReadyOut_SO <= '1'; 334 | InputBuffersEN_S <= '1'; 335 | NGramEN_S <= '1'; 336 | BundledHypervectorEN_S <= '1' when ModeIn_SI = mode_predict else '0'; 337 | FillNGramCntrEN_S <= '1' when ModeIn_SI = mode_train else '0'; 338 | end if; 339 | 340 | when accept_input => 341 | FSM_SN <= idle when ModeIn_SI = mode_train else forward_query; 342 | ReadyOut_SO <= '1'; 343 | InputBuffersEN_S <= '1'; 344 | NGramEN_S <= '1'; 345 | BundledHypervectorEN_S <= '1' when ModeIn_SI = mode_predict else '0'; 346 | FillNGramCntrEN_S <= '1' when ModeIn_SI = mode_train else '0'; 347 | 348 | when forward_query => 349 | FSM_SN <= forward_query when ReadyIn_SI = '0' else idle; 350 | ValidOut_SO <= '1'; 351 | end case; 352 | end process comb_fsm; 353 | end generate gen_comb_fsm; 354 | 355 | ----------------------------------------------------------------------------- 356 | ----------------------------------------------------------------------------- 357 | -- MEMORIES 358 | ----------------------------------------------------------------------------- 359 | ----------------------------------------------------------------------------- 360 | -- Input Buffers 361 | ----------------------------------------------------------------------------- 362 | -- Input Buffers 363 | seq_input_buffers : process (Clk_CI) 364 | begin -- process seq_InputBuffers 365 | if (rising_edge(Clk_CI)) then -- rising clock edge 366 | if Reset_RI = '1' then 367 | ModeIn_SP <= mode_predict; 368 | LabelIn_DP <= (others => '0'); 369 | elsif InputBuffersEN_S = '1' then 370 | ModeIn_SP <= ModeIn_SN; 371 | LabelIn_DP <= LabelIn_DN; 372 | end if; 373 | end if; 374 | end process seq_input_buffers; 375 | 376 | ----------------------------------------------------------------------------- 377 | -- Data Registers 378 | ----------------------------------------------------------------------------- 379 | -- NGram 380 | gen_seq_ngram : if NGRAM_SIZE > 1 generate 381 | seq_ngram : process (Clk_CI) 382 | begin -- process seq_ngram 383 | if (rising_edge(Clk_CI)) then -- rising clock edge 384 | if Reset_RI = '1' then 385 | NGram_DP <= (others => (others => '0')); 386 | elsif NGramEN_S = '1' then 387 | NGram_DP <= NGram_DN; 388 | end if; 389 | end if; 390 | end process seq_ngram; 391 | end generate gen_seq_ngram; 392 | 393 | ----------------------------------------------------------------------------- 394 | -- Control Registers 395 | ----------------------------------------------------------------------------- 396 | -- Fill NGram Counter 397 | gen_seq_fill_ngram_cntr : if NGRAM_SIZE > 1 generate 398 | seq_fill_ngram_cntr : process (Clk_CI) 399 | begin -- process seq_fill_ngram_cntr 400 | if (rising_edge(Clk_CI)) then -- rising clock edge 401 | if (Reset_RI or FillNGramCntrCLR_S) = '1' then 402 | FillNGramCntr_SP <= to_unsigned(NGRAM_SIZE-1, FILL_NGRAM_COUNTER_WIDTH); -- TODO: make sure this is the correct number to load 403 | elsif FillNGramCntrEN_S = '1' then 404 | FillNGramCntr_SP <= FillNGramCntr_SN; 405 | end if; 406 | end if; 407 | end process seq_fill_ngram_cntr; 408 | end generate gen_seq_fill_ngram_cntr; 409 | 410 | -- Finite State Machine 411 | seq_fsm : process (Clk_CI) 412 | begin -- process seq_fsm 413 | if (rising_edge(Clk_CI)) then -- rising clock edge 414 | if Reset_RI = '1' then 415 | FSM_SP <= idle; 416 | else 417 | FSM_SP <= FSM_SN; 418 | end if; 419 | end if; 420 | end process seq_fsm; 421 | 422 | 423 | end b2b; 424 | -------------------------------------------------------------------------------- /vhdl/source/temporal_encoder/temporal_encoder_bc_arc.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Temporal Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : temporal_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encoder. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | -- Abbreviations: 31 | -- *N : Only if NGRAM > 1 32 | -- *B : Only if Bundle Counter is used 33 | -- *S : Only if Similarity Counter is used 34 | ------------------------------------------------------------------------------- 35 | 36 | library ieee; 37 | use ieee.std_logic_1164.all; 38 | use ieee.numeric_std.all; 39 | use work.hdc_pkg.all; 40 | 41 | ------------------------------------------------------------------------------- 42 | 43 | architecture bc of temporal_encoder is 44 | 45 | ----------------------------------------------------------------------------- 46 | -- Constants 47 | ----------------------------------------------------------------------------- 48 | constant FILL_NGRAM_COUNTER_WIDTH : integer := num2bits(NGRAM_SIZE); 49 | 50 | ----------------------------------------------------------------------------- 51 | -- Signals 52 | ----------------------------------------------------------------------------- 53 | -- Input Buffers 54 | signal ModeIn_SP, ModeIn_SN : std_logic; 55 | signal LabelIn_DP, LabelIn_DN : std_logic_vector(LABEL_WIDTH-1 downto 0); 56 | 57 | -- Data Registers 58 | -- - Array starts at 1 to illustrate the latency (t-1, t-2, etc...) 59 | signal NGram_DP, NGram_DN : hypervector_array(1 to NGRAM_SIZE-1)(0 to HV_DIMENSION-1); -- *N 60 | 61 | -- Control Registers 62 | type fsm_states is (idle, forward_training, accept_input, forward_query); 63 | signal FSM_SP, FSM_SN : fsm_states; 64 | signal FillNGramCntr_SP, FillNGramCntr_SN : unsigned(FILL_NGRAM_COUNTER_WIDTH-1 downto 0); -- *N 65 | signal NGramFullMemory_SP, NGramFullMemory_SN : std_logic; -- *N 66 | 67 | -- Datapath Signals 68 | signal BindNGramOut_D : hypervector(0 to HV_DIMENSION-1); 69 | 70 | -- Status Signals 71 | signal ModeChange_S : std_logic; 72 | signal LabelChange_S : std_logic; 73 | signal NGramFull_S : std_logic; -- *N 74 | signal BundleCounterFed_S : std_logic; -- *N 75 | 76 | -- Control Signals 77 | signal InputBuffersEN_S : std_logic; 78 | signal NGramEN_S : std_logic; -- *N 79 | signal BundleCounterEN_S : std_logic; 80 | signal FirstHypervector_S : std_logic; 81 | signal FillNGramCntrEN_S : std_logic; -- *N 82 | signal FillNGramCntrCLR_S : std_logic; -- *N 83 | signal NGramFullMemoryEN_S : std_logic; -- *N 84 | 85 | ----------------------------------------------------------------------------- 86 | -- Components 87 | ----------------------------------------------------------------------------- 88 | component bundle_counter is 89 | generic ( 90 | WIDTH : integer); 91 | port ( 92 | Clk_CI : in std_logic; 93 | Reset_RI : in std_logic; 94 | Enable_SI : in std_logic; 95 | FirstHypervector_SI : in std_logic; 96 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 97 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1)); 98 | end component bundle_counter; 99 | 100 | begin 101 | 102 | ----------------------------------------------------------------------------- 103 | ----------------------------------------------------------------------------- 104 | -- DATAPATH 105 | ----------------------------------------------------------------------------- 106 | ----------------------------------------------------------------------------- 107 | -- Input Signals 108 | ----------------------------------------------------------------------------- 109 | ModeIn_SN <= ModeIn_SI; 110 | LabelIn_DN <= LabelIn_DI; 111 | 112 | ----------------------------------------------------------------------------- 113 | -- NGram 114 | ----------------------------------------------------------------------------- 115 | -- NGram Permutation 116 | gen_asgn_ngram_1 : if NGRAM_SIZE > 1 generate 117 | NGram_DN(1) <= HypervectorIn_DI ror 1; 118 | gen_asgn_ngram_2 : for i in 2 to NGRAM_SIZE-1 generate 119 | NGram_DN(i) <= NGram_DP(i-1) ror 1; 120 | end generate gen_asgn_ngram_2; 121 | end generate gen_asgn_ngram_1; 122 | 123 | -- NGram Binding 124 | gen_comb_bind_ngram : if NGRAM_SIZE > 1 generate 125 | comb_bind_ngram : process (HypervectorIn_DI, NGram_DP) is 126 | variable result : hypervector(0 to HV_DIMENSION-1) := (others => '0'); 127 | begin -- process comb_bind_ngram 128 | result := HypervectorIn_DI; 129 | for i in 1 to NGRAM_SIZE-1 loop 130 | result := result xor NGram_DP(i); 131 | end loop; -- i 132 | BindNGramOut_D <= result; 133 | end process comb_bind_ngram; 134 | else generate 135 | BindNGramOut_D <= HypervectorIn_DI; 136 | end generate gen_comb_bind_ngram; 137 | 138 | -- NGram Bundling 139 | i_bundle_counter_1 : bundle_counter 140 | generic map ( 141 | WIDTH => BUNDLE_NGRAMS_WIDTH) 142 | port map ( 143 | Clk_CI => Clk_CI, 144 | Reset_RI => Reset_RI, 145 | Enable_SI => BundleCounterEN_S, 146 | FirstHypervector_SI => FirstHypervector_S, 147 | HypervectorIn_DI => BindNGramOut_D, 148 | HypervectorOut_DO => HypervectorOut_DO); 149 | 150 | ----------------------------------------------------------------------------- 151 | -- Output Signals 152 | ----------------------------------------------------------------------------- 153 | ModeOut_SO <= ModeIn_SP; 154 | LabelOut_DO <= LabelIn_DP; 155 | 156 | ----------------------------------------------------------------------------- 157 | ----------------------------------------------------------------------------- 158 | -- CONTROLLER 159 | ----------------------------------------------------------------------------- 160 | ----------------------------------------------------------------------------- 161 | -- Controller Support Circuits 162 | ----------------------------------------------------------------------------- 163 | -- Label Comparison 164 | ModeChange_S <= '1' when ModeIn_SI /= ModeIn_SP else '0'; 165 | LabelChange_S <= '1' when LabelIn_DI /= LabelIn_DP else '0'; 166 | 167 | -- NGram Filling Counter 168 | gen_ngram_filling_cntr : if NGRAM_SIZE > 1 generate 169 | NGramFull_S <= nor(FillNGramCntr_SP); 170 | FillNGramCntr_SN <= FillNGramCntr_SP - 1; 171 | end generate gen_ngram_filling_cntr; 172 | 173 | -- Full NGram Memory 174 | gen_full_ngram_memory : if (NGRAM_SIZE > 1) generate 175 | BundleCounterFed_S <= '0' when NGramFull_S = '1' and NGramFullMemory_SP = '0' else '1'; 176 | NGramFullMemory_SN <= NGramFull_S; 177 | end generate gen_full_ngram_memory; 178 | 179 | ----------------------------------------------------------------------------- 180 | -- Finite State Machine 181 | ----------------------------------------------------------------------------- 182 | -- We need two different implementations of the controller: 183 | -- - One for the case NGram: N = 1 184 | -- - One for the case N > 1 185 | 186 | gen_comb_fsm : if NGRAM_SIZE = 1 generate 187 | comb_fsm : process (FSM_SP, LabelChange_S, ModeChange_S, ModeIn_SI, 188 | ReadyIn_SI, ValidIn_SI) is 189 | begin -- process comb_fsm 190 | -- Default Assignments 191 | FSM_SN <= idle; 192 | 193 | ReadyOut_SO <= '0'; 194 | ValidOut_SO <= '0'; 195 | 196 | InputBuffersEN_S <= '0'; 197 | BundleCounterEN_S <= '0'; 198 | FirstHypervector_S <= '0'; 199 | 200 | -- Trainsitions and Output 201 | case FSM_SP is 202 | when idle => 203 | if ValidIn_SI = '0' then 204 | FSM_SN <= idle; 205 | ReadyOut_SO <= '1'; 206 | else 207 | if ModeIn_SI = mode_train then 208 | FSM_SN <= idle; 209 | if ModeChange_S = '0' then 210 | if LabelChange_S = '0' then 211 | ReadyOut_SO <= '1'; 212 | InputBuffersEN_S <= '1'; 213 | BundleCounterEN_S <= '1'; 214 | else 215 | ValidOut_SO <= '1'; 216 | if ReadyIn_SI = '1' then 217 | ReadyOut_SO <= '1'; 218 | InputBuffersEN_S <= '1'; 219 | BundleCounterEN_S <= '1'; 220 | FirstHypervector_S <= '1'; 221 | end if; 222 | end if; 223 | else 224 | ReadyOut_SO <= '1'; 225 | InputBuffersEN_S <= '1'; 226 | BundleCounterEN_S <= '1'; 227 | FirstHypervector_S <= '1'; 228 | end if; 229 | else 230 | if ModeChange_S = '0' then 231 | FSM_SN <= forward_query; 232 | ReadyOut_SO <= '1'; 233 | InputBuffersEN_S <= '1'; 234 | BundleCounterEN_S <= '1'; 235 | FirstHypervector_S <= '1'; 236 | else 237 | ValidOut_SO <= '1'; 238 | if ReadyIn_SI = '0' then 239 | FSM_SN <= idle; 240 | else 241 | FSM_SN <= forward_query; 242 | ReadyOut_SO <= '1'; 243 | InputBuffersEN_S <= '1'; 244 | BundleCounterEN_S <= '1'; 245 | FirstHypervector_S <= '1'; 246 | end if; 247 | end if; 248 | end if; 249 | end if; 250 | 251 | when forward_query => 252 | FSM_SN <= forward_query when ReadyIn_SI = '0' else idle; 253 | ValidOut_SO <= '1'; 254 | 255 | when others => 256 | null; 257 | end case; 258 | end process comb_fsm; 259 | --------------------------------------------------------------------------- 260 | else generate 261 | comb_fsm : process (BundleCounterFed_S, FSM_SP, LabelChange_S, 262 | ModeChange_S, ModeIn_SI, NGramFull_S, ReadyIn_SI, 263 | ValidIn_SI) is 264 | begin -- process comb_fsm 265 | -- Default Assignments 266 | FSM_SN <= idle; 267 | 268 | ReadyOut_SO <= '0'; 269 | ValidOut_SO <= '0'; 270 | 271 | InputBuffersEN_S <= '0'; 272 | NGramEN_S <= '0'; 273 | BundleCounterEN_S <= '0'; 274 | FirstHypervector_S <= '0'; 275 | FillNGramCntrEN_S <= '0'; 276 | FillNGramCntrCLR_S <= '0'; 277 | NGramFullMemoryEN_S <= '0'; 278 | 279 | -- Trainsitions and Output 280 | case FSM_SP is 281 | when idle => 282 | if ValidIn_SI = '0' then 283 | FSM_SN <= idle; 284 | ReadyOut_SO <= '1'; 285 | else 286 | if ModeIn_SI = mode_train then 287 | if ModeChange_S = '0' then 288 | if LabelChange_S = '0' then 289 | FSM_SN <= idle; 290 | ReadyOut_SO <= '1'; 291 | InputBuffersEN_S <= '1'; 292 | NGramEN_S <= '1'; 293 | NGramFullMemoryEN_S <= '1'; 294 | if NGramFull_S = '0' then 295 | FillNGramCntrEN_S <= '1'; 296 | else 297 | BundleCounterEN_S <= '1'; 298 | FirstHypervector_S <= '1' when BundleCounterFed_S = '0' else '0'; 299 | end if; 300 | else 301 | FSM_SN <= forward_training when ReadyIn_SI = '0' else accept_input; 302 | ValidOut_SO <= '1'; 303 | FillNGramCntrCLR_S <= '1'; 304 | end if; 305 | else 306 | FSM_SN <= idle; 307 | ReadyOut_SO <= '1'; 308 | InputBuffersEN_S <= '1'; 309 | NGramEN_S <= '1'; 310 | FillNGramCntrEN_S <= '1'; 311 | NGramFullMemoryEN_S <= '1'; 312 | end if; 313 | else 314 | if ModeChange_S = '0' then 315 | FSM_SN <= forward_query; 316 | ReadyOut_SO <= '1'; 317 | InputBuffersEN_S <= '1'; 318 | NGramEN_S <= '1'; 319 | BundleCounterEN_S <= '1'; 320 | FirstHypervector_S <= '1'; 321 | else 322 | FSM_SN <= idle when ReadyIn_SI = '0' else forward_query; 323 | ValidOut_SO <= '1'; 324 | if ReadyIn_SI = '1' then 325 | ReadyOut_SO <= '1'; 326 | InputBuffersEN_S <= '1'; 327 | NGramEN_S <= '1'; 328 | BundleCounterEN_S <= '1'; 329 | FirstHypervector_S <= '1'; 330 | FillNGramCntrCLR_S <= '1'; 331 | end if; 332 | end if; 333 | end if; 334 | end if; 335 | 336 | when forward_training => 337 | FSM_SN <= forward_training when ReadyIn_SI = '0' else idle; 338 | ValidOut_SO <= '1'; 339 | if ReadyIn_SI = '1' then 340 | ReadyOut_SO <= '1'; 341 | InputBuffersEN_S <= '1'; 342 | NGramEN_S <= '1'; 343 | FillNGramCntrEN_S <= '1'; 344 | NGramFullMemoryEN_S <= '1'; 345 | end if; 346 | 347 | when accept_input => 348 | FSM_SN <= idle; 349 | ReadyOut_SO <= '1'; 350 | InputBuffersEN_S <= '1'; 351 | NGramEN_S <= '1'; 352 | FillNGramCntrEN_S <= '1'; 353 | NGramFullMemoryEN_S <= '1'; 354 | 355 | when forward_query => 356 | FSM_SN <= forward_query when ReadyIn_SI = '0' else idle; 357 | ValidOut_SO <= '1'; 358 | when others => 359 | null; 360 | end case; 361 | end process comb_fsm; 362 | end generate gen_comb_fsm; 363 | 364 | ----------------------------------------------------------------------------- 365 | ----------------------------------------------------------------------------- 366 | -- MEMORIES 367 | ----------------------------------------------------------------------------- 368 | ----------------------------------------------------------------------------- 369 | -- Input Buffers 370 | ----------------------------------------------------------------------------- 371 | -- Input Buffers 372 | seq_input_buffers : process (Clk_CI) 373 | begin -- process seq_InputBuffers 374 | if (rising_edge(Clk_CI)) then -- rising clock edge 375 | if Reset_RI = '1' then 376 | ModeIn_SP <= mode_predict; 377 | LabelIn_DP <= (others => '0'); 378 | elsif InputBuffersEN_S = '1' then 379 | ModeIn_SP <= ModeIn_SN; 380 | LabelIn_DP <= LabelIn_DN; 381 | end if; 382 | end if; 383 | end process seq_input_buffers; 384 | 385 | ----------------------------------------------------------------------------- 386 | -- Data Registers 387 | ----------------------------------------------------------------------------- 388 | -- NGram 389 | gen_seq_ngram : if NGRAM_SIZE > 1 generate 390 | seq_ngram : process (Clk_CI) 391 | begin -- process seq_ngram 392 | if (rising_edge(Clk_CI)) then -- rising clock edge 393 | if Reset_RI = '1' then 394 | NGram_DP <= (others => (others => '0')); 395 | elsif NGramEN_S = '1' then 396 | NGram_DP <= NGram_DN; 397 | end if; 398 | end if; 399 | end process seq_ngram; 400 | end generate gen_seq_ngram; 401 | 402 | ----------------------------------------------------------------------------- 403 | -- Control Registers 404 | ----------------------------------------------------------------------------- 405 | -- Fill NGram Counter 406 | gen_seq_fill_ngram_cntr : if NGRAM_SIZE > 1 generate 407 | seq_fill_ngram_cntr : process (Clk_CI) 408 | begin -- process seq_fill_ngram_cntr 409 | if (rising_edge(Clk_CI)) then -- rising clock edge 410 | if (Reset_RI or FillNGramCntrCLR_S) = '1' then 411 | FillNGramCntr_SP <= to_unsigned(NGRAM_SIZE-1, FILL_NGRAM_COUNTER_WIDTH); -- TODO: make sure this is the correct number to load 412 | elsif FillNGramCntrEN_S = '1' then 413 | FillNGramCntr_SP <= FillNGramCntr_SN; 414 | end if; 415 | end if; 416 | end process seq_fill_ngram_cntr; 417 | end generate gen_seq_fill_ngram_cntr; 418 | 419 | -- NGram Full Memory 420 | 421 | gen_seq_ngram_full_memory : if (NGRAM_SIZE > 1) generate 422 | seq_ngram_full_memory : process (Clk_CI) 423 | begin -- process seq_ngram_full_memory 424 | if (rising_edge(Clk_CI)) then -- rising clock edge 425 | if Reset_RI = '1' then 426 | NGramFullMemory_SP <= '0'; 427 | elsif NGramFullMemoryEN_S = '1' then 428 | NGramFullMemory_SP <= NGramFullMemory_SN; 429 | end if; 430 | end if; 431 | end process seq_ngram_full_memory; 432 | end generate gen_seq_ngram_full_memory; 433 | 434 | -- Finite State Machine 435 | seq_fsm : process (Clk_CI) 436 | begin -- process seq_fsm 437 | if (rising_edge(Clk_CI)) then -- rising clock edge 438 | if Reset_RI = '1' then 439 | FSM_SP <= idle; 440 | else 441 | FSM_SP <= FSM_SN; 442 | end if; 443 | end if; 444 | end process seq_fsm; 445 | 446 | 447 | end bc; 448 | -------------------------------------------------------------------------------- /vhdl/source/temporal_encoder/temporal_encoder_ent.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Title : Temporal Encoder 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : temporal_encoder_ent_arc.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-06-15 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Entity and architecture of the spatial encoder. 23 | ------------------------------------------------------------------------------- 24 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 25 | ------------------------------------------------------------------------------- 26 | -- Revisions : 27 | -- Date Version Author Description 28 | -- 2018 1.0 schmucma Created 29 | ------------------------------------------------------------------------------- 30 | -- Abbreviations: 31 | -- *N : Only if NGRAM > 1 32 | -- *B : Only if Bundle Counter is used 33 | -- *S : Only if Similarity Counter is used 34 | ------------------------------------------------------------------------------- 35 | 36 | library ieee; 37 | use ieee.std_logic_1164.all; 38 | use ieee.numeric_std.all; 39 | use work.hdc_pkg.all; 40 | 41 | ------------------------------------------------------------------------------- 42 | 43 | entity temporal_encoder is 44 | port ( 45 | -- Global Ports 46 | Clk_CI : in std_logic; 47 | Reset_RI : in std_logic; 48 | 49 | -- Handshake Ports 50 | ValidIn_SI : in std_logic; 51 | ReadyOut_SO : out std_logic; 52 | ReadyIn_SI : in std_logic; 53 | ValidOut_SO : out std_logic; 54 | 55 | -- Input Ports 56 | ModeIn_SI : in std_logic; 57 | LabelIn_DI : in std_logic_vector(LABEL_WIDTH-1 downto 0); 58 | HypervectorIn_DI : in hypervector(0 to HV_DIMENSION-1); 59 | 60 | -- Output Ports 61 | ModeOut_SO : out std_logic; 62 | LabelOut_DO : out std_logic_vector(LABEL_WIDTH-1 downto 0); 63 | HypervectorOut_DO : out hypervector(0 to HV_DIMENSION-1) 64 | ); 65 | end temporal_encoder; 66 | -------------------------------------------------------------------------------- /vhdl/templates/hdc_baseline_pkg_temp.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------ 12 | -- Title : HDC Baseline Package 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : hdc_baseline_pkg.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-01-02 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Provides the memories and functions required by the 23 | -- baseline architecture. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use ieee.math_real.all; 36 | use work.hdc_pkg.all; 37 | 38 | ------------------------------------------------------------------------------- 39 | 40 | package hdc_baseline_pkg is 41 | 42 | ----------------------------------------------------------------------------- 43 | -- Function Declarations 44 | ----------------------------------------------------------------------------- 45 | function majority (hvarray : hypervector_array) return hypervector; 46 | 47 | ----------------------------------------------------------------------------- 48 | -- Constant Declarations 49 | ----------------------------------------------------------------------------- 50 | constant ITEM_MEMORY : hypervector_array(0 to INPUT_CHANNELS-1)(0 to HV_DIMENSION-1) := ( 51 | -- This line will be overwritten by MATLAB 52 | ); 53 | 54 | constant CONTINUOUS_ITEM_MEMORY : hypervector_array(0 to INPUT_QUANTIZATION-1)(0 to HV_DIMENSION-1) := ( 55 | -- This line will be overwritten by MATLAB 56 | ); 57 | 58 | end hdc_baseline_pkg; 59 | 60 | ------------------------------------------------------------------------------- 61 | 62 | package body hdc_baseline_pkg is 63 | 64 | ----------------------------------------------------------------------------- 65 | -- Function Definitions 66 | ----------------------------------------------------------------------------- 67 | 68 | function majority (hvarray : hypervector_array) return hypervector is 69 | variable sum : integer := 0; 70 | variable result : hypervector(0 to HV_DIMENSION-1) := (others => '0'); 71 | begin 72 | sum := 0; 73 | for i in 0 to HV_DIMENSION-1 loop 74 | sum := logic_to_integer(hvarray(0)(i)); 75 | for j in 1 to hvarray'high loop 76 | if hvarray(j)(i) = '1' then 77 | sum := sum + 1; 78 | else 79 | sum := sum - 1; 80 | end if; 81 | end loop; -- j 82 | if sum > 0 then 83 | result(i) := '1'; 84 | else 85 | result(i) := '0'; 86 | end if; 87 | end loop; -- i 88 | return result; 89 | end majority; 90 | 91 | end hdc_baseline_pkg; 92 | -------------------------------------------------------------------------------- /vhdl/templates/hdc_enhanced_pkg_temp.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------ 12 | -- Title : HDC Enhanced Package 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : hdc_enhanced_pkg.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-01-02 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Provides seed vectors and connectivity matrices for the 23 | -- enhanced architecture. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2017 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use ieee.math_real.all; 36 | use work.hdc_pkg.all; 37 | 38 | ------------------------------------------------------------------------------- 39 | 40 | package hdc_enhanced_pkg is 41 | 42 | ----------------------------------------------------------------------------- 43 | -- Function Declarations 44 | ----------------------------------------------------------------------------- 45 | 46 | 47 | ----------------------------------------------------------------------------- 48 | -- Constant Declarations 49 | ----------------------------------------------------------------------------- 50 | constant NHOT_LUT : std_logic_vector_array(0 to INPUT_QUANTIZATION-1)(0 to INPUT_QUANTIZATION-2) := ( 51 | -- This line will be overwritten by MATLAB 52 | ); 53 | 54 | constant IM_SEED : hypervector(0 to HV_DIMENSION-1) := ( 55 | -- This line will be overwritten by MATLAB 56 | ); 57 | 58 | constant CIM_SEED : hypervector(0 to HV_DIMENSION-1) := ( 59 | -- This line will be overwritten by MATLAB 60 | ); 61 | 62 | constant IM_CONNECTIVITY_MATRIX : hypervector_array(0 to INPUT_CHANNELS-1)(0 to HV_DIMENSION-1) := ( 63 | -- This line will be overwritten by MATLAB 64 | ); 65 | 66 | constant CIM_CONNECTIVITY_MATRIX : hypervector_array(0 to INPUT_QUANTIZATION-2)(0 to HV_DIMENSION-1) := ( 67 | -- This line will be overwritten by MATLAB 68 | ); 69 | 70 | constant BUNDLE_CONNECTIVITY_MATRIX : hypervector_array(0 to MAX_BUNDLE_CYCLES-1)(0 to HV_DIMENSION-1) := ( 71 | -- This line will be overwritten by MATLAB 72 | ); 73 | 74 | end hdc_enhanced_pkg; 75 | 76 | ------------------------------------------------------------------------------- 77 | 78 | package body hdc_enhanced_pkg is 79 | 80 | 81 | 82 | end hdc_enhanced_pkg; 83 | -------------------------------------------------------------------------------- /vhdl/templates/hdc_pkg_temp.vhd: -------------------------------------------------------------------------------- 1 | -- Copyright 2018 ETH Zurich 2 | -- Copyright and related rights are licensed under the Solderpad Hardware 3 | -- License, Version 0.51 (the “License”); you may not use this file except in 4 | -- compliance with the License. You may obtain a copy of the License at 5 | -- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | -- or agreed to in writing, software, hardware and materials distributed under 7 | -- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | -- CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | -- specific language governing permissions and limitations under the License. 10 | 11 | ------------------------------------------------------------------------------ 12 | -- Title : Hyperdimensional Computing Package 13 | -- Project : Semester Thesis I 14 | ------------------------------------------------------------------------------- 15 | -- File : hdc_pkg.vhd 16 | -- Author : Manuel Schmuck 17 | -- Company : Integrated Systems Laboratory, ETH Zurich 18 | -- Created : 2017-09-30 19 | -- Last update: 2018-01-02 20 | -- Platform : ModelSim (simulation), Vivado (synthesis) 21 | ------------------------------------------------------------------------------- 22 | -- Description: Provides parameters and constants required for hyperdimensional 23 | -- computing classifiers. 24 | ------------------------------------------------------------------------------- 25 | -- Copyright (c) 2018 Integrated Systems Laboratory, ETH Zurich 26 | ------------------------------------------------------------------------------- 27 | -- Revisions : 28 | -- Date Version Author Description 29 | -- 2018 1.0 schmucma Created 30 | ------------------------------------------------------------------------------- 31 | 32 | library ieee; 33 | use ieee.std_logic_1164.all; 34 | use ieee.numeric_std.all; 35 | use ieee.math_real.all; 36 | 37 | ------------------------------------------------------------------------------- 38 | 39 | package hdc_pkg is 40 | 41 | ----------------------------------------------------------------------------- 42 | -- Data Type Declarations 43 | ----------------------------------------------------------------------------- 44 | type std_logic_vector_array is array (integer range <>) of std_logic_vector; 45 | type unsigned_array is array (integer range <>) of unsigned; 46 | type signed_array is array (integer range <>) of signed; 47 | 48 | subtype hypervector is std_logic_vector; 49 | subtype hypervector_arith is unsigned; 50 | subtype hypervector_array is std_logic_vector_array; 51 | subtype hypervector_array_arith is unsigned_array; 52 | 53 | ----------------------------------------------------------------------------- 54 | -- Function Declarations 55 | ----------------------------------------------------------------------------- 56 | function num2bits (number : integer) return integer; 57 | function logic_to_integer (logic : std_logic) return integer; 58 | 59 | ----------------------------------------------------------------------------- 60 | -- Constant Declarations 61 | ----------------------------------------------------------------------------- 62 | -- Parameters 63 | constant HV_DIMENSION : integer := 2**13; 64 | constant INPUT_CHANNELS : integer := 4; 65 | constant INPUT_QUANTIZATION : integer := 21; 66 | constant NGRAM_SIZE : integer := 1; 67 | constant CLASSES : integer := 5; 68 | constant BUNDLE_CHANNELS_WIDTH : integer := 3; 69 | constant BUNDLE_NGRAMS_WIDTH : integer := 3; 70 | constant MAX_BUNDLE_CYCLES : integer := 2**8; 71 | constant AM_BLOCK_WIDTH : integer := 2**4; 72 | constant NGRAM_BUNDLER_MODE : string := "similarity"; 73 | 74 | -- Deferred Parameters 75 | constant LABEL_WIDTH : integer; 76 | constant CHANNEL_WIDTH : integer; 77 | constant DISTANCE_WIDTH : integer; 78 | constant NGRAM_WIDTH : integer; 79 | constant AM_BLOCKS : integer; 80 | 81 | -- Aliases 82 | constant mode_train : std_logic := '0'; 83 | constant mode_predict : std_logic := '1'; 84 | constant mode_store : std_logic := '0'; 85 | constant mode_shift : std_logic := '1'; 86 | constant mode_similarity : string := "similarity"; 87 | constant mode_counter : string := "counter"; 88 | 89 | end hdc_pkg; 90 | 91 | ------------------------------------------------------------------------------- 92 | 93 | package body hdc_pkg is 94 | 95 | ----------------------------------------------------------------------------- 96 | -- Function Definitions 97 | ----------------------------------------------------------------------------- 98 | function num2bits (number : integer) return integer is 99 | begin 100 | if number <= 1 then 101 | return 0; 102 | else 103 | return integer(ceil(log2(real(number)))); 104 | end if; 105 | end num2bits; 106 | 107 | function logic_to_integer (logic : std_logic) return integer is 108 | begin 109 | if logic = '1' then 110 | return 1; 111 | else 112 | return 0; 113 | end if; 114 | end logic_to_integer; 115 | 116 | ----------------------------------------------------------------------------- 117 | -- Deferred Constants 118 | ----------------------------------------------------------------------------- 119 | constant LABEL_WIDTH : integer := num2bits(CLASSES); 120 | constant CHANNEL_WIDTH : integer := num2bits(INPUT_QUANTIZATION); 121 | constant DISTANCE_WIDTH : integer := num2bits(HV_DIMENSION); 122 | constant NGRAM_WIDTH : integer := num2bits(NGRAM_SIZE); 123 | constant AM_BLOCKS : integer := HV_DIMENSION / AM_BLOCK_WIDTH; 124 | 125 | 126 | end hdc_pkg; 127 | --------------------------------------------------------------------------------