├── README.md ├── Synopsys_uvm1.2_lab_guide.pdf ├── THE_UVM_PRIMER_CODE_EXAMPLES_1.0.zip ├── UVM-18002-2017-11tar.gz ├── UVMPrimer.zip ├── UVM实战 └── example_and_uvm_source_code.tar.gz ├── armcortexm0 ├── AT510-MN-80001-r2p0-00rel0.tgz └── 下载地址.txt ├── armcortexm3 └── AT421-MN-80001-r0p0-02rel0.tgz ├── ces_sva_2015.09.tar.gz ├── ces_svtb_2016.06.tar.gz ├── ces_uvm-1.2_2016.06.zip ├── dc ├── dc.tcl └── synopsys_dc.setup ├── eetop.cn_h265enc_v2.0.zip ├── uvm-1.1d.zip ├── uvm-1.2.zip ├── 《System Verilog for design》 └── sv-design_book_examples.tar └── 芯片验证漫游指南附赠源代码.zip /README.md: -------------------------------------------------------------------------------- 1 | # ExamplesCode 2 | SystemVerilog、Verilog、UVM 3 | -------------------------------------------------------------------------------- /Synopsys_uvm1.2_lab_guide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/Synopsys_uvm1.2_lab_guide.pdf -------------------------------------------------------------------------------- /THE_UVM_PRIMER_CODE_EXAMPLES_1.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/THE_UVM_PRIMER_CODE_EXAMPLES_1.0.zip -------------------------------------------------------------------------------- /UVM-18002-2017-11tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/UVM-18002-2017-11tar.gz -------------------------------------------------------------------------------- /UVMPrimer.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/UVMPrimer.zip -------------------------------------------------------------------------------- /UVM实战/example_and_uvm_source_code.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/UVM实战/example_and_uvm_source_code.tar.gz -------------------------------------------------------------------------------- /armcortexm0/AT510-MN-80001-r2p0-00rel0.tgz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/armcortexm0/AT510-MN-80001-r2p0-00rel0.tgz -------------------------------------------------------------------------------- /armcortexm0/下载地址.txt: -------------------------------------------------------------------------------- 1 | https://developer.arm.com/ip-products/designstart/eval -------------------------------------------------------------------------------- /armcortexm3/AT421-MN-80001-r0p0-02rel0.tgz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/armcortexm3/AT421-MN-80001-r0p0-02rel0.tgz -------------------------------------------------------------------------------- /ces_sva_2015.09.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/ces_sva_2015.09.tar.gz -------------------------------------------------------------------------------- /ces_svtb_2016.06.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/ces_svtb_2016.06.tar.gz -------------------------------------------------------------------------------- /ces_uvm-1.2_2016.06.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/ces_uvm-1.2_2016.06.zip -------------------------------------------------------------------------------- /dc/dc.tcl: -------------------------------------------------------------------------------- 1 | #2019-01-15 2 | #dyk 3 | #description: 4 | # design compiler scripts 5 | # 6 | remove_design -design 7 | 8 | source ./scripts/synopsys_dc.setup 9 | set CLOCK_NAME blif_clk_net 10 | #set CLOCK_NAME iccad_clk 11 | #set DESIGN_NAME s38584_bench 12 | set DESIGN_NAME sequencial_fsm 13 | ##design name is same with top module's name 14 | set DESIGN $DESIGN_NAME 15 | set HAVCLK "True" 16 | set DC_PATH ["pwd"] 17 | set TF_PATH "./../ref/tf" 18 | set TLUPLUS_PATH "./../ref/tluplus" 19 | set MW_LIB_PATH "./../ref/mw_lib" 20 | set LEF_PATH "./../lef" 21 | set DC_OUTPUTS "./outputs" 22 | set OUTPUTS_PATH $DC_PATH/outputs/$DESIGN_NAME 23 | set LOGS_PATH $DC_PATH/logs/$DESIGN_NAME 24 | set REPORTS_PATH $DC_PATH/reports/$DESIGN_NAME 25 | ################################################ 26 | ## mkdir for design 27 | ################################################ 28 | if {![file exists $OUTPUTS_PATH]} { file mkdir $OUTPUTS_PATH } 29 | if {![file exists $LOGS_PATH]} { file mkdir $LOGS_PATH } 30 | if {![file exists $REPORTS_PATH]} { file mkdir $REPORTS_PATH } 31 | 32 | 33 | 34 | 35 | set hdlin_translate_off_skip_text "true" 36 | set verilogout_no_tri "true" 37 | set default_schematic_options "-size infinite" 38 | set write_name_nets_same_as_ports "true" 39 | 40 | #set INPUT_PIN "ZN" 41 | set DRIVE_CELL "scc40nll_hdc40_hvt_tt_v1p1_25c_basic/CLKBUFV20_8TH40" 42 | set DRIVE_PIN "Z" 43 | 44 | set REF_LOAD "scc40nll_hdc40_hvt_tt_v1p1_25c_basic/CLKBUFV20_8TH40/I" 45 | 46 | set MAX_INPUT_DELAY 0.2 47 | set MIN_INPUT_DELAY 0.1 48 | set MAX_OUTPUT_DELAY 0.2 49 | set MIN_OUTPUT_DELAY 0.1 50 | set CLOCK_UNCERTAINTY 0.1 51 | 52 | set MAX_TRANSITION 0.15 53 | set MAX_FANOUT 10 54 | set PERIOD 1 55 | ### read design 56 | analyze -format verilog ./files/filelist.v 57 | elaborate $DESIGN > $LOGS_PATH/read_design.log 58 | 59 | current_design $DESIGN 60 | link 61 | 62 | #set MAX_TRANSITION [get_attribute $DRIVING_CELL/$DRIVE_PIN max_transition] 63 | set MAX_CAPACITANCE [get_attribute $DRIVE_CELL/$DRIVE_PIN max_capacitance] 64 | 65 | 66 | ### set operating condition 67 | # 68 | #set_min_library scc018ug_uhd_rvt_ff_v1p32_0c_basic.db -min_version \ 69 | # scc018ug_uhd_rvt_ss_v1p08_125c_basic.db 70 | #set_operating_conditions -min ff_v1p32_0c \ 71 | # -min_library scc018ug_uhd_rvt_ff_v1p32_0c_basic \ 72 | # -max ss_v1p08_125c \ 73 | # -max_library scc018ug_uhd_rvt_ss_v1p08_125c_basic \ 74 | # -analysis_type bc_wc 75 | set_operating_conditions tt_v1p1_25c -lib scc40nll_hdc40_hvt_tt_v1p1_25c_basic 76 | ###setting wire load model 77 | # 78 | #set auto_wire_load_selection false 79 | #set_wire_load_mode top 80 | #set_wire_load_model -name "4000" [current_design] 81 | 82 | ###setting I/O characteristic 83 | # 84 | 85 | set_load [expr [load_of $REF_LOAD]*30] [all_outputs] 86 | #set_load 10 [all_outputs] 87 | set_fanout 10 [all_outputs] 88 | 89 | ###setting design constraint 90 | # 91 | 92 | set_max_capacitance [expr $MAX_CAPACITANCE/2] [current_design] 93 | set_max_fanout $MAX_FANOUT [current_design] 94 | set_max_transition $MAX_TRANSITION [current_design] 95 | 96 | if { $HAVCLK } { 97 | set all_in_exc_clk [remove_from_collection [all_inputs] [get_ports blif_clk_net]] 98 | #set_driving_cell -lib_cell $DRIVE_CELL $all_in_exc_clk 99 | #set_driving_cell -lib_cell scc018ug_uhd_rvt_ff_v1p32_0c_basic/BUFUHDV8 $all_in_exc_clk 100 | #set_driving_cell -library scc018ug_uhd_rvt_ff_v1p32_0c_basic \ 101 | # -lib_cell BUFUHDV8 $all_in_exc_clk 102 | set_input_transition 0.1 $all_in_exc_clk 103 | set_drive 0 [get_ports blif_clk_net] 104 | ###setting timing constraint 105 | # 106 | create_clock -period $PERIOD -name CLK [get_ports blif_clk_net] 107 | set_input_delay -max $MAX_INPUT_DELAY -clock CLK [all_inputs] 108 | set_input_delay -min $MIN_INPUT_DELAY -clock CLK [all_inputs] 109 | set_output_delay -max $MAX_OUTPUT_DELAY -clock CLK [all_outputs] 110 | set_output_delay -min $MIN_OUTPUT_DELAY -clock CLK [all_outputs] 111 | set_clock_uncertainty $CLOCK_UNCERTAINTY [get_ports $CLOCK_NAME] 112 | } 113 | set_max_area 0 114 | 115 | 116 | #ungroup -all -flatten 117 | 118 | set_flatten false -design [get_designs $DESIGN ] 119 | ##compile 120 | # 121 | #compile -map_effort medium 122 | set_flatten false 123 | set_structure true 124 | compile_ultra -no_autoungroup 125 | #compile -map_effort high 126 | 127 | #remove_attribute [current_design ] flatten 128 | #remove_attribute [current_design ] ungroup 129 | #set_ungroup [current_design] false 130 | 131 | 132 | 133 | # For XG mode portability to back-end tools: 134 | set_fix_multiple_port_nets -all -buffer_constant 135 | 136 | ###set timing analyze path group 137 | #group_path -name INPUTS -from [all_inputs] 138 | #group_path -name OUTPUTS -from [all_outputs] 139 | #group_path -name COMBO -from [all_inputs] -to [all_outputs] 140 | 141 | check_design > $REPORTS_PATH/check_desing.log 142 | 143 | ###report design 144 | # 145 | report_constraint > $REPORTS_PATH/constraint.log 146 | report_timing > $REPORTS_PATH/timing.log 147 | report_area > $REPORTS_PATH/area.log 148 | report_power > $REPORTS_PATH/power.log 149 | ###check 150 | # 151 | check_timing > $REPORTS_PATH/check_timing.log 152 | 153 | ### save design 154 | # 155 | write -format verilog -hierarchy -output $OUTPUTS_PATH/$DESIGN_NAME.v 156 | write_sdc $OUTPUTS_PATH/$DESIGN_NAME.sdc 157 | write -format ddc -hierarchy -output $OUTPUTS_PATH/$DESIGN_NAME.ddc 158 | write_sdf $OUTPUTS_PATH/$DESIGN_NAME.sdf 159 | 160 | read_file -format verilog $OUTPUTS_PATH/$DESIGN_NAME.v 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | -------------------------------------------------------------------------------- /dc/synopsys_dc.setup: -------------------------------------------------------------------------------- 1 | #2019-01-15 2 | 3 | #remove previous design 4 | #remove_design -design 5 | #remove previous design and library 6 | #remove_design -all 7 | 8 | #preparing libraries 9 | 10 | 11 | lappend search_path [list "./../ref/liberty/1.1v" \ 12 | "./../ref/sdb" \ 13 | "./../ref/tf" \ 14 | "./../ref/tluplus/TD-LO40-XS-2008v0R_1PxM_1TM9k_ALPA28k/1P7M_1TM" \ 15 | "./../src/iscas/rtl" \ 16 | "./../src/rtl" 17 | ] 18 | set target_library "scc40nll_hdc40_hvt_tt_v1p1_25c_basic.db" 19 | set link_library "* scc40nll_hdc40_hvt_tt_v1p1_25c_basic.db " 20 | set symbol_library "scc40nll_hdc40_hvt.sdb" 21 | 22 | 23 | #check_library 24 | check_library > logs/check_lib.log 25 | 26 | 27 | -------------------------------------------------------------------------------- /eetop.cn_h265enc_v2.0.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/eetop.cn_h265enc_v2.0.zip -------------------------------------------------------------------------------- /uvm-1.1d.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/uvm-1.1d.zip -------------------------------------------------------------------------------- /uvm-1.2.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/uvm-1.2.zip -------------------------------------------------------------------------------- /《System Verilog for design》/sv-design_book_examples.tar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/《System Verilog for design》/sv-design_book_examples.tar -------------------------------------------------------------------------------- /芯片验证漫游指南附赠源代码.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/east1203/ExamplesCode/e35839df0f4a20aa33b8fa20fbe112f46ebf702c/芯片验证漫游指南附赠源代码.zip --------------------------------------------------------------------------------