├── AES_verilog_demo ├── README.md ├── ROM_2P │ └── AES_sTable.mif ├── RTL │ ├── AES_encryp_top.v │ ├── code_connect.png │ ├── colMix_keyAdd.v │ ├── keyExp.v │ ├── roundFunc.v │ ├── roundFunc_10.v │ ├── subByte_rowShift.v │ ├── subColMix.v │ └── 代码关系图.png └── simulation │ ├── AES_encryp_top.vt │ ├── AES调试数据_1.txt │ ├── 仿真图1.png │ ├── 仿真图2.png │ └── 仿真图3.png └── LICENSE /AES_verilog_demo/README.md: -------------------------------------------------------------------------------- 1 | # AES加密算法的Verilog代码 2 | 3 | ## 基本说明 4 | 5 | 本项目完全基于标准AES的加密流程，利用verilog设计实现了ECB模式下的AES加密过程。 6 | 7 | 代码实现过程请参考和对照标准AES加密过程。 8 | 9 | ## 参数说明 10 | 11 | - 顶层文件输入输出参数： 12 | - iKey，明文，长度128bit 13 | - iPlaintext，密钥，长度128bit 14 | - oCiphertext，密文，长度128bit 15 | - 数据的低位放置在变量的高位中 16 | - 其余参数请参考代码文件中的注释部分 17 | 18 | ## 项目文件说明 19 | 20 | 项目包含三个文件夹 21 | 22 | - ROM_2P 23 | 24 | - AES_sTable.mif：包含双端ROM的数据表，存放S盒数据 25 | 26 | - simulation 27 | 28 | - AES_encryp_top.vt：testBench文件，给出一组测试明文、测试密钥 29 | - AES调试数据_1.txt：记录了一些测试过程中的数据 30 | - 仿真图x.png：给出了仿真截图 31 | 32 | - RTL 33 | 34 | - 包含了所有Verilog代码，各文件关系由代码关系图.png给出。 35 | - 各文件主要内容请参考文件中的注释。 36 | 37 | 38 | 39 | ![image](https://github.com/eda-lab/AES-based-on-FPGA/blob/master/AES_verilog_demo/RTL/code_connect.png) 40 | 41 | ​ 代码关系图.png 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /AES_verilog_demo/ROM_2P/AES_sTable.mif: -------------------------------------------------------------------------------- 1 | -- S_table所对应的ROM表，创建双端口ROM时导入本文件 2 | 3 | WIDTH=8; 4 | DEPTH=256; 5 | 6 | ADDRESS_RADIX=UNS; 7 | DATA_RADIX=HEX; 8 | 9 | CONTENT BEGIN 10 | 0 : 63; 11 | 1 : 7C; 12 | 2 : 77; 13 | 3 : 7B; 14 | 4 : F2; 15 | 5 : 6B; 16 | 6 : 6F; 17 | 7 : C5; 18 | 8 : 30; 19 | 9 : 01; 20 | 10 : 67; 21 | 11 : 2B; 22 | 12 : FE; 23 | 13 : D7; 24 | 14 : AB; 25 | 15 : 76; 26 | 16 : CA; 27 | 17 : 82; 28 | 18 : C9; 29 | 19 : 7D; 30 | 20 : FA; 31 | 21 : 59; 32 | 22 : 47; 33 | 23 : F0; 34 | 24 : AD; 35 | 25 : D4; 36 | 26 : A2; 37 | 27 : AF; 38 | 28 : 9C; 39 | 29 : A4; 40 | 30 : 72; 41 | 31 : C0; 42 | 32 : B7; 43 | 33 : FD; 44 | 34 : 93; 45 | 35 : 26; 46 | 36 : 36; 47 | 37 : 3F; 48 | 38 : F7; 49 | 39 : CC; 50 | 40 : 34; 51 | 41 : A5; 52 | 42 : E5; 53 | 43 : F1; 54 | 44 : 71; 55 | 45 : D8; 56 | 46 : 31; 57 | 47 : 15; 58 | 48 : 04; 59 | 49 : C7; 60 | 50 : 23; 61 | 51 : C3; 62 | 52 : 18; 63 | 53 : 96; 64 | 54 : 05; 65 | 55 : 9A; 66 | 56 : 07; 67 | 57 : 12; 68 | 58 : 80; 69 | 59 : E2; 70 | 60 : EB; 71 | 61 : 27; 72 | 62 : B2; 73 | 63 : 75; 74 | 64 : 09; 75 | 65 : 83; 76 | 66 : 2C; 77 | 67 : 1A; 78 | 68 : 1B; 79 | 69 : 6E; 80 | 70 : 5A; 81 | 71 : A0; 82 | 72 : 52; 83 | 73 : 3B; 84 | 74 : D6; 85 | 75 : B3; 86 | 76 : 29; 87 | 77 : E3; 88 | 78 : 2F; 89 | 79 : 84; 90 | 80 : 53; 91 | 81 : D1; 92 | 82 : 00; 93 | 83 : ED; 94 | 84 : 20; 95 | 85 : FC; 96 | 86 : B1; 97 | 87 : 5B; 98 | 88 : 6A; 99 | 89 : CB; 100 | 90 : BE; 101 | 91 : 39; 102 | 92 : 4A; 103 | 93 : 4C; 104 | 94 : 58; 105 | 95 : CF; 106 | 96 : D0; 107 | 97 : EF; 108 | 98 : AA; 109 | 99 : FB; 110 | 100 : 43; 111 | 101 : 4D; 112 | 102 : 33; 113 | 103 : 85; 114 | 104 : 45; 115 | 105 : F9; 116 | 106 : 02; 117 | 107 : 7F; 118 | 108 : 50; 119 | 109 : 3C; 120 | 110 : 9F; 121 | 111 : A8; 122 | 112 : 51; 123 | 113 : A3; 124 | 114 : 40; 125 | 115 : 8F; 126 | 116 : 92; 127 | 117 : 9D; 128 | 118 : 38; 129 | 119 : F5; 130 | 120 : BC; 131 | 121 : B6; 132 | 122 : DA; 133 | 123 : 21; 134 | 124 : 10; 135 | 125 : FF; 136 | 126 : F3; 137 | 127 : D2; 138 | 128 : CD; 139 | 129 : 0C; 140 | 130 : 13; 141 | 131 : EC; 142 | 132 : 5F; 143 | 133 : 97; 144 | 134 : 44; 145 | 135 : 17; 146 | 136 : C4; 147 | 137 : A7; 148 | 138 : 7E; 149 | 139 : 3D; 150 | 140 : 64; 151 | 141 : 5D; 152 | 142 : 19; 153 | 143 : 73; 154 | 144 : 60; 155 | 145 : 81; 156 | 146 : 4F; 157 | 147 : DC; 158 | 148 : 22; 159 | 149 : 2A; 160 | 150 : 90; 161 | 151 : 88; 162 | 152 : 46; 163 | 153 : EE; 164 | 154 : B8; 165 | 155 : 14; 166 | 156 : DE; 167 | 157 : 5E; 168 | 158 : 0B; 169 | 159 : DB; 170 | 160 : E0; 171 | 161 : 32; 172 | 162 : 3A; 173 | 163 : 0A; 174 | 164 : 49; 175 | 165 : 06; 176 | 166 : 24; 177 | 167 : 5C; 178 | 168 : C2; 179 | 169 : D3; 180 | 170 : AC; 181 | 171 : 62; 182 | 172 : 91; 183 | 173 : 95; 184 | 174 : E4; 185 | 175 : 79; 186 | 176 : E7; 187 | 177 : C8; 188 | 178 : 37; 189 | 179 : 6D; 190 | 180 : 8D; 191 | 181 : D5; 192 | 182 : 4E; 193 | 183 : A9; 194 | 184 : 6C; 195 | 185 : 56; 196 | 186 : F4; 197 | 187 : EA; 198 | 188 : 65; 199 | 189 : 7A; 200 | 190 : AE; 201 | 191 : 08; 202 | 192 : BA; 203 | 193 : 78; 204 | 194 : 25; 205 | 195 : 2E; 206 | 196 : 1C; 207 | 197 : A6; 208 | 198 : B4; 209 | 199 : C6; 210 | 200 : E8; 211 | 201 : DD; 212 | 202 : 74; 213 | 203 : 1F; 214 | 204 : 4B; 215 | 205 : BD; 216 | 206 : 8B; 217 | 207 : 8A; 218 | 208 : 70; 219 | 209 : 3E; 220 | 210 : B5; 221 | 211 : 66; 222 | 212 : 48; 223 | 213 : 03; 224 | 214 : F6; 225 | 215 : 0E; 226 | 216 : 61; 227 | 217 : 35; 228 | 218 : 57; 229 | 219 : B9; 230 | 220 : 86; 231 | 221 : C1; 232 | 222 : 1D; 233 | 223 : 9E; 234 | 224 : E1; 235 | 225 : F8; 236 | 226 : 98; 237 | 227 : 11; 238 | 228 : 69; 239 | 229 : D9; 240 | 230 : 8E; 241 | 231 : 94; 242 | 232 : 9B; 243 | 233 : 1E; 244 | 234 : 87; 245 | 235 : E9; 246 | 236 : CE; 247 | 237 : 55; 248 | 238 : 28; 249 | 239 : DF; 250 | 240 : 8C; 251 | 241 : A1; 252 | 242 : 89; 253 | 243 : 0D; 254 | 244 : BF; 255 | 245 : E6; 256 | 246 : 42; 257 | 247 : 68; 258 | 248 : 41; 259 | 249 : 99; 260 | 250 : 2D; 261 | 251 : 0F; 262 | 252 : B0; 263 | 253 : 54; 264 | 254 : BB; 265 | 255 : 16; 266 | END; 267 | -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/AES_encryp_top.v: -------------------------------------------------------------------------------- 1 | module AES_encryp_top 2 | ( 3 | input clk, 4 | input rst_n, 5 | input [127 : 0] iKey,//密钥 6 | input [127 : 0] iPlaintext,//明文 7 | output [127 : 0] oCiphertext//密文 8 | ); 9 | 10 | wire [127 : 0] wkeyExp_OutValue1,wkeyExp_OutValue2,wkeyExp_OutValue3,wkeyExp_OutValue4, 11 | wkeyExp_OutValue5,wkeyExp_OutValue6,wkeyExp_OutValue7,wkeyExp_OutValue8, 12 | wkeyExp_OutValue9,wkeyExp_OutValue10; 13 | wire [127 : 0] wkeyExp_KeyValue1,wkeyExp_KeyValue2,wkeyExp_KeyValue3,wkeyExp_KeyValue4, 14 | wkeyExp_KeyValue5,wkeyExp_KeyValue6,wkeyExp_KeyValue7,wkeyExp_KeyValue8, 15 | wkeyExp_KeyValue9,wkeyExp_KeyValue10; 16 | 17 | //密钥拓展流水线 18 | keyExp keyExp_inst1 19 | ( 20 | .clk(clk), 21 | .rst_n(rst_n), 22 | .Rcon(32'h0100_0000),//当前级的Rcon 23 | .iBlockIn(iKey), 24 | .oKeyValue(wkeyExp_KeyValue1),//轮密钥 25 | .oBlockout(wkeyExp_OutValue1) 26 | ); 27 | 28 | keyExp keyExp_inst2 29 | ( 30 | .clk(clk), 31 | .rst_n(rst_n), 32 | .Rcon(32'h0200_0000),//当前级的Rcon 33 | .iBlockIn(wkeyExp_OutValue1), 34 | .oKeyValue(wkeyExp_KeyValue2),//轮密钥 35 | .oBlockout(wkeyExp_OutValue2) 36 | ); 37 | 38 | keyExp keyExp_inst3 39 | ( 40 | .clk(clk), 41 | .rst_n(rst_n), 42 | .Rcon(32'h0400_0000),//当前级的Rcon 43 | .iBlockIn(wkeyExp_OutValue2), 44 | .oKeyValue(wkeyExp_KeyValue3),//轮密钥 45 | .oBlockout(wkeyExp_OutValue3) 46 | ); 47 | 48 | keyExp keyExp_inst4 49 | ( 50 | .clk(clk), 51 | .rst_n(rst_n), 52 | .Rcon(32'h0800_0000),//当前级的Rcon 53 | .iBlockIn(wkeyExp_OutValue3), 54 | .oKeyValue(wkeyExp_KeyValue4),//轮密钥 55 | .oBlockout(wkeyExp_OutValue4) 56 | ); 57 | 58 | keyExp keyExp_inst5 59 | ( 60 | .clk(clk), 61 | .rst_n(rst_n), 62 | .Rcon(32'h1000_0000),//当前级的Rcon 63 | .iBlockIn(wkeyExp_OutValue4), 64 | .oKeyValue(wkeyExp_KeyValue5),//轮密钥 65 | .oBlockout(wkeyExp_OutValue5) 66 | ); 67 | 68 | keyExp keyExp_inst6 69 | ( 70 | .clk(clk), 71 | .rst_n(rst_n), 72 | .Rcon(32'h2000_0000),//当前级的Rcon 73 | .iBlockIn(wkeyExp_OutValue5), 74 | .oKeyValue(wkeyExp_KeyValue6),//轮密钥 75 | .oBlockout(wkeyExp_OutValue6) 76 | ); 77 | 78 | keyExp keyExp_inst7 79 | ( 80 | .clk(clk), 81 | .rst_n(rst_n), 82 | .Rcon(32'h4000_0000),//当前级的Rcon 83 | .iBlockIn(wkeyExp_OutValue6), 84 | .oKeyValue(wkeyExp_KeyValue7),//轮密钥 85 | .oBlockout(wkeyExp_OutValue7) 86 | ); 87 | 88 | keyExp keyExp_inst8 89 | ( 90 | .clk(clk), 91 | .rst_n(rst_n), 92 | .Rcon(32'h8000_0000),//当前级的Rcon 93 | .iBlockIn(wkeyExp_OutValue7), 94 | .oKeyValue(wkeyExp_KeyValue8),//轮密钥 95 | .oBlockout(wkeyExp_OutValue8) 96 | ); 97 | 98 | keyExp keyExp_inst9 99 | ( 100 | .clk(clk), 101 | .rst_n(rst_n), 102 | .Rcon(32'h1b00_0000),//当前级的Rcon 103 | .iBlockIn(wkeyExp_OutValue8), 104 | .oKeyValue(wkeyExp_KeyValue9),//轮密钥 105 | .oBlockout(wkeyExp_OutValue9) 106 | ); 107 | 108 | keyExp keyExp_inst10 109 | ( 110 | .clk(clk), 111 | .rst_n(rst_n), 112 | .Rcon(32'h3600_0000),//当前级的Rcon 113 | .iBlockIn(wkeyExp_OutValue9), 114 | .oKeyValue(wkeyExp_KeyValue10),//轮密钥 115 | .oBlockout(wkeyExp_OutValue10) 116 | ); 117 | 118 | //轮函数流水线 119 | 120 | //初始轮密钥加 121 | wire [127 : 0] preKeyAddOut = iPlaintext ^ iKey; 122 | //------------------------------------------------------------------------------- 123 | 124 | wire [127 : 0] wRoundFunc_Out1,wRoundFunc_Out2,wRoundFunc_Out3,wRoundFunc_Out4, 125 | wRoundFunc_Out5,wRoundFunc_Out6,wRoundFunc_Out7,wRoundFunc_Out8, 126 | wRoundFunc_Out9; 127 | 128 | roundFunc roundFunc_inst1 129 | ( 130 | .clk(clk), 131 | .rst_n(rst_n), 132 | .iBlockIn(preKeyAddOut), 133 | .iKeyValue(wkeyExp_KeyValue1),//轮密钥 134 | .oBlockout(wRoundFunc_Out1) 135 | ); 136 | 137 | roundFunc roundFunc_inst2 138 | ( 139 | .clk(clk), 140 | .rst_n(rst_n), 141 | .iBlockIn(wRoundFunc_Out1), 142 | .iKeyValue(wkeyExp_KeyValue2),//轮密钥 143 | .oBlockout(wRoundFunc_Out2) 144 | ); 145 | 146 | roundFunc roundFunc_inst3 147 | ( 148 | .clk(clk), 149 | .rst_n(rst_n), 150 | .iBlockIn(wRoundFunc_Out2), 151 | .iKeyValue(wkeyExp_KeyValue3),//轮密钥 152 | .oBlockout(wRoundFunc_Out3) 153 | ); 154 | 155 | roundFunc roundFunc_inst4 156 | ( 157 | .clk(clk), 158 | .rst_n(rst_n), 159 | .iBlockIn(wRoundFunc_Out3), 160 | .iKeyValue(wkeyExp_KeyValue4),//轮密钥 161 | .oBlockout(wRoundFunc_Out4) 162 | ); 163 | 164 | roundFunc roundFunc_inst5 165 | ( 166 | .clk(clk), 167 | .rst_n(rst_n), 168 | .iBlockIn(wRoundFunc_Out4), 169 | .iKeyValue(wkeyExp_KeyValue5),//轮密钥 170 | .oBlockout(wRoundFunc_Out5) 171 | ); 172 | 173 | roundFunc roundFunc_inst6 174 | ( 175 | .clk(clk), 176 | .rst_n(rst_n), 177 | .iBlockIn(wRoundFunc_Out5), 178 | .iKeyValue(wkeyExp_KeyValue6),//轮密钥 179 | .oBlockout(wRoundFunc_Out6) 180 | ); 181 | 182 | roundFunc roundFunc_inst7 183 | ( 184 | .clk(clk), 185 | .rst_n(rst_n), 186 | .iBlockIn(wRoundFunc_Out6), 187 | .iKeyValue(wkeyExp_KeyValue7),//轮密钥 188 | .oBlockout(wRoundFunc_Out7) 189 | ); 190 | 191 | roundFunc roundFunc_inst8 192 | ( 193 | .clk(clk), 194 | .rst_n(rst_n), 195 | .iBlockIn(wRoundFunc_Out7), 196 | .iKeyValue(wkeyExp_KeyValue8),//轮密钥 197 | .oBlockout(wRoundFunc_Out8) 198 | ); 199 | 200 | roundFunc roundFunc_inst9 201 | ( 202 | .clk(clk), 203 | .rst_n(rst_n), 204 | .iBlockIn(wRoundFunc_Out8), 205 | .iKeyValue(wkeyExp_KeyValue9),//轮密钥 206 | .oBlockout(wRoundFunc_Out9) 207 | ); 208 | 209 | roundFunc_10 roundFunc_inst10 210 | ( 211 | .clk(clk), 212 | .rst_n(rst_n), 213 | .iBlockIn(wRoundFunc_Out9), 214 | .iKeyValue(wkeyExp_KeyValue10),//轮密钥 215 | .oBlockout(oCiphertext)//密文输出 216 | ); 217 | 218 | endmodule -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/code_connect.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eda-lab/AES-based-on-FPGA/3483d4eaf3934421c6b511db7aa10e77ce1bc52c/AES_verilog_demo/RTL/code_connect.png -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/colMix_keyAdd.v: -------------------------------------------------------------------------------- 1 | module colMix_keyAdd 2 | ( 3 | input clk, 4 | input rst_n, 5 | input [127 : 0] iBlockIn, 6 | input [127 : 0] iKeyValue,//轮密钥 7 | output [127 : 0] oBlockout 8 | ); 9 | 10 | wire [127 : 0] wColMixOut; 11 | 12 | //列混淆 13 | subColMix subColMix_inst0//列1 14 | ( 15 | .iBlockIn(iBlockIn[127 : 96]), 16 | .oBlockout(wColMixOut[127 : 96]) 17 | ); 18 | 19 | subColMix subColMix_inst1//列2 20 | ( 21 | .iBlockIn(iBlockIn[95 : 64]), 22 | .oBlockout(wColMixOut[95 : 64]) 23 | ); 24 | 25 | subColMix subColMix_inst2//列3 26 | ( 27 | .iBlockIn(iBlockIn[63 : 32]), 28 | .oBlockout(wColMixOut[63 : 32]) 29 | ); 30 | 31 | subColMix subColMix_inst3//列4 32 | ( 33 | .iBlockIn(iBlockIn[31 : 0]), 34 | .oBlockout(wColMixOut[31 : 0]) 35 | ); 36 | 37 | //轮密钥加 38 | assign oBlockout = wColMixOut ^ iKeyValue;//由于字节替换的初始位置有寄存器， 39 | //所以这里不再加入寄存器 40 | 41 | endmodule -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/keyExp.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////////////////// 2 | // 密钥扩展模块 3 | // 每次处理128bit密钥 4 | // 以计算w4到w7为例，先计算w4，再计算w5，w6，w7 5 | /////////////////////////////////////////////////////////////////////////////////////// 6 | module keyExp 7 | ( 8 | input clk, 9 | input rst_n, 10 | input [31 : 0] Rcon,//当前级的Rcon 11 | input [127 : 0] iBlockIn, 12 | output [127 : 0] oKeyValue,//轮密钥 13 | output [127 : 0] oBlockout 14 | ); 15 | 16 | 17 | reg [127 : 0] keyTemp_0; 18 | always @(posedge clk or negedge rst_n)begin 19 | if(!rst_n) 20 | keyTemp_0 <=0 ; 21 | else 22 | keyTemp_0 <= iBlockIn; 23 | end 24 | 25 | //以计算w4为例，先取w3，对其进行字节移位和字节替换操作 26 | wire [31 : 0] wSubCol; 27 | rom_2p rom_2p_inst0 ( 28 | .address_a ( iBlockIn [23 : 16] ), 29 | .address_b ( iBlockIn [15 : 8] ), 30 | .clock ( clk ), 31 | .q_a ( wSubCol [31 : 24] ), 32 | .q_b ( wSubCol [23 : 16] ) 33 | ); 34 | rom_2p rom_2p_inst1 ( 35 | .address_a ( iBlockIn [7 : 0] ), 36 | .address_b ( iBlockIn [31 : 24] ), 37 | .clock ( clk ), 38 | .q_a ( wSubCol [15 : 8] ), 39 | .q_b ( wSubCol [7 : 0] ) 40 | ); 41 | 42 | reg [31 : 0] colTemp_1; 43 | reg [127 : 0] keyTemp_1; 44 | always @(posedge clk or negedge rst_n)begin 45 | if(!rst_n)begin 46 | keyTemp_1 <= 0; 47 | end 48 | else begin 49 | colTemp_1 = wSubCol ^ Rcon ^ keyTemp_0[127 : 96];//利用对w3处理的中间结果计算w4 50 | keyTemp_1 = {keyTemp_0[95 : 0], colTemp_1}; 51 | end 52 | end 53 | 54 | //计算w5,w6,w7 55 | reg [127 : 0] keyTemp_2; 56 | always @(*)begin : W_1_2_3 57 | reg [31 : 0] colTemp_2; 58 | integer i; 59 | 60 | keyTemp_2 = keyTemp_1; 61 | for(i = 0; i < 3; i = i + 1)begin 62 | colTemp_2 = keyTemp_2[127 : 96] ^ keyTemp_2[31 : 0]; 63 | keyTemp_2 = {keyTemp_2[95 : 0], colTemp_2}; 64 | end 65 | end 66 | 67 | assign oBlockout = keyTemp_2; 68 | assign oKeyValue = keyTemp_2; 69 | 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/roundFunc.v: -------------------------------------------------------------------------------- 1 | module roundFunc 2 | ( 3 | input clk, 4 | input rst_n, 5 | input [127 : 0] iBlockIn, 6 | input [127 : 0] iKeyValue,//轮密钥 7 | output [127 : 0] oBlockout 8 | ); 9 | 10 | wire [127 : 0] wRowShift; 11 | 12 | subByte_rowShift subByte_rowShift_inst1 13 | ( 14 | .clk(clk), 15 | .rst_n(rst_n), 16 | .iBlockIn(iBlockIn), 17 | .oBlockout(wRowShift) 18 | ); 19 | 20 | colMix_keyAdd colMix_keyAdd_inst1 21 | ( 22 | .clk(clk), 23 | .rst_n(rst_n), 24 | .iBlockIn(wRowShift), 25 | .iKeyValue(iKeyValue),//轮密钥 26 | .oBlockout(oBlockout) 27 | ); 28 | 29 | endmodule -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/roundFunc_10.v: -------------------------------------------------------------------------------- 1 | module roundFunc_10 2 | ( 3 | input clk, 4 | input rst_n, 5 | input [127 : 0] iBlockIn, 6 | input [127 : 0] iKeyValue,//轮密钥 7 | output reg [127 : 0] oBlockout 8 | ); 9 | 10 | wire [127 : 0] wRowShift; 11 | 12 | subByte_rowShift subByte_rowShift_inst1 13 | ( 14 | .clk(clk), 15 | .rst_n(rst_n), 16 | .iBlockIn(iBlockIn), 17 | .oBlockout(wRowShift) 18 | ); 19 | 20 | 21 | always @(posedge clk or negedge rst_n)begin 22 | if(!rst_n) 23 | oBlockout <= 0; 24 | else 25 | oBlockout <= wRowShift ^ iKeyValue; 26 | end 27 | 28 | endmodule -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/subByte_rowShift.v: -------------------------------------------------------------------------------- 1 | module subByte_rowShift 2 | ( 3 | input clk, 4 | input rst_n, 5 | input [127 : 0] iBlockIn, 6 | output reg [127 : 0] oBlockout 7 | ); 8 | 9 | wire [127 : 0] wSubOut, wRotShift; 10 | 11 | //字节替换逻辑，用8个双口rom实现 12 | rom_2p rom_2p_inst0 ( 13 | .address_a ( iBlockIn [127 : 120] ), 14 | .address_b ( iBlockIn [119 : 112] ), 15 | .clock ( clk ), 16 | .q_a ( wSubOut [127 : 120] ), 17 | .q_b ( wSubOut [119 : 112] ) 18 | ); 19 | rom_2p rom_2p_inst1 ( 20 | .address_a ( iBlockIn [111 : 104] ), 21 | .address_b ( iBlockIn [103 : 96 ] ), 22 | .clock ( clk ), 23 | .q_a ( wSubOut [111 : 104] ), 24 | .q_b ( wSubOut [103 : 96 ] ) 25 | ); 26 | rom_2p rom_2p_inst2 ( 27 | .address_a ( iBlockIn [95 : 88 ] ), 28 | .address_b ( iBlockIn [87 : 80 ] ), 29 | .clock ( clk ), 30 | .q_a ( wSubOut [95 : 88 ] ), 31 | .q_b ( wSubOut [87 : 80 ] ) 32 | ); 33 | rom_2p rom_2p_inst3 ( 34 | .address_a ( iBlockIn [79 : 72 ] ), 35 | .address_b ( iBlockIn [71 : 64 ] ), 36 | .clock ( clk ), 37 | .q_a ( wSubOut [79 : 72 ] ), 38 | .q_b ( wSubOut [71 : 64 ] ) 39 | ); 40 | rom_2p rom_2p_inst4 ( 41 | .address_a ( iBlockIn [63 : 56 ] ), 42 | .address_b ( iBlockIn [55 : 48 ] ), 43 | .clock ( clk ), 44 | .q_a ( wSubOut [63 : 56 ] ), 45 | .q_b ( wSubOut [55 : 48 ] ) 46 | ); 47 | rom_2p rom_2p_inst5 ( 48 | .address_a ( iBlockIn [47 : 40 ] ), 49 | .address_b ( iBlockIn [39 : 32 ] ), 50 | .clock ( clk ), 51 | .q_a ( wSubOut [47 : 40 ] ), 52 | .q_b ( wSubOut [39 : 32 ] ) 53 | ); 54 | rom_2p rom_2p_inst6 ( 55 | .address_a ( iBlockIn [31 : 24 ] ), 56 | .address_b ( iBlockIn [23 : 16 ] ), 57 | .clock ( clk ), 58 | .q_a ( wSubOut [31 : 24 ] ), 59 | .q_b ( wSubOut [23 : 16 ] ) 60 | ); 61 | rom_2p rom_2p_inst7 ( 62 | .address_a ( iBlockIn [15 : 8 ] ), 63 | .address_b ( iBlockIn [7 : 0 ] ), 64 | .clock ( clk ), 65 | .q_a ( wSubOut [15 : 8 ] ), 66 | .q_b ( wSubOut [7 : 0 ] ) 67 | ); 68 | 69 | //行移位，直接将线路对应连接即可 70 | assign wRotShift = {wSubOut [127 : 120],wSubOut [87 : 80],wSubOut [47 : 40],wSubOut [7 : 0], 71 | wSubOut [95 : 88],wSubOut [55 : 48],wSubOut [15 : 8 ],wSubOut [103 : 96], 72 | wSubOut [63 : 56],wSubOut [23 : 16],wSubOut [111 : 104],wSubOut [71 : 64], 73 | wSubOut [31 : 24],wSubOut [119 : 112],wSubOut [79 : 72],wSubOut [39 : 32]}; 74 | 75 | //输出寄存器，传递给下一级信号 76 | always @(posedge clk or negedge rst_n)begin 77 | if(!rst_n) 78 | oBlockout <= 0; 79 | else 80 | oBlockout <= wRotShift; 81 | end 82 | 83 | 84 | endmodule -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/subColMix.v: -------------------------------------------------------------------------------- 1 | module subColMix 2 | ( 3 | input [31 : 0] iBlockIn, 4 | output reg [31 : 0] oBlockout 5 | ); 6 | 7 | wire [7 : 0] wS00 = iBlockIn[31 : 24]; 8 | wire [7 : 0] wS10 = iBlockIn[23 : 16]; 9 | wire [7 : 0] wS20 = iBlockIn[15 : 8]; 10 | wire [7 : 0] wS30 = iBlockIn[7 : 0]; 11 | 12 | wire [7 : 0] wS00_1 = iBlockIn[31] ? {iBlockIn[30 : 24],1'b0} ^ 8'h1b : {iBlockIn[30 : 24],1'b0}; 13 | wire [7 : 0] wS10_1 = iBlockIn[23] ? {iBlockIn[22 : 16],1'b0} ^ 8'h1b : {iBlockIn[22 : 16],1'b0}; 14 | wire [7 : 0] wS20_1 = iBlockIn[15] ? {iBlockIn[14 : 8],1'b0} ^ 8'h1b : {iBlockIn[14 : 8],1'b0}; 15 | wire [7 : 0] wS30_1 = iBlockIn[7] ? {iBlockIn[6 : 0],1'b0} ^ 8'h1b : {iBlockIn[6 : 0],1'b0}; 16 | 17 | 18 | always @(*)begin 19 | oBlockout[31 : 24] = wS00_1 ^ (wS10_1 ^ wS10) ^ wS20 ^ wS30; 20 | oBlockout[23 : 16] = wS00 ^ wS10_1 ^ (wS20_1 ^ wS20) ^ wS30; 21 | oBlockout[15 : 8] = wS00 ^ wS10 ^ wS20_1 ^ (wS30_1 ^ wS30); 22 | oBlockout[7 : 0] = (wS00_1 ^ wS00) ^ wS10 ^ wS20 ^ wS30_1; 23 | end 24 | 25 | endmodule 26 | 27 | -------------------------------------------------------------------------------- /AES_verilog_demo/RTL/代码关系图.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eda-lab/AES-based-on-FPGA/3483d4eaf3934421c6b511db7aa10e77ce1bc52c/AES_verilog_demo/RTL/代码关系图.png -------------------------------------------------------------------------------- /AES_verilog_demo/simulation/AES_encryp_top.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 1991-2013 Altera Corporation 2 | // Your use of Altera Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Altera Program License 8 | // Subscription Agreement, Altera MegaCore Function License 9 | // Agreement, or other applicable license agreement, including, 10 | // without limitation, that your use is for the sole purpose of 11 | // programming logic devices manufactured by Altera and sold by 12 | // Altera or its authorized distributors. Please refer to the 13 | // applicable agreement for further details. 14 | 15 | // ***************************************************************************** 16 | // This file contains a Verilog test bench template that is freely editable to 17 | // suit user's needs .Comments are provided in each section to help the user 18 | // fill out necessary details. 19 | // ***************************************************************************** 20 | // Generated on "06/05/2019 14:46:04" 21 | 22 | // Verilog Test Bench template for design : AES_encryp_top 23 | // 24 | // Simulation tool : ModelSim-Altera (Verilog) 25 | // 26 | 27 | `timescale 1 ns/ 1 ns 28 | module AES_encryp_top_vlg_tst(); 29 | // constants 30 | // test vector input registers 31 | reg clk; 32 | reg [127:0] iKey; 33 | reg [127:0] iPlaintext; 34 | reg rst_n; 35 | // wires 36 | wire [127:0] oCiphertext; 37 | 38 | // assign statements (if any) 39 | AES_encryp_top i1 ( 40 | // port map - connection between master ports and signals/registers 41 | .clk(clk), 42 | .iKey(iKey), 43 | .iPlaintext(iPlaintext), 44 | .oCiphertext(oCiphertext), 45 | .rst_n(rst_n) 46 | ); 47 | initial 48 | begin 49 | #0 clk = 0; 50 | rst_n = 0; 51 | #5 rst_n = 1; 52 | iKey = 128'h31_32_33_34_35_36_37_38_39_30_31_32_33_34_35_36; 53 | iPlaintext = 128'h30_39_38_37_36_35_34_33_32_31_36_35_34_33_32_31; 54 | $display("Running testbench"); 55 | end 56 | always 57 | #10 clk = ~clk; 58 | begin 59 | 60 | end 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /AES_verilog_demo/simulation/AES调试数据_1.txt: -------------------------------------------------------------------------------- 1 | 明文： 2 | 30 39 38 37 36 35 34 33 32 31 36 35 34 33 32 31 3 | 4 | 密钥： 5 | 31 32 33 34 35 36 37 38 39 30 31 32 33 34 35 36 6 | 7 | 密钥和拓展密钥打印： 8 | 0: 31 32 33 34 35 36 37 38 39 30 31 32 33 34 35 36 9 | 1: 28 a4 36 f7 1d 92 1 cf 24 a2 30 fd 17 96 5 cb 10 | 2: ba cf 29 7 a7 5d 28 c8 83 ff 18 35 94 69 1d fe 11 | 3: 47 6b 92 25 e0 36 ba ed 63 c9 a2 d8 f7 a0 bf 26 12 | 4: af 63 65 4d 4f 55 df a0 2c 9c 7d 78 db 3c c2 5e 13 | 5: 54 46 3d f4 1b 13 e2 54 37 8f 9f 2c ec b3 5d 72 14 | 6: 19 a 7d 3a 2 19 9f 6e 35 96 0 42 d9 25 5d 30 15 | 7: 66 46 79 f 64 5f e6 61 51 c9 e6 23 88 ec bb 13 16 | 8: 28 ac 4 cb 4c f3 e2 aa 1d 3a 4 89 95 d6 bf 9a 17 | 9: c5 a4 bc e1 89 57 5e 4b 94 6d 5a c2 1 bb e5 58 18 | 10: 19 7d d6 9d 90 2a 88 d6 4 47 d2 14 5 fc 37 4c 19 | 20 | 初始轮密钥加结果： 21 | 1 b b 3 3 3 3 b b 1 7 7 7 7 7 7 22 | 23 | 第1轮SubBytes结果： 24 | 7c 2b 2b 7b 7b 7b 7b 2b 2b 7c c5 c5 c5 c5 c5 c5 25 | 第1轮ShiftRows结果： 26 | 7c 7b c5 c5 7b 7c c5 7b 2b c5 2b 2b c5 2b 7b c5 27 | 第1轮MixColumns结果： 28 | 75 1b c2 ab cc ac 1b c2 2 ec c5 c5 52 db 4c 95 29 | 第1轮密钥加结果： 30 | 5d bf f4 5c d1 3e 1a d 26 4e f5 38 45 4d 49 5e 31 | 32 | 33 | 第2轮SubBytes结果： 34 | 4c 8 bf 4a 3e b2 a2 d7 f7 2f e6 7 6e e3 3b 58 35 | 第2轮ShiftRows结果： 36 | 4c b2 e6 58 3e 2f 3b 4a f7 e3 bf d7 6e 8 a2 7 37 | 第2轮MixColumns结果： 38 | eb 5a c1 30 7c 67 b9 c2 a3 27 13 eb 61 84 30 16 39 | 第2轮密钥加结果： 40 | 51 95 e8 37 db 3a 91 a 20 d8 b de f5 ed 2d e8 41 | 42 | 第3轮SubBytes结果： 43 | d1 2a 9b 9a b9 80 81 67 b7 61 2b 1d e6 55 d8 9b 44 | 第3轮ShiftRows结果： 45 | d1 80 2b 9b b9 61 d8 9a b7 55 9b 67 e6 2a 81 1d 46 | 第3轮MixColumns结果： 47 | 92 2c b1 ee 88 92 c6 46 76 cc 66 c2 35 37 f2 a0 48 | 第3轮密钥加结果： 49 | d5 47 23 cb 68 a4 7c ab 15 5 c4 1a c2 97 4d 86 50 | 51 | 第4轮SubBytes结果： 52 | 3 a0 26 1f 45 49 10 62 59 6b 1c a2 25 88 e3 44 53 | 第4轮ShiftRows结果： 54 | 3 49 1c 44 45 6b e3 1f 59 88 26 62 25 a0 10 a2 55 | 第4轮MixColumns结果： 56 | 85 f1 be d8 cb b2 d2 79 75 5a 3b 81 3 ec 58 80 57 | 第4轮密钥加结果： 58 | 2a 92 db 95 84 e7 d d9 59 c6 46 f9 d8 d0 9a de 59 | 60 | 第5轮SubBytes结果： 61 | e5 4f b9 2a 5f 94 d7 35 cb b4 5a 99 61 70 b8 1d 62 | 第5轮ShiftRows结果： 63 | e5 94 5a 1d 5f b4 b8 2a cb 70 b9 35 61 4f d7 99 64 | 第5轮MixColumns结果： 65 | 31 25 e2 c0 eb d5 fe b9 91 ce 8d e5 5d 4 2b 12 66 | 第5轮密钥加结果： 67 | 65 63 df 34 f0 c6 1c ed a6 41 12 c9 b1 b7 76 60 68 | 69 | 第6轮SubBytes结果： 70 | 4d fb 9e 18 8c b4 9c 55 24 83 c9 dd c8 a9 38 d0 71 | 第6轮ShiftRows结果： 72 | 4d b4 c9 d0 8c 83 38 18 24 a9 9e 55 c8 fb 9c dd 73 | 第6轮MixColumns结果： 74 | 44 ae 1b 11 bd c1 57 4 63 81 55 f1 dc 47 6c 85 75 | 第6轮密钥加结果： 76 | 5d a4 66 2b bf d8 c8 6a 56 17 55 b3 5 62 31 b5 77 | 78 | 第7轮SubBytes结果： 79 | 4c 49 33 f1 8 61 e8 2 b1 f0 fc 6d 6b aa c7 d5 80 | 第7轮ShiftRows结果： 81 | 4c 61 fc d5 8 f0 c7 f1 b1 aa 33 2 6b 49 e8 6d 82 | 第7轮MixColumns结果： 83 | 12 44 aa f8 2d 50 65 d6 ad a9 7b 55 88 b7 5e c6 84 | 第7轮密钥加结果： 85 | 74 2 d3 f7 49 f 83 b7 fc 60 9d 76 0 5b e5 d5 86 | 87 | 第8轮SubBytes结果： 88 | 92 77 66 68 3b 76 ec a9 b0 d0 5e 38 63 39 d9 3 89 | 第8轮ShiftRows结果： 90 | 92 76 5e 3 3b d0 d9 68 b0 39 66 a9 63 77 ec 38 91 | 第8轮MixColumns结果： 92 | f8 9f 5d 83 ac 98 fa 94 ff c1 a5 dd 8b 9a 9f 4e 93 | 第8轮密钥加结果： 94 | d0 33 59 48 e0 6b 18 3e e2 fb a1 54 1e 4c 20 d4 95 | 96 | 第9轮SubBytes结果： 97 | 70 c3 cb 52 e1 7f ad b2 98 f 32 20 72 29 b7 48 98 | 第9轮ShiftRows结果： 99 | 70 7f 32 48 e1 f b7 52 98 29 cb b2 72 c3 ad 20 100 | 第9轮MixColumns结果： 101 | 1b 90 b3 4d 2d 6f 6d 24 29 3e f1 2e 37 23 90 b8 102 | 第9轮密钥加结果： 103 | de 34 f ac a4 38 33 6f bd 53 ab ec 36 98 75 e0 104 | 105 | 第10轮SubBytes结果： 106 | 1d 18 76 91 49 7 c3 a8 7a ed 62 ce 5 46 9d e1 107 | 第10轮ShiftRows结果： 108 | 1d 7 62 e1 49 ed 9d 91 7a 46 76 a8 5 18 c3 ce 109 | 第10轮MixColumns结果： 110 | 1d 7 62 e1 49 ed 9d 91 7a 46 76 a8 5 18 c3 ce 111 | 第10轮密钥加结果： 112 | 4 7a b4 7c d9 c7 15 47 7e 1 a4 bc 0 e4 f4 82 113 | 114 | 加密结果（密文）打印： 115 | 4 7a b4 7c d9 c7 15 47 7e 1 a4 bc 0 e4 f4 82 -------------------------------------------------------------------------------- /AES_verilog_demo/simulation/仿真图1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eda-lab/AES-based-on-FPGA/3483d4eaf3934421c6b511db7aa10e77ce1bc52c/AES_verilog_demo/simulation/仿真图1.png -------------------------------------------------------------------------------- /AES_verilog_demo/simulation/仿真图2.png: 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