├── .gitattributes ├── CNNAF_mobilenetv2 ├── 1.ddr_rd_ctrl │ ├── ddr_rd_ctrl.v │ └── ddr_rd_data_pro.v ├── 10.top │ └── top.md ├── 2.data_in_reorder │ ├── data_gen.v │ ├── data_in_reorder.v │ └── ip_core │ │ ├── fifo_data.qip │ │ └── fifo_data.v ├── 3.sc_ctrl │ └── sc_ctrl.md ├── 4.sc_add │ └── sc_add.md ├── 5.weight_ctrl │ ├── ip_core │ │ ├── ram_w_ctrlsig.qip │ │ └── ram_w_ctrlsig.v │ ├── w_ctrl.v │ └── w_gen.v ├── 6.bias_ctrl │ ├── bias_ctrl.v │ ├── bias_gen.v │ └── ip_core │ │ ├── fifo_bias_gen.qip │ │ └── fifo_bias_gen.v ├── 7.bias_add │ ├── bias_add.v │ └── ip_core │ │ ├── fp_add_bias.qip │ │ ├── fp_add_bias.sip │ │ ├── fp_add_bias.v │ │ ├── fp_add_bias │ │ ├── dspba_library.vhd │ │ ├── dspba_library_package.vhd │ │ └── fp_add_bias_0002.vhd │ │ ├── fp_cmp_bias.qip │ │ ├── fp_cmp_bias.sip │ │ ├── fp_cmp_bias.v │ │ └── fp_cmp_bias │ │ ├── dspba_library.vhd │ │ ├── dspba_library_package.vhd │ │ └── fp_cmp_bias_0002.vhd ├── 8.calc_unit │ ├── calc_unit_single.v │ ├── calc_unit_x16.v │ └── ip_core │ │ ├── fp_acc.qip │ │ ├── fp_acc.sip │ │ ├── fp_acc.v │ │ ├── fp_acc │ │ ├── dspba_library.vhd │ │ ├── dspba_library_package.vhd │ │ └── fp_acc_0002.vhd │ │ ├── fp_add.qip │ │ ├── fp_add.sip │ │ ├── fp_add.v │ │ ├── fp_add │ │ ├── dspba_library.vhd │ │ ├── dspba_library_package.vhd │ │ └── fp_add_0002.vhd │ │ ├── fp_mul.qip │ │ ├── fp_mul.sip │ │ ├── fp_mul.v │ │ └── fp_mul │ │ ├── dspba_library.vhd │ │ ├── dspba_library_package.vhd │ │ └── fp_mul_0002.vhd ├── 9.data_out_reorder │ └── addr_map.v ├── frame.png └── readme.md ├── LICENSE └── README.md /.gitattributes: -------------------------------------------------------------------------------- 1 | *.vhd linguist-language=verilog 2 | *.qip linguist-language=verilog 3 | *.sip linguist-language=verilog 4 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/10.top/top.md: -------------------------------------------------------------------------------- 1 | # top 2 | The top module is still in building. 3 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/2.data_in_reorder/data_gen.v: -------------------------------------------------------------------------------- 1 | module data_gen( 2 | input clk_200M, 3 | input clk_100M, 4 | input rst_n, 5 | input [127:0] data_in, 6 | input data_in_vld, 7 | 8 | output reg data_out_vld, 9 | output data_vld_for_w, 10 | output reg data_acc_s, 11 | output reg [7:0] data_acc_para, 12 | output [32*9*16-1:0] data_out 13 | ); 14 | //------------------------------------------- 15 | // regs & wires & parameters 16 | //------------------------------------------- 17 | parameter L_CONV = 3'd0; 18 | parameter L_DW = 3'd1; 19 | parameter L_PW = 3'd2; 20 | parameter L_AVGPL = 3'd3; 21 | parameter L_PW_SC = 3'd4; 22 | 23 | //------------------------------------------- 24 | // Instantiation 25 | //------------------------------------------- 26 | wire fifo_wr_en; 27 | wire [768+7+1+1+8-1:0] fifo_wr_all; 28 | 29 | data_in_reorder data_in_reorder( 30 | .clk_200M (clk_200M ), 31 | .rst_n (rst_n ), 32 | .data_in (data_in ), 33 | .data_in_vld (data_in_vld), 34 | .fifo_wr_en (fifo_wr_en ), 35 | .fifo_wr_all (fifo_wr_all) 36 | //assign fifo_wr_all = {fifo_wr_layer_type_cur, fifo_wr_calc_en, fifo_wr_acc_s, fifo_wr_acc_para, fifo_wr_data}; 37 | ); 38 | 39 | reg fifo_rd_en; 40 | wire fifo_empty; 41 | wire fifo_full; 42 | wire [7:0] fifo_rdusedw; 43 | wire [768+7+1+1+8-1:0] fifo_rd_data; 44 | 45 | fifo_data fifo_data_inst ( 46 | .wrclk ( clk_200M ), 47 | .wrreq ( fifo_wr_en ), 48 | .wrfull ( fifo_full ), 49 | .data ( fifo_wr_all ), 50 | .rdclk ( clk_100M ), 51 | .rdreq ( fifo_rd_en ), 52 | .rdempty ( fifo_empty ), 53 | .rdusedw ( fifo_rdusedw ), 54 | .q ( fifo_rd_data ) 55 | ); 56 | //------------------------------------------- 57 | // Read data processing 58 | //------------------------------------------- 59 | wire [6:0] fifo_rd_layer_type; 60 | wire fifo_rd_calc_en; 61 | wire [767:0] fifo_rd_data_part; 62 | wire fifo_rd_acc_s; 63 | wire [7:0] fifo_rd_acc_para; 64 | 65 | assign {fifo_rd_layer_type, fifo_rd_calc_en, fifo_rd_acc_s, fifo_rd_acc_para, fifo_rd_data_part} = fifo_rd_data; 66 | 67 | always @ (posedge clk_100M or negedge rst_n) 68 | begin 69 | if(!rst_n) begin 70 | fifo_rd_en <= 1'b0; 71 | end 72 | else if (fifo_empty == 1'b0) begin 73 | fifo_rd_en <= 1'b1; 74 | end 75 | else begin 76 | fifo_rd_en <= 1'b0; 77 | end 78 | end 79 | 80 | always @ (posedge clk_100M or negedge rst_n) 81 | begin 82 | if(!rst_n) begin 83 | data_acc_s <= 1'b0; 84 | end 85 | else begin 86 | data_acc_s <= fifo_rd_acc_s; 87 | end 88 | end 89 | 90 | always @ (posedge clk_100M or negedge rst_n) 91 | begin 92 | if(!rst_n) begin 93 | data_acc_para <= 8'b0; 94 | end 95 | else begin 96 | data_acc_para <= fifo_rd_acc_para; 97 | end 98 | end 99 | 100 | reg [95:0] calc_data_d3d1[15:0]; 101 | reg [95:0] calc_data_d6d4[15:0]; 102 | reg [95:0] calc_data_d9d7[15:0]; 103 | integer j; 104 | always @ (posedge clk_100M or negedge rst_n) 105 | begin 106 | if(!rst_n) begin 107 | for (j = 0; j < 16; j = j + 1) begin 108 | calc_data_d3d1[j] <= 96'b0; 109 | calc_data_d6d4[j] <= 96'b0; 110 | calc_data_d9d7[j] <= 96'b0; 111 | end 112 | end 113 | else if (fifo_empty == 1'b0 && fifo_rd_layer_type == L_CONV) begin 114 | for (j = 0; j < 16; j = j + 1) begin 115 | {calc_data_d9d7[j], calc_data_d6d4[j], calc_data_d3d1[j]} <= fifo_rd_data_part[287:0]; 116 | end 117 | end 118 | else begin 119 | for (j = 0; j < 16; j = j + 1) begin 120 | calc_data_d3d1[j] <= 96'b0; 121 | calc_data_d6d4[j] <= 96'b0; 122 | calc_data_d9d7[j] <= 96'b0; 123 | end 124 | end 125 | end 126 | 127 | reg data_out_vld_temp; 128 | 129 | always @ (posedge clk_100M or negedge rst_n) 130 | begin 131 | if(!rst_n) begin 132 | data_out_vld_temp <= 1'b0; 133 | end 134 | else if (fifo_empty == 1'b0 && fifo_rd_calc_en == 1'b1) begin 135 | data_out_vld_temp <= 1'b1; 136 | end 137 | else begin 138 | data_out_vld_temp <= 1'b0; 139 | end 140 | end 141 | 142 | assign data_vld_for_w = data_out_vld_temp; 143 | 144 | always @ (posedge clk_100M or negedge rst_n) 145 | begin 146 | if(!rst_n) begin 147 | data_out_vld <= 1'b0; 148 | end 149 | else begin 150 | data_out_vld <= data_out_vld_temp; 151 | end 152 | end 153 | 154 | genvar i; 155 | generate 156 | for(i = 0; i < 16; i = i + 1) begin : data_out_comb 157 | assign data_out[288*i+287:288*i] = {calc_data_d9d7[i], calc_data_d6d4[i], calc_data_d3d1[i]}; 158 | end 159 | endgenerate 160 | 161 | 162 | 163 | endmodule -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/2.data_in_reorder/ip_core/fifo_data.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_data.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_data_inst.v"] 6 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/2.data_in_reorder/ip_core/fifo_data.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: fifo_data.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module fifo_data ( 40 | data, 41 | rdclk, 42 | rdreq, 43 | wrclk, 44 | wrreq, 45 | q, 46 | rdempty, 47 | rdusedw, 48 | wrfull); 49 | 50 | input [784:0] data; 51 | input rdclk; 52 | input rdreq; 53 | input wrclk; 54 | input wrreq; 55 | output [784:0] q; 56 | output rdempty; 57 | output [7:0] rdusedw; 58 | output wrfull; 59 | 60 | wire [784:0] sub_wire0; 61 | wire sub_wire1; 62 | wire [7:0] sub_wire2; 63 | wire sub_wire3; 64 | wire [784:0] q = sub_wire0[784:0]; 65 | wire rdempty = sub_wire1; 66 | wire [7:0] rdusedw = sub_wire2[7:0]; 67 | wire wrfull = sub_wire3; 68 | 69 | dcfifo dcfifo_component ( 70 | .data (data), 71 | .rdclk (rdclk), 72 | .rdreq (rdreq), 73 | .wrclk (wrclk), 74 | .wrreq (wrreq), 75 | .q (sub_wire0), 76 | .rdempty (sub_wire1), 77 | .rdusedw (sub_wire2), 78 | .wrfull (sub_wire3), 79 | .aclr (), 80 | .eccstatus (), 81 | .rdfull (), 82 | .wrempty (), 83 | .wrusedw ()); 84 | defparam 85 | dcfifo_component.intended_device_family = "Cyclone V", 86 | dcfifo_component.lpm_numwords = 256, 87 | dcfifo_component.lpm_showahead = "ON", 88 | dcfifo_component.lpm_type = "dcfifo", 89 | dcfifo_component.lpm_width = 785, 90 | dcfifo_component.lpm_widthu = 8, 91 | dcfifo_component.overflow_checking = "ON", 92 | dcfifo_component.rdsync_delaypipe = 4, 93 | dcfifo_component.underflow_checking = "ON", 94 | dcfifo_component.use_eab = "ON", 95 | dcfifo_component.wrsync_delaypipe = 4; 96 | 97 | 98 | endmodule 99 | 100 | // ============================================================ 101 | // CNX file retrieval info 102 | // ============================================================ 103 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 104 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 105 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 106 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 107 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 108 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 109 | // Retrieval info: PRIVATE: Depth NUMERIC "256" 110 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 111 | // Retrieval info: PRIVATE: Full NUMERIC "1" 112 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 113 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 114 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" 115 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 116 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 117 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 118 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 119 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 120 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 121 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 122 | // Retrieval info: PRIVATE: Width NUMERIC "785" 123 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" 124 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 125 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 126 | // Retrieval info: PRIVATE: output_width NUMERIC "785" 127 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 128 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 129 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" 130 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 131 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 132 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 133 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 134 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" 135 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 136 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 137 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" 138 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" 139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 140 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "785" 141 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" 142 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 143 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 144 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 145 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 146 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 147 | // Retrieval info: USED_PORT: data 0 0 785 0 INPUT NODEFVAL "data[784..0]" 148 | // Retrieval info: USED_PORT: q 0 0 785 0 OUTPUT NODEFVAL "q[784..0]" 149 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 150 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" 151 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 152 | // Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL "rdusedw[7..0]" 153 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 154 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" 155 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 156 | // Retrieval info: CONNECT: @data 0 0 785 0 data 0 0 785 0 157 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 158 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 159 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 160 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 161 | // Retrieval info: CONNECT: q 0 0 785 0 @q 0 0 785 0 162 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 163 | // Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0 164 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 165 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.v TRUE 166 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.inc FALSE 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.cmp FALSE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.bsf FALSE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_inst.v TRUE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_bb.v FALSE 171 | // Retrieval info: LIB_FILE: altera_mf 172 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/3.sc_ctrl/sc_ctrl.md: -------------------------------------------------------------------------------- 1 | # sc_ctrl 2 | The shortcut module is still in building. 3 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/4.sc_add/sc_add.md: -------------------------------------------------------------------------------- 1 | # sc_add 2 | The shortcut module is still in building. 3 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/5.weight_ctrl/ip_core/ram_w_ctrlsig.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_w_ctrlsig.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_w_ctrlsig_inst.v"] 6 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/5.weight_ctrl/ip_core/ram_w_ctrlsig.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: ram_w_ctrlsig.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module ram_w_ctrlsig ( 40 | data, 41 | rdaddress, 42 | rdclock, 43 | wraddress, 44 | wrclock, 45 | wren, 46 | q); 47 | 48 | input [10:0] data; 49 | input [3:0] rdaddress; 50 | input rdclock; 51 | input [3:0] wraddress; 52 | input wrclock; 53 | input wren; 54 | output [10:0] q; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_off 57 | `endif 58 | tri1 wrclock; 59 | tri0 wren; 60 | `ifndef ALTERA_RESERVED_QIS 61 | // synopsys translate_on 62 | `endif 63 | 64 | wire [10:0] sub_wire0; 65 | wire [10:0] q = sub_wire0[10:0]; 66 | 67 | altsyncram altsyncram_component ( 68 | .address_a (wraddress), 69 | .address_b (rdaddress), 70 | .clock0 (wrclock), 71 | .clock1 (rdclock), 72 | .data_a (data), 73 | .wren_a (wren), 74 | .q_b (sub_wire0), 75 | .aclr0 (1'b0), 76 | .aclr1 (1'b0), 77 | .addressstall_a (1'b0), 78 | .addressstall_b (1'b0), 79 | .byteena_a (1'b1), 80 | .byteena_b (1'b1), 81 | .clocken0 (1'b1), 82 | .clocken1 (1'b1), 83 | .clocken2 (1'b1), 84 | .clocken3 (1'b1), 85 | .data_b ({11{1'b1}}), 86 | .eccstatus (), 87 | .q_a (), 88 | .rden_a (1'b1), 89 | .rden_b (1'b1), 90 | .wren_b (1'b0)); 91 | defparam 92 | altsyncram_component.address_aclr_b = "NONE", 93 | altsyncram_component.address_reg_b = "CLOCK1", 94 | altsyncram_component.clock_enable_input_a = "BYPASS", 95 | altsyncram_component.clock_enable_input_b = "BYPASS", 96 | altsyncram_component.clock_enable_output_b = "BYPASS", 97 | altsyncram_component.intended_device_family = "Cyclone V", 98 | altsyncram_component.lpm_type = "altsyncram", 99 | altsyncram_component.numwords_a = 16, 100 | altsyncram_component.numwords_b = 16, 101 | altsyncram_component.operation_mode = "DUAL_PORT", 102 | altsyncram_component.outdata_aclr_b = "NONE", 103 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 104 | altsyncram_component.power_up_uninitialized = "FALSE", 105 | altsyncram_component.ram_block_type = "MLAB", 106 | altsyncram_component.widthad_a = 4, 107 | altsyncram_component.widthad_b = 4, 108 | altsyncram_component.width_a = 11, 109 | altsyncram_component.width_b = 11, 110 | altsyncram_component.width_byteena_a = 1; 111 | 112 | 113 | endmodule 114 | 115 | // ============================================================ 116 | // CNX file retrieval info 117 | // ============================================================ 118 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 120 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 121 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 122 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 123 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 125 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 126 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 127 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 128 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 129 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 130 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 131 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 132 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 133 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 134 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 135 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 136 | // Retrieval info: PRIVATE: Clock NUMERIC "1" 137 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 139 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 140 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 141 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 142 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 143 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 144 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 145 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 146 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 147 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 148 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "176" 149 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 150 | // Retrieval info: PRIVATE: MIFfilename STRING "" 151 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 152 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 153 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 154 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1" 155 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 156 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" 157 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 158 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 159 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 160 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 161 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 162 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 163 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 164 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 165 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 166 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 167 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 168 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "11" 169 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "11" 170 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "11" 171 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "11" 172 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 173 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 174 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 175 | // Retrieval info: PRIVATE: enable NUMERIC "0" 176 | // Retrieval info: PRIVATE: rden NUMERIC "0" 177 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 178 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" 179 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" 180 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 181 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 182 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 183 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 184 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 185 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" 186 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" 187 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 188 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 189 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 190 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 191 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "MLAB" 192 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" 193 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" 194 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "11" 195 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "11" 196 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 197 | // Retrieval info: USED_PORT: data 0 0 11 0 INPUT NODEFVAL "data[10..0]" 198 | // Retrieval info: USED_PORT: q 0 0 11 0 OUTPUT NODEFVAL "q[10..0]" 199 | // Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" 200 | // Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" 201 | // Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]" 202 | // Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" 203 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 204 | // Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0 205 | // Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 206 | // Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 207 | // Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 208 | // Retrieval info: CONNECT: @data_a 0 0 11 0 data 0 0 11 0 209 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 210 | // Retrieval info: CONNECT: q 0 0 11 0 @q_b 0 0 11 0 211 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_w_ctrlsig.v TRUE 212 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_w_ctrlsig.inc FALSE 213 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_w_ctrlsig.cmp FALSE 214 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_w_ctrlsig.bsf FALSE 215 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_w_ctrlsig_inst.v TRUE 216 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_w_ctrlsig_bb.v FALSE 217 | // Retrieval info: LIB_FILE: altera_mf 218 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/5.weight_ctrl/w_gen.v: -------------------------------------------------------------------------------- 1 | module w_gen( 2 | input clk_200M, 3 | input rst_n, 4 | input clk_100M, 5 | 6 | input w_in_vld, 7 | input [127:0] w_in, 8 | input data_vld_in, 9 | 10 | output [32*9*16-1:0] w_out 11 | ); 12 | 13 | wire [15:0] ram_w_wr_en; 14 | wire [7:0] ram_w_wr_addr; 15 | wire [32*9*16-1:0] ram_w_wr_data_all; 16 | wire [10:0] w_change_ctrl; 17 | 18 | w_ctrl w_ctrl( 19 | .clk_200M (clk_200M ), 20 | .rst_n (rst_n ), 21 | .w_in_vld (w_in_vld ), 22 | .w_in (w_in ), 23 | .ram_w_wr_en (ram_w_wr_en ), 24 | .ram_w_wr_addr (ram_w_wr_addr ), 25 | .ram_w_wr_data_all (ram_w_wr_data_all), 26 | .w_change_ctrl (w_change_ctrl ) 27 | ); 28 | 29 | genvar i; 30 | // wire [287:0] ram_w_wr_data_part[15:0]; 31 | // generate 32 | // for(i = 0; i < 16; i = i + 1) begin : ram 33 | // assign ram_w_wr_data_part[i] = ram_w_wr_data_all[288*i+287 : 288*i]; 34 | // end 35 | // endgenerate 36 | 37 | wire [7:0] ram_w_rd_addr; 38 | 39 | generate 40 | for(i = 0; i < 16; i = i + 1) begin : ram_w_gen 41 | ram_w ram_w ( 42 | .wrclock ( clk_200M ), 43 | .wren ( ram_w_wr_en[i] ), 44 | .wraddress ( ram_w_wr_addr ), 45 | .data ( ram_w_wr_data_all[288*i+287 : 288*i]), 46 | 47 | .rdclock ( clk_100M ), 48 | .rdaddress ( ram_w_rd_addr ), 49 | .q ( w_out[288*i+287 : 288*i] ) 50 | ); 51 | end 52 | endgenerate 53 | 54 | wire [10:0] w_change_ctrl_rd; 55 | 56 | ram_w_ctrlsig ram_w_ctrlsig ( 57 | .wrclock ( clk_200M ), 58 | .wren ( 1'b1 ), 59 | .wraddress ( 4'b0 ), 60 | .data ( w_change_ctrl ), 61 | .rdclock ( clk_100M ), 62 | .rdaddress ( 4'b0 ), 63 | .q ( w_change_ctrl_rd ) 64 | ); 65 | 66 | reg [10:0] rd_cnt_cur; 67 | always @ (posedge clk_100M or negedge rst_n) 68 | begin 69 | if(!rst_n) begin 70 | rd_cnt_cur <= 11'd0; 71 | end 72 | else if (rd_cnt_cur >= w_change_ctrl_rd) begin 73 | rd_cnt_cur <= 1'b0; 74 | end 75 | else if (data_vld_in == 1'b1) begin 76 | rd_cnt_cur <= rd_cnt_cur + 1'b1; 77 | end 78 | end 79 | 80 | assign ram_w_rd_addr = rd_cnt_cur[7:0]; 81 | 82 | 83 | 84 | endmodule -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/6.bias_ctrl/bias_gen.v: -------------------------------------------------------------------------------- 1 | module bias_gen( 2 | input clk_200M, 3 | input rst_n, 4 | input clk_100M, 5 | 6 | input bias_in_vld, 7 | input [127:0] bias_in, 8 | 9 | output [511:0] bias_out 10 | ); 11 | 12 | wire fifo_wr_en; 13 | wire [511:0] fifo_wr_data; 14 | 15 | bias_ctrl bias_ctrl( 16 | .clk_200M (clk_200M ), 17 | .rst_n (rst_n ), 18 | .bias_in_vld (bias_in_vld ), 19 | .bias_in (bias_in ), 20 | .fifo_wr_en (fifo_wr_en ), 21 | .fifo_wr_data (fifo_wr_data) 22 | ); 23 | 24 | wire fifo_empty; 25 | reg fifo_rd_en; 26 | // wire [511:0] fifo_rd_data; 27 | 28 | fifo_bias_gen fifo_bias_gen_inst ( 29 | .wrclk ( clk_200M ), 30 | .wrreq ( fifo_wr_en ), 31 | .wrfull ( ), 32 | .data ( fifo_wr_data ), 33 | .rdclk ( clk_100M ), 34 | .rdreq ( fifo_rd_en ), 35 | .rdempty ( fifo_empty ), 36 | .q ( bias_out ) 37 | ); 38 | 39 | always @ (posedge clk_100M or negedge rst_n) 40 | begin 41 | if(!rst_n) begin 42 | fifo_rd_en <= 1'b0; 43 | end 44 | else if (fifo_empty == 1'b0) begin 45 | fifo_rd_en <= 1'b1; 46 | end 47 | else begin 48 | fifo_rd_en <= 1'b0; 49 | end 50 | end 51 | 52 | 53 | 54 | 55 | 56 | 57 | endmodule -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/6.bias_ctrl/ip_core/fifo_bias_gen.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_bias_gen.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_bias_gen_inst.v"] 6 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/6.bias_ctrl/ip_core/fifo_bias_gen.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: dcfifo 5 | 6 | // ============================================================ 7 | // File Name: fifo_bias_gen.v 8 | // Megafunction Name(s): 9 | // dcfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 17.1.0 Build 590 10/25/2017 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2017 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module fifo_bias_gen ( 40 | data, 41 | rdclk, 42 | rdreq, 43 | wrclk, 44 | wrreq, 45 | q, 46 | rdempty, 47 | wrfull); 48 | 49 | input [511:0] data; 50 | input rdclk; 51 | input rdreq; 52 | input wrclk; 53 | input wrreq; 54 | output [511:0] q; 55 | output rdempty; 56 | output wrfull; 57 | 58 | wire [511:0] sub_wire0; 59 | wire sub_wire1; 60 | wire sub_wire2; 61 | wire [511:0] q = sub_wire0[511:0]; 62 | wire rdempty = sub_wire1; 63 | wire wrfull = sub_wire2; 64 | 65 | dcfifo dcfifo_component ( 66 | .data (data), 67 | .rdclk (rdclk), 68 | .rdreq (rdreq), 69 | .wrclk (wrclk), 70 | .wrreq (wrreq), 71 | .q (sub_wire0), 72 | .rdempty (sub_wire1), 73 | .wrfull (sub_wire2), 74 | .aclr (), 75 | .eccstatus (), 76 | .rdfull (), 77 | .rdusedw (), 78 | .wrempty (), 79 | .wrusedw ()); 80 | defparam 81 | dcfifo_component.intended_device_family = "Cyclone V", 82 | dcfifo_component.lpm_numwords = 64, 83 | dcfifo_component.lpm_showahead = "OFF", 84 | dcfifo_component.lpm_type = "dcfifo", 85 | dcfifo_component.lpm_width = 512, 86 | dcfifo_component.lpm_widthu = 6, 87 | dcfifo_component.overflow_checking = "ON", 88 | dcfifo_component.rdsync_delaypipe = 4, 89 | dcfifo_component.underflow_checking = "ON", 90 | dcfifo_component.use_eab = "ON", 91 | dcfifo_component.wrsync_delaypipe = 4; 92 | 93 | 94 | endmodule 95 | 96 | // ============================================================ 97 | // CNX file retrieval info 98 | // ============================================================ 99 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 100 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 101 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 102 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 103 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" 104 | // Retrieval info: PRIVATE: Clock NUMERIC "4" 105 | // Retrieval info: PRIVATE: Depth NUMERIC "64" 106 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 107 | // Retrieval info: PRIVATE: Full NUMERIC "1" 108 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 109 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 110 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 111 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 112 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 113 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 114 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 115 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 116 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 117 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 118 | // Retrieval info: PRIVATE: Width NUMERIC "512" 119 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" 120 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 121 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 122 | // Retrieval info: PRIVATE: output_width NUMERIC "512" 123 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 124 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 125 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 126 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" 127 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 128 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 129 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 130 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" 131 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 132 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 133 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64" 134 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 135 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" 136 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "512" 137 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6" 138 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 139 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" 140 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 141 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 142 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" 143 | // Retrieval info: USED_PORT: data 0 0 512 0 INPUT NODEFVAL "data[511..0]" 144 | // Retrieval info: USED_PORT: q 0 0 512 0 OUTPUT NODEFVAL "q[511..0]" 145 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" 146 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty" 147 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 148 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" 149 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull" 150 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 151 | // Retrieval info: CONNECT: @data 0 0 512 0 data 0 0 512 0 152 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 153 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 154 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 155 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 156 | // Retrieval info: CONNECT: q 0 0 512 0 @q 0 0 512 0 157 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 158 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bias_gen.v TRUE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bias_gen.inc FALSE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bias_gen.cmp FALSE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bias_gen.bsf FALSE 163 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bias_gen_inst.v TRUE 164 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bias_gen_bb.v FALSE 165 | // Retrieval info: LIB_FILE: altera_mf 166 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/bias_add.v: -------------------------------------------------------------------------------- 1 | module bias_add( 2 | input clk_100M, 3 | input rst_n, 4 | 5 | input data_in_vld, 6 | input [511:0] data_in, 7 | input [511:0] bias_in, 8 | 9 | output data_out_vld, 10 | output [511:0] data_out 11 | ); 12 | 13 | //------------------------------------------- 14 | // regs & wires & parameters 15 | //------------------------------------------- 16 | wire [31:0] bias_in_part[15:0]; 17 | wire [31:0] data_in_part[15:0]; 18 | genvar i; 19 | 20 | //------------------------------------------- 21 | // split data 22 | //------------------------------------------- 23 | 24 | generate 25 | for(i = 0; i < 16; i = i + 1) begin : data_divide 26 | assign bias_in_part[i] = bias_in[i*32+31 : i*32]; 27 | assign data_in_part[i] = data_in[i*32+31 : i*32]; 28 | end 29 | endgenerate 30 | 31 | //------------------------------------------- 32 | // add bias and the output data from calc_unit 33 | //------------------------------------------- 34 | wire [31:0] add_out[15:0]; 35 | generate 36 | for(i = 0; i < 16; i = i + 1) begin : data_add 37 | fp_add_bias fp_add_bias( 38 | .clk (clk_100M), 39 | .areset (~rst_n), 40 | .a (bias_in_part[i]), 41 | .b (data_in_part[i]), 42 | .q (add_out[i]) 43 | ); 44 | end 45 | endgenerate 46 | //------------------------------------------- 47 | // ReLU6 48 | //------------------------------------------- 49 | wire less_than_6[15:0]; 50 | generate 51 | for(i = 0; i < 16; i = i + 1) begin : less_6_gen 52 | fp_cmp_bias fp_cmp_bias( 53 | .clk (clk_100M), 54 | .areset (~rst_n), 55 | .a (add_out[i]), 56 | .b (32'h40C00000), //6 57 | .q (less_than_6[i]) 58 | ); 59 | end 60 | endgenerate 61 | 62 | reg less_than_0[15:0]; 63 | generate 64 | for(i = 0; i < 16; i = i + 1) begin : less_0_gen 65 | always @ (posedge clk_100M or negedge rst_n) 66 | begin 67 | if(!rst_n) begin 68 | less_than_0[i] <= 1'b0; 69 | end 70 | else if (add_out[i][31] == 1'b1) begin 71 | less_than_0[i] <= 1'b1; 72 | end 73 | else begin 74 | less_than_0[i] <= 1'b0; 75 | end 76 | end 77 | end 78 | endgenerate 79 | 80 | reg [31:0] add_out_temp[15:0]; 81 | generate 82 | for(i = 0; i < 16; i = i + 1) begin : add_out_temp_gen 83 | always @ (posedge clk_100M or negedge rst_n) 84 | begin 85 | if(!rst_n) begin 86 | add_out_temp[i] <= 32'b0; 87 | end 88 | else begin 89 | add_out_temp[i] <= add_out[i]; 90 | end 91 | end 92 | end 93 | endgenerate 94 | //------------------------------------------- 95 | // output 96 | //------------------------------------------- 97 | wire [31:0] data_out_part[15:0]; 98 | generate 99 | for(i = 0; i < 16; i = i + 1) begin : data_out_par_gen 100 | assign data_out_part[i] = less_than_6[i] ? less_than_0[i] ? 32'b0 : add_out_temp[i] : 32'h40C00000; 101 | end 102 | endgenerate 103 | 104 | generate 105 | for(i = 0; i < 16; i = i + 1) begin : data_combine 106 | assign data_out[32*i+31 : 32*i] = data_out_part[i]; 107 | end 108 | endgenerate 109 | 110 | reg [6:0] vld_reg; 111 | always @ (posedge clk_100M or negedge rst_n) 112 | begin 113 | if(!rst_n) begin 114 | vld_reg <= 7'b0; 115 | end 116 | else begin 117 | vld_reg <= {vld_reg[5:0], data_in_vld}; 118 | end 119 | end 120 | 121 | assign data_out_vld = vld_reg[6]; 122 | 123 | 124 | 125 | 126 | endmodule -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_add_bias.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "fp_add_bias" -name MISC_FILE [file join $::quartus(qip_path) "fp_add_bias.cmp"] 5 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" 6 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 7 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_NAME "ZnBfYWRkX2JpYXM=" 10 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 11 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 14 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_VERSION "MTcuMQ==" 15 | set_global_assignment -entity "fp_add_bias" -library "fp_add_bias" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 16 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_NAME "ZnBfYWRkX2JpYXNfMDAwMg==" 17 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 18 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 19 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_INTERNAL "Off" 20 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 21 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_VERSION "MTcuMQ==" 22 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 23 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05fRkFNSUxZ::QVJJVEg=::RmFtaWx5" 24 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "QVJJVEhfZnVuY3Rpb24=::QURE::TmFtZQ==" 25 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "Q09OVkVSVF9mdW5jdGlvbg==::RlhQX0ZQ::TmFtZQ==" 26 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "QUxMX2Z1bmN0aW9u::QURE::TmFtZQ==" 27 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "RVhQX0xPR19mdW5jdGlvbg==::RVhQRQ==::TmFtZQ==" 28 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "VFJJR19mdW5jdGlvbg==::U0lO::TmFtZQ==" 29 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ==" 30 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ==" 31 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::QURE::ZGVyaXZlZGZ1bmN0aW9u" 32 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0" 33 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ=" 34 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ=" 35 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E=" 36 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ=" 37 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" 38 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" 39 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Ng==::VGFyZ2V0" 40 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::Y29tYmluZWQ=::R29hbA==" 41 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" 42 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" 43 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU=" 44 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::ZmFsc2U=::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U=" 45 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" 46 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k" 47 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw=" 48 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp" 49 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2lucHV0cw==::Mg==::SW5wdXQgVmVjdG9yIERpbWVuc2lvbg==" 50 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "dHJpZ19ub19yYW5nZV9yZWR1Y3Rpb24=::ZmFsc2U=::SW5wdXRzIGFyZSB3aXRoaW4gcmFuZ2UgLTJwaSB0byArMnBp" 51 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "cmVwb3J0X3Jlc291cmNlc190b194bWw=::ZmFsc2U=::cmVwb3J0X3Jlc291cmNlc190b194bWw=" 52 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg=" 53 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" 54 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" 55 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" 56 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Ng==::bGF0ZW5jeV9mZWVkYmFjaw==" 57 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" 58 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" 59 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" 60 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cF9kZXJpdmVk::OA==::ZnBfb3V0X2V4cF9kZXJpdmVk" 61 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbg==::MjM=::T3V0cHV0IE1hbnRpc3Nh" 62 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbl9kZXJpdmVk::OA==::ZnBfb3V0X21hbl9kZXJpdmVk" 63 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZm9ybWF0::c2luZ2xl::SW5wdXQgRm9ybWF0" 64 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhw::OA==::SW5wdXQgRXhwb25lbnQ=" 65 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhwX2Rlcml2ZWQ=::OA==::ZnBfaW5fZXhwX2Rlcml2ZWQ=" 66 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFu::MjM=::SW5wdXQgTWFudGlzc2E=" 67 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFuX2Rlcml2ZWQ=::OA==::ZnBfaW5fbWFuX2Rlcml2ZWQ=" 68 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 69 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 70 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" 71 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MA==::TXVsdGlwbGllcw==" 72 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::ODM0::TFVUcw==" 73 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" 74 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" 75 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" 76 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=" 77 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ=" 78 | 79 | set_global_assignment -library "fp_add_bias" -name VERILOG_FILE [file join $::quartus(qip_path) "fp_add_bias.v"] 80 | set_global_assignment -library "fp_add_bias" -name VHDL_FILE [file join $::quartus(qip_path) "fp_add_bias/dspba_library_package.vhd"] 81 | set_global_assignment -library "fp_add_bias" -name VHDL_FILE [file join $::quartus(qip_path) "fp_add_bias/dspba_library.vhd"] 82 | set_global_assignment -library "fp_add_bias" -name VHDL_FILE [file join $::quartus(qip_path) "fp_add_bias/fp_add_bias_0002.vhd"] 83 | 84 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_TOOL_NAME "altera_fp_functions" 85 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_TOOL_VERSION "17.1" 86 | set_global_assignment -entity "fp_add_bias_0002" -library "fp_add_bias" -name IP_TOOL_ENV "mwpim" 87 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_add_bias.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_add_bias" -library "lib_fp_add_bias" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_add_bias" -library "lib_fp_add_bias" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_add_bias" -library "lib_fp_add_bias" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_fp_add_bias" -name SPD_FILE [file join $::quartus(sip_path) "fp_add_bias.spd"] 5 | 6 | set_global_assignment -library "lib_fp_add_bias" -name MISC_FILE [file join $::quartus(sip_path) "fp_add_bias_sim/fp_add_bias.vo"] 7 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_add_bias.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTERA_FP_FUNCTIONS v17.1% 2 | // GENERATION: XML 3 | // fp_add_bias.v 4 | 5 | // Generated using ACDS version 17.1 590 6 | 7 | `timescale 1 ps / 1 ps 8 | module fp_add_bias ( 9 | input wire clk, // clk.clk 10 | input wire areset, // areset.reset 11 | input wire [31:0] a, // a.a 12 | input wire [31:0] b, // b.b 13 | output wire [31:0] q // q.q 14 | ); 15 | 16 | fp_add_bias_0002 fp_add_bias_inst ( 17 | .clk (clk), // clk.clk 18 | .areset (areset), // areset.reset 19 | .a (a), // a.a 20 | .b (b), // b.b 21 | .q (q) // q.q 22 | ); 23 | 24 | endmodule 25 | // Retrieval info: 26 | // 51 | // Retrieval info: 52 | // Retrieval info: 53 | // Retrieval info: 54 | // Retrieval info: 55 | // Retrieval info: 56 | // Retrieval info: 57 | // Retrieval info: 58 | // Retrieval info: 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // Retrieval info: 70 | // Retrieval info: 71 | // Retrieval info: 72 | // Retrieval info: 73 | // Retrieval info: 74 | // Retrieval info: 75 | // Retrieval info: 76 | // Retrieval info: 77 | // Retrieval info: 78 | // Retrieval info: 79 | // Retrieval info: 80 | // Retrieval info: 81 | // Retrieval info: 82 | // Retrieval info: 83 | // Retrieval info: 84 | // Retrieval info: 85 | // Retrieval info: 86 | // Retrieval info: 87 | // Retrieval info: 88 | // Retrieval info: 89 | // Retrieval info: 90 | // Retrieval info: 91 | // IPFS_FILES : fp_add_bias.vo 92 | // RELATED_FILES: fp_add_bias.v, dspba_library_package.vhd, dspba_library.vhd, fp_add_bias_0002.vhd 93 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_add_bias/dspba_library.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.dspba_library_package.all; 17 | 18 | entity dspba_delay is 19 | generic ( 20 | width : natural := 8; 21 | depth : natural := 1; 22 | reset_high : std_logic := '1'; 23 | reset_kind : string := "ASYNC" 24 | ); 25 | port ( 26 | clk : in std_logic; 27 | aclr : in std_logic; 28 | ena : in std_logic := '1'; 29 | xin : in std_logic_vector(width-1 downto 0); 30 | xout : out std_logic_vector(width-1 downto 0) 31 | ); 32 | end dspba_delay; 33 | 34 | architecture delay of dspba_delay is 35 | type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0); 36 | signal delay_signals : delay_array; 37 | begin 38 | delay_signals(depth) <= xin; 39 | 40 | delay_block: if 0 < depth generate 41 | begin 42 | delay_loop: for i in depth-1 downto 0 generate 43 | begin 44 | async_reset: if reset_kind = "ASYNC" generate 45 | process(clk, aclr) 46 | begin 47 | if aclr=reset_high then 48 | delay_signals(i) <= (others => '0'); 49 | elsif clk'event and clk='1' then 50 | if ena='1' then 51 | delay_signals(i) <= delay_signals(i + 1); 52 | end if; 53 | end if; 54 | end process; 55 | end generate; 56 | 57 | sync_reset: if reset_kind = "SYNC" generate 58 | process(clk) 59 | begin 60 | if clk'event and clk='1' then 61 | if aclr=reset_high then 62 | delay_signals(i) <= (others => '0'); 63 | elsif ena='1' then 64 | delay_signals(i) <= delay_signals(i + 1); 65 | end if; 66 | end if; 67 | end process; 68 | end generate; 69 | 70 | no_reset: if reset_kind = "NONE" generate 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | if ena='1' then 75 | delay_signals(i) <= delay_signals(i + 1); 76 | end if; 77 | end if; 78 | end process; 79 | end generate; 80 | end generate; 81 | end generate; 82 | 83 | xout <= delay_signals(0); 84 | end delay; 85 | 86 | -------------------------------------------------------------------------------- 87 | 88 | library IEEE; 89 | use IEEE.std_logic_1164.all; 90 | use IEEE.NUMERIC_STD.all; 91 | use work.dspba_library_package.all; 92 | 93 | entity dspba_sync_reg is 94 | generic ( 95 | width1 : natural := 8; 96 | init_value : std_logic_vector; 97 | width2 : natural := 8; 98 | depth : natural := 2; 99 | pulse_multiplier : natural := 1; 100 | counter_width : natural := 8; 101 | reset1_high : std_logic := '1'; 102 | reset2_high : std_logic := '1'; 103 | reset_kind : string := "ASYNC" 104 | ); 105 | port ( 106 | clk1 : in std_logic; 107 | aclr1 : in std_logic; 108 | ena : in std_logic_vector(0 downto 0); 109 | xin : in std_logic_vector(width1-1 downto 0); 110 | xout : out std_logic_vector(width1-1 downto 0); 111 | clk2 : in std_logic; 112 | aclr2 : in std_logic; 113 | sxout : out std_logic_vector(width2-1 downto 0) 114 | ); 115 | end entity; 116 | 117 | architecture sync_reg of dspba_sync_reg is 118 | type bit_array is array (depth-1 downto 0) of std_logic; 119 | 120 | signal iclk_enable : std_logic; 121 | signal iclk_data : std_logic_vector(width1-1 downto 0); 122 | signal oclk_data : std_logic_vector(width2-1 downto 0); 123 | 124 | -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops 125 | -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis 126 | signal sync_regs : bit_array; 127 | attribute altera_attribute : string; 128 | attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; 129 | 130 | signal oclk_enable : std_logic; 131 | 132 | constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value; 133 | 134 | signal counter : UNSIGNED(counter_width-1 downto 0); 135 | signal ena_internal : std_logic; 136 | begin 137 | oclk_enable <= sync_regs(depth-1); 138 | 139 | no_multiplication: if pulse_multiplier=1 generate 140 | ena_internal <= ena(0); 141 | end generate; 142 | 143 | async_reset: if reset_kind="ASYNC" generate 144 | 145 | multiply_ena: if pulse_multiplier>1 generate 146 | ena_internal <= '1' when counter>0 else ena(0); 147 | process (clk1, aclr1) 148 | begin 149 | if aclr1=reset1_high then 150 | counter <= (others => '0'); 151 | elsif clk1'event and clk1='1' then 152 | if counter>0 then 153 | if counter=pulse_multiplier-1 then 154 | counter <= (others => '0'); 155 | else 156 | counter <= counter + TO_UNSIGNED(1, counter_width); 157 | end if; 158 | else 159 | if ena(0)='1' then 160 | counter <= TO_UNSIGNED(1, counter_width); 161 | end if; 162 | end if; 163 | end if; 164 | end process; 165 | end generate; 166 | 167 | process (clk1, aclr1) 168 | begin 169 | if aclr1=reset1_high then 170 | iclk_enable <= '0'; 171 | iclk_data <= init_value_internal; 172 | elsif clk1'event and clk1='1' then 173 | iclk_enable <= ena_internal; 174 | if ena(0)='1' then 175 | iclk_data <= xin; 176 | end if; 177 | end if; 178 | end process; 179 | 180 | sync_reg_loop: for i in 0 to depth-1 generate 181 | process (clk2, aclr2) 182 | begin 183 | if aclr2=reset2_high then 184 | sync_regs(i) <= '0'; 185 | elsif clk2'event and clk2='1' then 186 | if i>0 then 187 | sync_regs(i) <= sync_regs(i-1); 188 | else 189 | sync_regs(i) <= iclk_enable; 190 | end if; 191 | end if; 192 | end process; 193 | end generate; 194 | 195 | process (clk2, aclr2) 196 | begin 197 | if aclr2=reset2_high then 198 | oclk_data <= init_value_internal(width2-1 downto 0); 199 | elsif clk2'event and clk2='1' then 200 | if oclk_enable='1' then 201 | oclk_data <= iclk_data(width2-1 downto 0); 202 | end if; 203 | end if; 204 | end process; 205 | end generate; 206 | 207 | sync_reset: if reset_kind="SYNC" generate 208 | 209 | multiply_ena: if pulse_multiplier>1 generate 210 | ena_internal <= '1' when counter>0 else ena(0); 211 | process (clk1) 212 | begin 213 | if clk1'event and clk1='1' then 214 | if aclr1=reset1_high then 215 | counter <= (others => '0'); 216 | else 217 | if counter>0 then 218 | if counter=pulse_multiplier-1 then 219 | counter <= (others => '0'); 220 | else 221 | counter <= counter + TO_UNSIGNED(1, counter_width); 222 | end if; 223 | else 224 | if ena(0)='1' then 225 | counter <= TO_UNSIGNED(1, counter_width); 226 | end if; 227 | end if; 228 | end if; 229 | end if; 230 | end process; 231 | end generate; 232 | 233 | process (clk1) 234 | begin 235 | if clk1'event and clk1='1' then 236 | if aclr1=reset1_high then 237 | iclk_enable <= '0'; 238 | iclk_data <= init_value_internal; 239 | else 240 | iclk_enable <= ena_internal; 241 | if ena(0)='1' then 242 | iclk_data <= xin; 243 | end if; 244 | end if; 245 | end if; 246 | end process; 247 | 248 | sync_reg_loop: for i in 0 to depth-1 generate 249 | process (clk2) 250 | begin 251 | if clk2'event and clk2='1' then 252 | if aclr2=reset2_high then 253 | sync_regs(i) <= '0'; 254 | else 255 | if i>0 then 256 | sync_regs(i) <= sync_regs(i-1); 257 | else 258 | sync_regs(i) <= iclk_enable; 259 | end if; 260 | end if; 261 | end if; 262 | end process; 263 | end generate; 264 | 265 | process (clk2) 266 | begin 267 | if clk2'event and clk2='1' then 268 | if aclr2=reset2_high then 269 | oclk_data <= init_value_internal(width2-1 downto 0); 270 | elsif oclk_enable='1' then 271 | oclk_data <= iclk_data(width2-1 downto 0); 272 | end if; 273 | end if; 274 | end process; 275 | end generate; 276 | 277 | none_reset: if reset_kind="NONE" generate 278 | 279 | multiply_ena: if pulse_multiplier>1 generate 280 | ena_internal <= '1' when counter>0 else ena(0); 281 | process (clk1, aclr1) 282 | begin 283 | if clk1'event and clk1='1' then 284 | if counter>0 then 285 | if counter=pulse_multiplier-1 then 286 | counter <= (others => '0'); 287 | else 288 | counter <= counter + TO_UNSIGNED(1, counter_width); 289 | end if; 290 | else 291 | if ena(0)='1' then 292 | counter <= TO_UNSIGNED(1, counter_width); 293 | end if; 294 | end if; 295 | end if; 296 | end process; 297 | end generate; 298 | 299 | process (clk1) 300 | begin 301 | if clk1'event and clk1='1' then 302 | iclk_enable <= ena_internal; 303 | if ena(0)='1' then 304 | iclk_data <= xin; 305 | end if; 306 | end if; 307 | end process; 308 | 309 | sync_reg_loop: for i in 0 to depth-1 generate 310 | process (clk2) 311 | begin 312 | if clk2'event and clk2='1' then 313 | if i>0 then 314 | sync_regs(i) <= sync_regs(i-1); 315 | else 316 | sync_regs(i) <= iclk_enable; 317 | end if; 318 | end if; 319 | end process; 320 | end generate; 321 | 322 | process (clk2) 323 | begin 324 | if clk2'event and clk2='1' then 325 | if oclk_enable='1' then 326 | oclk_data <= iclk_data(width2-1 downto 0); 327 | end if; 328 | end if; 329 | end process; 330 | end generate; 331 | 332 | xout <= iclk_data; 333 | sxout <= oclk_data; 334 | 335 | end sync_reg; 336 | 337 | -------------------------------------------------------------------------------- 338 | 339 | library ieee; 340 | use ieee.std_logic_1164.all; 341 | use ieee.numeric_std.all; 342 | 343 | entity dspba_pipe is 344 | generic( 345 | num_bits : positive := 8; 346 | num_stages : natural := 0; 347 | init_value : std_logic := 'X' 348 | ); 349 | port( 350 | clk: in std_logic; 351 | d : in std_logic_vector(num_bits-1 downto 0); 352 | q : out std_logic_vector(num_bits-1 downto 0) 353 | ); 354 | end entity dspba_pipe; 355 | 356 | architecture rtl of dspba_pipe is 357 | attribute altera_attribute : string; 358 | attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; 359 | 360 | type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0); 361 | signal stage_array : stage_array_type := (others => (others => init_value)); 362 | begin 363 | stage_array(0) <= d; 364 | 365 | g_pipe : for i in 1 to num_stages generate 366 | p_stage : process (clk) is 367 | begin 368 | if rising_edge(clk) then 369 | stage_array(i) <= stage_array(i-1); 370 | end if; 371 | end process p_stage; 372 | end generate g_pipe; 373 | 374 | q <= stage_array(num_stages); 375 | 376 | end rtl; 377 | 378 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_add_bias/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_cmp_bias.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "fp_cmp_bias" -name MISC_FILE [file join $::quartus(qip_path) "fp_cmp_bias.cmp"] 5 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" 6 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 7 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_NAME "ZnBfY21wX2JpYXM=" 10 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 11 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 14 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_VERSION "MTcuMQ==" 15 | set_global_assignment -entity "fp_cmp_bias" -library "fp_cmp_bias" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 16 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_NAME "ZnBfY21wX2JpYXNfMDAwMg==" 17 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 18 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 19 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_INTERNAL "Off" 20 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 21 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_VERSION "MTcuMQ==" 22 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 23 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05fRkFNSUxZ::Q09NUEFSRQ==::RmFtaWx5" 24 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "QVJJVEhfZnVuY3Rpb24=::QURE::TmFtZQ==" 25 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "Q09OVkVSVF9mdW5jdGlvbg==::RlhQX0ZQ::TmFtZQ==" 26 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "QUxMX2Z1bmN0aW9u::QURE::TmFtZQ==" 27 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "RVhQX0xPR19mdW5jdGlvbg==::RVhQRQ==::TmFtZQ==" 28 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "VFJJR19mdW5jdGlvbg==::U0lO::TmFtZQ==" 29 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TFQ=::TmFtZQ==" 30 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ==" 31 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::TFQ=::ZGVyaXZlZGZ1bmN0aW9u" 32 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0" 33 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ=" 34 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ=" 35 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E=" 36 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ=" 37 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" 38 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" 39 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::MQ==::VGFyZ2V0" 40 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::Y29tYmluZWQ=::R29hbA==" 41 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" 42 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" 43 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::ZmFsc2U=::dXNlX3JvdW5kaW5nX21vZGU=" 44 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::ZmFsc2U=::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U=" 45 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" 46 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k" 47 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw=" 48 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp" 49 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2lucHV0cw==::Mg==::SW5wdXQgVmVjdG9yIERpbWVuc2lvbg==" 50 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "dHJpZ19ub19yYW5nZV9yZWR1Y3Rpb24=::ZmFsc2U=::SW5wdXRzIGFyZSB3aXRoaW4gcmFuZ2UgLTJwaSB0byArMnBp" 51 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "cmVwb3J0X3Jlc291cmNlc190b194bWw=::ZmFsc2U=::cmVwb3J0X3Jlc291cmNlc190b194bWw=" 52 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg=" 53 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" 54 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" 55 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" 56 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::MQ==::bGF0ZW5jeV9mZWVkYmFjaw==" 57 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" 58 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" 59 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" 60 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cF9kZXJpdmVk::OA==::ZnBfb3V0X2V4cF9kZXJpdmVk" 61 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbg==::MjM=::T3V0cHV0IE1hbnRpc3Nh" 62 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbl9kZXJpdmVk::OA==::ZnBfb3V0X21hbl9kZXJpdmVk" 63 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZm9ybWF0::c2luZ2xl::SW5wdXQgRm9ybWF0" 64 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhw::OA==::SW5wdXQgRXhwb25lbnQ=" 65 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhwX2Rlcml2ZWQ=::OA==::ZnBfaW5fZXhwX2Rlcml2ZWQ=" 66 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFu::MjM=::SW5wdXQgTWFudGlzc2E=" 67 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFuX2Rlcml2ZWQ=::OA==::ZnBfaW5fbWFuX2Rlcml2ZWQ=" 68 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 69 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 70 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" 71 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MA==::TXVsdGlwbGllcw==" 72 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MTE4::TFVUcw==" 73 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" 74 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" 75 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" 76 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=" 77 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ=" 78 | 79 | set_global_assignment -library "fp_cmp_bias" -name VERILOG_FILE [file join $::quartus(qip_path) "fp_cmp_bias.v"] 80 | set_global_assignment -library "fp_cmp_bias" -name VHDL_FILE [file join $::quartus(qip_path) "fp_cmp_bias/dspba_library_package.vhd"] 81 | set_global_assignment -library "fp_cmp_bias" -name VHDL_FILE [file join $::quartus(qip_path) "fp_cmp_bias/dspba_library.vhd"] 82 | set_global_assignment -library "fp_cmp_bias" -name VHDL_FILE [file join $::quartus(qip_path) "fp_cmp_bias/fp_cmp_bias_0002.vhd"] 83 | 84 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_TOOL_NAME "altera_fp_functions" 85 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_TOOL_VERSION "17.1" 86 | set_global_assignment -entity "fp_cmp_bias_0002" -library "fp_cmp_bias" -name IP_TOOL_ENV "mwpim" 87 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_cmp_bias.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_cmp_bias" -library "lib_fp_cmp_bias" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_cmp_bias" -library "lib_fp_cmp_bias" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_cmp_bias" -library "lib_fp_cmp_bias" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_fp_cmp_bias" -name SPD_FILE [file join $::quartus(sip_path) "fp_cmp_bias.spd"] 5 | 6 | set_global_assignment -library "lib_fp_cmp_bias" -name MISC_FILE [file join $::quartus(sip_path) "fp_cmp_bias_sim/fp_cmp_bias.vo"] 7 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_cmp_bias.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTERA_FP_FUNCTIONS v17.1% 2 | // GENERATION: XML 3 | // fp_cmp_bias.v 4 | 5 | // Generated using ACDS version 17.1 590 6 | 7 | `timescale 1 ps / 1 ps 8 | module fp_cmp_bias ( 9 | input wire clk, // clk.clk 10 | input wire areset, // areset.reset 11 | input wire [31:0] a, // a.a 12 | input wire [31:0] b, // b.b 13 | output wire [0:0] q // q.q 14 | ); 15 | 16 | fp_cmp_bias_0002 fp_cmp_bias_inst ( 17 | .clk (clk), // clk.clk 18 | .areset (areset), // areset.reset 19 | .a (a), // a.a 20 | .b (b), // b.b 21 | .q (q) // q.q 22 | ); 23 | 24 | endmodule 25 | // Retrieval info: 26 | // 51 | // Retrieval info: 52 | // Retrieval info: 53 | // Retrieval info: 54 | // Retrieval info: 55 | // Retrieval info: 56 | // Retrieval info: 57 | // Retrieval info: 58 | // Retrieval info: 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // Retrieval info: 70 | // Retrieval info: 71 | // Retrieval info: 72 | // Retrieval info: 73 | // Retrieval info: 74 | // Retrieval info: 75 | // Retrieval info: 76 | // Retrieval info: 77 | // Retrieval info: 78 | // Retrieval info: 79 | // Retrieval info: 80 | // Retrieval info: 81 | // Retrieval info: 82 | // Retrieval info: 83 | // Retrieval info: 84 | // Retrieval info: 85 | // Retrieval info: 86 | // Retrieval info: 87 | // Retrieval info: 88 | // Retrieval info: 89 | // Retrieval info: 90 | // Retrieval info: 91 | // IPFS_FILES : fp_cmp_bias.vo 92 | // RELATED_FILES: fp_cmp_bias.v, dspba_library_package.vhd, dspba_library.vhd, fp_cmp_bias_0002.vhd 93 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_cmp_bias/dspba_library.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.dspba_library_package.all; 17 | 18 | entity dspba_delay is 19 | generic ( 20 | width : natural := 8; 21 | depth : natural := 1; 22 | reset_high : std_logic := '1'; 23 | reset_kind : string := "ASYNC" 24 | ); 25 | port ( 26 | clk : in std_logic; 27 | aclr : in std_logic; 28 | ena : in std_logic := '1'; 29 | xin : in std_logic_vector(width-1 downto 0); 30 | xout : out std_logic_vector(width-1 downto 0) 31 | ); 32 | end dspba_delay; 33 | 34 | architecture delay of dspba_delay is 35 | type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0); 36 | signal delay_signals : delay_array; 37 | begin 38 | delay_signals(depth) <= xin; 39 | 40 | delay_block: if 0 < depth generate 41 | begin 42 | delay_loop: for i in depth-1 downto 0 generate 43 | begin 44 | async_reset: if reset_kind = "ASYNC" generate 45 | process(clk, aclr) 46 | begin 47 | if aclr=reset_high then 48 | delay_signals(i) <= (others => '0'); 49 | elsif clk'event and clk='1' then 50 | if ena='1' then 51 | delay_signals(i) <= delay_signals(i + 1); 52 | end if; 53 | end if; 54 | end process; 55 | end generate; 56 | 57 | sync_reset: if reset_kind = "SYNC" generate 58 | process(clk) 59 | begin 60 | if clk'event and clk='1' then 61 | if aclr=reset_high then 62 | delay_signals(i) <= (others => '0'); 63 | elsif ena='1' then 64 | delay_signals(i) <= delay_signals(i + 1); 65 | end if; 66 | end if; 67 | end process; 68 | end generate; 69 | 70 | no_reset: if reset_kind = "NONE" generate 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | if ena='1' then 75 | delay_signals(i) <= delay_signals(i + 1); 76 | end if; 77 | end if; 78 | end process; 79 | end generate; 80 | end generate; 81 | end generate; 82 | 83 | xout <= delay_signals(0); 84 | end delay; 85 | 86 | -------------------------------------------------------------------------------- 87 | 88 | library IEEE; 89 | use IEEE.std_logic_1164.all; 90 | use IEEE.NUMERIC_STD.all; 91 | use work.dspba_library_package.all; 92 | 93 | entity dspba_sync_reg is 94 | generic ( 95 | width1 : natural := 8; 96 | init_value : std_logic_vector; 97 | width2 : natural := 8; 98 | depth : natural := 2; 99 | pulse_multiplier : natural := 1; 100 | counter_width : natural := 8; 101 | reset1_high : std_logic := '1'; 102 | reset2_high : std_logic := '1'; 103 | reset_kind : string := "ASYNC" 104 | ); 105 | port ( 106 | clk1 : in std_logic; 107 | aclr1 : in std_logic; 108 | ena : in std_logic_vector(0 downto 0); 109 | xin : in std_logic_vector(width1-1 downto 0); 110 | xout : out std_logic_vector(width1-1 downto 0); 111 | clk2 : in std_logic; 112 | aclr2 : in std_logic; 113 | sxout : out std_logic_vector(width2-1 downto 0) 114 | ); 115 | end entity; 116 | 117 | architecture sync_reg of dspba_sync_reg is 118 | type bit_array is array (depth-1 downto 0) of std_logic; 119 | 120 | signal iclk_enable : std_logic; 121 | signal iclk_data : std_logic_vector(width1-1 downto 0); 122 | signal oclk_data : std_logic_vector(width2-1 downto 0); 123 | 124 | -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops 125 | -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis 126 | signal sync_regs : bit_array; 127 | attribute altera_attribute : string; 128 | attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; 129 | 130 | signal oclk_enable : std_logic; 131 | 132 | constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value; 133 | 134 | signal counter : UNSIGNED(counter_width-1 downto 0); 135 | signal ena_internal : std_logic; 136 | begin 137 | oclk_enable <= sync_regs(depth-1); 138 | 139 | no_multiplication: if pulse_multiplier=1 generate 140 | ena_internal <= ena(0); 141 | end generate; 142 | 143 | async_reset: if reset_kind="ASYNC" generate 144 | 145 | multiply_ena: if pulse_multiplier>1 generate 146 | ena_internal <= '1' when counter>0 else ena(0); 147 | process (clk1, aclr1) 148 | begin 149 | if aclr1=reset1_high then 150 | counter <= (others => '0'); 151 | elsif clk1'event and clk1='1' then 152 | if counter>0 then 153 | if counter=pulse_multiplier-1 then 154 | counter <= (others => '0'); 155 | else 156 | counter <= counter + TO_UNSIGNED(1, counter_width); 157 | end if; 158 | else 159 | if ena(0)='1' then 160 | counter <= TO_UNSIGNED(1, counter_width); 161 | end if; 162 | end if; 163 | end if; 164 | end process; 165 | end generate; 166 | 167 | process (clk1, aclr1) 168 | begin 169 | if aclr1=reset1_high then 170 | iclk_enable <= '0'; 171 | iclk_data <= init_value_internal; 172 | elsif clk1'event and clk1='1' then 173 | iclk_enable <= ena_internal; 174 | if ena(0)='1' then 175 | iclk_data <= xin; 176 | end if; 177 | end if; 178 | end process; 179 | 180 | sync_reg_loop: for i in 0 to depth-1 generate 181 | process (clk2, aclr2) 182 | begin 183 | if aclr2=reset2_high then 184 | sync_regs(i) <= '0'; 185 | elsif clk2'event and clk2='1' then 186 | if i>0 then 187 | sync_regs(i) <= sync_regs(i-1); 188 | else 189 | sync_regs(i) <= iclk_enable; 190 | end if; 191 | end if; 192 | end process; 193 | end generate; 194 | 195 | process (clk2, aclr2) 196 | begin 197 | if aclr2=reset2_high then 198 | oclk_data <= init_value_internal(width2-1 downto 0); 199 | elsif clk2'event and clk2='1' then 200 | if oclk_enable='1' then 201 | oclk_data <= iclk_data(width2-1 downto 0); 202 | end if; 203 | end if; 204 | end process; 205 | end generate; 206 | 207 | sync_reset: if reset_kind="SYNC" generate 208 | 209 | multiply_ena: if pulse_multiplier>1 generate 210 | ena_internal <= '1' when counter>0 else ena(0); 211 | process (clk1) 212 | begin 213 | if clk1'event and clk1='1' then 214 | if aclr1=reset1_high then 215 | counter <= (others => '0'); 216 | else 217 | if counter>0 then 218 | if counter=pulse_multiplier-1 then 219 | counter <= (others => '0'); 220 | else 221 | counter <= counter + TO_UNSIGNED(1, counter_width); 222 | end if; 223 | else 224 | if ena(0)='1' then 225 | counter <= TO_UNSIGNED(1, counter_width); 226 | end if; 227 | end if; 228 | end if; 229 | end if; 230 | end process; 231 | end generate; 232 | 233 | process (clk1) 234 | begin 235 | if clk1'event and clk1='1' then 236 | if aclr1=reset1_high then 237 | iclk_enable <= '0'; 238 | iclk_data <= init_value_internal; 239 | else 240 | iclk_enable <= ena_internal; 241 | if ena(0)='1' then 242 | iclk_data <= xin; 243 | end if; 244 | end if; 245 | end if; 246 | end process; 247 | 248 | sync_reg_loop: for i in 0 to depth-1 generate 249 | process (clk2) 250 | begin 251 | if clk2'event and clk2='1' then 252 | if aclr2=reset2_high then 253 | sync_regs(i) <= '0'; 254 | else 255 | if i>0 then 256 | sync_regs(i) <= sync_regs(i-1); 257 | else 258 | sync_regs(i) <= iclk_enable; 259 | end if; 260 | end if; 261 | end if; 262 | end process; 263 | end generate; 264 | 265 | process (clk2) 266 | begin 267 | if clk2'event and clk2='1' then 268 | if aclr2=reset2_high then 269 | oclk_data <= init_value_internal(width2-1 downto 0); 270 | elsif oclk_enable='1' then 271 | oclk_data <= iclk_data(width2-1 downto 0); 272 | end if; 273 | end if; 274 | end process; 275 | end generate; 276 | 277 | none_reset: if reset_kind="NONE" generate 278 | 279 | multiply_ena: if pulse_multiplier>1 generate 280 | ena_internal <= '1' when counter>0 else ena(0); 281 | process (clk1, aclr1) 282 | begin 283 | if clk1'event and clk1='1' then 284 | if counter>0 then 285 | if counter=pulse_multiplier-1 then 286 | counter <= (others => '0'); 287 | else 288 | counter <= counter + TO_UNSIGNED(1, counter_width); 289 | end if; 290 | else 291 | if ena(0)='1' then 292 | counter <= TO_UNSIGNED(1, counter_width); 293 | end if; 294 | end if; 295 | end if; 296 | end process; 297 | end generate; 298 | 299 | process (clk1) 300 | begin 301 | if clk1'event and clk1='1' then 302 | iclk_enable <= ena_internal; 303 | if ena(0)='1' then 304 | iclk_data <= xin; 305 | end if; 306 | end if; 307 | end process; 308 | 309 | sync_reg_loop: for i in 0 to depth-1 generate 310 | process (clk2) 311 | begin 312 | if clk2'event and clk2='1' then 313 | if i>0 then 314 | sync_regs(i) <= sync_regs(i-1); 315 | else 316 | sync_regs(i) <= iclk_enable; 317 | end if; 318 | end if; 319 | end process; 320 | end generate; 321 | 322 | process (clk2) 323 | begin 324 | if clk2'event and clk2='1' then 325 | if oclk_enable='1' then 326 | oclk_data <= iclk_data(width2-1 downto 0); 327 | end if; 328 | end if; 329 | end process; 330 | end generate; 331 | 332 | xout <= iclk_data; 333 | sxout <= oclk_data; 334 | 335 | end sync_reg; 336 | 337 | -------------------------------------------------------------------------------- 338 | 339 | library ieee; 340 | use ieee.std_logic_1164.all; 341 | use ieee.numeric_std.all; 342 | 343 | entity dspba_pipe is 344 | generic( 345 | num_bits : positive := 8; 346 | num_stages : natural := 0; 347 | init_value : std_logic := 'X' 348 | ); 349 | port( 350 | clk: in std_logic; 351 | d : in std_logic_vector(num_bits-1 downto 0); 352 | q : out std_logic_vector(num_bits-1 downto 0) 353 | ); 354 | end entity dspba_pipe; 355 | 356 | architecture rtl of dspba_pipe is 357 | attribute altera_attribute : string; 358 | attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; 359 | 360 | type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0); 361 | signal stage_array : stage_array_type := (others => (others => init_value)); 362 | begin 363 | stage_array(0) <= d; 364 | 365 | g_pipe : for i in 1 to num_stages generate 366 | p_stage : process (clk) is 367 | begin 368 | if rising_edge(clk) then 369 | stage_array(i) <= stage_array(i-1); 370 | end if; 371 | end process p_stage; 372 | end generate g_pipe; 373 | 374 | q <= stage_array(num_stages); 375 | 376 | end rtl; 377 | 378 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/7.bias_add/ip_core/fp_cmp_bias/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/calc_unit_single.v: -------------------------------------------------------------------------------- 1 | module calc_unit_single( 2 | input clk_100M, 3 | input rst_n, 4 | 5 | input [32*9-1:0] w_in, 6 | input data_in_vld, 7 | input [32*9-1:0] data_in, 8 | 9 | // input [7:0] acc_para, 10 | input new_start, 11 | 12 | // output data_out_vld, 13 | output [31:0] data_out 14 | ); 15 | 16 | //------------------------------------------- 17 | // mul of input 18 | //------------------------------------------- 19 | wire [31:0] mul_a[8:0]; 20 | wire [31:0] mul_b[8:0]; 21 | wire [31:0] mul_o[8:0]; 22 | genvar i; 23 | integer j; 24 | 25 | generate 26 | for (i = 0; i < 9; i = i + 1) begin : mul_data 27 | assign mul_a[i] = data_in[32*i+31:32*i]; 28 | assign mul_b[i] = w_in[32*i+31:32*i]; 29 | end 30 | endgenerate 31 | 32 | generate 33 | for (i = 0; i < 9; i = i + 1) begin : mul_gen 34 | fp_mul mul 35 | ( 36 | .clk (clk_100M), // clk.clk 37 | .areset (~rst_n), // areset.reset 38 | .a (mul_a[i]), // a.a 39 | .b (mul_b[i]), // b.b 40 | .q (mul_o[i]) // q.q 41 | ); 42 | end 43 | endgenerate 44 | 45 | //------------------------------------------- 46 | // add of mul 47 | //------------------------------------------- 48 | wire [31:0] add_of2[3:0]; 49 | generate 50 | for (i = 0; i < 4; i = i + 1) begin : add_of_2_gen 51 | fp_add fp_add_2 52 | ( 53 | .clk (clk_100M), // clk.clk 54 | .areset (~rst_n), // areset.reset 55 | .a (mul_o[2 * i]), // a.a 56 | .b (mul_o[2 * i + 1]), // b.b 57 | .q (add_of2[i]) // q.q 58 | ); 59 | end 60 | endgenerate 61 | 62 | wire [31:0] add_of4[1:0]; 63 | generate 64 | for (i = 0; i < 2; i = i + 1) begin : add_of_4_gen 65 | fp_add fp_add_4 66 | ( 67 | .clk (clk_100M), // clk.clk 68 | .areset (~rst_n), // areset.reset 69 | .a (add_of2[2 * i]), // a.a 70 | .b (add_of2[2 * i + 1]), // b.b 71 | .q (add_of4[i]) // q.q 72 | ); 73 | end 74 | endgenerate 75 | 76 | wire [31:0] add_of8; 77 | 78 | fp_add fp_add_8( 79 | .clk (clk_100M), // clk.clk 80 | .areset (~rst_n), // areset.reset 81 | .a (add_of4[0]), // a.a 82 | .b (add_of4[1]), // b.b 83 | .q (add_of8) // q.q 84 | ); 85 | 86 | wire [31:0] add_ofall; 87 | reg [31:0] mul_o8_reg[20:0]; 88 | 89 | always @ (posedge clk_100M or negedge rst_n) 90 | begin 91 | if(!rst_n) begin 92 | for (j = 0; j < 21; j = j + 1) begin 93 | mul_o8_reg[j] <= 32'd0; 94 | end 95 | end 96 | else begin 97 | for (j = 0; j < 21; j = j + 1) begin 98 | if (j == 0) begin 99 | mul_o8_reg[0] <= mul_o[8]; 100 | end 101 | else begin 102 | mul_o8_reg[j] <= mul_o8_reg[j - 1]; 103 | end 104 | end 105 | end 106 | end 107 | 108 | fp_add add_all( 109 | .clk (clk_100M), // clk.clk 110 | .areset (~rst_n), // areset.reset 111 | .a (add_of8), // a.a 112 | .b (mul_o8_reg[17]), // b.b 113 | .q (add_ofall) // q.q 114 | ); 115 | 116 | //------------------------------------------- 117 | // acc of add 118 | //------------------------------------------- 119 | 120 | reg [27:0] n_s_reg; 121 | always @ (posedge clk_100M or negedge rst_n) 122 | begin 123 | if(!rst_n) begin 124 | n_s_reg <= 28'b0; 125 | end 126 | else begin 127 | n_s_reg <= {n_s_reg[26:0], new_start}; 128 | end 129 | end 130 | 131 | reg [27:0] data_in_vld_reg; 132 | always @ (posedge clk_100M or negedge rst_n) 133 | begin 134 | if(!rst_n) begin 135 | data_in_vld_reg <= 28'b0; 136 | end 137 | else begin 138 | data_in_vld_reg <= {data_in_vld_reg[26:0], data_in_vld}; 139 | end 140 | end 141 | 142 | // reg [7:0] acc_para_reg[27:0]; 143 | // always @ (posedge clk_100M or negedge rst_n) 144 | // begin 145 | // if(!rst_n) begin 146 | // for (j = 0; j < 28; j = j + 1) begin 147 | // acc_para_reg[j] <= 8'd255; 148 | // end 149 | // end 150 | // else begin 151 | // for (j = 0; j < 28; j = j + 1) begin 152 | // if(j == 0) begin 153 | // acc_para_reg[0] <= acc_para; 154 | // end 155 | // else begin 156 | // acc_para_reg[j] <= acc_para_reg[j - 1]; 157 | // end 158 | // end 159 | // end 160 | // end 161 | 162 | 163 | // reg [7:0] acc_cnt_cur; 164 | // always @ (posedge clk_100M or negedge rst_n) 165 | // begin 166 | // if(!rst_n) begin 167 | // acc_cnt_cur <= 8'b0; 168 | // end 169 | // else if (acc_cnt_cur >= acc_para) begin 170 | // acc_cnt_cur <= 8'b0; 171 | // end 172 | // else if (data_in_vld == 1'b1) begin 173 | // acc_cnt_cur <= acc_cnt_cur + 1'b1; 174 | // end 175 | // end 176 | 177 | // wire data_out_vld_cur; 178 | // assign data_out_vld_cur = (acc_cnt_cur == acc_para) && (data_in_vld == 1'b1); 179 | 180 | // reg [31:0] data_out_vld_reg; 181 | // always @ (posedge clk_100M or negedge rst_n) 182 | // begin 183 | // if(!rst_n) begin 184 | // data_out_vld_reg <= 31'b0; 185 | // end 186 | // else begin 187 | // data_out_vld_reg <= {data_out_vld_reg[30:0], data_out_vld_cur}; 188 | // end 189 | // end 190 | 191 | wire [31:0] acc_in; 192 | wire [31:0] acc_out; 193 | assign acc_in = data_in_vld_reg[27] ? add_ofall : 32'b0; 194 | 195 | fp_acc acc( 196 | .clk (clk_100M), // clk.clk 197 | .areset (~rst_n), // areset.reset 198 | .x (acc_in), // x.x 199 | .n (n_s_reg[27]), // n.n 200 | .r (acc_out), // r.r 201 | .xo (), // xo.xo 202 | .xu (), // xu.xu 203 | .ao (), // ao.ao 204 | .en (1'b1) // en.en 205 | ); 206 | 207 | assign data_out = acc_out; 208 | // assign data_out_vld = data_out_vld_reg[31]; 209 | 210 | endmodule -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/calc_unit_x16.v: -------------------------------------------------------------------------------- 1 | module calc_unit_x16( 2 | input clk_100M, 3 | input rst_n, 4 | 5 | input [32*9*16-1:0] w_in, 6 | input data_in_vld, 7 | input [32*9*16-1:0] data_in, 8 | 9 | input [7:0] acc_para, 10 | input new_start, 11 | 12 | output data_out_vld, 13 | output [32*16-1:0] data_out 14 | ); 15 | 16 | 17 | genvar i; 18 | generate 19 | for(i = 0; i < 16; i = i + 1) begin : calc_unit_gen 20 | calc_unit_single calc_unit_single( 21 | .clk_100M (clk_100M), 22 | .rst_n (rst_n), 23 | .w_in (w_in[i*288+287:i*288]), 24 | .data_in_vld (data_in_vld), 25 | .data_in (data_in[i*288+287:i*288]), 26 | .new_start (new_start), 27 | .data_out (data_out[i*32+31:i*32]) 28 | ); 29 | end 30 | endgenerate 31 | 32 | reg [7:0] acc_cnt_cur; 33 | always @ (posedge clk_100M or negedge rst_n) 34 | begin 35 | if(!rst_n) begin 36 | acc_cnt_cur <= 8'b0; 37 | end 38 | else if (acc_cnt_cur >= acc_para) begin 39 | acc_cnt_cur <= 8'b0; 40 | end 41 | else if (data_in_vld == 1'b1) begin 42 | acc_cnt_cur <= acc_cnt_cur + 1'b1; 43 | end 44 | end 45 | 46 | wire data_out_vld_cur; 47 | assign data_out_vld_cur = (acc_cnt_cur == acc_para) && (data_in_vld == 1'b1); 48 | 49 | reg [31:0] data_out_vld_reg; 50 | always @ (posedge clk_100M or negedge rst_n) 51 | begin 52 | if(!rst_n) begin 53 | data_out_vld_reg <= 31'b0; 54 | end 55 | else begin 56 | data_out_vld_reg <= {data_out_vld_reg[30:0], data_out_vld_cur}; 57 | end 58 | end 59 | 60 | assign data_out_vld = data_out_vld_reg[31]; 61 | 62 | endmodule -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_acc.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_TOOL_NAME "altera_fp_acc_custom" 2 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "fp_acc" -name MISC_FILE [file join $::quartus(qip_path) "fp_acc.cmp"] 5 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" 6 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 7 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_NAME "ZnBfYWNj" 10 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0FDQ19DVVNUT00=" 11 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 14 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_VERSION "MTcuMQ==" 15 | set_global_assignment -entity "fp_acc" -library "fp_acc" -name IP_COMPONENT_DESCRIPTION "QW4gYXBwbGljYXRpb24tc3BlY2lmaWMgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IuIEEgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IgdGhhdCBjYW4gYmUgY3VzdG9taXplZCB0byB0aGUgcmVxdWlyZWQgcmFuZ2Ugb2YgaW5wdXQgYW5kIG91dHB1dCB2YWx1ZXMuIFRoZSBhY2N1bXVsYXRvciB3aWxsIGJlIGJ1aWx0IHRvIG9wZXJhdGUgYXQgdGhlIHRhcmdldCBmcmVxdWVuY3kgb24gdGhlIHRhcmdldCBkZXZpY2UgZmFtaWx5Lg==" 16 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_NAME "ZnBfYWNjXzAwMDI=" 17 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0FDQ19DVVNUT00=" 18 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 19 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_INTERNAL "Off" 20 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 21 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_VERSION "MTcuMQ==" 22 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_DESCRIPTION "QW4gYXBwbGljYXRpb24tc3BlY2lmaWMgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IuIEEgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IgdGhhdCBjYW4gYmUgY3VzdG9taXplZCB0byB0aGUgcmVxdWlyZWQgcmFuZ2Ugb2YgaW5wdXQgYW5kIG91dHB1dCB2YWx1ZXMuIFRoZSBhY2N1bXVsYXRvciB3aWxsIGJlIGJ1aWx0IHRvIG9wZXJhdGUgYXQgdGhlIHRhcmdldCBmcmVxdWVuY3kgb24gdGhlIHRhcmdldCBkZXZpY2UgZmFtaWx5Lg==" 23 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::RmxvYXRpbmcgcG9pbnQgZm9ybWF0" 24 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5::MTAw::VGFyZ2V0IGZyZXF1ZW5jeQ==" 25 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::dHJ1ZQ==::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" 26 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "TVNCQQ==::MjA=::TVNCQQ==" 27 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "bWF4TVNCWA==::MTI=::bWF4TVNCWA==" 28 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "TFNCQQ==::LTI2::TFNCQQ==" 29 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" 30 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=" 31 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ=" 32 | 33 | set_global_assignment -library "fp_acc" -name VERILOG_FILE [file join $::quartus(qip_path) "fp_acc.v"] 34 | set_global_assignment -library "fp_acc" -name VHDL_FILE [file join $::quartus(qip_path) "fp_acc/dspba_library_package.vhd"] 35 | set_global_assignment -library "fp_acc" -name VHDL_FILE [file join $::quartus(qip_path) "fp_acc/dspba_library.vhd"] 36 | set_global_assignment -library "fp_acc" -name VHDL_FILE [file join $::quartus(qip_path) "fp_acc/fp_acc_0002.vhd"] 37 | 38 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_TOOL_NAME "altera_fp_acc_custom" 39 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_TOOL_VERSION "17.1" 40 | set_global_assignment -entity "fp_acc_0002" -library "fp_acc" -name IP_TOOL_ENV "mwpim" 41 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_acc.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_acc" -library "lib_fp_acc" -name IP_TOOL_NAME "altera_fp_acc_custom" 2 | set_global_assignment -entity "fp_acc" -library "lib_fp_acc" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_acc" -library "lib_fp_acc" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_fp_acc" -name SPD_FILE [file join $::quartus(sip_path) "fp_acc.spd"] 5 | 6 | set_global_assignment -library "lib_fp_acc" -name MISC_FILE [file join $::quartus(sip_path) "fp_acc_sim/dspba_library_package.vhd"] 7 | set_global_assignment -library "lib_fp_acc" -name MISC_FILE [file join $::quartus(sip_path) "fp_acc_sim/dspba_library.vhd"] 8 | set_global_assignment -library "lib_fp_acc" -name MISC_FILE [file join $::quartus(sip_path) "fp_acc_sim/fp_acc.vhd"] 9 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_acc.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTERA_FP_ACC_CUSTOM v17.1% 2 | // GENERATION: XML 3 | // fp_acc.v 4 | 5 | // Generated using ACDS version 17.1 590 6 | 7 | `timescale 1 ps / 1 ps 8 | module fp_acc ( 9 | input wire clk, // clk.clk 10 | input wire areset, // areset.reset 11 | input wire [31:0] x, // x.x 12 | input wire n, // n.n 13 | output wire [31:0] r, // r.r 14 | output wire xo, // xo.xo 15 | output wire xu, // xu.xu 16 | output wire ao, // ao.ao 17 | input wire [0:0] en // en.en 18 | ); 19 | 20 | fp_acc_0002 fp_acc_inst ( 21 | .clk (clk), // clk.clk 22 | .areset (areset), // areset.reset 23 | .x (x), // x.x 24 | .n (n), // n.n 25 | .r (r), // r.r 26 | .xo (xo), // xo.xo 27 | .xu (xu), // xu.xu 28 | .ao (ao), // ao.ao 29 | .en (en) // en.en 30 | ); 31 | 32 | endmodule 33 | // Retrieval info: 34 | // 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // IPFS_FILES : fp_acc.vo 70 | // RELATED_FILES: fp_acc.v, dspba_library_package.vhd, dspba_library.vhd, fp_acc_0002.vhd 71 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_acc/dspba_library.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.dspba_library_package.all; 17 | 18 | entity dspba_delay is 19 | generic ( 20 | width : natural := 8; 21 | depth : natural := 1; 22 | reset_high : std_logic := '1'; 23 | reset_kind : string := "ASYNC" 24 | ); 25 | port ( 26 | clk : in std_logic; 27 | aclr : in std_logic; 28 | ena : in std_logic := '1'; 29 | xin : in std_logic_vector(width-1 downto 0); 30 | xout : out std_logic_vector(width-1 downto 0) 31 | ); 32 | end dspba_delay; 33 | 34 | architecture delay of dspba_delay is 35 | type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0); 36 | signal delay_signals : delay_array; 37 | begin 38 | delay_signals(depth) <= xin; 39 | 40 | delay_block: if 0 < depth generate 41 | begin 42 | delay_loop: for i in depth-1 downto 0 generate 43 | begin 44 | async_reset: if reset_kind = "ASYNC" generate 45 | process(clk, aclr) 46 | begin 47 | if aclr=reset_high then 48 | delay_signals(i) <= (others => '0'); 49 | elsif clk'event and clk='1' then 50 | if ena='1' then 51 | delay_signals(i) <= delay_signals(i + 1); 52 | end if; 53 | end if; 54 | end process; 55 | end generate; 56 | 57 | sync_reset: if reset_kind = "SYNC" generate 58 | process(clk) 59 | begin 60 | if clk'event and clk='1' then 61 | if aclr=reset_high then 62 | delay_signals(i) <= (others => '0'); 63 | elsif ena='1' then 64 | delay_signals(i) <= delay_signals(i + 1); 65 | end if; 66 | end if; 67 | end process; 68 | end generate; 69 | 70 | no_reset: if reset_kind = "NONE" generate 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | if ena='1' then 75 | delay_signals(i) <= delay_signals(i + 1); 76 | end if; 77 | end if; 78 | end process; 79 | end generate; 80 | end generate; 81 | end generate; 82 | 83 | xout <= delay_signals(0); 84 | end delay; 85 | 86 | -------------------------------------------------------------------------------- 87 | 88 | library IEEE; 89 | use IEEE.std_logic_1164.all; 90 | use IEEE.NUMERIC_STD.all; 91 | use work.dspba_library_package.all; 92 | 93 | entity dspba_sync_reg is 94 | generic ( 95 | width1 : natural := 8; 96 | init_value : std_logic_vector; 97 | width2 : natural := 8; 98 | depth : natural := 2; 99 | pulse_multiplier : natural := 1; 100 | counter_width : natural := 8; 101 | reset1_high : std_logic := '1'; 102 | reset2_high : std_logic := '1'; 103 | reset_kind : string := "ASYNC" 104 | ); 105 | port ( 106 | clk1 : in std_logic; 107 | aclr1 : in std_logic; 108 | ena : in std_logic_vector(0 downto 0); 109 | xin : in std_logic_vector(width1-1 downto 0); 110 | xout : out std_logic_vector(width1-1 downto 0); 111 | clk2 : in std_logic; 112 | aclr2 : in std_logic; 113 | sxout : out std_logic_vector(width2-1 downto 0) 114 | ); 115 | end entity; 116 | 117 | architecture sync_reg of dspba_sync_reg is 118 | type bit_array is array (depth-1 downto 0) of std_logic; 119 | 120 | signal iclk_enable : std_logic; 121 | signal iclk_data : std_logic_vector(width1-1 downto 0); 122 | signal oclk_data : std_logic_vector(width2-1 downto 0); 123 | 124 | -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops 125 | -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis 126 | signal sync_regs : bit_array; 127 | attribute altera_attribute : string; 128 | attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; 129 | 130 | signal oclk_enable : std_logic; 131 | 132 | constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value; 133 | 134 | signal counter : UNSIGNED(counter_width-1 downto 0); 135 | signal ena_internal : std_logic; 136 | begin 137 | oclk_enable <= sync_regs(depth-1); 138 | 139 | no_multiplication: if pulse_multiplier=1 generate 140 | ena_internal <= ena(0); 141 | end generate; 142 | 143 | async_reset: if reset_kind="ASYNC" generate 144 | 145 | multiply_ena: if pulse_multiplier>1 generate 146 | ena_internal <= '1' when counter>0 else ena(0); 147 | process (clk1, aclr1) 148 | begin 149 | if aclr1=reset1_high then 150 | counter <= (others => '0'); 151 | elsif clk1'event and clk1='1' then 152 | if counter>0 then 153 | if counter=pulse_multiplier-1 then 154 | counter <= (others => '0'); 155 | else 156 | counter <= counter + TO_UNSIGNED(1, counter_width); 157 | end if; 158 | else 159 | if ena(0)='1' then 160 | counter <= TO_UNSIGNED(1, counter_width); 161 | end if; 162 | end if; 163 | end if; 164 | end process; 165 | end generate; 166 | 167 | process (clk1, aclr1) 168 | begin 169 | if aclr1=reset1_high then 170 | iclk_enable <= '0'; 171 | iclk_data <= init_value_internal; 172 | elsif clk1'event and clk1='1' then 173 | iclk_enable <= ena_internal; 174 | if ena(0)='1' then 175 | iclk_data <= xin; 176 | end if; 177 | end if; 178 | end process; 179 | 180 | sync_reg_loop: for i in 0 to depth-1 generate 181 | process (clk2, aclr2) 182 | begin 183 | if aclr2=reset2_high then 184 | sync_regs(i) <= '0'; 185 | elsif clk2'event and clk2='1' then 186 | if i>0 then 187 | sync_regs(i) <= sync_regs(i-1); 188 | else 189 | sync_regs(i) <= iclk_enable; 190 | end if; 191 | end if; 192 | end process; 193 | end generate; 194 | 195 | process (clk2, aclr2) 196 | begin 197 | if aclr2=reset2_high then 198 | oclk_data <= init_value_internal(width2-1 downto 0); 199 | elsif clk2'event and clk2='1' then 200 | if oclk_enable='1' then 201 | oclk_data <= iclk_data(width2-1 downto 0); 202 | end if; 203 | end if; 204 | end process; 205 | end generate; 206 | 207 | sync_reset: if reset_kind="SYNC" generate 208 | 209 | multiply_ena: if pulse_multiplier>1 generate 210 | ena_internal <= '1' when counter>0 else ena(0); 211 | process (clk1) 212 | begin 213 | if clk1'event and clk1='1' then 214 | if aclr1=reset1_high then 215 | counter <= (others => '0'); 216 | else 217 | if counter>0 then 218 | if counter=pulse_multiplier-1 then 219 | counter <= (others => '0'); 220 | else 221 | counter <= counter + TO_UNSIGNED(1, counter_width); 222 | end if; 223 | else 224 | if ena(0)='1' then 225 | counter <= TO_UNSIGNED(1, counter_width); 226 | end if; 227 | end if; 228 | end if; 229 | end if; 230 | end process; 231 | end generate; 232 | 233 | process (clk1) 234 | begin 235 | if clk1'event and clk1='1' then 236 | if aclr1=reset1_high then 237 | iclk_enable <= '0'; 238 | iclk_data <= init_value_internal; 239 | else 240 | iclk_enable <= ena_internal; 241 | if ena(0)='1' then 242 | iclk_data <= xin; 243 | end if; 244 | end if; 245 | end if; 246 | end process; 247 | 248 | sync_reg_loop: for i in 0 to depth-1 generate 249 | process (clk2) 250 | begin 251 | if clk2'event and clk2='1' then 252 | if aclr2=reset2_high then 253 | sync_regs(i) <= '0'; 254 | else 255 | if i>0 then 256 | sync_regs(i) <= sync_regs(i-1); 257 | else 258 | sync_regs(i) <= iclk_enable; 259 | end if; 260 | end if; 261 | end if; 262 | end process; 263 | end generate; 264 | 265 | process (clk2) 266 | begin 267 | if clk2'event and clk2='1' then 268 | if aclr2=reset2_high then 269 | oclk_data <= init_value_internal(width2-1 downto 0); 270 | elsif oclk_enable='1' then 271 | oclk_data <= iclk_data(width2-1 downto 0); 272 | end if; 273 | end if; 274 | end process; 275 | end generate; 276 | 277 | none_reset: if reset_kind="NONE" generate 278 | 279 | multiply_ena: if pulse_multiplier>1 generate 280 | ena_internal <= '1' when counter>0 else ena(0); 281 | process (clk1, aclr1) 282 | begin 283 | if clk1'event and clk1='1' then 284 | if counter>0 then 285 | if counter=pulse_multiplier-1 then 286 | counter <= (others => '0'); 287 | else 288 | counter <= counter + TO_UNSIGNED(1, counter_width); 289 | end if; 290 | else 291 | if ena(0)='1' then 292 | counter <= TO_UNSIGNED(1, counter_width); 293 | end if; 294 | end if; 295 | end if; 296 | end process; 297 | end generate; 298 | 299 | process (clk1) 300 | begin 301 | if clk1'event and clk1='1' then 302 | iclk_enable <= ena_internal; 303 | if ena(0)='1' then 304 | iclk_data <= xin; 305 | end if; 306 | end if; 307 | end process; 308 | 309 | sync_reg_loop: for i in 0 to depth-1 generate 310 | process (clk2) 311 | begin 312 | if clk2'event and clk2='1' then 313 | if i>0 then 314 | sync_regs(i) <= sync_regs(i-1); 315 | else 316 | sync_regs(i) <= iclk_enable; 317 | end if; 318 | end if; 319 | end process; 320 | end generate; 321 | 322 | process (clk2) 323 | begin 324 | if clk2'event and clk2='1' then 325 | if oclk_enable='1' then 326 | oclk_data <= iclk_data(width2-1 downto 0); 327 | end if; 328 | end if; 329 | end process; 330 | end generate; 331 | 332 | xout <= iclk_data; 333 | sxout <= oclk_data; 334 | 335 | end sync_reg; 336 | 337 | -------------------------------------------------------------------------------- 338 | 339 | library ieee; 340 | use ieee.std_logic_1164.all; 341 | use ieee.numeric_std.all; 342 | 343 | entity dspba_pipe is 344 | generic( 345 | num_bits : positive := 8; 346 | num_stages : natural := 0; 347 | init_value : std_logic := 'X' 348 | ); 349 | port( 350 | clk: in std_logic; 351 | d : in std_logic_vector(num_bits-1 downto 0); 352 | q : out std_logic_vector(num_bits-1 downto 0) 353 | ); 354 | end entity dspba_pipe; 355 | 356 | architecture rtl of dspba_pipe is 357 | attribute altera_attribute : string; 358 | attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; 359 | 360 | type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0); 361 | signal stage_array : stage_array_type := (others => (others => init_value)); 362 | begin 363 | stage_array(0) <= d; 364 | 365 | g_pipe : for i in 1 to num_stages generate 366 | p_stage : process (clk) is 367 | begin 368 | if rising_edge(clk) then 369 | stage_array(i) <= stage_array(i-1); 370 | end if; 371 | end process p_stage; 372 | end generate g_pipe; 373 | 374 | q <= stage_array(num_stages); 375 | 376 | end rtl; 377 | 378 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_acc/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_add.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "fp_add" -name MISC_FILE [file join $::quartus(qip_path) "fp_add.cmp"] 5 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" 6 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 7 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_NAME "ZnBfYWRk" 10 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 11 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 14 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_VERSION "MTcuMQ==" 15 | set_global_assignment -entity "fp_add" -library "fp_add" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 16 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_NAME "ZnBfYWRkXzAwMDI=" 17 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 18 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 19 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_INTERNAL "Off" 20 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 21 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_VERSION "MTcuMQ==" 22 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 23 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05fRkFNSUxZ::QVJJVEg=::RmFtaWx5" 24 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "QVJJVEhfZnVuY3Rpb24=::QURE::TmFtZQ==" 25 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "Q09OVkVSVF9mdW5jdGlvbg==::RlhQX0ZQ::TmFtZQ==" 26 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "QUxMX2Z1bmN0aW9u::QURE::TmFtZQ==" 27 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "RVhQX0xPR19mdW5jdGlvbg==::RVhQRQ==::TmFtZQ==" 28 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "VFJJR19mdW5jdGlvbg==::U0lO::TmFtZQ==" 29 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ==" 30 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ==" 31 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::QURE::ZGVyaXZlZGZ1bmN0aW9u" 32 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0" 33 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ=" 34 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ=" 35 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E=" 36 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ=" 37 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" 38 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" 39 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::Ng==::VGFyZ2V0" 40 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::Y29tYmluZWQ=::R29hbA==" 41 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" 42 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" 43 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU=" 44 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::ZmFsc2U=::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U=" 45 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" 46 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k" 47 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw=" 48 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp" 49 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2lucHV0cw==::Mg==::SW5wdXQgVmVjdG9yIERpbWVuc2lvbg==" 50 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "dHJpZ19ub19yYW5nZV9yZWR1Y3Rpb24=::ZmFsc2U=::SW5wdXRzIGFyZSB3aXRoaW4gcmFuZ2UgLTJwaSB0byArMnBp" 51 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "cmVwb3J0X3Jlc291cmNlc190b194bWw=::ZmFsc2U=::cmVwb3J0X3Jlc291cmNlc190b194bWw=" 52 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg=" 53 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" 54 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" 55 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" 56 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::Ng==::bGF0ZW5jeV9mZWVkYmFjaw==" 57 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" 58 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" 59 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" 60 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cF9kZXJpdmVk::OA==::ZnBfb3V0X2V4cF9kZXJpdmVk" 61 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbg==::MjM=::T3V0cHV0IE1hbnRpc3Nh" 62 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbl9kZXJpdmVk::OA==::ZnBfb3V0X21hbl9kZXJpdmVk" 63 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZm9ybWF0::c2luZ2xl::SW5wdXQgRm9ybWF0" 64 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhw::OA==::SW5wdXQgRXhwb25lbnQ=" 65 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhwX2Rlcml2ZWQ=::OA==::ZnBfaW5fZXhwX2Rlcml2ZWQ=" 66 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFu::MjM=::SW5wdXQgTWFudGlzc2E=" 67 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFuX2Rlcml2ZWQ=::OA==::ZnBfaW5fbWFuX2Rlcml2ZWQ=" 68 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 69 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 70 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" 71 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::MA==::TXVsdGlwbGllcw==" 72 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::ODM0::TFVUcw==" 73 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" 74 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" 75 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" 76 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=" 77 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ=" 78 | 79 | set_global_assignment -library "fp_add" -name VERILOG_FILE [file join $::quartus(qip_path) "fp_add.v"] 80 | set_global_assignment -library "fp_add" -name VHDL_FILE [file join $::quartus(qip_path) "fp_add/dspba_library_package.vhd"] 81 | set_global_assignment -library "fp_add" -name VHDL_FILE [file join $::quartus(qip_path) "fp_add/dspba_library.vhd"] 82 | set_global_assignment -library "fp_add" -name VHDL_FILE [file join $::quartus(qip_path) "fp_add/fp_add_0002.vhd"] 83 | 84 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_TOOL_NAME "altera_fp_functions" 85 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_TOOL_VERSION "17.1" 86 | set_global_assignment -entity "fp_add_0002" -library "fp_add" -name IP_TOOL_ENV "mwpim" 87 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_add.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_add" -library "lib_fp_add" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_add" -library "lib_fp_add" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_add" -library "lib_fp_add" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_fp_add" -name SPD_FILE [file join $::quartus(sip_path) "fp_add.spd"] 5 | 6 | set_global_assignment -library "lib_fp_add" -name MISC_FILE [file join $::quartus(sip_path) "fp_add_sim/fp_add.vo"] 7 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_add.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTERA_FP_FUNCTIONS v17.1% 2 | // GENERATION: XML 3 | // fp_add.v 4 | 5 | // Generated using ACDS version 17.1 590 6 | 7 | `timescale 1 ps / 1 ps 8 | module fp_add ( 9 | input wire clk, // clk.clk 10 | input wire areset, // areset.reset 11 | input wire [31:0] a, // a.a 12 | input wire [31:0] b, // b.b 13 | output wire [31:0] q // q.q 14 | ); 15 | 16 | fp_add_0002 fp_add_inst ( 17 | .clk (clk), // clk.clk 18 | .areset (areset), // areset.reset 19 | .a (a), // a.a 20 | .b (b), // b.b 21 | .q (q) // q.q 22 | ); 23 | 24 | endmodule 25 | // Retrieval info: 26 | // 51 | // Retrieval info: 52 | // Retrieval info: 53 | // Retrieval info: 54 | // Retrieval info: 55 | // Retrieval info: 56 | // Retrieval info: 57 | // Retrieval info: 58 | // Retrieval info: 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // Retrieval info: 70 | // Retrieval info: 71 | // Retrieval info: 72 | // Retrieval info: 73 | // Retrieval info: 74 | // Retrieval info: 75 | // Retrieval info: 76 | // Retrieval info: 77 | // Retrieval info: 78 | // Retrieval info: 79 | // Retrieval info: 80 | // Retrieval info: 81 | // Retrieval info: 82 | // Retrieval info: 83 | // Retrieval info: 84 | // Retrieval info: 85 | // Retrieval info: 86 | // Retrieval info: 87 | // Retrieval info: 88 | // Retrieval info: 89 | // Retrieval info: 90 | // Retrieval info: 91 | // IPFS_FILES : fp_add.vo 92 | // RELATED_FILES: fp_add.v, dspba_library_package.vhd, dspba_library.vhd, fp_add_0002.vhd 93 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_add/dspba_library.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.dspba_library_package.all; 17 | 18 | entity dspba_delay is 19 | generic ( 20 | width : natural := 8; 21 | depth : natural := 1; 22 | reset_high : std_logic := '1'; 23 | reset_kind : string := "ASYNC" 24 | ); 25 | port ( 26 | clk : in std_logic; 27 | aclr : in std_logic; 28 | ena : in std_logic := '1'; 29 | xin : in std_logic_vector(width-1 downto 0); 30 | xout : out std_logic_vector(width-1 downto 0) 31 | ); 32 | end dspba_delay; 33 | 34 | architecture delay of dspba_delay is 35 | type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0); 36 | signal delay_signals : delay_array; 37 | begin 38 | delay_signals(depth) <= xin; 39 | 40 | delay_block: if 0 < depth generate 41 | begin 42 | delay_loop: for i in depth-1 downto 0 generate 43 | begin 44 | async_reset: if reset_kind = "ASYNC" generate 45 | process(clk, aclr) 46 | begin 47 | if aclr=reset_high then 48 | delay_signals(i) <= (others => '0'); 49 | elsif clk'event and clk='1' then 50 | if ena='1' then 51 | delay_signals(i) <= delay_signals(i + 1); 52 | end if; 53 | end if; 54 | end process; 55 | end generate; 56 | 57 | sync_reset: if reset_kind = "SYNC" generate 58 | process(clk) 59 | begin 60 | if clk'event and clk='1' then 61 | if aclr=reset_high then 62 | delay_signals(i) <= (others => '0'); 63 | elsif ena='1' then 64 | delay_signals(i) <= delay_signals(i + 1); 65 | end if; 66 | end if; 67 | end process; 68 | end generate; 69 | 70 | no_reset: if reset_kind = "NONE" generate 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | if ena='1' then 75 | delay_signals(i) <= delay_signals(i + 1); 76 | end if; 77 | end if; 78 | end process; 79 | end generate; 80 | end generate; 81 | end generate; 82 | 83 | xout <= delay_signals(0); 84 | end delay; 85 | 86 | -------------------------------------------------------------------------------- 87 | 88 | library IEEE; 89 | use IEEE.std_logic_1164.all; 90 | use IEEE.NUMERIC_STD.all; 91 | use work.dspba_library_package.all; 92 | 93 | entity dspba_sync_reg is 94 | generic ( 95 | width1 : natural := 8; 96 | init_value : std_logic_vector; 97 | width2 : natural := 8; 98 | depth : natural := 2; 99 | pulse_multiplier : natural := 1; 100 | counter_width : natural := 8; 101 | reset1_high : std_logic := '1'; 102 | reset2_high : std_logic := '1'; 103 | reset_kind : string := "ASYNC" 104 | ); 105 | port ( 106 | clk1 : in std_logic; 107 | aclr1 : in std_logic; 108 | ena : in std_logic_vector(0 downto 0); 109 | xin : in std_logic_vector(width1-1 downto 0); 110 | xout : out std_logic_vector(width1-1 downto 0); 111 | clk2 : in std_logic; 112 | aclr2 : in std_logic; 113 | sxout : out std_logic_vector(width2-1 downto 0) 114 | ); 115 | end entity; 116 | 117 | architecture sync_reg of dspba_sync_reg is 118 | type bit_array is array (depth-1 downto 0) of std_logic; 119 | 120 | signal iclk_enable : std_logic; 121 | signal iclk_data : std_logic_vector(width1-1 downto 0); 122 | signal oclk_data : std_logic_vector(width2-1 downto 0); 123 | 124 | -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops 125 | -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis 126 | signal sync_regs : bit_array; 127 | attribute altera_attribute : string; 128 | attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; 129 | 130 | signal oclk_enable : std_logic; 131 | 132 | constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value; 133 | 134 | signal counter : UNSIGNED(counter_width-1 downto 0); 135 | signal ena_internal : std_logic; 136 | begin 137 | oclk_enable <= sync_regs(depth-1); 138 | 139 | no_multiplication: if pulse_multiplier=1 generate 140 | ena_internal <= ena(0); 141 | end generate; 142 | 143 | async_reset: if reset_kind="ASYNC" generate 144 | 145 | multiply_ena: if pulse_multiplier>1 generate 146 | ena_internal <= '1' when counter>0 else ena(0); 147 | process (clk1, aclr1) 148 | begin 149 | if aclr1=reset1_high then 150 | counter <= (others => '0'); 151 | elsif clk1'event and clk1='1' then 152 | if counter>0 then 153 | if counter=pulse_multiplier-1 then 154 | counter <= (others => '0'); 155 | else 156 | counter <= counter + TO_UNSIGNED(1, counter_width); 157 | end if; 158 | else 159 | if ena(0)='1' then 160 | counter <= TO_UNSIGNED(1, counter_width); 161 | end if; 162 | end if; 163 | end if; 164 | end process; 165 | end generate; 166 | 167 | process (clk1, aclr1) 168 | begin 169 | if aclr1=reset1_high then 170 | iclk_enable <= '0'; 171 | iclk_data <= init_value_internal; 172 | elsif clk1'event and clk1='1' then 173 | iclk_enable <= ena_internal; 174 | if ena(0)='1' then 175 | iclk_data <= xin; 176 | end if; 177 | end if; 178 | end process; 179 | 180 | sync_reg_loop: for i in 0 to depth-1 generate 181 | process (clk2, aclr2) 182 | begin 183 | if aclr2=reset2_high then 184 | sync_regs(i) <= '0'; 185 | elsif clk2'event and clk2='1' then 186 | if i>0 then 187 | sync_regs(i) <= sync_regs(i-1); 188 | else 189 | sync_regs(i) <= iclk_enable; 190 | end if; 191 | end if; 192 | end process; 193 | end generate; 194 | 195 | process (clk2, aclr2) 196 | begin 197 | if aclr2=reset2_high then 198 | oclk_data <= init_value_internal(width2-1 downto 0); 199 | elsif clk2'event and clk2='1' then 200 | if oclk_enable='1' then 201 | oclk_data <= iclk_data(width2-1 downto 0); 202 | end if; 203 | end if; 204 | end process; 205 | end generate; 206 | 207 | sync_reset: if reset_kind="SYNC" generate 208 | 209 | multiply_ena: if pulse_multiplier>1 generate 210 | ena_internal <= '1' when counter>0 else ena(0); 211 | process (clk1) 212 | begin 213 | if clk1'event and clk1='1' then 214 | if aclr1=reset1_high then 215 | counter <= (others => '0'); 216 | else 217 | if counter>0 then 218 | if counter=pulse_multiplier-1 then 219 | counter <= (others => '0'); 220 | else 221 | counter <= counter + TO_UNSIGNED(1, counter_width); 222 | end if; 223 | else 224 | if ena(0)='1' then 225 | counter <= TO_UNSIGNED(1, counter_width); 226 | end if; 227 | end if; 228 | end if; 229 | end if; 230 | end process; 231 | end generate; 232 | 233 | process (clk1) 234 | begin 235 | if clk1'event and clk1='1' then 236 | if aclr1=reset1_high then 237 | iclk_enable <= '0'; 238 | iclk_data <= init_value_internal; 239 | else 240 | iclk_enable <= ena_internal; 241 | if ena(0)='1' then 242 | iclk_data <= xin; 243 | end if; 244 | end if; 245 | end if; 246 | end process; 247 | 248 | sync_reg_loop: for i in 0 to depth-1 generate 249 | process (clk2) 250 | begin 251 | if clk2'event and clk2='1' then 252 | if aclr2=reset2_high then 253 | sync_regs(i) <= '0'; 254 | else 255 | if i>0 then 256 | sync_regs(i) <= sync_regs(i-1); 257 | else 258 | sync_regs(i) <= iclk_enable; 259 | end if; 260 | end if; 261 | end if; 262 | end process; 263 | end generate; 264 | 265 | process (clk2) 266 | begin 267 | if clk2'event and clk2='1' then 268 | if aclr2=reset2_high then 269 | oclk_data <= init_value_internal(width2-1 downto 0); 270 | elsif oclk_enable='1' then 271 | oclk_data <= iclk_data(width2-1 downto 0); 272 | end if; 273 | end if; 274 | end process; 275 | end generate; 276 | 277 | none_reset: if reset_kind="NONE" generate 278 | 279 | multiply_ena: if pulse_multiplier>1 generate 280 | ena_internal <= '1' when counter>0 else ena(0); 281 | process (clk1, aclr1) 282 | begin 283 | if clk1'event and clk1='1' then 284 | if counter>0 then 285 | if counter=pulse_multiplier-1 then 286 | counter <= (others => '0'); 287 | else 288 | counter <= counter + TO_UNSIGNED(1, counter_width); 289 | end if; 290 | else 291 | if ena(0)='1' then 292 | counter <= TO_UNSIGNED(1, counter_width); 293 | end if; 294 | end if; 295 | end if; 296 | end process; 297 | end generate; 298 | 299 | process (clk1) 300 | begin 301 | if clk1'event and clk1='1' then 302 | iclk_enable <= ena_internal; 303 | if ena(0)='1' then 304 | iclk_data <= xin; 305 | end if; 306 | end if; 307 | end process; 308 | 309 | sync_reg_loop: for i in 0 to depth-1 generate 310 | process (clk2) 311 | begin 312 | if clk2'event and clk2='1' then 313 | if i>0 then 314 | sync_regs(i) <= sync_regs(i-1); 315 | else 316 | sync_regs(i) <= iclk_enable; 317 | end if; 318 | end if; 319 | end process; 320 | end generate; 321 | 322 | process (clk2) 323 | begin 324 | if clk2'event and clk2='1' then 325 | if oclk_enable='1' then 326 | oclk_data <= iclk_data(width2-1 downto 0); 327 | end if; 328 | end if; 329 | end process; 330 | end generate; 331 | 332 | xout <= iclk_data; 333 | sxout <= oclk_data; 334 | 335 | end sync_reg; 336 | 337 | -------------------------------------------------------------------------------- 338 | 339 | library ieee; 340 | use ieee.std_logic_1164.all; 341 | use ieee.numeric_std.all; 342 | 343 | entity dspba_pipe is 344 | generic( 345 | num_bits : positive := 8; 346 | num_stages : natural := 0; 347 | init_value : std_logic := 'X' 348 | ); 349 | port( 350 | clk: in std_logic; 351 | d : in std_logic_vector(num_bits-1 downto 0); 352 | q : out std_logic_vector(num_bits-1 downto 0) 353 | ); 354 | end entity dspba_pipe; 355 | 356 | architecture rtl of dspba_pipe is 357 | attribute altera_attribute : string; 358 | attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; 359 | 360 | type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0); 361 | signal stage_array : stage_array_type := (others => (others => init_value)); 362 | begin 363 | stage_array(0) <= d; 364 | 365 | g_pipe : for i in 1 to num_stages generate 366 | p_stage : process (clk) is 367 | begin 368 | if rising_edge(clk) then 369 | stage_array(i) <= stage_array(i-1); 370 | end if; 371 | end process p_stage; 372 | end generate g_pipe; 373 | 374 | q <= stage_array(num_stages); 375 | 376 | end rtl; 377 | 378 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_add/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_mul.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "fp_mul" -name MISC_FILE [file join $::quartus(qip_path) "fp_mul.cmp"] 5 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" 6 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 7 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_NAME "ZnBfbXVs" 10 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 11 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 14 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_VERSION "MTcuMQ==" 15 | set_global_assignment -entity "fp_mul" -library "fp_mul" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 16 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_NAME "ZnBfbXVsXzAwMDI=" 17 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0ZVTkNUSU9OUw==" 18 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 19 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_INTERNAL "Off" 20 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 21 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_VERSION "MTcuMQ==" 22 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_DESCRIPTION "QSBjb2xsZWN0aW9uIG9mIGZsb2F0aW5nIHBvaW50IGZ1bmN0aW9ucw==" 23 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "RlVOQ1RJT05fRkFNSUxZ::QVJJVEg=::RmFtaWx5" 24 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "QVJJVEhfZnVuY3Rpb24=::TVVM::TmFtZQ==" 25 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "Q09OVkVSVF9mdW5jdGlvbg==::RlhQX0ZQ::TmFtZQ==" 26 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "QUxMX2Z1bmN0aW9u::QURE::TmFtZQ==" 27 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "RVhQX0xPR19mdW5jdGlvbg==::RVhQRQ==::TmFtZQ==" 28 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "VFJJR19mdW5jdGlvbg==::U0lO::TmFtZQ==" 29 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "Q09NUEFSRV9mdW5jdGlvbg==::TUlO::TmFtZQ==" 30 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "Uk9PVFNfZnVuY3Rpb24=::U1FSVA==::TmFtZQ==" 31 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZGZ1bmN0aW9u::TVVM::ZGVyaXZlZGZ1bmN0aW9u" 32 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::Rm9ybWF0" 33 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhw::OA==::RXhwb25lbnQ=" 34 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfZXhwX2Rlcml2ZWQ=::OA==::ZnBfZXhwX2Rlcml2ZWQ=" 35 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFu::MjM=::TWFudGlzc2E=" 36 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfbWFuX2Rlcml2ZWQ=::MjM=::ZnBfbWFuX2Rlcml2ZWQ=" 37 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZXhwb25lbnRfd2lkdGg=::MjM=::RXhwb25lbnQgV2lkdGg=" 38 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X3RhcmdldA==::MTAw::VGFyZ2V0" 39 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV90YXJnZXQ=::NA==::VGFyZ2V0" 40 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "cGVyZm9ybWFuY2VfZ29hbA==::Y29tYmluZWQ=::R29hbA==" 41 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZQ==::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyBhd2F5IGZyb20gemVybw==::TW9kZQ==" 42 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "cm91bmRpbmdfbW9kZV9kZXJpdmVk::bmVhcmVzdCB3aXRoIHRpZSBicmVha2luZyB0byBldmVu::TW9kZQ==" 43 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "dXNlX3JvdW5kaW5nX21vZGU=::dHJ1ZQ==::dXNlX3JvdW5kaW5nX21vZGU=" 44 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZmFpdGhmdWxfcm91bmRpbmc=::ZmFsc2U=::UmVsYXggcm91bmRpbmcgdG8gcm91bmQgdXAgb3IgZG93biB0byByZWR1Y2UgcmVzb3VyY2UgdXNhZ2U=" 45 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::ZmFsc2U=::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" 46 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZGl2aWRlX3R5cGU=::MA==::TWV0aG9k" 47 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0X3NpZ25hbF9lbmFibGU=::ZmFsc2U=::VXNlIFNlbGVjdCBTaWduYWw=" 48 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "c2NhbGVfYnlfcGk=::ZmFsc2U=::UmVwcmVzZW50IGFuZ2xlIGFzIG11bHRpcGxlIG9mIFBp" 49 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2lucHV0cw==::Mg==::SW5wdXQgVmVjdG9yIERpbWVuc2lvbg==" 50 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "dHJpZ19ub19yYW5nZV9yZWR1Y3Rpb24=::ZmFsc2U=::SW5wdXRzIGFyZSB3aXRoaW4gcmFuZ2UgLTJwaSB0byArMnBp" 51 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "cmVwb3J0X3Jlc291cmNlc190b194bWw=::ZmFsc2U=::cmVwb3J0X3Jlc291cmNlc190b194bWw=" 52 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF93aWR0aA==::MzI=::V2lkdGg=" 53 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9mcmFjdGlvbg==::MA==::RnJhY3Rpb24=" 54 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnhwdF9zaWdu::MQ==::U2lnbg==" 55 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5X2ZlZWRiYWNr::MA==::ZnJlcXVlbmN5X2ZlZWRiYWNr" 56 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "bGF0ZW5jeV9mZWVkYmFjaw==::NA==::bGF0ZW5jeV9mZWVkYmFjaw==" 57 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VfZWxhYm9yYXRl::MA==::Zm9yY2VfZWxhYm9yYXRl" 58 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2Zvcm1hdA==::c2luZ2xl::T3V0cHV0IEZvcm1hdA==" 59 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cA==::OA==::T3V0cHV0IEV4cG9uZW50" 60 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X2V4cF9kZXJpdmVk::OA==::ZnBfb3V0X2V4cF9kZXJpdmVk" 61 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbg==::MjM=::T3V0cHV0IE1hbnRpc3Nh" 62 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfb3V0X21hbl9kZXJpdmVk::OA==::ZnBfb3V0X21hbl9kZXJpdmVk" 63 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZm9ybWF0::c2luZ2xl::SW5wdXQgRm9ybWF0" 64 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhw::OA==::SW5wdXQgRXhwb25lbnQ=" 65 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fZXhwX2Rlcml2ZWQ=::OA==::ZnBfaW5fZXhwX2Rlcml2ZWQ=" 66 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFu::MjM=::SW5wdXQgTWFudGlzc2E=" 67 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZnBfaW5fbWFuX2Rlcml2ZWQ=::OA==::ZnBfaW5fbWFuX2Rlcml2ZWQ=" 68 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX2hhcmRfZnA=::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 69 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "bWFudWFsX2RzcF9wbGFubmluZw==::dHJ1ZQ==::RW5hYmxlIEhhcmQgRmxvYXRpbmcgUG9pbnQ=" 70 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "Zm9yY2VSZWdpc3RlcnM=::MTExMQ==::Zm9yY2VSZWdpc3RlcnM=" 71 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0RTUF9wYXJhbQ==::Mg==::TXVsdGlwbGllcw==" 72 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX0xVVF9wYXJhbQ==::MjE5::TFVUcw==" 73 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CSVRfcGFyYW0=::MA==::TWVtb3J5IEJpdHM=" 74 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "UkVTX01CTE9DS19wYXJhbQ==::MA==::TWVtb3J5IEJsb2Nrcw==" 75 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" 76 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Nw==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=" 77 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ=" 78 | 79 | set_global_assignment -library "fp_mul" -name VERILOG_FILE [file join $::quartus(qip_path) "fp_mul.v"] 80 | set_global_assignment -library "fp_mul" -name VHDL_FILE [file join $::quartus(qip_path) "fp_mul/dspba_library_package.vhd"] 81 | set_global_assignment -library "fp_mul" -name VHDL_FILE [file join $::quartus(qip_path) "fp_mul/dspba_library.vhd"] 82 | set_global_assignment -library "fp_mul" -name VHDL_FILE [file join $::quartus(qip_path) "fp_mul/fp_mul_0002.vhd"] 83 | 84 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_TOOL_NAME "altera_fp_functions" 85 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_TOOL_VERSION "17.1" 86 | set_global_assignment -entity "fp_mul_0002" -library "fp_mul" -name IP_TOOL_ENV "mwpim" 87 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_mul.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fp_mul" -library "lib_fp_mul" -name IP_TOOL_NAME "altera_fp_functions" 2 | set_global_assignment -entity "fp_mul" -library "lib_fp_mul" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "fp_mul" -library "lib_fp_mul" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_fp_mul" -name SPD_FILE [file join $::quartus(sip_path) "fp_mul.spd"] 5 | 6 | set_global_assignment -library "lib_fp_mul" -name MISC_FILE [file join $::quartus(sip_path) "fp_mul_sim/fp_mul.vo"] 7 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_mul.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTERA_FP_FUNCTIONS v17.1% 2 | // GENERATION: XML 3 | // fp_mul.v 4 | 5 | // Generated using ACDS version 17.1 590 6 | 7 | `timescale 1 ps / 1 ps 8 | module fp_mul ( 9 | input wire clk, // clk.clk 10 | input wire areset, // areset.reset 11 | input wire [31:0] a, // a.a 12 | input wire [31:0] b, // b.b 13 | output wire [31:0] q // q.q 14 | ); 15 | 16 | fp_mul_0002 fp_mul_inst ( 17 | .clk (clk), // clk.clk 18 | .areset (areset), // areset.reset 19 | .a (a), // a.a 20 | .b (b), // b.b 21 | .q (q) // q.q 22 | ); 23 | 24 | endmodule 25 | // Retrieval info: 26 | // 51 | // Retrieval info: 52 | // Retrieval info: 53 | // Retrieval info: 54 | // Retrieval info: 55 | // Retrieval info: 56 | // Retrieval info: 57 | // Retrieval info: 58 | // Retrieval info: 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // Retrieval info: 70 | // Retrieval info: 71 | // Retrieval info: 72 | // Retrieval info: 73 | // Retrieval info: 74 | // Retrieval info: 75 | // Retrieval info: 76 | // Retrieval info: 77 | // Retrieval info: 78 | // Retrieval info: 79 | // Retrieval info: 80 | // Retrieval info: 81 | // Retrieval info: 82 | // Retrieval info: 83 | // Retrieval info: 84 | // Retrieval info: 85 | // Retrieval info: 86 | // Retrieval info: 87 | // Retrieval info: 88 | // Retrieval info: 89 | // Retrieval info: 90 | // Retrieval info: 91 | // IPFS_FILES : fp_mul.vo 92 | // RELATED_FILES: fp_mul.v, dspba_library_package.vhd, dspba_library.vhd, fp_mul_0002.vhd 93 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_mul/dspba_library.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | use work.dspba_library_package.all; 17 | 18 | entity dspba_delay is 19 | generic ( 20 | width : natural := 8; 21 | depth : natural := 1; 22 | reset_high : std_logic := '1'; 23 | reset_kind : string := "ASYNC" 24 | ); 25 | port ( 26 | clk : in std_logic; 27 | aclr : in std_logic; 28 | ena : in std_logic := '1'; 29 | xin : in std_logic_vector(width-1 downto 0); 30 | xout : out std_logic_vector(width-1 downto 0) 31 | ); 32 | end dspba_delay; 33 | 34 | architecture delay of dspba_delay is 35 | type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0); 36 | signal delay_signals : delay_array; 37 | begin 38 | delay_signals(depth) <= xin; 39 | 40 | delay_block: if 0 < depth generate 41 | begin 42 | delay_loop: for i in depth-1 downto 0 generate 43 | begin 44 | async_reset: if reset_kind = "ASYNC" generate 45 | process(clk, aclr) 46 | begin 47 | if aclr=reset_high then 48 | delay_signals(i) <= (others => '0'); 49 | elsif clk'event and clk='1' then 50 | if ena='1' then 51 | delay_signals(i) <= delay_signals(i + 1); 52 | end if; 53 | end if; 54 | end process; 55 | end generate; 56 | 57 | sync_reset: if reset_kind = "SYNC" generate 58 | process(clk) 59 | begin 60 | if clk'event and clk='1' then 61 | if aclr=reset_high then 62 | delay_signals(i) <= (others => '0'); 63 | elsif ena='1' then 64 | delay_signals(i) <= delay_signals(i + 1); 65 | end if; 66 | end if; 67 | end process; 68 | end generate; 69 | 70 | no_reset: if reset_kind = "NONE" generate 71 | process(clk) 72 | begin 73 | if clk'event and clk='1' then 74 | if ena='1' then 75 | delay_signals(i) <= delay_signals(i + 1); 76 | end if; 77 | end if; 78 | end process; 79 | end generate; 80 | end generate; 81 | end generate; 82 | 83 | xout <= delay_signals(0); 84 | end delay; 85 | 86 | -------------------------------------------------------------------------------- 87 | 88 | library IEEE; 89 | use IEEE.std_logic_1164.all; 90 | use IEEE.NUMERIC_STD.all; 91 | use work.dspba_library_package.all; 92 | 93 | entity dspba_sync_reg is 94 | generic ( 95 | width1 : natural := 8; 96 | init_value : std_logic_vector; 97 | width2 : natural := 8; 98 | depth : natural := 2; 99 | pulse_multiplier : natural := 1; 100 | counter_width : natural := 8; 101 | reset1_high : std_logic := '1'; 102 | reset2_high : std_logic := '1'; 103 | reset_kind : string := "ASYNC" 104 | ); 105 | port ( 106 | clk1 : in std_logic; 107 | aclr1 : in std_logic; 108 | ena : in std_logic_vector(0 downto 0); 109 | xin : in std_logic_vector(width1-1 downto 0); 110 | xout : out std_logic_vector(width1-1 downto 0); 111 | clk2 : in std_logic; 112 | aclr2 : in std_logic; 113 | sxout : out std_logic_vector(width2-1 downto 0) 114 | ); 115 | end entity; 116 | 117 | architecture sync_reg of dspba_sync_reg is 118 | type bit_array is array (depth-1 downto 0) of std_logic; 119 | 120 | signal iclk_enable : std_logic; 121 | signal iclk_data : std_logic_vector(width1-1 downto 0); 122 | signal oclk_data : std_logic_vector(width2-1 downto 0); 123 | 124 | -- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops 125 | -- For TimeQuest this means: identify these flip-flops as synchronizer to enable automatic MTBF analysis 126 | signal sync_regs : bit_array; 127 | attribute altera_attribute : string; 128 | attribute altera_attribute of sync_regs : signal is "-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"; 129 | 130 | signal oclk_enable : std_logic; 131 | 132 | constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value; 133 | 134 | signal counter : UNSIGNED(counter_width-1 downto 0); 135 | signal ena_internal : std_logic; 136 | begin 137 | oclk_enable <= sync_regs(depth-1); 138 | 139 | no_multiplication: if pulse_multiplier=1 generate 140 | ena_internal <= ena(0); 141 | end generate; 142 | 143 | async_reset: if reset_kind="ASYNC" generate 144 | 145 | multiply_ena: if pulse_multiplier>1 generate 146 | ena_internal <= '1' when counter>0 else ena(0); 147 | process (clk1, aclr1) 148 | begin 149 | if aclr1=reset1_high then 150 | counter <= (others => '0'); 151 | elsif clk1'event and clk1='1' then 152 | if counter>0 then 153 | if counter=pulse_multiplier-1 then 154 | counter <= (others => '0'); 155 | else 156 | counter <= counter + TO_UNSIGNED(1, counter_width); 157 | end if; 158 | else 159 | if ena(0)='1' then 160 | counter <= TO_UNSIGNED(1, counter_width); 161 | end if; 162 | end if; 163 | end if; 164 | end process; 165 | end generate; 166 | 167 | process (clk1, aclr1) 168 | begin 169 | if aclr1=reset1_high then 170 | iclk_enable <= '0'; 171 | iclk_data <= init_value_internal; 172 | elsif clk1'event and clk1='1' then 173 | iclk_enable <= ena_internal; 174 | if ena(0)='1' then 175 | iclk_data <= xin; 176 | end if; 177 | end if; 178 | end process; 179 | 180 | sync_reg_loop: for i in 0 to depth-1 generate 181 | process (clk2, aclr2) 182 | begin 183 | if aclr2=reset2_high then 184 | sync_regs(i) <= '0'; 185 | elsif clk2'event and clk2='1' then 186 | if i>0 then 187 | sync_regs(i) <= sync_regs(i-1); 188 | else 189 | sync_regs(i) <= iclk_enable; 190 | end if; 191 | end if; 192 | end process; 193 | end generate; 194 | 195 | process (clk2, aclr2) 196 | begin 197 | if aclr2=reset2_high then 198 | oclk_data <= init_value_internal(width2-1 downto 0); 199 | elsif clk2'event and clk2='1' then 200 | if oclk_enable='1' then 201 | oclk_data <= iclk_data(width2-1 downto 0); 202 | end if; 203 | end if; 204 | end process; 205 | end generate; 206 | 207 | sync_reset: if reset_kind="SYNC" generate 208 | 209 | multiply_ena: if pulse_multiplier>1 generate 210 | ena_internal <= '1' when counter>0 else ena(0); 211 | process (clk1) 212 | begin 213 | if clk1'event and clk1='1' then 214 | if aclr1=reset1_high then 215 | counter <= (others => '0'); 216 | else 217 | if counter>0 then 218 | if counter=pulse_multiplier-1 then 219 | counter <= (others => '0'); 220 | else 221 | counter <= counter + TO_UNSIGNED(1, counter_width); 222 | end if; 223 | else 224 | if ena(0)='1' then 225 | counter <= TO_UNSIGNED(1, counter_width); 226 | end if; 227 | end if; 228 | end if; 229 | end if; 230 | end process; 231 | end generate; 232 | 233 | process (clk1) 234 | begin 235 | if clk1'event and clk1='1' then 236 | if aclr1=reset1_high then 237 | iclk_enable <= '0'; 238 | iclk_data <= init_value_internal; 239 | else 240 | iclk_enable <= ena_internal; 241 | if ena(0)='1' then 242 | iclk_data <= xin; 243 | end if; 244 | end if; 245 | end if; 246 | end process; 247 | 248 | sync_reg_loop: for i in 0 to depth-1 generate 249 | process (clk2) 250 | begin 251 | if clk2'event and clk2='1' then 252 | if aclr2=reset2_high then 253 | sync_regs(i) <= '0'; 254 | else 255 | if i>0 then 256 | sync_regs(i) <= sync_regs(i-1); 257 | else 258 | sync_regs(i) <= iclk_enable; 259 | end if; 260 | end if; 261 | end if; 262 | end process; 263 | end generate; 264 | 265 | process (clk2) 266 | begin 267 | if clk2'event and clk2='1' then 268 | if aclr2=reset2_high then 269 | oclk_data <= init_value_internal(width2-1 downto 0); 270 | elsif oclk_enable='1' then 271 | oclk_data <= iclk_data(width2-1 downto 0); 272 | end if; 273 | end if; 274 | end process; 275 | end generate; 276 | 277 | none_reset: if reset_kind="NONE" generate 278 | 279 | multiply_ena: if pulse_multiplier>1 generate 280 | ena_internal <= '1' when counter>0 else ena(0); 281 | process (clk1, aclr1) 282 | begin 283 | if clk1'event and clk1='1' then 284 | if counter>0 then 285 | if counter=pulse_multiplier-1 then 286 | counter <= (others => '0'); 287 | else 288 | counter <= counter + TO_UNSIGNED(1, counter_width); 289 | end if; 290 | else 291 | if ena(0)='1' then 292 | counter <= TO_UNSIGNED(1, counter_width); 293 | end if; 294 | end if; 295 | end if; 296 | end process; 297 | end generate; 298 | 299 | process (clk1) 300 | begin 301 | if clk1'event and clk1='1' then 302 | iclk_enable <= ena_internal; 303 | if ena(0)='1' then 304 | iclk_data <= xin; 305 | end if; 306 | end if; 307 | end process; 308 | 309 | sync_reg_loop: for i in 0 to depth-1 generate 310 | process (clk2) 311 | begin 312 | if clk2'event and clk2='1' then 313 | if i>0 then 314 | sync_regs(i) <= sync_regs(i-1); 315 | else 316 | sync_regs(i) <= iclk_enable; 317 | end if; 318 | end if; 319 | end process; 320 | end generate; 321 | 322 | process (clk2) 323 | begin 324 | if clk2'event and clk2='1' then 325 | if oclk_enable='1' then 326 | oclk_data <= iclk_data(width2-1 downto 0); 327 | end if; 328 | end if; 329 | end process; 330 | end generate; 331 | 332 | xout <= iclk_data; 333 | sxout <= oclk_data; 334 | 335 | end sync_reg; 336 | 337 | -------------------------------------------------------------------------------- 338 | 339 | library ieee; 340 | use ieee.std_logic_1164.all; 341 | use ieee.numeric_std.all; 342 | 343 | entity dspba_pipe is 344 | generic( 345 | num_bits : positive := 8; 346 | num_stages : natural := 0; 347 | init_value : std_logic := 'X' 348 | ); 349 | port( 350 | clk: in std_logic; 351 | d : in std_logic_vector(num_bits-1 downto 0); 352 | q : out std_logic_vector(num_bits-1 downto 0) 353 | ); 354 | end entity dspba_pipe; 355 | 356 | architecture rtl of dspba_pipe is 357 | attribute altera_attribute : string; 358 | attribute altera_attribute of rtl : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION off"; 359 | 360 | type stage_array_type is array(0 to num_stages) of std_logic_vector(num_bits-1 downto 0); 361 | signal stage_array : stage_array_type := (others => (others => init_value)); 362 | begin 363 | stage_array(0) <= d; 364 | 365 | g_pipe : for i in 1 to num_stages generate 366 | p_stage : process (clk) is 367 | begin 368 | if rising_edge(clk) then 369 | stage_array(i) <= stage_array(i-1); 370 | end if; 371 | end process p_stage; 372 | end generate g_pipe; 373 | 374 | q <= stage_array(num_stages); 375 | 376 | end rtl; 377 | 378 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/8.calc_unit/ip_core/fp_mul/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/frame.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eda-lab/CNNAF-CNN-Accelerator_init/ef2e88475fc051f0eb402d12f4f01e69c597aa67/CNNAF_mobilenetv2/frame.png -------------------------------------------------------------------------------- /CNNAF_mobilenetv2/readme.md: -------------------------------------------------------------------------------- 1 | CNN Accelerator based on FPGA 2 | === 3 | This folder contains the Verilog HDL code for MobileNetV2 on FPGA. 4 | ## Model 5 | The reference model is mobilenet_v2_1.0_128, refer more information on [MobileNet](https://github.com/tensorflow/models/tree/master/research/slim/nets/mobilenet). 6 | ## Framework 7 | This is the framework of our accelerator. 8 | ![](https://github.com/eda-lab/CNNAF-CNN-Accelerator/raw/master/mobilenetv2/frame.png) 9 | ## Platform 10 | Hardware platform is C5P FPGA of Terasic, Cyclone V 5CGXFC9D6F27C7.
11 | IP version is based on quartus17.1. 12 | ## Other information 13 | The shortcut module and top level module are still in building. 14 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 eda-lab 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # CNNAG-CNN-Accelerator 2 | Recent work on CNN accelerator based on FPGA. 3 | ## Model list 4 | [MobileNetV2](mobilenetv2) 5 | --------------------------------------------------------------------------------