├── Description ├── SFU_13 │ ├── SFU │ │ ├── RRO │ │ │ ├── Components │ │ │ │ ├── add_sub.vhd.bak │ │ │ │ ├── right_shifter.vhd │ │ │ │ ├── right_shifter.vhd.bak │ │ │ │ └── fp_leading_zeros_and_shift.vhd │ │ │ └── RRO_trig.vhd │ │ ├── fused_accm_tree │ │ │ ├── CSA_4_2.vhd │ │ │ └── Booth_PP.vhd │ │ ├── voter │ │ │ └── voter.vhd │ │ ├── sfu_tb_2.vhd │ │ └── Quadratic_Interpolator │ │ │ └── Single_LUTS │ │ │ ├── LUT_C2_sqrt_1_2.vhd │ │ │ ├── LUT_C2_sqrt_2_4.vhd │ │ │ ├── LUT_C2_cos.vhd │ │ │ ├── LUT_C2_exp.vhd │ │ │ ├── LUT_C2_sin.vhd │ │ │ ├── LUT_C2_ln2e0.vhd │ │ │ ├── LUT_C1_sqrt_1_2.vhd │ │ │ ├── LUT_C1_sqrt_2_4.vhd │ │ │ ├── LUT_C1_cos.vhd │ │ │ ├── LUT_C1_ln2e0.vhd │ │ │ ├── LUT_C1_exp.vhd │ │ │ └── LUT_C1_sin.vhd │ └── Verification │ │ ├── 4_view_waveform_modelsim.py │ │ ├── 1_launch_modelsim_simulation.py │ │ ├── wave.do │ │ └── 2_Generate_input_data.py ├── SFU_00 │ ├── Verification │ │ ├── 4_view_waveform_modelsim.py │ │ ├── 1_launch_modelsim_simulation.py │ │ ├── wave.do │ │ └── 2_Generate_input_data.py │ └── SFU │ │ ├── fused_accm_tree │ │ ├── CSA_4_2.vhd │ │ └── Booth_PP.vhd │ │ ├── sfu_tb_2.vhd │ │ ├── Quadratic_Interpolator │ │ └── Single_LUTS │ │ │ ├── LUT_C2_sqrt_1_2.vhd │ │ │ ├── LUT_C2_ln2e0.vhd │ │ │ ├── LUT_C2_sqrt_2_4.vhd │ │ │ ├── LUT_C2_exp.vhd │ │ │ ├── LUT_C2_cos.vhd │ │ │ ├── LUT_C2_sin.vhd │ │ │ ├── LUT_C1_sqrt_1_2.vhd │ │ │ ├── LUT_C1_sqrt_2_4.vhd │ │ │ ├── LUT_C1_ln2e0.vhd │ │ │ ├── LUT_C1_exp.vhd │ │ │ ├── LUT_C1_cos.vhd │ │ │ ├── LUT_C1_sin.vhd │ │ │ ├── LUT_C0_sqrt_1_2.vhd │ │ │ ├── LUT_C0_exp.vhd │ │ │ ├── LUT_C0_ln2e0.vhd │ │ │ └── LUT_C0_sqrt_2_4.vhd │ │ └── RRO │ │ ├── Components │ │ ├── right_shifter.vhd │ │ └── fp_leading_zeros_and_shift.vhd │ │ └── RRO_trig.vhd ├── SFU_11 │ ├── Verification │ │ ├── 4_view_waveform_modelsim.py │ │ ├── 1_launch_modelsim_simulation.py │ │ ├── wave.do │ │ └── 2_Generate_input_data.py │ └── SFU │ │ ├── fused_accm_tree │ │ ├── CSA_4_2.vhd │ │ └── Booth_PP.vhd │ │ ├── voter │ │ └── voter.vhd │ │ ├── sfu_tb_2.vhd │ │ ├── Quadratic_Interpolator │ │ └── Single_LUTS │ │ │ ├── LUT_C2_sqrt_1_2.vhd │ │ │ ├── LUT_C2_sqrt_2_4.vhd │ │ │ ├── LUT_C2_cos.vhd │ │ │ ├── LUT_C2_exp.vhd │ │ │ ├── LUT_C2_sin.vhd │ │ │ ├── LUT_C2_ln2e0.vhd │ │ │ ├── LUT_C1_sqrt_1_2.vhd │ │ │ ├── LUT_C1_sqrt_2_4.vhd │ │ │ ├── LUT_C1_cos.vhd │ │ │ ├── LUT_C1_ln2e0.vhd │ │ │ ├── LUT_C1_exp.vhd │ │ │ ├── LUT_C1_sin.vhd │ │ │ └── LUT_C0_ln2e0.vhd │ │ ├── sfu.vhd │ │ └── RRO │ │ ├── Components │ │ ├── right_shifter.vhd │ │ └── fp_leading_zeros_and_shift.vhd │ │ └── RRO_trig.vhd └── SFU_12 │ ├── Verification │ ├── 4_view_waveform_modelsim.py │ ├── 1_launch_modelsim_simulation.py │ ├── wave.do │ └── 2_Generate_input_data.py │ └── SFU │ ├── fused_accm_tree │ ├── CSA_4_2.vhd │ └── Booth_PP.vhd │ ├── voter │ └── voter.vhd │ ├── sfu_tb_2.vhd │ ├── Quadratic_Interpolator │ └── Single_LUTS │ │ ├── LUT_C2_sqrt_1_2.vhd │ │ ├── LUT_C2_sqrt_2_4.vhd │ │ ├── LUT_C2_cos.vhd │ │ ├── LUT_C2_exp.vhd │ │ ├── LUT_C2_sin.vhd │ │ ├── LUT_C2_ln2e0.vhd │ │ ├── LUT_C1_sqrt_1_2.vhd │ │ ├── LUT_C1_sqrt_2_4.vhd │ │ ├── LUT_C1_cos.vhd │ │ ├── LUT_C1_ln2e0.vhd │ │ ├── LUT_C1_exp.vhd │ │ ├── LUT_C1_sin.vhd │ │ └── LUT_C0_ln2e0.vhd │ └── RRO │ ├── Components │ ├── right_shifter.vhd │ └── fp_leading_zeros_and_shift.vhd │ └── RRO_trig.vhd ├── Golden model ├── coeffint.m ├── compare_vector.m ├── hex754_2dec.m ├── coeffbin.m ├── dec2spfp.m ├── coeffbinint.m ├── bin2dec.m ├── dec2bin.m ├── dec2bin754.m ├── hex2bin.m ├── binaryVectorToHex.m ├── loadLUTs.m ├── getLUT.m └── dec2hex754.m └── Implementación y evaluación de una unidad de funciones especiales tolerante a fallas basada en aproximación polinomial por partes.pdf /Description/SFU_13/SFU/RRO/Components/add_sub.vhd.bak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/edwar-vhd/SFU-Piecewise-Polynomial-Approximation/HEAD/Description/SFU_13/SFU/RRO/Components/add_sub.vhd.bak -------------------------------------------------------------------------------- /Golden model/coeffint.m: -------------------------------------------------------------------------------- 1 | function [C0i,C1i,C2i] = coeffint(C0d,C1d,C2d,t,p,q) 2 | C0i = floor(C0d*(2^t)); 3 | 4 | C1i = floor(C1d*(2^(p))); 5 | 6 | C2i = floor(C2d*(2^(q))); 7 | end -------------------------------------------------------------------------------- /Golden model/compare_vector.m: -------------------------------------------------------------------------------- 1 | function [o] = compare_vector(x,y) 2 | o=1; 3 | for i=1:size(x,2) 4 | if (x(i)!=y(i)) 5 | o=0; 6 | break 7 | endif 8 | endfor 9 | end 10 | -------------------------------------------------------------------------------- /Implementación y evaluación de una unidad de funciones especiales tolerante a fallas basada en aproximación polinomial por partes.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/edwar-vhd/SFU-Piecewise-Polynomial-Approximation/HEAD/Implementación y evaluación de una unidad de funciones especiales tolerante a fallas basada en aproximación polinomial por partes.pdf -------------------------------------------------------------------------------- /Golden model/hex754_2dec.m: -------------------------------------------------------------------------------- 1 | function y = hex754_2dec(x) 2 | %x='3863F107'; 3 | number = char(hex2bin(x)); 4 | 5 | % The sign 6 | sign = [1 -1]; 7 | s = number(1); 8 | 9 | exp = bin2dec(strcat(number(2:9),'.0'))-127; 10 | man = bin2dec(strcat('1.',number(10:end))); 11 | 12 | y = (man*2^exp)*sign(str2double(s)+1); 13 | end -------------------------------------------------------------------------------- /Description/SFU_00/Verification/4_view_waveform_modelsim.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -view "+File_path+"/vsim.wlf -do wave.do" 10 | print(command) 11 | os.system(command) 12 | -------------------------------------------------------------------------------- /Description/SFU_11/Verification/4_view_waveform_modelsim.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -view "+File_path+"/vsim.wlf -do wave.do" 10 | print(command) 11 | os.system(command) 12 | -------------------------------------------------------------------------------- /Description/SFU_12/Verification/4_view_waveform_modelsim.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -view "+File_path+"/vsim.wlf -do wave.do" 10 | print(command) 11 | os.system(command) 12 | -------------------------------------------------------------------------------- /Description/SFU_13/Verification/4_view_waveform_modelsim.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -view "+File_path+"/vsim.wlf -do wave.do" 10 | print(command) 11 | os.system(command) 12 | -------------------------------------------------------------------------------- /Golden model/coeffbin.m: -------------------------------------------------------------------------------- 1 | function [C0b,C1b,C2b] = coeffbin(C0d,C1d,C2d,t,p,q,m) 2 | C0b = char(zeros(2^m,t+2)); 3 | for i=1:size(C0d,1) 4 | C0b(i,:) = (dec2bin(abs(C0d(i)),t)); 5 | end 6 | 7 | C1b = char(zeros(2^m,p+2)); 8 | for i=1:size(C1d,1) 9 | C1b(i,:) = (dec2bin(abs(C1d(i)),p)); 10 | end 11 | 12 | C2b = char(zeros(2^m,q+2)); 13 | for i=1:size(C2d,1) 14 | C2b(i,:) = (dec2bin(abs(C2d(i)),q)); 15 | end 16 | end -------------------------------------------------------------------------------- /Golden model/dec2spfp.m: -------------------------------------------------------------------------------- 1 | % IEEE 754 single-precision floating-point 2 | 3 | function [s,e,m] = dec2spfp(x) 4 | 5 | if x == 0 6 | s = 0; 7 | e = char(zeros(1,8)+48); 8 | m = char(zeros(1,23)+48); 9 | else 10 | % Sign bit 11 | if x > 0 12 | s = 0; 13 | else 14 | s = 1; 15 | x=-x; 16 | end 17 | 18 | % Exponent 19 | e = bin(fi((floor(log2(x))+127),0,8,0)); 20 | 21 | % Mantissa 22 | m = bin(fi(((x/(2^(floor(log2(x)))))-1),0,23,23)); 23 | end 24 | end -------------------------------------------------------------------------------- /Golden model/coeffbinint.m: -------------------------------------------------------------------------------- 1 | function [C0b,C1b,C2b] = coeffbinint(C0i,C1i,C2i,m) 2 | aux = ceil(log2(C0i(1))); 3 | C0b = char(zeros(2^m,aux)); 4 | for i=1:size(C0i,1) 5 | C0b(i,:) = (dec2bin(abs(C0i(i)),0)); 6 | end 7 | 8 | aux = ceil(log2(abs(C1i(1)))); 9 | C1b = char(zeros(2^m,aux)); 10 | for i=1:size(C1i,1) 11 | C1b(i,:) = (dec2bin(abs(C1i(i)),0)); 12 | end 13 | 14 | aux = ceil(log2(abs(C2i(1)))); 15 | C2b = char(zeros(2^m,aux)); 16 | for i=1:size(C2i,1) 17 | C2b(i,:) = (dec2bin(abs(C2i(i)),0)); 18 | end 19 | end -------------------------------------------------------------------------------- /Description/SFU_00/Verification/1_launch_modelsim_simulation.py: -------------------------------------------------------------------------------- 1 | import os 2 | import subprocess 3 | import winsound 4 | 5 | print("Executing...\n2_Generate_input_data.py\n") 6 | os.system("2_Generate_input_data.py 1") 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -c -do "+File_path+"/testbench.tcl" 10 | print("Executing...\n"+command+"\n") 11 | os.system(command) 12 | 13 | print("Executing...\n3_Verification_results.py\n") 14 | os.system("3_Verification_results.py 1") 15 | 16 | winsound.MessageBeep() 17 | input ("Press Enter to Finish...") 18 | -------------------------------------------------------------------------------- /Description/SFU_11/Verification/1_launch_modelsim_simulation.py: -------------------------------------------------------------------------------- 1 | import os 2 | import subprocess 3 | import winsound 4 | 5 | print("Executing...\n2_Generate_input_data.py\n") 6 | os.system("2_Generate_input_data.py 1") 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -c -do "+File_path+"/testbench.tcl" 10 | print("Executing...\n"+command+"\n") 11 | os.system(command) 12 | 13 | print("Executing...\n3_Verification_results.py\n") 14 | os.system("3_Verification_results.py 1") 15 | 16 | winsound.MessageBeep() 17 | input ("Press Enter to Finish...") 18 | -------------------------------------------------------------------------------- /Description/SFU_12/Verification/1_launch_modelsim_simulation.py: -------------------------------------------------------------------------------- 1 | import os 2 | import subprocess 3 | import winsound 4 | 5 | print("Executing...\n2_Generate_input_data.py\n") 6 | os.system("2_Generate_input_data.py 1") 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -c -do "+File_path+"/testbench.tcl" 10 | print("Executing...\n"+command+"\n") 11 | os.system(command) 12 | 13 | print("Executing...\n3_Verification_results.py\n") 14 | os.system("3_Verification_results.py 1") 15 | 16 | winsound.MessageBeep() 17 | input ("Press Enter to Finish...") 18 | -------------------------------------------------------------------------------- /Description/SFU_13/Verification/1_launch_modelsim_simulation.py: -------------------------------------------------------------------------------- 1 | import os 2 | import subprocess 3 | import winsound 4 | 5 | print("Executing...\n2_Generate_input_data.py\n") 6 | os.system("2_Generate_input_data.py 1") 7 | 8 | File_path = os.getcwd() 9 | command = "C:/altera/13.0sp1/modelsim_ase/win32aloem/vsim.exe -c -do "+File_path+"/testbench.tcl" 10 | print("Executing...\n"+command+"\n") 11 | os.system(command) 12 | 13 | print("Executing...\n3_Verification_results.py\n") 14 | os.system("3_Verification_results.py 1") 15 | 16 | winsound.MessageBeep() 17 | input ("Press Enter to Finish...") 18 | -------------------------------------------------------------------------------- /Description/SFU_00/SFU/fused_accm_tree/CSA_4_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity CSA_4_2 is 6 | port( 7 | ci :in std_logic; 8 | X1 :in std_logic; 9 | X2 :in std_logic; 10 | X3 :in std_logic; 11 | X4 :in std_logic; 12 | co :out std_logic; 13 | C :out std_logic; 14 | S :out std_logic 15 | ); 16 | end entity CSA_4_2; 17 | 18 | architecture CSA_4_2_arch of CSA_4_2 is 19 | signal sxor1, sxor2, sxor3 :std_logic; 20 | begin 21 | sxor1 <= X1 xor X2; 22 | sxor2 <= X3 xor X4; 23 | sxor3 <= sxor1 xor sxor2; 24 | S <= sxor3 xor ci; 25 | co <= (X3 and X4) or (X2 and X4) or (X2 and X3); 26 | C <= ci when sxor3='1' else X1; 27 | end CSA_4_2_arch; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/fused_accm_tree/CSA_4_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity CSA_4_2 is 6 | port( 7 | ci :in std_logic; 8 | X1 :in std_logic; 9 | X2 :in std_logic; 10 | X3 :in std_logic; 11 | X4 :in std_logic; 12 | co :out std_logic; 13 | C :out std_logic; 14 | S :out std_logic 15 | ); 16 | end entity CSA_4_2; 17 | 18 | architecture CSA_4_2_arch of CSA_4_2 is 19 | signal sxor1, sxor2, sxor3 :std_logic; 20 | begin 21 | sxor1 <= X1 xor X2; 22 | sxor2 <= X3 xor X4; 23 | sxor3 <= sxor1 xor sxor2; 24 | S <= sxor3 xor ci; 25 | co <= (X3 and X4) or (X2 and X4) or (X2 and X3); 26 | C <= ci when sxor3='1' else X1; 27 | end CSA_4_2_arch; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/fused_accm_tree/CSA_4_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity CSA_4_2 is 6 | port( 7 | ci :in std_logic; 8 | X1 :in std_logic; 9 | X2 :in std_logic; 10 | X3 :in std_logic; 11 | X4 :in std_logic; 12 | co :out std_logic; 13 | C :out std_logic; 14 | S :out std_logic 15 | ); 16 | end entity CSA_4_2; 17 | 18 | architecture CSA_4_2_arch of CSA_4_2 is 19 | signal sxor1, sxor2, sxor3 :std_logic; 20 | begin 21 | sxor1 <= X1 xor X2; 22 | sxor2 <= X3 xor X4; 23 | sxor3 <= sxor1 xor sxor2; 24 | S <= sxor3 xor ci; 25 | co <= (X3 and X4) or (X2 and X4) or (X2 and X3); 26 | C <= ci when sxor3='1' else X1; 27 | end CSA_4_2_arch; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/fused_accm_tree/CSA_4_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity CSA_4_2 is 6 | port( 7 | ci :in std_logic; 8 | X1 :in std_logic; 9 | X2 :in std_logic; 10 | X3 :in std_logic; 11 | X4 :in std_logic; 12 | co :out std_logic; 13 | C :out std_logic; 14 | S :out std_logic 15 | ); 16 | end entity CSA_4_2; 17 | 18 | architecture CSA_4_2_arch of CSA_4_2 is 19 | signal sxor1, sxor2, sxor3 :std_logic; 20 | begin 21 | sxor1 <= X1 xor X2; 22 | sxor2 <= X3 xor X4; 23 | sxor3 <= sxor1 xor sxor2; 24 | S <= sxor3 xor ci; 25 | co <= (X3 and X4) or (X2 and X4) or (X2 and X3); 26 | C <= ci when sxor3='1' else X1; 27 | end CSA_4_2_arch; -------------------------------------------------------------------------------- /Golden model/bin2dec.m: -------------------------------------------------------------------------------- 1 | function y = bin2dec(x) 2 | format long 3 | 4 | b = strsplit(x,"."); 5 | 6 | intbin = char(b(1)); 7 | fracbin = char(b(2)); 8 | 9 | int = 0; 10 | frac = 0; 11 | 12 | % Integer part 13 | if size(intbin,2) > 1 14 | intbin = fliplr(intbin); 15 | for i=size(intbin,2):-1:1 16 | int = int + str2double(intbin(i))*2^(i-1); 17 | end 18 | else 19 | if str2double(intbin) == 1 20 | int = 1; 21 | end 22 | end 23 | 24 | % Fractional part 25 | if size(fracbin,2) > 0 26 | for i=1:size(fracbin,2) 27 | frac = frac + str2double(fracbin(i))*2^-i; 28 | end 29 | end 30 | y = int + frac; 31 | end -------------------------------------------------------------------------------- /Golden model/dec2bin.m: -------------------------------------------------------------------------------- 1 | function y = dec2bin(x,nd) 2 | format long 3 | 4 | int = floor(x); 5 | frac = x - int; 6 | nd_aux = nd; 7 | 8 | intbin = ''; 9 | fracbin = ''; 10 | 11 | % Integer part 12 | if int > 0 13 | while (int>0) 14 | if mod(int,2) == 1 15 | intbin = strcat('1',intbin); 16 | int = floor(int/2); 17 | else 18 | intbin = strcat('0',intbin); 19 | int = floor(int/2); 20 | end 21 | end 22 | else 23 | intbin = '0'; 24 | end 25 | 26 | % Fractional part 27 | while (nd>0) 28 | frac = frac*2; 29 | if frac >= 1 30 | fracbin = strcat(fracbin,'1'); 31 | frac = frac - 1; 32 | else 33 | fracbin = strcat(fracbin,'0'); 34 | end 35 | nd = nd - 1; 36 | end 37 | 38 | if nd_aux == 0 39 | y = intbin; 40 | else 41 | y = strcat(intbin,'.',fracbin); 42 | end 43 | end 44 | -------------------------------------------------------------------------------- /Golden model/dec2bin754.m: -------------------------------------------------------------------------------- 1 | function y = dec2bin754(x) 2 | format long 3 | 4 | cond_dec = 0; 5 | 6 | int = floor(x); 7 | frac = x - int; 8 | 9 | intbin = ''; 10 | fracbin = ''; 11 | 12 | % Integer part 13 | if int > 0 14 | while (int>0) 15 | if mod(int,2) == 1 16 | intbin = strcat('1',intbin); 17 | int = floor(int/2); 18 | else 19 | intbin = strcat('0',intbin); 20 | int = floor(int/2); 21 | end 22 | end 23 | else 24 | intbin = '0'; 25 | end 26 | 27 | % Fractional part 28 | if frac ~=0 29 | while (cond_dec == 0) 30 | frac = frac*2; 31 | if frac >= 1 32 | fracbin = strcat(fracbin,'1'); 33 | frac = frac - 1; 34 | cond_dec = 1; 35 | else 36 | fracbin = strcat(fracbin,'0'); 37 | end 38 | end 39 | end 40 | 41 | y = strcat(intbin,'.',fracbin); 42 | end -------------------------------------------------------------------------------- /Description/SFU_11/SFU/voter/voter.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity voter is 6 | generic( 7 | word_bits :natural:=2 8 | ); 9 | port( 10 | z1, z2, z3 : in std_logic_vector(word_bits-1 downto 0); 11 | z : out std_logic_vector(word_bits-1 downto 0); 12 | error : out std_logic 13 | ); 14 | end entity; 15 | 16 | architecture behav of voter is 17 | signal match_12, match_23, match_13 :std_logic; 18 | begin 19 | 20 | match_process: process (z1,z2,z3) 21 | begin 22 | for i in 1 to word_bits-1 loop 23 | match_12 <= (z1(i) xnor z2(i)) and (z1(i-1) xnor z2(i-1)); 24 | match_23 <= (z2(i) xnor z3(i)) and (z2(i-1) xnor z3(i-1)); 25 | match_13 <= (z1(i) xnor z3(i)) and (z1(i-1) xnor z3(i-1)); 26 | end loop; 27 | end process; 28 | 29 | error <= not(match_12 or match_23 or match_13); 30 | 31 | out_process: process(z1,z2,match_13) 32 | begin 33 | for i in 0 to word_bits-1 loop 34 | z(i) <= (match_13 and z1(i)) or (not(match_13) and z2(i)); 35 | end loop; 36 | end process; 37 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/voter/voter.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity voter is 6 | generic( 7 | word_bits :natural:=2 8 | ); 9 | port( 10 | z1, z2, z3 : in std_logic_vector(word_bits-1 downto 0); 11 | z : out std_logic_vector(word_bits-1 downto 0); 12 | error : out std_logic 13 | ); 14 | end entity; 15 | 16 | architecture behav of voter is 17 | signal match_12, match_23, match_13 :std_logic; 18 | begin 19 | 20 | match_process: process (z1,z2,z3) 21 | begin 22 | for i in 1 to word_bits-1 loop 23 | match_12 <= (z1(i) xnor z2(i)) and (z1(i-1) xnor z2(i-1)); 24 | match_23 <= (z2(i) xnor z3(i)) and (z2(i-1) xnor z3(i-1)); 25 | match_13 <= (z1(i) xnor z3(i)) and (z1(i-1) xnor z3(i-1)); 26 | end loop; 27 | end process; 28 | 29 | error <= not(match_12 or match_23 or match_13); 30 | 31 | out_process: process(z1,z2,match_13) 32 | begin 33 | for i in 0 to word_bits-1 loop 34 | z(i) <= (match_13 and z1(i)) or (not(match_13) and z2(i)); 35 | end loop; 36 | end process; 37 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/voter/voter.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity voter is 6 | generic( 7 | word_bits :natural:=2 8 | ); 9 | port( 10 | z1, z2, z3 : in std_logic_vector(word_bits-1 downto 0); 11 | z : out std_logic_vector(word_bits-1 downto 0); 12 | error : out std_logic 13 | ); 14 | end entity; 15 | 16 | architecture behav of voter is 17 | signal match_12, match_23, match_13 :std_logic; 18 | begin 19 | 20 | match_process: process (z1,z2,z3) 21 | begin 22 | for i in 1 to word_bits-1 loop 23 | match_12 <= (z1(i) xnor z2(i)) and (z1(i-1) xnor z2(i-1)); 24 | match_23 <= (z2(i) xnor z3(i)) and (z2(i-1) xnor z3(i-1)); 25 | match_13 <= (z1(i) xnor z3(i)) and (z1(i-1) xnor z3(i-1)); 26 | end loop; 27 | end process; 28 | 29 | error <= not(match_12 or match_23 or match_13); 30 | 31 | out_process: process(z1,z2,match_13) 32 | begin 33 | for i in 0 to word_bits-1 loop 34 | z(i) <= (match_13 and z1(i)) or (not(match_13) and z2(i)); 35 | end loop; 36 | end process; 37 | end architecture; -------------------------------------------------------------------------------- /Golden model/hex2bin.m: -------------------------------------------------------------------------------- 1 | function y = hex2bin(x) 2 | y = ''; 3 | for i=1:size(x,2) 4 | if x(i)=='0' 5 | y = strcat(y,"0000"); 6 | elseif x(i)=='1' 7 | y = strcat(y,"0001"); 8 | elseif x(i)=='2' 9 | y = strcat(y,"0010"); 10 | elseif x(i)=='3' 11 | y = strcat(y,"0011"); 12 | elseif x(i)=='4' 13 | y = strcat(y,"0100"); 14 | elseif x(i)=='5' 15 | y = strcat(y,"0101"); 16 | elseif x(i)=='6' 17 | y = strcat(y,"0110"); 18 | elseif x(i)=='7' 19 | y = strcat(y,"0111"); 20 | elseif x(i)=='8' 21 | y = strcat(y,"1000"); 22 | elseif x(i)=='9' 23 | y = strcat(y,"1001"); 24 | elseif x(i)=='a' || x(i)=='A' 25 | y = strcat(y,"1010"); 26 | elseif x(i)=='b' || x(i)=='B' 27 | y = strcat(y,"1011"); 28 | elseif x(i)=='c' || x(i)=='C' 29 | y = strcat(y,"1100"); 30 | elseif x(i)=='d' || x(i)=='D' 31 | y = strcat(y,"1101"); 32 | elseif x(i)=='e' || x(i)=='E' 33 | y = strcat(y,"1110"); 34 | elseif x(i)=='f' || x(i)=='F' 35 | y = strcat(y,"1111"); 36 | end 37 | end 38 | end -------------------------------------------------------------------------------- /Description/SFU_11/SFU/sfu_tb_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity sfu_tb_2 is 6 | end entity sfu_tb_2; 7 | 8 | architecture verification of sfu_tb_2 is 9 | signal s_src1_i :std_logic_vector(31 downto 0):=(others=>'0'); 10 | signal s_selop_i :std_logic_vector(2 downto 0):=(others=>'0'); 11 | signal s_Result_o :std_logic_vector(31 downto 0); 12 | 13 | signal lsfr_input :std_logic_vector(31 downto 0):=X"00000001"; 14 | signal lsfr_op :std_logic_vector(3 downto 0):="1000"; 15 | 16 | signal s_sel_phase :std_logic :='0'; 17 | signal s_rro_result :std_logic_vector(31 downto 0):=(others=>'0'); 18 | 19 | signal s_sfu_input :std_logic_vector(31 downto 0):=(others=>'0'); 20 | begin 21 | s_sel_phase <= '1' when s_selop_i = "100" else '0'; 22 | 23 | UUT: entity work.rro 24 | port map( 25 | selec_phase => s_sel_phase, 26 | input => s_src1_i, 27 | Result => s_rro_result); 28 | 29 | s_sfu_input <= s_rro_result when s_selop_i="000" else -- sin(x) 30 | s_rro_result when s_selop_i="001" else -- cos(x) 31 | s_rro_result when s_selop_i="100" else -- 2^x 32 | s_src1_i; 33 | 34 | DUT: entity work.sfu 35 | port map( 36 | src1_i => s_sfu_input, 37 | selop_i => s_selop_i, 38 | Result_o => s_Result_o); 39 | 40 | s_selop_i <= "000"; 41 | s_src1_i <= X"C3012443"; 42 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/sfu_tb_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity sfu_tb_2 is 6 | end entity sfu_tb_2; 7 | 8 | architecture verification of sfu_tb_2 is 9 | signal s_src1_i :std_logic_vector(31 downto 0):=(others=>'0'); 10 | signal s_selop_i :std_logic_vector(2 downto 0):=(others=>'0'); 11 | signal s_Result_o :std_logic_vector(31 downto 0); 12 | 13 | signal lsfr_input :std_logic_vector(31 downto 0):=X"00000001"; 14 | signal lsfr_op :std_logic_vector(3 downto 0):="1000"; 15 | 16 | signal s_sel_phase :std_logic :='0'; 17 | signal s_rro_result :std_logic_vector(31 downto 0):=(others=>'0'); 18 | 19 | signal s_sfu_input :std_logic_vector(31 downto 0):=(others=>'0'); 20 | 21 | signal s_Quad_int_err :std_logic:='0'; 22 | begin 23 | s_sel_phase <= '1' when s_selop_i = "100" else '0'; 24 | 25 | UUT: entity work.rro 26 | port map( 27 | selec_phase => s_sel_phase, 28 | input => s_src1_i, 29 | Result => s_rro_result); 30 | 31 | s_sfu_input <= s_rro_result when s_selop_i="000" else -- sin(x) 32 | s_rro_result when s_selop_i="001" else -- cos(x) 33 | s_rro_result when s_selop_i="100" else -- 2^x 34 | s_src1_i; 35 | 36 | DUT: entity work.sfu 37 | port map( 38 | src1_i => s_sfu_input, 39 | selop_i => s_selop_i, 40 | Result_o => s_Result_o, 41 | Quad_int_err => s_Quad_int_err); 42 | 43 | s_selop_i <= "000"; 44 | s_src1_i <= X"C3012443"; 45 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/sfu_tb_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity sfu_tb_2 is 6 | end entity sfu_tb_2; 7 | 8 | architecture verification of sfu_tb_2 is 9 | signal s_src1_i :std_logic_vector(31 downto 0):=(others=>'0'); 10 | signal s_selop_i :std_logic_vector(2 downto 0):=(others=>'0'); 11 | signal s_Result_o :std_logic_vector(31 downto 0); 12 | 13 | signal lsfr_input :std_logic_vector(31 downto 0):=X"00000001"; 14 | signal lsfr_op :std_logic_vector(3 downto 0):="1000"; 15 | 16 | signal s_sel_phase :std_logic :='0'; 17 | signal s_rro_result :std_logic_vector(31 downto 0):=(others=>'0'); 18 | 19 | signal s_sfu_input :std_logic_vector(31 downto 0):=(others=>'0'); 20 | 21 | signal s_Quad_int_err :std_logic:='0'; 22 | begin 23 | s_sel_phase <= '1' when s_selop_i = "100" else '0'; 24 | 25 | UUT: entity work.rro 26 | port map( 27 | selec_phase => s_sel_phase, 28 | input => s_src1_i, 29 | Result => s_rro_result); 30 | 31 | s_sfu_input <= s_rro_result when s_selop_i="000" else -- sin(x) 32 | s_rro_result when s_selop_i="001" else -- cos(x) 33 | s_rro_result when s_selop_i="100" else -- 2^x 34 | s_src1_i; 35 | 36 | DUT: entity work.sfu 37 | port map( 38 | src1_i => s_sfu_input, 39 | selop_i => s_selop_i, 40 | Result_o => s_Result_o, 41 | Quad_int_err => s_Quad_int_err); 42 | 43 | s_selop_i <= "000"; 44 | s_src1_i <= X"C3012443"; 45 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/Verification/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | 4 | radix define iee754s_fp -float -fraction 23 -base decimal -precision 10 5 | 6 | set SFUS 1 7 | 8 | add wave -noupdate -label CLK /sfu_tb/s_clk_i 9 | add wave -noupdate -label DATA_IN -radix hexadecimal /sfu_tb/s_src1_i 10 | add wave -noupdate -label DATA_RRO -radix hexadecimal /sfu_tb/s_sfu_input 11 | add wave -noupdate -label OPER /sfu_tb/s_selop_i 12 | add wave -noupdate -label RESULT -radix hexadecimal /sfu_tb/s_Result_o 13 | 14 | add wave -noupdate -group SFU_PROC /sfu_tb/DUT/* 15 | 16 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/uQuadraticInterpol/* 17 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol/u_SpecialSquaringUnit/* 18 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol/uFusedAccTree/* 19 | 20 | add wave -noupdate -group Test_Bench_Signals /sfu_tb/* 21 | 22 | TreeUpdate [SetDefaultTree] 23 | WaveRestoreCursors {{Cursor 1} {80000 ps} 0} 24 | quietly wave cursor active 1 25 | configure wave -namecolwidth 76 26 | configure wave -valuecolwidth 49 27 | configure wave -justifyvalue left 28 | configure wave -signalnamewidth 0 29 | configure wave -snapdistance 10 30 | configure wave -datasetprefix 0 31 | configure wave -rowmargin 4 32 | configure wave -childrowmargin 2 33 | configure wave -gridoffset 0 34 | configure wave -gridperiod 1 35 | configure wave -griddelta 40 36 | configure wave -timeline 0 37 | configure wave -timelineunits ns 38 | update 39 | WaveRestoreZoom {0 ps} {180 ns} 40 | -------------------------------------------------------------------------------- /Golden model/binaryVectorToHex.m: -------------------------------------------------------------------------------- 1 | function [y] = binaryVectorToHex(x) 2 | y=""; 3 | for i=1:8 4 | if compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 0 0 0]) 5 | aux = "0"; 6 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 0 0 1]) 7 | aux = "1"; 8 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 0 1 0]) 9 | aux = "2"; 10 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 0 1 1]) 11 | aux = "3"; 12 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 1 0 0]) 13 | aux = "4"; 14 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 1 0 1]) 15 | aux = "5"; 16 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 1 1 0]) 17 | aux = "6"; 18 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[0 1 1 1]) 19 | aux = "7"; 20 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 0 0 0]) 21 | aux = "8"; 22 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 0 0 1]) 23 | aux = "9"; 24 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 0 1 0]) 25 | aux = "A"; 26 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 0 1 1]) 27 | aux = "B"; 28 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 1 0 0]) 29 | aux = "C"; 30 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 1 0 1]) 31 | aux = "D"; 32 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 1 1 0]) 33 | aux = "E"; 34 | elseif compare_vector(x(((i-1)*4)+1:((i-1)*4)+4),[1 1 1 1]) 35 | aux = "F"; 36 | endif 37 | 38 | y = strcat(y,aux); 39 | endfor 40 | end 41 | -------------------------------------------------------------------------------- /Description/SFU_00/SFU/sfu_tb_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity sfu_tb_2 is 6 | end entity sfu_tb_2; 7 | 8 | architecture verification of sfu_tb_2 is 9 | signal s_src1_i :std_logic_vector(31 downto 0):=(others=>'0'); 10 | signal s_selop_i :std_logic_vector(2 downto 0):=(others=>'0'); 11 | -- "000" => sin(x) 12 | -- "001" => cos(x) 13 | -- "010" => rsqrt(x) 14 | -- "011" => log2(x) 15 | -- "100" => 2^x 16 | -- "101" => 1/x 17 | -- "110" => sqrt(x) 18 | -- "111" => bypass x 19 | signal s_Result_o :std_logic_vector(31 downto 0); 20 | 21 | signal lsfr_input :std_logic_vector(31 downto 0):=X"00000001"; 22 | signal lsfr_op :std_logic_vector(3 downto 0):="1000"; 23 | 24 | signal s_sel_phase :std_logic :='0'; 25 | signal s_rro_result :std_logic_vector(31 downto 0):=(others=>'0'); 26 | 27 | signal s_sfu_input :std_logic_vector(31 downto 0):=(others=>'0'); 28 | begin 29 | s_sel_phase <= '1' when s_selop_i = "100" else '0'; 30 | 31 | UUT: entity work.rro 32 | port map( 33 | selec_phase => s_sel_phase, 34 | input => s_src1_i, 35 | Result => s_rro_result); 36 | 37 | s_sfu_input <= s_rro_result when s_selop_i="000" else -- sin(x) 38 | s_rro_result when s_selop_i="001" else -- cos(x) 39 | s_rro_result when s_selop_i="100" else -- 2^x 40 | s_src1_i; 41 | 42 | DUT: entity work.sfu 43 | port map( 44 | src1_i => s_sfu_input, 45 | selop_i => s_selop_i, 46 | Result_o => s_Result_o); 47 | 48 | s_selop_i <= "101"; 49 | s_src1_i <= X"38d1b717"; 50 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/fused_accm_tree/Booth_PP.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | 6 | entity Booth_PP is 7 | generic( 8 | Data_widht :natural :=8 9 | ); 10 | port( 11 | x_i0 :in std_logic; 12 | x_i1 :in std_logic; 13 | x_i2 :in std_logic; 14 | Data_i :in std_logic_vector(Data_widht-1 downto 0); 15 | Data_o :out std_logic_vector(Data_widht-1 downto 0); 16 | adj_o :out std_logic 17 | ); 18 | end entity Booth_PP; 19 | 20 | architecture Booth_PP_arch of Booth_PP is 21 | signal signo_booth, signo_oper, zero, two_m :std_logic; 22 | signal shift :std_logic_vector(Data_widht-1 downto 0); 23 | signal sign_extend :std_logic_vector(Data_widht-1 downto 0); 24 | signal data_comp :std_logic_vector(Data_widht-1 downto 0); 25 | signal zero_extend :std_logic_vector(Data_widht-1 downto 0); 26 | signal data_o_tmp :std_logic_vector(Data_widht-1 downto 0); 27 | begin 28 | signo_booth <= (x_i2 and (not x_i1)) or (x_i2 and (not(x_i0))); 29 | 30 | two_m <= (x_i2 and (not(x_i1)) and (not(x_i0))) or ((not(x_i2)) and x_i1 and x_i0); 31 | 32 | zero <= (x_i2 or x_i1 or x_i0) and ((not(x_i2)) or (not(x_i1)) or (not(x_i0))); 33 | 34 | signo_oper <= signo_booth xor Data_i(Data_widht-1); 35 | 36 | shift <= Data_i(Data_widht-2 downto 0)&'0' when two_m='1' else '0'&Data_i(Data_widht-2 downto 0); 37 | 38 | sign_extend <= (others=>signo_oper); 39 | 40 | data_comp <= sign_extend xor shift; 41 | 42 | zero_extend <= (others=>zero); 43 | 44 | data_o_tmp <= zero_extend and data_comp; 45 | 46 | Data_o(Data_widht-1) <= not data_o_tmp(Data_widht-1); 47 | Data_o(Data_widht-2 downto 0) <= data_o_tmp(Data_widht-2 downto 0); 48 | adj_o <= signo_oper and zero; 49 | end Booth_PP_arch; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/fused_accm_tree/Booth_PP.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | 6 | entity Booth_PP is 7 | generic( 8 | Data_widht :natural :=8 9 | ); 10 | port( 11 | x_i0 :in std_logic; 12 | x_i1 :in std_logic; 13 | x_i2 :in std_logic; 14 | Data_i :in std_logic_vector(Data_widht-1 downto 0); 15 | Data_o :out std_logic_vector(Data_widht-1 downto 0); 16 | adj_o :out std_logic 17 | ); 18 | end entity Booth_PP; 19 | 20 | architecture Booth_PP_arch of Booth_PP is 21 | signal signo_booth, signo_oper, zero, two_m :std_logic; 22 | signal shift :std_logic_vector(Data_widht-1 downto 0); 23 | signal sign_extend :std_logic_vector(Data_widht-1 downto 0); 24 | signal data_comp :std_logic_vector(Data_widht-1 downto 0); 25 | signal zero_extend :std_logic_vector(Data_widht-1 downto 0); 26 | signal data_o_tmp :std_logic_vector(Data_widht-1 downto 0); 27 | begin 28 | signo_booth <= (x_i2 and (not x_i1)) or (x_i2 and (not(x_i0))); 29 | 30 | two_m <= (x_i2 and (not(x_i1)) and (not(x_i0))) or ((not(x_i2)) and x_i1 and x_i0); 31 | 32 | zero <= (x_i2 or x_i1 or x_i0) and ((not(x_i2)) or (not(x_i1)) or (not(x_i0))); 33 | 34 | signo_oper <= signo_booth xor Data_i(Data_widht-1); 35 | 36 | shift <= Data_i(Data_widht-2 downto 0)&'0' when two_m='1' else '0'&Data_i(Data_widht-2 downto 0); 37 | 38 | sign_extend <= (others=>signo_oper); 39 | 40 | data_comp <= sign_extend xor shift; 41 | 42 | zero_extend <= (others=>zero); 43 | 44 | data_o_tmp <= zero_extend and data_comp; 45 | 46 | Data_o(Data_widht-1) <= not data_o_tmp(Data_widht-1); 47 | Data_o(Data_widht-2 downto 0) <= data_o_tmp(Data_widht-2 downto 0); 48 | adj_o <= signo_oper and zero; 49 | end Booth_PP_arch; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/fused_accm_tree/Booth_PP.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | 6 | entity Booth_PP is 7 | generic( 8 | Data_widht :natural :=8 9 | ); 10 | port( 11 | x_i0 :in std_logic; 12 | x_i1 :in std_logic; 13 | x_i2 :in std_logic; 14 | Data_i :in std_logic_vector(Data_widht-1 downto 0); 15 | Data_o :out std_logic_vector(Data_widht-1 downto 0); 16 | adj_o :out std_logic 17 | ); 18 | end entity Booth_PP; 19 | 20 | architecture Booth_PP_arch of Booth_PP is 21 | signal signo_booth, signo_oper, zero, two_m :std_logic; 22 | signal shift :std_logic_vector(Data_widht-1 downto 0); 23 | signal sign_extend :std_logic_vector(Data_widht-1 downto 0); 24 | signal data_comp :std_logic_vector(Data_widht-1 downto 0); 25 | signal zero_extend :std_logic_vector(Data_widht-1 downto 0); 26 | signal data_o_tmp :std_logic_vector(Data_widht-1 downto 0); 27 | begin 28 | signo_booth <= (x_i2 and (not x_i1)) or (x_i2 and (not(x_i0))); 29 | 30 | two_m <= (x_i2 and (not(x_i1)) and (not(x_i0))) or ((not(x_i2)) and x_i1 and x_i0); 31 | 32 | zero <= (x_i2 or x_i1 or x_i0) and ((not(x_i2)) or (not(x_i1)) or (not(x_i0))); 33 | 34 | signo_oper <= signo_booth xor Data_i(Data_widht-1); 35 | 36 | shift <= Data_i(Data_widht-2 downto 0)&'0' when two_m='1' else '0'&Data_i(Data_widht-2 downto 0); 37 | 38 | sign_extend <= (others=>signo_oper); 39 | 40 | data_comp <= sign_extend xor shift; 41 | 42 | zero_extend <= (others=>zero); 43 | 44 | data_o_tmp <= zero_extend and data_comp; 45 | 46 | Data_o(Data_widht-1) <= not data_o_tmp(Data_widht-1); 47 | Data_o(Data_widht-2 downto 0) <= data_o_tmp(Data_widht-2 downto 0); 48 | adj_o <= signo_oper and zero; 49 | end Booth_PP_arch; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/fused_accm_tree/Booth_PP.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | 6 | entity Booth_PP is 7 | generic( 8 | Data_widht :natural :=8 9 | ); 10 | port( 11 | x_i0 :in std_logic; 12 | x_i1 :in std_logic; 13 | x_i2 :in std_logic; 14 | Data_i :in std_logic_vector(Data_widht-1 downto 0); 15 | Data_o :out std_logic_vector(Data_widht-1 downto 0); 16 | adj_o :out std_logic 17 | ); 18 | end entity Booth_PP; 19 | 20 | architecture Booth_PP_arch of Booth_PP is 21 | signal signo_booth, signo_oper, zero, two_m :std_logic; 22 | signal shift :std_logic_vector(Data_widht-1 downto 0); 23 | signal sign_extend :std_logic_vector(Data_widht-1 downto 0); 24 | signal data_comp :std_logic_vector(Data_widht-1 downto 0); 25 | signal zero_extend :std_logic_vector(Data_widht-1 downto 0); 26 | signal data_o_tmp :std_logic_vector(Data_widht-1 downto 0); 27 | begin 28 | signo_booth <= (x_i2 and (not x_i1)) or (x_i2 and (not(x_i0))); 29 | 30 | two_m <= (x_i2 and (not(x_i1)) and (not(x_i0))) or ((not(x_i2)) and x_i1 and x_i0); 31 | 32 | zero <= (x_i2 or x_i1 or x_i0) and ((not(x_i2)) or (not(x_i1)) or (not(x_i0))); 33 | 34 | signo_oper <= signo_booth xor Data_i(Data_widht-1); 35 | 36 | shift <= Data_i(Data_widht-2 downto 0)&'0' when two_m='1' else '0'&Data_i(Data_widht-2 downto 0); 37 | 38 | sign_extend <= (others=>signo_oper); 39 | 40 | data_comp <= sign_extend xor shift; 41 | 42 | zero_extend <= (others=>zero); 43 | 44 | data_o_tmp <= zero_extend and data_comp; 45 | 46 | Data_o(Data_widht-1) <= not data_o_tmp(Data_widht-1); 47 | Data_o(Data_widht-2 downto 0) <= data_o_tmp(Data_widht-2 downto 0); 48 | adj_o <= signo_oper and zero; 49 | end Booth_PP_arch; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=8; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "11111101", 21 | "11110111", 22 | "11110001", 23 | "11101100", 24 | "11100111", 25 | "11100010", 26 | "11011101", 27 | "11011000", 28 | "11010100", 29 | "11010000", 30 | "11001011", 31 | "11000111", 32 | "11000011", 33 | "11000000", 34 | "10111100", 35 | "10111000", 36 | "10110101", 37 | "10110010", 38 | "10101110", 39 | "10101011", 40 | "10101000", 41 | "10100101", 42 | "10100010", 43 | "10100000", 44 | "10011101", 45 | "10011010", 46 | "10011000", 47 | "10010101", 48 | "10010011", 49 | "10010000", 50 | "10001110", 51 | "10001100", 52 | "10001010", 53 | "10001000", 54 | "10000110", 55 | "10000100", 56 | "10000010", 57 | "10000000", 58 | "01111110", 59 | "01111100", 60 | "01111010", 61 | "01111000", 62 | "01110111", 63 | "01110101", 64 | "01110011", 65 | "01110010", 66 | "01110000", 67 | "01101111", 68 | "01101101", 69 | "01101100", 70 | "01101010", 71 | "01101001", 72 | "01101000", 73 | "01100110", 74 | "01100101", 75 | "01100100", 76 | "01100011", 77 | "01100001", 78 | "01100000", 79 | "01011111", 80 | "01011110", 81 | "01011101", 82 | "01011100", 83 | "01011011" 84 | ); 85 | begin 86 | data <= "1000"&rom(to_integer(unsigned(addr)))&"00"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_ln2e0 is 6 | generic( 7 | word_bits :natural:=9; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111100011", 21 | "111010011", 22 | "111000011", 23 | "110110100", 24 | "110100110", 25 | "110011000", 26 | "110001011", 27 | "101111111", 28 | "101110011", 29 | "101101000", 30 | "101011101", 31 | "101010011", 32 | "101001001", 33 | "100111111", 34 | "100110110", 35 | "100101101", 36 | "100100101", 37 | "100011100", 38 | "100010101", 39 | "100001101", 40 | "100000110", 41 | "011111111", 42 | "011111000", 43 | "011110010", 44 | "011101100", 45 | "011100110", 46 | "011100000", 47 | "011011010", 48 | "011010101", 49 | "011010000", 50 | "011001011", 51 | "011000110", 52 | "011000001", 53 | "010111101", 54 | "010111000", 55 | "010110100", 56 | "010110000", 57 | "010101100", 58 | "010101000", 59 | "010100100", 60 | "010100001", 61 | "010011101", 62 | "010011010", 63 | "010010110", 64 | "010010011", 65 | "010010000", 66 | "010001101", 67 | "010001010", 68 | "010000111", 69 | "010000101", 70 | "010000010", 71 | "001111111", 72 | "001111101", 73 | "001111010", 74 | "001111000", 75 | "001110110", 76 | "001110011", 77 | "001110001", 78 | "001101111", 79 | "001101101", 80 | "001101011", 81 | "001101001", 82 | "001100111", 83 | "001100101" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr)))&"000"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=9; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "101100101", 21 | "101011101", 22 | "101010101", 23 | "101001110", 24 | "101000110", 25 | "100111111", 26 | "100111001", 27 | "100110010", 28 | "100101100", 29 | "100100110", 30 | "100100000", 31 | "100011010", 32 | "100010101", 33 | "100001111", 34 | "100001010", 35 | "100000101", 36 | "100000000", 37 | "011111011", 38 | "011110111", 39 | "011110010", 40 | "011101110", 41 | "011101010", 42 | "011100110", 43 | "011100010", 44 | "011011110", 45 | "011011010", 46 | "011010111", 47 | "011010011", 48 | "011010000", 49 | "011001101", 50 | "011001001", 51 | "011000110", 52 | "011000011", 53 | "011000000", 54 | "010111101", 55 | "010111010", 56 | "010110111", 57 | "010110101", 58 | "010110010", 59 | "010110000", 60 | "010101101", 61 | "010101011", 62 | "010101000", 63 | "010100110", 64 | "010100100", 65 | "010100001", 66 | "010011111", 67 | "010011101", 68 | "010011011", 69 | "010011001", 70 | "010010111", 71 | "010010101", 72 | "010010011", 73 | "010010001", 74 | "010001111", 75 | "010001101", 76 | "010001100", 77 | "010001010", 78 | "010001000", 79 | "010000111", 80 | "010000101", 81 | "010000011", 82 | "010000010", 83 | "010000000" 84 | ); 85 | begin 86 | data <= "100"&rom(to_integer(unsigned(addr)))&"00"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_exp is 6 | generic( 7 | word_bits :natural:=10; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0111101110", 21 | "0111110100", 22 | "0111111001", 23 | "0111111110", 24 | "1000000100", 25 | "1000001010", 26 | "1000001111", 27 | "1000010101", 28 | "1000011011", 29 | "1000100001", 30 | "1000100111", 31 | "1000101101", 32 | "1000110011", 33 | "1000111001", 34 | "1000111111", 35 | "1001000101", 36 | "1001001100", 37 | "1001010010", 38 | "1001011001", 39 | "1001011111", 40 | "1001100110", 41 | "1001101100", 42 | "1001110011", 43 | "1001111010", 44 | "1010000001", 45 | "1010001000", 46 | "1010001111", 47 | "1010010110", 48 | "1010011101", 49 | "1010100101", 50 | "1010101100", 51 | "1010110100", 52 | "1010111011", 53 | "1011000011", 54 | "1011001010", 55 | "1011010010", 56 | "1011011010", 57 | "1011100010", 58 | "1011101010", 59 | "1011110010", 60 | "1011111010", 61 | "1100000011", 62 | "1100001011", 63 | "1100010100", 64 | "1100011100", 65 | "1100100101", 66 | "1100101110", 67 | "1100110110", 68 | "1100111111", 69 | "1101001000", 70 | "1101010010", 71 | "1101011011", 72 | "1101100100", 73 | "1101101110", 74 | "1101110111", 75 | "1110000001", 76 | "1110001011", 77 | "1110010101", 78 | "1110011111", 79 | "1110101001", 80 | "1110110011", 81 | "1110111101", 82 | "1111001000", 83 | "1111010010" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr)))&"00"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=10; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111110100", 21 | "1111011100", 22 | "1111000100", 23 | "1110110000", 24 | "1110011100", 25 | "1110001000", 26 | "1101110100", 27 | "1101100000", 28 | "1101010000", 29 | "1101000000", 30 | "1100101100", 31 | "1100011100", 32 | "1100001100", 33 | "1100000000", 34 | "1011110000", 35 | "1011100000", 36 | "1011010100", 37 | "1011001000", 38 | "1010111000", 39 | "1010101100", 40 | "1010100000", 41 | "1010010100", 42 | "1010001000", 43 | "1010000000", 44 | "1001110100", 45 | "1001101000", 46 | "1001100000", 47 | "1001010100", 48 | "1001001100", 49 | "1001000000", 50 | "1000111000", 51 | "1000110000", 52 | "1000101000", 53 | "1000100000", 54 | "1000011000", 55 | "1000010000", 56 | "1000001000", 57 | "1000000000", 58 | "0111111000", 59 | "0111110000", 60 | "0111101000", 61 | "0111100000", 62 | "0111011100", 63 | "0111010100", 64 | "0111001100", 65 | "0111001000", 66 | "0111000000", 67 | "0110111100", 68 | "0110110100", 69 | "0110110000", 70 | "0110101000", 71 | "0110100100", 72 | "0110100000", 73 | "0110011000", 74 | "0110010100", 75 | "0110010000", 76 | "0110001100", 77 | "0110000100", 78 | "0110000000", 79 | "0101111100", 80 | "0101111000", 81 | "0101110100", 82 | "0101110000", 83 | "0101101100" 84 | ); 85 | begin 86 | data <= "1000"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=10; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111110100", 21 | "1111011100", 22 | "1111000100", 23 | "1110110000", 24 | "1110011100", 25 | "1110001000", 26 | "1101110100", 27 | "1101100000", 28 | "1101010000", 29 | "1101000000", 30 | "1100101100", 31 | "1100011100", 32 | "1100001100", 33 | "1100000000", 34 | "1011110000", 35 | "1011100000", 36 | "1011010100", 37 | "1011001000", 38 | "1010111000", 39 | "1010101100", 40 | "1010100000", 41 | "1010010100", 42 | "1010001000", 43 | "1010000000", 44 | "1001110100", 45 | "1001101000", 46 | "1001100000", 47 | "1001010100", 48 | "1001001100", 49 | "1001000000", 50 | "1000111000", 51 | "1000110000", 52 | "1000101000", 53 | "1000100000", 54 | "1000011000", 55 | "1000010000", 56 | "1000001000", 57 | "1000000000", 58 | "0111111000", 59 | "0111110000", 60 | "0111101000", 61 | "0111100000", 62 | "0111011100", 63 | "0111010100", 64 | "0111001100", 65 | "0111001000", 66 | "0111000000", 67 | "0110111100", 68 | "0110110100", 69 | "0110110000", 70 | "0110101000", 71 | "0110100100", 72 | "0110100000", 73 | "0110011000", 74 | "0110010100", 75 | "0110010000", 76 | "0110001100", 77 | "0110000100", 78 | "0110000000", 79 | "0101111100", 80 | "0101111000", 81 | "0101110100", 82 | "0101110000", 83 | "0101101100" 84 | ); 85 | begin 86 | data <= "1000"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=10; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111110100", 21 | "1111011100", 22 | "1111000100", 23 | "1110110000", 24 | "1110011100", 25 | "1110001000", 26 | "1101110100", 27 | "1101100000", 28 | "1101010000", 29 | "1101000000", 30 | "1100101100", 31 | "1100011100", 32 | "1100001100", 33 | "1100000000", 34 | "1011110000", 35 | "1011100000", 36 | "1011010100", 37 | "1011001000", 38 | "1010111000", 39 | "1010101100", 40 | "1010100000", 41 | "1010010100", 42 | "1010001000", 43 | "1010000000", 44 | "1001110100", 45 | "1001101000", 46 | "1001100000", 47 | "1001010100", 48 | "1001001100", 49 | "1001000000", 50 | "1000111000", 51 | "1000110000", 52 | "1000101000", 53 | "1000100000", 54 | "1000011000", 55 | "1000010000", 56 | "1000001000", 57 | "1000000000", 58 | "0111111000", 59 | "0111110000", 60 | "0111101000", 61 | "0111100000", 62 | "0111011100", 63 | "0111010100", 64 | "0111001100", 65 | "0111001000", 66 | "0111000000", 67 | "0110111100", 68 | "0110110100", 69 | "0110110000", 70 | "0110101000", 71 | "0110100100", 72 | "0110100000", 73 | "0110011000", 74 | "0110010100", 75 | "0110010000", 76 | "0110001100", 77 | "0110000100", 78 | "0110000000", 79 | "0101111100", 80 | "0101111000", 81 | "0101110100", 82 | "0101110000", 83 | "0101101100" 84 | ); 85 | begin 86 | data <= "1000"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_cos is 6 | generic( 7 | word_bits :natural:=11; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "11111111111", 21 | "11111111110", 22 | "11111111100", 23 | "11111111001", 24 | "11111110101", 25 | "11111110000", 26 | "11111101010", 27 | "11111100011", 28 | "11111011011", 29 | "11111010010", 30 | "11111001000", 31 | "11110111110", 32 | "11110110010", 33 | "11110100101", 34 | "11110010111", 35 | "11110001000", 36 | "11101111000", 37 | "11101100111", 38 | "11101010110", 39 | "11101000011", 40 | "11100101111", 41 | "11100011011", 42 | "11100000101", 43 | "11011101110", 44 | "11011010111", 45 | "11010111111", 46 | "11010100101", 47 | "11010001011", 48 | "11001110000", 49 | "11001010100", 50 | "11000110111", 51 | "11000011001", 52 | "10111111011", 53 | "10111011011", 54 | "10110111011", 55 | "10110011001", 56 | "10101110111", 57 | "10101010100", 58 | "10100110000", 59 | "10100001100", 60 | "10011100110", 61 | "10011000000", 62 | "10010011001", 63 | "10001110001", 64 | "10001001001", 65 | "10000011111", 66 | "01111110101", 67 | "01111001010", 68 | "01110011111", 69 | "01101110010", 70 | "01101000101", 71 | "01100010111", 72 | "01011101001", 73 | "01010111010", 74 | "01010001010", 75 | "01001011001", 76 | "01000101000", 77 | "00111110111", 78 | "00111000100", 79 | "00110010001", 80 | "00101011110", 81 | "00100101001", 82 | "00011110101", 83 | "00010111111" 84 | ); 85 | begin 86 | data <= "101"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=11; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "10110010100", 21 | "10101110100", 22 | "10101010100", 23 | "10100111000", 24 | "10100011000", 25 | "10011111100", 26 | "10011100100", 27 | "10011001000", 28 | "10010110000", 29 | "10010011000", 30 | "10010000000", 31 | "10001101000", 32 | "10001010100", 33 | "10000111100", 34 | "10000101000", 35 | "10000010100", 36 | "10000000000", 37 | "01111101100", 38 | "01111011100", 39 | "01111001000", 40 | "01110111000", 41 | "01110101000", 42 | "01110011000", 43 | "01110001000", 44 | "01101111000", 45 | "01101101000", 46 | "01101011100", 47 | "01101001100", 48 | "01101000000", 49 | "01100110100", 50 | "01100100100", 51 | "01100011000", 52 | "01100001100", 53 | "01100000000", 54 | "01011110100", 55 | "01011101000", 56 | "01011011100", 57 | "01011010100", 58 | "01011001000", 59 | "01011000000", 60 | "01010110100", 61 | "01010101100", 62 | "01010100000", 63 | "01010011000", 64 | "01010010000", 65 | "01010000100", 66 | "01001111100", 67 | "01001110100", 68 | "01001101100", 69 | "01001100100", 70 | "01001011100", 71 | "01001010100", 72 | "01001001100", 73 | "01001000100", 74 | "01000111100", 75 | "01000110100", 76 | "01000110000", 77 | "01000101000", 78 | "01000100000", 79 | "01000011100", 80 | "01000010100", 81 | "01000001100", 82 | "01000001000", 83 | "01000000000" 84 | ); 85 | begin 86 | data <= "100"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=11; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "10110010100", 21 | "10101110100", 22 | "10101010100", 23 | "10100111000", 24 | "10100011000", 25 | "10011111100", 26 | "10011100100", 27 | "10011001000", 28 | "10010110000", 29 | "10010011000", 30 | "10010000000", 31 | "10001101000", 32 | "10001010100", 33 | "10000111100", 34 | "10000101000", 35 | "10000010100", 36 | "10000000000", 37 | "01111101100", 38 | "01111011100", 39 | "01111001000", 40 | "01110111000", 41 | "01110101000", 42 | "01110011000", 43 | "01110001000", 44 | "01101111000", 45 | "01101101000", 46 | "01101011100", 47 | "01101001100", 48 | "01101000000", 49 | "01100110100", 50 | "01100100100", 51 | "01100011000", 52 | "01100001100", 53 | "01100000000", 54 | "01011110100", 55 | "01011101000", 56 | "01011011100", 57 | "01011010100", 58 | "01011001000", 59 | "01011000000", 60 | "01010110100", 61 | "01010101100", 62 | "01010100000", 63 | "01010011000", 64 | "01010010000", 65 | "01010000100", 66 | "01001111100", 67 | "01001110100", 68 | "01001101100", 69 | "01001100100", 70 | "01001011100", 71 | "01001010100", 72 | "01001001100", 73 | "01001000100", 74 | "01000111100", 75 | "01000110100", 76 | "01000110000", 77 | "01000101000", 78 | "01000100000", 79 | "01000011100", 80 | "01000010100", 81 | "01000001100", 82 | "01000001000", 83 | "01000000000" 84 | ); 85 | begin 86 | data <= "100"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=11; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "10110010100", 21 | "10101110100", 22 | "10101010100", 23 | "10100111000", 24 | "10100011000", 25 | "10011111100", 26 | "10011100100", 27 | "10011001000", 28 | "10010110000", 29 | "10010011000", 30 | "10010000000", 31 | "10001101000", 32 | "10001010100", 33 | "10000111100", 34 | "10000101000", 35 | "10000010100", 36 | "10000000000", 37 | "01111101100", 38 | "01111011100", 39 | "01111001000", 40 | "01110111000", 41 | "01110101000", 42 | "01110011000", 43 | "01110001000", 44 | "01101111000", 45 | "01101101000", 46 | "01101011100", 47 | "01101001100", 48 | "01101000000", 49 | "01100110100", 50 | "01100100100", 51 | "01100011000", 52 | "01100001100", 53 | "01100000000", 54 | "01011110100", 55 | "01011101000", 56 | "01011011100", 57 | "01011010100", 58 | "01011001000", 59 | "01011000000", 60 | "01010110100", 61 | "01010101100", 62 | "01010100000", 63 | "01010011000", 64 | "01010010000", 65 | "01010000100", 66 | "01001111100", 67 | "01001110100", 68 | "01001101100", 69 | "01001100100", 70 | "01001011100", 71 | "01001010100", 72 | "01001001100", 73 | "01001000100", 74 | "01000111100", 75 | "01000110100", 76 | "01000110000", 77 | "01000101000", 78 | "01000100000", 79 | "01000011100", 80 | "01000010100", 81 | "01000001100", 82 | "01000001000", 83 | "01000000000" 84 | ); 85 | begin 86 | data <= "100"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/Verification/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | 4 | radix define iee754s_fp -float -fraction 23 -base decimal -precision 10 5 | 6 | set SFUS 1 7 | 8 | add wave -noupdate -label CLK /sfu_tb/s_clk_i 9 | add wave -noupdate -label DATA_IN -radix hexadecimal /sfu_tb/s_src1_i 10 | add wave -noupdate -label DATA_RRO -radix hexadecimal /sfu_tb/s_sfu_input 11 | add wave -noupdate -label OPER /sfu_tb/s_selop_i 12 | add wave -noupdate -label RESULT -radix hexadecimal /sfu_tb/s_Result_o 13 | add wave -noupdate -label ErrTMR /sfu_tb/s_Quad_int_err 14 | 15 | add wave -noupdate -group SFU_PROC /sfu_tb/DUT/* 16 | 17 | 18 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/uQuadraticInterpol/* 19 | 20 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol/u_SpecialSquaringUnit_1/* 21 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol/u_SpecialSquaringUnit_2/* 22 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol/u_SpecialSquaringUnit_3/* 23 | 24 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol/uFusedAccTree_1/* 25 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol/uFusedAccTree_2/* 26 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol/uFusedAccTree_3/* 27 | 28 | add wave -noupdate -group Test_Bench_Signals /sfu_tb/* 29 | 30 | TreeUpdate [SetDefaultTree] 31 | WaveRestoreCursors {{Cursor 1} {80000 ps} 0} 32 | quietly wave cursor active 1 33 | configure wave -namecolwidth 76 34 | configure wave -valuecolwidth 49 35 | configure wave -justifyvalue left 36 | configure wave -signalnamewidth 0 37 | configure wave -snapdistance 10 38 | configure wave -datasetprefix 0 39 | configure wave -rowmargin 4 40 | configure wave -childrowmargin 2 41 | configure wave -gridoffset 0 42 | configure wave -gridperiod 1 43 | configure wave -griddelta 40 44 | configure wave -timeline 0 45 | configure wave -timelineunits ns 46 | update 47 | WaveRestoreZoom {0 ps} {180 ns} 48 | -------------------------------------------------------------------------------- /Golden model/loadLUTs.m: -------------------------------------------------------------------------------- 1 | function [LUTC0,LUTC1,LUTC2,m] = loadLUTs(func) 2 | functions = { 'reci';... -- 1 (1-2) 3 | 'sqrt_1_2';... -- 2 (1-2) 4 | 'sqrt_2_4';... -- 3 (2-4) 5 | 'reci_sqrt_1_2';... -- 4 (1-2) 6 | 'reci_sqrt_2_4';... -- 5 (2-4) 7 | 'exp';... -- 6 (0-1) 8 | 'ln2';... -- 7 (1-2) 9 | 'ln2e0';... -- 8 (1-2) 10 | 'sin';... -- 9 (0-1) 11 | 'cos'}... -- 10(0-1) 12 | ; 13 | 14 | bus_C0 = 29; 15 | bus_C1 = 20; 16 | bus_C2 = 14; 17 | 18 | % Get de look-up-tables of a function 19 | [C0d,C1d,C2d,t,p,q,m] = coeff(functions{func}); 20 | 21 | % Get de look-up-tables in binary 22 | [C0b,C1b,C2b] = coeffbin(C0d,C1d,C2d,t,p,q,m); 23 | 24 | % Get bits to storage from binary look-up-tables 25 | [C0i,C0i_concat,C0i_sign] = getLUT(C0b,C0d,1); 26 | [C1i,C1i_concat,C1i_sign] = getLUT(C1b,C1d,1); 27 | [C2i,C2i_concat,C2i_sign] = getLUT(C2b,C2d,1); 28 | 29 | % Adjust the LUT values adding zeros to the right 30 | C0i = strcat(C0i,char(zeros(1,bus_C0-2-t)+48)); 31 | C1i = strcat(C1i,char(zeros(1,bus_C1-2-p)+48)); 32 | C2i = strcat(C2i,char(zeros(1,bus_C2-1-q)+48)); 33 | 34 | % Generate the concat values 35 | C0i_concat = strcat(C0i_sign+48,char(zeros(1,bus_C0-1-size(C0i_concat,2)-size(C0i,2))+48),C0i_concat); 36 | C1i_concat = strcat(C1i_sign+48,char(zeros(1,bus_C1-1-size(C1i_concat,2)-size(C1i,2))+48),C1i_concat); 37 | C2i_concat = strcat(C2i_sign+48,char(zeros(1,bus_C2-1-size(C2i_concat,2)-size(C2i,2))+48),C2i_concat); 38 | 39 | % Change the sign of the first sine constant in LUT C0 40 | if func == 9 41 | LUTC0 = strcat(C0i_concat,C0i); 42 | LUTC0(1,1) = '1'; 43 | else 44 | LUTC0 = strcat(C0i_concat,C0i); 45 | end 46 | 47 | LUTC1 = strcat(C1i_concat,C1i); 48 | LUTC2 = strcat(C2i_concat,C2i); 49 | end -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sin is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000011111", 21 | "000001011111", 22 | "000010011111", 23 | "000011011111", 24 | "000100011111", 25 | "000101011111", 26 | "000110011111", 27 | "000111011110", 28 | "001000011110", 29 | "001001011101", 30 | "001010011100", 31 | "001011011100", 32 | "001100011010", 33 | "001101011001", 34 | "001110011000", 35 | "001111010110", 36 | "010000010100", 37 | "010001010010", 38 | "010010001111", 39 | "010011001100", 40 | "010100001001", 41 | "010101000110", 42 | "010110000010", 43 | "010110111110", 44 | "010111111001", 45 | "011000110101", 46 | "011001101111", 47 | "011010101010", 48 | "011011100100", 49 | "011100011101", 50 | "011101010110", 51 | "011110001111", 52 | "011111000111", 53 | "011111111111", 54 | "100000110110", 55 | "100001101101", 56 | "100010100011", 57 | "100011011000", 58 | "100100001110", 59 | "100101000010", 60 | "100101110110", 61 | "100110101001", 62 | "100111011100", 63 | "101000001110", 64 | "101000111111", 65 | "101001110000", 66 | "101010100000", 67 | "101011010000", 68 | "101011111111", 69 | "101100101101", 70 | "101101011010", 71 | "101110000111", 72 | "101110110011", 73 | "101111011110", 74 | "110000001001", 75 | "110000110011", 76 | "110001011100", 77 | "110010000100", 78 | "110010101011", 79 | "110011010010", 80 | "110011111000", 81 | "110100011101", 82 | "110101000001", 83 | "110101100101" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_cos is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111111111111", 21 | "111111111110", 22 | "111111111100", 23 | "111111111001", 24 | "111111110101", 25 | "111111110000", 26 | "111111101010", 27 | "111111100011", 28 | "111111011011", 29 | "111111010010", 30 | "111111001000", 31 | "111110111110", 32 | "111110110010", 33 | "111110100101", 34 | "111110010111", 35 | "111110001000", 36 | "111101111000", 37 | "111101100111", 38 | "111101010110", 39 | "111101000011", 40 | "111100101111", 41 | "111100011011", 42 | "111100000101", 43 | "111011101110", 44 | "111011010111", 45 | "111010111111", 46 | "111010100101", 47 | "111010001011", 48 | "111001110000", 49 | "111001010100", 50 | "111000110111", 51 | "111000011001", 52 | "110111111011", 53 | "110111011011", 54 | "110110111011", 55 | "110110011001", 56 | "110101110111", 57 | "110101010100", 58 | "110100110000", 59 | "110100001100", 60 | "110011100110", 61 | "110011000000", 62 | "110010011001", 63 | "110001110001", 64 | "110001001001", 65 | "110000011111", 66 | "101111110101", 67 | "101111001010", 68 | "101110011111", 69 | "101101110010", 70 | "101101000101", 71 | "101100010111", 72 | "101011101001", 73 | "101010111010", 74 | "101010001010", 75 | "101001011001", 76 | "101000101000", 77 | "100111110111", 78 | "100111000100", 79 | "100110010001", 80 | "100101011110", 81 | "100100101001", 82 | "100011110101", 83 | "100010111111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_exp is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "011110111000", 21 | "011111010000", 22 | "011111100100", 23 | "011111111000", 24 | "100000010000", 25 | "100000101000", 26 | "100000111100", 27 | "100001010100", 28 | "100001101100", 29 | "100010000100", 30 | "100010011100", 31 | "100010110100", 32 | "100011001100", 33 | "100011100100", 34 | "100011111100", 35 | "100100010100", 36 | "100100110000", 37 | "100101001000", 38 | "100101100100", 39 | "100101111100", 40 | "100110011000", 41 | "100110110000", 42 | "100111001100", 43 | "100111101000", 44 | "101000000100", 45 | "101000100000", 46 | "101000111100", 47 | "101001011000", 48 | "101001110100", 49 | "101010010100", 50 | "101010110000", 51 | "101011010000", 52 | "101011101100", 53 | "101100001100", 54 | "101100101000", 55 | "101101001000", 56 | "101101101000", 57 | "101110001000", 58 | "101110101000", 59 | "101111001000", 60 | "101111101000", 61 | "110000001100", 62 | "110000101100", 63 | "110001010000", 64 | "110001110000", 65 | "110010010100", 66 | "110010111000", 67 | "110011011000", 68 | "110011111100", 69 | "110100100000", 70 | "110101001000", 71 | "110101101100", 72 | "110110010000", 73 | "110110111000", 74 | "110111011100", 75 | "111000000100", 76 | "111000101100", 77 | "111001010100", 78 | "111001111100", 79 | "111010100100", 80 | "111011001100", 81 | "111011110100", 82 | "111100100000", 83 | "111101001000" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sin is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000011111", 21 | "000001011111", 22 | "000010011111", 23 | "000011011111", 24 | "000100011111", 25 | "000101011111", 26 | "000110011111", 27 | "000111011110", 28 | "001000011110", 29 | "001001011101", 30 | "001010011100", 31 | "001011011100", 32 | "001100011010", 33 | "001101011001", 34 | "001110011000", 35 | "001111010110", 36 | "010000010100", 37 | "010001010010", 38 | "010010001111", 39 | "010011001100", 40 | "010100001001", 41 | "010101000110", 42 | "010110000010", 43 | "010110111110", 44 | "010111111001", 45 | "011000110101", 46 | "011001101111", 47 | "011010101010", 48 | "011011100100", 49 | "011100011101", 50 | "011101010110", 51 | "011110001111", 52 | "011111000111", 53 | "011111111111", 54 | "100000110110", 55 | "100001101101", 56 | "100010100011", 57 | "100011011000", 58 | "100100001110", 59 | "100101000010", 60 | "100101110110", 61 | "100110101001", 62 | "100111011100", 63 | "101000001110", 64 | "101000111111", 65 | "101001110000", 66 | "101010100000", 67 | "101011010000", 68 | "101011111111", 69 | "101100101101", 70 | "101101011010", 71 | "101110000111", 72 | "101110110011", 73 | "101111011110", 74 | "110000001001", 75 | "110000110011", 76 | "110001011100", 77 | "110010000100", 78 | "110010101011", 79 | "110011010010", 80 | "110011111000", 81 | "110100011101", 82 | "110101000001", 83 | "110101100101" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_cos is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111111111111", 21 | "111111111110", 22 | "111111111100", 23 | "111111111001", 24 | "111111110101", 25 | "111111110000", 26 | "111111101010", 27 | "111111100011", 28 | "111111011011", 29 | "111111010010", 30 | "111111001000", 31 | "111110111110", 32 | "111110110010", 33 | "111110100101", 34 | "111110010111", 35 | "111110001000", 36 | "111101111000", 37 | "111101100111", 38 | "111101010110", 39 | "111101000011", 40 | "111100101111", 41 | "111100011011", 42 | "111100000101", 43 | "111011101110", 44 | "111011010111", 45 | "111010111111", 46 | "111010100101", 47 | "111010001011", 48 | "111001110000", 49 | "111001010100", 50 | "111000110111", 51 | "111000011001", 52 | "110111111011", 53 | "110111011011", 54 | "110110111011", 55 | "110110011001", 56 | "110101110111", 57 | "110101010100", 58 | "110100110000", 59 | "110100001100", 60 | "110011100110", 61 | "110011000000", 62 | "110010011001", 63 | "110001110001", 64 | "110001001001", 65 | "110000011111", 66 | "101111110101", 67 | "101111001010", 68 | "101110011111", 69 | "101101110010", 70 | "101101000101", 71 | "101100010111", 72 | "101011101001", 73 | "101010111010", 74 | "101010001010", 75 | "101001011001", 76 | "101000101000", 77 | "100111110111", 78 | "100111000100", 79 | "100110010001", 80 | "100101011110", 81 | "100100101001", 82 | "100011110101", 83 | "100010111111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_exp is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "011110111000", 21 | "011111010000", 22 | "011111100100", 23 | "011111111000", 24 | "100000010000", 25 | "100000101000", 26 | "100000111100", 27 | "100001010100", 28 | "100001101100", 29 | "100010000100", 30 | "100010011100", 31 | "100010110100", 32 | "100011001100", 33 | "100011100100", 34 | "100011111100", 35 | "100100010100", 36 | "100100110000", 37 | "100101001000", 38 | "100101100100", 39 | "100101111100", 40 | "100110011000", 41 | "100110110000", 42 | "100111001100", 43 | "100111101000", 44 | "101000000100", 45 | "101000100000", 46 | "101000111100", 47 | "101001011000", 48 | "101001110100", 49 | "101010010100", 50 | "101010110000", 51 | "101011010000", 52 | "101011101100", 53 | "101100001100", 54 | "101100101000", 55 | "101101001000", 56 | "101101101000", 57 | "101110001000", 58 | "101110101000", 59 | "101111001000", 60 | "101111101000", 61 | "110000001100", 62 | "110000101100", 63 | "110001010000", 64 | "110001110000", 65 | "110010010100", 66 | "110010111000", 67 | "110011011000", 68 | "110011111100", 69 | "110100100000", 70 | "110101001000", 71 | "110101101100", 72 | "110110010000", 73 | "110110111000", 74 | "110111011100", 75 | "111000000100", 76 | "111000101100", 77 | "111001010100", 78 | "111001111100", 79 | "111010100100", 80 | "111011001100", 81 | "111011110100", 82 | "111100100000", 83 | "111101001000" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sin is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000011111", 21 | "000001011111", 22 | "000010011111", 23 | "000011011111", 24 | "000100011111", 25 | "000101011111", 26 | "000110011111", 27 | "000111011110", 28 | "001000011110", 29 | "001001011101", 30 | "001010011100", 31 | "001011011100", 32 | "001100011010", 33 | "001101011001", 34 | "001110011000", 35 | "001111010110", 36 | "010000010100", 37 | "010001010010", 38 | "010010001111", 39 | "010011001100", 40 | "010100001001", 41 | "010101000110", 42 | "010110000010", 43 | "010110111110", 44 | "010111111001", 45 | "011000110101", 46 | "011001101111", 47 | "011010101010", 48 | "011011100100", 49 | "011100011101", 50 | "011101010110", 51 | "011110001111", 52 | "011111000111", 53 | "011111111111", 54 | "100000110110", 55 | "100001101101", 56 | "100010100011", 57 | "100011011000", 58 | "100100001110", 59 | "100101000010", 60 | "100101110110", 61 | "100110101001", 62 | "100111011100", 63 | "101000001110", 64 | "101000111111", 65 | "101001110000", 66 | "101010100000", 67 | "101011010000", 68 | "101011111111", 69 | "101100101101", 70 | "101101011010", 71 | "101110000111", 72 | "101110110011", 73 | "101111011110", 74 | "110000001001", 75 | "110000110011", 76 | "110001011100", 77 | "110010000100", 78 | "110010101011", 79 | "110011010010", 80 | "110011111000", 81 | "110100011101", 82 | "110101000001", 83 | "110101100101" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_cos is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111111111111", 21 | "111111111110", 22 | "111111111100", 23 | "111111111001", 24 | "111111110101", 25 | "111111110000", 26 | "111111101010", 27 | "111111100011", 28 | "111111011011", 29 | "111111010010", 30 | "111111001000", 31 | "111110111110", 32 | "111110110010", 33 | "111110100101", 34 | "111110010111", 35 | "111110001000", 36 | "111101111000", 37 | "111101100111", 38 | "111101010110", 39 | "111101000011", 40 | "111100101111", 41 | "111100011011", 42 | "111100000101", 43 | "111011101110", 44 | "111011010111", 45 | "111010111111", 46 | "111010100101", 47 | "111010001011", 48 | "111001110000", 49 | "111001010100", 50 | "111000110111", 51 | "111000011001", 52 | "110111111011", 53 | "110111011011", 54 | "110110111011", 55 | "110110011001", 56 | "110101110111", 57 | "110101010100", 58 | "110100110000", 59 | "110100001100", 60 | "110011100110", 61 | "110011000000", 62 | "110010011001", 63 | "110001110001", 64 | "110001001001", 65 | "110000011111", 66 | "101111110101", 67 | "101111001010", 68 | "101110011111", 69 | "101101110010", 70 | "101101000101", 71 | "101100010111", 72 | "101011101001", 73 | "101010111010", 74 | "101010001010", 75 | "101001011001", 76 | "101000101000", 77 | "100111110111", 78 | "100111000100", 79 | "100110010001", 80 | "100101011110", 81 | "100100101001", 82 | "100011110101", 83 | "100010111111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_exp is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "011110111000", 21 | "011111010000", 22 | "011111100100", 23 | "011111111000", 24 | "100000010000", 25 | "100000101000", 26 | "100000111100", 27 | "100001010100", 28 | "100001101100", 29 | "100010000100", 30 | "100010011100", 31 | "100010110100", 32 | "100011001100", 33 | "100011100100", 34 | "100011111100", 35 | "100100010100", 36 | "100100110000", 37 | "100101001000", 38 | "100101100100", 39 | "100101111100", 40 | "100110011000", 41 | "100110110000", 42 | "100111001100", 43 | "100111101000", 44 | "101000000100", 45 | "101000100000", 46 | "101000111100", 47 | "101001011000", 48 | "101001110100", 49 | "101010010100", 50 | "101010110000", 51 | "101011010000", 52 | "101011101100", 53 | "101100001100", 54 | "101100101000", 55 | "101101001000", 56 | "101101101000", 57 | "101110001000", 58 | "101110101000", 59 | "101111001000", 60 | "101111101000", 61 | "110000001100", 62 | "110000101100", 63 | "110001010000", 64 | "110001110000", 65 | "110010010100", 66 | "110010111000", 67 | "110011011000", 68 | "110011111100", 69 | "110100100000", 70 | "110101001000", 71 | "110101101100", 72 | "110110010000", 73 | "110110111000", 74 | "110111011100", 75 | "111000000100", 76 | "111000101100", 77 | "111001010100", 78 | "111001111100", 79 | "111010100100", 80 | "111011001100", 81 | "111011110100", 82 | "111100100000", 83 | "111101001000" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_sin is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000011111", 21 | "000001011111", 22 | "000010011111", 23 | "000011011111", 24 | "000100011111", 25 | "000101011111", 26 | "000110011111", 27 | "000111011110", 28 | "001000011110", 29 | "001001011101", 30 | "001010011100", 31 | "001011011100", 32 | "001100011010", 33 | "001101011001", 34 | "001110011000", 35 | "001111010110", 36 | "010000010100", 37 | "010001010010", 38 | "010010001111", 39 | "010011001100", 40 | "010100001001", 41 | "010101000110", 42 | "010110000010", 43 | "010110111110", 44 | "010111111001", 45 | "011000110101", 46 | "011001101111", 47 | "011010101010", 48 | "011011100100", 49 | "011100011101", 50 | "011101010110", 51 | "011110001111", 52 | "011111000111", 53 | "011111111111", 54 | "100000110110", 55 | "100001101101", 56 | "100010100011", 57 | "100011011000", 58 | "100100001110", 59 | "100101000010", 60 | "100101110110", 61 | "100110101001", 62 | "100111011100", 63 | "101000001110", 64 | "101000111111", 65 | "101001110000", 66 | "101010100000", 67 | "101011010000", 68 | "101011111111", 69 | "101100101101", 70 | "101101011010", 71 | "101110000111", 72 | "101110110011", 73 | "101111011110", 74 | "110000001001", 75 | "110000110011", 76 | "110001011100", 77 | "110010000100", 78 | "110010101011", 79 | "110011010010", 80 | "110011111000", 81 | "110100011101", 82 | "110101000001", 83 | "110101100101" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_ln2e0 is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111100011000", 21 | "111010011000", 22 | "111000011000", 23 | "110110100000", 24 | "110100110000", 25 | "110011000000", 26 | "110001011000", 27 | "101111111000", 28 | "101110011000", 29 | "101101000000", 30 | "101011101000", 31 | "101010011000", 32 | "101001001000", 33 | "100111111000", 34 | "100110110000", 35 | "100101101000", 36 | "100100101000", 37 | "100011100000", 38 | "100010101000", 39 | "100001101000", 40 | "100000110000", 41 | "011111111000", 42 | "011111000000", 43 | "011110010000", 44 | "011101100000", 45 | "011100110000", 46 | "011100000000", 47 | "011011010000", 48 | "011010101000", 49 | "011010000000", 50 | "011001011000", 51 | "011000110000", 52 | "011000001000", 53 | "010111101000", 54 | "010111000000", 55 | "010110100000", 56 | "010110000000", 57 | "010101100000", 58 | "010101000000", 59 | "010100100000", 60 | "010100001000", 61 | "010011101000", 62 | "010011010000", 63 | "010010110000", 64 | "010010011000", 65 | "010010000000", 66 | "010001101000", 67 | "010001010000", 68 | "010000111000", 69 | "010000101000", 70 | "010000010000", 71 | "001111111000", 72 | "001111101000", 73 | "001111010000", 74 | "001111000000", 75 | "001110110000", 76 | "001110011000", 77 | "001110001000", 78 | "001101111000", 79 | "001101101000", 80 | "001101011000", 81 | "001101001000", 82 | "001100111000", 83 | "001100101000" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_ln2e0 is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111100011000", 21 | "111010011000", 22 | "111000011000", 23 | "110110100000", 24 | "110100110000", 25 | "110011000000", 26 | "110001011000", 27 | "101111111000", 28 | "101110011000", 29 | "101101000000", 30 | "101011101000", 31 | "101010011000", 32 | "101001001000", 33 | "100111111000", 34 | "100110110000", 35 | "100101101000", 36 | "100100101000", 37 | "100011100000", 38 | "100010101000", 39 | "100001101000", 40 | "100000110000", 41 | "011111111000", 42 | "011111000000", 43 | "011110010000", 44 | "011101100000", 45 | "011100110000", 46 | "011100000000", 47 | "011011010000", 48 | "011010101000", 49 | "011010000000", 50 | "011001011000", 51 | "011000110000", 52 | "011000001000", 53 | "010111101000", 54 | "010111000000", 55 | "010110100000", 56 | "010110000000", 57 | "010101100000", 58 | "010101000000", 59 | "010100100000", 60 | "010100001000", 61 | "010011101000", 62 | "010011010000", 63 | "010010110000", 64 | "010010011000", 65 | "010010000000", 66 | "010001101000", 67 | "010001010000", 68 | "010000111000", 69 | "010000101000", 70 | "010000010000", 71 | "001111111000", 72 | "001111101000", 73 | "001111010000", 74 | "001111000000", 75 | "001110110000", 76 | "001110011000", 77 | "001110001000", 78 | "001101111000", 79 | "001101101000", 80 | "001101011000", 81 | "001101001000", 82 | "001100111000", 83 | "001100101000" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C2_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C2_ln2e0 is 6 | generic( 7 | word_bits :natural:=12; 8 | bus_bits :natural:=14; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C2_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "111100011000", 21 | "111010011000", 22 | "111000011000", 23 | "110110100000", 24 | "110100110000", 25 | "110011000000", 26 | "110001011000", 27 | "101111111000", 28 | "101110011000", 29 | "101101000000", 30 | "101011101000", 31 | "101010011000", 32 | "101001001000", 33 | "100111111000", 34 | "100110110000", 35 | "100101101000", 36 | "100100101000", 37 | "100011100000", 38 | "100010101000", 39 | "100001101000", 40 | "100000110000", 41 | "011111111000", 42 | "011111000000", 43 | "011110010000", 44 | "011101100000", 45 | "011100110000", 46 | "011100000000", 47 | "011011010000", 48 | "011010101000", 49 | "011010000000", 50 | "011001011000", 51 | "011000110000", 52 | "011000001000", 53 | "010111101000", 54 | "010111000000", 55 | "010110100000", 56 | "010110000000", 57 | "010101100000", 58 | "010101000000", 59 | "010100100000", 60 | "010100001000", 61 | "010011101000", 62 | "010011010000", 63 | "010010110000", 64 | "010010011000", 65 | "010010000000", 66 | "010001101000", 67 | "010001010000", 68 | "010000111000", 69 | "010000101000", 70 | "010000010000", 71 | "001111111000", 72 | "001111101000", 73 | "001111010000", 74 | "001111000000", 75 | "001110110000", 76 | "001110011000", 77 | "001110001000", 78 | "001101111000", 79 | "001101101000", 80 | "001101011000", 81 | "001101001000", 82 | "001100111000", 83 | "001100101000" 84 | ); 85 | begin 86 | data <= "00"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=13; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111111111111", 21 | "1111110000001", 22 | "1111100000101", 23 | "1111010001100", 24 | "1111000010110", 25 | "1110110100010", 26 | "1110100110001", 27 | "1110011000011", 28 | "1110001010110", 29 | "1101111101100", 30 | "1101110000100", 31 | "1101100011110", 32 | "1101010111010", 33 | "1101001011000", 34 | "1100111111000", 35 | "1100110011010", 36 | "1100100111110", 37 | "1100011100011", 38 | "1100010001010", 39 | "1100000110010", 40 | "1011111011100", 41 | "1011110001000", 42 | "1011100110101", 43 | "1011011100100", 44 | "1011010010100", 45 | "1011001000101", 46 | "1010111111000", 47 | "1010110101011", 48 | "1010101100001", 49 | "1010100010111", 50 | "1010011001110", 51 | "1010010000111", 52 | "1010001000001", 53 | "1001111111100", 54 | "1001110111000", 55 | "1001101110101", 56 | "1001100110011", 57 | "1001011110010", 58 | "1001010110001", 59 | "1001001110010", 60 | "1001000110100", 61 | "1000111110111", 62 | "1000110111010", 63 | "1000101111111", 64 | "1000101000100", 65 | "1000100001010", 66 | "1000011010001", 67 | "1000010011000", 68 | "1000001100001", 69 | "1000000101010", 70 | "0111111110011", 71 | "0111110111110", 72 | "0111110001001", 73 | "0111101010101", 74 | "0111100100010", 75 | "0111011101111", 76 | "0111010111101", 77 | "0111010001011", 78 | "0111001011010", 79 | "0111000101010", 80 | "0110111111010", 81 | "0110111001011", 82 | "0110110011100", 83 | "0110101101110" 84 | ); 85 | begin 86 | data <= "0001"&rom(to_integer(unsigned(addr)))&"000"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=13; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1101010000010", 21 | "1100111001111", 22 | "1100100100000", 23 | "1100001110101", 24 | "1011111001110", 25 | "1011100101010", 26 | "1011010001010", 27 | "1010111101110", 28 | "1010101010101", 29 | "1010010111110", 30 | "1010000101011", 31 | "1001110011011", 32 | "1001100001110", 33 | "1001010000011", 34 | "1000111111100", 35 | "1000101110110", 36 | "1000011110100", 37 | "1000001110011", 38 | "0111111110101", 39 | "0111101111010", 40 | "0111100000000", 41 | "0111010001001", 42 | "0111000010100", 43 | "0110110100000", 44 | "0110100101111", 45 | "0110011000000", 46 | "0110001010010", 47 | "0101111100111", 48 | "0101101111101", 49 | "0101100010101", 50 | "0101010101110", 51 | "0101001001001", 52 | "0100111100110", 53 | "0100110000100", 54 | "0100100100100", 55 | "0100011000101", 56 | "0100001101000", 57 | "0100000001100", 58 | "0011110110001", 59 | "0011101011000", 60 | "0011100000000", 61 | "0011010101001", 62 | "0011001010100", 63 | "0010111111111", 64 | "0010110101100", 65 | "0010101011010", 66 | "0010100001001", 67 | "0010010111001", 68 | "0010001101011", 69 | "0010000011101", 70 | "0001111010000", 71 | "0001110000101", 72 | "0001100111010", 73 | "0001011110000", 74 | "0001010101000", 75 | "0001001100000", 76 | "0001000011001", 77 | "0000111010011", 78 | "0000110001101", 79 | "0000101001001", 80 | "0000100000110", 81 | "0000011000011", 82 | "0000010000001", 83 | "0000001000000" 84 | ); 85 | begin 86 | data <= "0010"&rom(to_integer(unsigned(addr)))&"000"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/Verification/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | 4 | radix define iee754s_fp -float -fraction 23 -base decimal -precision 10 5 | 6 | set SFUS 1 7 | 8 | add wave -noupdate -label CLK /sfu_tb/s_clk_i 9 | add wave -noupdate -label DATA_IN -radix hexadecimal /sfu_tb/s_src1_i 10 | add wave -noupdate -label DATA_RRO -radix hexadecimal /sfu_tb/s_sfu_input 11 | add wave -noupdate -label OPER /sfu_tb/s_selop_i 12 | add wave -noupdate -label RESULT -radix hexadecimal /sfu_tb/s_Result_o 13 | add wave -noupdate -label ErrTMR /sfu_tb/s_Quad_int_err 14 | 15 | add wave -noupdate -group SFU_PROC /sfu_tb/DUT/* 16 | 17 | 18 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/uQuadraticInterpol_1/* 19 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/uQuadraticInterpol_2/* 20 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/uQuadraticInterpol_3/* 21 | 22 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol_1/u_SpecialSquaringUnit/* 23 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol_2/u_SpecialSquaringUnit/* 24 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/uQuadraticInterpol_3/u_SpecialSquaringUnit/* 25 | 26 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol_1/uFusedAccTree/* 27 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol_2/uFusedAccTree/* 28 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/uQuadraticInterpol_3/uFusedAccTree/* 29 | 30 | add wave -noupdate -group Test_Bench_Signals /sfu_tb/* 31 | 32 | TreeUpdate [SetDefaultTree] 33 | WaveRestoreCursors {{Cursor 1} {80000 ps} 0} 34 | quietly wave cursor active 1 35 | configure wave -namecolwidth 76 36 | configure wave -valuecolwidth 49 37 | configure wave -justifyvalue left 38 | configure wave -signalnamewidth 0 39 | configure wave -snapdistance 10 40 | configure wave -datasetprefix 0 41 | configure wave -rowmargin 4 42 | configure wave -childrowmargin 2 43 | configure wave -gridoffset 0 44 | configure wave -gridperiod 1 45 | configure wave -griddelta 40 46 | configure wave -timeline 0 47 | configure wave -timelineunits ns 48 | update 49 | WaveRestoreZoom {0 ps} {180 ns} 50 | -------------------------------------------------------------------------------- /Golden model/getLUT.m: -------------------------------------------------------------------------------- 1 | function [LUTout,concat,sign] = getLUT(LUTin,constants,s) 2 | 3 | concat = ''; 4 | 5 | % Generate the bit of sign (0 for +;1 for -) 6 | % All the constants in a look-up-table have the same sign 7 | if s == 1 8 | if constants(2,1) > 0 9 | sign = 0; 10 | else 11 | sign = 1; 12 | end 13 | end 14 | 15 | % Remove the dot 16 | id = strfind(LUTin(1,:),"."); 17 | LUTin(:,id)=[]; 18 | 19 | while(1) 20 | for j=1:size(LUTin,2) 21 | aux = LUTin(1,j); % Save the first bit 22 | bool = 1; % Establish a condition 23 | for i=1:size(LUTin,1) 24 | if LUTin(i,j) ~= aux % Compare the bits of the all columns 25 | bool = 0; % If they are different, the condition changes 26 | endif 27 | endfor 28 | if bool == 1 % If confdition does not change, the bits can be concatenated 29 | concat = strcat(concat,LUTin(1:j)); % Save the bit to concatenate 30 | LUTin(:,j)=[]; % Remove the bit from the look-up-table 31 | break 32 | endif 33 | end 34 | 35 | if bool == 0 % If all the bits in a column are not equal, break the loop 36 | break 37 | endif 38 | end 39 | 40 | % Remove first 0 41 | cond = 0; 42 | for i=1:size(concat,2) 43 | if concat(i)=="1" 44 | cond = 1; 45 | break 46 | endif 47 | endfor 48 | 49 | if cond == 1 50 | while(1) 51 | bool = 1; 52 | for i=1:size(concat,2) 53 | if concat(i) == '0' 54 | concat(i) = []; 55 | break 56 | else 57 | bool = 0; 58 | break 59 | end 60 | end 61 | 62 | if bool == 0 63 | break 64 | end 65 | end 66 | else 67 | concat = []; 68 | end 69 | 70 | LUTout = LUTin; 71 | end -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_ln2e0 is 6 | generic( 7 | word_bits :natural:=15; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "101110001010011", 21 | "101101001101111", 22 | "101100010011100", 23 | "101011011011000", 24 | "101010100100011", 25 | "101001101111101", 26 | "101000111100100", 27 | "101000001011000", 28 | "100111011011001", 29 | "100110101100101", 30 | "100101111111101", 31 | "100101010011111", 32 | "100100101001100", 33 | "100100000000011", 34 | "100011011000100", 35 | "100010110001110", 36 | "100010001100000", 37 | "100001100111011", 38 | "100001000011110", 39 | "100000100001001", 40 | "011111111111100", 41 | "011111011110101", 42 | "011110111110110", 43 | "011110011111101", 44 | "011110000001011", 45 | "011101100011111", 46 | "011101000111001", 47 | "011100101011001", 48 | "011100001111110", 49 | "011011110101000", 50 | "011011011011000", 51 | "011011000001101", 52 | "011010101000111", 53 | "011010010000101", 54 | "011001111001000", 55 | "011001100010000", 56 | "011001001011011", 57 | "011000110101011", 58 | "011000011111111", 59 | "011000001010110", 60 | "010111110110001", 61 | "010111100010000", 62 | "010111001110011", 63 | "010110111011000", 64 | "010110101000001", 65 | "010110010101110", 66 | "010110000011101", 67 | "010101110001111", 68 | "010101100000101", 69 | "010101001111101", 70 | "010100111111000", 71 | "010100101110101", 72 | "010100011110101", 73 | "010100001111000", 74 | "010011111111101", 75 | "010011110000101", 76 | "010011100001111", 77 | "010011010011011", 78 | "010011000101001", 79 | "010010110111010", 80 | "010010101001100", 81 | "010010011100001", 82 | "010010001110111", 83 | "010010000010000" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr)))&"000"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/sfu.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------------------------------- 2 | -- Proyecto : SFU IEEE754 3 | -- Nombre de archivo : SFU.vhd 4 | -- Titulo : Special Function Unit 5 | ----------------------------------------------------------------------------- 6 | -- Descripcion : This unit performs the floating point operations 7 | -- sin(x), cos(x), rsqrt(x), log2(x), exp2(x), 1/x, and sqrt(x), using 8 | -- IEE754 standard and operational compliant with GPU G80 9 | -- architecture 10 | ----------------------------------------------------------------------------- 11 | -- Universidad Pedagogica y Tecnologica de Colombia 12 | -- Facultad de Ingeniería 13 | -- Escuela de Ingenieria Electronica - Extension Tunja 14 | -- 15 | -- Autor: Juan David Guerrero Balaguera; Edwar Javier Patiño Núñez 16 | -- October 2020 17 | ----------------------------------------------------------------------------- 18 | 19 | library ieee; 20 | use ieee.std_logic_1164.all; 21 | use ieee.numeric_std.all; 22 | 23 | entity sfu is 24 | port( 25 | src1_i :in std_logic_vector(31 downto 0); -- IEE754 input data 26 | selop_i :in std_logic_vector(2 downto 0); -- Operation selection 27 | Result_o :out std_logic_vector(31 downto 0); -- IEE754 result data output 28 | error :out std_logic 29 | ); 30 | end entity; 31 | 32 | architecture behav of sfu is 33 | signal s_Result_o_1 :std_logic_vector(31 downto 0); 34 | signal s_Result_o_2 :std_logic_vector(31 downto 0); 35 | signal s_Result_o_3 :std_logic_vector(31 downto 0); 36 | begin 37 | DUT01: entity work.sfu_components 38 | port map( 39 | src1_i => src1_i, 40 | selop_i => selop_i, 41 | Result_o => s_Result_o_1); 42 | 43 | DUT02: entity work.sfu_components 44 | port map( 45 | src1_i => src1_i, 46 | selop_i => selop_i, 47 | Result_o => s_Result_o_2); 48 | 49 | DUT03: entity work.sfu_components 50 | port map( 51 | src1_i => src1_i, 52 | selop_i => selop_i, 53 | Result_o => s_Result_o_3); 54 | 55 | voter_sfu:entity work.voter 56 | generic map( 57 | word_bits => 32 58 | ) 59 | port map( 60 | z1 => s_Result_o_1, 61 | z2 => s_Result_o_2, 62 | z3 => s_Result_o_3, 63 | z => Result_o, 64 | error => error 65 | ); 66 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_exp is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0101100010111000", 21 | "0101100110110000", 22 | "0101101010101010", 23 | "0101101110100110", 24 | "0101110010100110", 25 | "0101110110101000", 26 | "0101111010101101", 27 | "0101111110110101", 28 | "0110000011000000", 29 | "0110000111001110", 30 | "0110001011011110", 31 | "0110001111110010", 32 | "0110010100001001", 33 | "0110011000100010", 34 | "0110011100111111", 35 | "0110100001011111", 36 | "0110100110000010", 37 | "0110101010101000", 38 | "0110101111010001", 39 | "0110110011111110", 40 | "0110111000101110", 41 | "0110111101100001", 42 | "0111000010010111", 43 | "0111000111010001", 44 | "0111001100001110", 45 | "0111010001001111", 46 | "0111010110010011", 47 | "0111011011011011", 48 | "0111100000100110", 49 | "0111100101110101", 50 | "0111101011001000", 51 | "0111110000011110", 52 | "0111110101111000", 53 | "0111111011010110", 54 | "1000000000111000", 55 | "1000000110011101", 56 | "1000001100000110", 57 | "1000010001110100", 58 | "1000010111100101", 59 | "1000011101011010", 60 | "1000100011010011", 61 | "1000101001010001", 62 | "1000101111010010", 63 | "1000110101011000", 64 | "1000111011100010", 65 | "1001000001110001", 66 | "1001001000000011", 67 | "1001001110011010", 68 | "1001010100110110", 69 | "1001011011010110", 70 | "1001100001111010", 71 | "1001101000100011", 72 | "1001101111010001", 73 | "1001110110000011", 74 | "1001111100111010", 75 | "1010000011110110", 76 | "1010001010110111", 77 | "1010010001111101", 78 | "1010011001000111", 79 | "1010100000010111", 80 | "1010100111101011", 81 | "1010101111000101", 82 | "1010110110100100", 83 | "1010111110001000" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr)))&"000"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111111111111000", 21 | "1111110000001000", 22 | "1111100000101000", 23 | "1111010001100000", 24 | "1111000010110000", 25 | "1110110100010000", 26 | "1110100110001000", 27 | "1110011000011000", 28 | "1110001010110000", 29 | "1101111101100000", 30 | "1101110000100000", 31 | "1101100011110000", 32 | "1101010111010000", 33 | "1101001011000000", 34 | "1100111111000000", 35 | "1100110011010000", 36 | "1100100111110000", 37 | "1100011100011000", 38 | "1100010001010000", 39 | "1100000110010000", 40 | "1011111011100000", 41 | "1011110001000000", 42 | "1011100110101000", 43 | "1011011100100000", 44 | "1011010010100000", 45 | "1011001000101000", 46 | "1010111111000000", 47 | "1010110101011000", 48 | "1010101100001000", 49 | "1010100010111000", 50 | "1010011001110000", 51 | "1010010000111000", 52 | "1010001000001000", 53 | "1001111111100000", 54 | "1001110111000000", 55 | "1001101110101000", 56 | "1001100110011000", 57 | "1001011110010000", 58 | "1001010110001000", 59 | "1001001110010000", 60 | "1001000110100000", 61 | "1000111110111000", 62 | "1000110111010000", 63 | "1000101111111000", 64 | "1000101000100000", 65 | "1000100001010000", 66 | "1000011010001000", 67 | "1000010011000000", 68 | "1000001100001000", 69 | "1000000101010000", 70 | "0111111110011000", 71 | "0111110111110000", 72 | "0111110001001000", 73 | "0111101010101000", 74 | "0111100100010000", 75 | "0111011101111000", 76 | "0111010111101000", 77 | "0111010001011000", 78 | "0111001011010000", 79 | "0111000101010000", 80 | "0110111111010000", 81 | "0110111001011000", 82 | "0110110011100000", 83 | "0110101101110000" 84 | ); 85 | begin 86 | data <= "0001"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1101010000010000", 21 | "1100111001111000", 22 | "1100100100000000", 23 | "1100001110101000", 24 | "1011111001110000", 25 | "1011100101010000", 26 | "1011010001010000", 27 | "1010111101110000", 28 | "1010101010101000", 29 | "1010010111110000", 30 | "1010000101011000", 31 | "1001110011011000", 32 | "1001100001110000", 33 | "1001010000011000", 34 | "1000111111100000", 35 | "1000101110110000", 36 | "1000011110100000", 37 | "1000001110011000", 38 | "0111111110101000", 39 | "0111101111010000", 40 | "0111100000000000", 41 | "0111010001001000", 42 | "0111000010100000", 43 | "0110110100000000", 44 | "0110100101111000", 45 | "0110011000000000", 46 | "0110001010010000", 47 | "0101111100111000", 48 | "0101101111101000", 49 | "0101100010101000", 50 | "0101010101110000", 51 | "0101001001001000", 52 | "0100111100110000", 53 | "0100110000100000", 54 | "0100100100100000", 55 | "0100011000101000", 56 | "0100001101000000", 57 | "0100000001100000", 58 | "0011110110001000", 59 | "0011101011000000", 60 | "0011100000000000", 61 | "0011010101001000", 62 | "0011001010100000", 63 | "0010111111111000", 64 | "0010110101100000", 65 | "0010101011010000", 66 | "0010100001001000", 67 | "0010010111001000", 68 | "0010001101011000", 69 | "0010000011101000", 70 | "0001111010000000", 71 | "0001110000101000", 72 | "0001100111010000", 73 | "0001011110000000", 74 | "0001010101000000", 75 | "0001001100000000", 76 | "0001000011001000", 77 | "0000111010011000", 78 | "0000110001101000", 79 | "0000101001001000", 80 | "0000100000110000", 81 | "0000011000011000", 82 | "0000010000001000", 83 | "0000001000000000" 84 | ); 85 | begin 86 | data <= "0010"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111111111111000", 21 | "1111110000001000", 22 | "1111100000101000", 23 | "1111010001100000", 24 | "1111000010110000", 25 | "1110110100010000", 26 | "1110100110001000", 27 | "1110011000011000", 28 | "1110001010110000", 29 | "1101111101100000", 30 | "1101110000100000", 31 | "1101100011110000", 32 | "1101010111010000", 33 | "1101001011000000", 34 | "1100111111000000", 35 | "1100110011010000", 36 | "1100100111110000", 37 | "1100011100011000", 38 | "1100010001010000", 39 | "1100000110010000", 40 | "1011111011100000", 41 | "1011110001000000", 42 | "1011100110101000", 43 | "1011011100100000", 44 | "1011010010100000", 45 | "1011001000101000", 46 | "1010111111000000", 47 | "1010110101011000", 48 | "1010101100001000", 49 | "1010100010111000", 50 | "1010011001110000", 51 | "1010010000111000", 52 | "1010001000001000", 53 | "1001111111100000", 54 | "1001110111000000", 55 | "1001101110101000", 56 | "1001100110011000", 57 | "1001011110010000", 58 | "1001010110001000", 59 | "1001001110010000", 60 | "1001000110100000", 61 | "1000111110111000", 62 | "1000110111010000", 63 | "1000101111111000", 64 | "1000101000100000", 65 | "1000100001010000", 66 | "1000011010001000", 67 | "1000010011000000", 68 | "1000001100001000", 69 | "1000000101010000", 70 | "0111111110011000", 71 | "0111110111110000", 72 | "0111110001001000", 73 | "0111101010101000", 74 | "0111100100010000", 75 | "0111011101111000", 76 | "0111010111101000", 77 | "0111010001011000", 78 | "0111001011010000", 79 | "0111000101010000", 80 | "0110111111010000", 81 | "0110111001011000", 82 | "0110110011100000", 83 | "0110101101110000" 84 | ); 85 | begin 86 | data <= "0001"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1101010000010000", 21 | "1100111001111000", 22 | "1100100100000000", 23 | "1100001110101000", 24 | "1011111001110000", 25 | "1011100101010000", 26 | "1011010001010000", 27 | "1010111101110000", 28 | "1010101010101000", 29 | "1010010111110000", 30 | "1010000101011000", 31 | "1001110011011000", 32 | "1001100001110000", 33 | "1001010000011000", 34 | "1000111111100000", 35 | "1000101110110000", 36 | "1000011110100000", 37 | "1000001110011000", 38 | "0111111110101000", 39 | "0111101111010000", 40 | "0111100000000000", 41 | "0111010001001000", 42 | "0111000010100000", 43 | "0110110100000000", 44 | "0110100101111000", 45 | "0110011000000000", 46 | "0110001010010000", 47 | "0101111100111000", 48 | "0101101111101000", 49 | "0101100010101000", 50 | "0101010101110000", 51 | "0101001001001000", 52 | "0100111100110000", 53 | "0100110000100000", 54 | "0100100100100000", 55 | "0100011000101000", 56 | "0100001101000000", 57 | "0100000001100000", 58 | "0011110110001000", 59 | "0011101011000000", 60 | "0011100000000000", 61 | "0011010101001000", 62 | "0011001010100000", 63 | "0010111111111000", 64 | "0010110101100000", 65 | "0010101011010000", 66 | "0010100001001000", 67 | "0010010111001000", 68 | "0010001101011000", 69 | "0010000011101000", 70 | "0001111010000000", 71 | "0001110000101000", 72 | "0001100111010000", 73 | "0001011110000000", 74 | "0001010101000000", 75 | "0001001100000000", 76 | "0001000011001000", 77 | "0000111010011000", 78 | "0000110001101000", 79 | "0000101001001000", 80 | "0000100000110000", 81 | "0000011000011000", 82 | "0000010000001000", 83 | "0000001000000000" 84 | ); 85 | begin 86 | data <= "0010"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1111111111111000", 21 | "1111110000001000", 22 | "1111100000101000", 23 | "1111010001100000", 24 | "1111000010110000", 25 | "1110110100010000", 26 | "1110100110001000", 27 | "1110011000011000", 28 | "1110001010110000", 29 | "1101111101100000", 30 | "1101110000100000", 31 | "1101100011110000", 32 | "1101010111010000", 33 | "1101001011000000", 34 | "1100111111000000", 35 | "1100110011010000", 36 | "1100100111110000", 37 | "1100011100011000", 38 | "1100010001010000", 39 | "1100000110010000", 40 | "1011111011100000", 41 | "1011110001000000", 42 | "1011100110101000", 43 | "1011011100100000", 44 | "1011010010100000", 45 | "1011001000101000", 46 | "1010111111000000", 47 | "1010110101011000", 48 | "1010101100001000", 49 | "1010100010111000", 50 | "1010011001110000", 51 | "1010010000111000", 52 | "1010001000001000", 53 | "1001111111100000", 54 | "1001110111000000", 55 | "1001101110101000", 56 | "1001100110011000", 57 | "1001011110010000", 58 | "1001010110001000", 59 | "1001001110010000", 60 | "1001000110100000", 61 | "1000111110111000", 62 | "1000110111010000", 63 | "1000101111111000", 64 | "1000101000100000", 65 | "1000100001010000", 66 | "1000011010001000", 67 | "1000010011000000", 68 | "1000001100001000", 69 | "1000000101010000", 70 | "0111111110011000", 71 | "0111110111110000", 72 | "0111110001001000", 73 | "0111101010101000", 74 | "0111100100010000", 75 | "0111011101111000", 76 | "0111010111101000", 77 | "0111010001011000", 78 | "0111001011010000", 79 | "0111000101010000", 80 | "0110111111010000", 81 | "0110111001011000", 82 | "0110110011100000", 83 | "0110101101110000" 84 | ); 85 | begin 86 | data <= "0001"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=16; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1101010000010000", 21 | "1100111001111000", 22 | "1100100100000000", 23 | "1100001110101000", 24 | "1011111001110000", 25 | "1011100101010000", 26 | "1011010001010000", 27 | "1010111101110000", 28 | "1010101010101000", 29 | "1010010111110000", 30 | "1010000101011000", 31 | "1001110011011000", 32 | "1001100001110000", 33 | "1001010000011000", 34 | "1000111111100000", 35 | "1000101110110000", 36 | "1000011110100000", 37 | "1000001110011000", 38 | "0111111110101000", 39 | "0111101111010000", 40 | "0111100000000000", 41 | "0111010001001000", 42 | "0111000010100000", 43 | "0110110100000000", 44 | "0110100101111000", 45 | "0110011000000000", 46 | "0110001010010000", 47 | "0101111100111000", 48 | "0101101111101000", 49 | "0101100010101000", 50 | "0101010101110000", 51 | "0101001001001000", 52 | "0100111100110000", 53 | "0100110000100000", 54 | "0100100100100000", 55 | "0100011000101000", 56 | "0100001101000000", 57 | "0100000001100000", 58 | "0011110110001000", 59 | "0011101011000000", 60 | "0011100000000000", 61 | "0011010101001000", 62 | "0011001010100000", 63 | "0010111111111000", 64 | "0010110101100000", 65 | "0010101011010000", 66 | "0010100001001000", 67 | "0010010111001000", 68 | "0010001101011000", 69 | "0010000011101000", 70 | "0001111010000000", 71 | "0001110000101000", 72 | "0001100111010000", 73 | "0001011110000000", 74 | "0001010101000000", 75 | "0001001100000000", 76 | "0001000011001000", 77 | "0000111010011000", 78 | "0000110001101000", 79 | "0000101001001000", 80 | "0000100000110000", 81 | "0000011000011000", 82 | "0000010000001000", 83 | "0000001000000000" 84 | ); 85 | begin 86 | data <= "0010"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/Verification/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | 4 | radix define iee754s_fp -float -fraction 23 -base decimal -precision 10 5 | 6 | set SFUS 1 7 | 8 | add wave -noupdate -label CLK /sfu_tb/s_clk_i 9 | add wave -noupdate -label DATA_IN -radix hexadecimal /sfu_tb/s_src1_i 10 | add wave -noupdate -label DATA_RRO -radix hexadecimal /sfu_tb/s_sfu_input 11 | add wave -noupdate -label OPER /sfu_tb/s_selop_i 12 | add wave -noupdate -label RESULT -radix hexadecimal /sfu_tb/s_Result_o 13 | add wave -noupdate -label ErrTMR /sfu_tb/s_Result_o_err 14 | 15 | add wave -noupdate -group SFU_PROC /sfu_tb/DUT/DUT01/* 16 | add wave -noupdate -group SFU_PROC /sfu_tb/DUT/DUT02/* 17 | add wave -noupdate -group SFU_PROC /sfu_tb/DUT/DUT03/* 18 | 19 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/DUT01/uQuadraticInterpol/* 20 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/DUT01/uQuadraticInterpol/u_SpecialSquaringUnit/* 21 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/DUT01/uQuadraticInterpol/uFusedAccTree/* 22 | 23 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/DUT02/uQuadraticInterpol/* 24 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/DUT02/uQuadraticInterpol/u_SpecialSquaringUnit/* 25 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/DUT02/uQuadraticInterpol/uFusedAccTree/* 26 | 27 | add wave -noupdate -group uQuadraticInterpol /sfu_tb/DUT/DUT03/uQuadraticInterpol/* 28 | add wave -noupdate -group u_SpecialSquaringUnit /sfu_tb/DUT/DUT03/uQuadraticInterpol/u_SpecialSquaringUnit/* 29 | add wave -noupdate -group uFusedAccTree /sfu_tb/DUT/DUT03/uQuadraticInterpol/uFusedAccTree/* 30 | 31 | add wave -noupdate -group Test_Bench_Signals /sfu_tb/* 32 | 33 | TreeUpdate [SetDefaultTree] 34 | WaveRestoreCursors {{Cursor 1} {80000 ps} 0} 35 | quietly wave cursor active 1 36 | configure wave -namecolwidth 76 37 | configure wave -valuecolwidth 49 38 | configure wave -justifyvalue left 39 | configure wave -signalnamewidth 0 40 | configure wave -snapdistance 10 41 | configure wave -datasetprefix 0 42 | configure wave -rowmargin 4 43 | configure wave -childrowmargin 2 44 | configure wave -gridoffset 0 45 | configure wave -gridperiod 1 46 | configure wave -griddelta 40 47 | configure wave -timeline 0 48 | configure wave -timelineunits ns 49 | update 50 | WaveRestoreZoom {0 ps} {180 ns} 51 | -------------------------------------------------------------------------------- /Description/SFU_00/SFU/RRO/Components/right_shifter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Right Shifter for FP addition-subtraction (right_shifter.vhd) 3 | -- P: number of fractional (significant) bits 4 | -- right shift up to E positions. Generates in the last bit the sticky bit. 5 | -- PLOG is log (P); numbers of bits to represent P 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity right_shifter is 14 | generic ( 15 | P: natural := 27; 16 | E: natural := 8; 17 | PLOG: natural := 4 18 | ); 19 | port ( 20 | frac :in std_logic_vector (P downto 0); 21 | diff_exp :in std_logic_vector (E downto 0); 22 | frac_align :out std_logic_vector (P downto 0)); 23 | end entity; 24 | 25 | architecture behav of right_shifter is 26 | signal fracAlign_int :std_logic_vector(P downto 0); 27 | signal aux :std_logic_vector(E downto PLOG+1); 28 | constant allShifted :std_logic_vector(P downto 0):=(0 =>'1', others =>'0'); 29 | constant ZEROS :std_logic_vector(E downto PLOG+1):=(others =>'0'); 30 | begin 31 | --Right Shifter. Shifts up to p+3 positions 32 | process(diff_exp, frac) 33 | variable temp :std_logic_vector(P downto 0); 34 | variable dtemp :std_logic_vector(P downto 0); 35 | variable fracAgnVar :std_logic_vector(P downto 0); 36 | variable sticky :std_logic; 37 | constant zeros :std_logic_vector(P downto 0):=(others => '0'); 38 | begin 39 | temp := frac; 40 | sticky := '0'; 41 | for i in PLOG downto 0 loop --4 downto 0 for single (P=24+3=27) 42 | if (diff_exp(i) = '1') then 43 | dtemp := (others => '0'); 44 | dtemp(P - 2**i downto 0) := temp(P downto 2**i); 45 | if temp(2**i-1 downto 0) /= zeros(2**i-1 downto 0) then 46 | sticky := '1'; 47 | else 48 | sticky := '0'; 49 | end if; 50 | else 51 | dtemp := temp; 52 | end if; 53 | temp := dtemp; 54 | end loop; 55 | fracAlign_int <= dtemp(P downto 1)&(dtemp(0) or sticky); 56 | end process; 57 | 58 | frac_align <= fracAlign_int when diff_exp(E downto PLOG+1) = ZEROS else allShifted; 59 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/RRO/Components/right_shifter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Right Shifter for FP addition-subtraction (right_shifter.vhd) 3 | -- P: number of fractional (significant) bits 4 | -- right shift up to E positions. Generates in the last bit the sticky bit. 5 | -- PLOG is log (P); numbers of bits to represent P 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity right_shifter is 14 | generic ( 15 | P: natural := 27; 16 | E: natural := 8; 17 | PLOG: natural := 4 18 | ); 19 | port ( 20 | frac :in std_logic_vector (P downto 0); 21 | diff_exp :in std_logic_vector (E downto 0); 22 | frac_align :out std_logic_vector (P downto 0)); 23 | end entity; 24 | 25 | architecture behav of right_shifter is 26 | signal fracAlign_int :std_logic_vector(P downto 0); 27 | signal aux :std_logic_vector(E downto PLOG+1); 28 | constant allShifted :std_logic_vector(P downto 0):=(0 =>'1', others =>'0'); 29 | constant ZEROS :std_logic_vector(E downto PLOG+1):=(others =>'0'); 30 | begin 31 | --Right Shifter. Shifts up to p+3 positions 32 | process(diff_exp, frac) 33 | variable temp :std_logic_vector(P downto 0); 34 | variable dtemp :std_logic_vector(P downto 0); 35 | variable fracAgnVar :std_logic_vector(P downto 0); 36 | variable sticky :std_logic; 37 | constant zeros :std_logic_vector(P downto 0):=(others => '0'); 38 | begin 39 | temp := frac; 40 | sticky := '0'; 41 | for i in PLOG downto 0 loop --4 downto 0 for single (P=24+3=27) 42 | if (diff_exp(i) = '1') then 43 | dtemp := (others => '0'); 44 | dtemp(P - 2**i downto 0) := temp(P downto 2**i); 45 | if temp(2**i-1 downto 0) /= zeros(2**i-1 downto 0) then 46 | sticky := '1'; 47 | else 48 | sticky := '0'; 49 | end if; 50 | else 51 | dtemp := temp; 52 | end if; 53 | temp := dtemp; 54 | end loop; 55 | fracAlign_int <= dtemp(P downto 1)&(dtemp(0) or sticky); 56 | end process; 57 | 58 | frac_align <= fracAlign_int when diff_exp(E downto PLOG+1) = ZEROS else allShifted; 59 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/RRO/Components/right_shifter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Right Shifter for FP addition-subtraction (right_shifter.vhd) 3 | -- P: number of fractional (significant) bits 4 | -- right shift up to E positions. Generates in the last bit the sticky bit. 5 | -- PLOG is log (P); numbers of bits to represent P 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity right_shifter is 14 | generic ( 15 | P: natural := 27; 16 | E: natural := 8; 17 | PLOG: natural := 4 18 | ); 19 | port ( 20 | frac :in std_logic_vector (P downto 0); 21 | diff_exp :in std_logic_vector (E downto 0); 22 | frac_align :out std_logic_vector (P downto 0)); 23 | end entity; 24 | 25 | architecture behav of right_shifter is 26 | signal fracAlign_int :std_logic_vector(P downto 0); 27 | signal aux :std_logic_vector(E downto PLOG+1); 28 | constant allShifted :std_logic_vector(P downto 0):=(0 =>'1', others =>'0'); 29 | constant ZEROS :std_logic_vector(E downto PLOG+1):=(others =>'0'); 30 | begin 31 | --Right Shifter. Shifts up to p+3 positions 32 | process(diff_exp, frac) 33 | variable temp :std_logic_vector(P downto 0); 34 | variable dtemp :std_logic_vector(P downto 0); 35 | variable fracAgnVar :std_logic_vector(P downto 0); 36 | variable sticky :std_logic; 37 | constant zeros :std_logic_vector(P downto 0):=(others => '0'); 38 | begin 39 | temp := frac; 40 | sticky := '0'; 41 | for i in PLOG downto 0 loop --4 downto 0 for single (P=24+3=27) 42 | if (diff_exp(i) = '1') then 43 | dtemp := (others => '0'); 44 | dtemp(P - 2**i downto 0) := temp(P downto 2**i); 45 | if temp(2**i-1 downto 0) /= zeros(2**i-1 downto 0) then 46 | sticky := '1'; 47 | else 48 | sticky := '0'; 49 | end if; 50 | else 51 | dtemp := temp; 52 | end if; 53 | temp := dtemp; 54 | end loop; 55 | fracAlign_int <= dtemp(P downto 1)&(dtemp(0) or sticky); 56 | end process; 57 | 58 | frac_align <= fracAlign_int when diff_exp(E downto PLOG+1) = ZEROS else allShifted; 59 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/RRO/Components/right_shifter.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Right Shifter for FP addition-subtraction (right_shifter.vhd) 3 | -- P: number of fractional (significant) bits 4 | -- right shift up to E positions. Generates in the last bit the sticky bit. 5 | -- PLOG is log (P); numbers of bits to represent P 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity right_shifter is 14 | generic ( 15 | P: natural := 27; 16 | E: natural := 8; 17 | PLOG: natural := 4 18 | ); 19 | port ( 20 | frac :in std_logic_vector (P downto 0); 21 | diff_exp :in std_logic_vector (E downto 0); 22 | frac_align :out std_logic_vector (P downto 0)); 23 | end entity; 24 | 25 | architecture behav of right_shifter is 26 | signal fracAlign_int :std_logic_vector(P downto 0); 27 | signal aux :std_logic_vector(E downto PLOG+1); 28 | constant allShifted :std_logic_vector(P downto 0):=(0 =>'1', others =>'0'); 29 | constant ZEROS :std_logic_vector(E downto PLOG+1):=(others =>'0'); 30 | begin 31 | --Right Shifter. Shifts up to p+3 positions 32 | process(diff_exp, frac) 33 | variable temp :std_logic_vector(P downto 0); 34 | variable dtemp :std_logic_vector(P downto 0); 35 | variable fracAgnVar :std_logic_vector(P downto 0); 36 | variable sticky :std_logic; 37 | constant zeros :std_logic_vector(P downto 0):=(others => '0'); 38 | begin 39 | temp := frac; 40 | sticky := '0'; 41 | for i in PLOG downto 0 loop --4 downto 0 for single (P=24+3=27) 42 | if (diff_exp(i) = '1') then 43 | dtemp := (others => '0'); 44 | dtemp(P - 2**i downto 0) := temp(P downto 2**i); 45 | if temp(2**i-1 downto 0) /= zeros(2**i-1 downto 0) then 46 | sticky := '1'; 47 | else 48 | sticky := '0'; 49 | end if; 50 | else 51 | dtemp := temp; 52 | end if; 53 | temp := dtemp; 54 | end loop; 55 | fracAlign_int <= dtemp(P downto 1)&(dtemp(0) or sticky); 56 | end process; 57 | 58 | frac_align <= fracAlign_int when diff_exp(E downto PLOG+1) = ZEROS else allShifted; 59 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_cos is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000000000000000", 21 | "000000111111111111", 22 | "000001111111111110", 23 | "000010111111111011", 24 | "000011111111110101", 25 | "000100111111101011", 26 | "000101111111011100", 27 | "000110111111000111", 28 | "000111111110101011", 29 | "001000111110000111", 30 | "001001111101011010", 31 | "001010111100100011", 32 | "001011111011100001", 33 | "001100111010010011", 34 | "001101111000111001", 35 | "001110110111010000", 36 | "001111110101011000", 37 | "010000110011010001", 38 | "010001110000111001", 39 | "010010101110001111", 40 | "010011101011010011", 41 | "010100101000000010", 42 | "010101100100011101", 43 | "010110100000100011", 44 | "010111011100010010", 45 | "011000010111101001", 46 | "011001010010101001", 47 | "011010001101001111", 48 | "011011000111011010", 49 | "011100000001001011", 50 | "011100111010011111", 51 | "011101110011010111", 52 | "011110101011110001", 53 | "011111100011101100", 54 | "100000011011001000", 55 | "100001010010000011", 56 | "100010001000011101", 57 | "100010111110010101", 58 | "100011110011101001", 59 | "100100101000011010", 60 | "100101011100100111", 61 | "100110010000001110", 62 | "100111000011001110", 63 | "100111110101101000", 64 | "101000100111011010", 65 | "101001011000100011", 66 | "101010001001000011", 67 | "101010111000111000", 68 | "101011101000000011", 69 | "101100010110100010", 70 | "101101000100010101", 71 | "101101110001011011", 72 | "101110011101110011", 73 | "101111001001011100", 74 | "101111110100010111", 75 | "110000011110100001", 76 | "110001000111111011", 77 | "110001110000100100", 78 | "110010011000011011", 79 | "110010111111100000", 80 | "110011100101110010", 81 | "110100001011010000", 82 | "110100101111111010", 83 | "110101010011101111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_cos is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000000000000000", 21 | "000000111111111111", 22 | "000001111111111110", 23 | "000010111111111011", 24 | "000011111111110101", 25 | "000100111111101011", 26 | "000101111111011100", 27 | "000110111111000111", 28 | "000111111110101011", 29 | "001000111110000111", 30 | "001001111101011010", 31 | "001010111100100011", 32 | "001011111011100001", 33 | "001100111010010011", 34 | "001101111000111001", 35 | "001110110111010000", 36 | "001111110101011000", 37 | "010000110011010001", 38 | "010001110000111001", 39 | "010010101110001111", 40 | "010011101011010011", 41 | "010100101000000010", 42 | "010101100100011101", 43 | "010110100000100011", 44 | "010111011100010010", 45 | "011000010111101001", 46 | "011001010010101001", 47 | "011010001101001111", 48 | "011011000111011010", 49 | "011100000001001011", 50 | "011100111010011111", 51 | "011101110011010111", 52 | "011110101011110001", 53 | "011111100011101100", 54 | "100000011011001000", 55 | "100001010010000011", 56 | "100010001000011101", 57 | "100010111110010101", 58 | "100011110011101001", 59 | "100100101000011010", 60 | "100101011100100111", 61 | "100110010000001110", 62 | "100111000011001110", 63 | "100111110101101000", 64 | "101000100111011010", 65 | "101001011000100011", 66 | "101010001001000011", 67 | "101010111000111000", 68 | "101011101000000011", 69 | "101100010110100010", 70 | "101101000100010101", 71 | "101101110001011011", 72 | "101110011101110011", 73 | "101111001001011100", 74 | "101111110100010111", 75 | "110000011110100001", 76 | "110001000111111011", 77 | "110001110000100100", 78 | "110010011000011011", 79 | "110010111111100000", 80 | "110011100101110010", 81 | "110100001011010000", 82 | "110100101111111010", 83 | "110101010011101111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_cos is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000000000000000", 21 | "000000111111111111", 22 | "000001111111111110", 23 | "000010111111111011", 24 | "000011111111110101", 25 | "000100111111101011", 26 | "000101111111011100", 27 | "000110111111000111", 28 | "000111111110101011", 29 | "001000111110000111", 30 | "001001111101011010", 31 | "001010111100100011", 32 | "001011111011100001", 33 | "001100111010010011", 34 | "001101111000111001", 35 | "001110110111010000", 36 | "001111110101011000", 37 | "010000110011010001", 38 | "010001110000111001", 39 | "010010101110001111", 40 | "010011101011010011", 41 | "010100101000000010", 42 | "010101100100011101", 43 | "010110100000100011", 44 | "010111011100010010", 45 | "011000010111101001", 46 | "011001010010101001", 47 | "011010001101001111", 48 | "011011000111011010", 49 | "011100000001001011", 50 | "011100111010011111", 51 | "011101110011010111", 52 | "011110101011110001", 53 | "011111100011101100", 54 | "100000011011001000", 55 | "100001010010000011", 56 | "100010001000011101", 57 | "100010111110010101", 58 | "100011110011101001", 59 | "100100101000011010", 60 | "100101011100100111", 61 | "100110010000001110", 62 | "100111000011001110", 63 | "100111110101101000", 64 | "101000100111011010", 65 | "101001011000100011", 66 | "101010001001000011", 67 | "101010111000111000", 68 | "101011101000000011", 69 | "101100010110100010", 70 | "101101000100010101", 71 | "101101110001011011", 72 | "101110011101110011", 73 | "101111001001011100", 74 | "101111110100010111", 75 | "110000011110100001", 76 | "110001000111111011", 77 | "110001110000100100", 78 | "110010011000011011", 79 | "110010111111100000", 80 | "110011100101110010", 81 | "110100001011010000", 82 | "110100101111111010", 83 | "110101010011101111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_cos.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_cos is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_cos is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000000000000000", 21 | "000000111111111111", 22 | "000001111111111110", 23 | "000010111111111011", 24 | "000011111111110101", 25 | "000100111111101011", 26 | "000101111111011100", 27 | "000110111111000111", 28 | "000111111110101011", 29 | "001000111110000111", 30 | "001001111101011010", 31 | "001010111100100011", 32 | "001011111011100001", 33 | "001100111010010011", 34 | "001101111000111001", 35 | "001110110111010000", 36 | "001111110101011000", 37 | "010000110011010001", 38 | "010001110000111001", 39 | "010010101110001111", 40 | "010011101011010011", 41 | "010100101000000010", 42 | "010101100100011101", 43 | "010110100000100011", 44 | "010111011100010010", 45 | "011000010111101001", 46 | "011001010010101001", 47 | "011010001101001111", 48 | "011011000111011010", 49 | "011100000001001011", 50 | "011100111010011111", 51 | "011101110011010111", 52 | "011110101011110001", 53 | "011111100011101100", 54 | "100000011011001000", 55 | "100001010010000011", 56 | "100010001000011101", 57 | "100010111110010101", 58 | "100011110011101001", 59 | "100100101000011010", 60 | "100101011100100111", 61 | "100110010000001110", 62 | "100111000011001110", 63 | "100111110101101000", 64 | "101000100111011010", 65 | "101001011000100011", 66 | "101010001001000011", 67 | "101010111000111000", 68 | "101011101000000011", 69 | "101100010110100010", 70 | "101101000100010101", 71 | "101101110001011011", 72 | "101110011101110011", 73 | "101111001001011100", 74 | "101111110100010111", 75 | "110000011110100001", 76 | "110001000111111011", 77 | "110001110000100100", 78 | "110010011000011011", 79 | "110010111111100000", 80 | "110011100101110010", 81 | "110100001011010000", 82 | "110100101111111010", 83 | "110101010011101111" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_ln2e0 is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "101110001010011000", 21 | "101101001101111000", 22 | "101100010011100000", 23 | "101011011011000000", 24 | "101010100100011000", 25 | "101001101111101000", 26 | "101000111100100000", 27 | "101000001011000000", 28 | "100111011011001000", 29 | "100110101100101000", 30 | "100101111111101000", 31 | "100101010011111000", 32 | "100100101001100000", 33 | "100100000000011000", 34 | "100011011000100000", 35 | "100010110001110000", 36 | "100010001100000000", 37 | "100001100111011000", 38 | "100001000011110000", 39 | "100000100001001000", 40 | "011111111111100000", 41 | "011111011110101000", 42 | "011110111110110000", 43 | "011110011111101000", 44 | "011110000001011000", 45 | "011101100011111000", 46 | "011101000111001000", 47 | "011100101011001000", 48 | "011100001111110000", 49 | "011011110101000000", 50 | "011011011011000000", 51 | "011011000001101000", 52 | "011010101000111000", 53 | "011010010000101000", 54 | "011001111001000000", 55 | "011001100010000000", 56 | "011001001011011000", 57 | "011000110101011000", 58 | "011000011111111000", 59 | "011000001010110000", 60 | "010111110110001000", 61 | "010111100010000000", 62 | "010111001110011000", 63 | "010110111011000000", 64 | "010110101000001000", 65 | "010110010101110000", 66 | "010110000011101000", 67 | "010101110001111000", 68 | "010101100000101000", 69 | "010101001111101000", 70 | "010100111111000000", 71 | "010100101110101000", 72 | "010100011110101000", 73 | "010100001111000000", 74 | "010011111111101000", 75 | "010011110000101000", 76 | "010011100001111000", 77 | "010011010011011000", 78 | "010011000101001000", 79 | "010010110111010000", 80 | "010010101001100000", 81 | "010010011100001000", 82 | "010010001110111000", 83 | "010010000010000000" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_ln2e0 is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "101110001010011000", 21 | "101101001101111000", 22 | "101100010011100000", 23 | "101011011011000000", 24 | "101010100100011000", 25 | "101001101111101000", 26 | "101000111100100000", 27 | "101000001011000000", 28 | "100111011011001000", 29 | "100110101100101000", 30 | "100101111111101000", 31 | "100101010011111000", 32 | "100100101001100000", 33 | "100100000000011000", 34 | "100011011000100000", 35 | "100010110001110000", 36 | "100010001100000000", 37 | "100001100111011000", 38 | "100001000011110000", 39 | "100000100001001000", 40 | "011111111111100000", 41 | "011111011110101000", 42 | "011110111110110000", 43 | "011110011111101000", 44 | "011110000001011000", 45 | "011101100011111000", 46 | "011101000111001000", 47 | "011100101011001000", 48 | "011100001111110000", 49 | "011011110101000000", 50 | "011011011011000000", 51 | "011011000001101000", 52 | "011010101000111000", 53 | "011010010000101000", 54 | "011001111001000000", 55 | "011001100010000000", 56 | "011001001011011000", 57 | "011000110101011000", 58 | "011000011111111000", 59 | "011000001010110000", 60 | "010111110110001000", 61 | "010111100010000000", 62 | "010111001110011000", 63 | "010110111011000000", 64 | "010110101000001000", 65 | "010110010101110000", 66 | "010110000011101000", 67 | "010101110001111000", 68 | "010101100000101000", 69 | "010101001111101000", 70 | "010100111111000000", 71 | "010100101110101000", 72 | "010100011110101000", 73 | "010100001111000000", 74 | "010011111111101000", 75 | "010011110000101000", 76 | "010011100001111000", 77 | "010011010011011000", 78 | "010011000101001000", 79 | "010010110111010000", 80 | "010010101001100000", 81 | "010010011100001000", 82 | "010010001110111000", 83 | "010010000010000000" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_ln2e0 is 6 | generic( 7 | word_bits :natural:=18; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "101110001010011000", 21 | "101101001101111000", 22 | "101100010011100000", 23 | "101011011011000000", 24 | "101010100100011000", 25 | "101001101111101000", 26 | "101000111100100000", 27 | "101000001011000000", 28 | "100111011011001000", 29 | "100110101100101000", 30 | "100101111111101000", 31 | "100101010011111000", 32 | "100100101001100000", 33 | "100100000000011000", 34 | "100011011000100000", 35 | "100010110001110000", 36 | "100010001100000000", 37 | "100001100111011000", 38 | "100001000011110000", 39 | "100000100001001000", 40 | "011111111111100000", 41 | "011111011110101000", 42 | "011110111110110000", 43 | "011110011111101000", 44 | "011110000001011000", 45 | "011101100011111000", 46 | "011101000111001000", 47 | "011100101011001000", 48 | "011100001111110000", 49 | "011011110101000000", 50 | "011011011011000000", 51 | "011011000001101000", 52 | "011010101000111000", 53 | "011010010000101000", 54 | "011001111001000000", 55 | "011001100010000000", 56 | "011001001011011000", 57 | "011000110101011000", 58 | "011000011111111000", 59 | "011000001010110000", 60 | "010111110110001000", 61 | "010111100010000000", 62 | "010111001110011000", 63 | "010110111011000000", 64 | "010110101000001000", 65 | "010110010101110000", 66 | "010110000011101000", 67 | "010101110001111000", 68 | "010101100000101000", 69 | "010101001111101000", 70 | "010100111111000000", 71 | "010100101110101000", 72 | "010100011110101000", 73 | "010100001111000000", 74 | "010011111111101000", 75 | "010011110000101000", 76 | "010011100001111000", 77 | "010011010011011000", 78 | "010011000101001000", 79 | "010010110111010000", 80 | "010010101001100000", 81 | "010010011100001000", 82 | "010010001110111000", 83 | "010010000010000000" 84 | ); 85 | begin 86 | data <= "10"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/RRO/Components/right_shifter.vhd.bak: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Right Shifter for FP addition-subtraction (right_shifter.vhd) 3 | -- P: number of fractional (significant) bits 4 | -- right shift up to E positions. Generates in the last bit the sticky bit. 5 | -- PLOG is log (P); numbers of bits to represent P 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.std_logic_arith.all; 12 | use ieee.std_logic_unsigned.all; 13 | entity right_shifter is 14 | generic (P: natural:= 27; E: natural := 8; PLOG: natural := 4); 15 | Port ( frac : in std_logic_vector (P downto 0); 16 | diff_exp : in std_logic_vector (E downto 0); 17 | frac_align : out std_logic_vector (P downto 0)); 18 | end right_shifter; 19 | 20 | architecture Behavioral of right_shifter is 21 | signal fracAlign_int : std_logic_vector(P downto 0); 22 | constant allShifted : std_logic_vector(P downto 0) := (0 =>'1', others =>'0'); 23 | constant ZEROS : std_logic_vector(P downto PLOG) := (others =>'0'); 24 | 25 | begin 26 | --Right Shifter. Shifts up to p+3 positions 27 | process(diff_exp, frac) 28 | variable temp : std_logic_vector(P downto 0); 29 | variable dtemp : std_logic_vector(P downto 0); 30 | variable fracAgnVar : std_logic_vector(P downto 0); 31 | variable sticky : std_logic; 32 | constant zeros : std_logic_vector(P downto 0) := (others => '0'); 33 | begin 34 | temp := frac; 35 | sticky := '0'; 36 | for i in PLOG downto 0 loop --4 downto 0 for single (P=24+3=27) 37 | if (diff_exp(i) = '1') then 38 | dtemp := (others => '0'); 39 | dtemp(P - 2**i downto 0) := temp(P downto 2**i); 40 | if temp(2**i -1 downto 0) /= zeros(2**i downto 0) then 41 | sticky := '1'; 42 | end if; 43 | else --if (diff_exp(i) = '0') 44 | dtemp := temp; 45 | end if; 46 | temp := dtemp; 47 | end loop; 48 | 49 | fracAlign_int <= dtemp(P downto 1) & (dtemp(0) or sticky); 50 | 51 | end process; 52 | 53 | frac_align <= fracAlign_int when diff_exp(E downto PLOG+1) = ZEROS else allShifted; --if diffexp >> P -> allshifted 54 | 55 | end Behavioral; 56 | 57 | -------------------------------------------------------------------------------- /Description/SFU_00/SFU/RRO/RRO_trig.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity RRO_trig is 6 | port( 7 | input_data :in std_logic_vector(31 downto 0); 8 | output_data :out std_logic_vector(31 downto 0); 9 | quadrant :out std_logic_vector(1 downto 0) 10 | ); 11 | end entity; 12 | 13 | architecture Reduce_model of RRO_trig is 14 | signal Mult1,Mult2,Mult3,Sub1,Input_pos,output_sign :std_logic_vector(31 downto 0); 15 | signal Mult1_floor :std_logic_vector(253 downto 0); 16 | signal floor_tmp :std_logic_vector(253 downto 0); 17 | signal floor_tmp2 :std_logic_vector(253 downto 0); 18 | signal floor_tmp3 :std_logic_vector(253 downto 0); 19 | signal shift_select :unsigned(7 downto 0); 20 | signal floor_fp :std_logic_vector(31 downto 0); 21 | begin 22 | Input_pos <= '0'&input_data(30 downto 0); 23 | 24 | M0: entity work.multFP 25 | port map( 26 | entrada_x => Input_pos, 27 | entrada_y => X"3f22f983", 28 | salida => Mult1); 29 | 30 | --Floor input data 31 | Mult1_floor(253 downto 230) <= '1'&Mult1(22 downto 0); 32 | Mult1_floor(229 downto 0) <= (others=>'0'); 33 | 34 | shift_select <= (to_unsigned(254,8)-unsigned(Mult1(30 downto 23))); 35 | 36 | floor_tmp <= std_logic_vector(unsigned(Mult1_floor) srl to_integer(shift_select)); 37 | 38 | floor_tmp2(125 downto 0) <= (others=>'0'); 39 | floor_tmp2(253 downto 126) <= floor_tmp(253 downto 126); 40 | floor_tmp3 <= std_logic_vector(unsigned(floor_tmp2) sll to_integer(shift_select)); 41 | 42 | floor_fp(31) <= '0'; 43 | floor_fp(30 downto 23) <= Mult1(30 downto 23) when unsigned(floor_tmp3)/=0 else (others=>'0'); 44 | floor_fp(22 downto 0) <= floor_tmp3(252 downto 230); 45 | 46 | M1: entity work.multFP 47 | port map( 48 | entrada_x => floor_fp, 49 | entrada_y => X"3fc90000", 50 | salida => Mult2); 51 | 52 | M2: entity work.multFP 53 | port map( 54 | entrada_x => floor_fp, 55 | entrada_y => X"39fdaa22", 56 | salida => Mult3); 57 | 58 | S1: entity work.add_sub 59 | port map( 60 | FP_A => Input_pos, 61 | FP_B => Mult2, 62 | add_sub => '0', 63 | FP_Z => Sub1); 64 | 65 | S2: entity work.add_sub 66 | port map( 67 | FP_A => Sub1, 68 | FP_B => Mult3, 69 | add_sub => '0', 70 | FP_Z => output_sign); 71 | 72 | output_data <= input_data(31)&output_sign(30 downto 0); 73 | quadrant <= floor_tmp2(127 downto 126); 74 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/RRO/RRO_trig.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity RRO_trig is 6 | port( 7 | input_data :in std_logic_vector(31 downto 0); 8 | output_data :out std_logic_vector(31 downto 0); 9 | quadrant :out std_logic_vector(1 downto 0) 10 | ); 11 | end entity; 12 | 13 | architecture Reduce_model of RRO_trig is 14 | signal Mult1,Mult2,Mult3,Sub1,Input_pos,output_sign :std_logic_vector(31 downto 0); 15 | signal Mult1_floor :std_logic_vector(253 downto 0); 16 | signal floor_tmp :std_logic_vector(253 downto 0); 17 | signal floor_tmp2 :std_logic_vector(253 downto 0); 18 | signal floor_tmp3 :std_logic_vector(253 downto 0); 19 | signal shift_select :unsigned(7 downto 0); 20 | signal floor_fp :std_logic_vector(31 downto 0); 21 | begin 22 | Input_pos <= '0'&input_data(30 downto 0); 23 | 24 | M0: entity work.multFP 25 | port map( 26 | entrada_x => Input_pos, 27 | entrada_y => X"3f22f983", 28 | salida => Mult1); 29 | 30 | --Floor input data 31 | Mult1_floor(253 downto 230) <= '1'&Mult1(22 downto 0); 32 | Mult1_floor(229 downto 0) <= (others=>'0'); 33 | 34 | shift_select <= (to_unsigned(254,8)-unsigned(Mult1(30 downto 23))); 35 | 36 | floor_tmp <= std_logic_vector(unsigned(Mult1_floor) srl to_integer(shift_select)); 37 | 38 | floor_tmp2(125 downto 0) <= (others=>'0'); 39 | floor_tmp2(253 downto 126) <= floor_tmp(253 downto 126); 40 | floor_tmp3 <= std_logic_vector(unsigned(floor_tmp2) sll to_integer(shift_select)); 41 | 42 | floor_fp(31) <= '0'; 43 | floor_fp(30 downto 23) <= Mult1(30 downto 23) when unsigned(floor_tmp3)/=0 else (others=>'0'); 44 | floor_fp(22 downto 0) <= floor_tmp3(252 downto 230); 45 | 46 | M1: entity work.multFP 47 | port map( 48 | entrada_x => floor_fp, 49 | entrada_y => X"3fc90000", 50 | salida => Mult2); 51 | 52 | M2: entity work.multFP 53 | port map( 54 | entrada_x => floor_fp, 55 | entrada_y => X"39fdaa22", 56 | salida => Mult3); 57 | 58 | S1: entity work.add_sub 59 | port map( 60 | FP_A => Input_pos, 61 | FP_B => Mult2, 62 | add_sub => '0', 63 | FP_Z => Sub1); 64 | 65 | S2: entity work.add_sub 66 | port map( 67 | FP_A => Sub1, 68 | FP_B => Mult3, 69 | add_sub => '0', 70 | FP_Z => output_sign); 71 | 72 | output_data <= input_data(31)&output_sign(30 downto 0); 73 | quadrant <= floor_tmp2(127 downto 126); 74 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/RRO/RRO_trig.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity RRO_trig is 6 | port( 7 | input_data :in std_logic_vector(31 downto 0); 8 | output_data :out std_logic_vector(31 downto 0); 9 | quadrant :out std_logic_vector(1 downto 0) 10 | ); 11 | end entity; 12 | 13 | architecture Reduce_model of RRO_trig is 14 | signal Mult1,Mult2,Mult3,Sub1,Input_pos,output_sign :std_logic_vector(31 downto 0); 15 | signal Mult1_floor :std_logic_vector(253 downto 0); 16 | signal floor_tmp :std_logic_vector(253 downto 0); 17 | signal floor_tmp2 :std_logic_vector(253 downto 0); 18 | signal floor_tmp3 :std_logic_vector(253 downto 0); 19 | signal shift_select :unsigned(7 downto 0); 20 | signal floor_fp :std_logic_vector(31 downto 0); 21 | begin 22 | Input_pos <= '0'&input_data(30 downto 0); 23 | 24 | M0: entity work.multFP 25 | port map( 26 | entrada_x => Input_pos, 27 | entrada_y => X"3f22f983", 28 | salida => Mult1); 29 | 30 | --Floor input data 31 | Mult1_floor(253 downto 230) <= '1'&Mult1(22 downto 0); 32 | Mult1_floor(229 downto 0) <= (others=>'0'); 33 | 34 | shift_select <= (to_unsigned(254,8)-unsigned(Mult1(30 downto 23))); 35 | 36 | floor_tmp <= std_logic_vector(unsigned(Mult1_floor) srl to_integer(shift_select)); 37 | 38 | floor_tmp2(125 downto 0) <= (others=>'0'); 39 | floor_tmp2(253 downto 126) <= floor_tmp(253 downto 126); 40 | floor_tmp3 <= std_logic_vector(unsigned(floor_tmp2) sll to_integer(shift_select)); 41 | 42 | floor_fp(31) <= '0'; 43 | floor_fp(30 downto 23) <= Mult1(30 downto 23) when unsigned(floor_tmp3)/=0 else (others=>'0'); 44 | floor_fp(22 downto 0) <= floor_tmp3(252 downto 230); 45 | 46 | M1: entity work.multFP 47 | port map( 48 | entrada_x => floor_fp, 49 | entrada_y => X"3fc90000", 50 | salida => Mult2); 51 | 52 | M2: entity work.multFP 53 | port map( 54 | entrada_x => floor_fp, 55 | entrada_y => X"39fdaa22", 56 | salida => Mult3); 57 | 58 | S1: entity work.add_sub 59 | port map( 60 | FP_A => Input_pos, 61 | FP_B => Mult2, 62 | add_sub => '0', 63 | FP_Z => Sub1); 64 | 65 | S2: entity work.add_sub 66 | port map( 67 | FP_A => Sub1, 68 | FP_B => Mult3, 69 | add_sub => '0', 70 | FP_Z => output_sign); 71 | 72 | output_data <= input_data(31)&output_sign(30 downto 0); 73 | quadrant <= floor_tmp2(127 downto 126); 74 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/RRO/RRO_trig.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity RRO_trig is 6 | port( 7 | input_data :in std_logic_vector(31 downto 0); 8 | output_data :out std_logic_vector(31 downto 0); 9 | quadrant :out std_logic_vector(1 downto 0) 10 | ); 11 | end entity; 12 | 13 | architecture Reduce_model of RRO_trig is 14 | signal Mult1,Mult2,Mult3,Sub1,Input_pos,output_sign :std_logic_vector(31 downto 0); 15 | signal Mult1_floor :std_logic_vector(253 downto 0); 16 | signal floor_tmp :std_logic_vector(253 downto 0); 17 | signal floor_tmp2 :std_logic_vector(253 downto 0); 18 | signal floor_tmp3 :std_logic_vector(253 downto 0); 19 | signal shift_select :unsigned(7 downto 0); 20 | signal floor_fp :std_logic_vector(31 downto 0); 21 | begin 22 | Input_pos <= '0'&input_data(30 downto 0); 23 | 24 | M0: entity work.multFP 25 | port map( 26 | entrada_x => Input_pos, 27 | entrada_y => X"3f22f983", 28 | salida => Mult1); 29 | 30 | --Floor input data 31 | Mult1_floor(253 downto 230) <= '1'&Mult1(22 downto 0); 32 | Mult1_floor(229 downto 0) <= (others=>'0'); 33 | 34 | shift_select <= (to_unsigned(254,8)-unsigned(Mult1(30 downto 23))); 35 | 36 | floor_tmp <= std_logic_vector(unsigned(Mult1_floor) srl to_integer(shift_select)); 37 | 38 | floor_tmp2(125 downto 0) <= (others=>'0'); 39 | floor_tmp2(253 downto 126) <= floor_tmp(253 downto 126); 40 | floor_tmp3 <= std_logic_vector(unsigned(floor_tmp2) sll to_integer(shift_select)); 41 | 42 | floor_fp(31) <= '0'; 43 | floor_fp(30 downto 23) <= Mult1(30 downto 23) when unsigned(floor_tmp3)/=0 else (others=>'0'); 44 | floor_fp(22 downto 0) <= floor_tmp3(252 downto 230); 45 | 46 | M1: entity work.multFP 47 | port map( 48 | entrada_x => floor_fp, 49 | entrada_y => X"3fc90000", 50 | salida => Mult2); 51 | 52 | M2: entity work.multFP 53 | port map( 54 | entrada_x => floor_fp, 55 | entrada_y => X"39fdaa22", 56 | salida => Mult3); 57 | 58 | S1: entity work.add_sub 59 | port map( 60 | FP_A => Input_pos, 61 | FP_B => Mult2, 62 | add_sub => '0', 63 | FP_Z => Sub1); 64 | 65 | S2: entity work.add_sub 66 | port map( 67 | FP_A => Sub1, 68 | FP_B => Mult3, 69 | add_sub => '0', 70 | FP_Z => output_sign); 71 | 72 | output_data <= input_data(31)&output_sign(30 downto 0); 73 | quadrant <= floor_tmp2(127 downto 126); 74 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sin is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1000000000000000101", 21 | "0111111111111100101", 22 | "0111111111110000110", 23 | "0111111111011100110", 24 | "0111111111000000110", 25 | "0111111110011100110", 26 | "0111111101110000110", 27 | "0111111100111100111", 28 | "0111111100000001000", 29 | "0111111010111101010", 30 | "0111111001110001100", 31 | "0111111000011101111", 32 | "0111110111000010011", 33 | "0111110101011111000", 34 | "0111110011110011110", 35 | "0111110010000000110", 36 | "0111110000000110000", 37 | "0111101110000011100", 38 | "0111101011111001001", 39 | "0111101001100111010", 40 | "0111100111001101101", 41 | "0111100100101100011", 42 | "0111100010000011101", 43 | "0111011111010011011", 44 | "0111011100011011100", 45 | "0111011001011100010", 46 | "0111010110010101101", 47 | "0111010011000111101", 48 | "0111001111110010011", 49 | "0111001100010101110", 50 | "0111001000110010000", 51 | "0111000101000111001", 52 | "0111000001010101010", 53 | "0110111101011100010", 54 | "0110111001011100011", 55 | "0110110101010101100", 56 | "0110110001000111111", 57 | "0110101100110011011", 58 | "0110101000011000010", 59 | "0110100011110110100", 60 | "0110011111001110001", 61 | "0110011010011111011", 62 | "0110010101101010001", 63 | "0110010000101110101", 64 | "0110001011101100110", 65 | "0110000110100100110", 66 | "0110000001010110101", 67 | "0101111100000010100", 68 | "0101110110101000100", 69 | "0101110001001000100", 70 | "0101101011100010111", 71 | "0101100101110111100", 72 | "0101100000000110100", 73 | "0101011010010000001", 74 | "0101010100010100010", 75 | "0101001110010011000", 76 | "0101001000001100101", 77 | "0101000010000001000", 78 | "0100111011110000100", 79 | "0100110101011011000", 80 | "0100101111000000101", 81 | "0100101000100001101", 82 | "0100100001111101111", 83 | "0100011011010101101" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_exp is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0101100010111000000", 21 | "0101100110110000000", 22 | "0101101010101010000", 23 | "0101101110100110000", 24 | "0101110010100110000", 25 | "0101110110101000000", 26 | "0101111010101101000", 27 | "0101111110110101000", 28 | "0110000011000000000", 29 | "0110000111001110000", 30 | "0110001011011110000", 31 | "0110001111110010000", 32 | "0110010100001001000", 33 | "0110011000100010000", 34 | "0110011100111111000", 35 | "0110100001011111000", 36 | "0110100110000010000", 37 | "0110101010101000000", 38 | "0110101111010001000", 39 | "0110110011111110000", 40 | "0110111000101110000", 41 | "0110111101100001000", 42 | "0111000010010111000", 43 | "0111000111010001000", 44 | "0111001100001110000", 45 | "0111010001001111000", 46 | "0111010110010011000", 47 | "0111011011011011000", 48 | "0111100000100110000", 49 | "0111100101110101000", 50 | "0111101011001000000", 51 | "0111110000011110000", 52 | "0111110101111000000", 53 | "0111111011010110000", 54 | "1000000000111000000", 55 | "1000000110011101000", 56 | "1000001100000110000", 57 | "1000010001110100000", 58 | "1000010111100101000", 59 | "1000011101011010000", 60 | "1000100011010011000", 61 | "1000101001010001000", 62 | "1000101111010010000", 63 | "1000110101011000000", 64 | "1000111011100010000", 65 | "1001000001110001000", 66 | "1001001000000011000", 67 | "1001001110011010000", 68 | "1001010100110110000", 69 | "1001011011010110000", 70 | "1001100001111010000", 71 | "1001101000100011000", 72 | "1001101111010001000", 73 | "1001110110000011000", 74 | "1001111100111010000", 75 | "1010000011110110000", 76 | "1010001010110111000", 77 | "1010010001111101000", 78 | "1010011001000111000", 79 | "1010100000010111000", 80 | "1010100111101011000", 81 | "1010101111000101000", 82 | "1010110110100100000", 83 | "1010111110001000000" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sin is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1000000000000000101", 21 | "0111111111111100101", 22 | "0111111111110000110", 23 | "0111111111011100110", 24 | "0111111111000000110", 25 | "0111111110011100110", 26 | "0111111101110000110", 27 | "0111111100111100111", 28 | "0111111100000001000", 29 | "0111111010111101010", 30 | "0111111001110001100", 31 | "0111111000011101111", 32 | "0111110111000010011", 33 | "0111110101011111000", 34 | "0111110011110011110", 35 | "0111110010000000110", 36 | "0111110000000110000", 37 | "0111101110000011100", 38 | "0111101011111001001", 39 | "0111101001100111010", 40 | "0111100111001101101", 41 | "0111100100101100011", 42 | "0111100010000011101", 43 | "0111011111010011011", 44 | "0111011100011011100", 45 | "0111011001011100010", 46 | "0111010110010101101", 47 | "0111010011000111101", 48 | "0111001111110010011", 49 | "0111001100010101110", 50 | "0111001000110010000", 51 | "0111000101000111001", 52 | "0111000001010101010", 53 | "0110111101011100010", 54 | "0110111001011100011", 55 | "0110110101010101100", 56 | "0110110001000111111", 57 | "0110101100110011011", 58 | "0110101000011000010", 59 | "0110100011110110100", 60 | "0110011111001110001", 61 | "0110011010011111011", 62 | "0110010101101010001", 63 | "0110010000101110101", 64 | "0110001011101100110", 65 | "0110000110100100110", 66 | "0110000001010110101", 67 | "0101111100000010100", 68 | "0101110110101000100", 69 | "0101110001001000100", 70 | "0101101011100010111", 71 | "0101100101110111100", 72 | "0101100000000110100", 73 | "0101011010010000001", 74 | "0101010100010100010", 75 | "0101001110010011000", 76 | "0101001000001100101", 77 | "0101000010000001000", 78 | "0100111011110000100", 79 | "0100110101011011000", 80 | "0100101111000000101", 81 | "0100101000100001101", 82 | "0100100001111101111", 83 | "0100011011010101101" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_exp is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0101100010111000000", 21 | "0101100110110000000", 22 | "0101101010101010000", 23 | "0101101110100110000", 24 | "0101110010100110000", 25 | "0101110110101000000", 26 | "0101111010101101000", 27 | "0101111110110101000", 28 | "0110000011000000000", 29 | "0110000111001110000", 30 | "0110001011011110000", 31 | "0110001111110010000", 32 | "0110010100001001000", 33 | "0110011000100010000", 34 | "0110011100111111000", 35 | "0110100001011111000", 36 | "0110100110000010000", 37 | "0110101010101000000", 38 | "0110101111010001000", 39 | "0110110011111110000", 40 | "0110111000101110000", 41 | "0110111101100001000", 42 | "0111000010010111000", 43 | "0111000111010001000", 44 | "0111001100001110000", 45 | "0111010001001111000", 46 | "0111010110010011000", 47 | "0111011011011011000", 48 | "0111100000100110000", 49 | "0111100101110101000", 50 | "0111101011001000000", 51 | "0111110000011110000", 52 | "0111110101111000000", 53 | "0111111011010110000", 54 | "1000000000111000000", 55 | "1000000110011101000", 56 | "1000001100000110000", 57 | "1000010001110100000", 58 | "1000010111100101000", 59 | "1000011101011010000", 60 | "1000100011010011000", 61 | "1000101001010001000", 62 | "1000101111010010000", 63 | "1000110101011000000", 64 | "1000111011100010000", 65 | "1001000001110001000", 66 | "1001001000000011000", 67 | "1001001110011010000", 68 | "1001010100110110000", 69 | "1001011011010110000", 70 | "1001100001111010000", 71 | "1001101000100011000", 72 | "1001101111010001000", 73 | "1001110110000011000", 74 | "1001111100111010000", 75 | "1010000011110110000", 76 | "1010001010110111000", 77 | "1010010001111101000", 78 | "1010011001000111000", 79 | "1010100000010111000", 80 | "1010100111101011000", 81 | "1010101111000101000", 82 | "1010110110100100000", 83 | "1010111110001000000" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sin is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1000000000000000101", 21 | "0111111111111100101", 22 | "0111111111110000110", 23 | "0111111111011100110", 24 | "0111111111000000110", 25 | "0111111110011100110", 26 | "0111111101110000110", 27 | "0111111100111100111", 28 | "0111111100000001000", 29 | "0111111010111101010", 30 | "0111111001110001100", 31 | "0111111000011101111", 32 | "0111110111000010011", 33 | "0111110101011111000", 34 | "0111110011110011110", 35 | "0111110010000000110", 36 | "0111110000000110000", 37 | "0111101110000011100", 38 | "0111101011111001001", 39 | "0111101001100111010", 40 | "0111100111001101101", 41 | "0111100100101100011", 42 | "0111100010000011101", 43 | "0111011111010011011", 44 | "0111011100011011100", 45 | "0111011001011100010", 46 | "0111010110010101101", 47 | "0111010011000111101", 48 | "0111001111110010011", 49 | "0111001100010101110", 50 | "0111001000110010000", 51 | "0111000101000111001", 52 | "0111000001010101010", 53 | "0110111101011100010", 54 | "0110111001011100011", 55 | "0110110101010101100", 56 | "0110110001000111111", 57 | "0110101100110011011", 58 | "0110101000011000010", 59 | "0110100011110110100", 60 | "0110011111001110001", 61 | "0110011010011111011", 62 | "0110010101101010001", 63 | "0110010000101110101", 64 | "0110001011101100110", 65 | "0110000110100100110", 66 | "0110000001010110101", 67 | "0101111100000010100", 68 | "0101110110101000100", 69 | "0101110001001000100", 70 | "0101101011100010111", 71 | "0101100101110111100", 72 | "0101100000000110100", 73 | "0101011010010000001", 74 | "0101010100010100010", 75 | "0101001110010011000", 76 | "0101001000001100101", 77 | "0101000010000001000", 78 | "0100111011110000100", 79 | "0100110101011011000", 80 | "0100101111000000101", 81 | "0100101000100001101", 82 | "0100100001111101111", 83 | "0100011011010101101" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_exp is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0101100010111000000", 21 | "0101100110110000000", 22 | "0101101010101010000", 23 | "0101101110100110000", 24 | "0101110010100110000", 25 | "0101110110101000000", 26 | "0101111010101101000", 27 | "0101111110110101000", 28 | "0110000011000000000", 29 | "0110000111001110000", 30 | "0110001011011110000", 31 | "0110001111110010000", 32 | "0110010100001001000", 33 | "0110011000100010000", 34 | "0110011100111111000", 35 | "0110100001011111000", 36 | "0110100110000010000", 37 | "0110101010101000000", 38 | "0110101111010001000", 39 | "0110110011111110000", 40 | "0110111000101110000", 41 | "0110111101100001000", 42 | "0111000010010111000", 43 | "0111000111010001000", 44 | "0111001100001110000", 45 | "0111010001001111000", 46 | "0111010110010011000", 47 | "0111011011011011000", 48 | "0111100000100110000", 49 | "0111100101110101000", 50 | "0111101011001000000", 51 | "0111110000011110000", 52 | "0111110101111000000", 53 | "0111111011010110000", 54 | "1000000000111000000", 55 | "1000000110011101000", 56 | "1000001100000110000", 57 | "1000010001110100000", 58 | "1000010111100101000", 59 | "1000011101011010000", 60 | "1000100011010011000", 61 | "1000101001010001000", 62 | "1000101111010010000", 63 | "1000110101011000000", 64 | "1000111011100010000", 65 | "1001000001110001000", 66 | "1001001000000011000", 67 | "1001001110011010000", 68 | "1001010100110110000", 69 | "1001011011010110000", 70 | "1001100001111010000", 71 | "1001101000100011000", 72 | "1001101111010001000", 73 | "1001110110000011000", 74 | "1001111100111010000", 75 | "1010000011110110000", 76 | "1010001010110111000", 77 | "1010010001111101000", 78 | "1010011001000111000", 79 | "1010100000010111000", 80 | "1010100111101011000", 81 | "1010101111000101000", 82 | "1010110110100100000", 83 | "1010111110001000000" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C1_sin.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C1_sin is 6 | generic( 7 | word_bits :natural:=19; 8 | bus_bits :natural:=20; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C1_sin is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1000000000000000101", 21 | "0111111111111100101", 22 | "0111111111110000110", 23 | "0111111111011100110", 24 | "0111111111000000110", 25 | "0111111110011100110", 26 | "0111111101110000110", 27 | "0111111100111100111", 28 | "0111111100000001000", 29 | "0111111010111101010", 30 | "0111111001110001100", 31 | "0111111000011101111", 32 | "0111110111000010011", 33 | "0111110101011111000", 34 | "0111110011110011110", 35 | "0111110010000000110", 36 | "0111110000000110000", 37 | "0111101110000011100", 38 | "0111101011111001001", 39 | "0111101001100111010", 40 | "0111100111001101101", 41 | "0111100100101100011", 42 | "0111100010000011101", 43 | "0111011111010011011", 44 | "0111011100011011100", 45 | "0111011001011100010", 46 | "0111010110010101101", 47 | "0111010011000111101", 48 | "0111001111110010011", 49 | "0111001100010101110", 50 | "0111001000110010000", 51 | "0111000101000111001", 52 | "0111000001010101010", 53 | "0110111101011100010", 54 | "0110111001011100011", 55 | "0110110101010101100", 56 | "0110110001000111111", 57 | "0110101100110011011", 58 | "0110101000011000010", 59 | "0110100011110110100", 60 | "0110011111001110001", 61 | "0110011010011111011", 62 | "0110010101101010001", 63 | "0110010000101110101", 64 | "0110001011101100110", 65 | "0110000110100100110", 66 | "0110000001010110101", 67 | "0101111100000010100", 68 | "0101110110101000100", 69 | "0101110001001000100", 70 | "0101101011100010111", 71 | "0101100101110111100", 72 | "0101100000000110100", 73 | "0101011010010000001", 74 | "0101010100010100010", 75 | "0101001110010011000", 76 | "0101001000001100101", 77 | "0101000010000001000", 78 | "0100111011110000100", 79 | "0100110101011011000", 80 | "0100101111000000101", 81 | "0100101000100001101", 82 | "0100100001111101111", 83 | "0100011011010101101" 84 | ); 85 | begin 86 | data <= "0"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Golden model/dec2hex754.m: -------------------------------------------------------------------------------- 1 | function y = dec2hex754(x) 2 | % The sign 3 | sign = '0'; 4 | if x < 0 5 | sign = '1'; 6 | x = x*-1; 7 | end 8 | 9 | num = dec2bin754(x); 10 | 11 | % Get the position of the dot and the 1's 12 | id_dot = strfind(num(1,:),"."); 13 | id_one = strfind(num(1,:),"1"); 14 | 15 | % Get the exponent 16 | if id_dot-id_one(1) == 0 17 | exp = 0; 18 | man = num(id_one(1)+1:end); 19 | elseif id_dot-id_one(1) > 0 20 | exp = id_dot-id_one(1)-1; 21 | 22 | if exp >= 25 23 | num = dec2bin(x,0); 24 | man = num(2:26); 25 | else 26 | % Recalculate the number 27 | num = dec2bin(x,25-(id_dot-id_one(1)-1)); 28 | num(:,id_dot)=[]; 29 | man = num(id_one(1)+1:end); 30 | end 31 | else 32 | exp = id_dot-id_one(1); 33 | 34 | % Recalculate the number 35 | num = dec2bin(x,25+(id_one(1)-id_dot)); 36 | man = num(id_one(1)+1:end); 37 | end 38 | 39 | % The aproximation to the next... 40 | if (man(end-1)=='1') 41 | %man(end)=='1' && man(end-1)=='1' ||... 42 | %man(end)=='0' && man(end-1)=='1' ||... %* | man(end-1)=='1' && man(end-2)=='1' ||... 43 | %man(end)=='1' && man(end-1)=='1' && man(end-2)=='1' 44 | 45 | man = dec2bin(bin2dec(strcat(man(1:end-2),'.0'))+1,0); 46 | 47 | if size(man,2) < 23 48 | man = strcat(char(zeros(1,23-size(man,2))+48),man); 49 | elseif size(man,2) > 23 50 | man = man(2:end); 51 | exp = exp+1; 52 | end 53 | else 54 | man = man(1:end-2); 55 | end 56 | 57 | % Normalization of the exponent 58 | exp = dec2bin(exp+127,0); 59 | if size(exp,2)<8 60 | exp = strcat(char(zeros(1,8-size(exp,2))+48),exp); 61 | end 62 | 63 | res = strcat(sign,exp,man); 64 | 65 | % Get the representation in hexadecimal 66 | y = ''; 67 | while size(res,2)~=0 68 | if res(1:4)=="1010" 69 | y = strcat(y,'A'); 70 | elseif res(1:4)=="1011" 71 | y = strcat(y,'B'); 72 | elseif res(1:4)=="1100" 73 | y = strcat(y,'C'); 74 | elseif res(1:4)=="1101" 75 | y = strcat(y,'D'); 76 | elseif res(1:4)=="1110" 77 | y = strcat(y,'E'); 78 | elseif res(1:4)=="1111" 79 | y = strcat(y,'F'); 80 | else 81 | y = strcat(y,char(bin2dec(strcat(res(1:4),'.0'))+48)); 82 | end 83 | res(1:4)=[]; 84 | end 85 | end -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C0_sqrt_1_2.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C0_sqrt_1_2 is 6 | generic( 7 | word_bits :natural:=24; 8 | bus_bits :natural:=29; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C0_sqrt_1_2 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "000000000000000000000000", 21 | "000000111111110000001000", 22 | "000001111111000000111110", 23 | "000010111101110011010010", 24 | "000011111100000111101101", 25 | "000100111001111110111001", 26 | "000101110111011001100001", 27 | "000110110100011000001001", 28 | "000111110000111011011001", 29 | "001000101101000011110101", 30 | "001001101000110001111111", 31 | "001010100100000110011010", 32 | "001011011111000001100110", 33 | "001100011001100100000100", 34 | "001101010011101110010010", 35 | "001110001101100000101101", 36 | "001111000110111011110011", 37 | "010000000000000000000000", 38 | "010000111000101101101110", 39 | "010001110001000101011000", 40 | "010010101001000111010111", 41 | "010011100000110100000100", 42 | "010100011000001011110111", 43 | "010101001111001111000111", 44 | "010110000101111110001011", 45 | "010110111100011001011000", 46 | "010111110010100001000101", 47 | "011000101000010101100110", 48 | "011001011101110111001110", 49 | "011010010011000110010011", 50 | "011011001000000011000110", 51 | "011011111100101101111010", 52 | "011100110001000111000010", 53 | "011101100101001110101111", 54 | "011110011001000101010011", 55 | "011111001100101010111101", 56 | "100000000000000000000000", 57 | "100000110011000100101001", 58 | "100001100101111001001010", 59 | "100010011000011101110000", 60 | "100011001010110010101011", 61 | "100011111100111000001010", 62 | "100100101110101110011010", 63 | "100101100000010101101001", 64 | "100110010001101110000101", 65 | "100111000010110111111011", 66 | "100111110011110011010111", 67 | "101000100100100000100110", 68 | "101001010100111111110101", 69 | "101010000101010001001111", 70 | "101010110101010101000000", 71 | "101011100101001011010011", 72 | "101100010100110100010100", 73 | "101101000100010000001110", 74 | "101101110011011111001011", 75 | "101110100010100001010110", 76 | "101111010001010110111010", 77 | "110000000000000000000000", 78 | "110000101110011100110001", 79 | "110001011100101101011001", 80 | "110010001010110010000000", 81 | "110010111000101010110000", 82 | "110011100110010111110001", 83 | "110100010011111001001101" 84 | ); 85 | begin 86 | data <= "010"&rom(to_integer(unsigned(addr)))&"00"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C0_exp.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C0_exp is 6 | generic( 7 | word_bits :natural:=25; 8 | bus_bits :natural:=29; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C0_exp is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0000000000000000000000000", 21 | "0000001011001001101001000", 22 | "0000010110011011000011010", 23 | "0000100001110100010100011", 24 | "0000101101010101100001101", 25 | "0000111000111110110000110", 26 | "0001000100110000000111010", 27 | "0001010000101001101010110", 28 | "0001011100101011100000111", 29 | "0001101000110101101111101", 30 | "0001110101001000011100110", 31 | "0010000001100011101110001", 32 | "0010001110000111101001110", 33 | "0010011010110100010101101", 34 | "0010100111101001110111110", 35 | "0010110100101000010110101", 36 | "0011000001101111111000001", 37 | "0011001111000000100010110", 38 | "0011011100011010011100111", 39 | "0011101001111101101100110", 40 | "0011110111101010011001001", 41 | "0100000101100000101000100", 42 | "0100010011100000100001100", 43 | "0100100001101010001010111", 44 | "0100101111111101101011010", 45 | "0100111110011011001001111", 46 | "0101001101000010101101011", 47 | "0101011011110100011100111", 48 | "0101101010110000011111011", 49 | "0101111001110110111100011", 50 | "0110001001000111111010110", 51 | "0110011000100011100010000", 52 | "0110101000001001111001101", 53 | "0110110111111011001000111", 54 | "0111000111110111010111101", 55 | "0111010111111110101101011", 56 | "0111101000010001010001110", 57 | "0111111000101111001100111", 58 | "1000001001011000100110011", 59 | "1000011010001101100110011", 60 | "1000101011001110010101000", 61 | "1000111100011010111010011", 62 | "1001001101110011011110110", 63 | "1001011111011000001010100", 64 | "1001110001001001000110000", 65 | "1010000011000110011001111", 66 | "1010010101010000001110110", 67 | "1010100111100110101101011", 68 | "1010111010001001111110011", 69 | "1011001100111010001010111", 70 | "1011011111110111011011110", 71 | "1011110011000001111010010", 72 | "1100000110011001101111100", 73 | "1100011001111111000100110", 74 | "1100101101110010000011100", 75 | "1101000001110010110101001", 76 | "1101010110000001100011100", 77 | "1101101010011110011000000", 78 | "1101111111001001011100110", 79 | "1110010100000010111011101", 80 | "1110101001001010111110100", 81 | "1110111110100001101111110", 82 | "1111010100000111011001011", 83 | "1111101001111100000110000" 84 | ); 85 | begin 86 | data <= "01"&rom(to_integer(unsigned(addr)))&"00"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/RRO/Components/fp_leading_zeros_and_shift.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- FP leading zeros and normalization (fp_leading_zeros_and_shift.vhd) 3 | -- 4 | -- The fractional P includes the guard digits and the sticky bit. 5 | -- Returns the normalized number and the adjusted exponent 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity fp_leading_zeros_and_shift is 14 | generic ( 15 | P :natural:=27; 16 | E :natural:=8; 17 | PLOG :natural:=4 18 | ); 19 | port( 20 | frac :in std_logic_vector(P downto 0); 21 | exp :in std_logic_vector(E-1 downto 0); 22 | frac_Norm :out std_logic_vector(P downto 0); 23 | exp_Norm :out std_logic_vector(E-1 downto 0); 24 | underFlow :out std_logic 25 | ); 26 | end entity; 27 | 28 | architecture behav of fp_leading_zeros_and_shift is 29 | constant ZEROS :std_logic_vector(P downto 0):=(others => '0'); 30 | signal leadZerosBin :std_logic_vector(PLOG downto 0); 31 | signal exp_Norm_int :std_logic_vector(E-1 downto 0); 32 | signal isZ :std_logic; 33 | begin 34 | --count zeros: elegant version. 35 | detectZeros: process(frac, exp) 36 | variable leadZerosBinVar : std_logic_vector(PLOG downto 0); 37 | begin 38 | leadZerosBinVar := ZEROS(PLOG downto 0); 39 | for i in P downto 1 loop 40 | if (frac(P-1 downto P-i) = ZEROS(P-1 downto P-i)) then 41 | leadZerosBinVar := std_logic_vector(to_unsigned(i,PLOG+1)); 42 | exit; 43 | end if; 44 | end loop; 45 | leadZerosBin <= leadZerosBinVar; 46 | end process; 47 | 48 | adjustExponent: process(leadZerosBin,exp,isZ) 49 | begin 50 | if isZ = '1' then 51 | exp_Norm_int <= (others => '0'); 52 | else 53 | exp_Norm_int <= std_logic_vector(unsigned(exp) - unsigned("000" & leadZerosBin)); 54 | end if; 55 | end process; 56 | 57 | isZ <= '1' when frac(P-1 downto 0) = ZEROS (P-1 downto 0) else '0'; 58 | underFlow <= '0' when isZ='0' and exp > leadZerosBin else '1'; 59 | exp_Norm <= exp_Norm_int; 60 | 61 | shift: process(leadZerosBin, frac) 62 | variable temp : std_logic_vector(P downto 0); 63 | variable dtemp : std_logic_vector(P downto 0); 64 | variable fracAgnVar : std_logic_vector(P downto 0); 65 | begin 66 | temp := frac; 67 | for i in PLOG downto 0 loop 68 | if (leadZerosBin(i) = '1') then 69 | dtemp := (others => '0'); 70 | dtemp(P downto 2**i) := temp(P - 2**i downto 0); 71 | else 72 | dtemp := temp; 73 | end if; 74 | temp := dtemp; 75 | end loop; 76 | frac_Norm <= dtemp; 77 | end process; 78 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_11/SFU/RRO/Components/fp_leading_zeros_and_shift.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- FP leading zeros and normalization (fp_leading_zeros_and_shift.vhd) 3 | -- 4 | -- The fractional P includes the guard digits and the sticky bit. 5 | -- Returns the normalized number and the adjusted exponent 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity fp_leading_zeros_and_shift is 14 | generic ( 15 | P :natural:=27; 16 | E :natural:=8; 17 | PLOG :natural:=4 18 | ); 19 | port( 20 | frac :in std_logic_vector(P downto 0); 21 | exp :in std_logic_vector(E-1 downto 0); 22 | frac_Norm :out std_logic_vector(P downto 0); 23 | exp_Norm :out std_logic_vector(E-1 downto 0); 24 | underFlow :out std_logic 25 | ); 26 | end entity; 27 | 28 | architecture behav of fp_leading_zeros_and_shift is 29 | constant ZEROS :std_logic_vector(P downto 0):=(others => '0'); 30 | signal leadZerosBin :std_logic_vector(PLOG downto 0); 31 | signal exp_Norm_int :std_logic_vector(E-1 downto 0); 32 | signal isZ :std_logic; 33 | begin 34 | --count zeros: elegant version. 35 | detectZeros: process(frac, exp) 36 | variable leadZerosBinVar : std_logic_vector(PLOG downto 0); 37 | begin 38 | leadZerosBinVar := ZEROS(PLOG downto 0); 39 | for i in P downto 1 loop 40 | if (frac(P-1 downto P-i) = ZEROS(P-1 downto P-i)) then 41 | leadZerosBinVar := std_logic_vector(to_unsigned(i,PLOG+1)); 42 | exit; 43 | end if; 44 | end loop; 45 | leadZerosBin <= leadZerosBinVar; 46 | end process; 47 | 48 | adjustExponent: process(leadZerosBin,exp,isZ) 49 | begin 50 | if isZ = '1' then 51 | exp_Norm_int <= (others => '0'); 52 | else 53 | exp_Norm_int <= std_logic_vector(unsigned(exp) - unsigned("000" & leadZerosBin)); 54 | end if; 55 | end process; 56 | 57 | isZ <= '1' when frac(P-1 downto 0) = ZEROS (P-1 downto 0) else '0'; 58 | underFlow <= '0' when isZ='0' and exp > leadZerosBin else '1'; 59 | exp_Norm <= exp_Norm_int; 60 | 61 | shift: process(leadZerosBin, frac) 62 | variable temp : std_logic_vector(P downto 0); 63 | variable dtemp : std_logic_vector(P downto 0); 64 | variable fracAgnVar : std_logic_vector(P downto 0); 65 | begin 66 | temp := frac; 67 | for i in PLOG downto 0 loop 68 | if (leadZerosBin(i) = '1') then 69 | dtemp := (others => '0'); 70 | dtemp(P downto 2**i) := temp(P - 2**i downto 0); 71 | else 72 | dtemp := temp; 73 | end if; 74 | temp := dtemp; 75 | end loop; 76 | frac_Norm <= dtemp; 77 | end process; 78 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/RRO/Components/fp_leading_zeros_and_shift.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- FP leading zeros and normalization (fp_leading_zeros_and_shift.vhd) 3 | -- 4 | -- The fractional P includes the guard digits and the sticky bit. 5 | -- Returns the normalized number and the adjusted exponent 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity fp_leading_zeros_and_shift is 14 | generic ( 15 | P :natural:=27; 16 | E :natural:=8; 17 | PLOG :natural:=4 18 | ); 19 | port( 20 | frac :in std_logic_vector(P downto 0); 21 | exp :in std_logic_vector(E-1 downto 0); 22 | frac_Norm :out std_logic_vector(P downto 0); 23 | exp_Norm :out std_logic_vector(E-1 downto 0); 24 | underFlow :out std_logic 25 | ); 26 | end entity; 27 | 28 | architecture behav of fp_leading_zeros_and_shift is 29 | constant ZEROS :std_logic_vector(P downto 0):=(others => '0'); 30 | signal leadZerosBin :std_logic_vector(PLOG downto 0); 31 | signal exp_Norm_int :std_logic_vector(E-1 downto 0); 32 | signal isZ :std_logic; 33 | begin 34 | --count zeros: elegant version. 35 | detectZeros: process(frac, exp) 36 | variable leadZerosBinVar : std_logic_vector(PLOG downto 0); 37 | begin 38 | leadZerosBinVar := ZEROS(PLOG downto 0); 39 | for i in P downto 1 loop 40 | if (frac(P-1 downto P-i) = ZEROS(P-1 downto P-i)) then 41 | leadZerosBinVar := std_logic_vector(to_unsigned(i,PLOG+1)); 42 | exit; 43 | end if; 44 | end loop; 45 | leadZerosBin <= leadZerosBinVar; 46 | end process; 47 | 48 | adjustExponent: process(leadZerosBin,exp,isZ) 49 | begin 50 | if isZ = '1' then 51 | exp_Norm_int <= (others => '0'); 52 | else 53 | exp_Norm_int <= std_logic_vector(unsigned(exp) - unsigned("000" & leadZerosBin)); 54 | end if; 55 | end process; 56 | 57 | isZ <= '1' when frac(P-1 downto 0) = ZEROS (P-1 downto 0) else '0'; 58 | underFlow <= '0' when isZ='0' and exp > leadZerosBin else '1'; 59 | exp_Norm <= exp_Norm_int; 60 | 61 | shift: process(leadZerosBin, frac) 62 | variable temp : std_logic_vector(P downto 0); 63 | variable dtemp : std_logic_vector(P downto 0); 64 | variable fracAgnVar : std_logic_vector(P downto 0); 65 | begin 66 | temp := frac; 67 | for i in PLOG downto 0 loop 68 | if (leadZerosBin(i) = '1') then 69 | dtemp := (others => '0'); 70 | dtemp(P downto 2**i) := temp(P - 2**i downto 0); 71 | else 72 | dtemp := temp; 73 | end if; 74 | temp := dtemp; 75 | end loop; 76 | frac_Norm <= dtemp; 77 | end process; 78 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_13/SFU/RRO/Components/fp_leading_zeros_and_shift.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- FP leading zeros and normalization (fp_leading_zeros_and_shift.vhd) 3 | -- 4 | -- The fractional P includes the guard digits and the sticky bit. 5 | -- Returns the normalized number and the adjusted exponent 6 | -- Used in FP add of section 12.5.1 7 | ---------------------------------------------------------------------------------- 8 | 9 | library ieee; 10 | use ieee.std_logic_1164.all; 11 | use ieee.numeric_std.all; 12 | 13 | entity fp_leading_zeros_and_shift is 14 | generic ( 15 | P :natural:=27; 16 | E :natural:=8; 17 | PLOG :natural:=4 18 | ); 19 | port( 20 | frac :in std_logic_vector(P downto 0); 21 | exp :in std_logic_vector(E-1 downto 0); 22 | frac_Norm :out std_logic_vector(P downto 0); 23 | exp_Norm :out std_logic_vector(E-1 downto 0); 24 | underFlow :out std_logic 25 | ); 26 | end entity; 27 | 28 | architecture behav of fp_leading_zeros_and_shift is 29 | constant ZEROS :std_logic_vector(P downto 0):=(others => '0'); 30 | signal leadZerosBin :std_logic_vector(PLOG downto 0); 31 | signal exp_Norm_int :std_logic_vector(E-1 downto 0); 32 | signal isZ :std_logic; 33 | begin 34 | --count zeros: elegant version. 35 | detectZeros: process(frac, exp) 36 | variable leadZerosBinVar : std_logic_vector(PLOG downto 0); 37 | begin 38 | leadZerosBinVar := ZEROS(PLOG downto 0); 39 | for i in P downto 1 loop 40 | if (frac(P-1 downto P-i) = ZEROS(P-1 downto P-i)) then 41 | leadZerosBinVar := std_logic_vector(to_unsigned(i,PLOG+1)); 42 | exit; 43 | end if; 44 | end loop; 45 | leadZerosBin <= leadZerosBinVar; 46 | end process; 47 | 48 | adjustExponent: process(leadZerosBin,exp,isZ) 49 | begin 50 | if isZ = '1' then 51 | exp_Norm_int <= (others => '0'); 52 | else 53 | exp_Norm_int <= std_logic_vector(unsigned(exp) - unsigned("000" & leadZerosBin)); 54 | end if; 55 | end process; 56 | 57 | isZ <= '1' when frac(P-1 downto 0) = ZEROS (P-1 downto 0) else '0'; 58 | underFlow <= '0' when isZ='0' and exp > leadZerosBin else '1'; 59 | exp_Norm <= exp_Norm_int; 60 | 61 | shift: process(leadZerosBin, frac) 62 | variable temp : std_logic_vector(P downto 0); 63 | variable dtemp : std_logic_vector(P downto 0); 64 | variable fracAgnVar : std_logic_vector(P downto 0); 65 | begin 66 | temp := frac; 67 | for i in PLOG downto 0 loop 68 | if (leadZerosBin(i) = '1') then 69 | dtemp := (others => '0'); 70 | dtemp(P downto 2**i) := temp(P - 2**i downto 0); 71 | else 72 | dtemp := temp; 73 | end if; 74 | temp := dtemp; 75 | end loop; 76 | frac_Norm <= dtemp; 77 | end process; 78 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C0_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C0_ln2e0 is 6 | generic( 7 | word_bits :natural:=25; 8 | bus_bits :natural:=29; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C0_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "1110001010101000111010110", 21 | "1101110011110010110011110", 22 | "1101011101011010011011010", 23 | "1101000111011110110001000", 24 | "1100110001111110110111100", 25 | "1100011100111001110100100", 26 | "1100001000001110110000010", 27 | "1011110011111100110101100", 28 | "1011100000000011010001100", 29 | "1011001100100001010011110", 30 | "1010111001010110001101101", 31 | "1010100110100001010010111", 32 | "1010010100000001111000111", 33 | "1010000001110111010110111", 34 | "1001110000000001000101111", 35 | "1001011110011110100000010", 36 | "1001001101001111000010001", 37 | "1000111100010010001001000", 38 | "1000101011100111010011110", 39 | "1000011011001110000010011", 40 | "1000001011000101110110011", 41 | "0111111011001110010010011", 42 | "0111101011100110111001110", 43 | "0111011100001111010001100", 44 | "0111001101000110111111001", 45 | "0110111110001101101001100", 46 | "0110101111100010111000000", 47 | "0110100001000110010011010", 48 | "0110010010110111100100011", 49 | "0110000100110110010101110", 50 | "0101110111000010010001111", 51 | "0101101001011011000100101", 52 | "0101011100000000011010001", 53 | "0101001110110001111111010", 54 | "0101000001101111100001101", 55 | "0100110100111000101111011", 56 | "0100101000001101010111010", 57 | "0100011011101101001000110", 58 | "0100001111010111110011011", 59 | "0100000011001101000111110", 60 | "0011110111001100110110101", 61 | "0011101011010110110001010", 62 | "0011011111101010101001100", 63 | "0011010100001000010001101", 64 | "0011001000101111011100000", 65 | "0010111101011111111011111", 66 | "0010110010011001100100100", 67 | "0010100111011100001001110", 68 | "0010011100100111011111111", 69 | "0010010001111011011011000", 70 | "0010000111010111110000011", 71 | "0001111100111100010100110", 72 | "0001110010101000111101110", 73 | "0001101000011101100001000", 74 | "0001011110011001110100101", 75 | "0001010100011101101111000", 76 | "0001001010101001000110011", 77 | "0001000000111011110001111", 78 | "0000110111010101101000011", 79 | "0000101101110110100001010", 80 | "0000100100011110010100000", 81 | "0000011011001100111000011", 82 | "0000010010000010000110010", 83 | "0000001000111101110110000" 84 | ); 85 | begin 86 | data <= "010"&rom(to_integer(unsigned(addr)))&"0"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C0_sqrt_2_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C0_sqrt_2_4 is 6 | generic( 7 | word_bits :natural:=25; 8 | bus_bits :natural:=29; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C0_sqrt_2_4 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "0110101000001001111001101", 21 | "0110110011011011001010111", 22 | "0110111110100110111010100", 23 | "0111001001101101010000011", 24 | "0111010100101110010100010", 25 | "0111011111101010001101011", 26 | "0111101010100001000011010", 27 | "0111110101010010111100100", 28 | "1000000000000000000000000", 29 | "1000001010101000010100000", 30 | "1000010101001011111110110", 31 | "1000011111101011000110011", 32 | "1000101010000101110000100", 33 | "1000110100011100000011000", 34 | "1000111110101110000011000", 35 | "1001001000111011110101111", 36 | "1001010011000101100000111", 37 | "1001011101001011001000110", 38 | "1001100111001100110010011", 39 | "1001110001001010100010010", 40 | "1001111011000100011101001", 41 | "1010000100111010100111001", 42 | "1010001110101101000100101", 43 | "1010011000011011111001101", 44 | "1010100010000111001010010", 45 | "1010101011101110111010011", 46 | "1010110101010011001101101", 47 | "1010111110110100000111110", 48 | "1011001000010001101100011", 49 | "1011010001101011111111000", 50 | "1011011011000011000010111", 51 | "1011100100010110111011010", 52 | "1011101101100111101011101", 53 | "1011110110110101010110110", 54 | "1100000000000000000000000", 55 | "1100001001000111101010000", 56 | "1100010010001100011000000", 57 | "1100011011001110001100100", 58 | "1100100100001101001010011", 59 | "1100101101001001010100011", 60 | "1100110110000010101101000", 61 | "1100111110111001010110111", 62 | "1101000111101101010100100", 63 | "1101010000011110101000001", 64 | "1101011001001101010100011", 65 | "1101100001111001011011100", 66 | "1101101010100010111111110", 67 | "1101110011001010000011010", 68 | "1101111011101110101000010", 69 | "1110000100010000110000111", 70 | "1110001100110000011111001", 71 | "1110010101001101110101001", 72 | "1110011101101000110100111", 73 | "1110100110000001100000001", 74 | "1110101110010111111001000", 75 | "1110110110101100000001010", 76 | "1110111110111101111010110", 77 | "1111000111001101100111001", 78 | "1111001111011011001000010", 79 | "1111010111100110011111111", 80 | "1111011111101111101111101", 81 | "1111100111110110111001001", 82 | "1111101111111011111101111", 83 | "1111110111111110111111110" 84 | ); 85 | begin 86 | data <= "01"&rom(to_integer(unsigned(addr)))&"00"; 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_00/Verification/2_Generate_input_data.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | from datetime import datetime 8 | 9 | now = datetime.now() 10 | 11 | dir_name_result = "SFU_Input_data_"+now.strftime("%d_%m_%Y_%H_%M_%S") 12 | 13 | current_path=os.getcwd() 14 | os.system("Xcopy /E /I SFU_Input_data"+" "+dir_name_result) 15 | 16 | os.system("rmdir /s /q SFU_Input_data") 17 | os.system("mkdir SFU_Input_data") 18 | 19 | 20 | N_DATA=20000 21 | 22 | sin_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 23 | cos_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 24 | rsqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 25 | log2_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 26 | exp2_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 27 | rcp_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 28 | sqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 29 | 30 | #plt.plot(sqrt_ran_dat) 31 | #plt.show() 32 | 33 | 34 | # random data generation for sine operation test of SFU 35 | Special_conditions=[] 36 | Special_conditions.append("ffffffff") #NAN 37 | Special_conditions.append("ff800000") #-inf 38 | Special_conditions.append("80000001") #-subnorm 39 | Special_conditions.append("80000000") #-0 40 | Special_conditions.append("00000000") #+0 41 | Special_conditions.append("00000001") #+subnorm 42 | Special_conditions.append("7f800000") #+inf 43 | Special_conditions.append("7fffffff") #NAN 44 | 45 | X=[] 46 | X.extend(Special_conditions) 47 | X.extend(mf.float2hex(sin_ran_dat)) 48 | X.insert(0,"celldata") 49 | mf.write_files("./SFU_Input_data/input_sin.csv",X) 50 | 51 | X.clear() 52 | X.extend(Special_conditions) 53 | X.extend(mf.float2hex(cos_ran_dat)) 54 | X.insert(0,"celldata") 55 | mf.write_files("./SFU_Input_data/input_cos.csv",X) 56 | 57 | X.clear() 58 | X.extend(Special_conditions) 59 | X.extend(mf.float2hex(rsqrt_ran_dat)) 60 | X.insert(0,"celldata") 61 | mf.write_files("./SFU_Input_data/input_rsqrt.csv",X) 62 | 63 | X.clear() 64 | X.extend(Special_conditions) 65 | X.extend(mf.float2hex(log2_ran_dat)) 66 | X.insert(0,"celldata") 67 | mf.write_files("./SFU_Input_data/input_log2.csv",X) 68 | 69 | X.clear() 70 | X.extend(Special_conditions) 71 | X.extend(mf.float2hex(exp2_ran_dat)) 72 | X.insert(0,"celldata") 73 | mf.write_files("./SFU_Input_data/input_ex2.csv",X) 74 | 75 | X.clear() 76 | X.extend(Special_conditions) 77 | X.extend(mf.float2hex(rcp_ran_dat)) 78 | X.insert(0,"celldata") 79 | mf.write_files("./SFU_Input_data/input_rcp.csv",X) 80 | 81 | X.clear() 82 | X.extend(Special_conditions) 83 | X.extend(mf.float2hex(sqrt_ran_dat)) 84 | X.insert(0,"celldata") 85 | mf.write_files("./SFU_Input_data/input_sqrt.csv",X) 86 | 87 | print("data generated sucessfully....\r\n") 88 | -------------------------------------------------------------------------------- /Description/SFU_11/Verification/2_Generate_input_data.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | from datetime import datetime 8 | 9 | now = datetime.now() 10 | 11 | dir_name_result = "SFU_Input_data_"+now.strftime("%d_%m_%Y_%H_%M_%S") 12 | 13 | current_path=os.getcwd() 14 | os.system("Xcopy /E /I SFU_Input_data"+" "+dir_name_result) 15 | 16 | os.system("rmdir /s /q SFU_Input_data") 17 | os.system("mkdir SFU_Input_data") 18 | 19 | 20 | N_DATA=20000 21 | 22 | sin_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 23 | cos_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 24 | rsqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 25 | log2_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 26 | exp2_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 27 | rcp_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 28 | sqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 29 | 30 | #plt.plot(sqrt_ran_dat) 31 | #plt.show() 32 | 33 | 34 | # random data generation for sine operation test of SFU 35 | Special_conditions=[] 36 | Special_conditions.append("ffffffff") #NAN 37 | Special_conditions.append("ff800000") #-inf 38 | Special_conditions.append("80000001") #-subnorm 39 | Special_conditions.append("80000000") #-0 40 | Special_conditions.append("00000000") #+0 41 | Special_conditions.append("00000001") #+subnorm 42 | Special_conditions.append("7f800000") #+inf 43 | Special_conditions.append("7fffffff") #NAN 44 | 45 | X=[] 46 | X.extend(Special_conditions) 47 | X.extend(mf.float2hex(sin_ran_dat)) 48 | X.insert(0,"celldata") 49 | mf.write_files("./SFU_Input_data/input_sin.csv",X) 50 | 51 | X.clear() 52 | X.extend(Special_conditions) 53 | X.extend(mf.float2hex(cos_ran_dat)) 54 | X.insert(0,"celldata") 55 | mf.write_files("./SFU_Input_data/input_cos.csv",X) 56 | 57 | X.clear() 58 | X.extend(Special_conditions) 59 | X.extend(mf.float2hex(rsqrt_ran_dat)) 60 | X.insert(0,"celldata") 61 | mf.write_files("./SFU_Input_data/input_rsqrt.csv",X) 62 | 63 | X.clear() 64 | X.extend(Special_conditions) 65 | X.extend(mf.float2hex(log2_ran_dat)) 66 | X.insert(0,"celldata") 67 | mf.write_files("./SFU_Input_data/input_log2.csv",X) 68 | 69 | X.clear() 70 | X.extend(Special_conditions) 71 | X.extend(mf.float2hex(exp2_ran_dat)) 72 | X.insert(0,"celldata") 73 | mf.write_files("./SFU_Input_data/input_ex2.csv",X) 74 | 75 | X.clear() 76 | X.extend(Special_conditions) 77 | X.extend(mf.float2hex(rcp_ran_dat)) 78 | X.insert(0,"celldata") 79 | mf.write_files("./SFU_Input_data/input_rcp.csv",X) 80 | 81 | X.clear() 82 | X.extend(Special_conditions) 83 | X.extend(mf.float2hex(sqrt_ran_dat)) 84 | X.insert(0,"celldata") 85 | mf.write_files("./SFU_Input_data/input_sqrt.csv",X) 86 | 87 | print("data generated sucessfully....\r\n") 88 | -------------------------------------------------------------------------------- /Description/SFU_12/Verification/2_Generate_input_data.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | from datetime import datetime 8 | 9 | now = datetime.now() 10 | 11 | dir_name_result = "SFU_Input_data_"+now.strftime("%d_%m_%Y_%H_%M_%S") 12 | 13 | current_path=os.getcwd() 14 | os.system("Xcopy /E /I SFU_Input_data"+" "+dir_name_result) 15 | 16 | os.system("rmdir /s /q SFU_Input_data") 17 | os.system("mkdir SFU_Input_data") 18 | 19 | 20 | N_DATA=20000 21 | 22 | sin_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 23 | cos_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 24 | rsqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 25 | log2_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 26 | exp2_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 27 | rcp_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 28 | sqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 29 | 30 | #plt.plot(sqrt_ran_dat) 31 | #plt.show() 32 | 33 | 34 | # random data generation for sine operation test of SFU 35 | Special_conditions=[] 36 | Special_conditions.append("ffffffff") #NAN 37 | Special_conditions.append("ff800000") #-inf 38 | Special_conditions.append("80000001") #-subnorm 39 | Special_conditions.append("80000000") #-0 40 | Special_conditions.append("00000000") #+0 41 | Special_conditions.append("00000001") #+subnorm 42 | Special_conditions.append("7f800000") #+inf 43 | Special_conditions.append("7fffffff") #NAN 44 | 45 | X=[] 46 | X.extend(Special_conditions) 47 | X.extend(mf.float2hex(sin_ran_dat)) 48 | X.insert(0,"celldata") 49 | mf.write_files("./SFU_Input_data/input_sin.csv",X) 50 | 51 | X.clear() 52 | X.extend(Special_conditions) 53 | X.extend(mf.float2hex(cos_ran_dat)) 54 | X.insert(0,"celldata") 55 | mf.write_files("./SFU_Input_data/input_cos.csv",X) 56 | 57 | X.clear() 58 | X.extend(Special_conditions) 59 | X.extend(mf.float2hex(rsqrt_ran_dat)) 60 | X.insert(0,"celldata") 61 | mf.write_files("./SFU_Input_data/input_rsqrt.csv",X) 62 | 63 | X.clear() 64 | X.extend(Special_conditions) 65 | X.extend(mf.float2hex(log2_ran_dat)) 66 | X.insert(0,"celldata") 67 | mf.write_files("./SFU_Input_data/input_log2.csv",X) 68 | 69 | X.clear() 70 | X.extend(Special_conditions) 71 | X.extend(mf.float2hex(exp2_ran_dat)) 72 | X.insert(0,"celldata") 73 | mf.write_files("./SFU_Input_data/input_ex2.csv",X) 74 | 75 | X.clear() 76 | X.extend(Special_conditions) 77 | X.extend(mf.float2hex(rcp_ran_dat)) 78 | X.insert(0,"celldata") 79 | mf.write_files("./SFU_Input_data/input_rcp.csv",X) 80 | 81 | X.clear() 82 | X.extend(Special_conditions) 83 | X.extend(mf.float2hex(sqrt_ran_dat)) 84 | X.insert(0,"celldata") 85 | mf.write_files("./SFU_Input_data/input_sqrt.csv",X) 86 | 87 | print("data generated sucessfully....\r\n") 88 | -------------------------------------------------------------------------------- /Description/SFU_13/Verification/2_Generate_input_data.py: -------------------------------------------------------------------------------- 1 | import random 2 | import myFunctions as mf 3 | import numpy as np 4 | import matplotlib.pyplot as plt 5 | import os 6 | import subprocess 7 | from datetime import datetime 8 | 9 | now = datetime.now() 10 | 11 | dir_name_result = "SFU_Input_data_"+now.strftime("%d_%m_%Y_%H_%M_%S") 12 | 13 | current_path=os.getcwd() 14 | os.system("Xcopy /E /I SFU_Input_data"+" "+dir_name_result) 15 | 16 | os.system("rmdir /s /q SFU_Input_data") 17 | os.system("mkdir SFU_Input_data") 18 | 19 | 20 | N_DATA=20000 21 | 22 | sin_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 23 | cos_ran_dat=np.sort(np.float32(np.pi*np.random.uniform(-47.0,47.0,N_DATA))) 24 | rsqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 25 | log2_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 26 | exp2_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 27 | rcp_ran_dat=np.sort(np.float32(np.random.uniform(-47.0,47.0,N_DATA))) 28 | sqrt_ran_dat=np.sort(np.float32(np.random.uniform(0.0,47.0,N_DATA))) 29 | 30 | #plt.plot(sqrt_ran_dat) 31 | #plt.show() 32 | 33 | 34 | # random data generation for sine operation test of SFU 35 | Special_conditions=[] 36 | Special_conditions.append("ffffffff") #NAN 37 | Special_conditions.append("ff800000") #-inf 38 | Special_conditions.append("80000001") #-subnorm 39 | Special_conditions.append("80000000") #-0 40 | Special_conditions.append("00000000") #+0 41 | Special_conditions.append("00000001") #+subnorm 42 | Special_conditions.append("7f800000") #+inf 43 | Special_conditions.append("7fffffff") #NAN 44 | 45 | X=[] 46 | X.extend(Special_conditions) 47 | X.extend(mf.float2hex(sin_ran_dat)) 48 | X.insert(0,"celldata") 49 | mf.write_files("./SFU_Input_data/input_sin.csv",X) 50 | 51 | X.clear() 52 | X.extend(Special_conditions) 53 | X.extend(mf.float2hex(cos_ran_dat)) 54 | X.insert(0,"celldata") 55 | mf.write_files("./SFU_Input_data/input_cos.csv",X) 56 | 57 | X.clear() 58 | X.extend(Special_conditions) 59 | X.extend(mf.float2hex(rsqrt_ran_dat)) 60 | X.insert(0,"celldata") 61 | mf.write_files("./SFU_Input_data/input_rsqrt.csv",X) 62 | 63 | X.clear() 64 | X.extend(Special_conditions) 65 | X.extend(mf.float2hex(log2_ran_dat)) 66 | X.insert(0,"celldata") 67 | mf.write_files("./SFU_Input_data/input_log2.csv",X) 68 | 69 | X.clear() 70 | X.extend(Special_conditions) 71 | X.extend(mf.float2hex(exp2_ran_dat)) 72 | X.insert(0,"celldata") 73 | mf.write_files("./SFU_Input_data/input_ex2.csv",X) 74 | 75 | X.clear() 76 | X.extend(Special_conditions) 77 | X.extend(mf.float2hex(rcp_ran_dat)) 78 | X.insert(0,"celldata") 79 | mf.write_files("./SFU_Input_data/input_rcp.csv",X) 80 | 81 | X.clear() 82 | X.extend(Special_conditions) 83 | X.extend(mf.float2hex(sqrt_ran_dat)) 84 | X.insert(0,"celldata") 85 | mf.write_files("./SFU_Input_data/input_sqrt.csv",X) 86 | 87 | print("data generated sucessfully....\r\n") 88 | -------------------------------------------------------------------------------- /Description/SFU_11/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C0_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C0_ln2e0 is 6 | generic( 7 | word_bits :natural:=26; 8 | bus_bits :natural:=29; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C0_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "11100010101010001110101100", 21 | "11011100111100101100111100", 22 | "11010111010110100110110100", 23 | "11010001110111101100010000", 24 | "11001100011111101101111000", 25 | "11000111001110011101001000", 26 | "11000010000011101100000100", 27 | "10111100111111001101011000", 28 | "10111000000000110100011000", 29 | "10110011001000010100111100", 30 | "10101110010101100011011010", 31 | "10101001101000010100101110", 32 | "10100101000000011110001110", 33 | "10100000011101110101101110", 34 | "10011100000000010001011110", 35 | "10010111100111101000000100", 36 | "10010011010011110000100010", 37 | "10001111000100100010010000", 38 | "10001010111001110100111100", 39 | "10000110110011100000100110", 40 | "10000010110001011101100110", 41 | "01111110110011100100100110", 42 | "01111010111001101110011100", 43 | "01110111000011110100011000", 44 | "01110011010001101111110010", 45 | "01101111100011011010011000", 46 | "01101011111000101110000000", 47 | "01101000010001100100110100", 48 | "01100100101101111001000110", 49 | "01100001001101100101011100", 50 | "01011101110000100100011110", 51 | "01011010010110110001001010", 52 | "01010111000000000110100010", 53 | "01010011101100011111110100", 54 | "01010000011011111000011010", 55 | "01001101001110001011110110", 56 | "01001010000011010101110100", 57 | "01000110111011010010001100", 58 | "01000011110101111100110110", 59 | "01000000110011010001111100", 60 | "00111101110011001101101010", 61 | "00111010110101101100010100", 62 | "00110111111010101010011000", 63 | "00110101000010000100011010", 64 | "00110010001011110111000000", 65 | "00101111010111111110111110", 66 | "00101100100110011001001000", 67 | "00101001110111000010011100", 68 | "00100111001001110111111110", 69 | "00100100011110110110110000", 70 | "00100001110101111100000110", 71 | "00011111001111000101001100", 72 | "00011100101010001111011100", 73 | "00011010000111011000010000", 74 | "00010111100110011101001010", 75 | "00010101000111011011110000", 76 | "00010010101010010001100110", 77 | "00010000001110111100011110", 78 | "00001101110101011010000110", 79 | "00001011011101101000010100", 80 | "00001001000111100101000000", 81 | "00000110110011001110000110", 82 | "00000100100000100001100100", 83 | "00000010001111011101100000" 84 | ); 85 | begin 86 | data <= "010"&rom(to_integer(unsigned(addr))); 87 | end architecture; -------------------------------------------------------------------------------- /Description/SFU_12/SFU/Quadratic_Interpolator/Single_LUTS/LUT_C0_ln2e0.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | use ieee.numeric_std.all; 4 | 5 | entity LUT_C0_ln2e0 is 6 | generic( 7 | word_bits :natural:=26; 8 | bus_bits :natural:=29; 9 | add_bits :natural:=6 10 | ); 11 | port( 12 | addr :in std_logic_vector(add_bits-1 downto 0); 13 | data :out std_logic_vector(bus_bits-1 downto 0) 14 | ); 15 | end entity; 16 | 17 | architecture behav of LUT_C0_ln2e0 is 18 | type storage is array (0 to 2**add_bits-1) of std_logic_vector(word_bits-1 downto 0); 19 | signal rom:storage:=( 20 | "11100010101010001110101100", 21 | "11011100111100101100111100", 22 | "11010111010110100110110100", 23 | "11010001110111101100010000", 24 | "11001100011111101101111000", 25 | "11000111001110011101001000", 26 | "11000010000011101100000100", 27 | "10111100111111001101011000", 28 | "10111000000000110100011000", 29 | "10110011001000010100111100", 30 | "10101110010101100011011010", 31 | "10101001101000010100101110", 32 | "10100101000000011110001110", 33 | "10100000011101110101101110", 34 | "10011100000000010001011110", 35 | "10010111100111101000000100", 36 | "10010011010011110000100010", 37 | "10001111000100100010010000", 38 | "10001010111001110100111100", 39 | "10000110110011100000100110", 40 | "10000010110001011101100110", 41 | "01111110110011100100100110", 42 | "01111010111001101110011100", 43 | "01110111000011110100011000", 44 | "01110011010001101111110010", 45 | "01101111100011011010011000", 46 | "01101011111000101110000000", 47 | "01101000010001100100110100", 48 | "01100100101101111001000110", 49 | "01100001001101100101011100", 50 | "01011101110000100100011110", 51 | "01011010010110110001001010", 52 | "01010111000000000110100010", 53 | "01010011101100011111110100", 54 | "01010000011011111000011010", 55 | "01001101001110001011110110", 56 | "01001010000011010101110100", 57 | "01000110111011010010001100", 58 | "01000011110101111100110110", 59 | "01000000110011010001111100", 60 | "00111101110011001101101010", 61 | "00111010110101101100010100", 62 | "00110111111010101010011000", 63 | "00110101000010000100011010", 64 | "00110010001011110111000000", 65 | "00101111010111111110111110", 66 | "00101100100110011001001000", 67 | "00101001110111000010011100", 68 | "00100111001001110111111110", 69 | "00100100011110110110110000", 70 | "00100001110101111100000110", 71 | "00011111001111000101001100", 72 | "00011100101010001111011100", 73 | "00011010000111011000010000", 74 | "00010111100110011101001010", 75 | "00010101000111011011110000", 76 | "00010010101010010001100110", 77 | "00010000001110111100011110", 78 | "00001101110101011010000110", 79 | "00001011011101101000010100", 80 | "00001001000111100101000000", 81 | "00000110110011001110000110", 82 | "00000100100000100001100100", 83 | "00000010001111011101100000" 84 | ); 85 | begin 86 | data <= "010"&rom(to_integer(unsigned(addr))); 87 | end architecture; --------------------------------------------------------------------------------