├── .github └── workflows │ └── main.yml ├── .gitignore ├── .gitmodules ├── FPGA_Target ├── Nexys-A7 │ ├── PCore_FPGA.cache │ │ ├── ip │ │ │ └── 2019.1 │ │ │ │ ├── 1ad02aff4776235b │ │ │ │ ├── 1ad02aff4776235b.xci │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0.dcp │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_stub.v │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_stub.vhdl │ │ │ │ └── stats.txt │ │ │ │ ├── 338202550d587565 │ │ │ │ ├── 338202550d587565.xci │ │ │ │ ├── nexys_shell_axi_bram_ctrl_0_0.dcp │ │ │ │ ├── nexys_shell_axi_bram_ctrl_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_axi_bram_ctrl_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_axi_bram_ctrl_0_0_stub.v │ │ │ │ ├── nexys_shell_axi_bram_ctrl_0_0_stub.vhdl │ │ │ │ └── stats.txt │ │ │ │ ├── 4b46afa1bb8725cc │ │ │ │ ├── 4b46afa1bb8725cc.xci │ │ │ │ ├── nexys_shell_smartconnect_0_0.dcp │ │ │ │ ├── nexys_shell_smartconnect_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_smartconnect_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_smartconnect_0_0_stub.v │ │ │ │ └── nexys_shell_smartconnect_0_0_stub.vhdl │ │ │ │ ├── 7efb766302388b7c │ │ │ │ ├── 7efb766302388b7c.xci │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0.dcp │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_stub.v │ │ │ │ └── nexys_shell_proc_sys_reset_0_0_stub.vhdl │ │ │ │ ├── e004a9be8d67e29c │ │ │ │ ├── e004a9be8d67e29c.xci │ │ │ │ ├── nexys_shell_blk_mem_gen_0_0.dcp │ │ │ │ ├── nexys_shell_blk_mem_gen_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_blk_mem_gen_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_blk_mem_gen_0_0_stub.v │ │ │ │ ├── nexys_shell_blk_mem_gen_0_0_stub.vhdl │ │ │ │ └── stats.txt │ │ │ │ ├── e55fd993b8d06dc2 │ │ │ │ ├── e55fd993b8d06dc2.xci │ │ │ │ ├── nexys_shell_smartconnect_0_0.dcp │ │ │ │ ├── nexys_shell_smartconnect_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_smartconnect_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_smartconnect_0_0_stub.v │ │ │ │ └── nexys_shell_smartconnect_0_0_stub.vhdl │ │ │ │ ├── e86ee997a46ba5e2 │ │ │ │ ├── e86ee997a46ba5e2.xci │ │ │ │ ├── nexys_shell_smartconnect_0_0.dcp │ │ │ │ ├── nexys_shell_smartconnect_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_smartconnect_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_smartconnect_0_0_stub.v │ │ │ │ └── nexys_shell_smartconnect_0_0_stub.vhdl │ │ │ │ └── f5444ceac3b437cd │ │ │ │ ├── f5444ceac3b437cd.xci │ │ │ │ ├── nexys_shell_mig_7series_0_0.dcp │ │ │ │ ├── nexys_shell_mig_7series_0_0_sim_netlist.v │ │ │ │ ├── nexys_shell_mig_7series_0_0_sim_netlist.vhdl │ │ │ │ ├── nexys_shell_mig_7series_0_0_stub.v │ │ │ │ ├── nexys_shell_mig_7series_0_0_stub.vhdl │ │ │ │ └── stats.txt │ │ └── wt │ │ │ ├── gui_handlers.wdf │ │ │ ├── java_command_handlers.wdf │ │ │ ├── project.wpc │ │ │ ├── synthesis.wdf │ │ │ ├── synthesis_details.wdf │ │ │ └── webtalk_pa.xml │ ├── PCore_FPGA.hw │ │ ├── PCore_FPGA.lpr │ │ └── hw_1 │ │ │ └── hw.xml │ ├── PCore_FPGA.ip_user_files │ │ ├── README.txt │ │ ├── bd │ │ │ └── nexys_shell │ │ │ │ └── ip │ │ │ │ ├── nexys_shell_mig_7series_0_0_1 │ │ │ │ └── nexys_shell_mig_7series_0_0 │ │ │ │ │ └── user_design │ │ │ │ │ └── rtl │ │ │ │ │ ├── axi │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_addr_decode.v │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_read.v │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_reg.v │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_reg_bank.v │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_top.v │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_write.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_ar_channel.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_aw_channel.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_b_channel.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_cmd_arbiter.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_cmd_fsm.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_cmd_translator.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_incr_cmd.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_r_channel.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_simple_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_w_channel.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_wr_cmd_fsm.v │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_wrap_cmd.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_a_upsizer.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_axi_register_slice.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_axi_upsizer.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_axic_register_slice.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_and.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_latch_and.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_latch_or.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_or.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_command_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_comparator.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_comparator_sel.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_comparator_sel_static.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_r_upsizer.v │ │ │ │ │ └── mig_7series_v4_2_ddr_w_upsizer.v │ │ │ │ │ ├── clocking │ │ │ │ │ ├── mig_7series_v4_2_clk_ibuf.v │ │ │ │ │ ├── mig_7series_v4_2_infrastructure.v │ │ │ │ │ ├── mig_7series_v4_2_iodelay_ctrl.v │ │ │ │ │ └── mig_7series_v4_2_tempmon.v │ │ │ │ │ ├── controller │ │ │ │ │ ├── mig_7series_v4_2_arb_mux.v │ │ │ │ │ ├── mig_7series_v4_2_arb_row_col.v │ │ │ │ │ ├── mig_7series_v4_2_arb_select.v │ │ │ │ │ ├── mig_7series_v4_2_bank_cntrl.v │ │ │ │ │ ├── mig_7series_v4_2_bank_common.v │ │ │ │ │ ├── mig_7series_v4_2_bank_compare.v │ │ │ │ │ ├── mig_7series_v4_2_bank_mach.v │ │ │ │ │ ├── mig_7series_v4_2_bank_queue.v │ │ │ │ │ ├── mig_7series_v4_2_bank_state.v │ │ │ │ │ ├── mig_7series_v4_2_col_mach.v │ │ │ │ │ ├── mig_7series_v4_2_mc.v │ │ │ │ │ ├── mig_7series_v4_2_rank_cntrl.v │ │ │ │ │ ├── mig_7series_v4_2_rank_common.v │ │ │ │ │ ├── mig_7series_v4_2_rank_mach.v │ │ │ │ │ └── mig_7series_v4_2_round_robin_arb.v │ │ │ │ │ ├── ecc │ │ │ │ │ ├── mig_7series_v4_2_ecc_buf.v │ │ │ │ │ ├── mig_7series_v4_2_ecc_dec_fix.v │ │ │ │ │ ├── mig_7series_v4_2_ecc_gen.v │ │ │ │ │ ├── mig_7series_v4_2_ecc_merge_enc.v │ │ │ │ │ └── mig_7series_v4_2_fi_xor.v │ │ │ │ │ ├── ip_top │ │ │ │ │ ├── mig_7series_v4_2_mem_intfc.v │ │ │ │ │ └── mig_7series_v4_2_memc_ui_top_axi.v │ │ │ │ │ ├── nexys_shell_mig_7series_0_0.v │ │ │ │ │ ├── nexys_shell_mig_7series_0_0_mig_sim.v │ │ │ │ │ ├── phy │ │ │ │ │ ├── mig_7series_v4_2_ddr_byte_group_io.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_byte_lane.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_calib_top.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_if_post_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_mc_phy.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_mc_phy_wrapper.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_of_pre_fifo.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_4lanes.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_dqs_found_cal.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_init.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_cntlr.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_data.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_edge.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_lim.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_mux.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_samp.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_oclkdelay_cal.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_prbs_rdlvl.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_rdlvl.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_tempmon.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_top.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_wrcal.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_wrlvl.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v │ │ │ │ │ ├── mig_7series_v4_2_ddr_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_2_poc_cc.v │ │ │ │ │ ├── mig_7series_v4_2_poc_edge_store.v │ │ │ │ │ ├── mig_7series_v4_2_poc_meta.v │ │ │ │ │ ├── mig_7series_v4_2_poc_pd.v │ │ │ │ │ ├── mig_7series_v4_2_poc_tap_base.v │ │ │ │ │ └── mig_7series_v4_2_poc_top.v │ │ │ │ │ └── ui │ │ │ │ │ ├── mig_7series_v4_2_ui_cmd.v │ │ │ │ │ ├── mig_7series_v4_2_ui_rd_data.v │ │ │ │ │ ├── mig_7series_v4_2_ui_top.v │ │ │ │ │ └── mig_7series_v4_2_ui_wr_data.v │ │ │ │ └── nexys_shell_smartconnect_0_0_1 │ │ │ │ └── bd_0 │ │ │ │ └── bd_4cab.bd │ │ ├── mem_init_files │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── mig_a.prj │ │ │ ├── mig_b.prj │ │ │ ├── sc_post_elab.rld │ │ │ └── xlconstant_v1_1_6.h │ │ └── sim_scripts │ │ │ └── nexys_shell │ │ │ ├── README.txt │ │ │ ├── activehdl │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── nexys_shell.udo │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ └── xlconstant_v1_1_6.h │ │ │ ├── ies │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── run.f │ │ │ └── xlconstant_v1_1_6.h │ │ │ ├── modelsim │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── nexys_shell.udo │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ └── xlconstant_v1_1_6.h │ │ │ ├── questa │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── compile.do │ │ │ ├── elaborate.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── nexys_shell.udo │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ └── xlconstant_v1_1_6.h │ │ │ ├── riviera │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── compile.do │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── nexys_shell.udo │ │ │ ├── simulate.do │ │ │ ├── wave.do │ │ │ └── xlconstant_v1_1_6.h │ │ │ ├── vcs │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── simulate.do │ │ │ └── xlconstant_v1_1_6.h │ │ │ ├── xcelium │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── run.f │ │ │ └── xlconstant_v1_1_6.h │ │ │ └── xsim │ │ │ ├── README.txt │ │ │ ├── bd_4cab_one_0.h │ │ │ ├── cmd.tcl │ │ │ ├── file_info.txt │ │ │ ├── glbl.v │ │ │ ├── mig_b.prj │ │ │ ├── nexys_shell.sh │ │ │ ├── protoinst_files │ │ │ ├── bd_4cab.protoinst │ │ │ └── nexys_shell.protoinst │ │ │ ├── vhdl.prj │ │ │ ├── vlog.prj │ │ │ └── xlconstant_v1_1_6.h │ ├── PCore_FPGA.runs │ │ ├── .jobs │ │ │ ├── vrs_config_1.xml │ │ │ ├── vrs_config_10.xml │ │ │ ├── vrs_config_100.xml │ │ │ ├── vrs_config_101.xml │ │ │ ├── vrs_config_102.xml │ │ │ ├── vrs_config_103.xml │ │ │ ├── vrs_config_104.xml │ │ │ ├── vrs_config_105.xml │ │ │ ├── vrs_config_106.xml │ │ │ ├── vrs_config_107.xml │ │ │ ├── vrs_config_108.xml │ │ │ ├── vrs_config_109.xml │ │ │ ├── vrs_config_11.xml │ │ │ ├── vrs_config_110.xml │ │ │ ├── vrs_config_111.xml │ │ │ ├── vrs_config_112.xml │ │ │ ├── vrs_config_113.xml │ │ │ ├── vrs_config_114.xml │ │ │ ├── vrs_config_115.xml │ │ │ ├── vrs_config_116.xml │ │ │ ├── vrs_config_117.xml │ │ │ ├── vrs_config_118.xml │ │ │ ├── vrs_config_119.xml │ │ │ ├── vrs_config_12.xml │ │ │ ├── vrs_config_120.xml │ │ │ ├── vrs_config_121.xml │ │ │ ├── vrs_config_122.xml │ │ │ ├── vrs_config_123.xml │ │ │ ├── vrs_config_124.xml │ │ │ ├── vrs_config_125.xml │ │ │ ├── vrs_config_126.xml │ │ │ ├── vrs_config_127.xml │ │ │ ├── vrs_config_128.xml │ │ │ ├── vrs_config_129.xml │ │ │ ├── vrs_config_13.xml │ │ │ ├── vrs_config_130.xml │ │ │ ├── vrs_config_131.xml │ │ │ ├── vrs_config_132.xml │ │ │ ├── vrs_config_133.xml │ │ │ ├── vrs_config_134.xml │ │ │ ├── vrs_config_135.xml │ │ │ ├── vrs_config_136.xml │ │ │ ├── vrs_config_137.xml │ │ │ ├── vrs_config_138.xml │ │ │ ├── vrs_config_139.xml │ │ │ ├── vrs_config_14.xml │ │ │ ├── vrs_config_140.xml │ │ │ ├── vrs_config_141.xml │ │ │ ├── vrs_config_142.xml │ │ │ ├── vrs_config_143.xml │ │ │ ├── vrs_config_144.xml │ │ │ ├── vrs_config_145.xml │ │ │ ├── vrs_config_146.xml │ │ │ ├── vrs_config_147.xml │ │ │ ├── vrs_config_148.xml │ │ │ ├── vrs_config_149.xml │ │ │ ├── vrs_config_15.xml │ │ │ ├── vrs_config_150.xml │ │ │ ├── vrs_config_151.xml │ │ │ ├── vrs_config_152.xml │ │ │ ├── vrs_config_153.xml │ │ │ ├── vrs_config_154.xml │ │ │ ├── vrs_config_155.xml │ │ │ ├── vrs_config_156.xml │ │ │ ├── vrs_config_157.xml │ │ │ ├── vrs_config_158.xml │ │ │ ├── vrs_config_159.xml │ │ │ ├── vrs_config_16.xml │ │ │ ├── vrs_config_160.xml │ │ │ ├── vrs_config_161.xml │ │ │ ├── vrs_config_162.xml │ │ │ ├── vrs_config_163.xml │ │ │ ├── vrs_config_164.xml │ │ │ ├── vrs_config_165.xml │ │ │ ├── vrs_config_166.xml │ │ │ ├── vrs_config_167.xml │ │ │ ├── vrs_config_168.xml │ │ │ ├── vrs_config_169.xml │ │ │ ├── vrs_config_17.xml │ │ │ ├── vrs_config_170.xml │ │ │ ├── vrs_config_171.xml │ │ │ ├── vrs_config_172.xml │ │ │ ├── vrs_config_173.xml │ │ │ ├── vrs_config_174.xml │ │ │ ├── vrs_config_175.xml │ │ │ ├── vrs_config_176.xml │ │ │ ├── vrs_config_177.xml │ │ │ ├── vrs_config_178.xml │ │ │ ├── vrs_config_179.xml │ │ │ ├── vrs_config_18.xml │ │ │ ├── vrs_config_180.xml │ │ │ ├── vrs_config_181.xml │ │ │ ├── vrs_config_182.xml │ │ │ ├── vrs_config_183.xml │ │ │ ├── vrs_config_184.xml │ │ │ ├── vrs_config_185.xml │ │ │ ├── vrs_config_186.xml │ │ │ ├── vrs_config_187.xml │ │ │ ├── vrs_config_188.xml │ │ │ ├── vrs_config_189.xml │ │ │ ├── vrs_config_19.xml │ │ │ ├── vrs_config_190.xml │ │ │ ├── vrs_config_191.xml │ │ │ ├── vrs_config_192.xml │ │ │ ├── vrs_config_193.xml │ │ │ ├── vrs_config_194.xml │ │ │ ├── vrs_config_195.xml │ │ │ ├── vrs_config_196.xml │ │ │ ├── vrs_config_197.xml │ │ │ ├── vrs_config_198.xml │ │ │ ├── vrs_config_199.xml │ │ │ ├── vrs_config_2.xml │ │ │ ├── vrs_config_20.xml │ │ │ ├── vrs_config_200.xml │ │ │ ├── vrs_config_201.xml │ │ │ ├── vrs_config_202.xml │ │ │ ├── vrs_config_203.xml │ │ │ ├── vrs_config_204.xml │ │ │ ├── vrs_config_205.xml │ │ │ ├── vrs_config_206.xml │ │ │ ├── vrs_config_207.xml │ │ │ ├── vrs_config_208.xml │ │ │ ├── vrs_config_209.xml │ │ │ ├── vrs_config_21.xml │ │ │ ├── vrs_config_210.xml │ │ │ ├── vrs_config_211.xml │ │ │ ├── vrs_config_212.xml │ │ │ ├── vrs_config_213.xml │ │ │ ├── vrs_config_214.xml │ │ │ ├── vrs_config_215.xml │ │ │ ├── vrs_config_216.xml │ │ │ ├── vrs_config_217.xml │ │ │ ├── vrs_config_218.xml │ │ │ ├── vrs_config_219.xml │ │ │ ├── vrs_config_22.xml │ │ │ ├── vrs_config_220.xml │ │ │ ├── vrs_config_221.xml │ │ │ ├── vrs_config_222.xml │ │ │ ├── vrs_config_223.xml │ │ │ ├── vrs_config_224.xml │ │ │ ├── vrs_config_225.xml │ │ │ ├── vrs_config_226.xml │ │ │ ├── vrs_config_227.xml │ │ │ ├── vrs_config_228.xml │ │ │ ├── vrs_config_229.xml │ │ │ ├── vrs_config_23.xml │ │ │ ├── vrs_config_230.xml │ │ │ ├── vrs_config_231.xml │ │ │ ├── vrs_config_232.xml │ │ │ ├── vrs_config_233.xml │ │ │ ├── vrs_config_234.xml │ │ │ ├── vrs_config_235.xml │ │ │ ├── vrs_config_236.xml │ │ │ ├── vrs_config_237.xml │ │ │ ├── vrs_config_238.xml │ │ │ ├── vrs_config_239.xml │ │ │ ├── vrs_config_24.xml │ │ │ ├── vrs_config_240.xml │ │ │ ├── vrs_config_241.xml │ │ │ ├── vrs_config_242.xml │ │ │ ├── vrs_config_243.xml │ │ │ ├── vrs_config_244.xml │ │ │ ├── vrs_config_245.xml │ │ │ ├── vrs_config_246.xml │ │ │ ├── vrs_config_247.xml │ │ │ ├── vrs_config_248.xml │ │ │ ├── vrs_config_249.xml │ │ │ ├── vrs_config_25.xml │ │ │ ├── vrs_config_250.xml │ │ │ ├── vrs_config_251.xml │ │ │ ├── vrs_config_252.xml │ │ │ ├── vrs_config_253.xml │ │ │ ├── vrs_config_254.xml │ │ │ ├── vrs_config_255.xml │ │ │ ├── vrs_config_256.xml │ │ │ ├── vrs_config_257.xml │ │ │ ├── vrs_config_258.xml │ │ │ ├── vrs_config_259.xml │ │ │ ├── vrs_config_26.xml │ │ │ ├── vrs_config_260.xml │ │ │ ├── vrs_config_261.xml │ │ │ ├── vrs_config_262.xml │ │ │ ├── vrs_config_263.xml │ │ │ ├── vrs_config_264.xml │ │ │ ├── vrs_config_265.xml │ │ │ ├── vrs_config_266.xml │ │ │ ├── vrs_config_267.xml │ │ │ ├── vrs_config_268.xml │ │ │ ├── vrs_config_269.xml │ │ │ ├── vrs_config_27.xml │ │ │ ├── vrs_config_270.xml │ │ │ ├── vrs_config_271.xml │ │ │ ├── vrs_config_272.xml │ │ │ ├── vrs_config_273.xml │ │ │ ├── vrs_config_274.xml │ │ │ ├── vrs_config_275.xml │ │ │ ├── vrs_config_276.xml │ │ │ ├── vrs_config_277.xml │ │ │ ├── vrs_config_278.xml │ │ │ ├── vrs_config_279.xml │ │ │ ├── vrs_config_28.xml │ │ │ ├── vrs_config_280.xml │ │ │ ├── vrs_config_281.xml │ │ │ ├── vrs_config_282.xml │ │ │ ├── vrs_config_283.xml │ │ │ ├── vrs_config_284.xml │ │ │ ├── vrs_config_285.xml │ │ │ ├── vrs_config_286.xml │ │ │ ├── vrs_config_287.xml │ │ │ ├── vrs_config_288.xml │ │ │ ├── vrs_config_289.xml │ │ │ ├── vrs_config_29.xml │ │ │ ├── vrs_config_290.xml │ │ │ ├── vrs_config_291.xml │ │ │ ├── vrs_config_292.xml │ │ │ ├── vrs_config_293.xml │ │ │ ├── vrs_config_294.xml │ │ │ ├── vrs_config_295.xml │ │ │ ├── vrs_config_296.xml │ │ │ ├── vrs_config_297.xml │ │ │ ├── vrs_config_298.xml │ │ │ ├── vrs_config_299.xml │ │ │ ├── vrs_config_3.xml │ │ │ ├── vrs_config_30.xml │ │ │ ├── vrs_config_300.xml │ │ │ ├── vrs_config_301.xml │ │ │ ├── vrs_config_302.xml │ │ │ ├── vrs_config_303.xml │ │ │ ├── vrs_config_304.xml │ │ │ ├── vrs_config_305.xml │ │ │ ├── vrs_config_306.xml │ │ │ ├── vrs_config_307.xml │ │ │ ├── vrs_config_308.xml │ │ │ ├── vrs_config_309.xml │ │ │ ├── vrs_config_31.xml │ │ │ ├── vrs_config_310.xml │ │ │ ├── vrs_config_311.xml │ │ │ ├── vrs_config_312.xml │ │ │ ├── vrs_config_313.xml │ │ │ ├── vrs_config_314.xml │ │ │ ├── vrs_config_315.xml │ │ │ ├── vrs_config_316.xml │ │ │ ├── vrs_config_317.xml │ │ │ ├── vrs_config_318.xml │ │ │ ├── vrs_config_319.xml │ │ │ ├── vrs_config_32.xml │ │ │ ├── vrs_config_320.xml │ │ │ ├── vrs_config_321.xml │ │ │ ├── vrs_config_322.xml │ │ │ ├── vrs_config_323.xml │ │ │ ├── vrs_config_324.xml │ │ │ ├── vrs_config_325.xml │ │ │ ├── vrs_config_326.xml │ │ │ ├── vrs_config_327.xml │ │ │ ├── vrs_config_328.xml │ │ │ ├── vrs_config_329.xml │ │ │ ├── vrs_config_33.xml │ │ │ ├── vrs_config_330.xml │ │ │ ├── vrs_config_331.xml │ │ │ ├── vrs_config_332.xml │ │ │ ├── vrs_config_333.xml │ │ │ ├── vrs_config_334.xml │ │ │ ├── vrs_config_335.xml │ │ │ ├── vrs_config_336.xml │ │ │ ├── vrs_config_337.xml │ │ │ ├── vrs_config_338.xml │ │ │ ├── vrs_config_339.xml │ │ │ ├── vrs_config_34.xml │ │ │ ├── vrs_config_340.xml │ │ │ ├── vrs_config_341.xml │ │ │ ├── vrs_config_342.xml │ │ │ ├── vrs_config_343.xml │ │ │ ├── vrs_config_344.xml │ │ │ ├── vrs_config_345.xml │ │ │ ├── vrs_config_346.xml │ │ │ ├── vrs_config_347.xml │ │ │ ├── vrs_config_348.xml │ │ │ ├── vrs_config_349.xml │ │ │ ├── vrs_config_35.xml │ │ │ ├── vrs_config_350.xml │ │ │ ├── vrs_config_351.xml │ │ │ ├── vrs_config_352.xml │ │ │ ├── vrs_config_353.xml │ │ │ ├── vrs_config_354.xml │ │ │ ├── vrs_config_36.xml │ │ │ ├── vrs_config_37.xml │ │ │ ├── vrs_config_38.xml │ │ │ ├── vrs_config_39.xml │ │ │ ├── vrs_config_4.xml │ │ │ ├── vrs_config_40.xml │ │ │ ├── vrs_config_41.xml │ │ │ ├── vrs_config_42.xml │ │ │ ├── vrs_config_43.xml │ │ │ ├── vrs_config_44.xml │ │ │ ├── vrs_config_45.xml │ │ │ ├── vrs_config_46.xml │ │ │ ├── vrs_config_47.xml │ │ │ ├── vrs_config_48.xml │ │ │ ├── vrs_config_49.xml │ │ │ ├── vrs_config_5.xml │ │ │ ├── vrs_config_50.xml │ │ │ ├── vrs_config_51.xml │ │ │ ├── vrs_config_52.xml │ │ │ ├── vrs_config_53.xml │ │ │ ├── vrs_config_54.xml │ │ │ ├── vrs_config_55.xml │ │ │ ├── vrs_config_56.xml │ │ │ ├── vrs_config_57.xml │ │ │ ├── vrs_config_58.xml │ │ │ ├── vrs_config_59.xml │ │ │ ├── vrs_config_6.xml │ │ │ ├── vrs_config_60.xml │ │ │ ├── vrs_config_61.xml │ │ │ ├── vrs_config_62.xml │ │ │ ├── vrs_config_63.xml │ │ │ ├── vrs_config_64.xml │ │ │ ├── vrs_config_65.xml │ │ │ ├── vrs_config_66.xml │ │ │ ├── vrs_config_67.xml │ │ │ ├── vrs_config_68.xml │ │ │ ├── vrs_config_69.xml │ │ │ ├── vrs_config_7.xml │ │ │ ├── vrs_config_70.xml │ │ │ ├── vrs_config_71.xml │ │ │ ├── vrs_config_72.xml │ │ │ ├── vrs_config_73.xml │ │ │ ├── vrs_config_74.xml │ │ │ ├── vrs_config_75.xml │ │ │ ├── vrs_config_76.xml │ │ │ ├── vrs_config_77.xml │ │ │ ├── vrs_config_78.xml │ │ │ ├── vrs_config_79.xml │ │ │ ├── vrs_config_8.xml │ │ │ ├── vrs_config_80.xml │ │ │ ├── vrs_config_81.xml │ │ │ ├── vrs_config_82.xml │ │ │ ├── vrs_config_83.xml │ │ │ ├── vrs_config_84.xml │ │ │ ├── vrs_config_85.xml │ │ │ ├── vrs_config_86.xml │ │ │ ├── vrs_config_87.xml │ │ │ ├── vrs_config_88.xml │ │ │ ├── vrs_config_89.xml │ │ │ ├── vrs_config_9.xml │ │ │ ├── vrs_config_90.xml │ │ │ ├── vrs_config_91.xml │ │ │ ├── vrs_config_92.xml │ │ │ ├── vrs_config_93.xml │ │ │ ├── vrs_config_94.xml │ │ │ ├── vrs_config_95.xml │ │ │ ├── vrs_config_96.xml │ │ │ ├── vrs_config_97.xml │ │ │ ├── vrs_config_98.xml │ │ │ └── vrs_config_99.xml │ │ ├── impl_1 │ │ │ ├── .Vivado_Implementation.queue.rst │ │ │ ├── .init_design.begin.rst │ │ │ ├── .init_design.end.rst │ │ │ ├── .opt_design.begin.rst │ │ │ ├── .opt_design.end.rst │ │ │ ├── .place_design.begin.rst │ │ │ ├── .place_design.end.rst │ │ │ ├── .route_design.begin.rst │ │ │ ├── .route_design.end.rst │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── .write_bitstream.begin.rst │ │ │ ├── .write_bitstream.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── init_design.pb │ │ │ ├── opt_design.pb │ │ │ ├── place_design.pb │ │ │ ├── project.wdf │ │ │ ├── route_design.pb │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.sh │ │ │ ├── top.bit │ │ │ ├── top.hwdef │ │ │ ├── top.sysdef │ │ │ ├── top.tcl │ │ │ ├── top.vdi │ │ │ ├── top_bus_skew_routed.pb │ │ │ ├── top_bus_skew_routed.rpt │ │ │ ├── top_bus_skew_routed.rpx │ │ │ ├── top_clock_utilization_routed.rpt │ │ │ ├── top_control_sets_placed.rpt │ │ │ ├── top_drc_opted.pb │ │ │ ├── top_drc_opted.rpt │ │ │ ├── top_drc_opted.rpx │ │ │ ├── top_drc_routed.pb │ │ │ ├── top_drc_routed.rpt │ │ │ ├── top_drc_routed.rpx │ │ │ ├── top_io_placed.rpt │ │ │ ├── top_methodology_drc_routed.pb │ │ │ ├── top_methodology_drc_routed.rpt │ │ │ ├── top_methodology_drc_routed.rpx │ │ │ ├── top_opt.dcp │ │ │ ├── top_placed.dcp │ │ │ ├── top_power_routed.rpt │ │ │ ├── top_power_routed.rpx │ │ │ ├── top_power_summary_routed.pb │ │ │ ├── top_route_status.pb │ │ │ ├── top_route_status.rpt │ │ │ ├── top_routed.dcp │ │ │ ├── top_timing_summary_routed.pb │ │ │ ├── top_timing_summary_routed.rpt │ │ │ ├── top_timing_summary_routed.rpx │ │ │ ├── top_utilization_placed.pb │ │ │ ├── top_utilization_placed.rpt │ │ │ ├── usage_statistics_webtalk.html │ │ │ ├── usage_statistics_webtalk.xml │ │ │ ├── vivado.jou │ │ │ ├── vivado.pb │ │ │ └── write_bitstream.pb │ │ └── synth_1 │ │ │ ├── .Vivado_Synthesis.queue.rst │ │ │ ├── .Xil │ │ │ └── top_propImpl.xdc │ │ │ ├── .vivado.begin.rst │ │ │ ├── .vivado.end.rst │ │ │ ├── ISEWrap.js │ │ │ ├── ISEWrap.sh │ │ │ ├── __synthesis_is_complete__ │ │ │ ├── dont_touch.xdc │ │ │ ├── gen_run.xml │ │ │ ├── htr.txt │ │ │ ├── rundef.js │ │ │ ├── runme.bat │ │ │ ├── runme.sh │ │ │ ├── top.dcp │ │ │ ├── top.tcl │ │ │ ├── top.vds │ │ │ ├── top_utilization_synth.pb │ │ │ ├── top_utilization_synth.rpt │ │ │ ├── vivado.jou │ │ │ └── vivado.pb │ ├── PCore_FPGA.srcs │ │ ├── constrs_1 │ │ │ └── imports │ │ │ │ └── tcl │ │ │ │ ├── 1-clock.xdc │ │ │ │ ├── 2-pins.xdc │ │ │ │ ├── 3-bitstream.xdc │ │ │ │ └── const.ucf │ │ ├── sources_1 │ │ │ ├── bd │ │ │ │ └── nexys_shell │ │ │ │ │ ├── hdl │ │ │ │ │ └── nexys_shell_wrapper.v │ │ │ │ │ ├── hw_handoff │ │ │ │ │ ├── nexys_shell.hwh │ │ │ │ │ └── nexys_shell_bd.tcl │ │ │ │ │ ├── ip │ │ │ │ │ ├── nexys_shell_axi_bram_ctrl_0_0 │ │ │ │ │ │ └── nexys_shell_axi_bram_ctrl_0_0.xci │ │ │ │ │ ├── nexys_shell_blk_mem_gen_0_0 │ │ │ │ │ │ └── nexys_shell_blk_mem_gen_0_0.xci │ │ │ │ │ ├── nexys_shell_mig_7series_0_0 │ │ │ │ │ │ ├── board.prj │ │ │ │ │ │ ├── mig_a.prj │ │ │ │ │ │ └── nexys_shell_mig_7series_0_0.xci │ │ │ │ │ ├── nexys_shell_mig_7series_0_0_1 │ │ │ │ │ │ ├── board.prj │ │ │ │ │ │ ├── mig_a.prj │ │ │ │ │ │ ├── mig_b.prj │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0.veo │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0.xci │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0.xml │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0 │ │ │ │ │ │ │ ├── datasheet.txt │ │ │ │ │ │ │ ├── docs │ │ │ │ │ │ │ │ └── phy_only_support_readme.txt │ │ │ │ │ │ │ ├── example_design │ │ │ │ │ │ │ │ ├── par │ │ │ │ │ │ │ │ │ ├── compatible_ucf │ │ │ │ │ │ │ │ │ │ └── xc7a50tcsg324_pkg.xdc │ │ │ │ │ │ │ │ │ ├── example_top.xdc │ │ │ │ │ │ │ │ │ └── readme.txt │ │ │ │ │ │ │ │ └── rtl │ │ │ │ │ │ │ │ │ ├── example_top.v │ │ │ │ │ │ │ │ │ └── traffic_gen │ │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi4_tg.v │ │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi4_wrapper.v │ │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_cmd_prbs_gen_axi.v │ │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_data_gen_chk.v │ │ │ │ │ │ │ │ │ └── mig_7series_v4_2_tg.v │ │ │ │ │ │ │ ├── mig.prj │ │ │ │ │ │ │ └── user_design │ │ │ │ │ │ │ │ ├── constraints │ │ │ │ │ │ │ │ ├── compatible_ucf │ │ │ │ │ │ │ │ │ └── xc7a50tcsg324_pkg.xdc │ │ │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0.xdc │ │ │ │ │ │ │ │ └── nexys_shell_mig_7series_0_0_ooc.xdc │ │ │ │ │ │ │ │ └── rtl │ │ │ │ │ │ │ │ ├── axi │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_addr_decode.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_read.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_reg.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_reg_bank.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_top.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_ctrl_write.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_ar_channel.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_aw_channel.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_b_channel.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_cmd_arbiter.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_cmd_fsm.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_cmd_translator.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_fifo.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_incr_cmd.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_r_channel.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_simple_fifo.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_w_channel.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_wr_cmd_fsm.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_axi_mc_wrap_cmd.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_a_upsizer.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_axi_register_slice.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_axi_upsizer.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_axic_register_slice.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_and.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_latch_and.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_latch_or.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_carry_or.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_command_fifo.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_comparator.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_comparator_sel.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_comparator_sel_static.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_r_upsizer.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_ddr_w_upsizer.v │ │ │ │ │ │ │ │ ├── clocking │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_clk_ibuf.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_infrastructure.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_iodelay_ctrl.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_tempmon.v │ │ │ │ │ │ │ │ ├── controller │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_arb_mux.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_arb_row_col.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_arb_select.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_bank_cntrl.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_bank_common.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_bank_compare.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_bank_mach.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_bank_queue.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_bank_state.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_col_mach.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_mc.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_rank_cntrl.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_rank_common.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_rank_mach.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_round_robin_arb.v │ │ │ │ │ │ │ │ ├── ecc │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ecc_buf.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ecc_dec_fix.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ecc_gen.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ecc_merge_enc.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_fi_xor.v │ │ │ │ │ │ │ │ ├── ip_top │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_mem_intfc.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_memc_ui_top_axi.v │ │ │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0.v │ │ │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0_mig.v │ │ │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0_mig_sim.v │ │ │ │ │ │ │ │ ├── phy │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_byte_group_io.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_byte_lane.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_calib_top.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_if_post_fifo.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_mc_phy.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_mc_phy_wrapper.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_of_pre_fifo.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_4lanes.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_dqs_found_cal.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_dqs_found_cal_hr.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_init.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_cntlr.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_data.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_edge.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_lim.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_mux.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_ocd_samp.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_oclkdelay_cal.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_prbs_rdlvl.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_rdlvl.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_tempmon.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_top.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_wrcal.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_wrlvl.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_phy_wrlvl_off_delay.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ddr_prbs_gen.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_poc_cc.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_poc_edge_store.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_poc_meta.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_poc_pd.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_poc_tap_base.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_poc_top.v │ │ │ │ │ │ │ │ └── ui │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ui_cmd.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ui_rd_data.v │ │ │ │ │ │ │ │ ├── mig_7series_v4_2_ui_top.v │ │ │ │ │ │ │ │ └── mig_7series_v4_2_ui_wr_data.v │ │ │ │ │ │ ├── nexys_shell_mig_7series_0_0_xmdf.tcl │ │ │ │ │ │ ├── xil_txt.in │ │ │ │ │ │ └── xil_txt.out │ │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0 │ │ │ │ │ │ └── nexys_shell_proc_sys_reset_0_0.xci │ │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_1 │ │ │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0.xci │ │ │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0.xdc │ │ │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0.xml │ │ │ │ │ │ ├── nexys_shell_proc_sys_reset_0_0_board.xdc │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ └── nexys_shell_proc_sys_reset_0_0.vhd │ │ │ │ │ ├── nexys_shell_smartconnect_0_0 │ │ │ │ │ │ └── nexys_shell_smartconnect_0_0.xci │ │ │ │ │ └── nexys_shell_smartconnect_0_0_1 │ │ │ │ │ │ ├── bd_0 │ │ │ │ │ │ ├── bd_4cab.bd │ │ │ │ │ │ ├── bd_4cab.bxml │ │ │ │ │ │ ├── hdl │ │ │ │ │ │ │ └── bd_4cab_wrapper.v │ │ │ │ │ │ ├── hw_handoff │ │ │ │ │ │ │ ├── nexys_shell_smartconnect_0_0.hwh │ │ │ │ │ │ │ └── nexys_shell_smartconnect_0_0_bd.tcl │ │ │ │ │ │ ├── ip │ │ │ │ │ │ │ ├── ip_0 │ │ │ │ │ │ │ │ ├── bd_4cab_one_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_one_0.xml │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_one_0.v │ │ │ │ │ │ │ ├── ip_1 │ │ │ │ │ │ │ │ ├── bd_4cab_psr0_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_psr0_0.xdc │ │ │ │ │ │ │ │ ├── bd_4cab_psr0_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_psr0_0_board.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_psr0_0.vhd │ │ │ │ │ │ │ ├── ip_10 │ │ │ │ │ │ │ │ ├── bd_4cab_sawn_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_sawn_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_sawn_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_sawn_0.sv │ │ │ │ │ │ │ ├── ip_11 │ │ │ │ │ │ │ │ ├── bd_4cab_swn_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_swn_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_swn_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_swn_0.sv │ │ │ │ │ │ │ ├── ip_12 │ │ │ │ │ │ │ │ ├── bd_4cab_sbn_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_sbn_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_sbn_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_sbn_0.sv │ │ │ │ │ │ │ ├── ip_13 │ │ │ │ │ │ │ │ ├── bd_4cab_m00s2a_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_m00s2a_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_m00s2a_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_m00s2a_0.sv │ │ │ │ │ │ │ ├── ip_14 │ │ │ │ │ │ │ │ ├── bd_4cab_m00e_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_m00e_0.xml │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_m00e_0.sv │ │ │ │ │ │ │ ├── ip_2 │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk_0.xdc │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk_0_board.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_psr_aclk_0.vhd │ │ │ │ │ │ │ ├── ip_3 │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk1_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk1_0.xdc │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk1_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_psr_aclk1_0_board.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_psr_aclk1_0.vhd │ │ │ │ │ │ │ ├── ip_4 │ │ │ │ │ │ │ │ ├── bd_4cab_s00mmu_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_s00mmu_0.xml │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_s00mmu_0.sv │ │ │ │ │ │ │ ├── ip_5 │ │ │ │ │ │ │ │ ├── bd_4cab_s00tr_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_s00tr_0.xml │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_s00tr_0.sv │ │ │ │ │ │ │ ├── ip_6 │ │ │ │ │ │ │ │ ├── bd_4cab_s00sic_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_s00sic_0.xml │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_s00sic_0.sv │ │ │ │ │ │ │ ├── ip_7 │ │ │ │ │ │ │ │ ├── bd_4cab_s00a2s_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_s00a2s_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_s00a2s_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_s00a2s_0.sv │ │ │ │ │ │ │ ├── ip_8 │ │ │ │ │ │ │ │ ├── bd_4cab_sarn_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_sarn_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_sarn_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ │ └── bd_4cab_sarn_0.sv │ │ │ │ │ │ │ └── ip_9 │ │ │ │ │ │ │ │ ├── bd_4cab_srn_0.xci │ │ │ │ │ │ │ │ ├── bd_4cab_srn_0.xml │ │ │ │ │ │ │ │ ├── bd_4cab_srn_0_ooc.xdc │ │ │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ │ └── bd_4cab_srn_0.sv │ │ │ │ │ │ └── synth │ │ │ │ │ │ │ ├── bd_4cab.v │ │ │ │ │ │ │ └── nexys_shell_smartconnect_0_0.hwdef │ │ │ │ │ │ ├── nexys_shell_smartconnect_0_0.xci │ │ │ │ │ │ ├── nexys_shell_smartconnect_0_0.xml │ │ │ │ │ │ ├── ooc.xdc │ │ │ │ │ │ └── synth │ │ │ │ │ │ └── nexys_shell_smartconnect_0_0.v │ │ │ │ │ ├── ipshared │ │ │ │ │ ├── 7005 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── sc_sc2axi_v1_0_vl_rfs.sv │ │ │ │ │ ├── 8842 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── proc_sys_reset_v5_0_vh_rfs.vhd │ │ │ │ │ ├── 1ddd │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ ├── sc_util_v1_0_vl_rfs.sv │ │ │ │ │ │ │ └── verilog │ │ │ │ │ │ │ ├── sc_util_v1_0_4_constants.vh │ │ │ │ │ │ │ └── sc_util_v1_0_4_structs.svh │ │ │ │ │ ├── 66e7 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── xlconstant_v1_1_vl_rfs.v │ │ │ │ │ ├── 7de4 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── sc_si_converter_v1_0_vl_rfs.sv │ │ │ │ │ ├── b2d0 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ ├── sc_node_v1_0_vl_rfs.sv │ │ │ │ │ │ │ └── verilog │ │ │ │ │ │ │ └── sc_node_v1_0_10_t_reqsend.svh │ │ │ │ │ ├── b387 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── sc_exit_v1_0_vl_rfs.sv │ │ │ │ │ ├── b89e │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── sc_axi2sc_v1_0_vl_rfs.sv │ │ │ │ │ ├── ca72 │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── sc_transaction_regulator_v1_0_vl_rfs.sv │ │ │ │ │ ├── ef1e │ │ │ │ │ │ └── hdl │ │ │ │ │ │ │ └── lib_cdc_v1_0_rfs.vhd │ │ │ │ │ └── f85e │ │ │ │ │ │ └── hdl │ │ │ │ │ │ └── sc_mmu_v1_0_vl_rfs.sv │ │ │ │ │ ├── nexys_shell.bd │ │ │ │ │ ├── nexys_shell.bda │ │ │ │ │ ├── nexys_shell.bxml │ │ │ │ │ ├── nexys_shell_ooc.xdc │ │ │ │ │ ├── synth │ │ │ │ │ ├── nexys_shell.hwdef │ │ │ │ │ └── nexys_shell.v │ │ │ │ │ └── ui │ │ │ │ │ └── bd_29f0980c.ui │ │ │ └── imports │ │ │ │ ├── UETRV-PCore │ │ │ │ ├── top.v │ │ │ │ └── wb2axi.sv │ │ │ │ └── rtl │ │ │ │ ├── core │ │ │ │ ├── core_top.sv │ │ │ │ ├── mmu │ │ │ │ │ ├── dtlb.sv │ │ │ │ │ ├── itlb.sv │ │ │ │ │ ├── mmu.sv │ │ │ │ │ └── ptw.sv │ │ │ │ └── pipeline │ │ │ │ │ ├── amo.sv │ │ │ │ │ ├── csr.sv │ │ │ │ │ ├── decode.sv │ │ │ │ │ ├── divider.sv │ │ │ │ │ ├── execute.sv │ │ │ │ │ ├── fetch.sv │ │ │ │ │ ├── forward_stall.sv │ │ │ │ │ ├── lsu.sv │ │ │ │ │ ├── muldiv.sv │ │ │ │ │ ├── pipeline_top.sv │ │ │ │ │ ├── reg_file.sv │ │ │ │ │ └── writeback.sv │ │ │ │ ├── defines │ │ │ │ ├── a_ext_defs.svh │ │ │ │ ├── cache_defs.svh │ │ │ │ ├── ddr_defs.svh │ │ │ │ ├── m_ext_defs.svh │ │ │ │ ├── mmu_defs.svh │ │ │ │ ├── pcore_config_defs.svh │ │ │ │ ├── pcore_csr_defs.svh │ │ │ │ ├── pcore_interface_defs.svh │ │ │ │ ├── plic_defs.svh │ │ │ │ ├── spi_defs.svh │ │ │ │ └── uart_defs.svh │ │ │ │ ├── interconnect │ │ │ │ └── dbus_interconnect.sv │ │ │ │ ├── memory │ │ │ │ ├── bmem.sv │ │ │ │ ├── bmem_interface.sv │ │ │ │ ├── icache │ │ │ │ │ ├── icache_data_ram.sv │ │ │ │ │ ├── icache_tag_ram.sv │ │ │ │ │ └── icache_top.sv │ │ │ │ ├── main_mem.sv │ │ │ │ ├── mem_top.sv │ │ │ │ └── wb_dcache │ │ │ │ │ ├── dcache_data_ram.sv │ │ │ │ │ ├── dcache_tag_ram.sv │ │ │ │ │ ├── wb_dcache_controller.sv │ │ │ │ │ ├── wb_dcache_datapath.sv │ │ │ │ │ └── wb_dcache_top.sv │ │ │ │ ├── peripherals │ │ │ │ ├── clint │ │ │ │ │ └── clint.sv │ │ │ │ ├── plic │ │ │ │ │ ├── plic_gateway.sv │ │ │ │ │ ├── plic_regs.sv │ │ │ │ │ ├── plic_target.sv │ │ │ │ │ └── plic_top.sv │ │ │ │ ├── spi │ │ │ │ │ ├── spi_controller.sv │ │ │ │ │ ├── spi_datapath.sv │ │ │ │ │ ├── spi_fifo.sv │ │ │ │ │ ├── spi_regs.sv │ │ │ │ │ └── spi_top.sv │ │ │ │ └── uart │ │ │ │ │ ├── uart.sv │ │ │ │ │ ├── uart_rx.sv │ │ │ │ │ └── uart_tx.sv │ │ │ │ └── soc_top.sv │ │ └── utils_1 │ │ │ └── imports │ │ │ └── synth_1 │ │ │ └── top.dcp │ └── PCore_FPGA.xpr └── top.bit ├── LICENSE ├── Makefile ├── README.md ├── bench ├── pcore_tb.cpp └── pcore_tb.sv ├── docs └── images │ ├── linux_boot_log.png │ ├── pipeline.png │ └── soc.png ├── rtl ├── core │ ├── core_top.sv │ ├── mmu │ │ ├── dtlb.sv │ │ ├── itlb.sv │ │ ├── mmu.sv │ │ └── ptw.sv │ └── pipeline │ │ ├── amo.sv │ │ ├── csr.sv │ │ ├── decode.sv │ │ ├── divide.sv │ │ ├── divider.sv │ │ ├── execute.sv │ │ ├── fetch.sv │ │ ├── forward_stall.sv │ │ ├── lsu.sv │ │ ├── pipeline_top.sv │ │ ├── reg_file.sv │ │ └── writeback.sv ├── defines │ ├── a_ext_defs.svh │ ├── cache_defs.svh │ ├── ddr_defs.svh │ ├── m_ext_defs.svh │ ├── mmu_defs.svh │ ├── pcore_config_defs.svh │ ├── pcore_csr_defs.svh │ ├── pcore_interface_defs.svh │ ├── plic_defs.svh │ ├── spi_defs.svh │ └── uart_defs.svh ├── interconnect │ └── dbus_interconnect.sv ├── memory │ ├── Error_Documentation │ │ ├── Dcache ERROR DOCUMENTATION.docx │ │ └── icache error documentation.docx │ ├── Testbenches │ │ ├── dcache_tb.sv │ │ └── icache_top_tb.sv │ ├── Testplan │ │ ├── Dcache_testplan.xlsx │ │ └── Icache_testplan.xlsx │ ├── bmem.sv │ ├── bmem_interface.sv │ ├── icache │ │ ├── icache_data_ram.sv │ │ ├── icache_tag_ram.sv │ │ └── icache_top.sv │ ├── main_mem.sv │ ├── mem_top.sv │ └── wb_dcache │ │ ├── dcache_data_ram.sv │ │ ├── dcache_tag_ram.sv │ │ ├── wb_dcache_controller.sv │ │ ├── wb_dcache_datapath.sv │ │ └── wb_dcache_top.sv ├── peripherals │ ├── clint │ │ └── clint.sv │ ├── plic │ │ ├── plic_gateway.sv │ │ ├── plic_regs.sv │ │ ├── plic_target.sv │ │ └── plic_top.sv │ ├── spi │ │ ├── spi_controller.sv │ │ ├── spi_datapath.sv │ │ ├── spi_fifo.sv │ │ ├── spi_regs.sv │ │ └── spi_top.sv │ └── uart │ │ ├── uart.sv │ │ ├── uart_rx.sv │ │ └── uart_tx.sv └── soc_top.sv ├── sdk ├── boot_mem_fpga │ ├── Interfaces │ │ ├── uart.c │ │ └── uart.h │ ├── Makefile │ ├── bmem.S │ ├── bmem.elf │ ├── bmem.txt │ ├── build │ │ └── bmem.sv │ ├── dtpcore.dtb │ ├── dtpcore.dts │ ├── linker.ld │ ├── main.c │ ├── make_bin.py │ ├── make_sv.py │ └── make_txt.py ├── boot_mem_simulation │ ├── Makefile │ ├── bmem.S │ ├── bmem.sv │ ├── bmem.txt │ ├── dtpcore.dtb │ ├── dtpcore.dts │ ├── linker.ld │ ├── make_sv.py │ └── make_txt.py ├── example-linux │ └── imem.zip ├── example-uart │ ├── Interfaces │ │ ├── plic.c │ │ ├── plic.h │ │ ├── spi.c │ │ ├── spi.h │ │ ├── uart.c │ │ └── uart.h │ ├── Makefile │ ├── README.md │ ├── build.sh │ ├── build │ │ └── hello.hex │ ├── linker.ld │ ├── make.bat │ ├── maketxt.py │ ├── src │ │ ├── isr.s │ │ ├── main.c │ │ └── startup.s │ └── txt2hex.py ├── load_image_uart │ ├── cmd.txt │ ├── imem.bin │ └── serial_sendfile.py ├── microbenchmarks │ ├── Interfaces │ │ ├── plic.c │ │ ├── plic.h │ │ ├── spi.c │ │ ├── spi.h │ │ ├── uart.c │ │ └── uart.h │ ├── Makefile │ ├── README.md │ ├── build.sh │ ├── build │ │ ├── hello.hex │ │ ├── isr.o │ │ ├── main.bin │ │ ├── main.dump │ │ ├── main.elf │ │ ├── main.o │ │ ├── main.txt │ │ ├── plic.o │ │ ├── startup.o │ │ └── uart.o │ ├── linker.ld │ ├── make.bat │ ├── maketxt.py │ ├── src │ │ ├── isr.s │ │ ├── main.c │ │ └── startup.s │ └── txt2hex.py └── uart_logdata.txt └── verif ├── Readme.md ├── bin ├── Readme.md ├── riscv-isac │ ├── CHANGELOG.md │ ├── CONTRIBUTING.rst │ ├── LICENSE.incore │ ├── MANIFEST.in │ ├── README.rst │ ├── interface.py │ ├── riscv_isac │ │ ├── InstructionObject.py │ │ ├── __init__.py │ │ ├── cgf_normalize.py │ │ ├── constants.py │ │ ├── coverage.py │ │ ├── data │ │ │ ├── __init__.py │ │ │ ├── constants.py │ │ │ ├── instr_alias.yaml │ │ │ └── rvopcodesdecoder.py │ │ ├── fp_dataset.py │ │ ├── isac.py │ │ ├── log.py │ │ ├── main.py │ │ ├── plugins │ │ │ ├── __init__.py │ │ │ ├── c_sail.py │ │ │ ├── internaldecoder.py │ │ │ ├── specification.py │ │ │ ├── spike.py │ │ │ └── translator_cgf.py │ │ ├── requirements.txt │ │ ├── test_requirements.txt │ │ └── utils.py │ ├── setup.cfg │ ├── setup.py │ └── tests │ │ ├── __init__.py │ │ └── test_riscv_isac.py └── sail-riscv.tar.gz ├── config.ini ├── makehex.py ├── pcore-plugin ├── env │ ├── link.ld │ └── model_test.h ├── pcore_isa.yaml ├── pcore_platform.yaml └── riscof_pcore.py ├── run-tests.sh └── sail_cSim-plugin ├── __init__.py ├── env ├── link.ld └── model_test.h └── riscof_sail_cSim.py /.github/workflows/main.yml: -------------------------------------------------------------------------------- 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