├── README.md ├── ip ├── definition │ ├── AHB2APB.json │ ├── AHB2GPIO.json │ ├── AHB2SPI.json │ ├── AHBQSPIFI.json │ ├── APB2ADC.json │ ├── APB2BG.json │ ├── APB2CMP.json │ ├── APB2DAC.json │ ├── APB2I2C.json │ ├── APB2PWM.json │ ├── APB2SPI.json │ ├── APB2TMR.json │ ├── APBGPIO.json │ ├── APBUART.json │ ├── CORTEXM0_EF01.json │ ├── XSPRAMBLP_4096X32_M16P.json │ ├── category.json │ ├── category_schema.jsonc │ └── ip_schema.jsonc └── design_files │ └── source │ ├── AHB2GPIO.v │ ├── AHBQSPIFI.v │ ├── APB2I2C.v │ ├── APB2SPI.v │ ├── APBGPIO.v │ └── QSPIFI.v ├── soc ├── definition │ ├── bus.json │ ├── bus_schema.jsonc │ ├── soc_template.json │ └── soc_template_schema.jsonc └── design_files │ ├── soc_top_level.v │ ├── source │ ├── AHB2TWROM.v │ ├── AHBSRAM.v │ ├── CLKCTRL.v │ ├── DIGITALCORE.v │ ├── QSIXIP2w.v │ └── tap.v │ ├── sw │ ├── 23lc512_drv.c │ ├── 23lc512_drv.h │ ├── adc_drv.c │ ├── adc_drv.h │ ├── adc_regs.h │ ├── base_addr.h │ ├── bg_drv.c │ ├── bg_drv.h │ ├── clkctrl_regs.h │ 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