├── .gitignore ├── README.md ├── c1-dead-lock-sdspi ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bench │ └── cpp │ │ ├── .gitignore │ │ ├── .gtkwaverc │ │ ├── autotest_tb.cpp │ │ ├── sdspisim.cpp │ │ ├── sdspisim.h │ │ ├── testb.h │ │ └── wb_tb.h ├── bug9.instrument.cfg ├── rtl │ ├── llsdspi.v │ └── sdspi.v ├── sources.txt └── vivado_synth │ └── sdspi_wrapper.v ├── c2-producer-consumer-mismatch-optimus ├── .gitignore ├── .gtkwaverc ├── Makefile ├── Makefile.lc ├── README.md ├── bug5.instrument.cfg ├── ccip │ ├── device_if │ │ ├── avalon_mem_if.vh │ │ ├── avalon_mem_if_dbg.vh │ │ ├── ccip_if_clock.sv │ │ ├── ccip_if_pkg.sv │ │ └── device_if.vh │ ├── platform_afu_top_config.vh │ ├── platform_if.vh │ └── platform_shims │ │ ├── README.md │ │ ├── platform_shim_avalon_mem_if.sv │ │ ├── platform_shim_ccip.sv │ │ ├── platform_shim_ccip_std_afu.sv │ │ └── utils │ │ ├── avalon_mem_if_async_shim.sv │ │ ├── avalon_mem_if_connect.sv │ │ ├── avalon_mem_if_reg.sv │ │ ├── platform_utils_ccip_activity_cnt.sv │ │ ├── platform_utils_ccip_async_shim.sv │ │ ├── platform_utils_ccip_reg.sv │ │ └── quartus_ip │ │ ├── README │ │ ├── gen_platform_ip.sh │ │ ├── platform_utils_avalon_dc_fifo.sdc │ │ ├── platform_utils_avalon_dc_fifo.v │ │ ├── platform_utils_avalon_mm_bridge.v │ │ ├── platform_utils_avalon_mm_clock_crossing_bridge.v │ │ ├── platform_utils_dc_fifo.sdc │ │ ├── platform_utils_dc_fifo.sv │ │ ├── platform_utils_dcfifo_synchronizer_bundle.v │ │ └── platform_utils_std_synchronizer_nocut.v ├── lib │ ├── BBB_cci_mpf │ │ ├── README │ │ ├── hw │ │ │ ├── README │ │ │ ├── par │ │ │ │ ├── README │ │ │ │ ├── qsf_cci_mpf_PAR_files.qsf │ │ │ │ └── sdc_cci_mpf.sdc │ │ │ ├── rtl │ │ │ │ ├── cci-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_csr_if.vh │ │ │ │ │ ├── cci_csr_if_pkg.sv │ │ │ │ │ ├── ccip_feature_list.h │ │ │ │ │ ├── ccip_feature_list_pkg.sv │ │ │ │ │ ├── ccip_if_funcs_pkg.sv │ │ │ │ │ ├── ccip_if_pkg.sv │ │ │ │ │ ├── ccis_if_funcs_pkg.sv │ │ │ │ │ └── ccis_if_pkg.sv │ │ │ │ ├── cci-mpf-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_if.vh │ │ │ │ │ ├── cci_mpf_if_dbg.vh │ │ │ │ │ ├── cci_mpf_if_pkg.sv │ │ │ │ │ ├── cci_mpf_platform.vh │ │ │ │ │ ├── ccip_wires_to_mpf.sv │ │ │ │ │ └── ccis_wires_to_mpf.sv │ │ │ │ ├── cci-mpf-prims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_prim_arb_rr.sv │ │ │ │ │ ├── cci_mpf_prim_fifo1.sv │ │ │ │ │ ├── cci_mpf_prim_fifo2.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_bram.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_filter_cam.sv │ │ │ │ │ ├── cci_mpf_prim_filter_counting.sv │ │ │ │ │ ├── cci_mpf_prim_filter_decode.sv │ │ │ │ │ ├── cci_mpf_prim_hash.vh │ │ │ │ │ ├── cci_mpf_prim_heap.sv │ │ │ │ │ ├── cci_mpf_prim_lfsr.sv │ │ │ │ │ ├── cci_mpf_prim_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_onehot_to_bin.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport_byteena.sv │ │ │ │ │ ├── cci_mpf_prim_ram_simple.sv │ │ │ │ │ ├── cci_mpf_prim_repl_lru_pseudo.sv │ │ │ │ │ ├── cci_mpf_prim_repl_random.sv │ │ │ │ │ ├── cci_mpf_prim_rob.sv │ │ │ │ │ ├── cci_mpf_prim_semaphore_cam.sv │ │ │ │ │ ├── cci_mpf_prim_track_active_reqs.sv │ │ │ │ │ └── cci_mpf_prim_track_multi_write.sv │ │ │ │ ├── cci-mpf-shims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_shim.vh │ │ │ │ │ ├── cci_mpf_shim_buffer_afu.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_epoch.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_lockstep.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_csr.sv │ │ │ │ │ ├── cci_mpf_shim_dbg_history.sv │ │ │ │ │ ├── cci_mpf_shim_dedup_reads.sv │ │ │ │ │ ├── cci_mpf_shim_detect_eop.sv │ │ │ │ │ ├── cci_mpf_shim_edge │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_edge.vh │ │ │ │ │ │ ├── cci_mpf_shim_edge_afu.sv │ │ │ │ │ │ └── cci_mpf_shim_edge_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_latency_qos.sv │ │ │ │ │ ├── cci_mpf_shim_mux.sv │ │ │ │ │ ├── cci_mpf_shim_null.sv │ │ │ │ │ ├── cci_mpf_shim_pkg.sv │ │ │ │ │ ├── cci_mpf_shim_pwrite │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_pwrite.sv │ │ │ │ │ │ └── cci_mpf_shim_pwrite.vh │ │ │ │ │ ├── cci_mpf_shim_rsp_order.sv │ │ │ │ │ ├── cci_mpf_shim_vc_map.sv │ │ │ │ │ ├── cci_mpf_shim_vtp │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_vtp.sv │ │ │ │ │ │ ├── cci_mpf_shim_vtp.vh │ │ │ │ │ │ ├── cci_mpf_svc_vtp.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pipe.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pt_walk.sv │ │ │ │ │ │ └── cci_mpf_svc_vtp_tlb.sv │ │ │ │ │ └── cci_mpf_shim_wro │ │ │ │ │ │ ├── cci_mpf_shim_wro.sv │ │ │ │ │ │ ├── cci_mpf_shim_wro.vh │ │ │ │ │ │ ├── cci_mpf_shim_wro_epoch_order.sv │ │ │ │ │ │ └── cci_mpf_shim_wro_filter_group.sv │ │ │ │ ├── cci_mpf.sv │ │ │ │ ├── cci_mpf_config.vh │ │ │ │ ├── cci_mpf_csrs.vh │ │ │ │ ├── cci_mpf_csrs_pkg.sv │ │ │ │ ├── cci_mpf_null.sv │ │ │ │ ├── cci_mpf_pipe_std.sv │ │ │ │ └── cci_mpf_sources.txt │ │ │ └── sim │ │ │ │ └── cci_mpf_sim_addenda.txt │ │ ├── samples │ │ │ └── afu │ │ │ │ ├── cci_mpf_library_import.qsf │ │ │ │ ├── ccip_mpf_nlb.sv │ │ │ │ └── ccip_slow_mpf_nlb.sv │ │ ├── scripts │ │ │ ├── iterate.sh │ │ │ └── test-helloalivtpnlb-ase.sh │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── CMakeLists.txt │ │ │ ├── README │ │ │ ├── doc │ │ │ │ ├── Doxyfile.in │ │ │ │ ├── DoxygenLayout.xml │ │ │ │ └── doxygen.cmake │ │ │ ├── include │ │ │ │ ├── aalsdk │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── IMPF.h │ │ │ │ │ │ ├── MPFService.h │ │ │ │ │ │ └── config.h │ │ │ │ ├── opae │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ │ ├── connect.h │ │ │ │ │ │ ├── csrs.h │ │ │ │ │ │ ├── cxx │ │ │ │ │ │ ├── mpf_handle.h │ │ │ │ │ │ └── mpf_shared_buffer.h │ │ │ │ │ │ ├── mpf.h │ │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ │ ├── shim_vtp.h │ │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ │ └── types.h │ │ │ │ └── vai │ │ │ │ │ └── mpf │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ ├── connect.h │ │ │ │ │ ├── csrs.h │ │ │ │ │ ├── mpf.h │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ └── types.h │ │ │ ├── src │ │ │ │ ├── libmpf++ │ │ │ │ │ ├── mpf_handle.cpp │ │ │ │ │ └── mpf_shared_buffer.cpp │ │ │ │ ├── libmpf │ │ │ │ │ ├── connect.c │ │ │ │ │ ├── csrs.c │ │ │ │ │ ├── mpf_internal.h │ │ │ │ │ ├── mpf_os.c │ │ │ │ │ ├── mpf_os.h │ │ │ │ │ ├── shim_latency_qos.c │ │ │ │ │ ├── shim_pwrite.c │ │ │ │ │ ├── shim_vc_map.c │ │ │ │ │ ├── shim_vtp.c │ │ │ │ │ ├── shim_vtp_internal.h │ │ │ │ │ ├── shim_vtp_pt.c │ │ │ │ │ ├── shim_vtp_pt.h │ │ │ │ │ └── shim_wro.c │ │ │ │ └── mpf.cmake │ │ │ ├── src_aal │ │ │ │ ├── cci_mpf_service.cpp │ │ │ │ ├── cci_mpf_service.h │ │ │ │ ├── cci_mpf_shim_latency_qos.cpp │ │ │ │ ├── cci_mpf_shim_latency_qos.h │ │ │ │ ├── cci_mpf_shim_pwrite.cpp │ │ │ │ ├── cci_mpf_shim_pwrite.h │ │ │ │ ├── cci_mpf_shim_vc_map.cpp │ │ │ │ ├── cci_mpf_shim_vc_map.h │ │ │ │ ├── cci_mpf_shim_vtp.cpp │ │ │ │ ├── cci_mpf_shim_vtp.h │ │ │ │ ├── cci_mpf_shim_vtp_pt.cpp │ │ │ │ ├── cci_mpf_shim_vtp_pt.h │ │ │ │ ├── cci_mpf_shim_wro.cpp │ │ │ │ ├── cci_mpf_shim_wro.h │ │ │ │ └── mpf_aal.cmake │ │ │ └── src_vai │ │ │ │ ├── connect.c │ │ │ │ ├── csrs.c │ │ │ │ ├── mpf_internal.h │ │ │ │ ├── mpf_vai.cmake │ │ │ │ ├── shim_latency_qos.c │ │ │ │ ├── shim_pwrite.c │ │ │ │ ├── shim_vc_map.c │ │ │ │ └── shim_wro.c │ │ └── test │ │ │ └── test-mpf │ │ │ ├── base │ │ │ ├── hw │ │ │ │ ├── par │ │ │ │ │ └── cci_mpf_test_base_PAR_files.qsf │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf_default.vh │ │ │ │ │ ├── cci_test_afu.sv │ │ │ │ │ ├── cci_test_csrs.sv │ │ │ │ │ ├── cci_test_csrs.vh │ │ │ │ │ └── sys_cfg_pkg.svh │ │ │ │ └── sim │ │ │ │ │ ├── cci_mpf_test_base_addenda.txt │ │ │ │ │ └── setup_ase_sim.py │ │ │ └── sw │ │ │ │ ├── base_include.mk │ │ │ │ ├── cci_test.h │ │ │ │ ├── cci_test_main.cpp │ │ │ │ ├── opae_svc_wrapper.cpp │ │ │ │ └── opae_svc_wrapper.h │ │ │ ├── test_cci_mpf_null │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_cci_mpf_null.json │ │ │ │ │ └── test_cci_mpf_null.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── test_cci_mpf_null.cpp │ │ │ │ └── test_cci_mpf_null.h │ │ │ ├── test_mem_perf │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_mem_perf.json │ │ │ │ │ └── test_mem_perf.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── compute_latency_qos_params.cpp │ │ │ │ ├── compute_vc_map_params.cpp │ │ │ │ ├── scripts │ │ │ │ ├── plot_buffer_credits.gp │ │ │ │ ├── plot_buffer_credits_rw.gp │ │ │ │ ├── plot_lat.sh │ │ │ │ ├── plot_perf.gp │ │ │ │ ├── plot_perf.sh │ │ │ │ ├── run_lat.sh │ │ │ │ └── run_perf.sh │ │ │ │ ├── test_mem_latency.cpp │ │ │ │ ├── test_mem_perf.cpp │ │ │ │ ├── test_mem_perf.h │ │ │ │ └── test_mem_perf_common.cpp │ │ │ └── test_random │ │ │ ├── hw │ │ │ ├── rtl │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ ├── sources.txt │ │ │ │ ├── test_random.json │ │ │ │ └── test_random.sv │ │ │ └── sim │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── test_random.cpp │ │ │ └── test_random.h │ └── BBB_vai_mux_nested │ │ └── hw │ │ ├── par │ │ └── ccip_mux.qsf │ │ ├── rtl │ │ ├── a10_ram_sdp_wysiwyg.v │ │ ├── ccip_front_end.sv │ │ ├── ccip_intf_regs.sv │ │ ├── ccip_legacy_mux_nested.sv │ │ ├── ccip_mux_legacy.sv │ │ ├── fair_arbiter.sv │ │ ├── gram_sdp.v │ │ ├── sync_C1Tx_fifo.v │ │ ├── vai_audit_rx.sv │ │ ├── vai_audit_rx2.sv │ │ ├── vai_audit_tx.sv │ │ ├── vai_mgr.sv │ │ ├── vai_mgr_afu.sv │ │ ├── vai_mux.sv │ │ └── vendor_defines.vh │ │ └── sim │ │ ├── cci_mux_sim_addenda.txt │ │ └── mux_simfiles.list ├── origin_test │ ├── Makefile │ ├── image.cpp │ ├── image.h │ ├── input.png │ ├── main.cpp │ └── output.png ├── rtl │ ├── cci_mux.sv │ ├── ccip_std_afu.sv │ ├── ccip_std_afu_wrapper.sv │ ├── grayscale.sv │ ├── grayscale_csr.sv │ ├── grayscale_fifo.sv │ ├── grayscale_pkg.sv │ └── grayscale_requestor.sv ├── sources.txt └── test │ ├── ccip_std_afu.h │ ├── ccip_test_pkt.cpp │ ├── ccip_test_pkt.h │ ├── config-1.txt │ ├── config-2.txt │ └── main.cpp ├── c3-signal-asynchrony-sdspi ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bench │ └── cpp │ │ ├── .gitignore │ │ ├── .gtkwaverc │ │ ├── autotest_tb.cpp │ │ ├── sdspisim.cpp │ │ ├── sdspisim.h │ │ ├── testb.h │ │ └── wb_tb.h ├── bug8.instrument.cfg ├── rtl │ ├── llsdspi.v │ └── sdspi.v ├── sources.txt └── vivado_synth │ └── sdspi_wrapper.v ├── c4-signal-asynchrony-axi-stream-fifo ├── .gitignore ├── Makefile ├── Makefile.lc ├── README.md ├── instrument.txt ├── n6.instrument.cfg ├── rtl │ ├── axis_async_fifo.v │ ├── axis_fifo_wrapper.v │ ├── axis_register.v │ └── test_axis_async_fifo.v ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp ├── common ├── AXI_WRAPPER.tcl.template ├── Makefile.ILA.rules ├── Makefile.STP.rules ├── Makefile.env ├── Makefile.rules ├── altera │ ├── 220model.v │ └── altera_mf.v ├── cci_afu.json ├── ccip_dewrapper.sv ├── ccip_dewrapper_async.sv ├── clk250.xdc ├── libvai │ ├── include │ │ ├── hardcloud │ │ │ ├── hardcloud_app.h │ │ │ └── vai_svc_wrapper.h │ │ └── vai │ │ │ ├── fpga.h │ │ │ ├── mpf │ │ │ ├── cci_mpf_csrs.h │ │ │ ├── connect.h │ │ │ ├── csrs.h │ │ │ ├── mpf.h │ │ │ ├── shim_latency_qos.h │ │ │ ├── shim_pwrite.h │ │ │ ├── shim_vc_map.h │ │ │ ├── shim_wro.h │ │ │ └── types.h │ │ │ └── wrapper.h │ └── lib │ │ ├── libMPF_VAI.so │ │ ├── libhardcloud.so │ │ └── libvai-c-ase.so ├── trans.pl └── xilinx │ └── fakeila.sv ├── d1-buffer-overflow-rsd ├── .gitignore ├── .gtkwaverc ├── Makefile ├── Makefile.lc ├── README.md ├── bug3.instrument.cfg ├── ccip │ ├── device_if │ │ ├── avalon_mem_if.vh │ │ ├── avalon_mem_if_dbg.vh │ │ ├── ccip_if_clock.sv │ │ ├── ccip_if_pkg.sv │ │ └── device_if.vh │ ├── platform_afu_top_config.vh │ ├── platform_if.vh │ └── platform_shims │ │ ├── README.md │ │ ├── platform_shim_avalon_mem_if.sv │ │ ├── platform_shim_ccip.sv │ │ ├── platform_shim_ccip_std_afu.sv │ │ └── utils │ │ ├── avalon_mem_if_async_shim.sv │ │ ├── avalon_mem_if_connect.sv │ │ ├── avalon_mem_if_reg.sv │ │ ├── platform_utils_ccip_activity_cnt.sv │ │ ├── platform_utils_ccip_async_shim.sv │ │ ├── platform_utils_ccip_reg.sv │ │ └── quartus_ip │ │ ├── README │ │ ├── gen_platform_ip.sh │ │ ├── platform_utils_avalon_dc_fifo.sdc │ │ ├── platform_utils_avalon_dc_fifo.v │ │ ├── platform_utils_avalon_mm_bridge.v │ │ ├── platform_utils_avalon_mm_clock_crossing_bridge.v │ │ ├── platform_utils_dc_fifo.sdc │ │ ├── platform_utils_dc_fifo.sv │ │ ├── platform_utils_dcfifo_synchronizer_bundle.v │ │ └── platform_utils_std_synchronizer_nocut.v ├── lib │ ├── BBB_cci_mpf │ │ ├── README │ │ ├── hw │ │ │ ├── README │ │ │ ├── par │ │ │ │ ├── README │ │ │ │ ├── qsf_cci_mpf_PAR_files.qsf │ │ │ │ └── sdc_cci_mpf.sdc │ │ │ ├── rtl │ │ │ │ ├── cci-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_csr_if.vh │ │ │ │ │ ├── cci_csr_if_pkg.sv │ │ │ │ │ ├── ccip_feature_list.h │ │ │ │ │ ├── ccip_feature_list_pkg.sv │ │ │ │ │ ├── ccip_if_funcs_pkg.sv │ │ │ │ │ ├── ccip_if_pkg.sv │ │ │ │ │ ├── ccis_if_funcs_pkg.sv │ │ │ │ │ └── ccis_if_pkg.sv │ │ │ │ ├── cci-mpf-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_if.vh │ │ │ │ │ ├── cci_mpf_if_dbg.vh │ │ │ │ │ ├── cci_mpf_if_pkg.sv │ │ │ │ │ ├── cci_mpf_platform.vh │ │ │ │ │ ├── ccip_wires_to_mpf.sv │ │ │ │ │ └── ccis_wires_to_mpf.sv │ │ │ │ ├── cci-mpf-prims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_prim_arb_rr.sv │ │ │ │ │ ├── cci_mpf_prim_fifo1.sv │ │ │ │ │ ├── cci_mpf_prim_fifo2.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_bram.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_filter_cam.sv │ │ │ │ │ ├── cci_mpf_prim_filter_counting.sv │ │ │ │ │ ├── cci_mpf_prim_filter_decode.sv │ │ │ │ │ ├── cci_mpf_prim_hash.vh │ │ │ │ │ ├── cci_mpf_prim_heap.sv │ │ │ │ │ ├── cci_mpf_prim_lfsr.sv │ │ │ │ │ ├── cci_mpf_prim_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_onehot_to_bin.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport_byteena.sv │ │ │ │ │ ├── cci_mpf_prim_ram_simple.sv │ │ │ │ │ ├── cci_mpf_prim_repl_lru_pseudo.sv │ │ │ │ │ ├── cci_mpf_prim_repl_random.sv │ │ │ │ │ ├── cci_mpf_prim_rob.sv │ │ │ │ │ ├── cci_mpf_prim_semaphore_cam.sv │ │ │ │ │ ├── cci_mpf_prim_track_active_reqs.sv │ │ │ │ │ └── cci_mpf_prim_track_multi_write.sv │ │ │ │ ├── cci-mpf-shims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_shim.vh │ │ │ │ │ ├── cci_mpf_shim_buffer_afu.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_epoch.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_lockstep.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_csr.sv │ │ │ │ │ ├── cci_mpf_shim_dbg_history.sv │ │ │ │ │ ├── cci_mpf_shim_dedup_reads.sv │ │ │ │ │ ├── cci_mpf_shim_detect_eop.sv │ │ │ │ │ ├── cci_mpf_shim_edge │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_edge.vh │ │ │ │ │ │ ├── cci_mpf_shim_edge_afu.sv │ │ │ │ │ │ └── cci_mpf_shim_edge_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_latency_qos.sv │ │ │ │ │ ├── cci_mpf_shim_mux.sv │ │ │ │ │ ├── cci_mpf_shim_null.sv │ │ │ │ │ ├── cci_mpf_shim_pkg.sv │ │ │ │ │ ├── cci_mpf_shim_pwrite │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_pwrite.sv │ │ │ │ │ │ └── cci_mpf_shim_pwrite.vh │ │ │ │ │ ├── cci_mpf_shim_rsp_order.sv │ │ │ │ │ ├── cci_mpf_shim_vc_map.sv │ │ │ │ │ ├── cci_mpf_shim_vtp │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_vtp.sv │ │ │ │ │ │ ├── cci_mpf_shim_vtp.vh │ │ │ │ │ │ ├── cci_mpf_svc_vtp.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pipe.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pt_walk.sv │ │ │ │ │ │ └── cci_mpf_svc_vtp_tlb.sv │ │ │ │ │ └── cci_mpf_shim_wro │ │ │ │ │ │ ├── cci_mpf_shim_wro.sv │ │ │ │ │ │ ├── cci_mpf_shim_wro.vh │ │ │ │ │ │ ├── cci_mpf_shim_wro_epoch_order.sv │ │ │ │ │ │ └── cci_mpf_shim_wro_filter_group.sv │ │ │ │ ├── cci_mpf.sv │ │ │ │ ├── cci_mpf_config.vh │ │ │ │ ├── cci_mpf_csrs.vh │ │ │ │ ├── cci_mpf_csrs_pkg.sv │ │ │ │ ├── cci_mpf_null.sv │ │ │ │ ├── cci_mpf_pipe_std.sv │ │ │ │ └── cci_mpf_sources.txt │ │ │ └── sim │ │ │ │ └── cci_mpf_sim_addenda.txt │ │ ├── samples │ │ │ └── afu │ │ │ │ ├── cci_mpf_library_import.qsf │ │ │ │ ├── ccip_mpf_nlb.sv │ │ │ │ └── ccip_slow_mpf_nlb.sv │ │ ├── scripts │ │ │ ├── iterate.sh │ │ │ └── test-helloalivtpnlb-ase.sh │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── CMakeLists.txt │ │ │ ├── README │ │ │ ├── doc │ │ │ │ ├── Doxyfile.in │ │ │ │ ├── DoxygenLayout.xml │ │ │ │ └── doxygen.cmake │ │ │ ├── include │ │ │ │ ├── aalsdk │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── IMPF.h │ │ │ │ │ │ ├── MPFService.h │ │ │ │ │ │ └── config.h │ │ │ │ ├── opae │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ │ ├── connect.h │ │ │ │ │ │ ├── csrs.h │ │ │ │ │ │ ├── cxx │ │ │ │ │ │ ├── mpf_handle.h │ │ │ │ │ │ └── mpf_shared_buffer.h │ │ │ │ │ │ ├── mpf.h │ │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ │ ├── shim_vtp.h │ │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ │ └── types.h │ │ │ │ └── vai │ │ │ │ │ └── mpf │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ ├── connect.h │ │ │ │ │ ├── csrs.h │ │ │ │ │ ├── mpf.h │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ └── types.h │ │ │ ├── src │ │ │ │ ├── libmpf++ │ │ │ │ │ ├── mpf_handle.cpp │ │ │ │ │ └── mpf_shared_buffer.cpp │ │ │ │ ├── libmpf │ │ │ │ │ ├── connect.c │ │ │ │ │ ├── csrs.c │ │ │ │ │ ├── mpf_internal.h │ │ │ │ │ ├── mpf_os.c │ │ │ │ │ ├── mpf_os.h │ │ │ │ │ ├── shim_latency_qos.c │ │ │ │ │ ├── shim_pwrite.c │ │ │ │ │ ├── shim_vc_map.c │ │ │ │ │ ├── shim_vtp.c │ │ │ │ │ ├── shim_vtp_internal.h │ │ │ │ │ ├── shim_vtp_pt.c │ │ │ │ │ ├── shim_vtp_pt.h │ │ │ │ │ └── shim_wro.c │ │ │ │ └── mpf.cmake │ │ │ ├── src_aal │ │ │ │ ├── cci_mpf_service.cpp │ │ │ │ ├── cci_mpf_service.h │ │ │ │ ├── cci_mpf_shim_latency_qos.cpp │ │ │ │ ├── cci_mpf_shim_latency_qos.h │ │ │ │ ├── cci_mpf_shim_pwrite.cpp │ │ │ │ ├── cci_mpf_shim_pwrite.h │ │ │ │ ├── cci_mpf_shim_vc_map.cpp │ │ │ │ ├── cci_mpf_shim_vc_map.h │ │ │ │ ├── cci_mpf_shim_vtp.cpp │ │ │ │ ├── cci_mpf_shim_vtp.h │ │ │ │ ├── cci_mpf_shim_vtp_pt.cpp │ │ │ │ ├── cci_mpf_shim_vtp_pt.h │ │ │ │ ├── cci_mpf_shim_wro.cpp │ │ │ │ ├── cci_mpf_shim_wro.h │ │ │ │ └── mpf_aal.cmake │ │ │ └── src_vai │ │ │ │ ├── connect.c │ │ │ │ ├── csrs.c │ │ │ │ ├── mpf_internal.h │ │ │ │ ├── mpf_vai.cmake │ │ │ │ ├── shim_latency_qos.c │ │ │ │ ├── shim_pwrite.c │ │ │ │ ├── shim_vc_map.c │ │ │ │ └── shim_wro.c │ │ └── test │ │ │ └── test-mpf │ │ │ ├── base │ │ │ ├── hw │ │ │ │ ├── par │ │ │ │ │ └── cci_mpf_test_base_PAR_files.qsf │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf_default.vh │ │ │ │ │ ├── cci_test_afu.sv │ │ │ │ │ ├── cci_test_csrs.sv │ │ │ │ │ ├── cci_test_csrs.vh │ │ │ │ │ └── sys_cfg_pkg.svh │ │ │ │ └── sim │ │ │ │ │ ├── cci_mpf_test_base_addenda.txt │ │ │ │ │ └── setup_ase_sim.py │ │ │ └── sw │ │ │ │ ├── base_include.mk │ │ │ │ ├── cci_test.h │ │ │ │ ├── cci_test_main.cpp │ │ │ │ ├── opae_svc_wrapper.cpp │ │ │ │ └── opae_svc_wrapper.h │ │ │ ├── test_cci_mpf_null │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_cci_mpf_null.json │ │ │ │ │ └── test_cci_mpf_null.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── test_cci_mpf_null.cpp │ │ │ │ └── test_cci_mpf_null.h │ │ │ ├── test_mem_perf │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_mem_perf.json │ │ │ │ │ └── test_mem_perf.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── compute_latency_qos_params.cpp │ │ │ │ ├── compute_vc_map_params.cpp │ │ │ │ ├── scripts │ │ │ │ ├── plot_buffer_credits.gp │ │ │ │ ├── plot_buffer_credits_rw.gp │ │ │ │ ├── plot_lat.sh │ │ │ │ ├── plot_perf.gp │ │ │ │ ├── plot_perf.sh │ │ │ │ ├── run_lat.sh │ │ │ │ └── run_perf.sh │ │ │ │ ├── test_mem_latency.cpp │ │ │ │ ├── test_mem_perf.cpp │ │ │ │ ├── test_mem_perf.h │ │ │ │ └── test_mem_perf_common.cpp │ │ │ └── test_random │ │ │ ├── hw │ │ │ ├── rtl │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ ├── sources.txt │ │ │ │ ├── test_random.json │ │ │ │ └── test_random.sv │ │ │ └── sim │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── test_random.cpp │ │ │ └── test_random.h │ └── BBB_ccip_async │ │ ├── hw │ │ ├── par │ │ │ ├── ccip_async.sdc │ │ │ ├── ccip_async_addenda.qsf │ │ │ └── sample_ccip_async_import.qsf │ │ ├── rtl │ │ │ ├── ccip_afifo_channel.sv │ │ │ ├── ccip_async_activity_cnt.sv │ │ │ └── ccip_async_shim.sv │ │ └── sim │ │ │ └── ccip_async_sim_addenda.txt │ │ └── samples │ │ ├── async_nlb100.sv │ │ ├── async_nlb150.sv │ │ ├── async_nlb200.sv │ │ └── async_nlb300.sv ├── origin_test │ ├── Makefile │ └── main.cpp ├── rtl │ ├── BM_lamda.v │ ├── DP_RAM.v │ ├── GF_matrix_ascending_binary.v │ ├── GF_matrix_dec.v │ ├── GF_mult_add_syndromes.v │ ├── Omega_Phy.v │ ├── RS_dec.v │ ├── ccip_std_afu.sv │ ├── ccip_std_afu_wrapper.sv │ ├── error_correction.v │ ├── input_syndromes.v │ ├── lamda_roots.v │ ├── nomux.txt │ ├── out_stage.v │ ├── reed_solomon_decoder.json │ ├── reed_solomon_decoder.sv │ ├── reed_solomon_decoder_csr.sv │ ├── reed_solomon_decoder_fifo.sv │ ├── reed_solomon_decoder_pkg.sv │ ├── reed_solomon_decoder_requestor.sv │ ├── sources.txt │ └── transport_in2out.v ├── sources.txt └── test │ ├── ccip_std_afu.h │ ├── ccip_test_pkt.cpp │ ├── ccip_test_pkt.h │ ├── config.txt │ ├── main.cpp │ └── pkt.txt ├── d10-failure-to-update-sha512 ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bug1.instrument.cfg ├── ccip │ ├── device_if │ │ ├── avalon_mem_if.vh │ │ ├── avalon_mem_if_dbg.vh │ │ ├── ccip_if_clock.sv │ │ ├── ccip_if_pkg.sv │ │ └── device_if.vh │ ├── platform_afu_top_config.vh │ ├── platform_if.vh │ └── platform_shims │ │ ├── README.md │ │ ├── platform_shim_avalon_mem_if.sv │ │ ├── platform_shim_ccip.sv │ │ ├── platform_shim_ccip_std_afu.sv │ │ └── utils │ │ ├── avalon_mem_if_async_shim.sv │ │ ├── avalon_mem_if_connect.sv │ │ ├── avalon_mem_if_reg.sv │ │ ├── platform_utils_ccip_activity_cnt.sv │ │ ├── platform_utils_ccip_async_shim.sv │ │ ├── platform_utils_ccip_reg.sv │ │ └── quartus_ip │ │ ├── README │ │ ├── gen_platform_ip.sh │ │ ├── platform_utils_avalon_dc_fifo.sdc │ │ ├── platform_utils_avalon_dc_fifo.v │ │ ├── platform_utils_avalon_mm_bridge.v │ │ ├── platform_utils_avalon_mm_clock_crossing_bridge.v │ │ ├── platform_utils_dc_fifo.sdc │ │ ├── platform_utils_dc_fifo.sv │ │ ├── platform_utils_dcfifo_synchronizer_bundle.v │ │ └── platform_utils_std_synchronizer_nocut.v ├── rtl │ ├── ccip_std_afu.sv │ ├── ccip_std_afu_wrapper.sv │ ├── sha512.sv │ ├── sha512_core.v │ ├── sha512_csr.sv │ ├── sha512_h_constants.v │ ├── sha512_k_constants.v │ ├── sha512_pkg.sv │ ├── sha512_requestor.sv │ └── sha512_w_mem.v ├── sources.txt └── test │ ├── ccip_std_afu.h │ ├── ccip_test_pkt.cpp │ ├── ccip_test_pkt.h │ ├── config.txt │ └── main.cpp ├── d11-failure-to-update-frame-fifo ├── .gitignore ├── Makefile ├── README.md ├── instrument.txt ├── n9.instrument.cfg ├── rtl │ ├── axis_frame_fifo.v │ └── test_axis_fifo.v ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp ├── d12-failure-to-update-frame-fifo ├── .gitignore ├── Makefile ├── README.md ├── instrument.txt ├── n3.instrument.cfg ├── rtl │ ├── axis_fifo.v │ └── test_axis_fifo.v ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp ├── d13-failure-to-update-frame-len ├── .gitignore ├── Makefile ├── README.md ├── instrument.txt ├── n1.instrument.cfg ├── rtl │ ├── axis_frame_len.v │ ├── axis_frame_len_correctversion.v │ └── test_axis_frame_len_8.v ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp ├── d2-buffer-overflow-grayscale ├── .gitignore ├── .gtkwaverc ├── Makefile ├── Makefile.lc ├── README.md ├── bug4.instrument.cfg ├── ccip │ ├── device_if │ │ ├── avalon_mem_if.vh │ │ ├── avalon_mem_if_dbg.vh │ │ ├── ccip_if_clock.sv │ │ ├── ccip_if_pkg.sv │ │ └── device_if.vh │ ├── platform_afu_top_config.vh │ ├── platform_if.vh │ └── platform_shims │ │ ├── README.md │ │ ├── platform_shim_avalon_mem_if.sv │ │ ├── platform_shim_ccip.sv │ │ ├── platform_shim_ccip_std_afu.sv │ │ └── utils │ │ ├── avalon_mem_if_async_shim.sv │ │ ├── avalon_mem_if_connect.sv │ │ ├── avalon_mem_if_reg.sv │ │ ├── platform_utils_ccip_activity_cnt.sv │ │ ├── platform_utils_ccip_async_shim.sv │ │ ├── platform_utils_ccip_reg.sv │ │ └── quartus_ip │ │ ├── README │ │ ├── gen_platform_ip.sh │ │ ├── platform_utils_avalon_dc_fifo.sdc │ │ ├── platform_utils_avalon_dc_fifo.v │ │ ├── platform_utils_avalon_mm_bridge.v │ │ ├── platform_utils_avalon_mm_clock_crossing_bridge.v │ │ ├── platform_utils_dc_fifo.sdc │ │ ├── platform_utils_dc_fifo.sv │ │ ├── platform_utils_dcfifo_synchronizer_bundle.v │ │ └── platform_utils_std_synchronizer_nocut.v ├── lib │ ├── BBB_cci_mpf │ │ ├── README │ │ ├── hw │ │ │ ├── README │ │ │ ├── par │ │ │ │ ├── README │ │ │ │ ├── qsf_cci_mpf_PAR_files.qsf │ │ │ │ └── sdc_cci_mpf.sdc │ │ │ ├── rtl │ │ │ │ ├── cci-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_csr_if.vh │ │ │ │ │ ├── cci_csr_if_pkg.sv │ │ │ │ │ ├── ccip_feature_list.h │ │ │ │ │ ├── ccip_feature_list_pkg.sv │ │ │ │ │ ├── ccip_if_funcs_pkg.sv │ │ │ │ │ ├── ccip_if_pkg.sv │ │ │ │ │ ├── ccis_if_funcs_pkg.sv │ │ │ │ │ └── ccis_if_pkg.sv │ │ │ │ ├── cci-mpf-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_if.vh │ │ │ │ │ ├── cci_mpf_if_dbg.vh │ │ │ │ │ ├── cci_mpf_if_pkg.sv │ │ │ │ │ ├── cci_mpf_platform.vh │ │ │ │ │ ├── ccip_wires_to_mpf.sv │ │ │ │ │ └── ccis_wires_to_mpf.sv │ │ │ │ ├── cci-mpf-prims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_prim_arb_rr.sv │ │ │ │ │ ├── cci_mpf_prim_fifo1.sv │ │ │ │ │ ├── cci_mpf_prim_fifo2.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_bram.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_filter_cam.sv │ │ │ │ │ ├── cci_mpf_prim_filter_counting.sv │ │ │ │ │ ├── cci_mpf_prim_filter_decode.sv │ │ │ │ │ ├── cci_mpf_prim_hash.vh │ │ │ │ │ ├── cci_mpf_prim_heap.sv │ │ │ │ │ ├── cci_mpf_prim_lfsr.sv │ │ │ │ │ ├── cci_mpf_prim_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_onehot_to_bin.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport_byteena.sv │ │ │ │ │ ├── cci_mpf_prim_ram_simple.sv │ │ │ │ │ ├── cci_mpf_prim_repl_lru_pseudo.sv │ │ │ │ │ ├── cci_mpf_prim_repl_random.sv │ │ │ │ │ ├── cci_mpf_prim_rob.sv │ │ │ │ │ ├── cci_mpf_prim_semaphore_cam.sv │ │ │ │ │ ├── cci_mpf_prim_track_active_reqs.sv │ │ │ │ │ └── cci_mpf_prim_track_multi_write.sv │ │ │ │ ├── cci-mpf-shims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_shim.vh │ │ │ │ │ ├── cci_mpf_shim_buffer_afu.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_epoch.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_lockstep.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_csr.sv │ │ │ │ │ ├── cci_mpf_shim_dbg_history.sv │ │ │ │ │ ├── cci_mpf_shim_dedup_reads.sv │ │ │ │ │ ├── cci_mpf_shim_detect_eop.sv │ │ │ │ │ ├── cci_mpf_shim_edge │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_edge.vh │ │ │ │ │ │ ├── cci_mpf_shim_edge_afu.sv │ │ │ │ │ │ └── cci_mpf_shim_edge_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_latency_qos.sv │ │ │ │ │ ├── cci_mpf_shim_mux.sv │ │ │ │ │ ├── cci_mpf_shim_null.sv │ │ │ │ │ ├── cci_mpf_shim_pkg.sv │ │ │ │ │ ├── cci_mpf_shim_pwrite │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_pwrite.sv │ │ │ │ │ │ └── cci_mpf_shim_pwrite.vh │ │ │ │ │ ├── cci_mpf_shim_rsp_order.sv │ │ │ │ │ ├── cci_mpf_shim_vc_map.sv │ │ │ │ │ ├── cci_mpf_shim_vtp │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_vtp.sv │ │ │ │ │ │ ├── cci_mpf_shim_vtp.vh │ │ │ │ │ │ ├── cci_mpf_svc_vtp.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pipe.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pt_walk.sv │ │ │ │ │ │ └── cci_mpf_svc_vtp_tlb.sv │ │ │ │ │ └── cci_mpf_shim_wro │ │ │ │ │ │ ├── cci_mpf_shim_wro.sv │ │ │ │ │ │ ├── cci_mpf_shim_wro.vh │ │ │ │ │ │ ├── cci_mpf_shim_wro_epoch_order.sv │ │ │ │ │ │ └── cci_mpf_shim_wro_filter_group.sv │ │ │ │ ├── cci_mpf.sv │ │ │ │ ├── cci_mpf_config.vh │ │ │ │ ├── cci_mpf_csrs.vh │ │ │ │ ├── cci_mpf_csrs_pkg.sv │ │ │ │ ├── cci_mpf_null.sv │ │ │ │ ├── cci_mpf_pipe_std.sv │ │ │ │ └── cci_mpf_sources.txt │ │ │ └── sim │ │ │ │ └── cci_mpf_sim_addenda.txt │ │ ├── samples │ │ │ └── afu │ │ │ │ ├── cci_mpf_library_import.qsf │ │ │ │ ├── ccip_mpf_nlb.sv │ │ │ │ └── ccip_slow_mpf_nlb.sv │ │ ├── scripts │ │ │ ├── iterate.sh │ │ │ └── test-helloalivtpnlb-ase.sh │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── CMakeLists.txt │ │ │ ├── README │ │ │ ├── doc │ │ │ │ ├── Doxyfile.in │ │ │ │ ├── DoxygenLayout.xml │ │ │ │ └── doxygen.cmake │ │ │ ├── include │ │ │ │ ├── aalsdk │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── IMPF.h │ │ │ │ │ │ ├── MPFService.h │ │ │ │ │ │ └── config.h │ │ │ │ ├── opae │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ │ ├── connect.h │ │ │ │ │ │ ├── csrs.h │ │ │ │ │ │ ├── cxx │ │ │ │ │ │ ├── mpf_handle.h │ │ │ │ │ │ └── mpf_shared_buffer.h │ │ │ │ │ │ ├── mpf.h │ │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ │ ├── shim_vtp.h │ │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ │ └── types.h │ │ │ │ └── vai │ │ │ │ │ └── mpf │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ ├── connect.h │ │ │ │ │ ├── csrs.h │ │ │ │ │ ├── mpf.h │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ └── types.h │ │ │ ├── src │ │ │ │ ├── libmpf++ │ │ │ │ │ ├── mpf_handle.cpp │ │ │ │ │ └── mpf_shared_buffer.cpp │ │ │ │ ├── libmpf │ │ │ │ │ ├── connect.c │ │ │ │ │ ├── csrs.c │ │ │ │ │ ├── mpf_internal.h │ │ │ │ │ ├── mpf_os.c │ │ │ │ │ ├── mpf_os.h │ │ │ │ │ ├── shim_latency_qos.c │ │ │ │ │ ├── shim_pwrite.c │ │ │ │ │ ├── shim_vc_map.c │ │ │ │ │ ├── shim_vtp.c │ │ │ │ │ ├── shim_vtp_internal.h │ │ │ │ │ ├── shim_vtp_pt.c │ │ │ │ │ ├── shim_vtp_pt.h │ │ │ │ │ └── shim_wro.c │ │ │ │ └── mpf.cmake │ │ │ ├── src_aal │ │ │ │ ├── cci_mpf_service.cpp │ │ │ │ ├── cci_mpf_service.h │ │ │ │ ├── cci_mpf_shim_latency_qos.cpp │ │ │ │ ├── cci_mpf_shim_latency_qos.h │ │ │ │ ├── cci_mpf_shim_pwrite.cpp │ │ │ │ ├── cci_mpf_shim_pwrite.h │ │ │ │ ├── cci_mpf_shim_vc_map.cpp │ │ │ │ ├── cci_mpf_shim_vc_map.h │ │ │ │ ├── cci_mpf_shim_vtp.cpp │ │ │ │ ├── cci_mpf_shim_vtp.h │ │ │ │ ├── cci_mpf_shim_vtp_pt.cpp │ │ │ │ ├── cci_mpf_shim_vtp_pt.h │ │ │ │ ├── cci_mpf_shim_wro.cpp │ │ │ │ ├── cci_mpf_shim_wro.h │ │ │ │ └── mpf_aal.cmake │ │ │ └── src_vai │ │ │ │ ├── connect.c │ │ │ │ ├── csrs.c │ │ │ │ ├── mpf_internal.h │ │ │ │ ├── mpf_vai.cmake │ │ │ │ ├── shim_latency_qos.c │ │ │ │ ├── shim_pwrite.c │ │ │ │ ├── shim_vc_map.c │ │ │ │ └── shim_wro.c │ │ └── test │ │ │ └── test-mpf │ │ │ ├── base │ │ │ ├── hw │ │ │ │ ├── par │ │ │ │ │ └── cci_mpf_test_base_PAR_files.qsf │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf_default.vh │ │ │ │ │ ├── cci_test_afu.sv │ │ │ │ │ ├── cci_test_csrs.sv │ │ │ │ │ ├── cci_test_csrs.vh │ │ │ │ │ └── sys_cfg_pkg.svh │ │ │ │ └── sim │ │ │ │ │ ├── cci_mpf_test_base_addenda.txt │ │ │ │ │ └── setup_ase_sim.py │ │ │ └── sw │ │ │ │ ├── base_include.mk │ │ │ │ ├── cci_test.h │ │ │ │ ├── cci_test_main.cpp │ │ │ │ ├── opae_svc_wrapper.cpp │ │ │ │ └── opae_svc_wrapper.h │ │ │ ├── test_cci_mpf_null │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_cci_mpf_null.json │ │ │ │ │ └── test_cci_mpf_null.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── test_cci_mpf_null.cpp │ │ │ │ └── test_cci_mpf_null.h │ │ │ ├── test_mem_perf │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_mem_perf.json │ │ │ │ │ └── test_mem_perf.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── compute_latency_qos_params.cpp │ │ │ │ ├── compute_vc_map_params.cpp │ │ │ │ ├── scripts │ │ │ │ ├── plot_buffer_credits.gp │ │ │ │ ├── plot_buffer_credits_rw.gp │ │ │ │ ├── plot_lat.sh │ │ │ │ ├── plot_perf.gp │ │ │ │ ├── plot_perf.sh │ │ │ │ ├── run_lat.sh │ │ │ │ └── run_perf.sh │ │ │ │ ├── test_mem_latency.cpp │ │ │ │ ├── test_mem_perf.cpp │ │ │ │ ├── test_mem_perf.h │ │ │ │ └── test_mem_perf_common.cpp │ │ │ └── test_random │ │ │ ├── hw │ │ │ ├── rtl │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ ├── sources.txt │ │ │ │ ├── test_random.json │ │ │ │ └── test_random.sv │ │ │ └── sim │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── test_random.cpp │ │ │ └── test_random.h │ └── BBB_ccip_async │ │ ├── hw │ │ ├── par │ │ │ ├── ccip_async.sdc │ │ │ ├── ccip_async_addenda.qsf │ │ │ └── sample_ccip_async_import.qsf │ │ ├── rtl │ │ │ ├── ccip_afifo_channel.sv │ │ │ ├── ccip_async_activity_cnt.sv │ │ │ └── ccip_async_shim.sv │ │ └── sim │ │ │ └── ccip_async_sim_addenda.txt │ │ └── samples │ │ ├── async_nlb100.sv │ │ ├── async_nlb150.sv │ │ ├── async_nlb200.sv │ │ └── async_nlb300.sv ├── origin_test │ ├── Makefile │ ├── image.cpp │ ├── image.h │ ├── input.png │ ├── main.cpp │ └── output.png ├── rtl │ ├── ccip_std_afu.sv │ ├── ccip_std_afu_async.sv │ ├── ccip_std_afu_wrapper.sv │ ├── grayscale.sv │ ├── grayscale_csr.sv │ ├── grayscale_fifo.sv │ ├── grayscale_pkg.sv │ └── grayscale_requestor.sv ├── sources.txt └── test │ ├── ccip_std_afu.h │ ├── ccip_test_pkt.cpp │ ├── ccip_test_pkt.h │ ├── config.txt │ └── main.cpp ├── d3-buffer-overflow-optimus ├── .gitignore ├── .gtkwaverc ├── Makefile ├── Makefile.lc ├── README.md ├── bug5.instrument.cfg ├── ccip │ ├── device_if │ │ ├── avalon_mem_if.vh │ │ ├── avalon_mem_if_dbg.vh │ │ ├── ccip_if_clock.sv │ │ ├── ccip_if_pkg.sv │ │ └── device_if.vh │ ├── platform_afu_top_config.vh │ ├── platform_if.vh │ └── platform_shims │ │ ├── README.md │ │ ├── platform_shim_avalon_mem_if.sv │ │ ├── platform_shim_ccip.sv │ │ ├── platform_shim_ccip_std_afu.sv │ │ └── utils │ │ ├── avalon_mem_if_async_shim.sv │ │ ├── avalon_mem_if_connect.sv │ │ ├── avalon_mem_if_reg.sv │ │ ├── platform_utils_ccip_activity_cnt.sv │ │ ├── platform_utils_ccip_async_shim.sv │ │ ├── platform_utils_ccip_reg.sv │ │ └── quartus_ip │ │ ├── README │ │ ├── gen_platform_ip.sh │ │ ├── platform_utils_avalon_dc_fifo.sdc │ │ ├── platform_utils_avalon_dc_fifo.v │ │ ├── platform_utils_avalon_mm_bridge.v │ │ ├── platform_utils_avalon_mm_clock_crossing_bridge.v │ │ ├── platform_utils_dc_fifo.sdc │ │ ├── platform_utils_dc_fifo.sv │ │ ├── platform_utils_dcfifo_synchronizer_bundle.v │ │ └── platform_utils_std_synchronizer_nocut.v ├── lib │ ├── BBB_cci_mpf │ │ ├── README │ │ ├── hw │ │ │ ├── README │ │ │ ├── par │ │ │ │ ├── README │ │ │ │ ├── qsf_cci_mpf_PAR_files.qsf │ │ │ │ └── sdc_cci_mpf.sdc │ │ │ ├── rtl │ │ │ │ ├── cci-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_csr_if.vh │ │ │ │ │ ├── cci_csr_if_pkg.sv │ │ │ │ │ ├── ccip_feature_list.h │ │ │ │ │ ├── ccip_feature_list_pkg.sv │ │ │ │ │ ├── ccip_if_funcs_pkg.sv │ │ │ │ │ ├── ccip_if_pkg.sv │ │ │ │ │ ├── ccis_if_funcs_pkg.sv │ │ │ │ │ └── ccis_if_pkg.sv │ │ │ │ ├── cci-mpf-if │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_if.vh │ │ │ │ │ ├── cci_mpf_if_dbg.vh │ │ │ │ │ ├── cci_mpf_if_pkg.sv │ │ │ │ │ ├── cci_mpf_platform.vh │ │ │ │ │ ├── ccip_wires_to_mpf.sv │ │ │ │ │ └── ccis_wires_to_mpf.sv │ │ │ │ ├── cci-mpf-prims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_prim_arb_rr.sv │ │ │ │ │ ├── cci_mpf_prim_fifo1.sv │ │ │ │ │ ├── cci_mpf_prim_fifo2.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_bram.sv │ │ │ │ │ ├── cci_mpf_prim_fifo_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_filter_cam.sv │ │ │ │ │ ├── cci_mpf_prim_filter_counting.sv │ │ │ │ │ ├── cci_mpf_prim_filter_decode.sv │ │ │ │ │ ├── cci_mpf_prim_hash.vh │ │ │ │ │ ├── cci_mpf_prim_heap.sv │ │ │ │ │ ├── cci_mpf_prim_lfsr.sv │ │ │ │ │ ├── cci_mpf_prim_lutram.sv │ │ │ │ │ ├── cci_mpf_prim_onehot_to_bin.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport.sv │ │ │ │ │ ├── cci_mpf_prim_ram_dualport_byteena.sv │ │ │ │ │ ├── cci_mpf_prim_ram_simple.sv │ │ │ │ │ ├── cci_mpf_prim_repl_lru_pseudo.sv │ │ │ │ │ ├── cci_mpf_prim_repl_random.sv │ │ │ │ │ ├── cci_mpf_prim_rob.sv │ │ │ │ │ ├── cci_mpf_prim_semaphore_cam.sv │ │ │ │ │ ├── cci_mpf_prim_track_active_reqs.sv │ │ │ │ │ └── cci_mpf_prim_track_multi_write.sv │ │ │ │ ├── cci-mpf-shims │ │ │ │ │ ├── README │ │ │ │ │ ├── cci_mpf_shim.vh │ │ │ │ │ ├── cci_mpf_shim_buffer_afu.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_epoch.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_afu_lockstep.sv │ │ │ │ │ ├── cci_mpf_shim_buffer_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_csr.sv │ │ │ │ │ ├── cci_mpf_shim_dbg_history.sv │ │ │ │ │ ├── cci_mpf_shim_dedup_reads.sv │ │ │ │ │ ├── cci_mpf_shim_detect_eop.sv │ │ │ │ │ ├── cci_mpf_shim_edge │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_edge.vh │ │ │ │ │ │ ├── cci_mpf_shim_edge_afu.sv │ │ │ │ │ │ └── cci_mpf_shim_edge_fiu.sv │ │ │ │ │ ├── cci_mpf_shim_latency_qos.sv │ │ │ │ │ ├── cci_mpf_shim_mux.sv │ │ │ │ │ ├── cci_mpf_shim_null.sv │ │ │ │ │ ├── cci_mpf_shim_pkg.sv │ │ │ │ │ ├── cci_mpf_shim_pwrite │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_pwrite.sv │ │ │ │ │ │ └── cci_mpf_shim_pwrite.vh │ │ │ │ │ ├── cci_mpf_shim_rsp_order.sv │ │ │ │ │ ├── cci_mpf_shim_vc_map.sv │ │ │ │ │ ├── cci_mpf_shim_vtp │ │ │ │ │ │ ├── README │ │ │ │ │ │ ├── cci_mpf_shim_vtp.sv │ │ │ │ │ │ ├── cci_mpf_shim_vtp.vh │ │ │ │ │ │ ├── cci_mpf_svc_vtp.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pipe.sv │ │ │ │ │ │ ├── cci_mpf_svc_vtp_pt_walk.sv │ │ │ │ │ │ └── cci_mpf_svc_vtp_tlb.sv │ │ │ │ │ └── cci_mpf_shim_wro │ │ │ │ │ │ ├── cci_mpf_shim_wro.sv │ │ │ │ │ │ ├── cci_mpf_shim_wro.vh │ │ │ │ │ │ ├── cci_mpf_shim_wro_epoch_order.sv │ │ │ │ │ │ └── cci_mpf_shim_wro_filter_group.sv │ │ │ │ ├── cci_mpf.sv │ │ │ │ ├── cci_mpf_config.vh │ │ │ │ ├── cci_mpf_csrs.vh │ │ │ │ ├── cci_mpf_csrs_pkg.sv │ │ │ │ ├── cci_mpf_null.sv │ │ │ │ ├── cci_mpf_pipe_std.sv │ │ │ │ └── cci_mpf_sources.txt │ │ │ └── sim │ │ │ │ └── cci_mpf_sim_addenda.txt │ │ ├── samples │ │ │ └── afu │ │ │ │ ├── cci_mpf_library_import.qsf │ │ │ │ ├── ccip_mpf_nlb.sv │ │ │ │ └── ccip_slow_mpf_nlb.sv │ │ ├── scripts │ │ │ ├── iterate.sh │ │ │ └── test-helloalivtpnlb-ase.sh │ │ ├── sw │ │ │ ├── .gitignore │ │ │ ├── CMakeLists.txt │ │ │ ├── README │ │ │ ├── doc │ │ │ │ ├── Doxyfile.in │ │ │ │ ├── DoxygenLayout.xml │ │ │ │ └── doxygen.cmake │ │ │ ├── include │ │ │ │ ├── aalsdk │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── IMPF.h │ │ │ │ │ │ ├── MPFService.h │ │ │ │ │ │ └── config.h │ │ │ │ ├── opae │ │ │ │ │ └── mpf │ │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ │ ├── connect.h │ │ │ │ │ │ ├── csrs.h │ │ │ │ │ │ ├── cxx │ │ │ │ │ │ ├── mpf_handle.h │ │ │ │ │ │ └── mpf_shared_buffer.h │ │ │ │ │ │ ├── mpf.h │ │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ │ ├── shim_vtp.h │ │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ │ └── types.h │ │ │ │ └── vai │ │ │ │ │ └── mpf │ │ │ │ │ ├── cci_mpf_csrs.h │ │ │ │ │ ├── connect.h │ │ │ │ │ ├── csrs.h │ │ │ │ │ ├── mpf.h │ │ │ │ │ ├── shim_latency_qos.h │ │ │ │ │ ├── shim_pwrite.h │ │ │ │ │ ├── shim_vc_map.h │ │ │ │ │ ├── shim_wro.h │ │ │ │ │ └── types.h │ │ │ ├── src │ │ │ │ ├── libmpf++ │ │ │ │ │ ├── mpf_handle.cpp │ │ │ │ │ └── mpf_shared_buffer.cpp │ │ │ │ ├── libmpf │ │ │ │ │ ├── connect.c │ │ │ │ │ ├── csrs.c │ │ │ │ │ ├── mpf_internal.h │ │ │ │ │ ├── mpf_os.c │ │ │ │ │ ├── mpf_os.h │ │ │ │ │ ├── shim_latency_qos.c │ │ │ │ │ ├── shim_pwrite.c │ │ │ │ │ ├── shim_vc_map.c │ │ │ │ │ ├── shim_vtp.c │ │ │ │ │ ├── shim_vtp_internal.h │ │ │ │ │ ├── shim_vtp_pt.c │ │ │ │ │ ├── shim_vtp_pt.h │ │ │ │ │ └── shim_wro.c │ │ │ │ └── mpf.cmake │ │ │ ├── src_aal │ │ │ │ ├── cci_mpf_service.cpp │ │ │ │ ├── cci_mpf_service.h │ │ │ │ ├── cci_mpf_shim_latency_qos.cpp │ │ │ │ ├── cci_mpf_shim_latency_qos.h │ │ │ │ ├── cci_mpf_shim_pwrite.cpp │ │ │ │ ├── cci_mpf_shim_pwrite.h │ │ │ │ ├── cci_mpf_shim_vc_map.cpp │ │ │ │ ├── cci_mpf_shim_vc_map.h │ │ │ │ ├── cci_mpf_shim_vtp.cpp │ │ │ │ ├── cci_mpf_shim_vtp.h │ │ │ │ ├── cci_mpf_shim_vtp_pt.cpp │ │ │ │ ├── cci_mpf_shim_vtp_pt.h │ │ │ │ ├── cci_mpf_shim_wro.cpp │ │ │ │ ├── cci_mpf_shim_wro.h │ │ │ │ └── mpf_aal.cmake │ │ │ └── src_vai │ │ │ │ ├── connect.c │ │ │ │ ├── csrs.c │ │ │ │ ├── mpf_internal.h │ │ │ │ ├── mpf_vai.cmake │ │ │ │ ├── shim_latency_qos.c │ │ │ │ ├── shim_pwrite.c │ │ │ │ ├── shim_vc_map.c │ │ │ │ └── shim_wro.c │ │ └── test │ │ │ └── test-mpf │ │ │ ├── base │ │ │ ├── hw │ │ │ │ ├── par │ │ │ │ │ └── cci_mpf_test_base_PAR_files.qsf │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf_default.vh │ │ │ │ │ ├── cci_test_afu.sv │ │ │ │ │ ├── cci_test_csrs.sv │ │ │ │ │ ├── cci_test_csrs.vh │ │ │ │ │ └── sys_cfg_pkg.svh │ │ │ │ └── sim │ │ │ │ │ ├── cci_mpf_test_base_addenda.txt │ │ │ │ │ └── setup_ase_sim.py │ │ │ └── sw │ │ │ │ ├── base_include.mk │ │ │ │ ├── cci_test.h │ │ │ │ ├── cci_test_main.cpp │ │ │ │ ├── opae_svc_wrapper.cpp │ │ │ │ └── opae_svc_wrapper.h │ │ │ ├── test_cci_mpf_null │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_cci_mpf_null.json │ │ │ │ │ └── test_cci_mpf_null.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── test_cci_mpf_null.cpp │ │ │ │ └── test_cci_mpf_null.h │ │ │ ├── test_mem_perf │ │ │ ├── README │ │ │ ├── hw │ │ │ │ ├── rtl │ │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ │ ├── sources.txt │ │ │ │ │ ├── test_mem_perf.json │ │ │ │ │ └── test_mem_perf.sv │ │ │ │ └── sim │ │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ ├── compute_latency_qos_params.cpp │ │ │ │ ├── compute_vc_map_params.cpp │ │ │ │ ├── scripts │ │ │ │ ├── plot_buffer_credits.gp │ │ │ │ ├── plot_buffer_credits_rw.gp │ │ │ │ ├── plot_lat.sh │ │ │ │ ├── plot_perf.gp │ │ │ │ ├── plot_perf.sh │ │ │ │ ├── run_lat.sh │ │ │ │ └── run_perf.sh │ │ │ │ ├── test_mem_latency.cpp │ │ │ │ ├── test_mem_perf.cpp │ │ │ │ ├── test_mem_perf.h │ │ │ │ └── test_mem_perf_common.cpp │ │ │ └── test_random │ │ │ ├── hw │ │ │ ├── rtl │ │ │ │ ├── cci_mpf_test_conf.vh │ │ │ │ ├── sources.txt │ │ │ │ ├── test_random.json │ │ │ │ └── test_random.sv │ │ │ └── sim │ │ │ │ └── setup_ase │ │ │ └── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── test_random.cpp │ │ │ └── test_random.h │ └── BBB_vai_mux_nested │ │ └── hw │ │ ├── par │ │ └── ccip_mux.qsf │ │ ├── rtl │ │ ├── a10_ram_sdp_wysiwyg.v │ │ ├── ccip_front_end.sv │ │ ├── ccip_intf_regs.sv │ │ ├── ccip_legacy_mux_nested.sv │ │ ├── ccip_mux_legacy.sv │ │ ├── fair_arbiter.sv │ │ ├── gram_sdp.v │ │ ├── sync_C1Tx_fifo.v │ │ ├── vai_audit_rx.sv │ │ ├── vai_audit_rx2.sv │ │ ├── vai_audit_tx.sv │ │ ├── vai_mgr.sv │ │ ├── vai_mgr_afu.sv │ │ ├── vai_mux.sv │ │ └── vendor_defines.vh │ │ └── sim │ │ ├── cci_mux_sim_addenda.txt │ │ └── mux_simfiles.list ├── origin_test │ ├── Makefile │ ├── image.cpp │ ├── image.h │ ├── input.png │ ├── main.cpp │ └── output.png ├── rtl │ ├── cci_mux.sv │ ├── ccip_std_afu.sv │ ├── ccip_std_afu_wrapper.sv │ ├── grayscale.sv │ ├── grayscale_csr.sv │ ├── grayscale_fifo.sv │ ├── grayscale_pkg.sv │ └── grayscale_requestor.sv ├── sources.txt └── test │ ├── ccip_std_afu.h │ ├── ccip_test_pkt.cpp │ ├── ccip_test_pkt.h │ ├── config-1.txt │ ├── config-2.txt │ └── main.cpp ├── d4-buffer-overflow-frame-fifo ├── .gitignore ├── .gtkwaverc ├── Makefile ├── Makefile.lc ├── README.md ├── n7.instrument.cfg ├── rtl │ ├── axis_fifo.v │ └── axis_fifo_wrapper.sv ├── sources-sim.txt ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp ├── d5-bit-truncation-sha512 ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bug2.instrument.cfg ├── ccip │ ├── device_if │ │ ├── avalon_mem_if.vh │ │ ├── avalon_mem_if_dbg.vh │ │ ├── ccip_if_clock.sv │ │ ├── ccip_if_pkg.sv │ │ └── device_if.vh │ ├── platform_afu_top_config.vh │ ├── platform_if.vh │ └── platform_shims │ │ ├── README.md │ │ ├── platform_shim_avalon_mem_if.sv │ │ ├── platform_shim_ccip.sv │ │ ├── platform_shim_ccip_std_afu.sv │ │ └── utils │ │ ├── avalon_mem_if_async_shim.sv │ │ ├── avalon_mem_if_connect.sv │ │ ├── avalon_mem_if_reg.sv │ │ ├── platform_utils_ccip_activity_cnt.sv │ │ ├── platform_utils_ccip_async_shim.sv │ │ ├── platform_utils_ccip_reg.sv │ │ └── quartus_ip │ │ ├── README │ │ ├── gen_platform_ip.sh │ │ ├── platform_utils_avalon_dc_fifo.sdc │ │ ├── platform_utils_avalon_dc_fifo.v │ │ ├── platform_utils_avalon_mm_bridge.v │ │ ├── platform_utils_avalon_mm_clock_crossing_bridge.v │ │ ├── platform_utils_dc_fifo.sdc │ │ ├── platform_utils_dc_fifo.sv │ │ ├── platform_utils_dcfifo_synchronizer_bundle.v │ │ └── platform_utils_std_synchronizer_nocut.v ├── rtl │ ├── ccip_std_afu.sv │ ├── ccip_std_afu_wrapper.sv │ ├── sha512.sv │ ├── sha512_core.v │ ├── sha512_csr.sv │ ├── sha512_h_constants.v │ ├── sha512_k_constants.v │ ├── sha512_pkg.sv │ ├── sha512_requestor.sv │ └── sha512_w_mem.v ├── sources.txt └── test │ ├── ccip_std_afu.h │ ├── ccip_test_pkt.cpp │ ├── ccip_test_pkt.h │ ├── config.txt │ └── main.cpp ├── d6-bit-truncation-fft ├── .gitignore ├── .gtkwaverc ├── Makefile ├── bug12.instrument.cfg ├── cores │ ├── bimpy.v │ ├── bitreverse.v │ ├── butterfly.v │ ├── convround.v │ ├── fftmain.v │ ├── fftstage.v │ ├── hwbfly.v │ ├── laststage.v │ ├── longbimpy.v │ ├── qtrstage.v │ └── shiftaddmpy.v ├── hex │ ├── cmem_128.hex │ ├── cmem_16.hex │ ├── cmem_32.hex │ ├── cmem_64.hex │ └── cmem_8.hex ├── instrument.cfg ├── readme.md ├── source.txt ├── test │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── data_in.raw │ ├── expected.iq │ ├── fft_tb.cpp │ ├── fftsize.h │ ├── shit.txt │ ├── twoc.cpp │ ├── twoc.h │ └── vversion.sh └── vivado_synth │ └── fft_wrapper.v ├── d7-misindexing-fadd ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bug11.instrument.cfg ├── rtl │ ├── fadd.sv │ ├── fadd_buggy.sv │ └── fadd_correct.sv ├── sources-sim.txt ├── sources-veripass.txt ├── sources.txt ├── test │ └── main.cpp └── vivado_synth │ └── fadd_wrapper.v ├── d8-misindexing-axis-switch ├── .gitignore ├── Makefile ├── README.md ├── instrument.txt ├── n4.instrument.cfg ├── rtl │ ├── arbiter.v │ ├── axis_register.v │ ├── axis_switch.v │ ├── axis_switch_4x1.v │ ├── priority_encoder.v │ └── test_axis_switch_4x1.v ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp ├── d9-endianness-mismatch-sdspi ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bench │ └── cpp │ │ ├── .gitignore │ │ ├── .gtkwaverc │ │ ├── autotest_tb.cpp │ │ ├── sdspisim.cpp │ │ ├── sdspisim.h │ │ ├── testb.h │ │ └── wb_tb.h ├── bug10.instrument.cfg ├── rtl │ ├── llsdspi.v │ └── sdspi.v ├── sources.txt └── vivado_synth │ └── sdspi_wrapper.v ├── manual_debug_log └── used_tools.xlsx ├── s1-protocol-violation-axi-lite ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bug6.instrument.cfg ├── rtl │ ├── bugfix.patch │ ├── faxil_slave.v │ ├── trace_tb0.v │ ├── trace_tb1.v │ ├── xlnxdemo.sby │ └── xlnxdemo.v ├── sources.txt ├── sources0.txt ├── sources1.txt ├── test │ └── main.cpp └── vivado_synth │ └── xlnxdemo_wrapper.v ├── s2-protocol-violation-axi-stream ├── .gitignore ├── .gtkwaverc ├── Makefile ├── README.md ├── bug7.instrument.cfg ├── rtl │ ├── bugfix.patch │ ├── faxis_master.v │ ├── trace_tb.v │ ├── xlnxstream_2018_3.sby │ └── xlnxstream_2018_3.v ├── sources.txt ├── sources0.txt ├── test │ └── main.cpp └── vivado_synth │ └── xlnxstream_2018_3_wrapper.v ├── s3-incomplete-implementation-axis-adapter ├── .gitignore ├── Makefile ├── README.md ├── instrument.txt ├── n8.instrument.cfg ├── rtl │ ├── axis_adapter.v │ ├── axis_adapter_correct.v │ └── test_axis_adapter_64_8.v ├── sources-veripass.txt ├── sources.txt └── test │ └── main.cpp └── scripts ├── report_sweep.py ├── signaltap_util ├── README.txt ├── report_util.py ├── sweep.sh └── utils.py └── xilinxila_util ├── report_util.py ├── sweep.sh └── utils.py /.gitignore: -------------------------------------------------------------------------------- 1 | *notask* 2 | *withtask* 3 | bug?_step*.v 4 | build* 5 | *sweep*.v 6 | *sweep*.tcl 7 | __pycache__ 8 | *.swp 9 | *displayinfo* 10 | *widthinfo* 11 | .Xil 12 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Reproducible Hardware Bugs 2 | 3 | This is part of the artifact of our paper "Debugging in the Brave New World of Reconfigurable Hardware". Please refer [here](https://github.com/efeslab/asplos22-hardware-debugging-artifact) for the full artifact, setup tutorials, and licenses. 4 | 5 | This repository only include 20 reproducible bugs. For the full list of 68 bugs we studied in our paper, please refer [here](https://docs.google.com/spreadsheets/d/1GonADjkm878iRs2noQFXW5AidY4KiiJfTPJyIq-3Z4I/edit?usp=sharing). 6 | 7 | If you find our work interesting, please cite our paper. 8 | 9 | ``` 10 | @inproceedings{ma2022debugging, 11 | title={Debugging in the Brave New World of Reconfigurable Hardware}, 12 | author={Ma, Jiacheng and Zuo, Gefei and Loughlin, Kevin and Zhang, Haoyang and Quinn, Andrew and Kasikci, Baris}, 13 | booktitle={Proceedings of the Twenty-Seventh International Conference on Architectural Support for Programming Languages and Operating Systems}, 14 | year={2022} 15 | } 16 | ``` 17 | -------------------------------------------------------------------------------- /c1-dead-lock-sdspi/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *.img 6 | sdspi_tb 7 | bug9.v 8 | -------------------------------------------------------------------------------- /c1-dead-lock-sdspi/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /c1-dead-lock-sdspi/bench/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | *.vcd 2 | sdcard.img 3 | -------------------------------------------------------------------------------- /c1-dead-lock-sdspi/bench/cpp/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /c1-dead-lock-sdspi/bug9.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug9: SDSPI-deadlock 2 | # bug9_step1 3 | # deps(o_sck, 1) 4 | deps \ 5 | --control --data \ 6 | --variable "o_sck:0:0" \ 7 | --layer 1 \ 8 | --tag debug_display_9.1 9 | 10 | # deps(o_sck, 2) 11 | # bug9_step2 12 | deps \ 13 | --control --data \ 14 | --variable "o_sck:0:0" \ 15 | --layer 2 \ 16 | --tag debug_display_9.2 17 | output -o bug9.v 18 | sv2v \ 19 | --tasksupport --tasksupport-mode=ILA \ 20 | --tasksupport-tags debug_display_9.1 \ 21 | --tasksupport-tags debug_display_9.2 \ 22 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 23 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 24 | --arrayboundcheck 25 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 26 | -------------------------------------------------------------------------------- /c1-dead-lock-sdspi/sources.txt: -------------------------------------------------------------------------------- 1 | rtl/llsdspi.v 2 | rtl/sdspi.v 3 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | grayscale_mux4_test 6 | filter.txt 7 | optimus.losscheck.0.v 8 | optimus.losscheck.1.v 9 | optimus_grayscale_mux4_test 10 | optimus_grayscale_mux4_test_losscheck 11 | sources.losscheck-opae.0.txt 12 | sources.losscheck-opae.1.txt 13 | sources.losscheck.0.txt 14 | sources.losscheck.1.txt 15 | work_losscheck_1/ 16 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/ccip/platform_shims/README.md: -------------------------------------------------------------------------------- 1 | # Platform Shims 2 | 3 | Shims here are invoked by the top-level code that manages the partial reconfiguration 4 | boundary. Instead of directly instantiating an AFU (e.g. ccip_std_afu), these 5 | intermediate shims will be mapped first. The shims transform the interface and then 6 | connect to the AFU. **These shims and sub-directories are internal to the platform 7 | interface manager. Their interfaces or semantics may change from release to release.** 8 | 9 | Shims names are defined in the JSON field *platform-shim-module-name* in 10 | AFU top-level interface descriptions: [afu\_top\_ifc\_db](../../../afu_top_ifc_db/). 11 | 12 | Shims typically offer automatic clock crossing and automatic platform-specific 13 | register stage insertion to aid in timing closure. See the various instances of 14 | *clock* and *add-timing-reg-stages* in 15 | [platform\_defaults.json](../../../platform_db/platform_defaults.json). 16 | 17 | Some modules here are sub-shims, instantiated by larger shims. For example, 18 | platform\_shim\_ccip() manages only CCI-P clock crossing and register stage insertion. 19 | It is instantiated by platform\_shim\_ccip\_std\_afu(). 20 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/ccip/platform_shims/utils/quartus_ip/README: -------------------------------------------------------------------------------- 1 | This library is extracted from code in Quartus releases using gen_platform_ip.sh 2 | in this directory. Point the script at a Quartus release and it will do the rest. 3 | The module names are modified to make them unique, replacing the leading "altera" 4 | with "platform_utils". 5 | 6 | The SDC files are here instead of in a par directory to keep all the Qsys 7 | code together. 8 | 9 | Extracted components include: 10 | * Qsys Avalon-MM Clock Crossing Bridge 11 | * Qsys Avalon-MM Pipeline Bridge 12 | 13 | 14 | Note: copyrights should be changed to BSD/MIT licenses. 15 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/ccip/platform_shims/utils/quartus_ip/platform_utils_dcfifo_synchronizer_bundle.v: -------------------------------------------------------------------------------- 1 | // $File: //acds/rel/18.0/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $ 2 | // $Revision: #1 $ 3 | // $Date: 2018/02/08 $ 4 | // $Author: psgswbuild $ 5 | //------------------------------------------------------------------------------- 6 | 7 | `timescale 1 ns / 1 ns 8 | module platform_utils_dcfifo_synchronizer_bundle( 9 | clk, 10 | reset_n, 11 | din, 12 | dout 13 | ); 14 | parameter WIDTH = 1; 15 | parameter DEPTH = 3; 16 | 17 | input clk; 18 | input reset_n; 19 | input [WIDTH-1:0] din; 20 | output [WIDTH-1:0] dout; 21 | 22 | genvar i; 23 | 24 | generate 25 | for (i=0; i 11 | 12 | typedef enum 13 | { 14 | eFTYP_AFU = 1, 15 | eFTYP_BBB = 2, 16 | eFTYP_PVT = 3 17 | } 18 | CCIP_FEATURE_TYPE; 19 | 20 | 21 | // 22 | // Decode a device feature header (all except AFU headers) 23 | // 24 | class CCIP_FEATURE_DFH 25 | { 26 | private: 27 | // Encoded feature header 28 | bt64bitCSR dfh; 29 | 30 | public: 31 | CCIP_FEATURE_DFH(bt64bitCSR h) 32 | { 33 | dfh = h; 34 | } 35 | 36 | ~CCIP_FEATURE_DFH() {}; 37 | 38 | CCIP_FEATURE_TYPE getFeatureType() 39 | { 40 | return CCIP_FEATURE_TYPE((dfh >> 60) & 0xf); 41 | } 42 | 43 | uint32_t getVersion() 44 | { 45 | return (dfh >> 12) & 0xf; 46 | } 47 | 48 | uint32_t getID() 49 | { 50 | return dfh & 0xfff; 51 | } 52 | 53 | uint32_t getNext() 54 | { 55 | return (dfh >> 16) & 0xffffff; 56 | } 57 | 58 | bool isEOL() 59 | { 60 | return ((dfh >> 40) & 1) == 1; 61 | } 62 | }; 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-prims/README: -------------------------------------------------------------------------------- 1 | Primitives used by MPF (Memory Properties Factory) 2 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim.vh: -------------------------------------------------------------------------------- 1 | // 2 | // Wrapper for MPF shim structures and functions. 3 | // 4 | 5 | `ifndef CCI_MPF_SHIM_VH 6 | `define CCI_MPF_SHIM_VH 7 | 8 | import cci_mpf_shim_pkg::*; 9 | 10 | `endif 11 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_edge/README: -------------------------------------------------------------------------------- 1 | Edge shims are the final components of the primary MPF pipeline at 2 | both the AFU and FIU ends. The edge provides a number of functions: 3 | 4 | - Write data coming from the AFU is written to block RAM and dropped from 5 | channel 1 TX messages sent through MPF. The data is restored from the block 6 | RAM on exit in the FIU edge block. This greatly reduces the logic 7 | required for buffering data in the MPF pipeline. 8 | 9 | - Multi-line writes are reduced to a single control message by the AFU 10 | edge, allowing MPF to treat even multi-beat writes as a single flit. 11 | All flits are restored from the single control flit by MPF's FIU edge. 12 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_vtp/README: -------------------------------------------------------------------------------- 1 | The virtual to physical (VTP) shim. 2 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/hw/rtl/cci_mpf_sources.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Import MPF into an RTL project for either simulation or synthesis by including this 3 | # configuration file in a source list. Source lists are parsed by OPAE's rtl_src_config, 4 | # which is invoked by both afu_sim_setup and afu_synth_setup. 5 | # 6 | 7 | SI:../sim/cci_mpf_sim_addenda.txt 8 | QI:../par/qsf_cci_mpf_PAR_files.qsf 9 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/samples/afu/cci_mpf_library_import.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## MPF Quartus import -- 3 | ## 4 | ## Change the configuration parameters below and use this file as 5 | ## a template for importing the MPF library using: 6 | ## 7 | ## source cci_mpf_library_import.qsf 8 | ## 9 | 10 | 11 | ## Define the target platform. The list of platforms is in 12 | ## hw/rtl/cci-mpf-if/cci_mpf_platform.vh. 13 | ## 14 | set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_BDX=1" 15 | 16 | 17 | ## Define the path to the MPF sources 18 | ## 19 | set CCI_MPF_SRC "../samples/cci-mpf" 20 | 21 | 22 | ## Import sources 23 | ## 24 | source $CCI_MPF_SRC/hw/par/qsf_cci_mpf_PAR_files.qsf 25 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/scripts/iterate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | RUNCOUNT=0 4 | ERRCOUNT=0 5 | RUNLIMIT=$1 6 | 7 | TEST='rm -rf ../build && ./test-helloalivtpnlb-ase.sh' 8 | 9 | if [ -z "$1" ]; then 10 | echo "USAGE: $0 " 11 | exit -1 12 | fi 13 | 14 | while [ $RUNCOUNT -lt $RUNLIMIT ]; do 15 | echo -n "---- Test run $RUNCOUNT/$RUNLIMIT ----> " 16 | # $TEST 17 | rm -rf ../build && ./test-helloalivtpnlb-ase.sh &> iteration.${RUNCOUNT}.log 18 | if [ $? -eq 0 ]; then 19 | echo "success." 20 | else 21 | echo "failure." 22 | echo "Killing simulation." 23 | sleep 2 24 | killall ase_simv 25 | ERRCOUNT=$(( $ERRCOUNT + 1 )) 26 | fi 27 | RUNCOUNT=$(( $RUNCOUNT + 1 )) 28 | done 29 | 30 | echo "====================================================================" 31 | echo "Summary: $ERRCOUNT of $RUNCOUNT tests failed." 32 | 33 | exit $ERRCOUNT 34 | 35 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | build* 2 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/sw/README: -------------------------------------------------------------------------------- 1 | This tree holds MPF software libraries for controlling MPF shims on FPGAs. 2 | 3 | The library build is configured by CMake. Starting in the directory 4 | holding this README: 5 | 6 | mkdir build 7 | cd build 8 | cmake ../ 9 | make 10 | make install 11 | 12 | The build directory may be anywhere -- just adjust the path of this sw 13 | source directory passed to CMake. 14 | 15 | To select an installation directory other than CMake's default, set 16 | -DCMAKE_INSTALL_PREFIX= on the CMake command line. The MPF library 17 | and header file installation paths are layed out so they may be embedded 18 | in the standard Intel-provided FPGA library and header file trees. 19 | 20 | Set -DCMAKE_BUILD_TYPE=Debug on the CMake command line to emit symbols and 21 | eliminate optimization. 22 | 23 | Warning: the CMake "Release" build type causes errors and is not currently 24 | supported. 25 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/base/hw/par/cci_mpf_test_base_PAR_files.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Common configuration for synthesizing MPF tests. 3 | ## 4 | 5 | ## Find the root of the BBB source tree (6 levels up the directory tree) 6 | set this_script [dict get [ info frame 0 ] file] 7 | set BBB_CCI_SRC [file join {*}[lrange [file split $this_script] 0 end-7]] 8 | 9 | ## MPF and async FIFO libraries 10 | source $BBB_CCI_SRC/BBB_cci_mpf/hw/par/qsf_cci_mpf_PAR_files.qsf 11 | source $BBB_CCI_SRC/BBB_ccip_async/hw/par/ccip_async_addenda.qsf 12 | 13 | ## Base test sources 14 | set_global_assignment -name SEARCH_PATH $CCI_MPF_SRC/test/test-mpf/base/hw/rtl 15 | 16 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_afu.sv 17 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_csrs.sv 18 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/base/hw/rtl/sys_cfg_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef SYS_CFG_PKG_SV 2 | `define SYS_CFG_PKG_SV 3 | // `define CCIP_DEBUG // Add ccip_debug_module 4 | `define VENDOR_ALTERA // Use Altera FPGA 5 | `define TOOL_QUARTUS // Use Altera Quartus Tools 6 | `endif 7 | 8 | 9 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/base/hw/sim/cci_mpf_test_base_addenda.txt: -------------------------------------------------------------------------------- 1 | ## 2 | ## Base include file for describing MPF tests. 3 | ## 4 | 5 | # Include MPF 6 | -F ../../../../../hw/sim/cci_mpf_sim_addenda.txt 7 | 8 | # Include async FIFO 9 | -F ../../../../../../BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt 10 | 11 | +incdir+../rtl 12 | 13 | ../rtl/cci_test_afu.sv 14 | ../rtl/cci_test_csrs.sv 15 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/base/sw/base_include.mk: -------------------------------------------------------------------------------- 1 | ## 2 | ## Define base source files 3 | ## 4 | 5 | BASE_FILE_PATH = ../../base/sw 6 | BASE_FILE_SRC = cci_test_main.cpp opae_svc_wrapper.cpp 7 | BASE_FILE_INC = $(BASE_FILE_PATH)/opae_svc_wrapper.h 8 | 9 | VPATH = .:$(BASE_FILE_PATH) 10 | 11 | CPPFLAGS ?= -std=c++11 12 | CXX ?= g++ 13 | LDFLAGS ?= 14 | 15 | ifeq (,$(CFLAGS)) 16 | CFLAGS = -g -O2 17 | endif 18 | 19 | ifneq (,$(ndebug)) 20 | else 21 | CPPFLAGS += -DENABLE_DEBUG=1 22 | endif 23 | ifneq (,$(nassert)) 24 | else 25 | CPPFLAGS += -DENABLE_ASSERT=1 26 | endif 27 | 28 | ifeq (,$(DESTDIR)) 29 | ifneq (,$(prefix)) 30 | CPPFLAGS += -I$(prefix)/include 31 | LDFLAGS += -L$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(prefix)/lib \ 32 | -L$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(prefix)/lib64 33 | endif 34 | else 35 | ifeq (,$(prefix)) 36 | prefix = /usr/local 37 | endif 38 | CPPFLAGS += -I$(DESTDIR)$(prefix)/include 39 | LDFLAGS += -L$(DESTDIR)$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib \ 40 | -L$(DESTDIR)$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib64 41 | endif 42 | 43 | CPPFLAGS += -I../../base/sw 44 | LDFLAGS += -lboost_program_options -luuid -lMPF-cxx -lMPF -lopae-cxx-core 45 | 46 | FPGA_LIBS = -lopae-c -ljson-c 47 | ASE_LIBS = -lopae-c-ase 48 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/README: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null is a CCI-P test. The AFU uses MPF SystemVerilog interfaces 2 | but the actual MPF shim collection is never instantiated. 3 | 4 | The test allocates a collection of 2MB buffers. The write process streams through 5 | a buffer once, writing a known value to each line. The known value changes with 6 | each pass through a buffer. When a buffer is completely written the write 7 | process moves on to the next buffer. 8 | 9 | The read process follows the write process, streaming continuously through a 10 | single buffer that is not currently being written. The read process shifts 11 | buffers at the same time that the write process shifts. Each read response 12 | value is checked against the expected response. When a mismatch is detected 13 | the location and expected value are forwarded to the CPU. The CPU then 14 | checks the actual value in memory and determines whether the value in memory 15 | is correct. The error is then categorized as either write or read failure. 16 | 17 | The CPU is involved only to categorize errors and to control the length 18 | and number of testing passes. All other data comparison is done on the FPGA. 19 | 20 | There are options for 1, 2, 4 or variable size requests (--mcl) and the test 21 | can target either VA, one channel or some channel patterns (--rd-vc / 22 | --wr-vc). The channel used for signaling errors can also be configured 23 | (--dsm-vc). 24 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null.json 2 | 3 | # For now we force MPF to a particular platform. This will be fixed later. 4 | +define+MPF_PLATFORM_BDX 5 | 6 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 7 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 8 | 9 | +incdir+. 10 | test_cci_mpf_null.sv 11 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/test_cci_mpf_null.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_cci_mpf_null", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "bfd75b03-9608-4e82-ae22-f61a62b8f992" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null 2 | test_cci_mpf_null_ase 3 | obj 4 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_cci_mpf_null 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_cci_mpf_null.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/README: -------------------------------------------------------------------------------- 1 | test_mem_perf RTL is the basis for several tests. On the HW side it is a 2 | simple engine that generates sequential read and/or write traffic of varying 3 | buffer sizes, run lengths and offered loads. Software tests can configure 4 | the hardware for a variety of studies. 5 | 6 | sw/test_mem_latency computes a variety of latency vs. bandwidth data points. 7 | Scripts for generating and plotting results are stored in sw/scripts. 8 | The checked-in configuration assumes that test_mem_perf is built in two 9 | configurations: one with and one without MPF's ROB (the MPF SORT_READ_RESPONSES 10 | configuration option). It is run in the sw directory by: 11 | 12 | < load the version with SORT_READ_RESPONSES enabled > 13 | ./scripts/run_lat.sh ord 14 | < load the default version (SORT_READ_RESPONSES disabled) > 15 | ./scripts/run_lat.sh 16 | ./scripts/plot_lat.sh 17 | 18 | A graph will be stored in bw-lat.pdf. 19 | 20 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_mem_perf.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_mem_perf.sv 8 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/test_mem_perf.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_mem_perf", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "6da50a7d-c76f-42b1-9018-ec1aa7629471" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | compute_vc_map_params 2 | compute_latency_qos_params 3 | test_mem_latency 4 | test_mem_perf 5 | *_ase 6 | obj 7 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_lat.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | ## 4 | ## Run latency tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_latency --vcmap-enable=0 --mcl=${mcl} --vc=${vc} | tee stats/lat_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_latency --vcmap-enable=1 --mcl=${mcl} --vc=0 | tee stats/lat_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_perf.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Run bandwidth tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_perf --vcmap-enable=0 --mcl=${mcl} --vc=${vc} --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_perf --vcmap-enable=1 --mcl=${mcl} --vc=0 --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_random.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_random.sv 8 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/test_random.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_random", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "5037b187-e561-4ca2-ad5b-d6c7816273c2" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_random 2 | test_random_ase 3 | obj 4 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_random 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_random.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_vai_mux_nested/hw/sim/cci_mux_sim_addenda.txt: -------------------------------------------------------------------------------- 1 | +define+CCI_SIMULATION 2 | 3 | +incdir+../rtl 4 | 5 | ../rtl/ccip_mux_legacy.sv 6 | ../rtl/fair_arbiter.sv 7 | ../rtl/ccip_front_end.sv 8 | ../rtl/ccip_intf_regs.sv 9 | ../rtl/sync_C1Tx_fifo.v 10 | ../rtl/gram_sdp.v 11 | ../rtl/a10_ram_sdp_wysiwyg.v 12 | ../rtl/vai_audit_tx.sv 13 | ../rtl/vai_mux.sv 14 | ../rtl/vai_audit_rx.sv 15 | ../rtl/vai_mgr_afu.sv 16 | ../rtl/ccip_legacy_mux_nested.sv 17 | ../rtl/vai_audit_rx2.sv 18 | ../rtl/vai_mgr.sv 19 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/lib/BBB_vai_mux_nested/hw/sim/mux_simfiles.list: -------------------------------------------------------------------------------- 1 | ../rtl/ccip_mux.sv 2 | ../rtl/fair_arbiter.sv 3 | ../rtl/ccip_front_end.sv 4 | ../rtl/ccip_intf_regs.sv 5 | ../rtl/sync_C1Tx_fifo.v 6 | ../rtl/gram_sdp.v 7 | ../rtl/a10_ram_sdp_wysiwyg.v 8 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/origin_test/Makefile: -------------------------------------------------------------------------------- 1 | CXX = g++ 2 | ARGS = -O2 -g 3 | LIBS = -L../../common/libvai/lib -I../../common/libvai/include -lhardcloud -lMPF_VAI -lvai-c-ase -lpng 4 | TARGET = grayscale 5 | SRCS = main.cpp image.cpp 6 | SRCS_FILES = $(foreach F, $(SRCS), $(F)) 7 | 8 | all: 9 | $(CXX) $(ARGS) $(SRCS_FILES) $(LIBS) -o $(TARGET) 10 | 11 | clean: 12 | rm -rf $(TARGET) 13 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/origin_test/image.h: -------------------------------------------------------------------------------- 1 | //===----- image.h - load image files -------------------------------------===// 2 | // 3 | // Copyright (c) 2017 Ciro Ceissler 4 | // 5 | // See LICENSE for details. 6 | // 7 | //===----------------------------------------------------------------------===// 8 | // 9 | // Class to load image file, only supports png format. 10 | // 11 | //===----------------------------------------------------------------------===// 12 | 13 | #ifndef IMAGE_H_ 14 | #define IMAGE_H_ 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | class Image { 21 | private: 22 | png_byte color_type; 23 | png_byte bit_depth; 24 | 25 | void map_to_array(); 26 | 27 | public: 28 | Image() {} 29 | 30 | explicit Image(const std::string& filename) { 31 | std::cout << "[image] loading file: " << filename << std::endl; 32 | 33 | this->read_png_file(filename); 34 | } 35 | 36 | unsigned int* array_in; 37 | unsigned int* array_out; 38 | 39 | void map_back(); 40 | 41 | ~Image() {} 42 | 43 | int width; 44 | int height; 45 | png_bytep *row_pointers; 46 | 47 | void read_png_file(const std::string& filename); 48 | void write_png_file(const std::string& filename); 49 | void compare(const std::string& filename); 50 | }; 51 | 52 | #endif // IMAGE_H_ 53 | 54 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/origin_test/input.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/c2-producer-consumer-mismatch-optimus/origin_test/input.png -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/origin_test/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | #include "image.h" 7 | 8 | int main(int argc, char *argv[]) 9 | { 10 | std::string file_input("input.png"); 11 | std::string file_output("output.png"); 12 | 13 | Image image(file_input); 14 | 15 | unsigned int size = image.height*image.width; 16 | unsigned int height = image.height; 17 | unsigned int width = image.width; 18 | 19 | unsigned int* image_in = image.array_in; 20 | unsigned int* image_out = image.array_out; 21 | 22 | HardcloudApp app(true); 23 | 24 | unsigned int *out_buf = (unsigned int*)app.alloc_buffer(size*sizeof(unsigned int)); 25 | unsigned int *in_buf = (unsigned int*)app.alloc_buffer(size*sizeof(unsigned int)); 26 | 27 | memcpy(in_buf, image_in, size*sizeof(unsigned int)); 28 | 29 | printf("allocation done\n"); 30 | 31 | struct timespec ts1, ts2; 32 | timespec_get(&ts1, TIME_UTC); 33 | app.run(); 34 | timespec_get(&ts2, TIME_UTC); 35 | 36 | double t = (ts2.tv_sec*1000000 + ts2.tv_nsec/1000) - (ts1.tv_sec*1000000 + ts1.tv_nsec/1000); 37 | 38 | printf("time: %lf ms\n", t/1000); 39 | printf("throughput: %lf fig/s\n", 1.0/(t/1000000)); 40 | 41 | memcpy(image_out, out_buf, size*sizeof(unsigned int)); 42 | 43 | image.map_back(); 44 | 45 | image.write_png_file(file_output); 46 | app.delete_buffer(in_buf); 47 | app.delete_buffer(out_buf); 48 | 49 | return 0; 50 | } 51 | 52 | -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/origin_test/output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/c2-producer-consumer-mismatch-optimus/origin_test/output.png -------------------------------------------------------------------------------- /c2-producer-consumer-mismatch-optimus/rtl/grayscale.sv: -------------------------------------------------------------------------------- 1 | // grayscale.sv 2 | 3 | module grayscale 4 | ( 5 | input logic clk, 6 | input logic reset, 7 | input logic [511:0] data_in, 8 | input logic valid_in, 9 | output logic [511:0] data_out, 10 | output logic valid_out 11 | ); 12 | 13 | function [31:0] rgb2luma(input logic [31:0] data); 14 | logic [7:0] tmp; 15 | 16 | tmp = data[7:0] >> 2; 17 | tmp += data[7:0] >> 5; 18 | tmp += data[15:8] >> 1; 19 | tmp += data[15:8] >> 4; 20 | tmp += data[23:16] >> 4; 21 | tmp += data[23:16] >> 5; 22 | 23 | return {tmp, tmp, tmp}; 24 | endfunction : rgb2luma 25 | 26 | always_ff@(posedge clk or posedge reset) begin 27 | if (reset) begin 28 | valid_out <= 1'b0; 29 | end 30 | else begin 31 | valid_out <= valid_in; 32 | end 33 | end 34 | 35 | always_ff@(posedge clk or posedge reset) begin 36 | if (reset) begin 37 | data_out <= '0; 38 | end 39 | else begin 40 | for (int i = 0; i < 16; i++) begin 41 | data_out[32*i +: 32] <= rgb2luma(data_in[32*i +: 32]); 42 | end 43 | end 44 | end 45 | 46 | endmodule : grayscale 47 | 48 | -------------------------------------------------------------------------------- /c3-signal-asynchrony-sdspi/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *.img 6 | sdspi_tb 7 | -------------------------------------------------------------------------------- /c3-signal-asynchrony-sdspi/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /c3-signal-asynchrony-sdspi/bench/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | *.vcd 2 | sdcard.img 3 | -------------------------------------------------------------------------------- /c3-signal-asynchrony-sdspi/bench/cpp/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /c3-signal-asynchrony-sdspi/bug8.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug8: SDSPI-path-merging 2 | # printf(all control inputs) 3 | deps \ 4 | --variable "o_wb_data:31:0" \ 5 | --variable "o_wb_ack:0:0" \ 6 | --variable "fifo_a_reg:31:0" \ 7 | --variable "fifo_wb_addr:6:0" \ 8 | --layer 0 \ 9 | --tag debug_display_8 10 | output -o bug8.v 11 | sv2v \ 12 | --tasksupport --tasksupport-mode=ILA \ 13 | --tasksupport-tags debug_display_8 \ 14 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 15 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 16 | --arrayboundcheck 17 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 18 | -------------------------------------------------------------------------------- /c3-signal-asynchrony-sdspi/sources.txt: -------------------------------------------------------------------------------- 1 | rtl/llsdspi.v 2 | rtl/sdspi.v 3 | -------------------------------------------------------------------------------- /c4-signal-asynchrony-axi-stream-fifo/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *.lxt 6 | test_axis_async_fifo 7 | -------------------------------------------------------------------------------- /c4-signal-asynchrony-axi-stream-fifo/README.md: -------------------------------------------------------------------------------- 1 | # C4 - Signal Asynchrony - AXI Stream FIFO 2 | 3 | **Source:** Verilog-axis(Verilog AXI Stream Components): https://github.com/alexforencich/verilog-axis/commit/382226ad5966198862fb676c7a5810067c2c6a19 4 | 5 | Bug type: Reset-Data Asynchrony 6 | 7 | 8 | Data should not be accepted when reseting (input_tready should not be 1 when reseting) 9 | 10 | ### Synthetic Code 11 | ```verilog 12 | 13 | // reset synchronization 14 | always @(posedge input_clk or posedge async_rst) begin 15 | if (async_rst) begin 16 | input_rst_sync1 <= 1; 17 | input_rst_sync2 <= 1; 18 | input_rst_sync3 <= 1; 19 | end else begin 20 | input_rst_sync1 <= 0; 21 | input_rst_sync2 <= input_rst_sync1 | output_rst_sync1; 22 | input_rst_sync3 <= input_rst_sync2; 23 | end 24 | end 25 | 26 | // write 27 | always @(posedge input_clk) begin 28 | if (input_rst_sync3) begin 29 | wr_ptr <= 0; 30 | wr_ptr_gray <= 0; 31 | end else if (write) begin 32 | mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in; 33 | wr_ptr_next = wr_ptr + 1; 34 | wr_ptr <= wr_ptr_next; 35 | wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1); 36 | end 37 | end 38 | 39 | assign input_axis_tready = ~full; //Buggy here, should be ~full & ~input_rst_sync3; 40 | 41 | ``` 42 | -------------------------------------------------------------------------------- /c4-signal-asynchrony-axi-stream-fifo/instrument.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/test_axis_async_fifo.v 3 | test.v 4 | ../common/xilinx/fakeila.sv 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /c4-signal-asynchrony-axi-stream-fifo/n6.instrument.cfg: -------------------------------------------------------------------------------- 1 | 2 | # bug_step1 3 | # print ready and valid signals 4 | deps \ 5 | --variable "async_rst:0:0" \ 6 | --variable "reg_axis_tvalid:0:0" \ 7 | --variable "reg_axis_tready:0:0" \ 8 | --variable "reg_axis_tlast:0:0" \ 9 | --variable "UUT__DOT__full:0:0" \ 10 | --variable "UUT__DOT__empty:0:0" \ 11 | --variable "UUT__DOT__write:0:0" \ 12 | --variable "UUT__DOT__read:0:0" \ 13 | --layer 0 \ 14 | --control --data \ 15 | --tag debug_display_1 16 | 17 | output -o bug.v 18 | 19 | sv2v \ 20 | --tasksupport --tasksupport-mode=ILA \ 21 | --tasksupport-tags=debug_display_1 \ 22 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 23 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 24 | --arrayboundcheck 25 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 26 | -------------------------------------------------------------------------------- /c4-signal-asynchrony-axi-stream-fifo/sources-veripass.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/axis_async_fifo.v 3 | rtl/axis_fifo_wrapper.v 4 | rtl/axis_register.v 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /c4-signal-asynchrony-axi-stream-fifo/sources.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/axis_async_fifo.v 3 | rtl/test_axis_async_fifo.v 4 | rtl/axis_register.v 5 | rtl/axis_fifo_wrapper.v 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /common/Makefile.STP.rules: -------------------------------------------------------------------------------- 1 | SV2V_OUT_FILES+=notask 2 | SYNTH_FILES_GEN=$(foreach f, ${SV2V_OUT_FILES}, sources.$(f).txt) 3 | SV2V_SYNTH?=$(foreach f, ${SV2V_OUT_FILES}, build_$(f)) 4 | SYNTH_AFU_JSON=../common/cci_afu.json 5 | SYNTH_CCIP_DEWRAPPER=../common/ccip_dewrapper.sv 6 | 7 | sources.%.txt: %.v 8 | echo -e "${SYNTH_AFU_JSON}\n${SYNTH_CCIP_DEWRAPPER}\n$<" > $@ 9 | build_%: sources.%.txt %.v 10 | rm -rf $@ 11 | afu_synth_setup -s $< $@ 12 | cd $@ && run.sh > $@.log 2>&1 13 | 14 | report_util: 15 | @${STP_REPORT_UTIL} ${SV2V_SYNTH} 16 | 17 | report_depth_sweep: 18 | @for p in ${DEPTH_SWEEP_PREFIX}; do \ 19 | echo -e "\n### Depth Sweep of $${p}\n"; \ 20 | ${REPORT_SWEEP} --mode=STP --prefix build_$${p} --pattern-depth;\ 21 | done 22 | @echo 23 | @${STP_REPORT_UTIL} build_notask 24 | 25 | mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) 26 | mkfile_dir := $(dir $(mkfile_path)) 27 | include ${mkfile_dir}/Makefile.rules 28 | -------------------------------------------------------------------------------- /common/Makefile.env: -------------------------------------------------------------------------------- 1 | VERIPASS_PATH?=$(CURDIR)/../../veripass 2 | TOOLS?=${VERIPASS_PATH}/tools.py 3 | TCLGEN?=${VERIPASS_PATH}/vivado_tclgen.py 4 | STP_REPORT_UTIL?=../scripts/signaltap_util/report_util.py 5 | ILA_REPORT_UTIL?=../scripts/xilinxila_util/report_util.py 6 | REPORT_SWEEP?=../scripts/report_sweep.py 7 | DEPTH_SWEEP=10 11 12 13 8 | -------------------------------------------------------------------------------- /common/Makefile.rules: -------------------------------------------------------------------------------- 1 | # Expected variables: 2 | # SV2V_SYNTH: all targets related to synthesis 3 | # CODE_GEN: all automatic generated verilog files 4 | # SYNTH_FILES_GEN: all automatic generated files for synthesis 5 | # DEPTH_SWEEP_PREFIX: a list of prefix, each should be expand to make target "build_${prefix}_d%" 6 | CODE_GEN+=notask.v 7 | CODE_GEN+=$(wildcard ${DEPTH_SWEEP_PREFIX}*.tcl) 8 | notask.v: ${RTL_SOURCES} 9 | ${TOOLS} --top ${TOP_MODULE} -F ${RTL_SOURCES} -o $@ --not-retag-synthesis sv2v 10 | 11 | sv2v: notask.v 12 | 13 | .PHONY: clean_synth synth clean_codegen 14 | clean_synth: clean_codegen 15 | rm -rf ${SV2V_SYNTH} ${SYNTH_FILES_GEN} 16 | clean_codegen: 17 | rm -rf ${CODE_GEN} 18 | synth: ${SV2V_SYNTH} 19 | 20 | .PHONY: verilator_onefile 21 | verilator_onefile: ${VERILATOR_ONEFILE} clean 22 | @if [ -z $< ]; then echo "Please specify env VERILATOR_ONEFILE" && exit 1; fi 23 | $(VERILATOR) $(VERILATOR_OPT) -Wno-PROCASSWIRE -top-module $(TOP_MODULE) --Mdir $(RTL_WORK_DIR) $< 24 | $(MAKE) -C $(RTL_WORK_DIR) -f V$(TOP_MODULE).mk 25 | $(CXX) $(CXX_OPT) $(VERILATOR_CXX_FILES) $(TEST_CXX_FILES) $(TEST_RTL_SIMLIB) -o $(basename $<).exe 26 | 27 | # depth sweep 28 | DEPTH_SWEEP_TARGETS=$(foreach prefix, ${DEPTH_SWEEP_PREFIX}, $(foreach d, ${DEPTH_SWEEP}, build_${prefix}_d${d})) 29 | sweep_depth: ${DEPTH_SWEEP_TARGETS} build_notask 30 | -------------------------------------------------------------------------------- /common/altera/altera_mf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/common/altera/altera_mf.v -------------------------------------------------------------------------------- /common/cci_afu.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "cci_afu", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "c6aa954a-9b91-4a77-abc1-1d9f0709dcc7" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /common/clk250.xdc: -------------------------------------------------------------------------------- 1 | # For axi-lite sdspi-path-merge sdspi-deadlock sdspi-endian fft fadd 2 | create_clock -period 4.000 -name S_AXI_ACLK -waveform {0.000 2.000} [get_nets S_AXI_ACLK] 3 | # For axi-stream 4 | create_clock -period 4.000 -name M_AXIS_ACLK -waveform {0.000 2.000} [get_nets M_AXIS_ACLK] 5 | 6 | # For clk 7 | create_clock -period 4.000 -name clk -waveform {0.000 2.000} [get_nets clk] 8 | -------------------------------------------------------------------------------- /common/libvai/lib/libMPF_VAI.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/common/libvai/lib/libMPF_VAI.so -------------------------------------------------------------------------------- /common/libvai/lib/libhardcloud.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/common/libvai/lib/libhardcloud.so -------------------------------------------------------------------------------- /common/libvai/lib/libvai-c-ase.so: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/common/libvai/lib/libvai-c-ase.so -------------------------------------------------------------------------------- /common/trans.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl -w 2 | 3 | use warnings; 4 | use strict; 5 | 6 | use lib 'blib/lib'; 7 | use Verilog::EditFiles; 8 | use FindBin qw($RealBin $RealScript $Script); 9 | 10 | my $split = Verilog::EditFiles->new 11 | (outdir => ".", 12 | translate_synthesis => 0, 13 | lint_header => undef, 14 | celldefine => 1, 15 | ); 16 | 17 | $split->edit_file( 18 | filename=>@ARGV, 19 | cb=>sub { 20 | my $wholefile = shift; 21 | my $lint = "/*verilator lint_off CASEX*/ 22 | /*verilator lint_off COMBDLY*/ 23 | /*verilator lint_off INITIALDLY*/ 24 | /*verilator lint_off LITENDIAN*/ 25 | /*verilator lint_off MULTIDRIVEN*/ 26 | /*verilator lint_off UNOPTFLAT*/ 27 | /*verilator lint_off BLKANDNBLK*/ 28 | /*verilator lint_off PINMISSING*/ 29 | /*verilator lint_off TIMESCALEMOD*/ 30 | ", 31 | $wholefile =~ s%(\btri[01]\b)(.*)%logic$2 // -- converted tristate to logic%g; 32 | $wholefile =~ s%(buf\s*\(\s*(\w+)\s*,\s*(\w+)\));%assign $2 = $3; // -- converted buf to assign%g; 33 | $wholefile =~ s%1'b[xz]%1'b0 /* converted x or z to 1'b0 */%g; 34 | return $lint.$wholefile; 35 | }); 36 | 37 | -------------------------------------------------------------------------------- /common/xilinx/fakeila.sv: -------------------------------------------------------------------------------- 1 | module ila_0 ( 2 | input logic clk, 3 | input logic [4095:0] probe0, 4 | input logic [4095:0] probe1 5 | ); 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | reed_solomon_decoder_test 6 | rsd.losscheck.0.v 7 | rsd.losscheck.1.v 8 | origin_test/gaussian 9 | sources.losscheck-opae.0.txt 10 | sources.losscheck-opae.1.txt 11 | sources.losscheck.0.txt 12 | sources.losscheck.1.txt 13 | work_losscheck_1/ 14 | filter.txt 15 | reed_solomon_decoder_test_losscheck 16 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/bug3.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug3: RSD-BufferOverflow 2 | # bug3_step1 3 | # fsm_update(rd_state) 4 | # fsm_update(wr_state) 5 | fsm \ 6 | -S ccip_std_afu__DOT__uu_reed_solomon_decoder_requestor__DOT__rd_state:2:0 \ 7 | -S ccip_std_afu__DOT__uu_reed_solomon_decoder_requestor__DOT__wr_state:2:0 \ 8 | --tag debug_display_3.1 9 | # bug3_step2 10 | # count(ccip_rx.c0.rspValid) 11 | # count(valid_out) 12 | # count(valid_in) 13 | # count(ccip_tx.c1.valid) 14 | autocnt \ 15 | --valid-signal ccip_std_afu__DOT__ccip_rx:31 \ 16 | --valid-signal ccip_std_afu__DOT__valid_tx:0 \ 17 | --valid-signal ccip_std_afu__DOT__valid_rx:0 \ 18 | --valid-signal ccip_std_afu__DOT____Vcellout__uu_reed_solomon_decoder_requestor__ccip_c1_tx:0 \ 19 | --tag debug_display_3.2 20 | # bug3_step3 21 | # print(wr_ptr) 22 | deps \ 23 | --variable "ccip_std_afu__DOT__uu_reed_solomon_decoder_requestor__DOT__wr_ptr:5:0" \ 24 | --layer 0 \ 25 | --tag debug_display_3.3 26 | output -o bug3_step3.v 27 | sv2v \ 28 | --tasksupport --tasksupport-mode=STP \ 29 | --tasksupport-tags=debug_display_3.1 \ 30 | --tasksupport-tags=debug_display_3.2 \ 31 | --tasksupport-tags=debug_display_3.3 \ 32 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 33 | --arrayboundcheck 34 | {% if SV2V_OUTPUT is defined %} 35 | output --not-retag-synthesis -o {{SV2V_OUTPUT}} 36 | {% else %} 37 | output --not-retag-synthesis -o withtask.v 38 | {% endif %} 39 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/ccip/platform_shims/README.md: -------------------------------------------------------------------------------- 1 | # Platform Shims 2 | 3 | Shims here are invoked by the top-level code that manages the partial reconfiguration 4 | boundary. Instead of directly instantiating an AFU (e.g. ccip_std_afu), these 5 | intermediate shims will be mapped first. The shims transform the interface and then 6 | connect to the AFU. **These shims and sub-directories are internal to the platform 7 | interface manager. Their interfaces or semantics may change from release to release.** 8 | 9 | Shims names are defined in the JSON field *platform-shim-module-name* in 10 | AFU top-level interface descriptions: [afu\_top\_ifc\_db](../../../afu_top_ifc_db/). 11 | 12 | Shims typically offer automatic clock crossing and automatic platform-specific 13 | register stage insertion to aid in timing closure. See the various instances of 14 | *clock* and *add-timing-reg-stages* in 15 | [platform\_defaults.json](../../../platform_db/platform_defaults.json). 16 | 17 | Some modules here are sub-shims, instantiated by larger shims. For example, 18 | platform\_shim\_ccip() manages only CCI-P clock crossing and register stage insertion. 19 | It is instantiated by platform\_shim\_ccip\_std\_afu(). 20 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/ccip/platform_shims/utils/quartus_ip/README: -------------------------------------------------------------------------------- 1 | This library is extracted from code in Quartus releases using gen_platform_ip.sh 2 | in this directory. Point the script at a Quartus release and it will do the rest. 3 | The module names are modified to make them unique, replacing the leading "altera" 4 | with "platform_utils". 5 | 6 | The SDC files are here instead of in a par directory to keep all the Qsys 7 | code together. 8 | 9 | Extracted components include: 10 | * Qsys Avalon-MM Clock Crossing Bridge 11 | * Qsys Avalon-MM Pipeline Bridge 12 | 13 | 14 | Note: copyrights should be changed to BSD/MIT licenses. 15 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/ccip/platform_shims/utils/quartus_ip/platform_utils_dcfifo_synchronizer_bundle.v: -------------------------------------------------------------------------------- 1 | // $File: //acds/rel/18.0/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $ 2 | // $Revision: #1 $ 3 | // $Date: 2018/02/08 $ 4 | // $Author: psgswbuild $ 5 | //------------------------------------------------------------------------------- 6 | 7 | `timescale 1 ns / 1 ns 8 | module platform_utils_dcfifo_synchronizer_bundle( 9 | clk, 10 | reset_n, 11 | din, 12 | dout 13 | ); 14 | parameter WIDTH = 1; 15 | parameter DEPTH = 3; 16 | 17 | input clk; 18 | input reset_n; 19 | input [WIDTH-1:0] din; 20 | output [WIDTH-1:0] dout; 21 | 22 | genvar i; 23 | 24 | generate 25 | for (i=0; i 11 | 12 | typedef enum 13 | { 14 | eFTYP_AFU = 1, 15 | eFTYP_BBB = 2, 16 | eFTYP_PVT = 3 17 | } 18 | CCIP_FEATURE_TYPE; 19 | 20 | 21 | // 22 | // Decode a device feature header (all except AFU headers) 23 | // 24 | class CCIP_FEATURE_DFH 25 | { 26 | private: 27 | // Encoded feature header 28 | bt64bitCSR dfh; 29 | 30 | public: 31 | CCIP_FEATURE_DFH(bt64bitCSR h) 32 | { 33 | dfh = h; 34 | } 35 | 36 | ~CCIP_FEATURE_DFH() {}; 37 | 38 | CCIP_FEATURE_TYPE getFeatureType() 39 | { 40 | return CCIP_FEATURE_TYPE((dfh >> 60) & 0xf); 41 | } 42 | 43 | uint32_t getVersion() 44 | { 45 | return (dfh >> 12) & 0xf; 46 | } 47 | 48 | uint32_t getID() 49 | { 50 | return dfh & 0xfff; 51 | } 52 | 53 | uint32_t getNext() 54 | { 55 | return (dfh >> 16) & 0xffffff; 56 | } 57 | 58 | bool isEOL() 59 | { 60 | return ((dfh >> 40) & 1) == 1; 61 | } 62 | }; 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/hw/rtl/cci-mpf-prims/README: -------------------------------------------------------------------------------- 1 | Primitives used by MPF (Memory Properties Factory) 2 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim.vh: -------------------------------------------------------------------------------- 1 | // 2 | // Wrapper for MPF shim structures and functions. 3 | // 4 | 5 | `ifndef CCI_MPF_SHIM_VH 6 | `define CCI_MPF_SHIM_VH 7 | 8 | import cci_mpf_shim_pkg::*; 9 | 10 | `endif 11 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_edge/README: -------------------------------------------------------------------------------- 1 | Edge shims are the final components of the primary MPF pipeline at 2 | both the AFU and FIU ends. The edge provides a number of functions: 3 | 4 | - Write data coming from the AFU is written to block RAM and dropped from 5 | channel 1 TX messages sent through MPF. The data is restored from the block 6 | RAM on exit in the FIU edge block. This greatly reduces the logic 7 | required for buffering data in the MPF pipeline. 8 | 9 | - Multi-line writes are reduced to a single control message by the AFU 10 | edge, allowing MPF to treat even multi-beat writes as a single flit. 11 | All flits are restored from the single control flit by MPF's FIU edge. 12 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_vtp/README: -------------------------------------------------------------------------------- 1 | The virtual to physical (VTP) shim. 2 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/hw/rtl/cci_mpf_sources.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Import MPF into an RTL project for either simulation or synthesis by including this 3 | # configuration file in a source list. Source lists are parsed by OPAE's rtl_src_config, 4 | # which is invoked by both afu_sim_setup and afu_synth_setup. 5 | # 6 | 7 | SI:../sim/cci_mpf_sim_addenda.txt 8 | QI:../par/qsf_cci_mpf_PAR_files.qsf 9 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/samples/afu/cci_mpf_library_import.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## MPF Quartus import -- 3 | ## 4 | ## Change the configuration parameters below and use this file as 5 | ## a template for importing the MPF library using: 6 | ## 7 | ## source cci_mpf_library_import.qsf 8 | ## 9 | 10 | 11 | ## Define the target platform. The list of platforms is in 12 | ## hw/rtl/cci-mpf-if/cci_mpf_platform.vh. 13 | ## 14 | set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_BDX=1" 15 | 16 | 17 | ## Define the path to the MPF sources 18 | ## 19 | set CCI_MPF_SRC "../samples/cci-mpf" 20 | 21 | 22 | ## Import sources 23 | ## 24 | source $CCI_MPF_SRC/hw/par/qsf_cci_mpf_PAR_files.qsf 25 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/scripts/iterate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | RUNCOUNT=0 4 | ERRCOUNT=0 5 | RUNLIMIT=$1 6 | 7 | TEST='rm -rf ../build && ./test-helloalivtpnlb-ase.sh' 8 | 9 | if [ -z "$1" ]; then 10 | echo "USAGE: $0 " 11 | exit -1 12 | fi 13 | 14 | while [ $RUNCOUNT -lt $RUNLIMIT ]; do 15 | echo -n "---- Test run $RUNCOUNT/$RUNLIMIT ----> " 16 | # $TEST 17 | rm -rf ../build && ./test-helloalivtpnlb-ase.sh &> iteration.${RUNCOUNT}.log 18 | if [ $? -eq 0 ]; then 19 | echo "success." 20 | else 21 | echo "failure." 22 | echo "Killing simulation." 23 | sleep 2 24 | killall ase_simv 25 | ERRCOUNT=$(( $ERRCOUNT + 1 )) 26 | fi 27 | RUNCOUNT=$(( $RUNCOUNT + 1 )) 28 | done 29 | 30 | echo "====================================================================" 31 | echo "Summary: $ERRCOUNT of $RUNCOUNT tests failed." 32 | 33 | exit $ERRCOUNT 34 | 35 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | build* 2 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/sw/README: -------------------------------------------------------------------------------- 1 | This tree holds MPF software libraries for controlling MPF shims on FPGAs. 2 | 3 | The library build is configured by CMake. Starting in the directory 4 | holding this README: 5 | 6 | mkdir build 7 | cd build 8 | cmake ../ 9 | make 10 | make install 11 | 12 | The build directory may be anywhere -- just adjust the path of this sw 13 | source directory passed to CMake. 14 | 15 | To select an installation directory other than CMake's default, set 16 | -DCMAKE_INSTALL_PREFIX= on the CMake command line. The MPF library 17 | and header file installation paths are layed out so they may be embedded 18 | in the standard Intel-provided FPGA library and header file trees. 19 | 20 | Set -DCMAKE_BUILD_TYPE=Debug on the CMake command line to emit symbols and 21 | eliminate optimization. 22 | 23 | Warning: the CMake "Release" build type causes errors and is not currently 24 | supported. 25 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/base/hw/par/cci_mpf_test_base_PAR_files.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Common configuration for synthesizing MPF tests. 3 | ## 4 | 5 | ## Find the root of the BBB source tree (6 levels up the directory tree) 6 | set this_script [dict get [ info frame 0 ] file] 7 | set BBB_CCI_SRC [file join {*}[lrange [file split $this_script] 0 end-7]] 8 | 9 | ## MPF and async FIFO libraries 10 | source $BBB_CCI_SRC/BBB_cci_mpf/hw/par/qsf_cci_mpf_PAR_files.qsf 11 | source $BBB_CCI_SRC/BBB_ccip_async/hw/par/ccip_async_addenda.qsf 12 | 13 | ## Base test sources 14 | set_global_assignment -name SEARCH_PATH $CCI_MPF_SRC/test/test-mpf/base/hw/rtl 15 | 16 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_afu.sv 17 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_csrs.sv 18 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/base/hw/rtl/sys_cfg_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef SYS_CFG_PKG_SV 2 | `define SYS_CFG_PKG_SV 3 | // `define CCIP_DEBUG // Add ccip_debug_module 4 | `define VENDOR_ALTERA // Use Altera FPGA 5 | `define TOOL_QUARTUS // Use Altera Quartus Tools 6 | `endif 7 | 8 | 9 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/base/hw/sim/cci_mpf_test_base_addenda.txt: -------------------------------------------------------------------------------- 1 | ## 2 | ## Base include file for describing MPF tests. 3 | ## 4 | 5 | # Include MPF 6 | -F ../../../../../hw/sim/cci_mpf_sim_addenda.txt 7 | 8 | # Include async FIFO 9 | -F ../../../../../../BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt 10 | 11 | +incdir+../rtl 12 | 13 | ../rtl/cci_test_afu.sv 14 | ../rtl/cci_test_csrs.sv 15 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/base/sw/base_include.mk: -------------------------------------------------------------------------------- 1 | ## 2 | ## Define base source files 3 | ## 4 | 5 | BASE_FILE_PATH = ../../base/sw 6 | BASE_FILE_SRC = cci_test_main.cpp opae_svc_wrapper.cpp 7 | BASE_FILE_INC = $(BASE_FILE_PATH)/opae_svc_wrapper.h 8 | 9 | VPATH = .:$(BASE_FILE_PATH) 10 | 11 | CPPFLAGS ?= -std=c++11 12 | CXX ?= g++ 13 | LDFLAGS ?= 14 | 15 | ifeq (,$(CFLAGS)) 16 | CFLAGS = -g -O2 17 | endif 18 | 19 | ifneq (,$(ndebug)) 20 | else 21 | CPPFLAGS += -DENABLE_DEBUG=1 22 | endif 23 | ifneq (,$(nassert)) 24 | else 25 | CPPFLAGS += -DENABLE_ASSERT=1 26 | endif 27 | 28 | ifeq (,$(DESTDIR)) 29 | ifneq (,$(prefix)) 30 | CPPFLAGS += -I$(prefix)/include 31 | LDFLAGS += -L$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(prefix)/lib \ 32 | -L$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(prefix)/lib64 33 | endif 34 | else 35 | ifeq (,$(prefix)) 36 | prefix = /usr/local 37 | endif 38 | CPPFLAGS += -I$(DESTDIR)$(prefix)/include 39 | LDFLAGS += -L$(DESTDIR)$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib \ 40 | -L$(DESTDIR)$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib64 41 | endif 42 | 43 | CPPFLAGS += -I../../base/sw 44 | LDFLAGS += -lboost_program_options -luuid -lMPF-cxx -lMPF -lopae-cxx-core 45 | 46 | FPGA_LIBS = -lopae-c -ljson-c 47 | ASE_LIBS = -lopae-c-ase 48 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/README: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null is a CCI-P test. The AFU uses MPF SystemVerilog interfaces 2 | but the actual MPF shim collection is never instantiated. 3 | 4 | The test allocates a collection of 2MB buffers. The write process streams through 5 | a buffer once, writing a known value to each line. The known value changes with 6 | each pass through a buffer. When a buffer is completely written the write 7 | process moves on to the next buffer. 8 | 9 | The read process follows the write process, streaming continuously through a 10 | single buffer that is not currently being written. The read process shifts 11 | buffers at the same time that the write process shifts. Each read response 12 | value is checked against the expected response. When a mismatch is detected 13 | the location and expected value are forwarded to the CPU. The CPU then 14 | checks the actual value in memory and determines whether the value in memory 15 | is correct. The error is then categorized as either write or read failure. 16 | 17 | The CPU is involved only to categorize errors and to control the length 18 | and number of testing passes. All other data comparison is done on the FPGA. 19 | 20 | There are options for 1, 2, 4 or variable size requests (--mcl) and the test 21 | can target either VA, one channel or some channel patterns (--rd-vc / 22 | --wr-vc). The channel used for signaling errors can also be configured 23 | (--dsm-vc). 24 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null.json 2 | 3 | # For now we force MPF to a particular platform. This will be fixed later. 4 | +define+MPF_PLATFORM_BDX 5 | 6 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 7 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 8 | 9 | +incdir+. 10 | test_cci_mpf_null.sv 11 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/test_cci_mpf_null.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_cci_mpf_null", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "bfd75b03-9608-4e82-ae22-f61a62b8f992" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null 2 | test_cci_mpf_null_ase 3 | obj 4 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_cci_mpf_null 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_cci_mpf_null.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/README: -------------------------------------------------------------------------------- 1 | test_mem_perf RTL is the basis for several tests. On the HW side it is a 2 | simple engine that generates sequential read and/or write traffic of varying 3 | buffer sizes, run lengths and offered loads. Software tests can configure 4 | the hardware for a variety of studies. 5 | 6 | sw/test_mem_latency computes a variety of latency vs. bandwidth data points. 7 | Scripts for generating and plotting results are stored in sw/scripts. 8 | The checked-in configuration assumes that test_mem_perf is built in two 9 | configurations: one with and one without MPF's ROB (the MPF SORT_READ_RESPONSES 10 | configuration option). It is run in the sw directory by: 11 | 12 | < load the version with SORT_READ_RESPONSES enabled > 13 | ./scripts/run_lat.sh ord 14 | < load the default version (SORT_READ_RESPONSES disabled) > 15 | ./scripts/run_lat.sh 16 | ./scripts/plot_lat.sh 17 | 18 | A graph will be stored in bw-lat.pdf. 19 | 20 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_mem_perf.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_mem_perf.sv 8 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/test_mem_perf.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_mem_perf", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "6da50a7d-c76f-42b1-9018-ec1aa7629471" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | compute_vc_map_params 2 | compute_latency_qos_params 3 | test_mem_latency 4 | test_mem_perf 5 | *_ase 6 | obj 7 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_lat.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | ## 4 | ## Run latency tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_latency --vcmap-enable=0 --mcl=${mcl} --vc=${vc} | tee stats/lat_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_latency --vcmap-enable=1 --mcl=${mcl} --vc=0 | tee stats/lat_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_perf.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Run bandwidth tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_perf --vcmap-enable=0 --mcl=${mcl} --vc=${vc} --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_perf --vcmap-enable=1 --mcl=${mcl} --vc=0 --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_random.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_random.sv 8 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/test_random.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_random", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "5037b187-e561-4ca2-ad5b-d6c7816273c2" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_random 2 | test_random_ase 3 | obj 4 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_random 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_random.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_ccip_async/hw/par/ccip_async_addenda.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## This asynchronous clock crossing library is imported into Quartus with: 3 | ## 4 | ## source /BBB_ccip_async/hw/par/ccip_async_addenda.qsf 5 | ## 6 | 7 | ## Find the source tree relative to this script 8 | set this_script [dict get [ info frame 0 ] file] 9 | # Pop 3 levels (including the script name) off the path to find the root 10 | set CCIP_ASYNC_SRC [file join {*}[lrange [file split $this_script] 0 end-3]] 11 | 12 | ## Sources 13 | set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/hw/rtl/ccip_async_shim.sv 14 | set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/hw/rtl/ccip_async_activity_cnt.sv 15 | set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/hw/rtl/ccip_afifo_channel.sv 16 | 17 | ## Constraints 18 | set_global_assignment -name SDC_FILE $CCIP_ASYNC_SRC/hw/par/ccip_async.sdc 19 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_ccip_async/hw/par/sample_ccip_async_import.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Import the CCI-P asynchronous clock crossing module by copying this 3 | ## file, modifying the definition of CCIP_ASYNC_SRC below to point to 4 | ## the appropriate path and then sourcing the copied file from the QSF 5 | ## project. 6 | ## 7 | 8 | set CCIP_ASYNC_SRC "../samples/ccip-async" 9 | 10 | source $CCIP_ASYNC_SRC/par/ccip_async_addenda.qsf 11 | set_global_assignment -name SDC_FILE $CCIP_ASYNC_SRC/par/ccip_async.sdc 12 | 13 | # set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/HW/ccip_afifo_channel.sv 14 | # set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/HW/ccip_async_shim.sv 15 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/lib/BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt: -------------------------------------------------------------------------------- 1 | ## 2 | ## Include this file in an ASE build to import MPF into a simulation environment 3 | ## by adding the following line to vlog_files.list in an ASE build directory: 4 | ## 5 | ## -F /ccip_async_sim_addenda.txt 6 | ## 7 | 8 | ../rtl/ccip_afifo_channel.sv 9 | ../rtl/ccip_async_activity_cnt.sv 10 | ../rtl/ccip_async_shim.sv 11 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/origin_test/Makefile: -------------------------------------------------------------------------------- 1 | CXX = g++ 2 | ARGS = -O2 3 | LIBS = -L../../common/libvai/lib -I../../common/libvai/include -lhardcloud -lMPF_VAI -lvai-c-ase 4 | TARGET = reed_solomon_decoder 5 | SRCS = main.cpp 6 | SRCS_FILES = $(foreach F, $(SRCS), $(F)) 7 | 8 | all: 9 | $(CXX) $(ARGS) $(SRCS_FILES) $(LIBS) -o $(TARGET) 10 | 11 | clean: 12 | rm -rf $(TARGET) 13 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/origin_test/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | size_t cmdarg_getsize(const char *arg) { 9 | size_t l = strlen(arg); 10 | uint64_t n = atoll(arg); 11 | 12 | return n; 13 | } 14 | 15 | int main(int argc, char *argv[]) 16 | { 17 | uint8_t* data_in; 18 | uint8_t* data_out; 19 | uint64_t size, ni, nj; 20 | 21 | if (argc < 2) { 22 | printf("Usage: %s data_size\n", argv[0]); 23 | return -1; 24 | } 25 | else { 26 | size = cmdarg_getsize(argv[1]); 27 | ni = 51*CL(1)*size/sizeof(uint8_t); 28 | nj = 47*CL(1)*size/sizeof(uint8_t); 29 | } 30 | 31 | HardcloudApp app; 32 | 33 | data_out = (uint8_t *) app.alloc_buffer(nj * sizeof(uint8_t)); 34 | data_in = (uint8_t *) app.alloc_buffer(ni * sizeof(uint8_t)); 35 | 36 | for (uint64_t i = 0; i < ni; i++) 37 | { 38 | data_in[i] = rand(); 39 | } 40 | 41 | printf("allocation done\n"); 42 | 43 | struct timespec ts1, ts2; 44 | timespec_get(&ts1, TIME_UTC); 45 | app.run(); 46 | timespec_get(&ts2, TIME_UTC); 47 | 48 | double t = (ts2.tv_sec*1000000 + ts2.tv_nsec/1000) - (ts1.tv_sec*1000000 + ts1.tv_nsec/1000); 49 | 50 | printf("time: %lf ms\n", t/1000); 51 | printf("throughput: %lf MB/s\n", 1.0*ni*sizeof(uint8_t)/1024.0/1024.0/(t/1000000)); 52 | 53 | app.delete_buffer(data_in); 54 | app.delete_buffer(data_out); 55 | 56 | return 0; 57 | } 58 | 59 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/rtl/BM_lamda.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/d1-buffer-overflow-rsd/rtl/BM_lamda.v -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/rtl/nomux.txt: -------------------------------------------------------------------------------- 1 | QI:../par/cci_base_par_files.qsf 2 | SI:../sim/base_addenda.txt 3 | 4 | C:sources.txt 5 | reed_solomon_decoder.json 6 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/rtl/reed_solomon_decoder.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "reed_solomon_decoder", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "1cddcf01-c266-44de-af63-9d09858310e5" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/rtl/reed_solomon_decoder.sv: -------------------------------------------------------------------------------- 1 | // reed_solomon_decoder.sv 2 | 3 | module reed_solomon_decoder 4 | ( 5 | input logic clk, 6 | input logic reset, 7 | input logic [7:0] data_in, 8 | input logic valid_in, 9 | output logic [7:0] data_out, 10 | output logic valid_out 11 | ); 12 | 13 | RS_dec uu_rs_dec 14 | ( 15 | .clk (clk), 16 | .reset (reset), 17 | .input_byte (data_in), 18 | .CE (valid_in), 19 | .Out_byte (data_out), 20 | .CEO (valid_out), 21 | .Valid_out () 22 | ); 23 | 24 | endmodule : reed_solomon_decoder 25 | 26 | -------------------------------------------------------------------------------- /d1-buffer-overflow-rsd/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | +incdir+. 2 | +define+AFU_WITHMUX_NAME=reed_solomon_decoder_top 3 | +define+AFU_NOMUX_NAME=ccip_std_afu 4 | reed_solomon_decoder_pkg.sv 5 | 6 | BM_lamda.v 7 | DP_RAM.v 8 | error_correction.v 9 | GF_matrix_ascending_binary.v 10 | GF_matrix_dec.v 11 | GF_mult_add_syndromes.v 12 | input_syndromes.v 13 | lamda_roots.v 14 | Omega_Phy.v 15 | out_stage.v 16 | RS_dec.v 17 | transport_in2out.v 18 | 19 | reed_solomon_decoder.sv 20 | reed_solomon_decoder_csr.sv 21 | reed_solomon_decoder_fifo.sv 22 | reed_solomon_decoder_requestor.sv 23 | ccip_std_afu.sv 24 | -------------------------------------------------------------------------------- /d10-failure-to-update-sha512/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | sha512_test 6 | -------------------------------------------------------------------------------- /d10-failure-to-update-sha512/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d10-failure-to-update-sha512/ccip/platform_shims/README.md: -------------------------------------------------------------------------------- 1 | # Platform Shims 2 | 3 | Shims here are invoked by the top-level code that manages the partial reconfiguration 4 | boundary. Instead of directly instantiating an AFU (e.g. ccip_std_afu), these 5 | intermediate shims will be mapped first. The shims transform the interface and then 6 | connect to the AFU. **These shims and sub-directories are internal to the platform 7 | interface manager. Their interfaces or semantics may change from release to release.** 8 | 9 | Shims names are defined in the JSON field *platform-shim-module-name* in 10 | AFU top-level interface descriptions: [afu\_top\_ifc\_db](../../../afu_top_ifc_db/). 11 | 12 | Shims typically offer automatic clock crossing and automatic platform-specific 13 | register stage insertion to aid in timing closure. See the various instances of 14 | *clock* and *add-timing-reg-stages* in 15 | [platform\_defaults.json](../../../platform_db/platform_defaults.json). 16 | 17 | Some modules here are sub-shims, instantiated by larger shims. For example, 18 | platform\_shim\_ccip() manages only CCI-P clock crossing and register stage insertion. 19 | It is instantiated by platform\_shim\_ccip\_std\_afu(). 20 | -------------------------------------------------------------------------------- /d10-failure-to-update-sha512/ccip/platform_shims/utils/quartus_ip/README: -------------------------------------------------------------------------------- 1 | This library is extracted from code in Quartus releases using gen_platform_ip.sh 2 | in this directory. Point the script at a Quartus release and it will do the rest. 3 | The module names are modified to make them unique, replacing the leading "altera" 4 | with "platform_utils". 5 | 6 | The SDC files are here instead of in a par directory to keep all the Qsys 7 | code together. 8 | 9 | Extracted components include: 10 | * Qsys Avalon-MM Clock Crossing Bridge 11 | * Qsys Avalon-MM Pipeline Bridge 12 | 13 | 14 | Note: copyrights should be changed to BSD/MIT licenses. 15 | -------------------------------------------------------------------------------- /d10-failure-to-update-sha512/ccip/platform_shims/utils/quartus_ip/platform_utils_dcfifo_synchronizer_bundle.v: -------------------------------------------------------------------------------- 1 | // $File: //acds/rel/18.0/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $ 2 | // $Revision: #1 $ 3 | // $Date: 2018/02/08 $ 4 | // $Author: psgswbuild $ 5 | //------------------------------------------------------------------------------- 6 | 7 | `timescale 1 ns / 1 ns 8 | module platform_utils_dcfifo_synchronizer_bundle( 9 | clk, 10 | reset_n, 11 | din, 12 | dout 13 | ); 14 | parameter WIDTH = 1; 15 | parameter DEPTH = 3; 16 | 17 | input clk; 18 | input reset_n; 19 | input [WIDTH-1:0] din; 20 | output [WIDTH-1:0] dout; 21 | 22 | genvar i; 23 | 24 | generate 25 | for (i=0; i 11 | 12 | typedef enum 13 | { 14 | eFTYP_AFU = 1, 15 | eFTYP_BBB = 2, 16 | eFTYP_PVT = 3 17 | } 18 | CCIP_FEATURE_TYPE; 19 | 20 | 21 | // 22 | // Decode a device feature header (all except AFU headers) 23 | // 24 | class CCIP_FEATURE_DFH 25 | { 26 | private: 27 | // Encoded feature header 28 | bt64bitCSR dfh; 29 | 30 | public: 31 | CCIP_FEATURE_DFH(bt64bitCSR h) 32 | { 33 | dfh = h; 34 | } 35 | 36 | ~CCIP_FEATURE_DFH() {}; 37 | 38 | CCIP_FEATURE_TYPE getFeatureType() 39 | { 40 | return CCIP_FEATURE_TYPE((dfh >> 60) & 0xf); 41 | } 42 | 43 | uint32_t getVersion() 44 | { 45 | return (dfh >> 12) & 0xf; 46 | } 47 | 48 | uint32_t getID() 49 | { 50 | return dfh & 0xfff; 51 | } 52 | 53 | uint32_t getNext() 54 | { 55 | return (dfh >> 16) & 0xffffff; 56 | } 57 | 58 | bool isEOL() 59 | { 60 | return ((dfh >> 40) & 1) == 1; 61 | } 62 | }; 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/hw/rtl/cci-mpf-prims/README: -------------------------------------------------------------------------------- 1 | Primitives used by MPF (Memory Properties Factory) 2 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim.vh: -------------------------------------------------------------------------------- 1 | // 2 | // Wrapper for MPF shim structures and functions. 3 | // 4 | 5 | `ifndef CCI_MPF_SHIM_VH 6 | `define CCI_MPF_SHIM_VH 7 | 8 | import cci_mpf_shim_pkg::*; 9 | 10 | `endif 11 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_edge/README: -------------------------------------------------------------------------------- 1 | Edge shims are the final components of the primary MPF pipeline at 2 | both the AFU and FIU ends. The edge provides a number of functions: 3 | 4 | - Write data coming from the AFU is written to block RAM and dropped from 5 | channel 1 TX messages sent through MPF. The data is restored from the block 6 | RAM on exit in the FIU edge block. This greatly reduces the logic 7 | required for buffering data in the MPF pipeline. 8 | 9 | - Multi-line writes are reduced to a single control message by the AFU 10 | edge, allowing MPF to treat even multi-beat writes as a single flit. 11 | All flits are restored from the single control flit by MPF's FIU edge. 12 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_vtp/README: -------------------------------------------------------------------------------- 1 | The virtual to physical (VTP) shim. 2 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/hw/rtl/cci_mpf_sources.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Import MPF into an RTL project for either simulation or synthesis by including this 3 | # configuration file in a source list. Source lists are parsed by OPAE's rtl_src_config, 4 | # which is invoked by both afu_sim_setup and afu_synth_setup. 5 | # 6 | 7 | SI:../sim/cci_mpf_sim_addenda.txt 8 | QI:../par/qsf_cci_mpf_PAR_files.qsf 9 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/samples/afu/cci_mpf_library_import.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## MPF Quartus import -- 3 | ## 4 | ## Change the configuration parameters below and use this file as 5 | ## a template for importing the MPF library using: 6 | ## 7 | ## source cci_mpf_library_import.qsf 8 | ## 9 | 10 | 11 | ## Define the target platform. The list of platforms is in 12 | ## hw/rtl/cci-mpf-if/cci_mpf_platform.vh. 13 | ## 14 | set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_BDX=1" 15 | 16 | 17 | ## Define the path to the MPF sources 18 | ## 19 | set CCI_MPF_SRC "../samples/cci-mpf" 20 | 21 | 22 | ## Import sources 23 | ## 24 | source $CCI_MPF_SRC/hw/par/qsf_cci_mpf_PAR_files.qsf 25 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/scripts/iterate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | RUNCOUNT=0 4 | ERRCOUNT=0 5 | RUNLIMIT=$1 6 | 7 | TEST='rm -rf ../build && ./test-helloalivtpnlb-ase.sh' 8 | 9 | if [ -z "$1" ]; then 10 | echo "USAGE: $0 " 11 | exit -1 12 | fi 13 | 14 | while [ $RUNCOUNT -lt $RUNLIMIT ]; do 15 | echo -n "---- Test run $RUNCOUNT/$RUNLIMIT ----> " 16 | # $TEST 17 | rm -rf ../build && ./test-helloalivtpnlb-ase.sh &> iteration.${RUNCOUNT}.log 18 | if [ $? -eq 0 ]; then 19 | echo "success." 20 | else 21 | echo "failure." 22 | echo "Killing simulation." 23 | sleep 2 24 | killall ase_simv 25 | ERRCOUNT=$(( $ERRCOUNT + 1 )) 26 | fi 27 | RUNCOUNT=$(( $RUNCOUNT + 1 )) 28 | done 29 | 30 | echo "====================================================================" 31 | echo "Summary: $ERRCOUNT of $RUNCOUNT tests failed." 32 | 33 | exit $ERRCOUNT 34 | 35 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | build* 2 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/sw/README: -------------------------------------------------------------------------------- 1 | This tree holds MPF software libraries for controlling MPF shims on FPGAs. 2 | 3 | The library build is configured by CMake. Starting in the directory 4 | holding this README: 5 | 6 | mkdir build 7 | cd build 8 | cmake ../ 9 | make 10 | make install 11 | 12 | The build directory may be anywhere -- just adjust the path of this sw 13 | source directory passed to CMake. 14 | 15 | To select an installation directory other than CMake's default, set 16 | -DCMAKE_INSTALL_PREFIX= on the CMake command line. The MPF library 17 | and header file installation paths are layed out so they may be embedded 18 | in the standard Intel-provided FPGA library and header file trees. 19 | 20 | Set -DCMAKE_BUILD_TYPE=Debug on the CMake command line to emit symbols and 21 | eliminate optimization. 22 | 23 | Warning: the CMake "Release" build type causes errors and is not currently 24 | supported. 25 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/base/hw/par/cci_mpf_test_base_PAR_files.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Common configuration for synthesizing MPF tests. 3 | ## 4 | 5 | ## Find the root of the BBB source tree (6 levels up the directory tree) 6 | set this_script [dict get [ info frame 0 ] file] 7 | set BBB_CCI_SRC [file join {*}[lrange [file split $this_script] 0 end-7]] 8 | 9 | ## MPF and async FIFO libraries 10 | source $BBB_CCI_SRC/BBB_cci_mpf/hw/par/qsf_cci_mpf_PAR_files.qsf 11 | source $BBB_CCI_SRC/BBB_ccip_async/hw/par/ccip_async_addenda.qsf 12 | 13 | ## Base test sources 14 | set_global_assignment -name SEARCH_PATH $CCI_MPF_SRC/test/test-mpf/base/hw/rtl 15 | 16 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_afu.sv 17 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_csrs.sv 18 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/base/hw/rtl/sys_cfg_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef SYS_CFG_PKG_SV 2 | `define SYS_CFG_PKG_SV 3 | // `define CCIP_DEBUG // Add ccip_debug_module 4 | `define VENDOR_ALTERA // Use Altera FPGA 5 | `define TOOL_QUARTUS // Use Altera Quartus Tools 6 | `endif 7 | 8 | 9 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/base/hw/sim/cci_mpf_test_base_addenda.txt: -------------------------------------------------------------------------------- 1 | ## 2 | ## Base include file for describing MPF tests. 3 | ## 4 | 5 | # Include MPF 6 | -F ../../../../../hw/sim/cci_mpf_sim_addenda.txt 7 | 8 | # Include async FIFO 9 | -F ../../../../../../BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt 10 | 11 | +incdir+../rtl 12 | 13 | ../rtl/cci_test_afu.sv 14 | ../rtl/cci_test_csrs.sv 15 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/base/sw/base_include.mk: -------------------------------------------------------------------------------- 1 | ## 2 | ## Define base source files 3 | ## 4 | 5 | BASE_FILE_PATH = ../../base/sw 6 | BASE_FILE_SRC = cci_test_main.cpp opae_svc_wrapper.cpp 7 | BASE_FILE_INC = $(BASE_FILE_PATH)/opae_svc_wrapper.h 8 | 9 | VPATH = .:$(BASE_FILE_PATH) 10 | 11 | CPPFLAGS ?= -std=c++11 12 | CXX ?= g++ 13 | LDFLAGS ?= 14 | 15 | ifeq (,$(CFLAGS)) 16 | CFLAGS = -g -O2 17 | endif 18 | 19 | ifneq (,$(ndebug)) 20 | else 21 | CPPFLAGS += -DENABLE_DEBUG=1 22 | endif 23 | ifneq (,$(nassert)) 24 | else 25 | CPPFLAGS += -DENABLE_ASSERT=1 26 | endif 27 | 28 | ifeq (,$(DESTDIR)) 29 | ifneq (,$(prefix)) 30 | CPPFLAGS += -I$(prefix)/include 31 | LDFLAGS += -L$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(prefix)/lib \ 32 | -L$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(prefix)/lib64 33 | endif 34 | else 35 | ifeq (,$(prefix)) 36 | prefix = /usr/local 37 | endif 38 | CPPFLAGS += -I$(DESTDIR)$(prefix)/include 39 | LDFLAGS += -L$(DESTDIR)$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib \ 40 | -L$(DESTDIR)$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib64 41 | endif 42 | 43 | CPPFLAGS += -I../../base/sw 44 | LDFLAGS += -lboost_program_options -luuid -lMPF-cxx -lMPF -lopae-cxx-core 45 | 46 | FPGA_LIBS = -lopae-c -ljson-c 47 | ASE_LIBS = -lopae-c-ase 48 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/README: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null is a CCI-P test. The AFU uses MPF SystemVerilog interfaces 2 | but the actual MPF shim collection is never instantiated. 3 | 4 | The test allocates a collection of 2MB buffers. The write process streams through 5 | a buffer once, writing a known value to each line. The known value changes with 6 | each pass through a buffer. When a buffer is completely written the write 7 | process moves on to the next buffer. 8 | 9 | The read process follows the write process, streaming continuously through a 10 | single buffer that is not currently being written. The read process shifts 11 | buffers at the same time that the write process shifts. Each read response 12 | value is checked against the expected response. When a mismatch is detected 13 | the location and expected value are forwarded to the CPU. The CPU then 14 | checks the actual value in memory and determines whether the value in memory 15 | is correct. The error is then categorized as either write or read failure. 16 | 17 | The CPU is involved only to categorize errors and to control the length 18 | and number of testing passes. All other data comparison is done on the FPGA. 19 | 20 | There are options for 1, 2, 4 or variable size requests (--mcl) and the test 21 | can target either VA, one channel or some channel patterns (--rd-vc / 22 | --wr-vc). The channel used for signaling errors can also be configured 23 | (--dsm-vc). 24 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null.json 2 | 3 | # For now we force MPF to a particular platform. This will be fixed later. 4 | +define+MPF_PLATFORM_BDX 5 | 6 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 7 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 8 | 9 | +incdir+. 10 | test_cci_mpf_null.sv 11 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/test_cci_mpf_null.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_cci_mpf_null", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "bfd75b03-9608-4e82-ae22-f61a62b8f992" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null 2 | test_cci_mpf_null_ase 3 | obj 4 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_cci_mpf_null 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_cci_mpf_null.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/README: -------------------------------------------------------------------------------- 1 | test_mem_perf RTL is the basis for several tests. On the HW side it is a 2 | simple engine that generates sequential read and/or write traffic of varying 3 | buffer sizes, run lengths and offered loads. Software tests can configure 4 | the hardware for a variety of studies. 5 | 6 | sw/test_mem_latency computes a variety of latency vs. bandwidth data points. 7 | Scripts for generating and plotting results are stored in sw/scripts. 8 | The checked-in configuration assumes that test_mem_perf is built in two 9 | configurations: one with and one without MPF's ROB (the MPF SORT_READ_RESPONSES 10 | configuration option). It is run in the sw directory by: 11 | 12 | < load the version with SORT_READ_RESPONSES enabled > 13 | ./scripts/run_lat.sh ord 14 | < load the default version (SORT_READ_RESPONSES disabled) > 15 | ./scripts/run_lat.sh 16 | ./scripts/plot_lat.sh 17 | 18 | A graph will be stored in bw-lat.pdf. 19 | 20 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_mem_perf.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_mem_perf.sv 8 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/test_mem_perf.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_mem_perf", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "6da50a7d-c76f-42b1-9018-ec1aa7629471" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | compute_vc_map_params 2 | compute_latency_qos_params 3 | test_mem_latency 4 | test_mem_perf 5 | *_ase 6 | obj 7 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_lat.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | ## 4 | ## Run latency tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_latency --vcmap-enable=0 --mcl=${mcl} --vc=${vc} | tee stats/lat_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_latency --vcmap-enable=1 --mcl=${mcl} --vc=0 | tee stats/lat_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_perf.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Run bandwidth tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_perf --vcmap-enable=0 --mcl=${mcl} --vc=${vc} --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_perf --vcmap-enable=1 --mcl=${mcl} --vc=0 --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_random.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_random.sv 8 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/test_random.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_random", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "5037b187-e561-4ca2-ad5b-d6c7816273c2" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_random 2 | test_random_ase 3 | obj 4 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_random 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_random.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_ccip_async/hw/par/ccip_async_addenda.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## This asynchronous clock crossing library is imported into Quartus with: 3 | ## 4 | ## source /BBB_ccip_async/hw/par/ccip_async_addenda.qsf 5 | ## 6 | 7 | ## Find the source tree relative to this script 8 | set this_script [dict get [ info frame 0 ] file] 9 | # Pop 3 levels (including the script name) off the path to find the root 10 | set CCIP_ASYNC_SRC [file join {*}[lrange [file split $this_script] 0 end-3]] 11 | 12 | ## Sources 13 | set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/hw/rtl/ccip_async_shim.sv 14 | set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/hw/rtl/ccip_async_activity_cnt.sv 15 | set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/hw/rtl/ccip_afifo_channel.sv 16 | 17 | ## Constraints 18 | set_global_assignment -name SDC_FILE $CCIP_ASYNC_SRC/hw/par/ccip_async.sdc 19 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_ccip_async/hw/par/sample_ccip_async_import.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Import the CCI-P asynchronous clock crossing module by copying this 3 | ## file, modifying the definition of CCIP_ASYNC_SRC below to point to 4 | ## the appropriate path and then sourcing the copied file from the QSF 5 | ## project. 6 | ## 7 | 8 | set CCIP_ASYNC_SRC "../samples/ccip-async" 9 | 10 | source $CCIP_ASYNC_SRC/par/ccip_async_addenda.qsf 11 | set_global_assignment -name SDC_FILE $CCIP_ASYNC_SRC/par/ccip_async.sdc 12 | 13 | # set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/HW/ccip_afifo_channel.sv 14 | # set_global_assignment -name SYSTEMVERILOG_FILE $CCIP_ASYNC_SRC/HW/ccip_async_shim.sv 15 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/lib/BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt: -------------------------------------------------------------------------------- 1 | ## 2 | ## Include this file in an ASE build to import MPF into a simulation environment 3 | ## by adding the following line to vlog_files.list in an ASE build directory: 4 | ## 5 | ## -F /ccip_async_sim_addenda.txt 6 | ## 7 | 8 | ../rtl/ccip_afifo_channel.sv 9 | ../rtl/ccip_async_activity_cnt.sv 10 | ../rtl/ccip_async_shim.sv 11 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/origin_test/Makefile: -------------------------------------------------------------------------------- 1 | CXX = g++ 2 | ARGS = -O2 -g 3 | LIBS = -L../../common/libvai/lib -I../../common/libvai/include -lhardcloud -lMPF_VAI -lvai-c-ase -lpng 4 | TARGET = grayscale 5 | SRCS = main.cpp image.cpp 6 | SRCS_FILES = $(foreach F, $(SRCS), $(F)) 7 | 8 | all: 9 | $(CXX) $(ARGS) $(SRCS_FILES) $(LIBS) -o $(TARGET) 10 | 11 | clean: 12 | rm -rf $(TARGET) 13 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/origin_test/image.h: -------------------------------------------------------------------------------- 1 | //===----- image.h - load image files -------------------------------------===// 2 | // 3 | // Copyright (c) 2017 Ciro Ceissler 4 | // 5 | // See LICENSE for details. 6 | // 7 | //===----------------------------------------------------------------------===// 8 | // 9 | // Class to load image file, only supports png format. 10 | // 11 | //===----------------------------------------------------------------------===// 12 | 13 | #ifndef IMAGE_H_ 14 | #define IMAGE_H_ 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | class Image { 21 | private: 22 | png_byte color_type; 23 | png_byte bit_depth; 24 | 25 | void map_to_array(); 26 | 27 | public: 28 | Image() {} 29 | 30 | explicit Image(const std::string& filename) { 31 | std::cout << "[image] loading file: " << filename << std::endl; 32 | 33 | this->read_png_file(filename); 34 | } 35 | 36 | unsigned int* array_in; 37 | unsigned int* array_out; 38 | 39 | void map_back(); 40 | 41 | ~Image() {} 42 | 43 | int width; 44 | int height; 45 | png_bytep *row_pointers; 46 | 47 | void read_png_file(const std::string& filename); 48 | void write_png_file(const std::string& filename); 49 | void compare(const std::string& filename); 50 | }; 51 | 52 | #endif // IMAGE_H_ 53 | 54 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/origin_test/input.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/d2-buffer-overflow-grayscale/origin_test/input.png -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/origin_test/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | #include "image.h" 7 | 8 | int main(int argc, char *argv[]) 9 | { 10 | std::string file_input("input.png"); 11 | std::string file_output("output.png"); 12 | 13 | Image image(file_input); 14 | 15 | unsigned int size = image.height*image.width; 16 | unsigned int height = image.height; 17 | unsigned int width = image.width; 18 | 19 | unsigned int* image_in = image.array_in; 20 | unsigned int* image_out = image.array_out; 21 | 22 | HardcloudApp app; 23 | 24 | unsigned int *out_buf = (unsigned int*)app.alloc_buffer(size*sizeof(unsigned int)); 25 | unsigned int *in_buf = (unsigned int*)app.alloc_buffer(size*sizeof(unsigned int)); 26 | 27 | memcpy(in_buf, image_in, size*sizeof(unsigned int)); 28 | 29 | printf("allocation done\n"); 30 | 31 | struct timespec ts1, ts2; 32 | timespec_get(&ts1, TIME_UTC); 33 | app.run(); 34 | timespec_get(&ts2, TIME_UTC); 35 | 36 | double t = (ts2.tv_sec*1000000 + ts2.tv_nsec/1000) - (ts1.tv_sec*1000000 + ts1.tv_nsec/1000); 37 | 38 | printf("time: %lf ms\n", t/1000); 39 | printf("throughput: %lf fig/s\n", 1.0/(t/1000000)); 40 | 41 | memcpy(image_out, out_buf, size*sizeof(unsigned int)); 42 | 43 | image.map_back(); 44 | 45 | image.write_png_file(file_output); 46 | app.delete_buffer(in_buf); 47 | app.delete_buffer(out_buf); 48 | 49 | return 0; 50 | } 51 | 52 | -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/origin_test/output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/d2-buffer-overflow-grayscale/origin_test/output.png -------------------------------------------------------------------------------- /d2-buffer-overflow-grayscale/rtl/grayscale.sv: -------------------------------------------------------------------------------- 1 | // grayscale.sv 2 | 3 | module grayscale 4 | ( 5 | input logic clk, 6 | input logic reset, 7 | input logic [511:0] data_in, 8 | input logic valid_in, 9 | output logic [511:0] data_out, 10 | output logic valid_out 11 | ); 12 | 13 | function [31:0] rgb2luma(input logic [31:0] data); 14 | logic [7:0] tmp; 15 | 16 | tmp = data[7:0] >> 2; 17 | tmp += data[7:0] >> 5; 18 | tmp += data[15:8] >> 1; 19 | tmp += data[15:8] >> 4; 20 | tmp += data[23:16] >> 4; 21 | tmp += data[23:16] >> 5; 22 | 23 | return {tmp, tmp, tmp}; 24 | endfunction : rgb2luma 25 | 26 | always_ff@(posedge clk or posedge reset) begin 27 | if (reset) begin 28 | valid_out <= 1'b0; 29 | end 30 | else begin 31 | valid_out <= valid_in; 32 | end 33 | end 34 | 35 | always_ff@(posedge clk or posedge reset) begin 36 | if (reset) begin 37 | data_out <= '0; 38 | end 39 | else begin 40 | for (int i = 0; i < 16; i++) begin 41 | data_out[32*i +: 32] <= rgb2luma(data_in[32*i +: 32]); 42 | end 43 | end 44 | end 45 | 46 | endmodule : grayscale 47 | 48 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | grayscale_mux4_test 6 | filter.txt 7 | optimus.losscheck.0.v 8 | optimus.losscheck.1.v 9 | optimus_grayscale_mux4_test_losscheck 10 | sources.losscheck-opae.0.txt 11 | sources.losscheck-opae.1.txt 12 | sources.losscheck.0.txt 13 | sources.losscheck.1.txt 14 | work_losscheck_1/ 15 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/ccip/platform_shims/README.md: -------------------------------------------------------------------------------- 1 | # Platform Shims 2 | 3 | Shims here are invoked by the top-level code that manages the partial reconfiguration 4 | boundary. Instead of directly instantiating an AFU (e.g. ccip_std_afu), these 5 | intermediate shims will be mapped first. The shims transform the interface and then 6 | connect to the AFU. **These shims and sub-directories are internal to the platform 7 | interface manager. Their interfaces or semantics may change from release to release.** 8 | 9 | Shims names are defined in the JSON field *platform-shim-module-name* in 10 | AFU top-level interface descriptions: [afu\_top\_ifc\_db](../../../afu_top_ifc_db/). 11 | 12 | Shims typically offer automatic clock crossing and automatic platform-specific 13 | register stage insertion to aid in timing closure. See the various instances of 14 | *clock* and *add-timing-reg-stages* in 15 | [platform\_defaults.json](../../../platform_db/platform_defaults.json). 16 | 17 | Some modules here are sub-shims, instantiated by larger shims. For example, 18 | platform\_shim\_ccip() manages only CCI-P clock crossing and register stage insertion. 19 | It is instantiated by platform\_shim\_ccip\_std\_afu(). 20 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/ccip/platform_shims/utils/quartus_ip/README: -------------------------------------------------------------------------------- 1 | This library is extracted from code in Quartus releases using gen_platform_ip.sh 2 | in this directory. Point the script at a Quartus release and it will do the rest. 3 | The module names are modified to make them unique, replacing the leading "altera" 4 | with "platform_utils". 5 | 6 | The SDC files are here instead of in a par directory to keep all the Qsys 7 | code together. 8 | 9 | Extracted components include: 10 | * Qsys Avalon-MM Clock Crossing Bridge 11 | * Qsys Avalon-MM Pipeline Bridge 12 | 13 | 14 | Note: copyrights should be changed to BSD/MIT licenses. 15 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/ccip/platform_shims/utils/quartus_ip/platform_utils_dcfifo_synchronizer_bundle.v: -------------------------------------------------------------------------------- 1 | // $File: //acds/rel/18.0/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $ 2 | // $Revision: #1 $ 3 | // $Date: 2018/02/08 $ 4 | // $Author: psgswbuild $ 5 | //------------------------------------------------------------------------------- 6 | 7 | `timescale 1 ns / 1 ns 8 | module platform_utils_dcfifo_synchronizer_bundle( 9 | clk, 10 | reset_n, 11 | din, 12 | dout 13 | ); 14 | parameter WIDTH = 1; 15 | parameter DEPTH = 3; 16 | 17 | input clk; 18 | input reset_n; 19 | input [WIDTH-1:0] din; 20 | output [WIDTH-1:0] dout; 21 | 22 | genvar i; 23 | 24 | generate 25 | for (i=0; i 11 | 12 | typedef enum 13 | { 14 | eFTYP_AFU = 1, 15 | eFTYP_BBB = 2, 16 | eFTYP_PVT = 3 17 | } 18 | CCIP_FEATURE_TYPE; 19 | 20 | 21 | // 22 | // Decode a device feature header (all except AFU headers) 23 | // 24 | class CCIP_FEATURE_DFH 25 | { 26 | private: 27 | // Encoded feature header 28 | bt64bitCSR dfh; 29 | 30 | public: 31 | CCIP_FEATURE_DFH(bt64bitCSR h) 32 | { 33 | dfh = h; 34 | } 35 | 36 | ~CCIP_FEATURE_DFH() {}; 37 | 38 | CCIP_FEATURE_TYPE getFeatureType() 39 | { 40 | return CCIP_FEATURE_TYPE((dfh >> 60) & 0xf); 41 | } 42 | 43 | uint32_t getVersion() 44 | { 45 | return (dfh >> 12) & 0xf; 46 | } 47 | 48 | uint32_t getID() 49 | { 50 | return dfh & 0xfff; 51 | } 52 | 53 | uint32_t getNext() 54 | { 55 | return (dfh >> 16) & 0xffffff; 56 | } 57 | 58 | bool isEOL() 59 | { 60 | return ((dfh >> 40) & 1) == 1; 61 | } 62 | }; 63 | 64 | #endif 65 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-prims/README: -------------------------------------------------------------------------------- 1 | Primitives used by MPF (Memory Properties Factory) 2 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim.vh: -------------------------------------------------------------------------------- 1 | // 2 | // Wrapper for MPF shim structures and functions. 3 | // 4 | 5 | `ifndef CCI_MPF_SHIM_VH 6 | `define CCI_MPF_SHIM_VH 7 | 8 | import cci_mpf_shim_pkg::*; 9 | 10 | `endif 11 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_edge/README: -------------------------------------------------------------------------------- 1 | Edge shims are the final components of the primary MPF pipeline at 2 | both the AFU and FIU ends. The edge provides a number of functions: 3 | 4 | - Write data coming from the AFU is written to block RAM and dropped from 5 | channel 1 TX messages sent through MPF. The data is restored from the block 6 | RAM on exit in the FIU edge block. This greatly reduces the logic 7 | required for buffering data in the MPF pipeline. 8 | 9 | - Multi-line writes are reduced to a single control message by the AFU 10 | edge, allowing MPF to treat even multi-beat writes as a single flit. 11 | All flits are restored from the single control flit by MPF's FIU edge. 12 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/hw/rtl/cci-mpf-shims/cci_mpf_shim_vtp/README: -------------------------------------------------------------------------------- 1 | The virtual to physical (VTP) shim. 2 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/hw/rtl/cci_mpf_sources.txt: -------------------------------------------------------------------------------- 1 | # 2 | # Import MPF into an RTL project for either simulation or synthesis by including this 3 | # configuration file in a source list. Source lists are parsed by OPAE's rtl_src_config, 4 | # which is invoked by both afu_sim_setup and afu_synth_setup. 5 | # 6 | 7 | SI:../sim/cci_mpf_sim_addenda.txt 8 | QI:../par/qsf_cci_mpf_PAR_files.qsf 9 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/samples/afu/cci_mpf_library_import.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## MPF Quartus import -- 3 | ## 4 | ## Change the configuration parameters below and use this file as 5 | ## a template for importing the MPF library using: 6 | ## 7 | ## source cci_mpf_library_import.qsf 8 | ## 9 | 10 | 11 | ## Define the target platform. The list of platforms is in 12 | ## hw/rtl/cci-mpf-if/cci_mpf_platform.vh. 13 | ## 14 | set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_BDX=1" 15 | 16 | 17 | ## Define the path to the MPF sources 18 | ## 19 | set CCI_MPF_SRC "../samples/cci-mpf" 20 | 21 | 22 | ## Import sources 23 | ## 24 | source $CCI_MPF_SRC/hw/par/qsf_cci_mpf_PAR_files.qsf 25 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/scripts/iterate.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | RUNCOUNT=0 4 | ERRCOUNT=0 5 | RUNLIMIT=$1 6 | 7 | TEST='rm -rf ../build && ./test-helloalivtpnlb-ase.sh' 8 | 9 | if [ -z "$1" ]; then 10 | echo "USAGE: $0 " 11 | exit -1 12 | fi 13 | 14 | while [ $RUNCOUNT -lt $RUNLIMIT ]; do 15 | echo -n "---- Test run $RUNCOUNT/$RUNLIMIT ----> " 16 | # $TEST 17 | rm -rf ../build && ./test-helloalivtpnlb-ase.sh &> iteration.${RUNCOUNT}.log 18 | if [ $? -eq 0 ]; then 19 | echo "success." 20 | else 21 | echo "failure." 22 | echo "Killing simulation." 23 | sleep 2 24 | killall ase_simv 25 | ERRCOUNT=$(( $ERRCOUNT + 1 )) 26 | fi 27 | RUNCOUNT=$(( $RUNCOUNT + 1 )) 28 | done 29 | 30 | echo "====================================================================" 31 | echo "Summary: $ERRCOUNT of $RUNCOUNT tests failed." 32 | 33 | exit $ERRCOUNT 34 | 35 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | build* 2 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/sw/README: -------------------------------------------------------------------------------- 1 | This tree holds MPF software libraries for controlling MPF shims on FPGAs. 2 | 3 | The library build is configured by CMake. Starting in the directory 4 | holding this README: 5 | 6 | mkdir build 7 | cd build 8 | cmake ../ 9 | make 10 | make install 11 | 12 | The build directory may be anywhere -- just adjust the path of this sw 13 | source directory passed to CMake. 14 | 15 | To select an installation directory other than CMake's default, set 16 | -DCMAKE_INSTALL_PREFIX= on the CMake command line. The MPF library 17 | and header file installation paths are layed out so they may be embedded 18 | in the standard Intel-provided FPGA library and header file trees. 19 | 20 | Set -DCMAKE_BUILD_TYPE=Debug on the CMake command line to emit symbols and 21 | eliminate optimization. 22 | 23 | Warning: the CMake "Release" build type causes errors and is not currently 24 | supported. 25 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/base/hw/par/cci_mpf_test_base_PAR_files.qsf: -------------------------------------------------------------------------------- 1 | ## 2 | ## Common configuration for synthesizing MPF tests. 3 | ## 4 | 5 | ## Find the root of the BBB source tree (6 levels up the directory tree) 6 | set this_script [dict get [ info frame 0 ] file] 7 | set BBB_CCI_SRC [file join {*}[lrange [file split $this_script] 0 end-7]] 8 | 9 | ## MPF and async FIFO libraries 10 | source $BBB_CCI_SRC/BBB_cci_mpf/hw/par/qsf_cci_mpf_PAR_files.qsf 11 | source $BBB_CCI_SRC/BBB_ccip_async/hw/par/ccip_async_addenda.qsf 12 | 13 | ## Base test sources 14 | set_global_assignment -name SEARCH_PATH $CCI_MPF_SRC/test/test-mpf/base/hw/rtl 15 | 16 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_afu.sv 17 | set_global_assignment -name SYSTEMVERILOG_FILE $CCI_MPF_SRC/test/test-mpf/base/hw/rtl/cci_test_csrs.sv 18 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/base/hw/rtl/sys_cfg_pkg.svh: -------------------------------------------------------------------------------- 1 | `ifndef SYS_CFG_PKG_SV 2 | `define SYS_CFG_PKG_SV 3 | // `define CCIP_DEBUG // Add ccip_debug_module 4 | `define VENDOR_ALTERA // Use Altera FPGA 5 | `define TOOL_QUARTUS // Use Altera Quartus Tools 6 | `endif 7 | 8 | 9 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/base/hw/sim/cci_mpf_test_base_addenda.txt: -------------------------------------------------------------------------------- 1 | ## 2 | ## Base include file for describing MPF tests. 3 | ## 4 | 5 | # Include MPF 6 | -F ../../../../../hw/sim/cci_mpf_sim_addenda.txt 7 | 8 | # Include async FIFO 9 | -F ../../../../../../BBB_ccip_async/hw/sim/ccip_async_sim_addenda.txt 10 | 11 | +incdir+../rtl 12 | 13 | ../rtl/cci_test_afu.sv 14 | ../rtl/cci_test_csrs.sv 15 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/base/sw/base_include.mk: -------------------------------------------------------------------------------- 1 | ## 2 | ## Define base source files 3 | ## 4 | 5 | BASE_FILE_PATH = ../../base/sw 6 | BASE_FILE_SRC = cci_test_main.cpp opae_svc_wrapper.cpp 7 | BASE_FILE_INC = $(BASE_FILE_PATH)/opae_svc_wrapper.h 8 | 9 | VPATH = .:$(BASE_FILE_PATH) 10 | 11 | CPPFLAGS ?= -std=c++11 12 | CXX ?= g++ 13 | LDFLAGS ?= 14 | 15 | ifeq (,$(CFLAGS)) 16 | CFLAGS = -g -O2 17 | endif 18 | 19 | ifneq (,$(ndebug)) 20 | else 21 | CPPFLAGS += -DENABLE_DEBUG=1 22 | endif 23 | ifneq (,$(nassert)) 24 | else 25 | CPPFLAGS += -DENABLE_ASSERT=1 26 | endif 27 | 28 | ifeq (,$(DESTDIR)) 29 | ifneq (,$(prefix)) 30 | CPPFLAGS += -I$(prefix)/include 31 | LDFLAGS += -L$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(prefix)/lib \ 32 | -L$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(prefix)/lib64 33 | endif 34 | else 35 | ifeq (,$(prefix)) 36 | prefix = /usr/local 37 | endif 38 | CPPFLAGS += -I$(DESTDIR)$(prefix)/include 39 | LDFLAGS += -L$(DESTDIR)$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib \ 40 | -L$(DESTDIR)$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib64 41 | endif 42 | 43 | CPPFLAGS += -I../../base/sw 44 | LDFLAGS += -lboost_program_options -luuid -lMPF-cxx -lMPF -lopae-cxx-core 45 | 46 | FPGA_LIBS = -lopae-c -ljson-c 47 | ASE_LIBS = -lopae-c-ase 48 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/README: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null is a CCI-P test. The AFU uses MPF SystemVerilog interfaces 2 | but the actual MPF shim collection is never instantiated. 3 | 4 | The test allocates a collection of 2MB buffers. The write process streams through 5 | a buffer once, writing a known value to each line. The known value changes with 6 | each pass through a buffer. When a buffer is completely written the write 7 | process moves on to the next buffer. 8 | 9 | The read process follows the write process, streaming continuously through a 10 | single buffer that is not currently being written. The read process shifts 11 | buffers at the same time that the write process shifts. Each read response 12 | value is checked against the expected response. When a mismatch is detected 13 | the location and expected value are forwarded to the CPU. The CPU then 14 | checks the actual value in memory and determines whether the value in memory 15 | is correct. The error is then categorized as either write or read failure. 16 | 17 | The CPU is involved only to categorize errors and to control the length 18 | and number of testing passes. All other data comparison is done on the FPGA. 19 | 20 | There are options for 1, 2, 4 or variable size requests (--mcl) and the test 21 | can target either VA, one channel or some channel patterns (--rd-vc / 22 | --wr-vc). The channel used for signaling errors can also be configured 23 | (--dsm-vc). 24 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null.json 2 | 3 | # For now we force MPF to a particular platform. This will be fixed later. 4 | +define+MPF_PLATFORM_BDX 5 | 6 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 7 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 8 | 9 | +incdir+. 10 | test_cci_mpf_null.sv 11 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/rtl/test_cci_mpf_null.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_cci_mpf_null", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "bfd75b03-9608-4e82-ae22-f61a62b8f992" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_cci_mpf_null 2 | test_cci_mpf_null_ase 3 | obj 4 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_cci_mpf_null/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_cci_mpf_null 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_cci_mpf_null.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/README: -------------------------------------------------------------------------------- 1 | test_mem_perf RTL is the basis for several tests. On the HW side it is a 2 | simple engine that generates sequential read and/or write traffic of varying 3 | buffer sizes, run lengths and offered loads. Software tests can configure 4 | the hardware for a variety of studies. 5 | 6 | sw/test_mem_latency computes a variety of latency vs. bandwidth data points. 7 | Scripts for generating and plotting results are stored in sw/scripts. 8 | The checked-in configuration assumes that test_mem_perf is built in two 9 | configurations: one with and one without MPF's ROB (the MPF SORT_READ_RESPONSES 10 | configuration option). It is run in the sw directory by: 11 | 12 | < load the version with SORT_READ_RESPONSES enabled > 13 | ./scripts/run_lat.sh ord 14 | < load the default version (SORT_READ_RESPONSES disabled) > 15 | ./scripts/run_lat.sh 16 | ./scripts/plot_lat.sh 17 | 18 | A graph will be stored in bw-lat.pdf. 19 | 20 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_mem_perf.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_mem_perf.sv 8 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/rtl/test_mem_perf.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_mem_perf", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "6da50a7d-c76f-42b1-9018-ec1aa7629471" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/.gitignore: -------------------------------------------------------------------------------- 1 | compute_vc_map_params 2 | compute_latency_qos_params 3 | test_mem_latency 4 | test_mem_perf 5 | *_ase 6 | obj 7 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_lat.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | ## 4 | ## Run latency tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_latency --vcmap-enable=0 --mcl=${mcl} --vc=${vc} | tee stats/lat_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_latency --vcmap-enable=1 --mcl=${mcl} --vc=0 | tee stats/lat_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_mem_perf/sw/scripts/run_perf.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Run bandwidth tests. 5 | ## 6 | ## Arguments: 7 | ## $1 is the number of channels (default 3). For DCP use 1. 8 | ## $2 is a tag in the middle of file names. 9 | ## 10 | 11 | num_channels=3 12 | if [ -n "${1}" ]; then 13 | num_channels=${1} 14 | fi 15 | 16 | tag="" 17 | if [ -n "${2}" ]; then 18 | tag="${2}_" 19 | fi 20 | 21 | mkdir -p stats 22 | 23 | for mcl in 1 2 4 24 | do 25 | for ((vc=0; vc < ${num_channels}; vc++)) 26 | do 27 | ./test_mem_perf --vcmap-enable=0 --mcl=${mcl} --vc=${vc} --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}mcl${mcl}_vc${vc}.dat 28 | done 29 | 30 | if [ $num_channels -gt 1 ]; then 31 | ./test_mem_perf --vcmap-enable=1 --mcl=${mcl} --vc=0 --rdline-s=0 --wrline-m=0 | tee stats/perf_${tag}map_mcl${mcl}_vc0.dat 32 | fi 33 | done 34 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/sources.txt: -------------------------------------------------------------------------------- 1 | test_random.json 2 | 3 | SI:../../../base/hw/sim/cci_mpf_test_base_addenda.txt 4 | QI:../../../base/hw/par/cci_mpf_test_base_PAR_files.qsf 5 | 6 | +incdir+. 7 | test_random.sv 8 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/rtl/test_random.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": 1, 3 | "afu-image": { 4 | "power": 0, 5 | "afu-top-interface": 6 | { 7 | "name": "ccip_std_afu" 8 | }, 9 | "accelerator-clusters": 10 | [ 11 | { 12 | "name": "test_random", 13 | "total-contexts": 1, 14 | "accelerator-type-uuid": "5037b187-e561-4ca2-ad5b-d6c7816273c2" 15 | } 16 | ] 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/hw/sim/setup_ase: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | ## 4 | ## Setup ASE environment using ../rtl/sources.txt. 5 | ## 6 | 7 | # Absolute path to this script 8 | SCRIPT=$(readlink -f "$0") 9 | SCRIPT_PATH=$(dirname "$SCRIPT") 10 | 11 | afu_sim_setup --sources=${SCRIPT_PATH}/../rtl/sources.txt $* 12 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/.gitignore: -------------------------------------------------------------------------------- 1 | test_random 2 | test_random_ase 3 | obj 4 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_cci_mpf/test/test-mpf/test_random/sw/Makefile: -------------------------------------------------------------------------------- 1 | include ../../base/sw/base_include.mk 2 | 3 | # Primary test name 4 | TEST = test_random 5 | 6 | # Build directory, including generated .h files 7 | OBJDIR = obj 8 | CFLAGS += -I./$(OBJDIR) 9 | CPPFLAGS += -I./$(OBJDIR) 10 | 11 | # Files and folders 12 | SRCS = $(TEST).cpp $(BASE_FILE_SRC) 13 | OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.cpp,%.o,$(SRCS))) 14 | 15 | # Targets 16 | all: $(TEST) $(TEST)_ase 17 | 18 | # AFU info from JSON file, including AFU UUID 19 | AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h 20 | $(AFU_JSON_INFO): ../hw/rtl/test_random.json | objdir 21 | afu_json_mgr json-info --afu-json=$^ --c-hdr=$@ 22 | $(OBJS): $(AFU_JSON_INFO) 23 | 24 | $(TEST): $(OBJS) 25 | $(CXX) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS) 26 | 27 | $(TEST)_ase: $(OBJS) 28 | $(CXX) -o $@ $^ $(LDFLAGS) $(ASE_LIBS) 29 | 30 | $(OBJDIR)/%.o: %.cpp | objdir 31 | $(CXX) $(CPPFLAGS) $(CFLAGS) -c $< -o $@ 32 | 33 | clean: 34 | rm -rf $(TEST) $(TEST)_ase $(OBJDIR) 35 | 36 | objdir: 37 | @mkdir -p $(OBJDIR) 38 | 39 | .PHONY: all clean 40 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_vai_mux_nested/hw/sim/cci_mux_sim_addenda.txt: -------------------------------------------------------------------------------- 1 | +define+CCI_SIMULATION 2 | 3 | +incdir+../rtl 4 | 5 | ../rtl/ccip_mux_legacy.sv 6 | ../rtl/fair_arbiter.sv 7 | ../rtl/ccip_front_end.sv 8 | ../rtl/ccip_intf_regs.sv 9 | ../rtl/sync_C1Tx_fifo.v 10 | ../rtl/gram_sdp.v 11 | ../rtl/a10_ram_sdp_wysiwyg.v 12 | ../rtl/vai_audit_tx.sv 13 | ../rtl/vai_mux.sv 14 | ../rtl/vai_audit_rx.sv 15 | ../rtl/vai_mgr_afu.sv 16 | ../rtl/ccip_legacy_mux_nested.sv 17 | ../rtl/vai_audit_rx2.sv 18 | ../rtl/vai_mgr.sv 19 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/lib/BBB_vai_mux_nested/hw/sim/mux_simfiles.list: -------------------------------------------------------------------------------- 1 | ../rtl/ccip_mux.sv 2 | ../rtl/fair_arbiter.sv 3 | ../rtl/ccip_front_end.sv 4 | ../rtl/ccip_intf_regs.sv 5 | ../rtl/sync_C1Tx_fifo.v 6 | ../rtl/gram_sdp.v 7 | ../rtl/a10_ram_sdp_wysiwyg.v 8 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/origin_test/Makefile: -------------------------------------------------------------------------------- 1 | CXX = g++ 2 | ARGS = -O2 -g 3 | LIBS = -L../../common/libvai/lib -I../../common/libvai/include -lhardcloud -lMPF_VAI -lvai-c-ase -lpng 4 | TARGET = grayscale 5 | SRCS = main.cpp image.cpp 6 | SRCS_FILES = $(foreach F, $(SRCS), $(F)) 7 | 8 | all: 9 | $(CXX) $(ARGS) $(SRCS_FILES) $(LIBS) -o $(TARGET) 10 | 11 | clean: 12 | rm -rf $(TARGET) 13 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/origin_test/image.h: -------------------------------------------------------------------------------- 1 | //===----- image.h - load image files -------------------------------------===// 2 | // 3 | // Copyright (c) 2017 Ciro Ceissler 4 | // 5 | // See LICENSE for details. 6 | // 7 | //===----------------------------------------------------------------------===// 8 | // 9 | // Class to load image file, only supports png format. 10 | // 11 | //===----------------------------------------------------------------------===// 12 | 13 | #ifndef IMAGE_H_ 14 | #define IMAGE_H_ 15 | 16 | #include 17 | #include 18 | #include 19 | 20 | class Image { 21 | private: 22 | png_byte color_type; 23 | png_byte bit_depth; 24 | 25 | void map_to_array(); 26 | 27 | public: 28 | Image() {} 29 | 30 | explicit Image(const std::string& filename) { 31 | std::cout << "[image] loading file: " << filename << std::endl; 32 | 33 | this->read_png_file(filename); 34 | } 35 | 36 | unsigned int* array_in; 37 | unsigned int* array_out; 38 | 39 | void map_back(); 40 | 41 | ~Image() {} 42 | 43 | int width; 44 | int height; 45 | png_bytep *row_pointers; 46 | 47 | void read_png_file(const std::string& filename); 48 | void write_png_file(const std::string& filename); 49 | void compare(const std::string& filename); 50 | }; 51 | 52 | #endif // IMAGE_H_ 53 | 54 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/origin_test/input.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/d3-buffer-overflow-optimus/origin_test/input.png -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/origin_test/main.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | #include "image.h" 7 | 8 | int main(int argc, char *argv[]) 9 | { 10 | std::string file_input("input.png"); 11 | std::string file_output("output.png"); 12 | 13 | Image image(file_input); 14 | 15 | unsigned int size = image.height*image.width; 16 | unsigned int height = image.height; 17 | unsigned int width = image.width; 18 | 19 | unsigned int* image_in = image.array_in; 20 | unsigned int* image_out = image.array_out; 21 | 22 | HardcloudApp app(true); 23 | 24 | unsigned int *out_buf = (unsigned int*)app.alloc_buffer(size*sizeof(unsigned int)); 25 | unsigned int *in_buf = (unsigned int*)app.alloc_buffer(size*sizeof(unsigned int)); 26 | 27 | memcpy(in_buf, image_in, size*sizeof(unsigned int)); 28 | 29 | printf("allocation done\n"); 30 | 31 | struct timespec ts1, ts2; 32 | timespec_get(&ts1, TIME_UTC); 33 | app.run(); 34 | timespec_get(&ts2, TIME_UTC); 35 | 36 | double t = (ts2.tv_sec*1000000 + ts2.tv_nsec/1000) - (ts1.tv_sec*1000000 + ts1.tv_nsec/1000); 37 | 38 | printf("time: %lf ms\n", t/1000); 39 | printf("throughput: %lf fig/s\n", 1.0/(t/1000000)); 40 | 41 | memcpy(image_out, out_buf, size*sizeof(unsigned int)); 42 | 43 | image.map_back(); 44 | 45 | image.write_png_file(file_output); 46 | app.delete_buffer(in_buf); 47 | app.delete_buffer(out_buf); 48 | 49 | return 0; 50 | } 51 | 52 | -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/origin_test/output.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/d3-buffer-overflow-optimus/origin_test/output.png -------------------------------------------------------------------------------- /d3-buffer-overflow-optimus/rtl/grayscale.sv: -------------------------------------------------------------------------------- 1 | // grayscale.sv 2 | 3 | module grayscale 4 | ( 5 | input logic clk, 6 | input logic reset, 7 | input logic [511:0] data_in, 8 | input logic valid_in, 9 | output logic [511:0] data_out, 10 | output logic valid_out 11 | ); 12 | 13 | function [31:0] rgb2luma(input logic [31:0] data); 14 | logic [7:0] tmp; 15 | 16 | tmp = data[7:0] >> 2; 17 | tmp += data[7:0] >> 5; 18 | tmp += data[15:8] >> 1; 19 | tmp += data[15:8] >> 4; 20 | tmp += data[23:16] >> 4; 21 | tmp += data[23:16] >> 5; 22 | 23 | return {tmp, tmp, tmp}; 24 | endfunction : rgb2luma 25 | 26 | always_ff@(posedge clk or posedge reset) begin 27 | if (reset) begin 28 | valid_out <= 1'b0; 29 | end 30 | else begin 31 | valid_out <= valid_in; 32 | end 33 | end 34 | 35 | always_ff@(posedge clk or posedge reset) begin 36 | if (reset) begin 37 | data_out <= '0; 38 | end 39 | else begin 40 | for (int i = 0; i < 16; i++) begin 41 | data_out[32*i +: 32] <= rgb2luma(data_in[32*i +: 32]); 42 | end 43 | end 44 | end 45 | 46 | endmodule : grayscale 47 | 48 | -------------------------------------------------------------------------------- /d4-buffer-overflow-frame-fifo/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | fadd_test 6 | bug.v 7 | -------------------------------------------------------------------------------- /d4-buffer-overflow-frame-fifo/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d4-buffer-overflow-frame-fifo/n7.instrument.cfg: -------------------------------------------------------------------------------- 1 | # N7: buffer overflow in a frame fifo 2 | # step1 3 | # autocnt(s_axis_tlast) 4 | # autocnt(m_axis_tlast) 5 | autocnt \ 6 | --valid-signal axis_fifo_inst__DOT__s_axis:9 \ 7 | --valid-signal axis_fifo_inst__DOT__m_axis_reg:8 \ 8 | --tag debug_display_11 9 | 10 | # step2 11 | # signalcat(write) 12 | # signalcat(wr_addr_reg) 13 | 14 | output -o bug.v 15 | sv2v \ 16 | --tasksupport --tasksupport-mode=ILA \ 17 | --tasksupport-tags debug_display_11 \ 18 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 19 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 20 | --arrayboundcheck 21 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 22 | -------------------------------------------------------------------------------- /d4-buffer-overflow-frame-fifo/sources-sim.txt: -------------------------------------------------------------------------------- 1 | rtl/axis_fifo.v 2 | rtl/axis_fifo_wrapper.sv 3 | -------------------------------------------------------------------------------- /d4-buffer-overflow-frame-fifo/sources-veripass.txt: -------------------------------------------------------------------------------- 1 | rtl/axis_fifo.v 2 | rtl/axis_fifo_wrapper.sv 3 | -------------------------------------------------------------------------------- /d4-buffer-overflow-frame-fifo/sources.txt: -------------------------------------------------------------------------------- 1 | test.v 2 | ../common/xilinx/fakeila.sv 3 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | sha512_test 6 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/README.md: -------------------------------------------------------------------------------- 1 | # D5 - Bit Truncation - SHA512 2 | 3 | Code: https://github.com/efeslab/hardcloud/tree/e28ca96fdbb67904ef909fb04e026cf6dc724198/samples/sha512 4 | 5 | This bug occurs in the memory requestor of an SHA512 accelerator. CPU-side software configure the accelerator with the location of the data to be hashed by writing the address to the accelerator. Because the accelerator can only access memory at cacheline granularity, it needs to translate a normal memory address to a cacheline address by erasing both the least significant bits (because they must be 0) and the most significant bits (because they are not supported by the memory bus). 6 | 7 | Unfortunately, the accelerator performs a width conversion before doing the shift; as a result, some meaningful bits (i.e., bit 42-47) are erased. 8 | 9 | This bug would cause the accelerator to access an invalid address, thus triggering an IOMMU page fault which freezes the whole accelerator. 10 | 11 | ### Synthetic Code 12 | ``` verilog 13 | logic [41:0] left; 14 | logic [63:0] right; 15 | assign left = 42'(right) >> 6; 16 | ``` 17 | 18 | To fix the bug, simply change the third line to: 19 | 20 | ```verilog 21 | assign left = 42'(right >> 6); 22 | ``` 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/bug2.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug2: SHA512-BitTruncation 2 | # bug2_step1.1 3 | # fsm_update(rd_state) 4 | # fsm_update(wr_state) 5 | fsm \ 6 | -S ccip_std_afu__DOT__uu_sha512_requestor__DOT__rd_state:2:0 \ 7 | -S ccip_std_afu__DOT__uu_sha512_requestor__DOT__wr_state:2:0 \ 8 | --tag debug_display_2.1.1 9 | # bug2_step1.2 10 | # dep(rd_hdr.address, 1) 11 | # dep(wr_hdr.address, 1) 12 | deps \ 13 | --control --data \ 14 | --variable "ccip_std_afu__DOT__uu_sha512_requestor__DOT__rd_hdr:57:16" \ 15 | --variable "ccip_std_afu__DOT__uu_sha512_requestor__DOT__wr_hdr:57:16" \ 16 | --layer 1 \ 17 | --tag debug_display_2.1.2 18 | output -o bug2_step1.2.v 19 | sv2v \ 20 | --tasksupport --tasksupport-mode=STP \ 21 | --tasksupport-tags=debug_display_2.1.1 \ 22 | --tasksupport-tags=debug_display_2.1.2 \ 23 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 24 | --arrayboundcheck 25 | {% if SV2V_OUTPUT is defined %} 26 | output --not-retag-synthesis -o {{SV2V_OUTPUT}} 27 | {% else %} 28 | output --not-retag-synthesis -o withtask_bug2.v 29 | {% endif %} 30 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/ccip/platform_shims/README.md: -------------------------------------------------------------------------------- 1 | # Platform Shims 2 | 3 | Shims here are invoked by the top-level code that manages the partial reconfiguration 4 | boundary. Instead of directly instantiating an AFU (e.g. ccip_std_afu), these 5 | intermediate shims will be mapped first. The shims transform the interface and then 6 | connect to the AFU. **These shims and sub-directories are internal to the platform 7 | interface manager. Their interfaces or semantics may change from release to release.** 8 | 9 | Shims names are defined in the JSON field *platform-shim-module-name* in 10 | AFU top-level interface descriptions: [afu\_top\_ifc\_db](../../../afu_top_ifc_db/). 11 | 12 | Shims typically offer automatic clock crossing and automatic platform-specific 13 | register stage insertion to aid in timing closure. See the various instances of 14 | *clock* and *add-timing-reg-stages* in 15 | [platform\_defaults.json](../../../platform_db/platform_defaults.json). 16 | 17 | Some modules here are sub-shims, instantiated by larger shims. For example, 18 | platform\_shim\_ccip() manages only CCI-P clock crossing and register stage insertion. 19 | It is instantiated by platform\_shim\_ccip\_std\_afu(). 20 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/ccip/platform_shims/utils/quartus_ip/README: -------------------------------------------------------------------------------- 1 | This library is extracted from code in Quartus releases using gen_platform_ip.sh 2 | in this directory. Point the script at a Quartus release and it will do the rest. 3 | The module names are modified to make them unique, replacing the leading "altera" 4 | with "platform_utils". 5 | 6 | The SDC files are here instead of in a par directory to keep all the Qsys 7 | code together. 8 | 9 | Extracted components include: 10 | * Qsys Avalon-MM Clock Crossing Bridge 11 | * Qsys Avalon-MM Pipeline Bridge 12 | 13 | 14 | Note: copyrights should be changed to BSD/MIT licenses. 15 | -------------------------------------------------------------------------------- /d5-bit-truncation-sha512/ccip/platform_shims/utils/quartus_ip/platform_utils_dcfifo_synchronizer_bundle.v: -------------------------------------------------------------------------------- 1 | // $File: //acds/rel/18.0/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $ 2 | // $Revision: #1 $ 3 | // $Date: 2018/02/08 $ 4 | // $Author: psgswbuild $ 5 | //------------------------------------------------------------------------------- 6 | 7 | `timescale 1 ns / 1 ns 8 | module platform_utils_dcfifo_synchronizer_bundle( 9 | clk, 10 | reset_n, 11 | din, 12 | dout 13 | ); 14 | parameter WIDTH = 1; 15 | parameter DEPTH = 3; 16 | 17 | input clk; 18 | input reset_n; 19 | input [WIDTH-1:0] din; 20 | output [WIDTH-1:0] dout; 21 | 22 | genvar i; 23 | 24 | generate 25 | for (i=0; i/dev/null 2>/dev/null & 25 | 26 | # for resource-util synthesize 27 | TOP_MODULE_SYNTH=fft_wrapper 28 | TCLGEN_SRCS=vivado_synth/fft_wrapper.v 29 | SV2V_OUT_FILES+=withtask 30 | CODE_GEN+=withtask.v bug12.v 31 | 32 | withtask.v: ${RTL_SOURCES} bug12.instrument.cfg 33 | ${TOOLS} --top ${TOP_MODULE} -F ${RTL_SOURCES} --config bug12.instrument.cfg --reset "i_reset" 34 | 35 | DEPTH_SWEEP_PREFIX+=depth_sweep_bug12 36 | depth_sweep_bug12_d%.v: ${RTL_SOURCES} bug12.instrument.cfg 37 | ${TOOLS} --top ${TOP_MODULE} -F ${RTL_SOURCES} --config bug12.instrument.cfg --reset "!i_reset" --config-override="{\"LOG2_SAMPLE_DEPTH\":$*, \"SV2V_OUTPUT\":\"$@\", \"ILA_OUTPUT\":\"$(basename $@).ila.tcl\"}" 38 | include ../common/Makefile.ILA.rules 39 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/bug12.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug12: FFT-BitTruncation 2 | # manually insert display tasks (by jcma) 3 | output -o bug12.v 4 | sv2v \ 5 | --tasksupport --tasksupport-mode=ILA \ 6 | --tasksupport-tags debug_display_1\ 7 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 8 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 9 | --arrayboundcheck 10 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 11 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/hex/cmem_128.hex: -------------------------------------------------------------------------------- 1 | 4000000000 2 | 3fec4fcdc1 3 | 3fb12f9ba1 4 | 3f4ebf69bf 5 | 3ec53f383a 6 | 3e150f0730 7 | 3d3e8ed6c0 8 | 3c424ea706 9 | 3b20de7822 10 | 39dafe4a2f 11 | 38716e1d4a 12 | 36e50df18f 13 | 3536ddc719 14 | 3367cd9e01 15 | 31790d7662 16 | 2f6bcd5053 17 | 2d414d2bec 18 | 2afadd0944 19 | 2899ece870 20 | 261ffcc984 21 | 238e7cac93 22 | 20e71c91b0 23 | 1e2b6c78ea 24 | 1b5d1c6251 25 | 187dec4df3 26 | 158fac3bdc 27 | 12940c2c18 28 | 0f8d0c1eb0 29 | 0c7c6c13ad 30 | 09641c0b15 31 | 0645fc04ee 32 | 0323fc013c 33 | 00000c0000 34 | fcdc1c013c 35 | f9ba1c04ee 36 | f69bfc0b15 37 | f383ac13ad 38 | f0730c1eb0 39 | ed6c0c2c18 40 | ea706c3bdc 41 | e7822c4df3 42 | e4a2fc6251 43 | e1d4ac78ea 44 | df18fc91b0 45 | dc719cac93 46 | d9e01cc984 47 | d7662ce870 48 | d5053d0944 49 | d2becd2bec 50 | d0944d5053 51 | ce870d7662 52 | cc984d9e01 53 | cac93dc719 54 | c91b0df18f 55 | c78eae1d4a 56 | c6251e4a2f 57 | c4df3e7822 58 | c3bdcea706 59 | c2c18ed6c0 60 | c1eb0f0730 61 | c13adf383a 62 | c0b15f69bf 63 | c04eef9ba1 64 | c013cfcdc1 65 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/hex/cmem_16.hex: -------------------------------------------------------------------------------- 1 | 40000000000 2 | 3b20db9e087 3 | 2d413f4afb1 4 | 187de7137ca 5 | 00000300000 6 | e7821f137ca 7 | d2bec74afb1 8 | c4df2b9e087 9 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/hex/cmem_32.hex: -------------------------------------------------------------------------------- 1 | 40000000000 2 | 3ec533ce0e9 3 | 3b20db9e087 4 | 3536cf71c62 5 | 2d413f4afb1 6 | 238e7b2b24d 7 | 187de7137ca 8 | 0c7c5f04eb4 9 | 00000300000 10 | f383a704eb4 11 | e7821f137ca 12 | dc718b2b24d 13 | d2bec74afb1 14 | cac93771c62 15 | c4df2b9e087 16 | c13ad3ce0e9 17 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/hex/cmem_64.hex: -------------------------------------------------------------------------------- 1 | 10000000000 2 | 0fec47f3743 3 | 0fb14de7074 4 | 0f4fa1dad7f 5 | 0ec837cf044 6 | 0e1c5bc3a94 7 | 0d4db5b8e31 8 | 0c5e41aecc3 9 | 0b5051a57d8 10 | 0a267b9d0e0 11 | 08e39f95926 12 | 078ad98f1d3 13 | 061f7989be5 14 | 04a50385830 15 | 031f198275a 16 | 01917b809dd 17 | 00000180000 18 | 3e6e87809dd 19 | 3ce0e98275a 20 | 3b5aff85830 21 | 39e08989be5 22 | 3875298f1d3 23 | 371c6395926 24 | 35d9879d0e0 25 | 34afb1a57d8 26 | 33a1c1aecc3 27 | 32b24db8e31 28 | 31e3a7c3a94 29 | 3137cbcf044 30 | 30b061dad7f 31 | 304eb5e7074 32 | 3013bbf3743 33 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/hex/cmem_8.hex: -------------------------------------------------------------------------------- 1 | 100000000000 2 | 0b504f695f62 3 | 000000600000 4 | 34afb1695f62 5 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/instrument.cfg: -------------------------------------------------------------------------------- 1 | deps \ 2 | --variable "w_d128:33:0" \ 3 | --data \ 4 | --layer 5 \ 5 | --tag debug_display_2 6 | 7 | output -o fft.notask.v 8 | sv2v \ 9 | --tasksupport --tasksupport-mode=ILA \ 10 | --tasksupport-tags=debug_display_1 \ 11 | --tasksupport-tags=debug_display_2 12 | output --not-retag-synthesis -o fft.withtask.v 13 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/source.txt: -------------------------------------------------------------------------------- 1 | cores/bimpy.v 2 | cores/bitreverse.v 3 | cores/butterfly.v 4 | cores/convround.v 5 | cores/fftmain.v 6 | cores/fftstage.v 7 | cores/hwbfly.v 8 | cores/laststage.v 9 | cores/longbimpy.v 10 | cores/qtrstage.v 11 | cores/shiftaddmpy.v 12 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/test/.gitignore: -------------------------------------------------------------------------------- 1 | *.pass 2 | fft_tb 3 | -------------------------------------------------------------------------------- /d6-bit-truncation-fft/test/README.md: -------------------------------------------------------------------------------- 1 | Here are the bench tests for the pipelined FFT. In general, there's a 2 | `*_tb.cpp` file corresponding to every unit within the FFT. Feel free to 3 | try them. 4 | 5 | Be aware, however, the [fft_tb](fft_tb.cpp) doesn't truly 6 | check for success--I just haven't gotten to the point of verifying that 7 | the FFT result is *close enough* to the right answer in spite of actually 8 | calculating the right answer. Instead, it creates a data file that can be 9 | read in Octave via [fft_tb.m](fft_tb.m). That will show the first test output. 10 | The second and subsequent outputs can be read via `k=k+1;` followed by calling 11 | [plottst](plottst.m). 12 | 13 | As another note (before I clean things up more), you'll need the `*.hex` files 14 | in the same directory as the one you call [fft_tb](fft_tb.cpp) or 15 | [fftstage_tb](fftstage_tb.cpp) from. 16 | 17 | I expect the IFFT will work: it's just an FFT with conjugate twiddle factors, 18 | although I haven't fully tested it yet. 19 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | fadd_test 6 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/README.md: -------------------------------------------------------------------------------- 1 | # D7 - Misindexing - FADD 2 | 3 | A PhD student at University of Michigan reports this bug in one of his hardware project. 4 | 5 | This bug is in a simple floating point adder that's optimized for resource. The author uses the wrong index range to access the fraction, which causes the least significant bit of the exponent being treated as the most significant bit of the fraction, thus making the adder producing wrong results. 6 | 7 | The following code snippet shows the errorous code and the correct one. 8 | 9 | ### Code Snippet 10 | 11 | ```verilog 12 | // errorous code 13 | for(int i = 0; i < N-E; ++i) begin 14 | if(tmp_mant[N-E-i]) begin 15 | // Check for underflow 16 | if(i > tmp_exp) begin 17 | res_exp_next = 1; 18 | end else begin 19 | res_exp_next = tmp_exp - i; 20 | res_mant_next = tmp_mant[N-E-S:0] << i; 21 | end 22 | 23 | break; 24 | end 25 | end 26 | 27 | // correct code 28 | for(int i = 0; i < N-E-1; ++i) begin 29 | if(tmp_mant[N-E-1-i]) begin 30 | // Check for underflow 31 | if(i > tmp_exp) begin 32 | res_exp_next = 1; 33 | end else begin 34 | res_exp_next = tmp_exp - i; 35 | res_mant_next = tmp_mant[N-E-S-1:0] << i; 36 | end 37 | 38 | break; 39 | end 40 | end 41 | ``` 42 | 43 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/bug11.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug11: FADD-Misindexing 2 | # print(all_output) 3 | deps \ 4 | --variable "res_val:0:0" \ 5 | --variable "res:31:0" \ 6 | --layer 0 \ 7 | --tag debug_display_11 8 | 9 | output -o bug11.v 10 | sv2v \ 11 | --tasksupport --tasksupport-mode=ILA \ 12 | --tasksupport-tags debug_display_11 \ 13 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 14 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 15 | --arrayboundcheck 16 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 17 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/rtl/fadd.sv: -------------------------------------------------------------------------------- 1 | module fadd #(parameter N = 32, parameter E = 8, parameter S = 1) ( 2 | // Inputs 3 | input logic clk, 4 | input logic rst, 5 | input logic en, 6 | input logic [N-1:0] op1, 7 | input logic [N-1:0] op2, 8 | 9 | // Outputs 10 | output logic res_val_correct, 11 | output logic [N-1:0] res_correct, 12 | output logic res_val_buggy, 13 | output logic [N-1:0] res_buggy 14 | ); 15 | 16 | fadd_buggy buggy( 17 | .clk(clk), 18 | .rst(rst), 19 | .en(en), 20 | .op1(op1), 21 | .op2(op2), 22 | .res_val(res_val_buggy), 23 | .res(res_buggy) 24 | ); 25 | 26 | fadd_correct correct( 27 | .clk(clk), 28 | .rst(rst), 29 | .en(en), 30 | .op1(op1), 31 | .op2(op2), 32 | .res_val(res_val_correct), 33 | .res(res_correct) 34 | ); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/sources-sim.txt: -------------------------------------------------------------------------------- 1 | rtl/fadd.sv 2 | rtl/fadd_buggy.sv 3 | rtl/fadd_correct.sv 4 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/sources-veripass.txt: -------------------------------------------------------------------------------- 1 | rtl/fadd_buggy.sv 2 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/sources.txt: -------------------------------------------------------------------------------- 1 | test.v 2 | -------------------------------------------------------------------------------- /d7-misindexing-fadd/vivado_synth/fadd_wrapper.v: -------------------------------------------------------------------------------- 1 | module fadd_wrapper ( 2 | S_AXI_ACLK, 3 | S_AXI_ARESETN, 4 | S_AXI_AWADDR, 5 | S_AXI_AWPROT, 6 | S_AXI_AWVALID, 7 | S_AXI_AWREADY, 8 | S_AXI_WDATA, 9 | S_AXI_WSTRB, 10 | S_AXI_WVALID, 11 | S_AXI_WREADY, 12 | S_AXI_BRESP, 13 | S_AXI_BVALID, 14 | S_AXI_BREADY, 15 | S_AXI_ARADDR, 16 | S_AXI_ARPROT, 17 | S_AXI_ARVALID, 18 | S_AXI_ARREADY, 19 | S_AXI_RDATA, 20 | S_AXI_RRESP, 21 | S_AXI_RVALID, 22 | S_AXI_RREADY 23 | ); 24 | 25 | input wire S_AXI_ACLK; 26 | input wire S_AXI_ARESETN; 27 | input wire [6 : 0] S_AXI_AWADDR; 28 | input wire [2 : 0] S_AXI_AWPROT; 29 | input wire S_AXI_AWVALID; 30 | output wire S_AXI_AWREADY; 31 | input wire [31 : 0] S_AXI_WDATA; 32 | input wire [3 : 0] S_AXI_WSTRB; 33 | input wire S_AXI_WVALID; 34 | output wire S_AXI_WREADY; 35 | output wire [1 : 0] S_AXI_BRESP; 36 | output wire S_AXI_BVALID; 37 | input wire S_AXI_BREADY; 38 | input wire [6 : 0] S_AXI_ARADDR; 39 | input wire [2 : 0] S_AXI_ARPROT; 40 | input wire S_AXI_ARVALID; 41 | output wire S_AXI_ARREADY; 42 | output wire [31 : 0] S_AXI_RDATA; 43 | output wire [1 : 0] S_AXI_RRESP; 44 | output wire S_AXI_RVALID; 45 | input wire S_AXI_RREADY; 46 | 47 | fadd_buggy 48 | inst ( 49 | .clk(S_AXI_ACLK), 50 | .rst(!S_AXI_ARESETN), 51 | .en(S_AXI_AWVALID), 52 | .op1(S_AXI_WDATA), 53 | .op2(S_AXI_WDATA), 54 | .res_val(S_AXI_AWREADY), 55 | .res(S_AXI_RDATA) 56 | ); 57 | endmodule 58 | 59 | -------------------------------------------------------------------------------- /d8-misindexing-axis-switch/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.lxt 5 | test_axis_switch_4x4 -------------------------------------------------------------------------------- /d8-misindexing-axis-switch/README.md: -------------------------------------------------------------------------------- 1 | # D8 - Misindexing - AXI Stream Switch 2 | 3 | **Source:** Verilog-axis(Verilog AXI Stream Components): https://github.com/alexforencich/verilog-axis/commit/76c805e4167c1065db0a7cdec711b30c1e11da91#diff-09b0ecbe0779c53e7a28b0d57be6ca8bd2f6224a339902399abed42ee0338d57 4 | 5 | Bug type: Miss-indexing 6 | 7 | 8 | ### Synthetic Code 9 | ```verilog 10 | // Line 228 11 | assign int_s_axis_tready[m] = int_axis_tready[select_reg*M_COUNT+m] || drop_reg; //M_COUNT should be S_COUNT 12 | 13 | // Line 296 14 | wire s_axis_tvalid_mux = int_axis_tvalid[grant_encoded*S_COUNT+n] && grant_valid; //S_COUNT should be M_COUNT 15 | 16 | ``` 17 | -------------------------------------------------------------------------------- /d8-misindexing-axis-switch/instrument.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | withtask.v 3 | rtl/test_axis_fifo.v 4 | 5 | -------------------------------------------------------------------------------- /d8-misindexing-axis-switch/n4.instrument.cfg: -------------------------------------------------------------------------------- 1 | 2 | # bug_step1 3 | # print ready and valid signals 4 | deps \ 5 | --variable "s_axis_tvalid:3:0" \ 6 | --variable "s_axis_tready:3:0" \ 7 | --variable "m_axis_tvalid:0:0" \ 8 | --variable "m_axis_tready:0:0" \ 9 | --layer 0 \ 10 | --control --data \ 11 | --tag debug_display_1 12 | 13 | # we will see that the ready and valid signals are messed up, 14 | # it should be a problem of the mux inside the switch 15 | # bug_step2 16 | deps \ 17 | --variable "UUT__DOT__int_axis_tready:3:0" \ 18 | --layer 0 \ 19 | --control --data \ 20 | --tag debug_display_2 21 | 22 | output -o bug.v 23 | 24 | sv2v \ 25 | --tasksupport --tasksupport-mode=ILA \ 26 | --tasksupport-tags=debug_display_1 \ 27 | --tasksupport-tags=debug_display_2 \ 28 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 29 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 30 | --arrayboundcheck 31 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 32 | -------------------------------------------------------------------------------- /d8-misindexing-axis-switch/sources-veripass.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/axis_switch.v 3 | rtl/axis_register.v 4 | rtl/arbiter.v 5 | rtl/priority_encoder.v 6 | rtl/axis_switch_4x1.v 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /d8-misindexing-axis-switch/sources.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/axis_switch.v 3 | rtl/axis_register.v 4 | rtl/arbiter.v 5 | rtl/priority_encoder.v 6 | rtl/test_axis_switch_4x1.v 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /d9-endianness-mismatch-sdspi/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *.img 6 | sdspi_tb 7 | -------------------------------------------------------------------------------- /d9-endianness-mismatch-sdspi/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d9-endianness-mismatch-sdspi/bench/cpp/.gitignore: -------------------------------------------------------------------------------- 1 | *.vcd 2 | sdcard.img 3 | -------------------------------------------------------------------------------- /d9-endianness-mismatch-sdspi/bench/cpp/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /d9-endianness-mismatch-sdspi/bug10.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug10: SDSPI-deadlock 2 | # print(all_output) 3 | deps \ 4 | --variable "o_wb_ack:0:0" \ 5 | --variable "o_wb_stall:0:0" \ 6 | --variable "o_wb_data:31:0" \ 7 | --variable "o_cs_n:0:0" \ 8 | --variable "o_sck:0:0" \ 9 | --variable "o_mosi:0:0" \ 10 | --variable "o_int:0:0" \ 11 | --layer 0 \ 12 | --tag debug_display_10 13 | 14 | output -o bug10.v 15 | sv2v \ 16 | --tasksupport --tasksupport-mode=ILA \ 17 | --tasksupport-tags debug_display_10 \ 18 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 19 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 20 | --arrayboundcheck 21 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 22 | -------------------------------------------------------------------------------- /d9-endianness-mismatch-sdspi/sources.txt: -------------------------------------------------------------------------------- 1 | rtl/llsdspi.v 2 | rtl/sdspi.v 3 | -------------------------------------------------------------------------------- /manual_debug_log/used_tools.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/efeslab/hardware-bugbase/7702e478f4ffdca477273d5a395992ecf006d70f/manual_debug_log/used_tools.xlsx -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *_test 6 | *_work 7 | *.tcl 8 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/README.md: -------------------------------------------------------------------------------- 1 | # S1 - Protocol Violation - AXI-Lite 2 | 3 | Source: https://zipcpu.com/formal/2018/12/28/axilite.html 4 | 5 | This bug is from Xilinx's official demostrative AXI-Lite implementation provided in Vivado. It's first found by [ZipCPU](https://zipcpu.com), who provides a detailed description and analysis in the link above. 6 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/bug6.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug6: AXI-Lite-DropAck 2 | # printf(all control inputs) 3 | deps \ 4 | --variable "S_AXI_AWADDR:6:0" \ 5 | --variable "S_AXI_AWPROT:2:0" \ 6 | --variable "S_AXI_AWVALID:0:0" \ 7 | --variable "S_AXI_WSTRB:3:0" \ 8 | --variable "S_AXI_WVALID:0:0" \ 9 | --variable "S_AXI_BREADY:0:0" \ 10 | --variable "S_AXI_ARADDR:6:0" \ 11 | --variable "S_AXI_ARPROT:2:0" \ 12 | --variable "S_AXI_ARVALID:0:0" \ 13 | --variable "S_AXI_RREADY:0:0" \ 14 | --layer 0 \ 15 | --tag debug_display_6 16 | output -o bug6.v 17 | sv2v \ 18 | --tasksupport --tasksupport-mode=ILA \ 19 | --tasksupport-tags debug_display_6 \ 20 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 21 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 22 | --arrayboundcheck 23 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 24 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/rtl/bugfix.patch: -------------------------------------------------------------------------------- 1 | diff --git a/xilinx-axi-lite-incomplete-implementation/rtl/xlnxdemo.v b/xilinx-axi-lite-incomplete-implementation/rtl/xlnxdemo.v 2 | index ee19767..5c61a61 100644 3 | --- a/xilinx-axi-lite-incomplete-implementation/rtl/xlnxdemo.v 4 | +++ b/xilinx-axi-lite-incomplete-implementation/rtl/xlnxdemo.v 5 | @@ -192,7 +192,7 @@ module xlnxdemo # 6 | end 7 | else 8 | begin 9 | - if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) 10 | + if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && (!S_AXI_BVALID || S_AXI_BREADY)) 11 | begin 12 | // slave is ready to accept write address when 13 | // there is a valid write address and write data 14 | @@ -240,7 +240,7 @@ module xlnxdemo # 15 | end 16 | else 17 | begin 18 | - if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID) 19 | + if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && (!S_AXI_BVALID || S_AXI_BREADY)) 20 | begin 21 | // slave is ready to accept write data when 22 | // there is a valid write address and write data 23 | @@ -617,7 +617,7 @@ module xlnxdemo # 24 | end 25 | else 26 | begin 27 | - if (~axi_arready && S_AXI_ARVALID) 28 | + if (~axi_arready && S_AXI_ARVALID && (!S_AXI_RVALID || S_AXI_RREADY)) 29 | begin 30 | // indicates that the slave has acceped the valid read address 31 | axi_arready <= 1'b1; 32 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/rtl/xlnxdemo.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | cvr 3 | prf 4 | 5 | [options] 6 | cvr: mode cover 7 | cvr: depth 60 8 | prf: mode prove 9 | prf: depth 40 10 | 11 | [engines] 12 | smtbmc 13 | 14 | [script] 15 | read -formal xlnxdemo.v 16 | read -formal faxil_slave.v 17 | prep -top xlnxdemo 18 | 19 | [files] 20 | xlnxdemo.v 21 | faxil_slave.v 22 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/sources.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/faxil_slave.v 3 | rtl/xlnxdemo.v 4 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/sources0.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/faxil_slave.v 3 | rtl/trace_tb0.v 4 | rtl/xlnxdemo.v 5 | -------------------------------------------------------------------------------- /s1-protocol-violation-axi-lite/sources1.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/faxil_slave.v 3 | rtl/trace_tb1.v 4 | rtl/xlnxdemo.v 5 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *_test 6 | *_work 7 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/.gtkwaverc: -------------------------------------------------------------------------------- 1 | hier_max_level 99 2 | splash_disable 1 3 | highlight_wavewindow 1 4 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/README.md: -------------------------------------------------------------------------------- 1 | # S2 - Protocol Violation - AXI-Stream 2 | 3 | Source: https://zipcpu.com/dsp/2020/04/20/axil2axis.html 4 | 5 | This bug is from Xilinx's official demostrative AXI-Stream implementation provided in Vivado. It's first found by [ZipCPU](https://zipcpu.com), who provides a detailed description and analysis in the link above. 6 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/bug7.instrument.cfg: -------------------------------------------------------------------------------- 1 | # bug7: AXI-Stream-Incorrect-Last 2 | # printf(all control inputs) 3 | deps \ 4 | --variable "M_AXIS_TVALID:0:0" \ 5 | --variable "M_AXIS_TREADY:0:0" \ 6 | --variable "M_AXIS_TLAST:0:0" \ 7 | --layer 0 \ 8 | --tag debug_display_7 9 | output -o bug7.v 10 | sv2v \ 11 | --tasksupport --tasksupport-mode=ILA \ 12 | --tasksupport-tags debug_display_7 \ 13 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 14 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 15 | --arrayboundcheck 16 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 17 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/rtl/bugfix.patch: -------------------------------------------------------------------------------- 1 | diff --git a/xilinx-axi-stream-incomplete-implementation/rtl/xlnxstream_2018_3.v b/xilinx-axi-stream-incomplete-implementation/rtl/xlnxstream_2018_3.v 2 | index 2887e6b..92798b4 100644 3 | --- a/xilinx-axi-stream-incomplete-implementation/rtl/xlnxstream_2018_3.v 4 | +++ b/xilinx-axi-stream-incomplete-implementation/rtl/xlnxstream_2018_3.v 5 | @@ -185,7 +185,8 @@ module xlnxstream_2018_3 # 6 | axis_tlast_delay <= 1'b0; 7 | end else begin 8 | axis_tvalid_delay <= axis_tvalid; 9 | - axis_tlast_delay <= axis_tlast; 10 | + if (!axis_tvalid_delay || M_AXIS_TREADY) 11 | + axis_tlast_delay <= axis_tlast; 12 | end 13 | 14 | 15 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/rtl/xlnxstream_2018_3.sby: -------------------------------------------------------------------------------- 1 | [tasks] 2 | prf 3 | cvr 4 | 5 | [options] 6 | prf: mode prove 7 | prf: depth 120 8 | prf: expect FAIL 9 | cvr: mode cover 10 | cvr: depth 60 11 | 12 | [engines] 13 | smtbmc 14 | 15 | [script] 16 | read -formal faxis_master.v 17 | read -formal xlnxstream_2018_3.v 18 | prep -top xlnxstream_2018_3 19 | chformal -assert -skip 2 20 | 21 | [files] 22 | faxis_master.v 23 | xlnxstream_2018_3.v 24 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/sources.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/faxis_master.v 3 | rtl/xlnxstream_2018_3.v 4 | -------------------------------------------------------------------------------- /s2-protocol-violation-axi-stream/sources0.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/faxis_master.v 3 | rtl/trace_tb.v 4 | rtl/xlnxstream_2018_3.v 5 | -------------------------------------------------------------------------------- /s3-incomplete-implementation-axis-adapter/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | *.fst.hier 3 | *.fst 4 | *.vcd 5 | *.lxt 6 | test_axis_adapter_64_8 7 | -------------------------------------------------------------------------------- /s3-incomplete-implementation-axis-adapter/instrument.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | withtask.v 3 | rtl/test_axis_adapter_64_8.v 4 | 5 | -------------------------------------------------------------------------------- /s3-incomplete-implementation-axis-adapter/n8.instrument.cfg: -------------------------------------------------------------------------------- 1 | 2 | # bug_step1 3 | deps \ 4 | --variable "output_axis_tlast_int:0:0" \ 5 | --variable "input_axis_tlast:0:0" \ 6 | --variable "input_axis_tkeep:7:0" \ 7 | --layer 0 \ 8 | --tag debug_display_1 9 | output -o bug.v 10 | 11 | 12 | sv2v \ 13 | --tasksupport --tasksupport-mode=ILA \ 14 | --tasksupport-tags=debug_display_1 \ 15 | --tasksupport-ila-tcl={{ILA_OUTPUT|default("withtask.ila.tcl")}} \ 16 | {% if LOG2_SAMPLE_DEPTH is defined %} --tasksupport-log2depth={{LOG2_SAMPLE_DEPTH}} {% endif %} \ 17 | --arrayboundcheck 18 | output --not-retag-synthesis -o {{SV2V_OUTPUT|default("withtask.v")}} 19 | -------------------------------------------------------------------------------- /s3-incomplete-implementation-axis-adapter/sources-veripass.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/axis_adapter.v 3 | 4 | 5 | 6 | 7 | 8 | -------------------------------------------------------------------------------- /s3-incomplete-implementation-axis-adapter/sources.txt: -------------------------------------------------------------------------------- 1 | +define+FORMAL 2 | rtl/axis_adapter.v 3 | rtl/test_axis_adapter_64_8.v 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /scripts/signaltap_util/README.txt: -------------------------------------------------------------------------------- 1 | report_util.py 2 | Report resource utilization of given synthesize directories (the one you run 3 | `run.sh`). 4 | 5 | report_sweep.py 6 | Report resource utilization of synthesize directories for configuration space 7 | sweeping. 8 | 9 | sweep.sh 10 | Generate verilog files and makefile targets for configuration space sweeping. 11 | -------------------------------------------------------------------------------- /scripts/signaltap_util/report_util.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import argparse 3 | from utils import report_dir_summary 4 | 5 | parser = argparse.ArgumentParser(description="Print Resource Util of skx_pr_afu.fit.summary in given synth directories") 6 | parser.add_argument('dirs', nargs='+', help="synth directories") 7 | args = parser.parse_args() 8 | 9 | for d in args.dirs: 10 | report_dir_summary(d) 11 | -------------------------------------------------------------------------------- /scripts/signaltap_util/sweep.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Usage: 3 | # 1. Generate sweep configurations 4 | # ./sweep.sh gen 5 | # 2. Generate makefile targets 6 | # ./sweep.sh make > jobs.txt 7 | # parallel -j 10 < jobs.txt 8 | # 3. Check missing resource util reports of sweep configurations 9 | # NOTE: designed to sweep based on sha512 10 | sweep() { 11 | func=$1 12 | for w in `seq 5 11`; do 13 | for d in `seq 10 13`; do 14 | $func $w $d 15 | done 16 | done 17 | } 18 | gen() { 19 | ${HOME}/FPGA/veripass/tools.py --top ccip_std_afu_wrapper -F sources.txt -o sweep_w${w}_d${d}.v sv2v --tasksupport --tasksupport-mode=SWEEPSTP --tasksupport-log2width ${w} --tasksupport-log2depth ${d} 20 | } 21 | make() { 22 | w=$1 23 | d=$2 24 | echo make build_sweep_w${w}_d${d} 25 | } 26 | check() { 27 | w=$1 28 | d=$2 29 | build_dir=build_sweep_w${w}_d${d} 30 | if [ ! -f $build_dir/build/output_files/skx_pr_afu.fit.summary ]; then 31 | echo "skx_pr_afu.fit.summary not found in" $build_dir 32 | fi 33 | } 34 | 35 | case $1 in 36 | gen) 37 | sweep gen ;; 38 | make) 39 | sweep make;; 40 | check) 41 | sweep check ;; 42 | *) echo "${0} gen|check" 43 | esac 44 | -------------------------------------------------------------------------------- /scripts/signaltap_util/utils.py: -------------------------------------------------------------------------------- 1 | import re 2 | import os 3 | MATCH_RULES = { 4 | 'ALM': r'Logic utilization \(in ALMs\) : ([0-9,]+)', 5 | 'FFs': r'Total registers : ([0-9]+)', 6 | 'BRAMbit' : r'Total block memory bits : ([0-9,]+)', 7 | 'BRAM#B' : r'Total RAM Blocks : ([0-9,]+)', 8 | } 9 | 10 | def get_sorted_keys(): 11 | return sorted(MATCH_RULES.keys()) 12 | 13 | """ 14 | Return : {str -> int} 15 | Dict keys are the same as the above MATCH_RULES 16 | """ 17 | def analyse_summary(summary: str): 18 | result = {} 19 | for key, rule in MATCH_RULES.items(): 20 | m = re.findall(rule, summary) 21 | assert(len(m) == 1) 22 | result[key] = int(m[0].replace(',', '')) 23 | return result 24 | 25 | def analyse_dir_summary(dirname: str): 26 | fit_summary = os.path.join(dirname, 'build', 'output_files', 'skx_pr_afu.fit.summary') 27 | if not os.path.exists(fit_summary): 28 | return None 29 | with open(fit_summary, 'r') as f: 30 | summary = f.read() 31 | return analyse_summary(summary) 32 | 33 | def report_dir_summary(dirname: str): 34 | res = analyse_dir_summary(dirname) 35 | if res: 36 | keys = get_sorted_keys() 37 | print("{}: {}".format(dirname, ' '.join(keys))) 38 | print(';'.join([str(res[x]) for x in keys])) 39 | else: 40 | print("Cannot find skx_pr_afu.fit.summary in {}".format(dirname)) 41 | -------------------------------------------------------------------------------- /scripts/xilinxila_util/report_util.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | import argparse 3 | from utils import report_dir_summary 4 | 5 | parser = argparse.ArgumentParser(description="Print Resource Util of xilinx implementation results") 6 | parser.add_argument('--instance', type=str, default=None, help="Report the overhead of what instance in the circuit? (by default do not match") 7 | parser.add_argument('--module', type=str, default=None, help="Report the overhead of what module in the circuit? (by default do not match") 8 | parser.add_argument('dirs', nargs='+', help="synthesis directories") 9 | args = parser.parse_args() 10 | 11 | if not (args.instance or args.module): 12 | parser.error("Need to match at least one of instance name or module name") 13 | 14 | for d in args.dirs: 15 | report_dir_summary(d, args.instance, args.module) 16 | -------------------------------------------------------------------------------- /scripts/xilinxila_util/sweep.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # Usage: 3 | # 1. Generate sweep configurations 4 | # ./sweep.sh gen 5 | # 2. Generate makefile targets 6 | # ./sweep.sh make > jobs.txt 7 | # parallel -j 10 < jobs.txt 8 | # 3. Check missing resource util reports of sweep configurations 9 | # NOTE: designed to sweep based on xilinx-axi-lite-incomplete-implementation 10 | sweep() { 11 | func=$1 12 | for w in `seq 5 10`; do 13 | for d in `seq 10 13`; do 14 | $func $w $d 15 | done 16 | done 17 | } 18 | gen() { 19 | w=$1 20 | d=$2 21 | name=sweep_w${w}_d${d} 22 | ${HOME}/FPGA/veripass/tools.py --top xlnxdemo -F sources.txt --reset "!S_AXI_ARESETN" -o ${name}.v sv2v --tasksupport --tasksupport-mode=SWEEPILA --tasksupport-log2width ${w} --tasksupport-log2depth ${d} --tasksupport-ila-tcl=${name}.ila.tcl 23 | } 24 | make() { 25 | w=$1 26 | d=$2 27 | name=sweep_w${w}_d${d} 28 | echo make build_${name} 29 | } 30 | check() { 31 | w=$1 32 | d=$2 33 | name=sweep_w${w}_d${d} 34 | build_dir=build_${name} 35 | rpt=build_${name}.util.rpt 36 | if [ ! -f $build_dir/${rpt} ]; then 37 | echo "${rpt} not found in" $build_dir 38 | fi 39 | } 40 | 41 | case $1 in 42 | gen) 43 | sweep gen ;; 44 | make) 45 | sweep make ;; 46 | check) 47 | sweep check ;; 48 | *) echo "${0} gen|check" 49 | esac 50 | --------------------------------------------------------------------------------