├── .travis.yml ├── Makefile ├── README.md ├── build └── .gitkeep ├── makebin ├── makebin.sh └── prepend_header.sh ├── sdk ├── lib │ ├── hal_sdr_controller.o │ ├── lib_platform.a │ └── startup.o ├── scripts │ ├── export-rom.txt │ └── rlx8195a.ld └── src │ ├── sw │ ├── lib │ │ └── sw_lib │ │ │ └── mbed │ │ │ ├── hal │ │ │ ├── analogin_api.h │ │ │ ├── analogout_api.h │ │ │ ├── gpio_api.h │ │ │ ├── gpio_irq_api.h │ │ │ ├── i2c_api.h │ │ │ ├── pinmap.h │ │ │ ├── pwmout_api.h │ │ │ ├── serial_api.h │ │ │ ├── spi_api.h │ │ │ └── us_ticker_api.h │ │ │ └── targets │ │ │ └── hal │ │ │ └── rtl8195a │ │ │ ├── PeripheralNames.h │ │ │ ├── PinNames.h │ │ │ ├── PortNames.h │ │ │ ├── device.h │ │ │ └── objects.h │ └── os │ │ ├── basic_types.h │ │ ├── platform_options.h │ │ └── section_config.h │ └── targets │ ├── cmsis │ ├── core_cm3.h │ ├── core_cmFunc.h │ ├── core_cmInstr.h │ └── target_rtk │ │ └── target_8195a │ │ ├── app_start.c │ │ ├── cmsis.h │ │ ├── cmsis_nvic.h │ │ └── diag.h │ └── hal │ └── target_rtk │ └── target_8195a │ ├── hal_adc.h │ ├── hal_api.h │ ├── hal_dac.h │ ├── hal_diag.h │ ├── hal_efuse.h │ ├── hal_gdma.h │ ├── hal_gpio.h │ ├── hal_i2c.h │ ├── hal_i2s.h │ ├── hal_irqn.h │ ├── hal_misc.h │ ├── hal_peri_on.h │ ├── hal_pinmux.h │ ├── hal_platform.h │ ├── hal_pwm.h │ ├── hal_sdr_controller.c │ ├── hal_spi_flash.h │ ├── hal_ssi.h │ ├── hal_timer.h │ ├── hal_uart.h │ ├── hal_util.h │ ├── hal_vector_table.h │ └── rtl8195a │ ├── rtl8195a.h │ ├── rtl8195a_adc.h │ ├── rtl8195a_dac.h │ ├── rtl8195a_gdma.h │ ├── rtl8195a_gpio.h │ ├── rtl8195a_i2c.h │ ├── rtl8195a_i2s.h │ ├── rtl8195a_peri_on.h │ ├── rtl8195a_pwm.h │ ├── rtl8195a_spi_flash.h │ ├── rtl8195a_ssi.h │ ├── rtl8195a_sys_on.h │ ├── rtl8195a_timer.h │ └── rtl8195a_uart.h └── src └── main.c /.travis.yml: -------------------------------------------------------------------------------- 1 | 2 | language: c 3 | 4 | matrix: 5 | fast_finish: true 6 | include: 7 | - os: linux 8 | sudo: false 9 | env: GCC_VER=4.8 10 | - os: linux 11 | sudo: false 12 | env: GCC_VER=4.9 13 | - os: linux 14 | sudo: false 15 | env: GCC_VER=5.0 16 | 17 | addons: 18 | apt: 19 | packages: 20 | - libc6-i386 21 | 22 | before_install: 23 | - if [ "${TRAVIS_OS_NAME}" = "linux" ]; then 24 | pushd . 25 | && cd ~ && mkdir gcc && cd gcc 26 | && if [ "$GCC_VER" = "4.8" ]; then GCC_URL="https://launchpadlibrarian.net/186124160/gcc-arm-none-eabi-4_8-2014q3-20140805-linux.tar.bz2" ; fi 27 | && if [ "$GCC_VER" = "4.9" ]; then GCC_URL="https://launchpad.net/gcc-arm-embedded/4.9/4.9-2015-q3-update/+download/gcc-arm-none-eabi-4_9-2015q3-20150921-linux.tar.bz2" ; fi 28 | && if [ "$GCC_VER" = "5.0" ]; then GCC_URL="https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q1-update/+download/gcc-arm-none-eabi-5_3-2016q1-20160330-linux.tar.bz2" ; fi 29 | && wget -O gcc.tar.bz2 ${GCC_URL} 30 | && tar -jxf gcc.tar.bz2 --strip 1 31 | && exportline="export PATH=\$HOME/gcc/bin:\$PATH" 32 | && if grep -Fxq "$exportline" ~/.profile; then echo nothing to do ; else echo $exportline >> ~/.profile; fi 33 | && . ~/.profile 34 | && popd 35 | ; 36 | fi 37 | 38 | before_script: 39 | - arm-none-eabi-gcc --version 40 | 41 | script: 42 | - make 43 | 44 | notifications: 45 | email: false 46 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | .SUFFIXES: .o .a .c .s 2 | 3 | DEV_NUL=/dev/null 4 | 5 | CHIP=ameba 6 | 7 | RM=rm -f 8 | 9 | CROSS_COMPILE = arm-none-eabi- 10 | AR = $(CROSS_COMPILE)ar 11 | CC = $(CROSS_COMPILE)gcc 12 | CPP = $(CROSS_COMPILE)g++ 13 | AS = $(CROSS_COMPILE)as 14 | NM = $(CROSS_COMPILE)nm 15 | SIZE = $(CROSS_COMPILE)size 16 | 17 | SDK_SRC_BASE_PATH = sdk/src 18 | 19 | vpath %.c ./src 20 | vpath %.c $(SDK_SRC_BASE_PATH)/targets/hal/target_rtk/target_8195a 21 | vpath %.c $(SDK_SRC_BASE_PATH)/targets/cmsis/target_rtk/target_8195a 22 | vpath %.cc ./src 23 | 24 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/targets/cmsis 25 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/targets/cmsis/target_rtk/target_8195a 26 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/targets/hal/target_rtk/target_8195a 27 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/targets/hal/target_rtk/target_8195a/rtl8195a 28 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/sw/lib/sw_lib/mbed/hal 29 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/sw/lib/sw_lib/mbed/targets/hal/rtl8195a/ 30 | INCLUDES += -I$(SDK_SRC_BASE_PATH)/sw/os 31 | 32 | OUTPUT_PATH=build 33 | 34 | CFLAGS = -g -mcpu=cortex-m3 35 | CFLAGS += -mthumb 36 | CFLAGS += -c -nostartfiles -fno-short-enums 37 | CFLAGS += -Wall -Wpointer-arith -Wstrict-prototypes -Wundef 38 | CFLAGS += -Wno-write-strings 39 | CFLAGS += -MMD -MP 40 | CFLAGS += -fno-common -fmessage-length=0 -fno-exceptions 41 | CFLAGS += -ffunction-sections -fdata-sections 42 | CFLAGS += -fomit-frame-pointer 43 | CFLAGS += -std=gnu99 44 | CFLAGS += -O2 $(INCLUDES) -D$(CHIP) 45 | 46 | CPPFLAGS = -g -mcpu=cortex-m3 47 | CPPFLAGS += -mthumb 48 | CPPFLAGS += -c -nostartfiles -fno-short-enums 49 | CPPFLAGS += -Wall -Wpointer-arith -Wundef 50 | CPPFLAGS += -Wno-write-strings 51 | CPPFLAGS += -MMD -MP 52 | CPPFLAGS += -fno-common -fmessage-length=0 -fno-exceptions 53 | CPPFLAGS += -ffunction-sections -fdata-sections 54 | CPPFLAGS += -fomit-frame-pointer 55 | CPPFLAGS += -O2 $(INCLUDES) -D$(CHIP) 56 | 57 | 58 | ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -a -g $(INCLUDES) 59 | 60 | ifeq ($(SDRAM), true) 61 | else 62 | C_SRC+=$(wildcard $(SDK_SRC_BASE_PATH)/targets/hal/target_rtk/target_8195a/hal_sdr_controller.c) 63 | endif 64 | C_SRC+=$(wildcard $(SDK_SRC_BASE_PATH)/targets/cmsis/target_rtk/target_8195a/app_start.c) 65 | C_SRC+=$(wildcard src/*.c) 66 | CPP_SRC=$(wildcard src/*.cc) 67 | 68 | C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC))) 69 | CPP_OBJ_TEMP=$(patsubst %.cc, %.o, $(notdir $(CPP_SRC))) 70 | 71 | # during development, remove some files 72 | C_OBJ_FILTER= 73 | CPP_OBJ_FILTER= 74 | 75 | C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP)) 76 | CPP_OBJ=$(filter-out $(CPP_OBJ_FILTER), $(CPP_OBJ_TEMP)) 77 | 78 | ELF_FLAGS= -O2 -Wl,--gc-sections -mcpu=cortex-m3 -mthumb --specs=nano.specs 79 | ELF_FLAGS+= -Lsdk/lib -Lsdk/scripts -Tsdk/scripts/rlx8195a.ld -Wl,-Map=$(OUTPUT_PATH)/target.map 80 | ELF_FLAGS+= -Wl,--cref -Wl,--gc-sections -Wl,--entry=Reset_Handler -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--no-enum-size-warning 81 | 82 | ifeq ($(SDRAM), true) 83 | ELF_LDLIBS= sdk/lib/startup.o sdk/lib/hal_sdr_controller.o -l_platform -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys 84 | else 85 | ELF_LDLIBS= sdk/lib/startup.o -l_platform -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys 86 | endif 87 | 88 | all: makebin/ram_all.bin 89 | 90 | makebin/ram_all.bin: $(OUTPUT_PATH)/target.axf 91 | cd ./makebin && /bin/bash ./makebin.sh 92 | 93 | $(OUTPUT_PATH)/target.axf: $(addprefix $(OUTPUT_PATH)/,$(C_OBJ)) $(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)) 94 | echo build all objects 95 | $(CC) $(ELF_FLAGS) -o $(OUTPUT_PATH)/target.axf -Wl,--start-group $^ -Wl,--end-group $(ELF_LDLIBS) 96 | $(SIZE) $(OUTPUT_PATH)/target.axf 97 | 98 | $(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c 99 | @echo "$(CC) -c $(CFLAGS) $< -o $@" 100 | @"$(CC)" -c $(CFLAGS) $< -o $@ 101 | 102 | $(addprefix $(OUTPUT_PATH)/,$(CPP_OBJ)): $(OUTPUT_PATH)/%.o: %.cc 103 | @echo "$(CPP) -c $(CPPFLAGS) $< -o $@" 104 | @"$(CPP)" -c $(CPPFLAGS) $< -o $@ 105 | 106 | clean: 107 | @echo clean 108 | -@$(RM) $(OUTPUT_PATH)/target.* 1>$(DEV_NUL) 2>&1 109 | -@$(RM) $(OUTPUT_PATH)/*.d 1>$(DEV_NUL) 2>&1 110 | -@$(RM) $(OUTPUT_PATH)/*.o 1>$(DEV_NUL) 2>&1 111 | -@$(RM) $(OUTPUT_PATH)/*.i 1>$(DEV_NUL) 2>&1 112 | -@$(RM) $(OUTPUT_PATH)/*.s 1>$(DEV_NUL) 2>&1 113 | -@$(RM) ./makebin/target* 1>$(DEV_NUL) 2>&1 114 | -@$(RM) ./makebin/*.bin 1>$(DEV_NUL) 2>&1 115 | 116 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # rtl_ameba_gcc_sample 2 | 3 | Realtek ameba gcc build environment 4 | 5 | * os : linux 6 | * toolchan : arm-eabi-none-gcc 7 | 8 | # usage 9 | 10 | ``` 11 | $ make 12 | ... 13 | genrate makebin/ram_all.bin 14 | ``` 15 | 16 | * When use SDRAM (for RTL8195AM or RTL8711AM) 17 | 18 | ``` 19 | $ make SDRAM=true 20 | ... 21 | genrate makebin/ram_all.bin 22 | ``` 23 | 24 | program ram_all.bin to ameba. ( [Programming the RTL8710 via DAP](https://github.com/eggman/RTL8710_DOC/blob/master/ProgrammingRTL8710.md) ) 25 | 26 | 27 | 28 | 29 | # support chips 30 | * RTL8195AM 31 | * RTL8711AM 32 | * RTL8711AF 33 | * RTL8710AF 34 | 35 | # features 36 | ## support 37 | * UART 38 | * GPIO 39 | * I2C 40 | * SPI 41 | * FLASH 42 | * PWM 43 | * Timer 44 | * ADC (RTL8195AM only) 45 | * DAC (RTL8195AM only) 46 | * SDRAM (RTL8195AM and RTL8711AM only) 47 | * I2S (only HAL support) 48 | 49 | ## not support 50 | * Wi-Fi 51 | * USB OTG 52 | * Ethernet 53 | * SDIO Host 54 | * SDIO Device 55 | * NFC 56 | 57 | Features depend on sdk/lib/lib_platform.a . 58 | 59 | # other 60 | 61 | This environment is based on https://github.com/neojou/arm-gcc-blink-example 62 | -------------------------------------------------------------------------------- /build/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eggman/rtl_ameba_gcc_sample/d5d2f9294a7e66641f75f699e051a31ab14c0f97/build/.gitkeep -------------------------------------------------------------------------------- /makebin/makebin.sh: -------------------------------------------------------------------------------- 1 | ###!/bin/bash 2 | 3 | TOOLCHAIN=arm-none-eabi 4 | 5 | 6 | chr() { 7 | [ ${1} -lt 256 ] || return 1 8 | printf \\$(printf '%03o' $1) 9 | } 10 | 11 | # Another version doing the octal conversion with arithmetic 12 | # faster as it avoids a subshell 13 | chr () { 14 | [ ${1} -lt 256 ] || return 1 15 | printf \\$(($1/64*100+$1%64/8*10+$1%8)) 16 | } 17 | 18 | # Another version using a temporary variable to avoid subshell. 19 | # This one requires bash 3.1. 20 | chr() { 21 | local tmp 22 | [ ${1} -lt 256 ] || return 1 23 | printf -v tmp '%03o' "$1" 24 | printf \\"$tmp" 25 | } 26 | 27 | 28 | ord() { 29 | LC_CTYPE=C printf '%d' "'$1" 30 | } 31 | 32 | 33 | SOURCE="${BASH_SOURCE[0]}" 34 | 35 | # resolve $SOURCE until the file is no longer a symlink 36 | # if $SOURCE was a relative symlink, we need to resolve it relative to the path where the symlink file was located 37 | 38 | while [ -h "$SOURCE" ]; do 39 | TARGET="$(readlink "$SOURCE")" 40 | if [[ $SOURCE == /* ]]; then 41 | # echo "SOURCE '$SOURCE' is an absolute symlink to '$TARGET'" 42 | SOURCE="$TARGET" 43 | else 44 | DIR="$( dirname "$SOURCE" )" 45 | # echo "SOURCE '$SOURCE' is a relative symlink to '$TARGET' (relative to '$DIR')" 46 | SOURCE="$DIR/$TARGET" 47 | fi 48 | done 49 | 50 | RDIR="$( dirname "$SOURCE" )" 51 | DIR="$( cd -P "$( dirname "$SOURCE" )" && pwd )" 52 | 53 | cd $DIR 54 | 55 | cp -f ../build/target.axf . 56 | 57 | 58 | 59 | cp ./target.axf ./target_pure.axf 60 | ${TOOLCHAIN}-strip ./target_pure.axf 61 | 62 | ${TOOLCHAIN}-objcopy -j .ram.start.table -j .ram_image1.text \ 63 | -Obinary ./target_pure.axf ./ram_1.bin 64 | 65 | ${TOOLCHAIN}-objcopy -j .image2.start.table -j .ram_image2.text -j .ram.data \ 66 | -Obinary ./target_pure.axf ./ram_2.bin 67 | 68 | ${TOOLCHAIN}-nm target.axf | sort > target.map 69 | 70 | ${TOOLCHAIN}-objdump -d target.axf > target.asm 71 | 72 | ./prepend_header.sh ./ram_1.bin __ram_image1_text_start__ ./target.map 0 73 | ./prepend_header.sh ./ram_2.bin __ram_image2_text_start__ ./target.map 74 | cat ./ram_1_prepend.bin ./ram_2_prepend.bin > ./ram_all.bin 75 | 76 | 77 | #mbed_disk=100 78 | #while [[ $mbed_disk -le 122 ]] 79 | #do 80 | # 81 | # diskname=`chr $mbed_disk` 82 | # filename="/cygdrive/$diskname/mbed.htm" 83 | # if [ -f $filename ]; 84 | # then 85 | # break 86 | # fi 87 | # mbed_disk=$((mbed_disk+1)) 88 | #done 89 | 90 | 91 | #if [[ $mbed_disk -le 122 ]]; 92 | #then 93 | # echo cp ./ram_all.bin /cygdrive/$diskname/ 94 | # cp ./ram_all.bin /cygdrive/$diskname/ 95 | #else 96 | # echo mbed usb disk not found 97 | #fi 98 | 99 | -------------------------------------------------------------------------------- /makebin/prepend_header.sh: -------------------------------------------------------------------------------- 1 | ##!/bin/bash 2 | 3 | ################ 4 | # Library 5 | ################ 6 | Usage() { 7 | echo "Usage: $0 [Image Name] [Start Symbol Name] [Symbols List File]" 8 | } 9 | 10 | # Parameter: 11 | # value, width, dest 12 | function MakeFixedWidthHeaderString() { 13 | local __value=$1 14 | local __width=$2 15 | local __dest=$3 16 | local __header_raw 17 | local __header_raw_reorder 18 | local __header_array 19 | 20 | if [[ "$__dest" ]]; then 21 | 22 | __header_raw=$(printf "%0""$__width""x" $__value) 23 | # echo $__header_raw 24 | 25 | # 20000680 to 80060020 26 | for (( i=$__width; i > 0; i-=2 )) 27 | do 28 | __header_raw_reorder+=$(echo $__header_raw | cut -b $((i-1))) 29 | __header_raw_reorder+=$(echo $__header_raw | cut -b $i) 30 | done 31 | # echo $__header_raw_reorder 32 | 33 | __header_array=($(echo $__header_raw_reorder | sed 's/\(.\)/\1 /g')) 34 | 35 | for (( i=0; i < $__width; i+=2)) 36 | do 37 | eval $__dest+='\\x'"${__header_array[$i]}${__header_array[$i+1]}" 38 | done 39 | fi 40 | } 41 | 42 | ################ 43 | # Main 44 | ################ 45 | if [ "$#" -lt 3 ]; then 46 | Usage 47 | exit 1 48 | fi 49 | 50 | # Get Parameters 51 | IMAGE_FILENAME=$1 52 | IMAGE_SECTION_START_NAME=$2 53 | SYMBOL_LIST=$3 54 | IMG2_OFFSET=$4 55 | 56 | # Constant Variables 57 | PATTERN_1=0x96969999 58 | PATTERN_2=0xFC66CC3F 59 | PATTERN_3=0x03CC33C0 60 | PATTERN_4=0x6231DCE5 61 | RSVD=0xFFFFFFFFFFFFFFFF 62 | IMAGE_LEN=$(du -b $IMAGE_FILENAME | cut -f 1) 63 | IMAGE_ADDR="0x$(grep $IMAGE_SECTION_START_NAME $SYMBOL_LIST | awk '{print $1}')" 64 | IMAGE_FILENAME_PREPEND="${IMAGE_FILENAME%.*}"'_prepend.'"${IMAGE_FILENAME##*.}" 65 | 66 | IMAGE_FILENAME_NEW=$(basename $IMAGE_FILENAME) 67 | 68 | HEADER_FINAL='' 69 | if [ "$IMAGE_FILENAME_NEW" == "ram_1.bin" ]; then 70 | MakeFixedWidthHeaderString $PATTERN_1 8 HEADER_FINAL 71 | MakeFixedWidthHeaderString $PATTERN_2 8 HEADER_FINAL 72 | MakeFixedWidthHeaderString $PATTERN_3 8 HEADER_FINAL 73 | MakeFixedWidthHeaderString $PATTERN_4 8 HEADER_FINAL 74 | fi 75 | 76 | MakeFixedWidthHeaderString $IMAGE_LEN 8 HEADER_FINAL 77 | MakeFixedWidthHeaderString $IMAGE_ADDR 8 HEADER_FINAL 78 | if [ "$IMAGE_FILENAME_NEW" == "ram_1.bin" ]; then 79 | MakeFixedWidthHeaderString $IMG2_OFFSET 4 HEADER_FINAL 80 | MakeFixedWidthHeaderString $RSVD 12 HEADER_FINAL 81 | else 82 | MakeFixedWidthHeaderString $RSVD 16 HEADER_FINAL 83 | fi 84 | 85 | # echo $HEADER_FINAL 86 | 87 | echo -n -e $HEADER_FINAL | cat - $IMAGE_FILENAME > $IMAGE_FILENAME_PREPEND 88 | 89 | -------------------------------------------------------------------------------- /sdk/lib/hal_sdr_controller.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eggman/rtl_ameba_gcc_sample/d5d2f9294a7e66641f75f699e051a31ab14c0f97/sdk/lib/hal_sdr_controller.o -------------------------------------------------------------------------------- /sdk/lib/lib_platform.a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eggman/rtl_ameba_gcc_sample/d5d2f9294a7e66641f75f699e051a31ab14c0f97/sdk/lib/lib_platform.a -------------------------------------------------------------------------------- /sdk/lib/startup.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eggman/rtl_ameba_gcc_sample/d5d2f9294a7e66641f75f699e051a31ab14c0f97/sdk/lib/startup.o -------------------------------------------------------------------------------- /sdk/scripts/rlx8195a.ld: -------------------------------------------------------------------------------- 1 | 2 | 3 | ENTRY(PreProcessForVendor) 4 | 5 | INCLUDE "export-rom.txt" 6 | 7 | 8 | MEMORY 9 | { 10 | TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536 11 | BD_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 455735 12 | SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M 13 | } 14 | 15 | STACK_SIZE = 0x2000 ; 16 | 17 | 18 | SECTIONS 19 | { 20 | __rom_bss_start__ = 0x10000300; 21 | __rom_bss_end__ = 0x10000bc8; 22 | 23 | .ram.start.table : 24 | { 25 | __ram_image1_text_start__ = .; 26 | __ram_start_table_start__ = .; 27 | KEEP(*(SORT(.start.ram.data*))) 28 | __ram_start_table_end__ = .; 29 | 30 | } > BD_RAM 31 | 32 | 33 | /* Add . to assign the start address of the section, * 34 | * to prevent the change of the start address by ld doing section alignment */ 35 | .ram_image1.text . : 36 | { 37 | /* these 4 sections is used by ROM global variable */ 38 | /* Don't move them and never add RAM code variable to these sections */ 39 | __image1_validate_code__ = .; 40 | KEEP(*(.image1.validate.rodata*)) 41 | KEEP(*(.infra.ram.data*)) 42 | KEEP(*(.timer.ram.data*)) 43 | KEEP(*(.hal.ram.data*)) 44 | __image1_bss_start__ = .; 45 | *(.hal.flash.data*) 46 | *(.hal.sdrc.data*) 47 | __image1_bss_end__ = .; 48 | 49 | *(.hal.ram.text*) 50 | *(.hal.flash.text*) 51 | *(.hal.sdrc.text*) 52 | *(.rodata*) 53 | *(.infra.ram.text*) 54 | __ram_image1_text_end__ = .; 55 | } > BD_RAM 56 | 57 | .image2.start.table : 58 | { 59 | __ram_image2_text_start__ = .; 60 | __image2_entry_func__ = .; 61 | KEEP(*(SORT(.image2.ram.data*))) 62 | __image2_validate_code__ = .; 63 | KEEP(*(.image2.validate.rodata*)) 64 | } > BD_RAM 65 | 66 | .ram_image2.text : 67 | { 68 | KEEP(*(.vectors .vectors.*)) 69 | *(.infra.ram.start*) 70 | *(.mon.ram.text*) 71 | *(.text .text.* .gnu.linkonce.t.*) 72 | *(.ramfunc .ramfunc.*); 73 | *(.glue_7t) *(.glue_7) 74 | *(.gnu.linkonce.r.*) 75 | 76 | 77 | } > BD_RAM 78 | 79 | .ARM.extab : 80 | { 81 | *(.ARM.extab* .gnu.linkonce.armextab.*) 82 | } > BD_RAM 83 | 84 | .ram.data : 85 | { 86 | __data_start__ = .; 87 | . = ALIGN(4); 88 | *(vtable) 89 | 90 | . = ALIGN(4); 91 | *(.data .data.*); 92 | 93 | 94 | . = ALIGN(4); 95 | /* preinit data */ 96 | PROVIDE (__preinit_array_start = .); 97 | KEEP(*(.preinit_array)) 98 | PROVIDE (__preinit_array_end = .); 99 | 100 | 101 | /* init data */ 102 | 103 | . = ALIGN(4); 104 | KEEP(*(.init)) 105 | 106 | . = ALIGN(4); 107 | PROVIDE (__init_array_start = .); 108 | KEEP(*(SORT(.init_array.*))) 109 | KEEP(*(.init_array)) 110 | PROVIDE (__init_array_end = .); 111 | 112 | . = ALIGN(0x4); 113 | KEEP (*crtbegin.o(.ctors)) 114 | KEEP(*crtbegin?.o(.ctors)) 115 | KEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) 116 | KEEP (*(SORT(.ctors.*))) 117 | KEEP (*crtend.o(.ctors)) 118 | KEEP(*(.ctors)) 119 | 120 | 121 | /* finit data */ 122 | . = ALIGN(4); 123 | KEEP(*(.fini)) 124 | 125 | . = ALIGN(4); 126 | PROVIDE (__fini_array_start = .); 127 | KEEP(*(SORT(.fini_array.*))) 128 | KEEP(*(.fini_array)) 129 | PROVIDE (__fini_array_end = .); 130 | 131 | . = ALIGN(4); 132 | KEEP (*crtbegin.o(.dtors)) 133 | KEEP(*crtbegin?.o(.dtors)) 134 | KEEP(*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) 135 | KEEP(*(SORT(.dtors.*))) 136 | KEEP(*crtend.o(.dtors)) 137 | KEEP(*(.dtors)) 138 | 139 | } > BD_RAM 140 | 141 | . = ALIGN(4); 142 | /* .ARM.exidx is sorted, so has to go in its own output section. */ 143 | PROVIDE_HIDDEN (__exidx_start = .); 144 | .ARM.exidx ALIGN(4) : AT(__exidx_start) 145 | { 146 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) 147 | 148 | /* All data end */ 149 | __data_end__ = .; 150 | __ram_image2_text_end__ = .; 151 | 152 | } > BD_RAM 153 | PROVIDE_HIDDEN (__exidx_end = .); 154 | 155 | 156 | .sdr_data : 157 | { 158 | __sdram_data_start__ = .; 159 | *(.sdram.data*) 160 | __sdram_data_end__ = .; 161 | 162 | } > SDRAM_RAM 163 | 164 | 165 | 166 | /* .bss section which is used for uninitialized data */ 167 | .bss (NOLOAD): 168 | { 169 | . = ALIGN(4); 170 | __bss_start__ = .; 171 | _sbss = . ; 172 | _szero = .; 173 | 174 | *(.bss .bss.*) 175 | *(COMMON) 176 | *(.bdsram.data*) 177 | 178 | . = ALIGN(4); 179 | _ebss = . ; 180 | _ezero = .; 181 | __bss_end__ = .; 182 | } > BD_RAM 183 | 184 | .bf_data (NOLOAD): 185 | { 186 | __buffer_data_start__ = .; 187 | *(.bfsram.data*) 188 | __buffer_data_end__ = .; 189 | 190 | } > BD_RAM 191 | 192 | .heap (NOLOAD): 193 | { 194 | __end__ = .; 195 | end = __end__; 196 | *(.heap*) 197 | __HeapLimit = .; 198 | } > BD_RAM 199 | 200 | 201 | /* stack section */ 202 | . = ALIGN(8); 203 | PROVIDE( _sstack = .); 204 | PROVIDE(__StackLimit = _sstack); 205 | 206 | 207 | .stack_dummy (NOLOAD) : AT(_sstack) 208 | { 209 | . = ALIGN(8); 210 | . = . + STACK_SIZE; 211 | . = ALIGN(8); 212 | } > BD_RAM 213 | 214 | PROVIDE(_estack = .); 215 | PROVIDE(__StackTop = _estack); 216 | PROVIDE(__stack = __StackTop); 217 | 218 | 219 | 220 | . = ALIGN(4); 221 | _end = . ; 222 | 223 | 224 | } 225 | 226 | 227 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/analogin_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_ANALOGIN_API_H 17 | #define MBED_ANALOGIN_API_H 18 | 19 | #include "device.h" 20 | 21 | #if DEVICE_ANALOGIN 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | typedef struct analogin_s analogin_t; 28 | 29 | extern void analogin_init (analogin_t *obj, PinName pin); 30 | extern float analogin_read (analogin_t *obj); 31 | extern uint16_t analogin_read_u16(analogin_t *obj); 32 | extern uint32_t analogin_read_for_random(analogin_t *obj); 33 | 34 | #ifdef __cplusplus 35 | } 36 | #endif 37 | 38 | #endif 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/analogout_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_ANALOGOUT_API_H 17 | #define MBED_ANALOGOUT_API_H 18 | 19 | #include "device.h" 20 | 21 | #if DEVICE_ANALOGOUT 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | typedef struct dac_s dac_t; 28 | 29 | void analogout_init (dac_t *obj, PinName pin); 30 | void analogout_free (dac_t *obj); 31 | void analogout_write (dac_t *obj, float value); 32 | void analogout_write_u16(dac_t *obj, uint16_t value); 33 | float analogout_read (dac_t *obj); 34 | uint16_t analogout_read_u16 (dac_t *obj); 35 | 36 | #ifdef __cplusplus 37 | } 38 | #endif 39 | 40 | #endif 41 | 42 | #endif 43 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/gpio_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_GPIO_API_H 17 | #define MBED_GPIO_API_H 18 | 19 | #include "device.h" 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | /* Set the given pin as GPIO 26 | * @param pin The pin to be set as GPIO 27 | * @return The GPIO port mask for this pin 28 | **/ 29 | uint32_t gpio_set(PinName pin); 30 | 31 | /* GPIO object */ 32 | void gpio_init(gpio_t *obj, PinName pin); 33 | 34 | void gpio_mode (gpio_t *obj, PinMode mode); 35 | void gpio_dir (gpio_t *obj, PinDirection direction); 36 | 37 | void gpio_write(gpio_t *obj, int value); 38 | int gpio_read (gpio_t *obj); 39 | 40 | // the following set of functions are generic and are implemented in the common gpio.c file 41 | void gpio_init_in(gpio_t* gpio, PinName pin); 42 | void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode); 43 | void gpio_init_out(gpio_t* gpio, PinName pin); 44 | void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value); 45 | void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value); 46 | 47 | #ifdef __cplusplus 48 | } 49 | #endif 50 | 51 | #endif 52 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/gpio_irq_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_GPIO_IRQ_API_H 17 | #define MBED_GPIO_IRQ_API_H 18 | 19 | #include "device.h" 20 | 21 | #if DEVICE_INTERRUPTIN 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | typedef enum { 28 | IRQ_NONE, 29 | IRQ_RISE, 30 | IRQ_FALL 31 | } gpio_irq_event; 32 | 33 | typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); 34 | 35 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id); 36 | void gpio_irq_free(gpio_irq_t *obj); 37 | void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable); 38 | void gpio_irq_enable(gpio_irq_t *obj); 39 | void gpio_irq_disable(gpio_irq_t *obj); 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/i2c_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_I2C_API_H 17 | #define MBED_I2C_API_H 18 | 19 | #include 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | #include "objects.h" 26 | 27 | typedef struct i2c_s i2c_t; 28 | 29 | enum { 30 | I2C_ERROR_NO_SLAVE = -1, 31 | I2C_ERROR_BUS_BUSY = -2 32 | }; 33 | 34 | extern void i2c_init (i2c_t *obj, PinName sda, PinName scl); 35 | extern void i2c_frequency (i2c_t *obj, int hz); 36 | extern int i2c_start (i2c_t *obj); 37 | extern int i2c_stop (i2c_t *obj); 38 | extern int i2c_read (i2c_t *obj, int address, char *data, int length, int stop); 39 | extern int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop); 40 | extern void i2c_reset (i2c_t *obj); 41 | extern int i2c_byte_read (i2c_t *obj, int last); 42 | extern int i2c_byte_write (i2c_t *obj, int data); 43 | 44 | extern void i2c_slave_mode (i2c_t *obj, int enable_slave); 45 | extern int i2c_slave_receive(i2c_t *obj); 46 | extern int i2c_slave_read (i2c_t *obj, char *data, int length); 47 | extern int i2c_slave_write (i2c_t *obj, const char *data, int length); 48 | extern void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask); 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | 55 | #endif 56 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/pinmap.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_PINMAP_H 17 | #define MBED_PINMAP_H 18 | 19 | #include "PinNames.h" 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | typedef struct { 26 | PinName pin; 27 | int peripheral; 28 | int function; 29 | } PinMap; 30 | 31 | void pin_function(PinName pin, int function); 32 | void pin_mode (PinName pin, PinMode mode); 33 | 34 | uint32_t pinmap_peripheral(PinName pin, const PinMap* map); 35 | uint32_t pinmap_merge (uint32_t a, uint32_t b); 36 | void pinmap_pinout (PinName pin, const PinMap *map); 37 | uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map); 38 | 39 | #ifdef __cplusplus 40 | } 41 | #endif 42 | 43 | #endif 44 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/pwmout_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_PWMOUT_API_H 17 | #define MBED_PWMOUT_API_H 18 | 19 | #include "device.h" 20 | 21 | #if DEVICE_PWMOUT 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | typedef struct pwmout_s pwmout_t; 28 | 29 | void pwmout_init (pwmout_t* obj, PinName pin); 30 | void pwmout_free (pwmout_t* obj); 31 | 32 | void pwmout_write (pwmout_t* obj, float percent); 33 | float pwmout_read (pwmout_t* obj); 34 | 35 | void pwmout_period (pwmout_t* obj, float seconds); 36 | void pwmout_period_ms (pwmout_t* obj, int ms); 37 | void pwmout_period_us (pwmout_t* obj, int us); 38 | 39 | void pwmout_pulsewidth (pwmout_t* obj, float seconds); 40 | void pwmout_pulsewidth_ms(pwmout_t* obj, int ms); 41 | void pwmout_pulsewidth_us(pwmout_t* obj, int us); 42 | 43 | #ifdef __cplusplus 44 | } 45 | #endif 46 | 47 | #endif 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/serial_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_SERIAL_API_H 17 | #define MBED_SERIAL_API_H 18 | 19 | #include "device.h" 20 | 21 | #if DEVICE_SERIAL 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | typedef enum { 28 | ParityNone = 0, 29 | ParityOdd = 1, 30 | ParityEven = 2, 31 | ParityForced1 = 3, 32 | ParityForced0 = 4 33 | } SerialParity; 34 | 35 | typedef enum { 36 | RxIrq, 37 | TxIrq 38 | } SerialIrq; 39 | 40 | typedef enum { 41 | FlowControlNone, 42 | FlowControlRTS, 43 | FlowControlCTS, 44 | FlowControlRTSCTS 45 | } FlowControl; 46 | 47 | typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event); 48 | 49 | typedef struct serial_s serial_t; 50 | 51 | void serial_init (serial_t *obj, PinName tx, PinName rx); 52 | void serial_free (serial_t *obj); 53 | void serial_baud (serial_t *obj, int baudrate); 54 | void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits); 55 | 56 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id); 57 | void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable); 58 | 59 | int serial_getc (serial_t *obj); 60 | void serial_putc (serial_t *obj, int c); 61 | int serial_readable (serial_t *obj); 62 | int serial_writable (serial_t *obj); 63 | void serial_clear (serial_t *obj); 64 | 65 | void serial_break_set (serial_t *obj); 66 | void serial_break_clear(serial_t *obj); 67 | 68 | void serial_pinout_tx(PinName tx); 69 | 70 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow); 71 | 72 | #ifdef __cplusplus 73 | } 74 | #endif 75 | 76 | #endif 77 | 78 | #endif 79 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/spi_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_SPI_API_H 17 | #define MBED_SPI_API_H 18 | 19 | #include "device.h" 20 | 21 | #if DEVICE_SPI 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | typedef struct spi_s spi_t; 28 | 29 | void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel); 30 | void spi_free (spi_t *obj); 31 | void spi_format (spi_t *obj, int bits, int mode, int slave); 32 | void spi_frequency (spi_t *obj, int hz); 33 | int spi_master_write (spi_t *obj, int value); 34 | int spi_slave_receive(spi_t *obj); 35 | int spi_slave_read (spi_t *obj); 36 | void spi_slave_write (spi_t *obj, int value); 37 | int spi_busy (spi_t *obj); 38 | 39 | #ifdef __cplusplus 40 | } 41 | #endif 42 | 43 | #endif 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/hal/us_ticker_api.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_US_TICKER_API_H 17 | #define MBED_US_TICKER_API_H 18 | 19 | #include 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | typedef uint64_t timestamp_t; 26 | 27 | uint32_t us_ticker_read(void); 28 | 29 | typedef void (*ticker_event_handler)(uint32_t id); 30 | void us_ticker_set_handler(ticker_event_handler handler); 31 | 32 | typedef struct ticker_event_s { 33 | timestamp_t timestamp; 34 | uint32_t id; 35 | struct ticker_event_s *next; 36 | } ticker_event_t; 37 | 38 | void us_ticker_init(void); 39 | void us_ticker_set_interrupt(timestamp_t timestamp); 40 | void us_ticker_disable_interrupt(void); 41 | void us_ticker_clear_interrupt(void); 42 | void us_ticker_irq_handler(void); 43 | 44 | void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id); 45 | void us_ticker_remove_event(ticker_event_t *obj); 46 | 47 | #ifdef __cplusplus 48 | } 49 | #endif 50 | 51 | #endif 52 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/targets/hal/rtl8195a/PeripheralNames.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_PERIPHERALNAMES_H 17 | #define MBED_PERIPHERALNAMES_H 18 | 19 | #include "cmsis.h" 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | #if 0 26 | typedef enum { 27 | UART_1 = (int)USART1_BASE, 28 | UART_2 = (int)USART2_BASE, 29 | UART_3 = (int)USART3_BASE, 30 | UART_4 = (int)UART4_BASE, 31 | UART_5 = (int)UART5_BASE, 32 | UART_6 = (int)USART6_BASE 33 | } UARTName; 34 | 35 | typedef enum { 36 | ADC0_0 = 0, 37 | ADC0_1, 38 | ADC0_2, 39 | ADC0_3, 40 | ADC0_4, 41 | ADC0_5, 42 | ADC0_6, 43 | ADC0_7, 44 | ADC0_8, 45 | ADC0_9, 46 | ADC0_10, 47 | ADC0_11, 48 | ADC0_12, 49 | ADC0_13, 50 | ADC0_14, 51 | ADC0_15 52 | } ADCName; 53 | 54 | typedef enum { 55 | DAC_0 = 0, 56 | DAC_1 57 | } DACName; 58 | 59 | typedef enum { 60 | SPI_1 = (int)SPI1_BASE, 61 | SPI_2 = (int)SPI2_BASE, 62 | SPI_3 = (int)SPI3_BASE, 63 | } SPIName; 64 | 65 | typedef enum { 66 | I2C_1 = (int)I2C1_BASE, 67 | I2C_2 = (int)I2C2_BASE, 68 | I2C_3 = (int)I2C3_BASE 69 | } I2CName; 70 | 71 | typedef enum { 72 | PWM_1 = 1, 73 | PWM_2, 74 | PWM_3, 75 | PWM_4, 76 | PWM_5, 77 | PWM_6 78 | } PWMName; 79 | 80 | typedef enum { 81 | CAN_1 = (int)CAN1_BASE, 82 | CAN_2 = (int)CAN2_BASE 83 | } CANName; 84 | #endif 85 | 86 | #define STDIO_UART_TX PA_6 87 | #define STDIO_UART_RX PA_7 88 | #define STDIO_UART UART0 89 | 90 | #ifdef __cplusplus 91 | } 92 | #endif 93 | 94 | #endif 95 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/targets/hal/rtl8195a/PinNames.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef _PINNAMES_H_ 3 | #define _PINNAMES_H_ 4 | 5 | #include "cmsis.h" 6 | 7 | #ifdef __cplusplus 8 | extern "C" { 9 | #endif 10 | 11 | typedef enum { 12 | PORT_A = 0, 13 | PORT_B = 1, 14 | PORT_C = 2, 15 | PORT_D = 3, 16 | PORT_E = 4, 17 | PORT_F = 5, 18 | PORT_G = 6, 19 | PORT_H = 7, 20 | PORT_I = 8, 21 | PORT_J = 9, 22 | PORT_K = 10, 23 | 24 | PORT_V = 11, 25 | PORT_MAX 26 | } GPIO_PORT; 27 | 28 | #define RTL_PIN_PERI(FUN, IDX, SEL) ((int)(((FUN) << 8) | ((IDX)<<4) | (SEL))) 29 | #define RTL_PIN_FUNC(FUN, SEL) ((int)(((FUN) << 7) | (SEL))) 30 | #define RTL_GET_PERI_SEL(peri) ((int)((peri)&0x0F)) 31 | #define RTL_GET_PERI_IDX(peri) ((int)(((peri) >> 4)&0x0F)) 32 | 33 | typedef enum { 34 | PIN_INPUT=0, 35 | PIN_OUTPUT 36 | } PinDirection; 37 | 38 | typedef enum { 39 | PA_0 = (PORT_A<<4|0), 40 | PA_1 = (PORT_A<<4|1), 41 | PA_2 = (PORT_A<<4|2), 42 | PA_3 = (PORT_A<<4|3), 43 | PA_4 = (PORT_A<<4|4), 44 | PA_5 = (PORT_A<<4|5), 45 | PA_6 = (PORT_A<<4|6), 46 | PA_7 = (PORT_A<<4|7), 47 | 48 | PB_0 = (PORT_B<<4|0), 49 | PB_1 = (PORT_B<<4|1), 50 | PB_2 = (PORT_B<<4|2), 51 | PB_3 = (PORT_B<<4|3), 52 | PB_4 = (PORT_B<<4|4), 53 | PB_5 = (PORT_B<<4|5), 54 | PB_6 = (PORT_B<<4|6), 55 | PB_7 = (PORT_B<<4|7), 56 | 57 | PC_0 = (PORT_C<<4|0), 58 | PC_1 = (PORT_C<<4|1), 59 | PC_2 = (PORT_C<<4|2), 60 | PC_3 = (PORT_C<<4|3), 61 | PC_4 = (PORT_C<<4|4), 62 | PC_5 = (PORT_C<<4|5), 63 | PC_6 = (PORT_C<<4|6), 64 | PC_7 = (PORT_C<<4|7), 65 | PC_8 = (PORT_C<<4|8), 66 | PC_9 = (PORT_C<<4|9), 67 | 68 | PD_0 = (PORT_D<<4|0), 69 | PD_1 = (PORT_D<<4|1), 70 | PD_2 = (PORT_D<<4|2), 71 | PD_3 = (PORT_D<<4|3), 72 | PD_4 = (PORT_D<<4|4), 73 | PD_5 = (PORT_D<<4|5), 74 | PD_6 = (PORT_D<<4|6), 75 | PD_7 = (PORT_D<<4|7), 76 | PD_8 = (PORT_D<<4|8), 77 | PD_9 = (PORT_D<<4|9), 78 | 79 | PE_0 = (PORT_E<<4|0), 80 | PE_1 = (PORT_E<<4|1), 81 | PE_2 = (PORT_E<<4|2), 82 | PE_3 = (PORT_E<<4|3), 83 | PE_4 = (PORT_E<<4|4), 84 | PE_5 = (PORT_E<<4|5), 85 | PE_6 = (PORT_E<<4|6), 86 | PE_7 = (PORT_E<<4|7), 87 | PE_8 = (PORT_E<<4|8), 88 | PE_9 = (PORT_E<<4|9), 89 | PE_A = (PORT_E<<4|10), 90 | 91 | PF_0 = (PORT_F<<4|0), 92 | PF_1 = (PORT_F<<4|1), 93 | PF_2 = (PORT_F<<4|2), 94 | PF_3 = (PORT_F<<4|3), 95 | PF_4 = (PORT_F<<4|4), 96 | PF_5 = (PORT_F<<4|5), 97 | // PF_6 = (PORT_F<<4|6), 98 | // PF_7 = (PORT_F<<4|7), 99 | 100 | PG_0 = (PORT_G<<4|0), 101 | PG_1 = (PORT_G<<4|1), 102 | PG_2 = (PORT_G<<4|2), 103 | PG_3 = (PORT_G<<4|3), 104 | PG_4 = (PORT_G<<4|4), 105 | PG_5 = (PORT_G<<4|5), 106 | PG_6 = (PORT_G<<4|6), 107 | PG_7 = (PORT_G<<4|7), 108 | 109 | PH_0 = (PORT_H<<4|0), 110 | PH_1 = (PORT_H<<4|1), 111 | PH_2 = (PORT_H<<4|2), 112 | PH_3 = (PORT_H<<4|3), 113 | PH_4 = (PORT_H<<4|4), 114 | PH_5 = (PORT_H<<4|5), 115 | PH_6 = (PORT_H<<4|6), 116 | PH_7 = (PORT_H<<4|7), 117 | 118 | PI_0 = (PORT_I<<4|0), 119 | PI_1 = (PORT_I<<4|1), 120 | PI_2 = (PORT_I<<4|2), 121 | PI_3 = (PORT_I<<4|3), 122 | PI_4 = (PORT_I<<4|4), 123 | PI_5 = (PORT_I<<4|5), 124 | PI_6 = (PORT_I<<4|6), 125 | PI_7 = (PORT_I<<4|7), 126 | 127 | PJ_0 = (PORT_J<<4|0), 128 | PJ_1 = (PORT_J<<4|1), 129 | PJ_2 = (PORT_J<<4|2), 130 | PJ_3 = (PORT_J<<4|3), 131 | PJ_4 = (PORT_J<<4|4), 132 | PJ_5 = (PORT_J<<4|5), 133 | PJ_6 = (PORT_J<<4|6), 134 | // PJ_7 = (PORT_J<<4|7), 135 | 136 | PK_0 = (PORT_K<<4|0), 137 | PK_1 = (PORT_K<<4|1), 138 | PK_2 = (PORT_K<<4|2), 139 | PK_3 = (PORT_K<<4|3), 140 | PK_4 = (PORT_K<<4|4), 141 | PK_5 = (PORT_K<<4|5), 142 | PK_6 = (PORT_K<<4|6), 143 | // PK_7 = (PORT_K<<4|7), 144 | 145 | AD_1 = (PORT_V<<4|1), 146 | AD_2 = (PORT_V<<4|2), 147 | AD_3 = (PORT_V<<4|3), 148 | 149 | // Arduino connector namings 150 | A0 = AD_2, 151 | A1 = AD_2, 152 | A2 = AD_3, 153 | 154 | // Generic signals namings 155 | LED1 = PB_4, 156 | LED2 = PB_5, 157 | LED3 = PB_6, 158 | LED4 = PB_7, 159 | USER_BUTTON = PA_3, 160 | SERIAL_TX = PA_7, 161 | SERIAL_RX = PA_6, 162 | USBTX = PA_7, 163 | USBRX = PA_6, 164 | I2C_SCL = PC_5, 165 | I2C_SDA = PC_4, 166 | SPI_MOSI = PC_2, 167 | SPI_MISO = PC_3, 168 | SPI_SCK = PC_1, 169 | SPI_CS = PC_0, 170 | PWM_OUT = PD_4, 171 | 172 | // Not connected 173 | NC = (uint32_t)0xFFFFFFFF 174 | } PinName; 175 | 176 | typedef enum { 177 | PullNone = 0, 178 | PullUp = 1, 179 | PullDown = 2, 180 | OpenDrain = 3, 181 | PullDefault = PullNone 182 | } PinMode; 183 | 184 | #define PORT_NUM(pin) (((uint32_t)(pin) >> 4) & 0xF) 185 | #define PIN_NUM(pin) ((uint32_t)(pin) & 0xF) 186 | 187 | #ifdef __cplusplus 188 | } 189 | #endif 190 | 191 | #endif 192 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/targets/hal/rtl8195a/PortNames.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_PORTNAMES_H 17 | #define MBED_PORTNAMES_H 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | typedef enum { 24 | PortA = 0, 25 | PortB = 1, 26 | PortC = 2, 27 | PortD = 3, 28 | PortE = 4, 29 | PortF = 5, 30 | PortG = 6, 31 | PortH = 7, 32 | PortI = 8 33 | } PortName; 34 | 35 | #ifdef __cplusplus 36 | } 37 | #endif 38 | #endif 39 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/targets/hal/rtl8195a/device.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_DEVICE_H 17 | #define MBED_DEVICE_H 18 | 19 | #define DEVICE_PORTIN 1 20 | #define DEVICE_PORTOUT 1 21 | #define DEVICE_PORTINOUT 1 22 | 23 | #define DEVICE_INTERRUPTIN 1 24 | 25 | #define DEVICE_ANALOGIN 1 26 | #define DEVICE_ANALOGOUT 0 27 | 28 | #define DEVICE_SERIAL 1 29 | 30 | #define DEVICE_I2C 1 31 | #define DEVICE_I2CSLAVE 1 32 | 33 | #define DEVICE_SPI 1 34 | #define DEVICE_SPISLAVE 1 35 | 36 | #define DEVICE_CAN 0 37 | 38 | #define DEVICE_RTC 1 39 | 40 | #define DEVICE_ETHERNET 0 41 | 42 | #define DEVICE_PWMOUT 1 43 | 44 | #define DEVICE_SLEEP 0 45 | 46 | #include "objects.h" 47 | 48 | #endif 49 | -------------------------------------------------------------------------------- /sdk/src/sw/lib/sw_lib/mbed/targets/hal/rtl8195a/objects.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * Copyright (c) 2006-2013 ARM Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | #ifndef MBED_OBJECTS_H 17 | #define MBED_OBJECTS_H 18 | 19 | 20 | #ifdef __cplusplus 21 | extern "C" { 22 | #endif 23 | 24 | #include "cmsis.h" 25 | #include "PortNames.h" 26 | #include "PeripheralNames.h" 27 | #include "PinNames.h" 28 | 29 | #include "device.h" 30 | 31 | #ifdef CONFIG_GPIO_EN 32 | struct gpio_irq_s { 33 | PinName pin; 34 | uint32_t event; 35 | HAL_GPIO_PIN hal_pin; 36 | }; 37 | 38 | typedef struct gpio_irq_s gpio_irq_t; 39 | 40 | struct gpio_s { 41 | PinName pin; 42 | PinMode mode; 43 | PinDirection direction; 44 | HAL_GPIO_PIN hal_pin; 45 | }; 46 | 47 | typedef struct gpio_s gpio_t; 48 | 49 | struct port_s { 50 | // Todo: 51 | void *unused; // TODO: need remove 52 | }; 53 | #endif // end of "#ifdef CONFIG_GPIO_EN" 54 | 55 | #ifdef CONFIG_UART_EN 56 | struct serial_s { 57 | HAL_RUART_OP hal_uart_op; 58 | HAL_RUART_ADAPTER hal_uart_adp; 59 | // UART_DMA_CONFIG hal_uart_dma_cfg; 60 | }; 61 | #endif // end of "#ifdef CONFIG_UART_EN" 62 | 63 | #ifdef CONFIG_SPI_COM_EN 64 | 65 | #endif 66 | 67 | #ifdef CONFIG_PWM_EN 68 | struct pwmout_s { 69 | uint8_t pwm_idx; 70 | uint8_t pin_sel; 71 | uint32_t period; 72 | uint32_t pulse; 73 | 74 | }; 75 | #endif 76 | 77 | #ifdef CONFIG_I2C_EN 78 | struct i2c_s { 79 | SAL_I2C_MNGT_ADPT SalI2CMngtAdpt; 80 | SAL_I2C_HND_PRIV SalI2CHndPriv; 81 | HAL_I2C_INIT_DAT HalI2CInitData; 82 | HAL_I2C_OP HalI2COp; 83 | IRQ_HANDLE I2CIrqHandleDat; 84 | HAL_GDMA_ADAPTER HalI2CTxGdmaAdpt; 85 | HAL_GDMA_ADAPTER HalI2CRxGdmaAdpt; 86 | HAL_GDMA_OP HalI2CGdmaOp; 87 | IRQ_HANDLE I2CTxGdmaIrqHandleDat; 88 | IRQ_HANDLE I2CRxGdmaIrqHandleDat; 89 | SAL_I2C_USER_CB SalI2CUserCB; 90 | SAL_I2C_USERCB_ADPT SalI2CUserCBAdpt[SAL_USER_CB_NUM]; 91 | SAL_I2C_DMA_USER_DEF SalI2CDmaUserDef; 92 | }; 93 | #endif 94 | 95 | 96 | struct flash_s 97 | { 98 | SPIC_INIT_PARA SpicInitPara; 99 | }; 100 | 101 | 102 | 103 | #ifdef CONFIG_ADC_EN 104 | struct analogin_s { 105 | SAL_ADC_MNGT_ADPT SalADCMngtAdpt; 106 | SAL_ADC_HND_PRIV SalADCHndPriv; 107 | HAL_ADC_INIT_DAT HalADCInitData; 108 | HAL_ADC_OP HalADCOp; 109 | IRQ_HANDLE ADCIrqHandleDat; 110 | HAL_GDMA_ADAPTER HalADCGdmaAdpt; 111 | HAL_GDMA_OP HalADCGdmaOp; 112 | IRQ_HANDLE ADCGdmaIrqHandleDat; 113 | SAL_ADC_USER_CB SalADCUserCB; 114 | SAL_ADC_USERCB_ADPT SalADCUserCBAdpt[SAL_USER_CB_NUM]; 115 | }; 116 | #endif 117 | 118 | #if 0 119 | struct i2c_s { 120 | I2C_Type *i2c; 121 | }; 122 | 123 | struct spi_s { 124 | SPI_Type *spi; 125 | }; 126 | 127 | #endif 128 | 129 | #ifdef CONFIG_NFC_EN 130 | struct nfctag_s { 131 | NFC_ADAPTER NFCAdapter; 132 | void *nfc_rd_cb; // read callback function 133 | void *rd_cb_arg; 134 | void *nfc_wr_cb; // write callback function 135 | void *wr_cb_arg; 136 | void *nfc_ev_cb; // event callback function 137 | void *ev_cb_arg; 138 | void *nfc_cache_rd_cb; // cache read callback function 139 | void *cache_read_cb_arg; 140 | unsigned int event_mask; 141 | int pwr_status; 142 | }; 143 | #endif 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif 148 | 149 | #endif 150 | -------------------------------------------------------------------------------- /sdk/src/sw/os/basic_types.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 | * 5 | * This program is free software; you can redistribute it and/or modify it 6 | * under the terms of version 2 of the GNU General Public License as 7 | * published by the Free Software Foundation. 8 | * 9 | * This program is distributed in the hope that it will be useful, but WITHOUT 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 | * more details. 13 | * 14 | * You should have received a copy of the GNU General Public License along with 15 | * this program; if not, write to the Free Software Foundation, Inc., 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 | * 18 | * 19 | ******************************************************************************/ 20 | #ifndef __BASIC_TYPES_H__ 21 | #define __BASIC_TYPES_H__ 22 | 23 | //#define PLATFORM_FREERTOS 24 | #include 25 | 26 | #define PLATFORM_LITTLE_ENDIAN 0 27 | #define PLATFORM_BIG_ENDIAN 1 28 | 29 | #define SYSTEM_ENDIAN PLATFORM_LITTLE_ENDIAN 30 | 31 | #define SUCCESS 0 32 | #define FAIL (-1) 33 | 34 | #undef _SUCCESS 35 | #define _SUCCESS 1 36 | 37 | #undef _FAIL 38 | #define _FAIL 0 39 | 40 | #ifndef FALSE 41 | #define FALSE 0 42 | #endif 43 | 44 | #ifndef TRUE 45 | #define TRUE (!FALSE) 46 | #endif 47 | 48 | #define _TRUE TRUE 49 | #define _FALSE FALSE 50 | 51 | #ifndef NULL 52 | #define NULL 0 53 | #endif 54 | 55 | #ifdef __GNUC__ 56 | #define __weak __attribute__((weak)) 57 | #define likely(x) __builtin_expect ((x), 1) 58 | #define unlikely(x) __builtin_expect ((x), 0) 59 | #endif 60 | 61 | typedef unsigned int uint; 62 | typedef signed int sint; 63 | 64 | 65 | #define s8 int8_t 66 | #define u8 uint8_t 67 | #define s16 int16_t 68 | #define u16 uint16_t 69 | #define s32 int32_t 70 | #define u32 uint32_t 71 | #define s64 int64_t 72 | #define u64 uint64_t 73 | 74 | typedef unsigned int BOOL; 75 | 76 | #define UCHAR uint8_t 77 | #define USHORT uint16_t 78 | #define UINT uint32_t 79 | #define ULONG uint32_t 80 | 81 | typedef struct { volatile int counter; } atomic_t; 82 | 83 | typedef enum _RTK_STATUS_ { 84 | _EXIT_SUCCESS = 0, 85 | _EXIT_FAILURE = 1 86 | }RTK_STATUS, *PRTK_STATUS; 87 | 88 | #define IN 89 | #define OUT 90 | #define VOID void 91 | #define INOUT 92 | #define NDIS_OID uint 93 | #define NDIS_STATUS uint 94 | 95 | #ifndef PVOID 96 | typedef void * PVOID; 97 | #endif 98 | 99 | typedef u32 dma_addr_t; 100 | 101 | typedef void (*proc_t)(void*); 102 | 103 | typedef unsigned int __kernel_size_t; 104 | typedef int __kernel_ssize_t; 105 | 106 | typedef __kernel_size_t SIZE_T; 107 | typedef __kernel_ssize_t SSIZE_T; 108 | #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) 109 | 110 | #define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) 111 | #define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) 112 | 113 | #define SIZE_PTR SIZE_T 114 | #define SSIZE_PTR SSIZE_T 115 | 116 | #ifndef ON 117 | #define ON 1 118 | #endif 119 | 120 | #ifndef OFF 121 | #define OFF 0 122 | #endif 123 | 124 | #ifndef ENABLE 125 | #define ENABLE 1 126 | #endif 127 | 128 | #ifndef DISABLE 129 | #define DISABLE 0 130 | #endif 131 | 132 | 133 | #define BIT0 0x0001 134 | #define BIT1 0x0002 135 | #define BIT2 0x0004 136 | #define BIT3 0x0008 137 | #define BIT4 0x0010 138 | #define BIT5 0x0020 139 | #define BIT6 0x0040 140 | #define BIT7 0x0080 141 | #define BIT8 0x0100 142 | #define BIT9 0x0200 143 | #define BIT10 0x0400 144 | #define BIT11 0x0800 145 | #define BIT12 0x1000 146 | #define BIT13 0x2000 147 | #define BIT14 0x4000 148 | #define BIT15 0x8000 149 | #define BIT16 0x00010000 150 | #define BIT17 0x00020000 151 | #define BIT18 0x00040000 152 | #define BIT19 0x00080000 153 | #define BIT20 0x00100000 154 | #define BIT21 0x00200000 155 | #define BIT22 0x00400000 156 | #define BIT23 0x00800000 157 | #define BIT24 0x01000000 158 | #define BIT25 0x02000000 159 | #define BIT26 0x04000000 160 | #define BIT27 0x08000000 161 | #define BIT28 0x10000000 162 | #define BIT29 0x20000000 163 | #define BIT30 0x40000000 164 | #define BIT31 0x80000000 165 | 166 | #define BIT_(__n) (1<<(__n)) 167 | 168 | #ifndef BIT 169 | #define BIT(__n) (1<<(__n)) 170 | #endif 171 | 172 | #define SECTION(_name) __attribute__ ((__section__(_name))) 173 | #define _PACKED_ __attribute__ ((packed)) 174 | #define _LONG_CALL_ __attribute__ ((long_call)) 175 | #define _WEAK __attribute__ ((weak)) 176 | 177 | 178 | 179 | //port from fw by thomas 180 | // TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness 181 | 182 | #define SWAP32(x) ((u32)( \ 183 | (((u32)(x) & (u32)0x000000ff) << 24) | \ 184 | (((u32)(x) & (u32)0x0000ff00) << 8) | \ 185 | (((u32)(x) & (u32)0x00ff0000) >> 8) | \ 186 | (((u32)(x) & (u32)0xff000000) >> 24))) 187 | 188 | #define WAP16(x) ((u16)( \ 189 | (((u16)(x) & (u16)0x00ff) << 8) | \ 190 | (((u16)(x) & (u16)0xff00) >> 8))) 191 | 192 | #if SYSTEM_ENDIAN == PLATFORM_LITTLE_ENDIAN 193 | #ifndef rtk_le16_to_cpu 194 | #define rtk_cpu_to_le32(x) ((u32)(x)) 195 | #define rtk_le32_to_cpu(x) ((u32)(x)) 196 | #define rtk_cpu_to_le16(x) ((u16)(x)) 197 | #define rtk_le16_to_cpu(x) ((u16)(x)) 198 | #define rtk_cpu_to_be32(x) SWAP32((x)) 199 | #define rtk_be32_to_cpu(x) SWAP32((x)) 200 | #define rtk_cpu_to_be16(x) WAP16((x)) 201 | #define rtk_be16_to_cpu(x) WAP16((x)) 202 | #endif 203 | 204 | #elif SYSTEM_ENDIAN == PLATFORM_BIG_ENDIAN 205 | #ifndef rtk_le16_to_cpu 206 | #define rtk_cpu_to_le32(x) SWAP32((x)) 207 | #define rtk_le32_to_cpu(x) SWAP32((x)) 208 | #define rtk_cpu_to_le16(x) WAP16((x)) 209 | #define rtk_le16_to_cpu(x) WAP16((x)) 210 | #define rtk_cpu_to_be32(x) ((__u32)(x)) 211 | #define rtk_be32_to_cpu(x) ((__u32)(x)) 212 | #define rtk_cpu_to_be16(x) ((__u16)(x)) 213 | #define rtk_be16_to_cpu(x) ((__u16)(x)) 214 | #endif 215 | #endif 216 | 217 | 218 | /* 219 | * Call endian free function when 220 | * 1. Read/write packet content. 221 | * 2. Before write integer to IO. 222 | * 3. After read integer from IO. 223 | */ 224 | 225 | // 226 | // Byte Swapping routine. 227 | // 228 | #define EF1Byte (u8) 229 | #define EF2Byte le16_to_cpu 230 | #define EF4Byte le32_to_cpu 231 | 232 | // 233 | // Read LE format data from memory 234 | // 235 | #define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) 236 | #define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) 237 | #define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) 238 | 239 | // 240 | // Write LE data to memory 241 | // 242 | #define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) 243 | #define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) 244 | #define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) 245 | 246 | // 247 | // Example: 248 | // BIT_LEN_MASK_32(0) => 0x00000000 249 | // BIT_LEN_MASK_32(1) => 0x00000001 250 | // BIT_LEN_MASK_32(2) => 0x00000003 251 | // BIT_LEN_MASK_32(32) => 0xFFFFFFFF 252 | // 253 | #define BIT_LEN_MASK_32(__BitLen) \ 254 | (0xFFFFFFFF >> (32 - (__BitLen))) 255 | // 256 | // Example: 257 | // BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 258 | // BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 259 | // 260 | #define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ 261 | (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) 262 | 263 | // 264 | // Description: 265 | // Return 4-byte value in host byte ordering from 266 | // 4-byte pointer in litten-endian system. 267 | // 268 | #define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ 269 | (EF4Byte(*((u32 *)(__pStart)))) 270 | 271 | // 272 | // Description: 273 | // Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to 274 | // 4-byte value in host byte ordering. 275 | // 276 | #define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ 277 | ( \ 278 | ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ 279 | & \ 280 | BIT_LEN_MASK_32(__BitLen) \ 281 | ) 282 | 283 | // 284 | // Description: 285 | // Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering 286 | // and return the result in 4-byte value in host byte ordering. 287 | // 288 | #define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ 289 | ( \ 290 | LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ 291 | & \ 292 | ( ~ BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ 293 | ) 294 | 295 | // 296 | // Description: 297 | // Set subfield of little-endian 4-byte value to specified value. 298 | // 299 | #define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ 300 | *((u32 *)(__pStart)) = \ 301 | EF4Byte( \ 302 | LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ 303 | | \ 304 | ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ 305 | ); 306 | 307 | 308 | #define BIT_LEN_MASK_16(__BitLen) \ 309 | (0xFFFF >> (16 - (__BitLen))) 310 | 311 | #define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ 312 | (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) 313 | 314 | #define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ 315 | (EF2Byte(*((u16 *)(__pStart)))) 316 | 317 | #define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ 318 | ( \ 319 | ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ 320 | & \ 321 | BIT_LEN_MASK_16(__BitLen) \ 322 | ) 323 | 324 | #define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ 325 | ( \ 326 | LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ 327 | & \ 328 | ( ~ BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ 329 | ) 330 | 331 | #define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ 332 | *((u16 *)(__pStart)) = \ 333 | EF2Byte( \ 334 | LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ 335 | | \ 336 | ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ 337 | ); 338 | 339 | #define BIT_LEN_MASK_8(__BitLen) \ 340 | (0xFF >> (8 - (__BitLen))) 341 | 342 | #define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ 343 | (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) 344 | 345 | #define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ 346 | (EF1Byte(*((u8 *)(__pStart)))) 347 | 348 | #define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ 349 | ( \ 350 | ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ 351 | & \ 352 | BIT_LEN_MASK_8(__BitLen) \ 353 | ) 354 | 355 | #define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ 356 | ( \ 357 | LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ 358 | & \ 359 | ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ 360 | ) 361 | 362 | #define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ 363 | *((u8 *)(__pStart)) = \ 364 | EF1Byte( \ 365 | LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ 366 | | \ 367 | ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ 368 | ); 369 | 370 | //pclint 371 | #define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ 372 | ( \ 373 | LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ 374 | ) 375 | 376 | //pclint 377 | #define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \ 378 | { \ 379 | *((pu1Byte)(__pStart)) = \ 380 | EF1Byte( \ 381 | LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \ 382 | | \ 383 | ((u1Byte)__Value) \ 384 | ); \ 385 | } 386 | 387 | 388 | 389 | // Get the N-bytes aligment offset from the current length 390 | #define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) 391 | 392 | typedef unsigned char BOOLEAN,*PBOOLEAN; 393 | 394 | #define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0) 395 | #define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag) 396 | #define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag)) 397 | #define CLEAR_FLAGS(__Flag) ((__Flag) = 0) 398 | #define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags)) 399 | 400 | /* Define compilor specific symbol */ 401 | // 402 | // inline function 403 | // 404 | 405 | #define __inline__ inline 406 | #define __inline inline 407 | #define __inline_definition inline 408 | 409 | // 410 | // pack 411 | // 412 | 413 | 414 | #define RTW_PACK_STRUCT_BEGIN 415 | #define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__)) 416 | #define RTW_PACK_STRUCT_END 417 | 418 | 419 | typedef struct _RAM_START_FUNCTION_ { 420 | VOID (*RamStartFun) (VOID); 421 | }RAM_START_FUNCTION, *PRAM_START_FUNCTION; 422 | 423 | typedef struct _RAM_FUNCTION_START_TABLE_ { 424 | VOID (*RamStartFun) (VOID); 425 | VOID (*RamWakeupFun) (VOID); 426 | VOID (*RamPatchFun0) (VOID); 427 | VOID (*RamPatchFun1) (VOID); 428 | VOID (*RamPatchFun2) (VOID); 429 | }RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE; 430 | 431 | #endif// __BASIC_TYPES_H__ 432 | -------------------------------------------------------------------------------- /sdk/src/sw/os/platform_options.h: -------------------------------------------------------------------------------- 1 | 2 | #ifndef __PLATFORM_OPTIONS_H__ 3 | #define __PLATFORM_OPTIONS_H__ 4 | 5 | 6 | 7 | /* 8 | * Target Platform Selection 9 | */ 10 | 11 | const static int SYSTEM_CLK = 166666666; 12 | const static int CPU_CLOCK_SEL_VALUE = 0; 13 | //const static int DRAM_TIMING_TCK = 20000; 14 | const static int SDR_CLOCK_SEL_VALUE = 1; 15 | 16 | 17 | // 18 | // Configuration for boot sequence 19 | // 20 | const static int CONFIG_MP=0; 21 | 22 | // 23 | // Config for modules 24 | // 25 | const static int CONFIG_SPIC_MODULE = 1; 26 | const static int CONFIG_SDR_EN = 1; 27 | 28 | // 29 | #define CONFIG_UART_LOG_HISTORY 1 30 | #define CONFIG_DEBUG_LOG 1 31 | #define CONFIG_CHIP_B_CUT 1 32 | 33 | 34 | // 35 | 36 | #undef CONFIG_TIMER_TEST 37 | #define CONFIG_TIMER_MODULE 1 38 | #undef CONFIG_WDG 39 | #define CONFIG_WDG_NON 1 40 | #define CONFIG_GDMA_EN 1 41 | #define CONFIG_GDMA_NORMAL 1 42 | #undef CONFIG_GDMA_TEST 43 | #define CONFIG_GDMA_MODULE 1 44 | #undef CONFIG_WIFI_EN 45 | #define CONFIG_GPIO_EN 1 46 | #define CONFIG_GPIO_NORMAL 1 47 | #undef CONFIG_GPIO_TEST 48 | #define CONFIG_GPIO_MODULE 1 49 | #undef CONFIG_SDIO_DEVICE_EN 50 | #undef CONFIG_SDIO_HOST_EN 51 | #undef CONFIG_USB_EN 52 | #define CONFIG_SPI_COM_EN 1 53 | #define CONFIG_SPI_COM_NORMAL 1 54 | #undef CONFIG_SPI_COM_TEST 55 | #define CONFIG_SPI_COM_MODULE 1 56 | #define CONFIG_UART_EN 1 57 | #define CONFIG_UART_NORMAL 1 58 | #undef CONFIG_UART_TEST 59 | #define CONFIG_UART_MODULE 1 60 | #define CONFIG_I2C_EN 1 61 | #define CONFIG_I2C_NORMAL 1 62 | #undef CONFIG_I2C_TEST 63 | #define CONFIG_I2C_MODULE 1 64 | #undef CONFIG_DEBUG_LOG_I2C_HAL 65 | #undef CONFIG_PCM_EN 66 | #define CONFIG_I2S_EN 1 67 | #define CONFIG_I2S_NORMAL 1 68 | #undef CONFIG_I2S_TEST 69 | #define CONFIG_I2S_MODULE 1 70 | #undef CONFIG_DEBUG_LOG_I2S_HAL 71 | #undef CONFIG_NFC_EN 72 | #undef CONFIG_NFC_NORMAL 73 | #undef CONFIG_NFC_TEST 74 | #define CONFIG_NFC_MODULE 1 75 | #undef CONFIG_SOC_PS_EN 76 | #undef CONFIG_MII_EN 77 | #define CONFIG_PWM_EN 1 78 | #define CONFIG_PWM_NORMAL 1 79 | #undef CONFIG_PWM_TEST 80 | #define CONFIG_PWM_MODULE 1 81 | #define CONFIG_EFUSE_EN 1 82 | #define CONFIG_EFUSE_NORMAL 1 83 | #undef CONFIG_EFUSE_TEST 84 | #define CONFIG_EFUSE_MODULE 1 85 | #define CONFIG_SDR_NORMAL 1 86 | #undef CONFIG_SDR_TEST 87 | #define CONFIG_SDR_MODULE 1 88 | #define CONFIG_SPIC_EN 1 89 | #define CONFIG_SPIC_NORMAL 1 90 | #undef CONFIG_SPIC_TEST 91 | 92 | #define CONFIG_ADC_EN 1 93 | #define CONFIG_DAC_EN 1 94 | #define CONFIG_DAC_NORMAL 1 95 | #undef CONFIG_DAC_TEST 96 | #define CONFIG_DAC_MODULE 1 97 | #define CONFIG_DEBUG_LOG_DAC_HAL 1 98 | #define CONFIG_NOR_FLASH 1 99 | #undef CONFIG_SPI_FLASH 100 | #undef CONFIG_NAND_FLASH 101 | #undef CONFIG_NONE_FLASH 102 | 103 | 104 | #endif // __PLATFORM_OPTIONS_H__ 105 | 106 | -------------------------------------------------------------------------------- /sdk/src/sw/os/section_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _SECTION_CONFIG_H_ 11 | #define _SECTION_CONFIG_H_ 12 | 13 | #include "basic_types.h" 14 | 15 | #define RAM_DEDECATED_VECTOR_TABLE_SECTION \ 16 | SECTION(".ram_dedecated_vector_table") 17 | 18 | #define RAM_USER_IRQ_FUN_TABLE_SECTION \ 19 | SECTION(".ram_user_define_irq_table") 20 | 21 | #define RAM_USER_IRQ_DATA_TABLE_SECTION \ 22 | SECTION(".ram_user_define_data_table") 23 | 24 | //3 Timer Section 25 | #define SECTION_RAM_TIMER2TO7_VECTOR_TABLE \ 26 | SECTION(".timer2_7_vector_table.data") 27 | 28 | #define SECTION_RAM_BSS_TIMER_RECORDER_TABLE \ 29 | SECTION(".timer.ram.data") 30 | 31 | #define TIMER_ROM_TEXT_SECTION \ 32 | SECTION(".timer.rom.text") 33 | 34 | #define TIMER_ROM_DATA_SECTION \ 35 | SECTION(".timer.rom.rodata") 36 | 37 | #define TIMER_RAM_TEXT_SECTION \ 38 | SECTION(".timer.ram.text") 39 | 40 | #define TIMER_RAM_DATA_SECTION \ 41 | SECTION(".timer.ram.data") 42 | 43 | 44 | //3 Wifi Section 45 | #define WIFI_ROM_TEXT_SECTION \ 46 | SECTION(".wifi.rom.text") 47 | 48 | #define WIFI_ROM_DATA_SECTION \ 49 | SECTION(".wifi.rom.rodata") 50 | 51 | #define WIFI_RAM_TEXT_SECTION \ 52 | SECTION(".wifi.ram.text") 53 | 54 | #define WIFI_RAM_DATA_SECTION \ 55 | SECTION(".wifi.ram.data") 56 | 57 | //3 Hal Section 58 | #define HAL_ROM_TEXT_SECTION \ 59 | SECTION(".hal.rom.text") 60 | 61 | #define HAL_ROM_DATA_SECTION \ 62 | SECTION(".hal.rom.rodata") 63 | 64 | #define HAL_RAM_TEXT_SECTION \ 65 | SECTION(".hal.ram.text") 66 | 67 | #define HAL_FLASH_TEXT_SECTION \ 68 | SECTION(".hal.flash.text") 69 | 70 | #define HAL_FLASH_DATA_SECTION \ 71 | SECTION(".hal.flash.data") 72 | 73 | #define HAL_SDRC_TEXT_SECTION \ 74 | SECTION(".hal.sdrc.text") 75 | 76 | #define HAL_SDRC_DATA_SECTION \ 77 | SECTION(".hal.sdrc.data") 78 | 79 | #define HAL_RAM_DATA_SECTION \ 80 | SECTION(".hal.ram.data") 81 | 82 | #define HAL_RAM_BSS_SECTION \ 83 | SECTION(".hal.ram.bss") 84 | 85 | #define HAL_ROM_OP_SECTION \ 86 | SECTION(".halop.rom.rodata") 87 | 88 | //3 Store the Image 1 validate code 89 | #define IMAGE1_VALID_PATTEN_SECTION \ 90 | SECTION(".image1.validate.rodata") 91 | 92 | #define IMAGE2_VALID_PATTEN_SECTION \ 93 | SECTION(".image2.validate.rodata") 94 | 95 | //3 Infra Section 96 | #define INFRA_ROM_TEXT_SECTION \ 97 | SECTION(".infra.rom.text") 98 | 99 | #define INFRA_ROM_DATA_SECTION \ 100 | SECTION(".infra.rom.rodata") 101 | 102 | #define INFRA_RAM_TEXT_SECTION \ 103 | SECTION(".infra.ram.text") 104 | 105 | #define INFRA_RAM_DATA_SECTION \ 106 | SECTION(".infra.ram.data") 107 | 108 | #define INFRA_RAM_BSS_SECTION \ 109 | SECTION(".infra.ram.bss") 110 | 111 | #define INFRA_START_SECTION \ 112 | SECTION(".infra.ram.start") 113 | 114 | 115 | //3 Pin Mutex Section 116 | #define PINMUX_ROM_TEXT_SECTION \ 117 | SECTION(".hal.rom.text") 118 | 119 | #define PINMUX_ROM_DATA_SECTION \ 120 | SECTION(".hal.rom.rodata") 121 | 122 | #define PINMUX_RAM_TEXT_SECTION \ 123 | SECTION(".hal.ram.text") 124 | 125 | #define PINMUX_RAM_DATA_SECTION \ 126 | SECTION(".hal.ram.data") 127 | 128 | #define PINMUX_RAM_BSS_SECTION \ 129 | SECTION(".hal.ram.bss") 130 | 131 | 132 | //3 Monitor App Section 133 | #define MON_ROM_TEXT_SECTION \ 134 | SECTION(".mon.rom.text") 135 | 136 | #define MON_ROM_DATA_SECTION \ 137 | SECTION(".mon.rom.rodata") 138 | 139 | #define MON_RAM_TEXT_SECTION \ 140 | SECTION(".mon.ram.text") 141 | 142 | #define MON_RAM_DATA_SECTION \ 143 | SECTION(".mon.ram.data") 144 | 145 | #define MON_RAM_BSS_SECTION \ 146 | SECTION(".mon.ram.bss") 147 | 148 | 149 | //3 SDIO Section 150 | #define SECTION_SDIO_RAM 151 | #define SECTION_SDIO_ROM 152 | 153 | //3 SRAM Config Section 154 | #define SRAM_BD_DATA_SECTION \ 155 | SECTION(".bdsram.data") 156 | 157 | #define SRAM_BF_DATA_SECTION \ 158 | SECTION(".bfsram.data") 159 | 160 | 161 | #define START_RAM_FUN_SECTION \ 162 | SECTION(".start.ram.data") 163 | 164 | #define START_RAM_FUN_A_SECTION \ 165 | SECTION(".start.ram.data.a") 166 | 167 | #define START_RAM_FUN_B_SECTION \ 168 | SECTION(".start.ram.data.b") 169 | 170 | #define START_RAM_FUN_C_SECTION \ 171 | SECTION(".start.ram.data.c") 172 | 173 | #define START_RAM_FUN_D_SECTION \ 174 | SECTION(".start.ram.data.d") 175 | 176 | #define START_RAM_FUN_E_SECTION \ 177 | SECTION(".start.ram.data.e") 178 | 179 | #define IMAGE2_START_RAM_FUN_SECTION \ 180 | SECTION(".image2.ram.data") 181 | 182 | #define SDRAM_DATA_SECTION \ 183 | SECTION(".sdram.data") 184 | 185 | //3 Wlan Section 186 | #define WLAN_ROM_TEXT_SECTION \ 187 | SECTION(".wlan.rom.text") 188 | 189 | #define WLAN_ROM_DATA_SECTION \ 190 | SECTION(".wlan.rom.rodata") 191 | 192 | #define WLAN_RAM_MAP_SECTION \ 193 | SECTION(".wlan_ram_map") 194 | 195 | //3 Apple Section 196 | #define APPLE_ROM_TEXT_SECTION \ 197 | SECTION(".apple.rom.text") 198 | 199 | #define APPLE_ROM_DATA_SECTION \ 200 | SECTION(".apple.rom.rodata") 201 | 202 | //3 Libc Section 203 | #define LIBC_ROM_TEXT_SECTION \ 204 | SECTION(".libc.rom.text") 205 | 206 | #define LIBC_ROM_DATA_SECTION \ 207 | SECTION(".libc.rom.rodata") 208 | 209 | #define LIBC_RAM_BSS_SECTION \ 210 | SECTION(".libc.ram.bss") 211 | 212 | #endif //_SECTION_CONFIG_H_ 213 | -------------------------------------------------------------------------------- /sdk/src/targets/cmsis/target_rtk/target_8195a/app_start.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #include "rtl8195a.h" 11 | //#include "build_info.h" 12 | 13 | 14 | 15 | 16 | extern int main( void ); 17 | 18 | #ifdef PLATFORM_RTX 19 | extern void SVC_Handler (void); 20 | extern void PendSV_Handler (void); 21 | extern void SysTick_Handler (void); 22 | #endif 23 | 24 | 25 | 26 | 27 | // The Main App entry point 28 | void _AppStart(void) 29 | { 30 | #ifdef PLATFORM_RTX 31 | InterruptForOSInit((VOID*)SVC_Handler, 32 | (VOID*)PendSV_Handler, 33 | (VOID*)SysTick_Handler); 34 | __asm ( 35 | "ldr r0, =SystemInit\n" 36 | "blx r0\n" 37 | "ldr r0, =_start\n" 38 | "bx r0\n" 39 | ); 40 | 41 | DiagPrintf("OS system finished\n"); 42 | #else 43 | 44 | main(); 45 | 46 | #endif // end of else of "#ifdef CONFIG_MBED_ENABLED" 47 | 48 | } 49 | -------------------------------------------------------------------------------- /sdk/src/targets/cmsis/target_rtk/target_8195a/cmsis.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * A generic CMSIS include header 3 | ******************************************************************************* 4 | * Copyright (c) 2014, STMicroelectronics 5 | * All rights reserved. 6 | * 7 | * Redistribution and use in source and binary forms, with or without 8 | * modification, are permitted provided that the following conditions are met: 9 | * 10 | * 1. Redistributions of source code must retain the above copyright notice, 11 | * this list of conditions and the following disclaimer. 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, 13 | * this list of conditions and the following disclaimer in the documentation 14 | * and/or other materials provided with the distribution. 15 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 16 | * may be used to endorse or promote products derived from this software 17 | * without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | ******************************************************************************* 30 | */ 31 | 32 | #ifndef MBED_CMSIS_H 33 | #define MBED_CMSIS_H 34 | 35 | #include "rtl8195a.h" 36 | #include "cmsis_nvic.h" 37 | 38 | #endif 39 | -------------------------------------------------------------------------------- /sdk/src/targets/cmsis/target_rtk/target_8195a/cmsis_nvic.h: -------------------------------------------------------------------------------- 1 | /* mbed Microcontroller Library 2 | * CMSIS-style functionality to support dynamic vectors 3 | ******************************************************************************* 4 | * Copyright (c) 2014, STMicroelectronics 5 | * All rights reserved. 6 | * 7 | * Redistribution and use in source and binary forms, with or without 8 | * modification, are permitted provided that the following conditions are met: 9 | * 10 | * 1. Redistributions of source code must retain the above copyright notice, 11 | * this list of conditions and the following disclaimer. 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, 13 | * this list of conditions and the following disclaimer in the documentation 14 | * and/or other materials provided with the distribution. 15 | * 3. Neither the name of STMicroelectronics nor the names of its contributors 16 | * may be used to endorse or promote products derived from this software 17 | * without specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | ******************************************************************************* 30 | */ 31 | 32 | #ifndef MBED_CMSIS_NVIC_H 33 | #define MBED_CMSIS_NVIC_H 34 | 35 | // CORE: 64 vectors = 64 bytes from 0x00 to 0x3F 36 | // MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ... 37 | // Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM 38 | #define NVIC_NUM_VECTORS 128 39 | #define NVIC_USER_IRQ_OFFSET 64 40 | 41 | #include "cmsis.h" 42 | 43 | #ifdef __cplusplus 44 | extern "C" { 45 | #endif 46 | 47 | void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); 48 | uint32_t NVIC_GetVector(IRQn_Type IRQn); 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif 55 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_adc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_ADC_H_ 11 | #define _HAL_ADC_H_ 12 | 13 | #include "rtl8195a.h" 14 | #include "rtl8195a_adc.h" 15 | #include "hal_gdma.h" 16 | 17 | //================ ADC Configuration ========================= 18 | #define ADC_INTR_OP_TYPE 1 19 | #define ADC_DMA_OP_TYPE 1 20 | 21 | // ADC SAL management macros 22 | #define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT)) 23 | 24 | // ADC used module. 25 | // Please set the ADC module flag to 1 to enable the related 26 | #define ADC0_USED 1 27 | #define ADC1_USED 1 28 | #define ADC2_USED 1 29 | #define ADC3_USED 1 30 | 31 | 32 | //================ Debug MSG Definition ======================= 33 | #define ADC_PREFIX "RTL8195A[adc]: " 34 | #define ADC_PREFIX_LVL " [ADC_DBG]: " 35 | 36 | typedef enum _ADC_DBG_LVL_ { 37 | HAL_ADC_LVL = 0x01, 38 | SAL_ADC_LVL = 0x02, 39 | VERI_ADC_LVL = 0x04, 40 | }ADC_DBG_LVL,*PADC_DBG_LVL; 41 | 42 | #ifdef CONFIG_DEBUG_LOG 43 | #ifdef CONFIG_DEBUG_LOG_ADC_HAL 44 | 45 | #define DBG_8195A_ADC(...) do{ \ 46 | _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\ 47 | }while(0) 48 | 49 | 50 | #define ADCDBGLVL 0xFF 51 | #define DBG_8195A_ADC_LVL(LVL,...) do{\ 52 | if (LVL&ADCDBGLVL){\ 53 | _DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\ 54 | }\ 55 | }while(0) 56 | #else 57 | #define DBG_ADC_LOG_PERD 100 58 | #define DBG_8195A_ADC(...) 59 | #define DBG_8195A_ADC_LVL(...) 60 | #endif 61 | #endif 62 | 63 | 64 | //================ ADC HAL Related Enumeration ================== 65 | // ADC Module Selection 66 | typedef enum _ADC_MODULE_SEL_ { 67 | ADC0_SEL = 0x0, 68 | ADC1_SEL = 0x1, 69 | ADC2_SEL = 0x2, 70 | ADC3_SEL = 0x3, 71 | }ADC_MODULE_SEL,*PADC_MODULE_SEL; 72 | 73 | // ADC module status 74 | typedef enum _ADC_MODULE_STATUS_ { 75 | ADC_DISABLE = 0x0, 76 | ADC_ENABLE = 0x1, 77 | }ADC_MODULE_STATUS, *PADC_MODULE_STATUS; 78 | 79 | // ADC Data Endian 80 | typedef enum _ADC_DATA_ENDIAN_ { 81 | ADC_DATA_ENDIAN_LITTLE = 0x0, 82 | ADC_DATA_ENDIAN_BIG = 0x1, 83 | }ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN; 84 | 85 | // ADC Debug Select 86 | typedef enum _ADC_DEBUG_SEL_ { 87 | ADC_DBG_SEL_DISABLE = 0x0, 88 | ADC_DBG_SEL_ENABLE = 0x1, 89 | }ADC_DEBUG_SEL,*PADC_DEBUG_SEL; 90 | 91 | typedef enum _ADC_COMPARE_SET_ { 92 | ADC_COMP_SMALLER_THAN = 0x0, 93 | ADC_COMP_GREATER_THAN = 0x1, 94 | }ADC_COMPARE_SET, *PADC_COMPARE_SET; 95 | 96 | // ADC feature status 97 | typedef enum _ADC_FEATURE_STATUS_{ 98 | ADC_FEATURE_DISABLED = 0, 99 | ADC_FEATURE_ENABLED = 1, 100 | }ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS; 101 | 102 | // ADC operation type 103 | typedef enum _ADC_OP_TYPE_ { 104 | ADC_RDREG_TYPE = 0x0, 105 | ADC_DMA_TYPE = 0x1, 106 | ADC_INTR_TYPE = 0x2, 107 | }ADC_OP_TYPE, *PADC_OP_TYPE; 108 | 109 | // ADC device status 110 | typedef enum _ADC_DEVICE_STATUS_ { 111 | ADC_STS_UNINITIAL = 0x00, 112 | ADC_STS_INITIALIZED = 0x01, 113 | ADC_STS_IDLE = 0x02, 114 | 115 | ADC_STS_TX_READY = 0x03, 116 | ADC_STS_TX_ING = 0x04, 117 | 118 | ADC_STS_RX_READY = 0x05, 119 | ADC_STS_RX_ING = 0x06, 120 | 121 | ADC_STS_ERROR = 0x07, 122 | ADC_STS_FULL = 0x08, 123 | }ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS; 124 | 125 | // ADC error type 126 | typedef enum _ADC_ERR_TYPE_ { 127 | ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error 128 | }ADC_ERR_TYPE, *PADC_ERR_TYPE; 129 | 130 | // ADC initial status 131 | typedef enum _ADC_INITAIL_STATUS_ { 132 | ADC0_INITED = 0x1, 133 | ADC1_INITED = 0x2, 134 | ADC2_INITED = 0x4, 135 | ADC3_INITED = 0x8, 136 | }ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS; 137 | 138 | 139 | //================ ADC HAL Data Structure ====================== 140 | // ADC HAL initial data structure 141 | typedef struct _HAL_ADC_INIT_DAT_ { 142 | u8 ADCIdx; //ADC index used 143 | u8 ADCEn; //ADC module enable 144 | u8 ADCEndian; //ADC endian selection, 145 | //but actually it's for 32-bit ADC data swap control 146 | //1'b0: no swap, 147 | //1'b1: swap the upper 16-bit and the lower 16-bit 148 | u8 ADCBurstSz; //ADC DMA operation threshold 149 | 150 | u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable) 151 | u8 ADCOneShotEn; //ADC one-shot mode enable 152 | u8 ADCOverWREn; //ADC overwrite mode enable 153 | u8 ADCOneShotTD; //ADC one shot mode threshold 154 | 155 | u16 ADCCompCtrl; //ADC compare mode control, 156 | //1'b0:less than the compare threshold 157 | //1'b1:greater than the compare threshod 158 | u16 ADCCompTD; //ADC compare mode threshold 159 | 160 | u8 ADCDataRate; //ADC down sample data rate, 161 | u8 ADCAudioEn; //ADC audio mode enable 162 | u8 ADCEnManul; //ADC enable manually 163 | u8 ADCDbgSel; 164 | 165 | u32 RSVD0; 166 | 167 | u32 *ADCData; //ADC data pointer 168 | u32 ADCPWCtrl; //ADC0 power control 169 | u32 ADCIntrMSK; //ADC Interrupt Mask 170 | u32 ADCAnaParAd3; //ADC analog parameter 3 171 | }HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT; 172 | 173 | // ADC HAL Operations 174 | typedef struct _HAL_ADC_OP_ { 175 | RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization 176 | RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization 177 | RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization 178 | u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive 179 | RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control 180 | u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register 181 | }HAL_ADC_OP, *PHAL_ADC_OP; 182 | 183 | // ADC user callback adapter 184 | typedef struct _SAL_ADC_USERCB_ADPT_ { 185 | VOID (*USERCB) (VOID *Data); 186 | u32 USERData; 187 | }SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT; 188 | 189 | // ADC user callback structure 190 | typedef struct _SAL_ADC_USER_CB_ { 191 | PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback 192 | PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback 193 | PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback 194 | PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback 195 | PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback 196 | PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback 197 | PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback 198 | PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback 199 | PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback 200 | PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback 201 | }SAL_ADC_USER_CB, *PSAL_ADC_USER_CB; 202 | 203 | // ADC Transmit Buffer 204 | typedef struct _SAL_ADC_TRANSFER_BUF_ { 205 | u32 DataLen; //ADC Transmfer Length 206 | u32 *pDataBuf; //ADC Transfer Buffer Pointer 207 | u32 RSVD; // 208 | }SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF; 209 | 210 | // Software API Level ADC Handler 211 | typedef struct _SAL_ADC_HND_ { 212 | u8 DevNum; //ADC device number 213 | u8 PinMux; //ADC pin mux seletion 214 | u8 OpType; //ADC operation type selection 215 | volatile u8 DevSts; //ADC device status 216 | 217 | u32 ADCExd; //ADC extended options: 218 | //bit 0: example 219 | //bit 31~bit 1: Reserved 220 | u32 ErrType; // 221 | u32 TimeOut; //ADC IO Timeout count 222 | 223 | PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct 224 | PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer 225 | PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback 226 | }SAL_ADC_HND, *PSAL_ADC_HND; 227 | 228 | // ADC SAL handle private 229 | typedef struct _SAL_ADC_HND_PRIV_ { 230 | VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer 231 | SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND 232 | }SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV; 233 | 234 | //ADC SAL management adapter 235 | typedef struct _SAL_ADC_MNGT_ADPT_ { 236 | PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND 237 | PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT ) 238 | PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP ) 239 | VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function 240 | 241 | PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) 242 | VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function 243 | VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL ADC initialize function 244 | PHAL_GDMA_ADAPTER pHalGdmaAdp; 245 | PHAL_GDMA_OP pHalGdmaOp; 246 | 247 | VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL I2C interrupt function 248 | PIRQ_HANDLE pIrqGdmaHnd; 249 | PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB ) 250 | }SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT; 251 | 252 | 253 | //================ ADC HAL Function Prototype =================== 254 | // ADC HAL inline function 255 | // For checking I2C input index valid or not 256 | static inline RTK_STATUS 257 | RtkADCIdxChk( 258 | IN u8 ADCIdx 259 | ) 260 | { 261 | #if !ADC0_USED 262 | if (ADCIdx == ADC0_SEL) 263 | return _EXIT_FAILURE; 264 | #endif 265 | 266 | #if !ADC1_USED 267 | if (ADCIdx == ADC1_SEL) 268 | return _EXIT_FAILURE; 269 | #endif 270 | 271 | #if !ADC2_USED 272 | if (ADCIdx == ADC2_SEL) 273 | return _EXIT_FAILURE; 274 | #endif 275 | 276 | #if !ADC3_USED 277 | if (ADCIdx == ADC3_SEL) 278 | return _EXIT_FAILURE; 279 | #endif 280 | 281 | return _EXIT_SUCCESS; 282 | } 283 | 284 | VOID HalADCOpInit(IN VOID *Data); 285 | PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx); 286 | RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND); 287 | RTK_STATUS RtkADCLoadDefault(IN VOID *Data); 288 | RTK_STATUS RtkADCInit(IN VOID *Data); 289 | RTK_STATUS RtkADCDeInit(IN VOID *Data); 290 | //RTK_STATUS RtkADCReceive(IN VOID *Data); 291 | u32 RtkADCReceive(IN VOID *Data); 292 | u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf); 293 | uint32_t RtkADCReceiveBuf_for_random(IN VOID *Data); 294 | 295 | PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx); 296 | RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt); 297 | VOID ADCISRHandle(IN VOID *Data); 298 | VOID ADCGDMAISRHandle(IN VOID *Data); 299 | 300 | #endif 301 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_api.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | #ifndef _HAL_API_H_ 10 | #define _HAL_API_H_ 11 | 12 | #define HAL_READ32(base, addr) \ 13 | rtk_le32_to_cpu(*((volatile u32*)(base + addr))) 14 | 15 | #define HAL_WRITE32(base, addr, value32) \ 16 | ((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32)) 17 | 18 | 19 | #define HAL_READ16(base, addr) \ 20 | rtk_le16_to_cpu(*((volatile u16*)(base + addr))) 21 | 22 | #define HAL_WRITE16(base, addr, value) \ 23 | ((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value)) 24 | 25 | 26 | #define HAL_READ8(base, addr) \ 27 | (*((volatile u8*)(base + addr))) 28 | 29 | #define HAL_WRITE8(base, addr, value) \ 30 | ((*((volatile u8*)(base + addr))) = value) 31 | 32 | #define PinCtrl HalPinCtrlRtl8195A 33 | 34 | #define DiagPutChar HalSerialPutcRtl8195a 35 | #define DiagGetChar HalSerialGetcRtl8195a 36 | #define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a 37 | #define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a 38 | 39 | #define InterruptForOSInit VectorTableInitForOSRtl8195A 40 | #define InterruptRegister VectorIrqRegisterRtl8195A 41 | #define InterruptUnRegister VectorIrqUnRegisterRtl8195A 42 | 43 | #define InterruptEn VectorIrqEnRtl8195A 44 | #define InterruptDis VectorIrqDisRtl8195A 45 | 46 | #define SpicFlashInit SpicFlashInitRtl8195A 47 | #define Calibration32k En32KCalibration 48 | #define WDGInit InitWDGIRQ 49 | 50 | typedef enum _HAL_Status 51 | { 52 | HAL_OK = 0x00, 53 | HAL_BUSY = 0x01, 54 | HAL_TIMEOUT = 0x02, 55 | HAL_ERR_PARA = 0x03, // error with invaild parameters 56 | HAL_ERR_MEM = 0x04, // error with memory allocation failed 57 | HAL_ERR_HW = 0x05, // error with hardware error 58 | 59 | HAL_ERR_UNKNOWN = 0xee // unknown error 60 | 61 | } HAL_Status; 62 | 63 | 64 | #endif //_HAL_API_H_ 65 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_dac.h: -------------------------------------------------------------------------------- 1 | //====================================================== 2 | // Routines to access hardware 3 | // 4 | // Copyright (c) 2013 Realtek Semiconductor Corp. 5 | // 6 | // This module is a confidential and proprietary property of RealTek and 7 | // possession or use of this module requires written permission of RealTek. 8 | //====================================================== 9 | #ifndef _HAL_DAC_H_ 10 | #define _HAL_DAC_H_ 11 | 12 | #include "rtl8195a_dac.h" 13 | #include "hal_api.h" 14 | #include "hal_gdma.h" 15 | 16 | //#include "cmsis_os.h" 17 | 18 | //================ DAC Configuration ========================= 19 | #define DAC_INTR_OP_TYPE 1 20 | #define DAC_DMA_OP_TYPE 1 21 | 22 | // DAC SAL management macros 23 | #define SAL_DAC_USER_CB_NUM (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT)) 24 | 25 | // DAC SAL used module. 26 | // Please set the DAC module flag to 1 to enable the related DAC module functions. 27 | #define DAC0_USED 1 28 | #define DAC1_USED 1 29 | 30 | 31 | //================ Debug MSG Definition ======================= 32 | #define DAC_PREFIX "RTL8195A[dac]: " 33 | #define DAC_PREFIX_LVL " [DAC_DBG]: " 34 | 35 | typedef enum _DAC_DBG_LVL_ { 36 | HAL_DAC_LVL = 0x00, 37 | SAL_DAC_LVL = 0x02, 38 | VERI_DAC_LVL = 0x04, 39 | }DAC_DBG_LVL,*PDAC_DBG_LVL; 40 | 41 | #ifdef CONFIG_DEBUG_LOG 42 | #ifdef CONFIG_DEBUG_LOG_DAC_HAL 43 | 44 | #define DBG_8195A_DAC(...) do{ \ 45 | _DbgDump("\r"DAC_PREFIX __VA_ARGS__);\ 46 | }while(0) 47 | 48 | 49 | #define DACDBGLVL 0xFF 50 | #define DBG_8195A_DAC_LVL(LVL,...) do{\ 51 | if (LVL&DACDBGLVL){\ 52 | _DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\ 53 | }\ 54 | }while(0) 55 | #else 56 | #define DBG_DAC_LOG_PERD 100 57 | #define DBG_8195A_DAC(...) 58 | #define DBG_8195A_DAC_LVL(...) 59 | #endif 60 | #endif 61 | 62 | 63 | //================ DAC HAL Related Enumeration ================== 64 | // DAC Module Selection 65 | typedef enum _DAC_MODULE_SEL_ { 66 | DAC0_SEL = 0x0, 67 | DAC1_SEL = 0x1, 68 | }DAC_MODULE_SEL,*PDAC_MODULE_SEL; 69 | 70 | // DAC module status 71 | typedef enum _DAC_MODULE_STATUS_ { 72 | DAC_DISABLE = 0x0, 73 | DAC_ENABLE = 0x1, 74 | }DAC_MODULE_STATUS, *PDAC_MODULE_STATUS; 75 | 76 | // DAC Data Rate 77 | typedef enum _DAC_DATA_RATE_ { 78 | DAC_DATA_RATE_10K = 0x0, 79 | DAC_DATA_RATE_250K = 0x1, 80 | }DAC_DATA_RATE,*PDAC_DATA_RATE; 81 | 82 | // DAC Data Endian 83 | typedef enum _DAC_DATA_ENDIAN_ { 84 | DAC_DATA_ENDIAN_LITTLE = 0x0, 85 | DAC_DATA_ENDIAN_BIG = 0x1, 86 | }DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN; 87 | 88 | // DAC Debug Select 89 | typedef enum _DAC_DEBUG_SEL_ { 90 | DAC_DBG_SEL_DISABLE = 0x0, 91 | DAC_DBG_SEL_ENABLE = 0x1, 92 | }DAC_DEBUG_SEL,*PDAC_DEBUG_SEL; 93 | 94 | // DAC Dsc Debug Select 95 | typedef enum _DAC_DSC_DEBUG_SEL_ { 96 | DAC_DSC_DBG_SEL_DISABLE = 0x0, 97 | DAC_DSC_DBG_SEL_ENABLE = 0x1, 98 | }DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL; 99 | 100 | 101 | // DAC Bypass Dsc Debug Select 102 | typedef enum _DAC_BYPASS_DSC_SEL_ { 103 | DAC_BYPASS_DSC_SEL_DISABLE = 0x0, 104 | DAC_BYPASS_DSC_SEL_ENABLE = 0x1, 105 | }DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL; 106 | 107 | // DAC feature status 108 | typedef enum _DAC_FEATURE_STATUS_{ 109 | DAC_FEATURE_DISABLED = 0, 110 | DAC_FEATURE_ENABLED = 1, 111 | }DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS; 112 | 113 | // DAC operation type 114 | typedef enum _DAC_OP_TYPE_ { 115 | DAC_POLL_TYPE = 0x0, 116 | DAC_DMA_TYPE = 0x1, 117 | DAC_INTR_TYPE = 0x2, 118 | }DAC_OP_TYPE, *PDAC_OP_TYPE; 119 | 120 | // DAC device status 121 | typedef enum _DAC_Device_STATUS_ { 122 | DAC_STS_UNINITIAL = 0x00, 123 | DAC_STS_INITIALIZED = 0x01, 124 | DAC_STS_IDLE = 0x02, 125 | 126 | DAC_STS_TX_READY = 0x03, 127 | DAC_STS_TX_ING = 0x04, 128 | 129 | DAC_STS_RX_READY = 0x05, 130 | DAC_STS_RX_ING = 0x06, 131 | 132 | DAC_STS_ERROR = 0x07, 133 | }DAC_Device_STATUS, *PDAC_Device_STATUS; 134 | 135 | //DAC device error type 136 | typedef enum _DAC_ERR_TYPE_ { 137 | DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow. 138 | DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically. 139 | DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register. 140 | DAC_ERR_FIFO_DSC_OVER0 = 0x20, 141 | DAC_ERR_FIFO_DSC_OVER1 = 0x40, 142 | }DAC_ERR_TYPE, *PDAC_ERR_TYPE; 143 | 144 | 145 | //====================================================== 146 | // DAC HAL initial data structure 147 | typedef struct _HAL_DAC_INIT_DAT_ { 148 | u8 DACIdx; //DAC index used 149 | u8 DACEn; //DAC module enable 150 | u8 DACDataRate; //DAC data rate, 1'b0:10KHz, 1'b1:250KHz 151 | u8 DACEndian; //DAC endian selection, 152 | //but actually it's for 32-bit DAC data swap control 153 | //1'b0: no swap, 154 | //1'b1: swap the upper 16-bit and the lower 16-bit 155 | u8 DACFilterSet; //DAC filter settle 156 | u8 DACBurstSz; //DAC burst size 157 | u8 DACDbgSel; //DAC debug sel 158 | u8 DACDscDbgSel; //DAC debug dsc sel 159 | 160 | u8 DACBPDsc; //DAC bypass delta sigma for loopback 161 | u8 DACDeltaSig; //DAC bypass value of delta sigma 162 | u16 RSVD1; 163 | 164 | 165 | 166 | u32 *DACData; //DAC data pointer 167 | u32 DACPWCtrl; //DAC0 and DAC1 power control 168 | u32 DACAnaCtrl0; //DAC anapar_da control 0 169 | u32 DACAnaCtrl1; //DAC anapar_da control 1 170 | u32 DACIntrMSK; //DAC Interrupt Mask 171 | }HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT; 172 | 173 | // DAC HAL Operations 174 | typedef struct _HAL_DAC_OP_ { 175 | RTK_STATUS (*HalDACInit) (VOID *Data); //HAL DAC initialization 176 | RTK_STATUS (*HalDACDeInit) (VOID *Data); //HAL DAC de-initialization 177 | RTK_STATUS (*HalDACEnable) (VOID *Data); //HAL DAC de-initialization 178 | u8 (*HalDACSend) (VOID *Data); //HAL DAC receive 179 | RTK_STATUS (*HalDACIntrCtrl) (VOID *Data); //HAL DAC interrupt control 180 | u32 (*HalDACReadReg) (VOID *Data, u8 DACReg);//HAL DAC read register 181 | }HAL_DAC_OP, *PHAL_DAC_OP; 182 | 183 | // DAC user callback adapter 184 | typedef struct _SAL_DAC_USERCB_ADPT_ { 185 | VOID (*USERCB) (VOID *Data); 186 | u32 USERData; 187 | }SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT; 188 | 189 | // DAC user callback structure 190 | typedef struct _SAL_DAC_USER_CB_ { 191 | PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback 192 | PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback 193 | PSAL_DAC_USERCB_ADPT pRXCB; //DAC Receive Callback 194 | PSAL_DAC_USERCB_ADPT pRXCCB; //DAC Receive Complete Callback 195 | PSAL_DAC_USERCB_ADPT pRDREQCB; //DAC Read Request Callback 196 | PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback 197 | PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback 198 | PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback 199 | PSAL_DAC_USERCB_ADPT pDMARXCB; //DAC DMA Receive Callback 200 | PSAL_DAC_USERCB_ADPT pDMARXCCB; //DAC DMA Receive Complete Callback 201 | }SAL_DAC_USER_CB, *PSAL_DAC_USER_CB; 202 | 203 | // DAC Transmit Buffer 204 | typedef struct _SAL_DAC_TRANSFER_BUF_ { 205 | u32 DataLen; //DAC Transmfer Length 206 | u32 *pDataBuf; //DAC Transfer Buffer Pointer 207 | u32 RSVD; // 208 | }SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF; 209 | 210 | // Software API Level DAC Handler 211 | typedef struct _SAL_DAC_HND_ { 212 | u8 DevNum; //DAC device number 213 | u8 PinMux; //DAC pin mux seletion 214 | u8 OpType; //DAC operation type selection 215 | volatile u8 DevSts; //DAC device status 216 | 217 | u32 DACExd; //I2C extended options: 218 | //bit 0: example 219 | //bit 31~bit 1: Reserved 220 | u32 ErrType; // 221 | u32 TimeOut; //I2C IO Timeout count 222 | 223 | PHAL_DAC_INIT_DAT pInitDat; //Pointer to I2C initial data struct 224 | PSAL_DAC_TRANSFER_BUF pTXBuf; //Pointer to I2C TX buffer 225 | PSAL_DAC_USER_CB pUserCB; //Pointer to I2C User Callback 226 | }SAL_DAC_HND, *PSAL_DAC_HND; 227 | 228 | // DAC SAL handle private 229 | typedef struct _SAL_DAC_HND_PRIV_ { 230 | VOID **ppSalDACHnd; //Pointer to SAL_I2C_HND pointer 231 | SAL_DAC_HND SalDACHndPriv; //Private SAL_I2C_HND 232 | }SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV; 233 | 234 | //DAC SAL management adapter 235 | typedef struct _SAL_DAC_MNGT_ADPT_ { 236 | PSAL_DAC_HND_PRIV pSalHndPriv; //Pointer to SAL_DAC_HND 237 | PHAL_DAC_INIT_DAT pHalInitDat; //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT ) 238 | PHAL_DAC_OP pHalOp; //Pointer to HAL DAC operation( HAL_DAC_OP ) 239 | PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE ) 240 | 241 | PHAL_GDMA_ADAPTER pHalGdmaAdp; 242 | PHAL_GDMA_OP pHalGdmaOp; 243 | PIRQ_HANDLE pIrqGdmaHnd; 244 | 245 | PSAL_DAC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_DAC_USER_CB ) 246 | 247 | //NeoJou 248 | // osThreadId thread_id; 249 | }SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT; 250 | 251 | 252 | //================ DAC HAL Function Prototype =================== 253 | // DAC HAL inline function 254 | // For checking DAC input index valid or not 255 | static inline RTK_STATUS 256 | RtkDACIdxChk( 257 | IN u8 DACIdx 258 | ) 259 | { 260 | #if !DAC0_USED 261 | if (DACIdx == DAC0_SEL) 262 | return _EXIT_FAILURE; 263 | #endif 264 | 265 | #if !DAC1_USED 266 | if (DACIdx == DAC1_SEL) 267 | return _EXIT_FAILURE; 268 | #endif 269 | 270 | return _EXIT_SUCCESS; 271 | } 272 | 273 | VOID HalDACOpInit(IN VOID *Data); 274 | RTK_STATUS RtkDACLoadDefault(IN VOID *Data); 275 | RTK_STATUS RtkDACInit(IN VOID *Data); 276 | RTK_STATUS RtkDACDeInit(IN VOID *Data); 277 | extern RTK_STATUS RtkDACSend(IN VOID *Data); 278 | //extern osEvent RtkDACWait(void); 279 | PSAL_DAC_HND RtkDACGetSalHnd(IN u8 DACIdx); 280 | RTK_STATUS RtkDACFreeSalHnd(IN PSAL_DAC_HND pSalDACHND); 281 | PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN u8 DACIdx); 282 | RTK_STATUS RtkDACFreeMngtAdpt(IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt); 283 | 284 | #endif 285 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_diag.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_DIAG_H_ 11 | #define _HAL_DIAG_H_ 12 | 13 | 14 | //Register offset 15 | #define UART_REV_BUF_OFF 0x00 16 | #define UART_TRAN_HOLD_OFF 0x00 17 | #define UART_DLH_OFF 0x04 18 | #define UART_DLL_OFF 0x00 19 | #define UART_INTERRUPT_EN_REG_OFF 0x04 20 | #define UART_INTERRUPT_IDEN_REG_OFF 0x08 21 | #define UART_FIFO_CTL_REG_OFF 0x08 22 | #define UART_LINE_CTL_REG_OFF 0x0c 23 | #define UART_MODEM_CTL_REG_OFF 0x10 24 | #define UART_LINE_STATUS_REG_OFF 0x14 25 | #define UART_MODEM_STATUS_REG_OFF 0x18 26 | #define UART_FIFO_ACCESS_REG_OFF 0x70 27 | #define UART_STATUS_REG_OFF 0x7c 28 | #define UART_TFL_OFF 0x80 29 | #define UART_RFL_OFF 0x84 30 | 31 | 32 | //Buad rate 33 | #define UART_BAUD_RATE_2400 2400 34 | #define UART_BAUD_RATE_4800 4800 35 | #define UART_BAUD_RATE_9600 9600 36 | #define UART_BAUD_RATE_19200 19200 37 | #define UART_BAUD_RATE_38400 38400 38 | #define UART_BAUD_RATE_57600 57600 39 | #define UART_BAUD_RATE_115200 115200 40 | #define UART_BAUD_RATE_921600 921600 41 | #define UART_BAUD_RATE_1152000 1152000 42 | 43 | #define UART_PARITY_ENABLE 0x08 44 | #define UART_PARITY_DISABLE 0 45 | 46 | #define UART_DATA_LEN_5BIT 0x0 47 | #define UART_DATA_LEN_6BIT 0x1 48 | #define UART_DATA_LEN_7BIT 0x2 49 | #define UART_DATA_LEN_8BIT 0x3 50 | 51 | #define UART_STOP_1BIT 0x0 52 | #define UART_STOP_2BIT 0x4 53 | 54 | 55 | #define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr) 56 | #define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value) 57 | #define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr) 58 | #define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value) 59 | #define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr) 60 | #define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value) 61 | 62 | typedef struct _LOG_UART_ADAPTER_ { 63 | u32 BaudRate; 64 | u32 FIFOControl; 65 | u32 IntEnReg; 66 | u8 Parity; 67 | u8 Stop; 68 | u8 DataLength; 69 | }LOG_UART_ADAPTER, *PLOG_UART_ADAPTER; 70 | 71 | typedef struct _COMMAND_TABLE_ { 72 | const u8* cmd; 73 | u16 ArgvCnt; 74 | u32 (*func)(u16 argc, u8* argv[]); 75 | const u8* msg; 76 | }COMMAND_TABLE, *PCOMMAND_TABLE; 77 | 78 | //VOID 79 | //HalLogUartHandle(void); 80 | 81 | 82 | extern _LONG_CALL_ u32 83 | HalLogUartInit( 84 | IN LOG_UART_ADAPTER UartAdapter 85 | ); 86 | 87 | 88 | extern _LONG_CALL_ VOID 89 | HalSerialPutcRtl8195a( 90 | IN u8 c 91 | ); 92 | 93 | extern _LONG_CALL_ u8 94 | HalSerialGetcRtl8195a( 95 | IN BOOL PullMode 96 | ); 97 | 98 | extern _LONG_CALL_ u32 99 | HalSerialGetIsrEnRegRtl8195a(VOID); 100 | 101 | extern _LONG_CALL_ VOID 102 | HalSerialSetIrqEnRegRtl8195a ( 103 | IN u32 SetValue 104 | ); 105 | 106 | 107 | #endif//_HAL_DIAG_H_ 108 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_efuse.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_EFUSE_H_ 11 | #define _HAL_EFUSE_H_ 12 | 13 | _LONG_CALL_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage); 14 | _LONG_CALL_ extern u32 HALEFUSEOneByteReadROM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage); 15 | _LONG_CALL_ extern u32 HALEFUSEOneByteWriteROM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage); 16 | 17 | #define EFUSERead8 HALEFUSEOneByteReadROM 18 | #define EFUSEWrite8 HALEFUSEOneByteWriteROM 19 | 20 | #define L25EOUTVOLTAGE 7 21 | 22 | VOID HalEFUSEOpInit( 23 | IN VOID *Data 24 | ); 25 | 26 | 27 | #endif 28 | 29 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_gdma.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_GDMA_H_ 11 | #define _HAL_GDMA_H_ 12 | 13 | #include "rtl8195a_gdma.h" 14 | 15 | typedef struct _GDMA_CH_LLI_ELE_ { 16 | u32 Sarx; 17 | u32 Darx; 18 | u32 Llpx; 19 | u32 CtlxLow; 20 | u32 CtlxUp; 21 | u32 Temp; 22 | }GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE; 23 | #if 1 24 | #if 0 25 | typedef struct _GDMA_CH_LLI_ { 26 | PGDMA_CH_LLI_ELE pLliEle; 27 | PGDMA_CH_LLI pNextLli; 28 | }GDMA_CH_LLI, *PGDMA_CH_LLI; 29 | 30 | typedef struct _BLOCK_SIZE_LIST_ { 31 | u32 BlockSize; 32 | PBLOCK_SIZE_LIST pNextBlockSiz; 33 | }BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST; 34 | #else 35 | struct GDMA_CH_LLI { 36 | PGDMA_CH_LLI_ELE pLliEle; 37 | struct GDMA_CH_LLI *pNextLli; 38 | }; 39 | 40 | struct BLOCK_SIZE_LIST { 41 | u32 BlockSize; 42 | struct BLOCK_SIZE_LIST *pNextBlockSiz; 43 | }; 44 | 45 | #endif 46 | 47 | #endif 48 | typedef struct _HAL_GDMA_ADAPTER_ { 49 | u32 ChSar; 50 | u32 ChDar; 51 | GDMA_CHANNEL_NUM ChEn; 52 | GDMA_CTL_REG GdmaCtl; 53 | GDMA_CFG_REG GdmaCfg; 54 | u32 PacketLen; 55 | u32 BlockLen; 56 | u32 MuliBlockCunt; 57 | u32 MaxMuliBlock; 58 | struct GDMA_CH_LLI *pLlix; 59 | struct BLOCK_SIZE_LIST *pBlockSizeList; 60 | 61 | PGDMA_CH_LLI_ELE pLli; 62 | u32 NextPlli; 63 | u8 TestItem; 64 | u8 ChNum; 65 | u8 GdmaIndex; 66 | u8 IsrCtrl:1; 67 | u8 GdmaOnOff:1; 68 | u8 Llpctrl:1; 69 | u8 Lli0:1; 70 | u8 Rsvd4to7:4; 71 | u8 GdmaIsrType; 72 | }HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER; 73 | 74 | 75 | typedef struct _HAL_GDMA_OP_ { 76 | VOID (*HalGdmaOnOff)(VOID *Data); 77 | BOOL (*HalGdamChInit)(VOID *Data); 78 | BOOL (*HalGdmaChSeting)(VOID *Data); 79 | BOOL (*HalGdmaChBlockSeting)(VOID *Data); 80 | VOID (*HalGdmaChDis)(VOID *Data); 81 | VOID (*HalGdmaChEn)(VOID *Data); 82 | VOID (*HalGdmaChIsrEnAndDis) (VOID *Data); 83 | u8 (*HalGdmaChIsrClean)(VOID *Data); 84 | VOID (*HalGdmaChCleanAutoSrc)(VOID *Data); 85 | VOID (*HalGdmaChCleanAutoDst)(VOID *Data); 86 | }HAL_GDMA_OP, *PHAL_GDMA_OP; 87 | 88 | 89 | VOID HalGdmaOpInit( 90 | IN VOID *Data 91 | ); 92 | 93 | extern const HAL_GDMA_OP _HalGdmaOp; 94 | 95 | #endif 96 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_gpio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_GPIO_H_ 11 | #define _HAL_GPIO_H_ 12 | 13 | 14 | #define HAL_GPIO_PIN_INT_MODE 0x80 15 | 16 | typedef enum { 17 | _PORT_A = 0, 18 | _PORT_B = 1, 19 | _PORT_C = 2, 20 | _PORT_D = 3, 21 | _PORT_E = 4, 22 | _PORT_F = 5, 23 | _PORT_G = 6, 24 | _PORT_H = 7, 25 | _PORT_I = 8, 26 | _PORT_J = 9, 27 | _PORT_K = 10, 28 | 29 | _PORT_MAX 30 | } HAL_GPIO_PORT_NAME; 31 | 32 | typedef enum { 33 | _PA_0 = (_PORT_A<<4|0), 34 | _PA_1 = (_PORT_A<<4|1), 35 | _PA_2 = (_PORT_A<<4|2), 36 | _PA_3 = (_PORT_A<<4|3), 37 | _PA_4 = (_PORT_A<<4|4), 38 | _PA_5 = (_PORT_A<<4|5), 39 | _PA_6 = (_PORT_A<<4|6), 40 | _PA_7 = (_PORT_A<<4|7), 41 | 42 | _PB_0 = (_PORT_B<<4|0), 43 | _PB_1 = (_PORT_B<<4|1), 44 | _PB_2 = (_PORT_B<<4|2), 45 | _PB_3 = (_PORT_B<<4|3), 46 | _PB_4 = (_PORT_B<<4|4), 47 | _PB_5 = (_PORT_B<<4|5), 48 | _PB_6 = (_PORT_B<<4|6), 49 | _PB_7 = (_PORT_B<<4|7), 50 | 51 | _PC_0 = (_PORT_C<<4|0), 52 | _PC_1 = (_PORT_C<<4|1), 53 | _PC_2 = (_PORT_C<<4|2), 54 | _PC_3 = (_PORT_C<<4|3), 55 | _PC_4 = (_PORT_C<<4|4), 56 | _PC_5 = (_PORT_C<<4|5), 57 | _PC_6 = (_PORT_C<<4|6), 58 | _PC_7 = (_PORT_C<<4|7), 59 | _PC_8 = (_PORT_C<<4|8), 60 | _PC_9 = (_PORT_C<<4|9), 61 | 62 | _PD_0 = (_PORT_D<<4|0), 63 | _PD_1 = (_PORT_D<<4|1), 64 | _PD_2 = (_PORT_D<<4|2), 65 | _PD_3 = (_PORT_D<<4|3), 66 | _PD_4 = (_PORT_D<<4|4), 67 | _PD_5 = (_PORT_D<<4|5), 68 | _PD_6 = (_PORT_D<<4|6), 69 | _PD_7 = (_PORT_D<<4|7), 70 | _PD_8 = (_PORT_D<<4|8), 71 | _PD_9 = (_PORT_D<<4|9), 72 | 73 | _PE_0 = (_PORT_E<<4|0), 74 | _PE_1 = (_PORT_E<<4|1), 75 | _PE_2 = (_PORT_E<<4|2), 76 | _PE_3 = (_PORT_E<<4|3), 77 | _PE_4 = (_PORT_E<<4|4), 78 | _PE_5 = (_PORT_E<<4|5), 79 | _PE_6 = (_PORT_E<<4|6), 80 | _PE_7 = (_PORT_E<<4|7), 81 | _PE_8 = (_PORT_E<<4|8), 82 | _PE_9 = (_PORT_E<<4|9), 83 | _PE_A = (_PORT_E<<4|10), 84 | 85 | _PF_0 = (_PORT_F<<4|0), 86 | _PF_1 = (_PORT_F<<4|1), 87 | _PF_2 = (_PORT_F<<4|2), 88 | _PF_3 = (_PORT_F<<4|3), 89 | _PF_4 = (_PORT_F<<4|4), 90 | _PF_5 = (_PORT_F<<4|5), 91 | // _PF_6 = (_PORT_F<<4|6), 92 | // _PF_7 = (_PORT_F<<4|7), 93 | 94 | _PG_0 = (_PORT_G<<4|0), 95 | _PG_1 = (_PORT_G<<4|1), 96 | _PG_2 = (_PORT_G<<4|2), 97 | _PG_3 = (_PORT_G<<4|3), 98 | _PG_4 = (_PORT_G<<4|4), 99 | _PG_5 = (_PORT_G<<4|5), 100 | _PG_6 = (_PORT_G<<4|6), 101 | _PG_7 = (_PORT_G<<4|7), 102 | 103 | _PH_0 = (_PORT_H<<4|0), 104 | _PH_1 = (_PORT_H<<4|1), 105 | _PH_2 = (_PORT_H<<4|2), 106 | _PH_3 = (_PORT_H<<4|3), 107 | _PH_4 = (_PORT_H<<4|4), 108 | _PH_5 = (_PORT_H<<4|5), 109 | _PH_6 = (_PORT_H<<4|6), 110 | _PH_7 = (_PORT_H<<4|7), 111 | 112 | _PI_0 = (_PORT_I<<4|0), 113 | _PI_1 = (_PORT_I<<4|1), 114 | _PI_2 = (_PORT_I<<4|2), 115 | _PI_3 = (_PORT_I<<4|3), 116 | _PI_4 = (_PORT_I<<4|4), 117 | _PI_5 = (_PORT_I<<4|5), 118 | _PI_6 = (_PORT_I<<4|6), 119 | _PI_7 = (_PORT_I<<4|7), 120 | 121 | _PJ_0 = (_PORT_J<<4|0), 122 | _PJ_1 = (_PORT_J<<4|1), 123 | _PJ_2 = (_PORT_J<<4|2), 124 | _PJ_3 = (_PORT_J<<4|3), 125 | _PJ_4 = (_PORT_J<<4|4), 126 | _PJ_5 = (_PORT_J<<4|5), 127 | _PJ_6 = (_PORT_J<<4|6), 128 | // _PJ_7 = (_PORT_J<<4|7), 129 | 130 | _PK_0 = (_PORT_K<<4|0), 131 | _PK_1 = (_PORT_K<<4|1), 132 | _PK_2 = (_PORT_K<<4|2), 133 | _PK_3 = (_PORT_K<<4|3), 134 | _PK_4 = (_PORT_K<<4|4), 135 | _PK_5 = (_PORT_K<<4|5), 136 | _PK_6 = (_PORT_K<<4|6), 137 | // _PK_7 = (_PORT_K<<4|7), 138 | 139 | // Not connected 140 | _PIN_NC = (int)0xFFFFFFFF 141 | } HAL_PIN_NAME; 142 | 143 | typedef enum 144 | { 145 | GPIO_PIN_LOW = 0, 146 | GPIO_PIN_HIGH = 1, 147 | GPIO_PIN_ERR = 2 // read Pin error 148 | } HAL_GPIO_PIN_STATE; 149 | 150 | typedef enum { 151 | DIN_PULL_NONE = 0, //floating or high impedance ? 152 | DIN_PULL_LOW = 1, 153 | DIN_PULL_HIGH = 2, 154 | 155 | DOUT_PUSH_PULL = 3, 156 | DOUT_OPEN_DRAIN = 4, 157 | 158 | INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger 159 | INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger 160 | INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger 161 | INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger 162 | } HAL_GPIO_PIN_MODE; 163 | 164 | enum { 165 | GPIO_PORT_A = 0, 166 | GPIO_PORT_B = 1, 167 | GPIO_PORT_C = 2, 168 | GPIO_PORT_D = 3 169 | }; 170 | 171 | typedef enum { 172 | hal_PullNone = 0, 173 | hal_PullUp = 1, 174 | hal_PullDown = 2, 175 | hal_OpenDrain = 3, 176 | hal_PullDefault = hal_PullNone 177 | } HAL_PinMode; 178 | 179 | typedef struct _HAL_GPIO_PORT_ { 180 | u32 out_data; // to write the GPIO port 181 | u32 in_data; // to read the GPIO port 182 | u32 dir; // config each pin direction 183 | }HAL_GPIO_PORT, *PHAL_GPIO_PORT; 184 | 185 | #define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin)) 186 | #define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03) 187 | #define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f) 188 | 189 | typedef struct _HAL_GPIO_PIN_ { 190 | HAL_GPIO_PIN_MODE pin_mode; 191 | u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number 192 | }HAL_GPIO_PIN, *PHAL_GPIO_PIN; 193 | 194 | 195 | typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id); 196 | typedef void (*GPIO_USER_IRQ_FUN)(u32 Id); 197 | 198 | typedef struct _HAL_GPIO_ADAPTER_ { 199 | IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle 200 | GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler 201 | GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x] 202 | VOID *PortA_IrqData[32]; 203 | VOID (*EnterCritical)(void); 204 | VOID (*ExitCritical)(void); 205 | u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out 206 | u8 Gpio_Func_En; // Is GPIO HW function enabled ? 207 | u8 Locked; 208 | }HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER; 209 | 210 | 211 | u32 212 | HAL_GPIO_GetPinName( 213 | u32 chip_pin 214 | ); 215 | 216 | VOID 217 | HAL_GPIO_PullCtrl( 218 | u32 pin, 219 | u32 mode 220 | ); 221 | 222 | VOID 223 | HAL_GPIO_Init( 224 | HAL_GPIO_PIN *GPIO_Pin 225 | ); 226 | 227 | VOID 228 | HAL_GPIO_Irq_Init( 229 | HAL_GPIO_PIN *GPIO_Pin 230 | ); 231 | 232 | VOID 233 | HAL_GPIO_DeInit( 234 | HAL_GPIO_PIN *GPIO_Pin 235 | ); 236 | 237 | s32 238 | HAL_GPIO_ReadPin( 239 | HAL_GPIO_PIN *GPIO_Pin 240 | ); 241 | 242 | VOID 243 | HAL_GPIO_WritePin( 244 | HAL_GPIO_PIN *GPIO_Pin, 245 | u32 Value 246 | ); 247 | 248 | VOID 249 | HAL_GPIO_UserRegIrq( 250 | HAL_GPIO_PIN *GPIO_Pin, 251 | VOID *IrqHandler, 252 | VOID *IrqData 253 | ); 254 | 255 | VOID 256 | HAL_GPIO_UserUnRegIrq( 257 | HAL_GPIO_PIN *GPIO_Pin 258 | ); 259 | 260 | VOID 261 | HAL_GPIO_IntCtrl( 262 | HAL_GPIO_PIN *GPIO_Pin, 263 | u32 En 264 | ); 265 | 266 | VOID 267 | HAL_GPIO_MaskIrq( 268 | HAL_GPIO_PIN *GPIO_Pin 269 | ); 270 | 271 | VOID 272 | HAL_GPIO_UnMaskIrq( 273 | HAL_GPIO_PIN *GPIO_Pin 274 | ); 275 | 276 | #endif // end of "#define _HAL_GPIO_H_" 277 | 278 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_i2s.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_I2S_H_ 11 | #define _HAL_I2S_H_ 12 | 13 | #include "rtl8195a_i2s.h" 14 | 15 | /* User Define Flags */ 16 | 17 | #define I2S0_USED 1 18 | #define I2S1_USED 1 19 | 20 | /* 21 | typedef struct _GDMA_CH_LLI_ELE_ { 22 | u32 Sarx; 23 | u32 Darx; 24 | u32 Llpx; 25 | u32 CtlxLow; 26 | u32 CtlxUp; 27 | u32 Temp; 28 | }GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE; 29 | #if 1 30 | #if 0 31 | typedef struct _GDMA_CH_LLI_ { 32 | PGDMA_CH_LLI_ELE pLliEle; 33 | PGDMA_CH_LLI pNextLli; 34 | }GDMA_CH_LLI, *PGDMA_CH_LLI; 35 | 36 | typedef struct _BLOCK_SIZE_LIST_ { 37 | u32 BlockSize; 38 | PBLOCK_SIZE_LIST pNextBlockSiz; 39 | }BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST; 40 | #else 41 | struct GDMA_CH_LLI { 42 | PGDMA_CH_LLI_ELE pLliEle; 43 | struct GDMA_CH_LLI *pNextLli; 44 | }; 45 | 46 | struct BLOCK_SIZE_LIST { 47 | u32 BlockSize; 48 | struct BLOCK_SIZE_LIST *pNextBlockSiz; 49 | }; 50 | 51 | #endif 52 | 53 | #endif 54 | typedef struct _HAL_I2S_ADAPTER_ { 55 | u32 ChSar; 56 | u32 ChDar; 57 | GDMA_CHANNEL_NUM ChEn; 58 | GDMA_CTL_REG GdmaCtl; 59 | GDMA_CFG_REG GdmaCfg; 60 | u32 PacketLen; 61 | u32 BlockLen; 62 | u32 MuliBlockCunt; 63 | u32 MaxMuliBlock; 64 | struct GDMA_CH_LLI *pLlix; 65 | struct BLOCK_SIZE_LIST *pBlockSizeList; 66 | 67 | PGDMA_CH_LLI_ELE pLli; 68 | u32 NextPlli; 69 | u8 TestItem; 70 | u8 ChNum; 71 | u8 GdmaIndex; 72 | u8 IsrCtrl:1; 73 | u8 GdmaOnOff:1; 74 | u8 Llpctrl:1; 75 | u8 Lli0:1; 76 | u8 Rsvd4to7:4; 77 | u8 GdmaIsrType; 78 | }HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER; 79 | 80 | */ 81 | 82 | /**********************************************************************/ 83 | /* I2S HAL initial data structure */ 84 | typedef struct _HAL_I2S_INIT_DAT_ { 85 | u8 I2SIdx; /*I2S index used*/ 86 | u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/ 87 | u8 I2SMaster; /*I2S Master or Slave mode*/ 88 | u8 I2SWordLen; /*I2S Word length 16 or 24bits*/ 89 | 90 | u8 I2SChNum; /*I2S Channel number mono or stereo*/ 91 | u8 I2SPageNum; /*I2S Page Number 2~4*/ 92 | u16 I2SPageSize; /*I2S page Size 1~4096 word*/ 93 | 94 | u8 *I2STxData; /*I2S Tx data pointer*/ 95 | 96 | u8 *I2SRxData; /*I2S Rx data pointer*/ 97 | 98 | u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/ 99 | u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */ 100 | 101 | u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/ 102 | u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/ 103 | 104 | u16 I2STxIdx; /*I2S TX page index */ 105 | u16 I2SRxIdx; /*I2S RX page index */ 106 | 107 | u16 I2SHWTxIdx; /*I2S HW TX page index */ 108 | u16 I2SHWRxIdx; /*I2S HW RX page index */ 109 | 110 | 111 | u16 I2SRate; /*I2S sample rate*/ 112 | u8 I2STRxAct; /*I2S tx rx act*/ 113 | }HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT; 114 | 115 | /**********************************************************************/ 116 | /* I2S Data Structures */ 117 | /* I2S Module Selection */ 118 | typedef enum _I2S_MODULE_SEL_ { 119 | I2S0_SEL = 0x0, 120 | I2S1_SEL = 0x1, 121 | }I2S_MODULE_SEL,*PI2S_MODULE_SEL; 122 | /* 123 | typedef struct _HAL_I2S_ADAPTER_ { 124 | u32 Enable:1; 125 | I2S_CTL_REG I2sCtl; 126 | I2S_SETTING_REG I2sSetting; 127 | u32 abc; 128 | u8 I2sIndex; 129 | }HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER; 130 | */ 131 | /* I2S HAL Operations */ 132 | typedef struct _HAL_I2S_OP_ { 133 | RTK_STATUS (*HalI2SInit) (VOID *Data); 134 | RTK_STATUS (*HalI2SDeInit) (VOID *Data); 135 | RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff); 136 | RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff); 137 | RTK_STATUS (*HalI2SEnable) (VOID *Data); 138 | RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data); 139 | u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg); 140 | RTK_STATUS (*HalI2SSetRate) (VOID *Data); 141 | RTK_STATUS (*HalI2SSetWordLen) (VOID *Data); 142 | RTK_STATUS (*HalI2SSetChNum) (VOID *Data); 143 | RTK_STATUS (*HalI2SSetPageNum) (VOID *Data); 144 | RTK_STATUS (*HalI2SSetPageSize) (VOID *Data); 145 | 146 | RTK_STATUS (*HalI2SClrIntr) (VOID *Data); 147 | RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data); 148 | RTK_STATUS (*HalI2SDMACtrl) (VOID *Data); 149 | /* 150 | VOID (*HalI2sOnOff)(VOID *Data); 151 | BOOL (*HalI2sInit)(VOID *Data); 152 | BOOL (*HalI2sSetting)(VOID *Data); 153 | BOOL (*HalI2sEn)(VOID *Data); 154 | BOOL (*HalI2sIsrEnAndDis) (VOID *Data); 155 | BOOL (*HalI2sDumpReg)(VOID *Data); 156 | BOOL (*HalI2s)(VOID *Data); 157 | */ 158 | }HAL_I2S_OP, *PHAL_I2S_OP; 159 | 160 | 161 | /**********************************************************************/ 162 | 163 | /* I2S Pinmux Selection */ 164 | typedef enum _I2S0_PINMUX_ { 165 | I2S0_TO_S0 = 0x0, 166 | I2S0_TO_S1 = 0x1, 167 | I2S0_TO_S2 = 0x2, 168 | }I2S0_PINMUX, *PI2S0_PINMUX; 169 | 170 | typedef enum _I2S1_PINMUX_ { 171 | I2S1_TO_S0 = 0x0, 172 | I2S1_TO_S1 = 0x1, 173 | }I2S1_PINMUX, *PI2S1_PINMUX; 174 | 175 | 176 | /* I2S Module Status */ 177 | typedef enum _I2S_MODULE_STATUS_ { 178 | I2S_DISABLE = 0x0, 179 | I2S_ENABLE = 0x1, 180 | }I2S_MODULE_STATUS, *PI2S_MODULE_STATUS; 181 | 182 | 183 | /* I2S Device Status */ 184 | typedef enum _I2S_Device_STATUS_ { 185 | I2S_STS_UNINITIAL = 0x00, 186 | I2S_STS_INITIALIZED = 0x01, 187 | I2S_STS_IDLE = 0x02, 188 | 189 | I2S_STS_TX_READY = 0x03, 190 | I2S_STS_TX_ING = 0x04, 191 | 192 | I2S_STS_RX_READY = 0x05, 193 | I2S_STS_RX_ING = 0x06, 194 | 195 | I2S_STS_TRX_READY = 0x07, 196 | I2S_STS_TRX_ING = 0x08, 197 | 198 | I2S_STS_ERROR = 0x09, 199 | }I2S_Device_STATUS, *PI2S_Device_STATUS; 200 | 201 | 202 | /* I2S Feature Status */ 203 | typedef enum _I2S_FEATURE_STATUS_{ 204 | I2S_FEATURE_DISABLED = 0, 205 | I2S_FEATURE_ENABLED = 1, 206 | }I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS; 207 | 208 | /* I2S Device Mode */ 209 | typedef enum _I2S_DEV_MODE_ { 210 | I2S_SLAVE_MODE = 0x0, 211 | I2S_MASTER_MODE = 0x1 212 | }I2S_DEV_MODE, *PI2S_DEV_MODE; 213 | 214 | /* I2S Bus Transmit/Receive */ 215 | typedef enum _I2S_DIRECTION_ { 216 | I2S_ONLY_RX = 0x0, 217 | I2S_ONLY_TX = 0x1, 218 | I2S_TXRX = 0x2 219 | }I2S_DIRECTION, *PI2S_DIRECTION; 220 | 221 | /* I2S Channel number */ 222 | typedef enum _I2S_CH_NUM_ { 223 | I2S_CH_STEREO = 0x0, 224 | I2S_CH_RSVD = 0x1, 225 | I2S_CH_MONO = 0x2 226 | }I2S_CH_NUM, *PI2S_CH_NUM; 227 | 228 | /* I2S Page number */ 229 | typedef enum _I2S_PAGE_NUM_ { 230 | I2S_1PAGE = 0x0, 231 | I2S_2PAGE = 0x1, 232 | I2S_3PAGE = 0x2, 233 | I2S_4PAGE = 0x3 234 | }I2S_PAGE_NUM, *PI2S_PAGE_NUM; 235 | 236 | /* I2S Sample rate*/ 237 | typedef enum _I2S_SAMPLE_RATE_ { 238 | I2S_SR_8KHZ = 0x00, 239 | I2S_SR_16KHZ = 0x01, 240 | I2S_SR_24KHZ = 0x02, 241 | I2S_SR_48KHZ = 0x05 242 | }I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE; 243 | 244 | /* I2S User Callbacks */ 245 | typedef struct _SAL_I2S_USER_CB_{ 246 | VOID (*TXCB) (VOID *Data); 247 | VOID (*TXCCB) (VOID *Data); 248 | VOID (*RXCB) (VOID *Data); 249 | VOID (*RXCCB) (VOID *Data); 250 | VOID (*RDREQCB) (VOID *Data); 251 | VOID (*ERRCB) (VOID *Data); 252 | VOID (*GENCALLCB) (VOID *Data); 253 | }SAL_I2S_USER_CB,*PSAL_I2S_USER_CB; 254 | 255 | /* I2S Transmit Buffer */ 256 | typedef struct _SAL_I2S_TRANSFER_BUF_{ 257 | u16 DataLen; 258 | u16 TargetAddr; 259 | u32 RegAddr; 260 | u32 RSVD; 261 | u8 *pDataBuf; 262 | }SAL_I2S_TRANSFER_BUF,*PSAL_I2S_TRANSFER_BUF; 263 | 264 | /* RTK I2S OP */ 265 | typedef struct _RTK_I2S_OP_ { 266 | RTK_STATUS (*Init) (VOID *Data); 267 | RTK_STATUS (*DeInit) (VOID *Data); 268 | RTK_STATUS (*Send) (VOID *Data); 269 | RTK_STATUS (*Receive) (VOID *Data); 270 | RTK_STATUS (*IoCtrl) (VOID *Data); 271 | RTK_STATUS (*PowerCtrl) (VOID *Data); 272 | }RTK_I2S_OP, *PRTK_I2S_OP; 273 | 274 | 275 | /* Software API Level I2S Handler */ 276 | typedef struct _SAL_I2S_HND_{ 277 | u8 DevNum; //I2S device number 278 | u8 PinMux; //I2S pin mux seletion 279 | u8 RSVD0; //Reserved 280 | volatile u8 DevSts; //I2S device status 281 | 282 | u8 I2SChNum; //I2S Channel number mono or stereo 283 | u8 I2SPageNum; //I2S Page number 2~4 284 | u16 I2SPageSize; //I2S Page size 1~4096 word 285 | 286 | u16 I2SRate; //I2S sample rate 8k ~ 96khz 287 | u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx 288 | u8 I2SWordLen; //I2S Word length 16bit or 24bit 289 | u8 RSVD1; //Reserved 290 | 291 | u32 RSVD2; //Reserved 292 | u32 I2SExd; //I2S extended options: 293 | //bit 0: I2C RESTART supported, 294 | // 0 for NOT supported, 295 | // 1 for supported 296 | //bit 1: I2C General Call supported 297 | // 0 for NOT supported, 298 | // 1 for supported 299 | //bit 2: I2C START Byte supported 300 | // 0 for NOT supported, 301 | // 1 for supported 302 | //bit 3: I2C Slave-No-Ack 303 | // supported 304 | // 0 for NOT supported, 305 | // 1 for supported 306 | //bit 4: I2C bus loading, 307 | // 0 for 100pf, 308 | // 1 for 400pf 309 | //bit 5: I2C slave ack to General 310 | // Call 311 | //bit 6: I2C User register address 312 | //bit 7: I2C 2-Byte User register 313 | // address 314 | //bit 31~bit 8: Reserved 315 | u32 ErrType; // 316 | u32 TimeOut; //I2S IO Timeout count 317 | 318 | PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct 319 | u8 *pTXBuf; //Pointer to I2S TX buffer 320 | u8 *pRXBuf; //Pointer to I2S RX buffer 321 | PSAL_I2S_USER_CB pUserCB; //Pointer to I2S User Callback 322 | }SAL_I2S_HND, *PSAL_I2S_HND; 323 | 324 | 325 | /**********************************************************************/ 326 | // Global Parameters 327 | #if I2S0_USED 328 | extern SAL_I2S_HND SalI2S0Hnd; 329 | #endif 330 | 331 | #if I2S1_USED 332 | extern SAL_I2S_HND SalI2S1Hnd; 333 | #endif 334 | 335 | /**********************************************************************/ 336 | // Function Prototypes 337 | static inline RTK_STATUS 338 | RtkI2SIdxChk( 339 | IN u8 I2SIdx 340 | ) 341 | { 342 | #if !I2S0_USED 343 | if (I2SIdx == I2S0_SEL) 344 | return _EXIT_FAILURE; 345 | #endif 346 | 347 | #if !I2S1_USED 348 | if (I2SIdx == I2S1_SEL) 349 | return _EXIT_FAILURE; 350 | #endif 351 | 352 | return _EXIT_SUCCESS; 353 | } 354 | 355 | 356 | /**********************************************************************/ 357 | PSAL_I2S_HND 358 | RtkI2SGetSalHnd(IN u8 I2SIdx); 359 | 360 | RTK_STATUS 361 | RtkI2SLoadDefault(IN VOID *Data); 362 | 363 | RTK_STATUS 364 | RtkI2SInit(IN VOID *Data); 365 | 366 | RTK_STATUS 367 | RtkI2SDeInit(IN VOID *Data); 368 | 369 | RTK_STATUS 370 | RtkI2SSend(IN VOID *Data); 371 | 372 | RTK_STATUS 373 | RtkI2SReceive(IN VOID *Data); 374 | 375 | VOID SalI2SOpInit(IN VOID *Data); 376 | 377 | /**********************************************************************/ 378 | 379 | 380 | VOID I2S0ISRHandle(VOID *Data); 381 | VOID I2S1ISRHandle(VOID *Data); 382 | 383 | 384 | /**********************************************************************/ 385 | 386 | VOID HalI2SOpInit( 387 | IN VOID *Data 388 | ); 389 | 390 | 391 | #endif 392 | 393 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_irqn.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_IRQN_H_ 11 | #define _HAL_IRQN_H_ 12 | 13 | 14 | // C structure 15 | #ifdef __cplusplus 16 | extern "C"{ 17 | #endif // __cplusplus 18 | 19 | 20 | #define PERIPHERAL_IRQ_BASE_NUM 64 21 | 22 | typedef enum _IRQn_Type_ { 23 | #if 0 24 | /****** Cortex-M3 Processor Exceptions Numbers ********/ 25 | NON_MASKABLE_INT_IRQ = -14, 26 | HARD_FAULT_IRQ = -13, 27 | MEM_MANAGE_FAULT_IRQ = -12, 28 | BUS_FAULT_IRQ = -11, 29 | USAGE_FAULT_IRQ = -10, 30 | SVCALL_IRQ = -5, 31 | DEBUG_MONITOR_IRQ = -4, 32 | PENDSVC_IRQ = -2, 33 | SYSTICK_IRQ = -1, 34 | #else 35 | /****** Cortex-M3 Processor Exceptions Numbers ********/ 36 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 37 | HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 38 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 39 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 40 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 41 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 42 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 43 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 44 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 45 | #endif 46 | /****** RTL8195A Specific Interrupt Numbers ************/ 47 | SYSTEM_ON_IRQ = 0, 48 | WDG_IRQ = 1, 49 | TIMER0_IRQ = 2, 50 | TIMER1_IRQ = 3, 51 | I2C3_IRQ = 4, 52 | TIMER2_7_IRQ = 5, 53 | SPI0_IRQ = 6, 54 | GPIO_IRQ = 7, 55 | UART0_IRQ = 8, 56 | SPI_FLASH_IRQ = 9, 57 | USB_OTG_IRQ = 10, 58 | SDIO_HOST_IRQ = 11, 59 | SDIO_DEVICE_IRQ = 12, 60 | I2S0_PCM0_IRQ = 13, 61 | I2S1_PCM1_IRQ = 14, 62 | WL_DMA_IRQ = 15, 63 | WL_PROTOCOL_IRQ = 16, 64 | CRYPTO_IRQ = 17, 65 | GMAC_IRQ = 18, 66 | PERIPHERAL_IRQ = 19, 67 | GDMA0_CHANNEL0_IRQ = 20, 68 | GDMA0_CHANNEL1_IRQ = 21, 69 | GDMA0_CHANNEL2_IRQ = 22, 70 | GDMA0_CHANNEL3_IRQ = 23, 71 | GDMA0_CHANNEL4_IRQ = 24, 72 | GDMA0_CHANNEL5_IRQ = 25, 73 | GDMA1_CHANNEL0_IRQ = 26, 74 | GDMA1_CHANNEL1_IRQ = 27, 75 | GDMA1_CHANNEL2_IRQ = 28, 76 | GDMA1_CHANNEL3_IRQ = 29, 77 | GDMA1_CHANNEL4_IRQ = 30, 78 | GDMA1_CHANNEL5_IRQ = 31, 79 | 80 | /****** RTL8195A Peripheral Interrupt Numbers ************/ 81 | I2C0_IRQ = 64,// 0 + 64, 82 | I2C1_IRQ = 65,// 1 + 64, 83 | I2C2_IRQ = 66,// 2 + 64, 84 | SPI1_IRQ = 72,// 8 + 64, 85 | SPI2_IRQ = 73,// 9 + 64, 86 | UART1_IRQ = 80,// 16 + 64, 87 | UART2_IRQ = 81,// 17 + 64, 88 | UART_LOG_IRQ = 88,// 24 + 64, 89 | ADC_IRQ = 89,// 25 + 64, 90 | DAC0_IRQ = 91,// 27 + 64, 91 | DAC1_IRQ = 92,// 28 + 64, 92 | //RXI300_IRQ = 93// 29 + 64 93 | LP_EXTENSION_IRQ = 93,// 29+64 94 | 95 | RXI300_IRQ = 96,// 0+32 + 64 96 | NFC_IRQ = 97// 1+32+64 97 | } IRQn_Type, *PIRQn_Type; 98 | 99 | 100 | typedef VOID (*HAL_VECTOR_FUN) (VOID); 101 | 102 | typedef enum _VECTOR_TABLE_TYPE_{ 103 | DEDECATED_VECTRO_TABLE, 104 | PERIPHERAL_VECTOR_TABLE 105 | }VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE; 106 | 107 | 108 | typedef u32 (*IRQ_FUN)(VOID *Data); 109 | 110 | typedef struct _IRQ_HANDLE_ { 111 | IRQ_FUN IrqFun; 112 | IRQn_Type IrqNum; 113 | u32 Data; 114 | u32 Priority; 115 | }IRQ_HANDLE, *PIRQ_HANDLE; 116 | 117 | #ifdef __cplusplus 118 | } 119 | #endif // __cplusplus 120 | 121 | 122 | #endif //_HAL_IRQN_H_ 123 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_misc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _MISC_H_ 11 | #define _MISC_H_ 12 | 13 | #include 14 | 15 | extern u32 HalDelayUs(u32 us); 16 | 17 | extern u32 HalGetCpuClk(VOID); 18 | extern u8 HalGetRomInfo(VOID); 19 | 20 | extern _LONG_CALL_ void *_memset( void *s, int c, SIZE_T n ); 21 | extern _LONG_CALL_ void *_memcpy( void *s1, const void *s2, SIZE_T n ); 22 | extern _LONG_CALL_ int *_memcmp( const void *av, const void *bv, SIZE_T len ); 23 | 24 | extern _LONG_CALL_ SIZE_T _strlen(const char *s); 25 | extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct); 26 | 27 | 28 | #endif //_MISC_H_ 29 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_pinmux.h: -------------------------------------------------------------------------------- 1 | #ifndef _HAL_PINMUX_ 2 | #define _HAL_PINMUX_ 3 | 4 | 5 | //Function Index 6 | #define UART0 0 7 | #define UART1 1 8 | #define UART2 2 9 | #define SPI0 8 10 | #define SPI1 9 11 | #define SPI2 10 12 | #define SPI0_MCS 15 13 | #define I2C0 16 14 | #define I2C1 17 15 | #define I2C2 18 16 | #define I2C3 19 17 | #define I2S0 24 18 | #define I2S1 25 19 | #define PCM0 28 20 | #define PCM1 29 21 | #define SDIOD 64 22 | #define SDIOH 65 23 | #define MII 88 24 | #define WL_LED 96 25 | #define WL_ANT0 104 26 | #define WL_ANT1 105 27 | #define WL_BTCOEX 108 28 | #define WL_BTCMD 109 29 | #define NFC 112 30 | #define PWM0 160 31 | #define PWM1 161 32 | #define PWM2 162 33 | #define PWM3 163 34 | #define ETE0 164 35 | #define ETE1 165 36 | #define ETE2 166 37 | #define ETE3 167 38 | #define EGTIM 168 39 | #define SPI_FLASH 196 40 | #define SDR 200 41 | #define JTAG 216 42 | #define TRACE 217 43 | #define LOG_UART 220 44 | #define LOG_UART_IR 221 45 | #define SIC 224 46 | #define EEPROM 225 47 | #define DEBUG 226 48 | 49 | //Location Index(Pin Mux Selection) 50 | #define S0 0 51 | #define S1 1 52 | #define S2 2 53 | #define S3 3 54 | 55 | //#ifndef _TRUE 56 | //#define _TRUE 1 57 | //#endif 58 | 59 | //#ifndef _FALSE 60 | //#define _FALSE 0 61 | //#endif 62 | 63 | #ifndef ON 64 | #define ON 1 65 | #endif 66 | 67 | #ifndef OFF 68 | #define OFF 0 69 | #endif 70 | u8 71 | HalPinCtrlRtl8195A( 72 | IN u32 Function, 73 | IN u32 PinLocation, 74 | IN BOOL Operation); 75 | #endif //_HAL_PINMUX_ -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_platform.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | 11 | #ifndef _HAL_PLATFORM_ 12 | #define _HAL_PLATFORM_ 13 | 14 | #define ROMVERSION 0x02 15 | #define ROMINFORMATION (ROMVERSION) 16 | 17 | 18 | #define SDR_SDRAM_BASE 0x30000000 19 | #define SYSTEM_CTRL_BASE 0x40000000 20 | #define PERI_ON_BASE 0x40000000 21 | #define VENDOR_REG_BASE 0x40002800 22 | #define SPI_FLASH_BASE 0x98000000 23 | #define SDR_CTRL_BASE 0x40005000 24 | 25 | #define PERIPHERAL_IRQ_STATUS 0x04 26 | #define PERIPHERAL_IRQ_MODE 0x08 27 | #define PERIPHERAL_IRQ_EN 0x0C 28 | #define LP_PERI_EXT_IRQ_STATUS 0x24 29 | #define LP_PERI_EXT_IRQ_MODE 0x28 30 | #define LP_PERI_EXT_IRQ_EN 0x2C 31 | 32 | #define PERIPHERAL_IRQ_ALL_LEVEL 0 33 | 34 | #define TIMER_CLK 32*1000 35 | 36 | //3 Peripheral IP Base Address 37 | #define GPIO_REG_BASE 0x40001000 38 | #define TIMER_REG_BASE 0x40002000 39 | #define NFC_INTERFACE_BASE 0x40002400 40 | #define LOG_UART_REG_BASE 0x40003000 41 | #define I2C2_REG_BASE 0x40003400 42 | #define I2C3_REG_BASE 0x40003800 43 | #define SPI_FLASH_CTRL_BASE 0x40006000 44 | #define ADC_REG_BASE 0x40010000 45 | #define DAC_REG_BASE 0x40011000 46 | #define UART0_REG_BASE 0x40040000 47 | #define UART1_REG_BASE 0x40040400 48 | #define UART2_REG_BASE 0x40040800 49 | #define SPI0_REG_BASE 0x40042000 50 | #define SPI1_REG_BASE 0x40042400 51 | #define SPI2_REG_BASE 0x40042800 52 | #define I2C0_REG_BASE 0x40044000 53 | #define I2C1_REG_BASE 0x40044400 54 | #define SDIO_DEVICE_REG_BASE 0x40050000 55 | #define MII_REG_BASE 0x40050000 56 | #define SDIO_HOST_REG_BASE 0x40058000 57 | #define GDMA0_REG_BASE 0x40060000 58 | #define GDMA1_REG_BASE 0x40061000 59 | #define I2S0_REG_BASE 0x40062000 60 | #define I2S1_REG_BASE 0x40063000 61 | #define PCM0_REG_BASE 0x40064000 62 | #define PCM1_REG_BASE 0x40065000 63 | #define CRYPTO_REG_BASE 0x40070000 64 | #define WIFI_REG_BASE 0x40080000 65 | #define USB_OTG_REG_BASE 0x400C0000 66 | 67 | #define GDMA1_REG_OFF 0x1000 68 | #define I2S1_REG_OFF 0x1000 69 | #define PCM1_REG_OFF 0x1000 70 | #define SSI_REG_OFF 0x400 71 | #define RUART_REG_OFF 0x400 72 | 73 | #define CPU_CLK_TYPE_NO 6 74 | 75 | enum _BOOT_TYPE_ { 76 | BOOT_FROM_FLASH = 0, 77 | BOOT_FROM_SDIO = 1, 78 | BOOT_FROM_USB = 2, 79 | BOOT_FROM_RSVD = 3, 80 | }; 81 | 82 | enum _EFUSE_CPU_CLK_ { 83 | CLK_200M = 0, 84 | CLK_100M = 1, 85 | CLK_50M = 2, 86 | CLK_25M = 3, 87 | CLK_12_5M = 4, 88 | CLK_4M = 5, 89 | }; 90 | 91 | 92 | #endif //_HAL_PLATFORM_ 93 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_pwm.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_PWM_H_ 11 | #define _HAL_PWM_H_ 12 | 13 | #define MAX_PWM_CTRL_PIN 4 14 | // the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T) 15 | #define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5 16 | #define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2 17 | #define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2 18 | 19 | typedef struct _HAL_PWM_ADAPTER_ { 20 | u8 pwm_id; // the PWM ID, 0~3 21 | u8 sel; // PWM Pin selection, 0~3 22 | u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6 23 | u8 enable; // is enabled 24 | // u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM 25 | u32 tick_time; // the tick time for the G-timer 26 | u32 period; // the period of a PWM control cycle, in PWM tick 27 | u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio 28 | // float duty_ratio; // the dyty ratio = pulswidth/period 29 | }HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER; 30 | 31 | 32 | extern HAL_Status 33 | HAL_Pwm_Init( 34 | u32 pwm_id, 35 | u32 sel 36 | ); 37 | 38 | extern void 39 | HAL_Pwm_Enable( 40 | u32 pwm_id 41 | ); 42 | 43 | extern void 44 | HAL_Pwm_Disable( 45 | u32 pwm_id 46 | ); 47 | 48 | extern void 49 | HAL_Pwm_SetDuty( 50 | u32 pwm_id, 51 | u32 period, 52 | u32 pulse_width 53 | ); 54 | 55 | 56 | #endif 57 | 58 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_sdr_controller.c: -------------------------------------------------------------------------------- 1 | #include "rtl8195a.h" 2 | 3 | uint32_t SdrControllerInit(void) __attribute__((section(".hal.ram.text"))); 4 | 5 | uint32_t SdrControllerInit(void) 6 | { 7 | return FALSE; 8 | } 9 | 10 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_spi_flash.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | 11 | #ifndef _HAL_SPIFLASH__ 12 | #define _HAL_SPIFLASH__ 13 | //====================================================== 14 | // Header files 15 | #include "rtl8195a_spi_flash.h" 16 | 17 | //====================================================== 18 | // Definition 19 | #define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32) 20 | #define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16) 21 | #define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8) 22 | #define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr) 23 | #define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr) 24 | #define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr) 25 | 26 | typedef struct _SPIC_INIT_PARA_ { 27 | u8 BaudRate; 28 | u8 RdDummyCyle; 29 | u8 DelayLine; 30 | union { 31 | u8 Rsvd; 32 | u8 Valid; 33 | }; 34 | }SPIC_INIT_PARA, *PSPIC_INIT_PARA; 35 | 36 | 37 | enum _SPIC_BIT_MODE_ { 38 | SpicOneBitMode = 0, 39 | SpicDualBitMode = 1, 40 | SpicQuadBitMode = 2, 41 | }; 42 | 43 | //====================================================== 44 | // Flash type used 45 | #define FLASH_MXIC_MX25L4006E 1 46 | #define FLASH_MXIC_MX25L8073E 0 47 | 48 | // The below parts are based on the flash characteristics 49 | //====== Flash Command Definition ====== 50 | #if FLASH_MXIC_MX25L4006E 51 | #define FLASH_CMD_WREN 0x06 //write enable 52 | #define FLASH_CMD_WRDI 0x04 //write disable 53 | #define FLASH_CMD_WRSR 0x01 //write status register 54 | #define FLASH_CMD_RDID 0x9F //read idenfication 55 | #define FLASH_CMD_RDSR 0x05 //read status register 56 | #define FLASH_CMD_READ 0x03 //read data 57 | #define FLASH_CMD_FREAD 0x0B //fast read data 58 | #define FLASH_CMD_RDSFDP 0x5A //Read SFDP 59 | #define FLASH_CMD_RES 0xAB //Read Electronic ID 60 | #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID 61 | #define FLASH_CMD_DREAD 0x3B //Double Output Mode command 62 | #define FLASH_CMD_SE 0x20 //Sector Erase 63 | #define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52) 64 | #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) 65 | #define FLASH_CMD_PP 0x02 //Page Program 66 | #define FLASH_CMD_DP 0xB9 //Deep Power Down 67 | #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down 68 | #elif FLASH_MXIC_MX25L8073E 69 | #define FLASH_CMD_WREN 0x06 //write enable 70 | #define FLASH_CMD_WRDI 0x04 //write disable 71 | #define FLASH_CMD_WRSR 0x01 //write status register 72 | #define FLASH_CMD_RDID 0x9F //read idenfication 73 | #define FLASH_CMD_RDSR 0x05 //read status register 74 | #define FLASH_CMD_READ 0x03 //read data 75 | #define FLASH_CMD_FREAD 0x0B //fast read data 76 | #define FLASH_CMD_RDSFDP 0x5A //Read SFDP 77 | #define FLASH_CMD_RES 0xAB //Read Electronic ID 78 | #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID 79 | #define FLASH_CMD_DREAD 0x3B //Double Output Mode command 80 | #define FLASH_CMD_SE 0x20 //Sector Erase 81 | #define FLASH_CMD_BE 0x52 //Block Erase 82 | #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) 83 | #define FLASH_CMD_PP 0x02 //Page Program 84 | #define FLASH_CMD_DP 0xB9 //Deep Power Down 85 | #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down 86 | #define FLASH_CMD_2READ 0xBB // 2 x I/O read command 87 | #define FLASH_CMD_4READ 0xEB // 4 x I/O read command 88 | #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 89 | #define FLASH_CMD_4PP 0x38 //quad page program 90 | #define FLASH_CMD_FF 0xFF //Release Read Enhanced 91 | #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode 92 | #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode 93 | #define FLASH_CMD_ENSO 0xB1 // enter secured OTP 94 | #define FLASH_CMD_EXSO 0xC1 // exit secured OTP 95 | #define FLASH_CMD_RDSCUR 0x2B // read security register 96 | #define FLASH_CMD_WRSCUR 0x2F // write security register 97 | #else 98 | #define FLASH_CMD_WREN 0x06 //write enable 99 | #define FLASH_CMD_WRDI 0x04 //write disable 100 | #define FLASH_CMD_WRSR 0x01 //write status register 101 | #define FLASH_CMD_RDID 0x9F //read idenfication 102 | #define FLASH_CMD_RDSR 0x05 //read status register 103 | #define FLASH_CMD_READ 0x03 //read data 104 | #define FLASH_CMD_FREAD 0x0B //fast read data 105 | #define FLASH_CMD_RDSFDP 0x5A //Read SFDP 106 | #define FLASH_CMD_RES 0xAB //Read Electronic ID 107 | #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID 108 | #define FLASH_CMD_DREAD 0x3B //Double Output Mode command 109 | #define FLASH_CMD_SE 0x20 //Sector Erase 110 | #define FLASH_CMD_BE 0x52 //Block Erase 111 | #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) 112 | #define FLASH_CMD_PP 0x02 //Page Program 113 | #define FLASH_CMD_DP 0xB9 //Deep Power Down 114 | #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down 115 | #define FLASH_CMD_2READ 0xBB // 2 x I/O read command 116 | #define FLASH_CMD_4READ 0xEB // 4 x I/O read command 117 | #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 118 | #define FLASH_CMD_4PP 0x38 //quad page program 119 | #define FLASH_CMD_FF 0xFF //Release Read Enhanced 120 | #define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode 121 | #define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode 122 | #define FLASH_CMD_ENSO 0xB1 // enter secured OTP 123 | #define FLASH_CMD_EXSO 0xC1 // exit secured OTP 124 | #define FLASH_CMD_RDSCUR 0x2B // read security register 125 | #define FLASH_CMD_WRSCUR 0x2F // write security register 126 | #endif //#if FLASH_MXIC_MX25L4006E 127 | // ============================ 128 | 129 | // ===== Flash Parameter Definition ===== 130 | #if FLASH_MXIC_MX25L4006E 131 | #define FLASH_RD_2IO_EN 0 132 | #define FLASH_RD_2O_EN 1 133 | #define FLASH_RD_4IO_EN 0 134 | #define FLASH_RD_4O_EN 0 135 | #define FLASH_WR_2IO_EN 0 136 | #define FLASH_WR_2O_EN 0 137 | #define FLASH_WR_4IO_EN 0 138 | #define FLASH_WR_4O_EN 0 139 | 140 | #define FLASH_DM_CYCLE_2O 0x08 141 | #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I) 142 | #define FLASH_VLD_QUAD_CMDS (0) 143 | 144 | #elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it, 145 | //the code MUST be rechecked according to the flash spec. 146 | #define FLASH_RD_2IO_EN 1 147 | #define FLASH_RD_2O_EN 0 148 | #define FLASH_RD_4IO_EN 1 149 | #define FLASH_RD_4O_EN 0 150 | #define FLASH_WR_2IO_EN 1 151 | #define FLASH_WR_2O_EN 0 152 | #define FLASH_WR_4IO_EN 1 153 | #define FLASH_WR_4O_EN 0 154 | 155 | #define FLASH_DM_CYCLE_2O 0x08 156 | #define FLASH_DM_CYCLE_2IO 0x04 157 | #define FLASH_DM_CYCLE_4O 0x08 158 | #define FLASH_DM_CYCLE_4IO 0x04 159 | 160 | #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO) 161 | #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) 162 | #else 163 | #define FLASH_RD_2IO_EN 1 164 | #define FLASH_RD_2O_EN 0 165 | #define FLASH_RD_4IO_EN 1 166 | #define FLASH_RD_4O_EN 0 167 | #define FLASH_WR_2IO_EN 1 168 | #define FLASH_WR_2O_EN 0 169 | #define FLASH_WR_4IO_EN 1 170 | #define FLASH_WR_4O_EN 0 171 | 172 | #define FLASH_DM_CYCLE_2O 0x08 173 | #define FLASH_DM_CYCLE_2IO 0x04 174 | #define FLASH_DM_CYCLE_4O 0x08 175 | #define FLASH_DM_CYCLE_4IO 0x04 176 | 177 | #define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO) 178 | #define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO) 179 | #endif 180 | 181 | //====================================================== 182 | // Function prototype 183 | BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode); 184 | 185 | _LONG_CALL_ 186 | extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara); 187 | 188 | // spi-flash controller initialization 189 | _LONG_CALL_ 190 | extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); 191 | 192 | // wait sr[0] = 0, wait transmission done 193 | _LONG_CALL_ 194 | extern VOID SpicWaitBusyDoneRtl8195A(VOID); 195 | 196 | // wait spi-flash status register[0] = 0 197 | //_LONG_CALL_ 198 | //extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); 199 | 200 | VOID SpicBlockEraseFlashRtl8195A(IN u32 Address); 201 | VOID SpicSectorEraseFlashRtl8195A(IN u32 Address); 202 | VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect); 203 | VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); 204 | VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara); 205 | u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara); 206 | VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode); 207 | u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk); 208 | VOID SpicDisableRtl8195A(VOID); 209 | 210 | #endif //_HAL_SPIFLASH__ 211 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_ssi.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_SSI_H_ 11 | #define _HAL_SSI_H_ 12 | 13 | #include "rtl8195a_ssi.h" 14 | 15 | /** 16 | * LOG Configurations 17 | */ 18 | 19 | extern u32 SSI_DBG_CONFIG; 20 | extern uint8_t SPI0_IS_AS_SLAVE; 21 | 22 | 23 | #define SSI_DBG_ENTRANCE(...) do {\ 24 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \ 25 | DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \ 26 | }while(0) 27 | 28 | #define SSI_DBG_INIT(...) do {\ 29 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \ 30 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 31 | }while(0) 32 | 33 | #define SSI_DBG_INIT_V(...) do {\ 34 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \ 35 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 36 | }while(0) 37 | 38 | #define SSI_DBG_INIT_VV(...) do {\ 39 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \ 40 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 41 | }while(0) 42 | 43 | #define SSI_DBG_PINMUX(...) do {\ 44 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \ 45 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 46 | }while(0) 47 | 48 | #define SSI_DBG_ENDIS(...) do {\ 49 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \ 50 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 51 | }while(0) 52 | 53 | #define SSI_DBG_INT(...) do {\ 54 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \ 55 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 56 | }while(0) 57 | 58 | #define SSI_DBG_INT_V(...) do {\ 59 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \ 60 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 61 | }while(0) 62 | 63 | #define SSI_DBG_INT_HNDLR(...) do {\ 64 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \ 65 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 66 | }while(0) 67 | 68 | #define SSI_DBG_INT_READ(...) do {\ 69 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \ 70 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 71 | }while(0) 72 | 73 | #define SSI_DBG_INT_WRITE(...) do {\ 74 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \ 75 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 76 | }while(0) 77 | 78 | #define SSI_DBG_STATUS(...) do {\ 79 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \ 80 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 81 | }while(0) 82 | 83 | #define SSI_DBG_FIFO(...) do {\ 84 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \ 85 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 86 | }while(0) 87 | 88 | #define SSI_DBG_READ(...) do {\ 89 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \ 90 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 91 | }while(0) 92 | 93 | #define SSI_DBG_WRITE(...) do {\ 94 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \ 95 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 96 | }while(0) 97 | 98 | #define SSI_DBG_SLV_CTRL(...) do {\ 99 | if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \ 100 | DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \ 101 | }while(0) 102 | 103 | typedef enum _SSI_DBG_TYPE_LIST_ { 104 | DBG_TYPE_ENTRANCE = 1 << 0, 105 | DBG_TYPE_INIT = 1 << 1, 106 | DBG_TYPE_INIT_V = 1 << 2, 107 | DBG_TYPE_INIT_VV = 1 << 3, 108 | DBG_TYPE_PINMUX = 1 << 4, 109 | DBG_TYPE_ENDIS = 1 << 5, 110 | DBG_TYPE_INT = 1 << 6, 111 | DBG_TYPE_INT_V = 1 << 7, 112 | DBG_TYPE_INT_HNDLR = 1 << 8, 113 | DBG_TYPE_INT_READ = 1 << 9, 114 | DBG_TYPE_INT_WRITE = 1 << 10, 115 | DBG_TYPE_STATUS = 1 << 11, 116 | DBG_TYPE_FIFO = 1 << 12, 117 | DBG_TYPE_READ = 1 << 13, 118 | DBG_TYPE_WRITE = 1 << 14, 119 | DBG_TYPE_SLV_CTRL = 1 << 15 120 | } SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST; 121 | 122 | typedef struct _SSI_DMA_CONFIG_ { 123 | VOID *pHalGdmaOp; 124 | VOID *pTxHalGdmaAdapter; 125 | VOID *pRxHalGdmaAdapter; 126 | u8 RxDmaBurstSize; 127 | u8 TxDmaBurstSize; 128 | u8 RxDmaEnable; 129 | u8 TxDmaEnable; 130 | IRQ_HANDLE RxGdmaIrqHandle; 131 | IRQ_HANDLE TxGdmaIrqHandle; 132 | }SSI_DMA_CONFIG, *PSSI_DMA_CONFIG; 133 | 134 | /** 135 | * DesignWare SSI Configurations 136 | */ 137 | typedef struct _HAL_SSI_ADAPTOR_ { 138 | SSI_DMA_CONFIG DmaConfig; 139 | IRQ_HANDLE IrqHandle; 140 | // 141 | VOID (*RxCompCallback)(VOID *Para); 142 | VOID *RxCompCbPara; 143 | VOID *RxData; 144 | VOID (*TxCompCallback)(VOID *Para); 145 | VOID *TxCompCbPara; 146 | VOID *TxData; 147 | u32 DmaRxDataLevel; 148 | u32 DmaTxDataLevel; 149 | u32 InterruptPriority; 150 | u32 RxLength; 151 | u32 RxLengthRemainder; 152 | u32 RxThresholdLevel; 153 | u32 TxLength; 154 | u32 TxThresholdLevel; 155 | u32 SlaveSelectEnable; 156 | // 157 | u16 ClockDivider; 158 | u16 DataFrameNumber; 159 | // 160 | u8 ControlFrameSize; 161 | u8 DataFrameFormat; 162 | u8 DataFrameSize; 163 | u8 DmaControl; 164 | u8 Index; 165 | u8 InterruptMask; 166 | u8 MicrowireDirection; 167 | u8 MicrowireHandshaking; 168 | u8 MicrowireTransferMode; 169 | u8 PinmuxSelect; 170 | u8 Role; 171 | u8 SclkPhase; 172 | u8 SclkPolarity; 173 | u8 SlaveOutputEnable; 174 | u8 TransferMode; 175 | u8 TransferMechanism; 176 | }HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR; 177 | 178 | typedef struct _HAL_SSI_OP_{ 179 | HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor); 180 | HAL_Status (*HalSsiEnable)(VOID *Adaptor); 181 | HAL_Status (*HalSsiDisable)(VOID *Adaptor); 182 | HAL_Status (*HalSsiInit)(VOID *Adaptor); 183 | HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor); 184 | HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor); 185 | HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value); 186 | HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting); 187 | HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor); 188 | HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role); 189 | HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor); 190 | HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor); 191 | HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length); 192 | HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor); 193 | HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor); 194 | HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, VOID *TxData, u32 Length); 195 | HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex); 196 | u32 (*HalSsiBusy)(VOID *Adaptor); 197 | u32 (*HalSsiReadable)(VOID *Adaptor); 198 | u32 (*HalSsiWriteable)(VOID *Adaptor); 199 | u32 (*HalSsiGetInterruptMask)(VOID *Adaptor); 200 | u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor); 201 | u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor); 202 | u32 (*HalSsiGetStatus)(VOID *Adaptor); 203 | u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor); 204 | u32 (*HalSsiRead)(VOID *Adaptor); 205 | u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor); 206 | u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor); 207 | }HAL_SSI_OP, *PHAL_SSI_OP; 208 | 209 | typedef struct _DW_SSI_DEFAULT_SETTING_ { 210 | VOID (*RxCompCallback)(VOID *Para); 211 | VOID *RxCompCbPara; 212 | VOID *RxData; 213 | VOID (*TxCompCallback)(VOID *Para); 214 | VOID *TxCompCbPara; 215 | VOID *TxData; 216 | u32 DmaRxDataLevel; 217 | u32 DmaTxDataLevel; 218 | u32 InterruptPriority; 219 | u32 RxLength; 220 | u32 RxLengthRemainder; 221 | u32 RxThresholdLevel; 222 | u32 TxLength; 223 | u32 TxThresholdLevel; 224 | u32 SlaveSelectEnable; 225 | // 226 | u16 ClockDivider; 227 | u16 DataFrameNumber; 228 | // 229 | u8 ControlFrameSize; 230 | u8 DataFrameFormat; 231 | u8 DataFrameSize; 232 | u8 DmaControl; 233 | //u8 Index; 234 | u8 InterruptMask; 235 | u8 MicrowireDirection; 236 | u8 MicrowireHandshaking; 237 | u8 MicrowireTransferMode; 238 | //u8 PinmuxSelect; 239 | //u8 Role; 240 | u8 SclkPhase; 241 | u8 SclkPolarity; 242 | u8 SlaveOutputEnable; 243 | u8 TransferMode; 244 | u8 TransferMechanism; 245 | } DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING; 246 | 247 | 248 | struct spi_s { 249 | HAL_SSI_ADAPTOR spi_adp; 250 | HAL_SSI_OP spi_op; 251 | }; 252 | 253 | VOID HalSsiOpInit(VOID *Adaptor); 254 | 255 | #endif 256 | 257 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_timer.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_TIMER_H_ 11 | #define _HAL_TIMER_H_ 12 | #include "basic_types.h" 13 | #include "hal_platform.h" 14 | #include "rtl8195a_timer.h" 15 | 16 | typedef enum _TIMER_MODE_ { 17 | FREE_RUN_MODE = 0, 18 | USER_DEFINED = 1 19 | }TIMER_MODE, *PTIMER_MODE; 20 | 21 | 22 | typedef struct _TIMER_ADAPTER_ { 23 | 24 | u32 TimerLoadValueUs; 25 | u32 TimerIrqPriority; 26 | TIMER_MODE TimerMode; 27 | IRQ_HANDLE IrqHandle; 28 | u8 TimerId; 29 | u8 IrqDis; 30 | 31 | }TIMER_ADAPTER, *PTIMER_ADAPTER; 32 | 33 | 34 | typedef struct _HAL_TIMER_OP_ { 35 | u32 (*HalGetTimerId)(u32 *TimerId); 36 | BOOL (*HalTimerInit)(VOID *Data); 37 | u32 (*HalTimerReadCount)(u32 TimerId); 38 | VOID (*HalTimerIrqClear)(u32 TimerId); 39 | VOID (*HalTimerDis)(u32 TimerId); 40 | VOID (*HalTimerEn)(u32 TimerId); 41 | VOID (*HalTimerDumpReg)(u32 TimerId); 42 | }HAL_TIMER_OP, *PHAL_TIMER_OP; 43 | 44 | 45 | VOID HalTimerOpInit( 46 | IN VOID *Data 47 | ); 48 | 49 | 50 | #endif 51 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_uart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _HAL_UART_H_ 11 | #define _HAL_UART_H_ 12 | 13 | #include "rtl8195a_uart.h" 14 | 15 | /** 16 | * RUART Configurations 17 | */ 18 | #define UART_WAIT_FOREVER 0xffffffff 19 | 20 | typedef struct _UART_DMA_CONFIG_ { 21 | u8 TxDmaEnable; 22 | u8 RxDmaEnable; 23 | u8 TxDmaBurstSize; 24 | u8 RxDmaBurstSize; 25 | VOID *pHalGdmaOp; 26 | VOID *pTxHalGdmaAdapter; 27 | VOID *pRxHalGdmaAdapter; 28 | IRQ_HANDLE TxGdmaIrqHandle; 29 | IRQ_HANDLE RxGdmaIrqHandle; 30 | }UART_DMA_CONFIG, *PUART_DMA_CONFIG; 31 | 32 | typedef struct _HAL_RUART_ADAPTER_ { 33 | u32 BaudRate; 34 | u32 FlowControl; 35 | u32 FifoControl; 36 | u32 Interrupts; 37 | u32 TxCount; // how many byte to TX 38 | u32 RxCount; // how many bytes to RX 39 | u8 *pTxBuf; 40 | u8 *pRxBuf; 41 | HAL_UART_State State; // UART state 42 | u8 Status; // Transfer Status 43 | u8 Locked; // is UART locked for operation 44 | u8 UartIndex; 45 | u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits 46 | u8 StopBit; // word length select: 0 -> no stop bit, 1 -> 1 stop bit 47 | u8 Parity; // parity check enable 48 | u8 ParityType; // parity check type 49 | u8 StickParity; 50 | u8 ModemStatus; // the modem status 51 | u8 DmaEnable; 52 | u8 TestCaseNumber; 53 | u8 PinmuxSelect; 54 | BOOL PullMode; 55 | IRQ_HANDLE IrqHandle; 56 | PUART_DMA_CONFIG DmaConfig; 57 | VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler 58 | VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function 59 | VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function 60 | VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function 61 | VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function 62 | VOID *TxTDCbPara; // the pointer agrument for TxTDCallback 63 | VOID *RxDRCbPara; // the pointer agrument for RxDRCallback 64 | VOID *TxCompCbPara; // the pointer argument for TxCompCbPara 65 | VOID *RxCompCbPara; // the pointer argument for RxCompCallback 66 | VOID (*EnterCritical)(void); 67 | VOID (*ExitCritical)(void); 68 | }HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER; 69 | 70 | typedef struct _HAL_RUART_OP_ { 71 | VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting 72 | VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting 73 | VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting 74 | HAL_Status (*HalRuartResetRxFifo)(VOID *Data); 75 | HAL_Status (*HalRuartInit)(VOID *Data); 76 | VOID (*HalRuartDeInit)(VOID *Data); 77 | HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData); 78 | u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout); 79 | HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length); 80 | HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length); 81 | HAL_Status (*HalRuartStopSend)(VOID *Data); 82 | HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte); 83 | u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout); 84 | HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length); 85 | HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length); 86 | HAL_Status (*HalRuartStopRecv)(VOID *Data); 87 | u8 (*HalRuartGetIMR)(VOID *Data); 88 | VOID (*HalRuartSetIMR)(VOID *Data); 89 | u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel); 90 | VOID (*HalRuartDmaInit)(VOID *Data); 91 | VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl); 92 | VOID (*HalRuartRegIrq)(VOID *Data); 93 | VOID (*HalRuartIntEnable)(VOID *Data); 94 | VOID (*HalRuartIntDisable)(VOID *Data); 95 | }HAL_RUART_OP, *PHAL_RUART_OP; 96 | 97 | typedef struct _RUART_DATA_ { 98 | PHAL_RUART_ADAPTER pHalRuartAdapter; 99 | BOOL PullMode; 100 | u8 BinaryData; 101 | u8 SendBuffer; 102 | u8 RecvBuffer; 103 | }RUART_DATA, *PRUART_DATA; 104 | 105 | typedef struct _RUART_ADAPTER_ { 106 | PHAL_RUART_OP pHalRuartOp; 107 | PHAL_RUART_ADAPTER pHalRuartAdapter; 108 | PUART_DMA_CONFIG pHalRuartDmaCfg; 109 | }RUART_ADAPTER, *PRUART_ADAPTER; 110 | 111 | VOID 112 | HalRuartOpInit( 113 | IN VOID *Data 114 | ); 115 | 116 | extern const HAL_RUART_OP _HalRuartOp; 117 | 118 | #endif 119 | 120 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_util.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | #ifndef _HAL_UTIL_H_ 10 | #define _HAL_UTIL_H_ 11 | 12 | #ifdef __cplusplus 13 | extern "C" { 14 | #endif 15 | 16 | /* 17 | * Simple doubly linked list implementation. 18 | * 19 | * Some of the internal functions ("__xxx") are useful when 20 | * manipulating whole lists rather than single entries, as 21 | * sometimes we already know the next/prev entries and we can 22 | * generate better code by using them directly rather than 23 | * using the generic single-entry routines. 24 | */ 25 | struct LIST_HEADER { 26 | struct LIST_HEADER *Next, *Prev; 27 | }; 28 | 29 | typedef struct LIST_HEADER _LIST; 30 | 31 | //#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) } 32 | 33 | #define RTL_INIT_LIST_HEAD(ptr) do { \ 34 | (ptr)->Next = (ptr); (ptr)->Prev = (ptr); \ 35 | } while (0) 36 | 37 | 38 | /* 39 | * Insert a new entry between two known consecutive entries. 40 | * 41 | * This is only for internal list manipulation where we know 42 | * the prev/next entries already! 43 | */ 44 | static __inline__ VOID 45 | __List_Add( 46 | IN struct LIST_HEADER * New, 47 | IN struct LIST_HEADER * Prev, 48 | IN struct LIST_HEADER * Next 49 | ) 50 | { 51 | Next->Prev = New; 52 | New->Next = Next; 53 | New->Prev = Prev; 54 | Prev->Next = New; 55 | } 56 | 57 | /* 58 | * Delete a list entry by making the prev/next entries 59 | * point to each other. 60 | * 61 | * This is only for internal list manipulation where we know 62 | * the prev/next entries already! 63 | */ 64 | static __inline__ VOID 65 | __List_Del( 66 | IN struct LIST_HEADER * Prev, 67 | IN struct LIST_HEADER * Next 68 | ) 69 | { 70 | Next->Prev = Prev; 71 | Prev->Next = Next; 72 | } 73 | 74 | /** 75 | * ListDel - deletes entry from list. 76 | * @entry: the element to delete from the list. 77 | * Note: list_empty on entry does not return true after this, the entry is in an undefined state. 78 | */ 79 | static __inline__ VOID 80 | ListDel( 81 | IN struct LIST_HEADER *Entry 82 | ) 83 | { 84 | __List_Del(Entry->Prev, Entry->Next); 85 | } 86 | 87 | /** 88 | * ListDelInit - deletes entry from list and reinitialize it. 89 | * @entry: the element to delete from the list. 90 | */ 91 | static __inline__ VOID 92 | ListDelInit( 93 | IN struct LIST_HEADER *Entry 94 | ) 95 | { 96 | __List_Del(Entry->Prev, Entry->Next); 97 | RTL_INIT_LIST_HEAD(Entry); 98 | 99 | } 100 | 101 | /** 102 | * ListEmpty - tests whether a list is empty 103 | * @head: the list to test. 104 | */ 105 | static __inline__ u32 106 | ListEmpty( 107 | IN struct LIST_HEADER *Head 108 | ) 109 | { 110 | return Head->Next == Head; 111 | } 112 | 113 | /** 114 | * ListSplice - join two lists 115 | * @list: the new list to add. 116 | * @head: the place to add it in the first list. 117 | */ 118 | static __inline__ VOID 119 | ListSplice( 120 | IN struct LIST_HEADER *List, 121 | IN struct LIST_HEADER *Head 122 | ) 123 | { 124 | struct LIST_HEADER *First = List->Next; 125 | 126 | if (First != List) { 127 | struct LIST_HEADER *Last = List->Prev; 128 | struct LIST_HEADER *At = Head->Next; 129 | 130 | First->Prev = Head; 131 | Head->Next = First; 132 | 133 | Last->Next = At; 134 | At->Prev = Last; 135 | } 136 | } 137 | 138 | static __inline__ VOID 139 | ListAdd( 140 | IN struct LIST_HEADER *New, 141 | IN struct LIST_HEADER *head 142 | ) 143 | { 144 | __List_Add(New, head, head->Next); 145 | } 146 | 147 | 148 | static __inline__ VOID 149 | ListAddTail( 150 | IN struct LIST_HEADER *New, 151 | IN struct LIST_HEADER *head 152 | ) 153 | { 154 | __List_Add(New, head->Prev, head); 155 | } 156 | 157 | static __inline VOID 158 | RtlInitListhead( 159 | IN _LIST *list 160 | ) 161 | { 162 | RTL_INIT_LIST_HEAD(list); 163 | } 164 | 165 | 166 | /* 167 | For the following list_xxx operations, 168 | caller must guarantee the atomic context. 169 | Otherwise, there will be racing condition. 170 | */ 171 | static __inline u32 172 | RtlIsListEmpty( 173 | IN _LIST *phead 174 | ) 175 | { 176 | 177 | if (ListEmpty(phead)) 178 | return _TRUE; 179 | else 180 | return _FALSE; 181 | 182 | } 183 | 184 | static __inline VOID 185 | RtlListInsertHead( 186 | IN _LIST *plist, 187 | IN _LIST *phead 188 | ) 189 | { 190 | ListAdd(plist, phead); 191 | } 192 | 193 | static __inline VOID 194 | RtlListInsertTail( 195 | IN _LIST *plist, 196 | IN _LIST *phead 197 | ) 198 | { 199 | ListAddTail(plist, phead); 200 | } 201 | 202 | 203 | static __inline _LIST 204 | *RtlListGetNext( 205 | IN _LIST *plist 206 | ) 207 | { 208 | return plist->Next; 209 | } 210 | 211 | static __inline VOID 212 | RtlListDelete( 213 | IN _LIST *plist 214 | ) 215 | { 216 | ListDelInit(plist); 217 | } 218 | 219 | #define RTL_LIST_CONTAINOR(ptr, type, member) \ 220 | ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) 221 | 222 | #ifndef CONTAINER_OF 223 | #define CONTAINER_OF(ptr, type, member) \ 224 | ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) 225 | #endif 226 | 227 | #define list_entry(ptr, type, member) \ 228 | CONTAINER_OF(ptr, type, member) 229 | 230 | #define list_first_entry(ptr, type, member) \ 231 | list_entry((ptr)->Next, type, member) 232 | 233 | #define list_next_entry(pos, member, type) \ 234 | list_entry((pos)->member.Next, type, member) 235 | 236 | #define list_for_each_entry(pos, head, member, type) \ 237 | for (pos = list_first_entry(head, type, member); \ 238 | &pos->member != (head); \ 239 | pos = list_next_entry(pos, member, type)) 240 | #define list_for_each(pos, head) \ 241 | for (pos = (head)->Next; pos != (head); pos = pos->Next) 242 | 243 | 244 | #ifndef BIT 245 | #define BIT(x) ( 1 << (x)) 246 | #endif 247 | 248 | #ifdef __cplusplus 249 | } 250 | #endif 251 | 252 | #endif //_HAL_UTIL_H_ 253 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/hal_vector_table.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | 11 | #ifndef _HAL_VECTOR_TABLE_H_ 12 | #define _HAL_VECTOR_TABLE_H_ 13 | 14 | 15 | 16 | 17 | extern _LONG_CALL_ VOID 18 | VectorTableInitRtl8195A( 19 | IN u32 StackP 20 | ); 21 | 22 | extern _LONG_CALL_ VOID 23 | VectorTableInitForOSRtl8195A( 24 | IN VOID *PortSVC, 25 | IN VOID *PortPendSVH, 26 | IN VOID *PortSysTick 27 | ); 28 | 29 | extern _LONG_CALL_ BOOL 30 | VectorIrqRegisterRtl8195A( 31 | IN PIRQ_HANDLE pIrqHandle 32 | ); 33 | 34 | extern _LONG_CALL_ BOOL 35 | VectorIrqUnRegisterRtl8195A( 36 | IN PIRQ_HANDLE pIrqHandle 37 | ); 38 | 39 | 40 | extern _LONG_CALL_ VOID 41 | VectorIrqEnRtl8195A( 42 | IN PIRQ_HANDLE pIrqHandle 43 | ); 44 | 45 | extern _LONG_CALL_ VOID 46 | VectorIrqDisRtl8195A( 47 | IN PIRQ_HANDLE pIrqHandle 48 | ); 49 | 50 | 51 | extern _LONG_CALL_ VOID 52 | HalPeripheralIntrHandle(VOID); 53 | #endif //_HAL_VECTOR_TABLE_H_ 54 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/rtl8195a/rtl8195a.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | #ifndef _HAL_8195A_H_ 10 | #define _HAL_8195A_H_ 11 | 12 | #include "platform_options.h" 13 | #include "basic_types.h" 14 | #include "section_config.h" 15 | #include "rtl8195a_sys_on.h" 16 | #include "rtl8195a_peri_on.h" 17 | #include "hal_platform.h" 18 | #include "hal_pinmux.h" 19 | #include "hal_api.h" 20 | #include "hal_peri_on.h" 21 | #include "hal_misc.h" 22 | #include "hal_irqn.h" 23 | #include "hal_vector_table.h" 24 | #include "hal_diag.h" 25 | #include "hal_spi_flash.h" 26 | #include "hal_timer.h" 27 | #include "hal_util.h" 28 | #include "hal_efuse.h" 29 | #include "diag.h" 30 | 31 | /* ---------------------------------------------------------------------------- 32 | -- Cortex M3 Core Configuration 33 | ---------------------------------------------------------------------------- */ 34 | 35 | /*! 36 | * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 37 | * @{ 38 | */ 39 | 40 | #define __CM3_REV 0x0200 /**< Core revision r0p0 */ 41 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ 42 | #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ 43 | #define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */ 44 | 45 | #include "core_cm3.h" 46 | 47 | #include "hal_timer.h" 48 | 49 | #ifdef CONFIG_GDMA_EN 50 | #include "hal_gdma.h" 51 | #include "rtl8195a_gdma.h" 52 | #endif 53 | 54 | #ifdef CONFIG_GPIO_EN 55 | #include "hal_gpio.h" 56 | #include "rtl8195a_gpio.h" 57 | #endif 58 | 59 | #ifdef CONFIG_SPI_COM_EN 60 | #include "hal_ssi.h" 61 | #include "rtl8195a_ssi.h" 62 | #endif 63 | 64 | #ifdef CONFIG_UART_EN 65 | #include "hal_uart.h" 66 | #include "rtl8195a_uart.h" 67 | #endif 68 | 69 | #ifdef CONFIG_I2C_EN 70 | #include "hal_i2c.h" 71 | #include "rtl8195a_i2c.h" 72 | #endif 73 | 74 | #ifdef CONFIG_PCM_EN 75 | #include "hal_pcm.h" 76 | #include "rtl8195a_pcm.h" 77 | #endif 78 | 79 | #ifdef CONFIG_PWM_EN 80 | #include "hal_pwm.h" 81 | #include "rtl8195a_pwm.h" 82 | #endif 83 | 84 | #ifdef CONFIG_I2S_EN 85 | #include "hal_i2s.h" 86 | #include "rtl8195a_i2s.h" 87 | #endif 88 | 89 | #ifdef CONFIG_DAC_EN 90 | #include "hal_dac.h" 91 | #include "rtl8195a_dac.h" 92 | #endif 93 | 94 | #ifdef CONFIG_ADC_EN 95 | #include "hal_adc.h" 96 | #include "rtl8195a_adc.h" 97 | #endif 98 | 99 | 100 | 101 | #ifdef CONFIG_SDIO_DEVICE_EN 102 | #include "hal_sdio.h" 103 | #endif 104 | 105 | #ifdef CONFIG_NFC_EN 106 | #include "hal_nfc.h" 107 | #include "rtl8195a_nfc.h" 108 | #endif 109 | 110 | 111 | #endif //_HAL_8195A_H_ 112 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/rtl8195a/rtl8195a_dac.h: -------------------------------------------------------------------------------- 1 | #ifndef _RTL8195A_DAC_H_ 2 | #define _RTL8195A_DAC_H_ 3 | 4 | //================ Register Bit Field ========================== 5 | //2 REG_DAC0_FIFO_WR 6 | 7 | #define BIT_SHIFT_DAC0_FIFO_WO 0 8 | #define BIT_MASK_DAC0_FIFO_WO 0xffffffffL 9 | #define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) 10 | #define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO) 11 | #define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO) 12 | 13 | 14 | //2 REG_DAC_CTRL 15 | 16 | #define BIT_SHIFT_DAC_DELTA_SIGMA 25 17 | #define BIT_MASK_DAC_DELTA_SIGMA 0x7 18 | #define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) 19 | #define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA) 20 | #define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA) 21 | 22 | #define BIT_DAC_BYPASS_DSC BIT(24) 23 | #define BIT_SHIFT_DAC_BYPASS_DSC 24 24 | #define BIT_MASK_DAC_BYPASS_DSC 0x1 25 | #define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC) 26 | 27 | 28 | #define BIT_SHIFT_DAC_DSC_DBG_SEL 19 29 | #define BIT_MASK_DAC_DSC_DBG_SEL 0x3 30 | #define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) 31 | #define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL) 32 | #define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL) 33 | 34 | 35 | #define BIT_SHIFT_DAC_DBG_SEL 16 36 | #define BIT_MASK_DAC_DBG_SEL 0x7 37 | #define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) 38 | #define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL) 39 | #define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL) 40 | 41 | 42 | #define BIT_SHIFT_DAC_BURST_SIZE 8 43 | #define BIT_MASK_DAC_BURST_SIZE 0xf 44 | #define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) 45 | #define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE) 46 | #define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE) 47 | 48 | #define BIT_DAC_FILTER_SETTLE BIT(4) 49 | #define BIT_SHIFT_DAC_FILTER_SETTLE 4 50 | #define BIT_MASK_DAC_FILTER_SETTLE 0x1 51 | #define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE) 52 | 53 | #define BIT_DAC_OV_OPTION BIT(3) 54 | #define BIT_SHIFT_DAC_OV_OPTION 3 55 | #define BIT_MASK_DAC_OV_OPTION 0x1 56 | #define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION) 57 | 58 | #define BIT_DAC_ENDIAN BIT(2) 59 | #define BIT_SHIFT_DAC_ENDIAN 2 60 | #define BIT_MASK_DAC_ENDIAN 0x1 61 | #define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN) 62 | 63 | #define BIT_DAC_SPEED BIT(1) 64 | #define BIT_SHIFT_DAC_SPEED 1 65 | #define BIT_MASK_DAC_SPEED 0x1 66 | #define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED) 67 | 68 | #define BIT_DAC_FIFO_EN BIT(0) 69 | #define BIT_SHIFT_DAC_FIFO_EN 0 70 | #define BIT_MASK_DAC_FIFO_EN 0x1 71 | #define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN) 72 | 73 | 74 | //2 REG_DAC_INTR_CTRL 75 | #define BIT_DAC_DSC_OVERFLOW1_EN BIT(6) 76 | #define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6 77 | #define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1 78 | #define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN) 79 | 80 | #define BIT_DAC_DSC_OVERFLOW0_EN BIT(5) 81 | #define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5 82 | #define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1 83 | #define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN) 84 | 85 | #define BIT_DAC__WRITE_ERROR_EN BIT(4) 86 | #define BIT_SHIFT_DAC__WRITE_ERROR_EN 4 87 | #define BIT_MASK_DAC__WRITE_ERROR_EN 0x1 88 | #define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN) 89 | 90 | #define BIT_DAC_FIFO_STOP_EN BIT(3) 91 | #define BIT_SHIFT_DAC_FIFO_STOP_EN 3 92 | #define BIT_MASK_DAC_FIFO_STOP_EN 0x1 93 | #define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN) 94 | 95 | #define BIT_DAC_FIFO_OVERFLOW_EN BIT(2) 96 | #define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2 97 | #define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1 98 | #define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN) 99 | 100 | #define BIT_DAC_FIFO_WR_REQ_EN BIT(1) 101 | #define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1 102 | #define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1 103 | #define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN) 104 | 105 | #define BIT_DAC_FIFO_FULL_EN BIT(0) 106 | #define BIT_SHIFT_DAC_FIFO_FULL_EN 0 107 | #define BIT_MASK_DAC_FIFO_FULL_EN 0x1 108 | #define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN) 109 | 110 | 111 | //2 REG_DAC_INTR_STS 112 | #define BIT_DAC_DSC_OVERFLOW1_ST BIT(6) 113 | #define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6 114 | #define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1 115 | #define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST) 116 | 117 | #define BIT_DAC_DSC_OVERFLOW0_ST BIT(5) 118 | #define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5 119 | #define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1 120 | #define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST) 121 | 122 | #define BIT_DAC__WRITE_ERROR_ST BIT(4) 123 | #define BIT_SHIFT_DAC__WRITE_ERROR_ST 4 124 | #define BIT_MASK_DAC__WRITE_ERROR_ST 0x1 125 | #define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST) 126 | 127 | #define BIT_DAC_FIFO_STOP_ST BIT(3) 128 | #define BIT_SHIFT_DAC_FIFO_STOP_ST 3 129 | #define BIT_MASK_DAC_FIFO_STOP_ST 0x1 130 | #define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST) 131 | 132 | #define BIT_DAC_FIFO_OVERFLOW_ST BIT(2) 133 | #define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2 134 | #define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1 135 | #define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST) 136 | 137 | #define BIT_DAC_FIFO_WR_REQ_ST BIT(1) 138 | #define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1 139 | #define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1 140 | #define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST) 141 | 142 | #define BIT_DAC_FIFO_FULL_ST BIT(0) 143 | #define BIT_SHIFT_DAC_FIFO_FULL_ST 0 144 | #define BIT_MASK_DAC_FIFO_FULL_ST 0x1 145 | #define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST) 146 | 147 | 148 | //2 REG_DAC_PWR_CTRL 149 | 150 | #define BIT_SHIFT_DAC_PWR_CUT_CNTR 16 151 | #define BIT_MASK_DAC_PWR_CUT_CNTR 0xff 152 | #define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) 153 | #define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR) 154 | #define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR) 155 | 156 | #define BIT_ST_DAC_FIFO_ON BIT(11) 157 | #define BIT_SHIFT_ST_DAC_FIFO_ON 11 158 | #define BIT_MASK_ST_DAC_FIFO_ON 0x1 159 | #define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON) 160 | 161 | #define BIT_ST_DAC_ISO_ON BIT(10) 162 | #define BIT_SHIFT_ST_DAC_ISO_ON 10 163 | #define BIT_MASK_ST_DAC_ISO_ON 0x1 164 | #define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON) 165 | 166 | #define BIT_ST_DAC_PWR33_ON BIT(9) 167 | #define BIT_SHIFT_ST_DAC_PWR33_ON 9 168 | #define BIT_MASK_ST_DAC_PWR33_ON 0x1 169 | #define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON) 170 | 171 | #define BIT_ST_DAC_PWR12_ON BIT(8) 172 | #define BIT_SHIFT_ST_DAC_PWR12_ON 8 173 | #define BIT_MASK_ST_DAC_PWR12_ON 0x1 174 | #define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON) 175 | 176 | #define BIT_DAC_ISO_MANU BIT(3) 177 | #define BIT_SHIFT_DAC_ISO_MANU 3 178 | #define BIT_MASK_DAC_ISO_MANU 0x1 179 | #define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU) 180 | 181 | #define BIT_DAC_PWR33_MANU BIT(2) 182 | #define BIT_SHIFT_DAC_PWR33_MANU 2 183 | #define BIT_MASK_DAC_PWR33_MANU 0x1 184 | #define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU) 185 | 186 | #define BIT_DAC_PWR12_MANU BIT(1) 187 | #define BIT_SHIFT_DAC_PWR12_MANU 1 188 | #define BIT_MASK_DAC_PWR12_MANU 0x1 189 | #define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU) 190 | 191 | #define BIT_DAC_PWR_AUTO BIT(0) 192 | #define BIT_SHIFT_DAC_PWR_AUTO 0 193 | #define BIT_MASK_DAC_PWR_AUTO 0x1 194 | #define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO) 195 | 196 | 197 | //2 REG_DAC_ANAPAR_DA0 198 | 199 | #define BIT_SHIFT_PWR_ALL_CNTR 12 200 | #define BIT_MASK_PWR_ALL_CNTR 0xfffff 201 | #define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) 202 | #define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR) 203 | #define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR) 204 | 205 | 206 | #define BIT_SHIFT_PWR_FUP_CNTR 0 207 | #define BIT_MASK_PWR_FUP_CNTR 0xfff 208 | #define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) 209 | #define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR) 210 | #define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR) 211 | 212 | 213 | //2 REG_DAC_ANAPAR_DA1 214 | #define BIT_FUP_EN BIT(31) 215 | #define BIT_SHIFT_FUP_EN 31 216 | #define BIT_MASK_FUP_EN 0x1 217 | #define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN) 218 | 219 | 220 | #define BIT_SHIFT_ANAPAR_DA 8 221 | #define BIT_MASK_ANAPAR_DA 0x7fffff 222 | #define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) 223 | #define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA) 224 | #define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA) 225 | 226 | #define BIT_D_POW_DACVREF BIT(7) 227 | #define BIT_SHIFT_D_POW_DACVREF 7 228 | #define BIT_MASK_D_POW_DACVREF 0x1 229 | #define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF) 230 | 231 | #define BIT_D_POW_VREF2 BIT(6) 232 | #define BIT_SHIFT_D_POW_VREF2 6 233 | #define BIT_MASK_D_POW_VREF2 0x1 234 | #define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2) 235 | 236 | #define BIT_D_POW_MBIAS BIT(5) 237 | #define BIT_SHIFT_D_POW_MBIAS 5 238 | #define BIT_MASK_D_POW_MBIAS 0x1 239 | #define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS) 240 | 241 | #define BIT_D_POW_DIV4 BIT(4) 242 | #define BIT_SHIFT_D_POW_DIV4 4 243 | #define BIT_MASK_D_POW_DIV4 0x1 244 | #define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4) 245 | 246 | #define BIT_D_POW_DF1SE_R BIT(3) 247 | #define BIT_SHIFT_D_POW_DF1SE_R 3 248 | #define BIT_MASK_D_POW_DF1SE_R 0x1 249 | #define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R) 250 | 251 | #define BIT_D_POW_DF2SE_L BIT(2) 252 | #define BIT_SHIFT_D_POW_DF2SE_L 2 253 | #define BIT_MASK_D_POW_DF2SE_L 0x1 254 | #define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L) 255 | 256 | #define BIT_D_POW_DAC_R BIT(1) 257 | #define BIT_SHIFT_D_POW_DAC_R 1 258 | #define BIT_MASK_D_POW_DAC_R 0x1 259 | #define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R) 260 | 261 | #define BIT_D_POW_DAC_L BIT(0) 262 | #define BIT_SHIFT_D_POW_DAC_L 0 263 | #define BIT_MASK_D_POW_DAC_L 0x1 264 | #define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L) 265 | 266 | 267 | //================ Register Reg Field ========================= 268 | #define REG_DAC0_FIFO_WR 0x0000 269 | #define REG_DAC_CTRL 0x0004 270 | #define REG_DAC_INTR_CTRL 0x0008 271 | #define REG_DAC_INTR_STS 0x000C 272 | #define REG_DAC_PWR_CTRL 0x0010 273 | #define REG_DAC_ANAPAR_DA0 0x0014 274 | #define REG_DAC_ANAPAR_DA1 0x0018 275 | 276 | 277 | //================ DAC HAL related enumeration ================== 278 | 279 | 280 | //================ DAC HAL Macro =========================== 281 | #define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \ 282 | ,addr,value) 283 | #define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr) 284 | 285 | 286 | //================ DAC Function Prototypes ===================== 287 | RTK_STATUS HalDACInit8195a(IN VOID *Data); 288 | RTK_STATUS HalDACDeInit8195a(IN VOID *Data); 289 | RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data); 290 | RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data); 291 | u8 HalDACSendRtl8195a(IN VOID *Data); 292 | u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg); 293 | 294 | #endif 295 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/rtl8195a/rtl8195a_gpio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | 11 | #ifndef _RTL8195A_GPIO_H_ 12 | #define _RTL8195A_GPIO_H_ 13 | 14 | #include "hal_api.h" 15 | #include "hal_gpio.h" 16 | 17 | #define GPIO_PORTA_DR 0x00 // data register 18 | #define GPIO_PORTA_DDR 0x04 // data direction 19 | #define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software 20 | 21 | #define GPIO_PORTB_DR 0x0c // data register 22 | #define GPIO_PORTB_DDR 0x10 // data direction 23 | #define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software 24 | 25 | #define GPIO_PORTC_DR 0x18 // data register 26 | #define GPIO_PORTC_DDR 0x1c // data direction 27 | #define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software 28 | 29 | //1 Only the PORTA can be configured to generate interrupts 30 | #define GPIO_INT_EN 0x30 // Interrupt enable register 31 | #define GPIO_INT_MASK 0x34 // Interrupt mask 32 | #define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register 33 | #define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register 34 | #define GPIO_INT_STATUS 0x40 // Interrupt status 35 | #define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask 36 | #define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce 37 | #define GPIO_PORTA_EOI 0x4c // Clear interrupt 38 | 39 | #define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back 40 | #define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back 41 | #define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back 42 | 43 | #define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK 44 | 45 | enum { 46 | HAL_GPIO_HIGHZ = 0, 47 | HAL_GPIO_PULL_LOW = 1, 48 | HAL_GPIO_PULL_HIGH = 2 49 | }; 50 | 51 | extern u32 52 | HAL_GPIO_IrqHandler_8195a( 53 | IN VOID *pData 54 | ); 55 | 56 | extern u32 57 | HAL_GPIO_MbedIrqHandler_8195a( 58 | IN VOID *pData 59 | ); 60 | 61 | extern u32 62 | HAL_GPIO_MbedIrqHandler_8195a( 63 | IN VOID *pData 64 | ); 65 | 66 | HAL_Status 67 | HAL_GPIO_IntCtrl_8195a( 68 | HAL_GPIO_PIN *GPIO_Pin, 69 | u32 En 70 | ); 71 | 72 | HAL_Status 73 | HAL_GPIO_Init_8195a( 74 | HAL_GPIO_PIN *GPIO_Pin 75 | ); 76 | 77 | HAL_Status 78 | HAL_GPIO_DeInit_8195a( 79 | HAL_GPIO_PIN *GPIO_Pin 80 | ); 81 | 82 | HAL_GPIO_PIN_STATE 83 | HAL_GPIO_ReadPin_8195a( 84 | HAL_GPIO_PIN *GPIO_Pin 85 | ); 86 | 87 | HAL_Status 88 | HAL_GPIO_WritePin_8195a( 89 | HAL_GPIO_PIN *GPIO_Pin, 90 | HAL_GPIO_PIN_STATE Pin_State 91 | ); 92 | 93 | HAL_Status 94 | HAL_GPIO_RegIrq_8195a( 95 | IN PIRQ_HANDLE pIrqHandle 96 | ); 97 | 98 | HAL_Status 99 | HAL_GPIO_UnRegIrq_8195a( 100 | IN PIRQ_HANDLE pIrqHandle 101 | ); 102 | 103 | HAL_Status 104 | HAL_GPIO_UserRegIrq_8195a( 105 | HAL_GPIO_PIN *GPIO_Pin, 106 | VOID *IrqHandler, 107 | VOID *IrqData 108 | ); 109 | 110 | HAL_Status 111 | HAL_GPIO_UserUnRegIrq_8195a( 112 | HAL_GPIO_PIN *GPIO_Pin 113 | ); 114 | 115 | HAL_Status 116 | HAL_GPIO_MaskIrq_8195a( 117 | HAL_GPIO_PIN *GPIO_Pin 118 | ); 119 | 120 | HAL_Status 121 | HAL_GPIO_UnMaskIrq_8195a( 122 | HAL_GPIO_PIN *GPIO_Pin 123 | ); 124 | 125 | HAL_Status 126 | HAL_GPIO_IntDebounce_8195a( 127 | HAL_GPIO_PIN *GPIO_Pin, 128 | u8 Enable 129 | ); 130 | 131 | u32 132 | HAL_GPIO_GetIPPinName_8195a( 133 | u32 chip_pin 134 | ); 135 | 136 | HAL_Status 137 | HAL_GPIO_PullCtrl_8195a( 138 | u32 chip_pin, 139 | u8 pull_type 140 | ); 141 | 142 | #endif // end of "#define _RTL8195A_GPIO_H_" 143 | 144 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/rtl8195a/rtl8195a_pwm.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | 11 | #ifndef _RTL8195A_PWM_H_ 12 | #define _RTL8195A_PWM_H_ 13 | 14 | extern void 15 | HAL_Pwm_SetDuty_8195a( 16 | HAL_PWM_ADAPTER *pPwmAdapt, 17 | u32 period, 18 | u32 pulse_width 19 | ); 20 | 21 | extern HAL_Status 22 | HAL_Pwm_Init_8195a( 23 | HAL_PWM_ADAPTER *pPwmAdapt 24 | ); 25 | 26 | extern void 27 | HAL_Pwm_Enable_8195a( 28 | HAL_PWM_ADAPTER *pPwmAdapt 29 | ); 30 | 31 | extern void 32 | HAL_Pwm_Disable_8195a( 33 | HAL_PWM_ADAPTER *pPwmAdapt 34 | ); 35 | 36 | 37 | #endif 38 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/rtl8195a/rtl8195a_timer.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | #ifndef _RTL8195A_TIMER_H_ 11 | #define _RTL8195A_TIMER_H_ 12 | 13 | 14 | #define TIMER_TICK_US 31 15 | 16 | #define TIMER_LOAD_COUNT_OFF 0x00 17 | #define TIMER_CURRENT_VAL_OFF 0x04 18 | #define TIMER_CTL_REG_OFF 0x08 19 | #define TIMER_EOI_OFF 0x0c 20 | #define TIMER_INT_STATUS_OFF 0x10 21 | #define TIMER_INTERVAL 0x14 22 | #define TIMERS_INT_STATUS_OFF 0xa0 23 | #define TIMERS_EOI_OFF 0xa4 24 | #define TIMERS_RAW_INT_STATUS_OFF 0xa8 25 | #define TIMERS_COMP_VER_OFF 0xac 26 | 27 | #define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr) 28 | #define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value) 29 | #define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr) 30 | #define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value) 31 | #define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr) 32 | #define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value) 33 | 34 | u32 35 | HalGetTimerIdRtl8195a( 36 | IN u32 *TimerID 37 | ); 38 | 39 | BOOL 40 | HalTimerInitRtl8195a( 41 | IN VOID *Data 42 | ); 43 | 44 | u32 45 | HalTimerReadCountRtl8195a( 46 | IN u32 TimerId 47 | ); 48 | 49 | VOID 50 | HalTimerIrqClearRtl8195a( 51 | IN u32 TimerId 52 | ); 53 | 54 | VOID 55 | HalTimerDisRtl8195a( 56 | IN u32 TimerId 57 | ); 58 | 59 | VOID 60 | HalTimerEnRtl8195a( 61 | IN u32 TimerId 62 | ); 63 | 64 | VOID 65 | HalTimerDumpRegRtl8195a( 66 | IN u32 TimerId 67 | ); 68 | 69 | 70 | u32 71 | HalTimerReadCountRamRtl8195a( 72 | IN u32 TimerId 73 | ); 74 | 75 | #endif //_RTL8195A_TIMER_H_ 76 | -------------------------------------------------------------------------------- /sdk/src/targets/hal/target_rtk/target_8195a/rtl8195a/rtl8195a_uart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Routines to access hardware 3 | * 4 | * Copyright (c) 2013 Realtek Semiconductor Corp. 5 | * 6 | * This module is a confidential and proprietary property of RealTek and 7 | * possession or use of this module requires written permission of RealTek. 8 | */ 9 | 10 | 11 | #ifndef _RTL8195A_UART_H_ 12 | #define _RTL8195A_UART_H_ 13 | 14 | 15 | #define RUART_DLL_OFF 0x00 16 | #define RUART_DLM_OFF 0x04 //RW, DLAB = 1 17 | #define RUART_INTERRUPT_EN_REG_OFF 0x04 18 | #define RUART_IER_ERBI 0x01 //BIT0, Enable Received Data Available Interrupt (rx trigger) 19 | #define RUART_IER_ETBEI (1<<1) //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty) 20 | #define RUART_IER_ELSI (1<<2) //BIT2, Enable Receiver Line Status Interrupt (receiver line status) 21 | #define RUART_IER_EDSSI (1<<3) //BIT3, Enable Modem Status Interrupt (modem status transition) 22 | 23 | #define RUART_INT_ID_REG_OFF 0x08 //[R] 24 | #define RUART_IIR_INT_PEND 0x01 25 | #define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0) 26 | #define RUART_FIFO_CTL_REG_OFF 0x08 //[W] 27 | #define RUART_FIFO_CTL_REG_CLEAR_RXFIFO (1<<1) //BIT1, 0x02, Write 1 clear 28 | #define RUART_FIFO_CTL_REG_DMA_ENABLE 0x08 //BIT3 29 | 30 | #define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9 31 | #define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1 32 | 33 | #define RUART_MODEM_CTL_REG_OFF 0x10 34 | #define RUART_MCR_RTS BIT1 35 | #define RUART_MCL_AUTOFLOW_ENABLE (1<<5) //BIT5, 0x20 36 | 37 | #define RUART_LINE_CTL_REG_OFF 0x0C 38 | #define RUART_LINE_CTL_REG_DLAB_ENABLE (1<<7) //BIT7, 0x80 39 | 40 | #define RUART_LINE_STATUS_REG_OFF 0x14 41 | #define RUART_LINE_STATUS_REG_DR 0x01 //BIT0, Data Ready indicator 42 | #define RUART_LINE_STATUS_ERR_OVERRUN (1<<1) //BIT1, Over Run 43 | #define RUART_LINE_STATUS_ERR_PARITY (1<<2) //BIT2, Parity error 44 | #define RUART_LINE_STATUS_ERR_FRAMING (1<<3) //BIT3, Framing error 45 | #define RUART_LINE_STATUS_ERR_BREAK (1<<4) //BIT4, Break interrupt error 46 | #define RUART_LINE_STATUS_REG_THRE (1<<5) //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable 47 | #define RUART_LINE_STATUS_REG_TEMT (1<<6) //BIT6, 0x40, Transmitter Empty indicator(bit) 48 | #define RUART_LINE_STATUS_ERR_RXFIFO (1<<7) //BIT7, RX FIFO error 49 | #define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \ 50 | RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \ 51 | RUART_LINE_STATUS_ERR_RXFIFO) //Line status error 52 | 53 | #define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register 54 | #define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register 55 | #define RUART_SP_REG_RXBREAK_INT_STATUS (1<<7) //BIT7, 0x80, Write 1 clear 56 | #define RUART_SP_REG_DBG_SEL 0x0F<<8 //[11:8], Debug port selection 57 | #define RUART_SP_REG_XFACTOR_ADJ 0x7FF<<16 //[26:16] 58 | 59 | #define RUART_STS_REG_OFF 0x20 60 | #define RUART_STS_REG_RESET_RCV (1<<3) //BIT3, 0x08, Reset Uart Receiver 61 | #define RUART_STS_REG_XFACTOR 0xF<<4 62 | 63 | #define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register 64 | #define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register 65 | 66 | #define RUART_MISC_CTL_REG_OFF 0x28 67 | #define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3 68 | #define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8 69 | 70 | #define RUART_DEBUG_REG_OFF 0x3C 71 | 72 | // RUART_LINE_CTL_REG_OFF (0x0C) 73 | #define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits 74 | #define BIT_MASK_LCR_WLS_8BITS 0x1 75 | #define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS) 76 | #define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS)) 77 | 78 | #define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit 79 | #define BIT_MASK_LCR_STB_EN 0x1 80 | #define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB) 81 | #define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB)) 82 | 83 | #define BIT_SHIFT_LCR_PARITY_EN 3 84 | #define BIT_MASK_LCR_PARITY_EN 0x1 85 | #define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN) 86 | #define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN)) 87 | 88 | #define BIT_SHIFT_LCR_PARITY_TYPE 4 89 | #define BIT_MASK_LCR_PARITY_TYPE 0x1 90 | #define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE) 91 | #define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE)) 92 | 93 | #define BIT_SHIFT_LCR_STICK_PARITY_EN 5 94 | #define BIT_MASK_LCR_STICK_PARITY_EN 0x1 95 | #define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN) 96 | #define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN)) 97 | 98 | #define BIT_SHIFT_LCR_BREAK_CTRL 6 99 | #define BIT_MASK_LCR_BREAK_CTRL 0x1 100 | #define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL) 101 | 102 | #define RUART_BAUD_RATE_2400 2400 103 | #define RUART_BAUD_RATE_4800 4800 104 | #define RUART_BAUD_RATE_9600 9600 105 | #define RUART_BAUD_RATE_19200 19200 106 | #define RUART_BAUD_RATE_38400 38400 107 | #define RUART_BAUD_RATE_57600 57600 108 | #define RUART_BAUD_RATE_115200 115200 109 | #define RUART_BAUD_RATE_921600 921600 110 | #define RUART_BAUD_RATE_1152000 1152000 111 | 112 | #define HAL_RUART_READ32(UartIndex, addr) \ 113 | HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) 114 | #define HAL_RUART_WRITE32(UartIndex, addr, value) \ 115 | HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) 116 | #define HAL_RUART_READ16(UartIndex, addr) \ 117 | HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) 118 | #define HAL_RUART_WRITE16(UartIndex, addr, value) \ 119 | HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) 120 | #define HAL_RUART_READ8(UartIndex, addr) \ 121 | HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr) 122 | #define HAL_RUART_WRITE8(UartIndex, addr, value) \ 123 | HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value) 124 | 125 | typedef struct _RUART_SPEED_SETTING_ { 126 | u32 BaudRate; 127 | u32 Ovsr; 128 | u32 Div; 129 | u32 Ovsr_adj; 130 | }RUART_SPEED_SETTING, *PRUART_SPEED_SETTING; 131 | 132 | typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ { 133 | OneByte = 0x00, 134 | FourBytes = 0x01, 135 | EightBytes = 0x10, 136 | FourteenBytes = 0x11 137 | }UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL; 138 | 139 | typedef enum _RUART0_PINMUX_SELECT_ { 140 | RUART0_MUX_TO_GPIOC = S0, 141 | RUART0_MUX_TO_GPIOE = S1, 142 | RUART0_MUX_TO_GPIOA = S2 143 | }RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT; 144 | 145 | typedef enum _RUART1_PINMUX_SELECT_ { 146 | RUART1_MUX_TO_GPIOD = S0, 147 | RUART1_MUX_TO_GPIOE = S1, 148 | RUART1_MUX_TO_GPIOB = S2 149 | }RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT; 150 | 151 | typedef enum _RUART2_PINMUX_SELECT_ { 152 | RUART2_MUX_TO_GPIOA = S0, 153 | RUART2_MUX_TO_GPIOC = S1, 154 | RUART2_MUX_TO_GPIOD = S2 155 | }RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT; 156 | 157 | typedef enum _RUART_FLOW_CONTROL_ { 158 | AUTOFLOW_DISABLE = 0, 159 | AUTOFLOW_ENABLE = 1 160 | }RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL; 161 | 162 | typedef enum _RUART_WORD_LEN_SEL_ { 163 | RUART_WLS_7BITS = 0, 164 | RUART_WLS_8BITS = 1 165 | }RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL; 166 | 167 | typedef enum _RUART_STOP_BITS_ { 168 | RUART_NO_STOP_BIT = 0, 169 | RUART_1_STOP_BIT = 1 170 | }RUART_STOP_BITS, *PRUART_STOP_BITS; 171 | 172 | typedef enum _RUART_PARITY_CONTROL_ { 173 | RUART_PARITY_DISABLE = 0, 174 | RUART_PARITY_ENABLE = 1 175 | }RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL; 176 | 177 | typedef enum _RUART_PARITY_TYPE_ { 178 | RUART_ODD_PARITY = 0, 179 | RUART_EVEN_PARITY = 1 180 | }RUART_PARITY_TYPE, *PRUART_PARITY_TYPE; 181 | 182 | typedef enum _RUART_STICK_PARITY_CONTROL_ { 183 | RUART_STICK_PARITY_DISABLE = 0, 184 | RUART_STICK_PARITY_ENABLE = 1 185 | }RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL; 186 | 187 | typedef enum _UART_INT_ID_ { 188 | ModemStatus = 0, 189 | TxFifoEmpty = 1, 190 | ReceiverDataAvailable = 2, 191 | ReceivLineStatus = 3, 192 | TimeoutIndication = 6 193 | }UART_INT_ID, *PUART_INT_ID; 194 | 195 | typedef enum _HAL_UART_State_ 196 | { 197 | HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet 198 | HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use 199 | HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration 200 | HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX 201 | HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX 202 | HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX 203 | HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout 204 | HAL_UART_STATE_ERROR = 0x40 // UART Error 205 | }HAL_UART_State, *PHAL_UART_State; 206 | 207 | typedef enum _HAL_UART_Status_ 208 | { 209 | HAL_UART_STATUS_OK = 0x00, // Transfer OK 210 | HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout 211 | HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run 212 | HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error 213 | HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error 214 | HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt 215 | HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error 216 | HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error 217 | }HAL_UART_Status, *PHAL_UART_Status; 218 | 219 | u32 220 | HalRuartGetDebugValueRtl8195a( 221 | IN VOID* Data, 222 | IN u32 DbgSel 223 | ); 224 | 225 | #if 0 226 | u32 227 | FindElementIndex( 228 | u32 Element, 229 | u32* Array 230 | ); 231 | #endif 232 | 233 | VOID 234 | RuartResetRxFifoRtl8195a( 235 | IN u8 UartIndex 236 | ); 237 | #if 0 238 | VOID 239 | RuartBusDomainEnableRtl8195a( 240 | IN u8 UartIndex 241 | ); 242 | #endif 243 | 244 | HAL_Status 245 | HalRuartResetRxFifoRtl8195a( 246 | IN VOID *Data 247 | ); 248 | 249 | HAL_Status 250 | HalRuartInitRtl8195a( 251 | IN VOID *Data 252 | ); 253 | 254 | VOID 255 | HalRuartDeInitRtl8195a( 256 | IN VOID *Data ///< RUART Adapter 257 | ); 258 | 259 | HAL_Status 260 | HalRuartPutCRtl8195a( 261 | IN VOID *Data, 262 | IN u8 TxData 263 | ); 264 | 265 | u32 266 | HalRuartSendRtl8195a( 267 | IN VOID *Data, 268 | IN u8 *pTxData, 269 | IN u32 Length, 270 | IN u32 Timeout 271 | ); 272 | 273 | HAL_Status 274 | HalRuartIntSendRtl8195a( 275 | IN VOID *Data, // PHAL_RUART_ADAPTER 276 | IN u8 *pTxData, // the Buffer to be send 277 | IN u32 Length // the length of data to be send 278 | ); 279 | 280 | HAL_Status 281 | HalRuartDmaSendRtl8195a( 282 | IN VOID *Data, // PHAL_RUART_ADAPTER 283 | IN u8 *pTxData, // the Buffer to be send 284 | IN u32 Length // the length of data to be send 285 | ); 286 | 287 | HAL_Status 288 | HalRuartStopSendRtl8195a( 289 | IN VOID *Data // PHAL_RUART_ADAPTER 290 | ); 291 | 292 | HAL_Status 293 | HalRuartGetCRtl8195a( 294 | IN VOID *Data, 295 | OUT u8 *pRxByte 296 | ); 297 | 298 | u32 299 | HalRuartRecvRtl8195a( 300 | IN VOID *Data, 301 | IN u8 *pRxData, 302 | IN u32 Length, 303 | IN u32 Timeout 304 | ); 305 | 306 | HAL_Status 307 | HalRuartIntRecvRtl8195a( 308 | IN VOID *Data, ///< RUART Adapter 309 | IN u8 *pRxData, ///< Rx buffer 310 | IN u32 Length // buffer length 311 | ); 312 | 313 | HAL_Status 314 | HalRuartDmaRecvRtl8195a( 315 | IN VOID *Data, ///< RUART Adapter 316 | IN u8 *pRxData, ///< Rx buffer 317 | IN u32 Length // buffer length 318 | ); 319 | 320 | HAL_Status 321 | HalRuartStopRecvRtl8195a( 322 | IN VOID *Data // PHAL_RUART_ADAPTER 323 | ); 324 | 325 | u8 326 | HalRuartGetIMRRtl8195a( 327 | IN VOID *Data 328 | ); 329 | 330 | _LONG_CALL_ VOID 331 | HalRuartSetIMRRtl8195a( 332 | IN VOID *Data 333 | ); 334 | 335 | VOID 336 | HalRuartDmaInitRtl8195a( 337 | IN VOID *Data 338 | ); 339 | 340 | VOID 341 | HalRuartRTSCtrlRtl8195a( 342 | IN VOID *Data, 343 | IN BOOLEAN RtsCtrl 344 | ); 345 | 346 | VOID 347 | HalRuartRegIrqRtl8195a( 348 | IN VOID *Data 349 | ); 350 | 351 | VOID 352 | HalRuartIntEnableRtl8195a( 353 | IN VOID *Data 354 | ); 355 | 356 | VOID 357 | HalRuartIntDisableRtl8195a( 358 | IN VOID *Data 359 | ); 360 | 361 | VOID 362 | HalRuartAdapterLoadDefRtl8195a( 363 | IN VOID *pAdp, 364 | IN u8 UartIdx 365 | ); 366 | 367 | VOID 368 | HalRuartTxGdmaLoadDefRtl8195a( 369 | IN VOID *pAdp, 370 | IN VOID *pCfg 371 | ); 372 | 373 | VOID 374 | HalRuartRxGdmaLoadDefRtl8195a( 375 | IN VOID *pAdp, 376 | IN VOID *pCfg 377 | ); 378 | 379 | #endif 380 | 381 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | #include "rtl8195a.h" 2 | 3 | int main(void) 4 | { 5 | int i=0; 6 | 7 | while (1) { 8 | DiagPrintf("Hello World : %d\r\n", i++); 9 | HalDelayUs(1000000); 10 | } 11 | } 12 | 13 | --------------------------------------------------------------------------------