├── src ├── test │ ├── test-files │ │ ├── ANTLRCompiler.test │ │ │ ├── empty.sv │ │ │ ├── correct.sv │ │ │ ├── several_error.sv │ │ │ ├── single_error.sv │ │ │ ├── single_error.txt │ │ │ ├── single_error.v │ │ │ └── unicode.sv │ │ ├── foo.txt │ │ ├── MacroReplace.test │ │ │ ├── no_macros.sv │ │ │ ├── no_macros_expected.sv │ │ │ ├── single_macro_no_uses_expected.sv │ │ │ ├── single_macro_no_uses.sv │ │ │ ├── redefined_macro_expected.sv │ │ │ ├── single_macro_multiple_uses_expected.sv │ │ │ ├── multiline_macro_expected.sv │ │ │ ├── single_macro_multiple_uses.sv │ │ │ ├── multiple_macros_multiple_uses_expected.sv │ │ │ ├── redefined_macro.sv │ │ │ ├── multiple_macros_interspersed_expected.sv │ │ │ ├── multiline_macro.sv │ │ │ ├── multiple_macros_multiple_uses.sv │ │ │ └── multiple_macros_interspersed.sv │ │ ├── VCSCompiler.test │ │ │ ├── baz.sv │ │ │ ├── foo.sv │ │ │ └── foo.stdout.txt │ │ ├── VerilatorCompiler.test │ │ │ ├── baz.sv │ │ │ ├── qux.sv │ │ │ ├── bar.sv │ │ │ ├── foo.sv │ │ │ ├── bar.stderr.txt │ │ │ ├── foo.stderr.txt │ │ │ └── qux.stderr.txt │ │ ├── VeribleCompiler.test │ │ │ ├── baz.sv │ │ │ ├── foo_error.stdout.txt │ │ │ ├── foo.sv │ │ │ ├── foo_error.sv │ │ │ └── foo.stdout.txt │ │ ├── illegal_symbols.sv │ │ └── design.sv │ ├── SyntaxErrorListener.test.ts │ ├── runTest.ts │ ├── index.ts │ ├── utils.client.test.ts │ ├── utils.common.test.ts │ ├── ReferenceProvider.test.ts │ └── index-coverage.ts ├── compiling │ ├── ANTLR │ │ ├── grammar │ │ │ ├── Strings.g4 │ │ │ ├── SystemVerilog.g4 │ │ │ ├── SubroutineCallStatements.g4 │ │ │ ├── Attributes.g4 │ │ │ ├── PrimitiveTerminals.g4 │ │ │ ├── BlockItemDeclarations.g4 │ │ │ ├── PrimitiveStrengths.g4 │ │ │ ├── UDPInstantiation.g4 │ │ │ ├── ConditionalStatements.g4 │ │ │ ├── PrimitiveGateAndSwitchTypes.g4 │ │ │ ├── ParallelAndSequentialBlocks.g4 │ │ │ ├── SpecifyBlockTerminals.g4 │ │ │ ├── DeclarationRanges.g4 │ │ │ ├── SpecifyBlockDeclaration.g4 │ │ │ ├── ContinuousAssignmentAndNetAliasStatements.g4 │ │ │ ├── InterfaceItems.g4 │ │ │ ├── Operators.g4 │ │ │ ├── ProgramItems.g4 │ │ │ ├── ExpressionLeftsideValues.g4 │ │ │ ├── UDPPorts.g4 │ │ │ ├── UDPDeclaration.g4 │ │ │ ├── SpecifyPathDeclarations.g4 │ │ │ ├── LetDeclarations.g4 │ │ │ ├── InterfaceDeclarations.g4 │ │ │ ├── PackageItems.g4 │ │ │ ├── LoopingStatements.g4 │ │ │ ├── UDPBody.g4 │ │ │ ├── TaskDeclarations.g4 │ │ │ ├── Concatenations.g4 │ │ │ ├── CheckerItems.g4 │ │ │ ├── ConfigurationSourceText.g4 │ │ │ ├── ProceduralBlocksAndAssignments.g4 │ │ │ ├── Randsequence.g4 │ │ │ ├── GeneratedInstantiation.g4 │ │ │ ├── ClockingBlock.g4 │ │ │ ├── DeclarationAssignments.g4 │ │ │ ├── TimingControlStatements.g4 │ │ │ ├── FunctionDeclarations.g4 │ │ │ ├── Constraints.g4 │ │ │ ├── DeclarationLists.g4 │ │ │ ├── AssertionStatements.g4 │ │ │ ├── Statements.g4 │ │ │ ├── ClassItems.g4 │ │ │ ├── Numbers.g4 │ │ │ ├── ModuleParametersAndPorts.g4 │ │ │ ├── PrimitiveInstantiationAndInstances.g4 │ │ │ ├── Instantiation.g4 │ │ │ ├── LexRules.g4 │ │ │ ├── ModuleItems.g4 │ │ │ ├── CaseStatements.g4 │ │ │ ├── DeclarationTypes.g4 │ │ │ ├── Primaries.g4 │ │ │ ├── SpecifyPathDelays.g4 │ │ │ ├── Expressions.g4 │ │ │ ├── DeclarationDataTypes.g4 │ │ │ └── SubroutineCalls.g4 │ │ └── SyntaxErrorListener.ts │ ├── DiagnosticData.ts │ ├── SystemVerilogCompiler.ts │ └── VCSCompiler.ts ├── utils │ ├── client.ts │ ├── common.ts │ └── server.ts ├── providers │ └── HoverProvider.ts ├── wip │ └── TreeDataProvider.ts └── symbol.ts ├── .vscode ├── settings.json ├── launch.json └── tasks.json ├── resources ├── icon.png ├── goToDef_demo.gif ├── find_references.gif ├── moduleInit_demo.gif ├── SymbolKind_icons.png ├── sys_verilog_logo.png ├── module_index_status.png ├── syntax_example_adder.png ├── CompletionItemKind_icons.png ├── VSCode_SystemVerilog_Icons.fig ├── client_server_configuration.png ├── va.svg ├── vams.svg ├── sdc_dark.svg ├── sdc_light.svg ├── sv_dark.svg ├── sv_light.svg ├── v_dark.svg ├── v_light.svg ├── f_dark.svg ├── svh_dark.svg ├── svh_light.svg ├── vh_dark.svg ├── vh_light.svg └── f_light.svg ├── .eslintignore ├── configs ├── vhdl.configuration.json ├── verilogFileList.json ├── sdc.json └── systemVerilog.json ├── verilog-examples ├── fiellist.f ├── class_extern.svh ├── primitive_table.sv ├── my_invl.vh ├── .vscode │ ├── settings.json │ └── tasks.json ├── interface.sv ├── package.sv ├── excluded_inst.sv ├── allman_example.sv ├── allman_example.svh ├── transaction.sv ├── comment_error.sv ├── design.v ├── design.vh ├── class_example.sv ├── inheritance_example.sv ├── random_test.sv ├── generator.sv ├── parameter_test.sv ├── environment.sv ├── directed_test.sv ├── instantiation_example.sv ├── cover_example.sv ├── testbench.sv ├── error_test.sv ├── segdetect.v ├── ekv.va ├── driver.sv ├── varistor.vams └── jtag.xdc ├── .gitignore ├── .prettierignore ├── .vscodeignore ├── .github └── workflows │ ├── deploy.yaml │ └── test.yaml ├── tsconfig.json ├── .prettierrc ├── LICENSE ├── schemas └── tasks.schema.json ├── .eslintrc.json └── syntaxes ├── verilog-filelist.json └── codeblock.json /src/test/test-files/ANTLRCompiler.test/empty.sv: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/test/test-files/foo.txt: -------------------------------------------------------------------------------- 1 | a file for WorkspaceSymbolProvider.test.ts -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "typescript.tsdk": "./node_modules/typescript/lib" 3 | } 4 | -------------------------------------------------------------------------------- /resources/icon.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/icon.png -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/no_macros.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | endmodule; 4 | -------------------------------------------------------------------------------- /resources/goToDef_demo.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/goToDef_demo.gif -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/no_macros_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | endmodule; 4 | -------------------------------------------------------------------------------- /resources/find_references.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/find_references.gif -------------------------------------------------------------------------------- /resources/moduleInit_demo.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/moduleInit_demo.gif -------------------------------------------------------------------------------- /resources/SymbolKind_icons.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/SymbolKind_icons.png -------------------------------------------------------------------------------- /resources/sys_verilog_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/sys_verilog_logo.png -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Strings.g4: -------------------------------------------------------------------------------- 1 | grammar Strings; 2 | import Attributes; 3 | 4 | string_literal : STRING_LITERAL ; 5 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/single_macro_no_uses_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | endmodule; 4 | -------------------------------------------------------------------------------- /resources/module_index_status.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/module_index_status.png -------------------------------------------------------------------------------- /resources/syntax_example_adder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/syntax_example_adder.png -------------------------------------------------------------------------------- /resources/CompletionItemKind_icons.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/CompletionItemKind_icons.png -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/single_macro_no_uses.sv: -------------------------------------------------------------------------------- 1 | `define MYMACRO 0 2 | module mymodule(); 3 | reg a = 0; 4 | endmodule; 5 | -------------------------------------------------------------------------------- /resources/VSCode_SystemVerilog_Icons.fig: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/VSCode_SystemVerilog_Icons.fig -------------------------------------------------------------------------------- /resources/client_server_configuration.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/eirikpre/VSCode-SystemVerilog/HEAD/resources/client_server_configuration.png -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/redefined_macro_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | reg b = 1; 4 | endmodule; 5 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/single_macro_multiple_uses_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | reg b = 0; 4 | endmodule; 5 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SystemVerilog.g4: -------------------------------------------------------------------------------- 1 | grammar SystemVerilog; 2 | import SystemVerilogSourceText; 3 | 4 | system_verilog_text : source_text EOF ; 5 | -------------------------------------------------------------------------------- /.eslintignore: -------------------------------------------------------------------------------- 1 | .vscode/ 2 | .vscode-test/ 3 | build/ 4 | coverage/ 5 | dist/ 6 | node_modules/ 7 | out/ 8 | src/compiling/ANTLR/grammar 9 | src/wip/ 10 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/multiline_macro_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | reg b = 0; 4 | reg c = 1; 5 | reg d = 1; 6 | endmodule; 7 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/single_macro_multiple_uses.sv: -------------------------------------------------------------------------------- 1 | `define MYMACRO 0 2 | module mymodule(); 3 | reg a = `MYMACRO; 4 | reg b = `MYMACRO; 5 | endmodule; 6 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/multiple_macros_multiple_uses_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | reg b = 0; 4 | reg c = 1; 5 | reg d = 1; 6 | endmodule; 7 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/redefined_macro.sv: -------------------------------------------------------------------------------- 1 | `define MYMACRO 0 2 | module mymodule(); 3 | reg a = `MYMACRO; 4 | `define MYMACRO 1 5 | reg b = `MYMACRO; 6 | endmodule; 7 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/multiple_macros_interspersed_expected.sv: -------------------------------------------------------------------------------- 1 | module mymodule(); 2 | reg a = 0; 3 | reg b = 0; 4 | reg c = 1; 5 | reg d = 1; 6 | endmodule; 7 | -------------------------------------------------------------------------------- /configs/vhdl.configuration.json: -------------------------------------------------------------------------------- 1 | { 2 | "comments": { 3 | "lineComment": "--", 4 | "blockComment": [] 5 | }, 6 | "brackets": [ 7 | ["{", "}"], 8 | ["[", "]"], 9 | ["(", ")"] 10 | ] 11 | } -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/multiline_macro.sv: -------------------------------------------------------------------------------- 1 | `define REG_A_REG_B_DEF reg a = 0;\ 2 | reg b = 0; 3 | module mymodule(); 4 | `REG_A_REG_B_DEF 5 | reg c = 1; 6 | reg d = 1; 7 | endmodule; 8 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SubroutineCallStatements.g4: -------------------------------------------------------------------------------- 1 | grammar SubroutineCallStatements; 2 | import AssertionStatements; 3 | 4 | subroutine_call_statement : subroutine_call ';' | 'void' APOSTROPHE '(' function_subroutine_call ')' ';' ; 5 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Attributes.g4: -------------------------------------------------------------------------------- 1 | grammar Attributes; 2 | import Identifiers; 3 | 4 | attribute_instance : '(*' attr_spec ( ',' attr_spec )* '*)' ; 5 | attr_spec : attr_name ( '=' constant_expression )? ; 6 | attr_name : identifier ; 7 | -------------------------------------------------------------------------------- /src/test/SyntaxErrorListener.test.ts: -------------------------------------------------------------------------------- 1 | suite('SyntaxErrorListener Tests', () => { 2 | test('test #1: Error list for no syntax errors', async () => {}); 3 | 4 | test('test #2: Error list for several syntax errors', async () => {}); 5 | }); 6 | -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/multiple_macros_multiple_uses.sv: -------------------------------------------------------------------------------- 1 | `define MYMACRO0 0 2 | `define MYMACRO1 1 3 | module mymodule(); 4 | reg a = `MYMACRO0; 5 | reg b = `MYMACRO0; 6 | reg c = `MYMACRO1; 7 | reg d = `MYMACRO1; 8 | endmodule; 9 | -------------------------------------------------------------------------------- /verilog-examples/fiellist.f: -------------------------------------------------------------------------------- 1 | // A great comment 2 | -f ./${dirname}/my_files.f 3 | -F $(MY_PATH)/my_relative_files.f 4 | -v a_verilog_file.v 5 | -define SYNTHESIS 6 | # another comment 7 | -incdir ./rtl 8 | +incdir+ ./include 9 | +define+NO_PORTS 10 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /.nyc_output/ 2 | /.vscode-test/ 3 | /coverage/ 4 | /dist/ 5 | /node_modules/ 6 | /out/ 7 | /packages/ 8 | /results.xml 9 | /src/compiling/ANTLR/grammar/build/ 10 | /syntaxes/systemverilog.tmLanguage.json 11 | **/.antlr 12 | *.vsix 13 | .DS_Store 14 | -------------------------------------------------------------------------------- /verilog-examples/class_extern.svh: -------------------------------------------------------------------------------- 1 | `ifndef CLASS_EXTERN_SVI 2 | `define CLASS_EXTERN_SVI 3 | 4 | class class_extern; 5 | int address; 6 | bit [63:0] data; 7 | shortint crc; 8 | 9 | extern function new(); 10 | extern task print(); 11 | endclass 12 | 13 | 14 | `endif -------------------------------------------------------------------------------- /verilog-examples/primitive_table.sv: -------------------------------------------------------------------------------- 1 | primitive MyUDP (x, a, b, c); 2 | output x; 3 | input a, b, c; 4 | table 5 | // a b c : x 6 | 0 n P : 0; 7 | 1 ? (10) : 1; 8 | * 0 x : -; 9 | ? 1 1 : 1; 10 | endtable 11 | endprimitive -------------------------------------------------------------------------------- /src/test/test-files/MacroReplace.test/multiple_macros_interspersed.sv: -------------------------------------------------------------------------------- 1 | `define MYMACRO0_0 0 2 | module mymodule(); 3 | reg a = `MYMACRO0_0; 4 | `define MYMACRO0_1 0 5 | reg b = `MYMACRO0_1; 6 | `define MYMACRO1 1 7 | reg c = `MYMACRO1; 8 | reg d = `MYMACRO1; 9 | endmodule; 10 | -------------------------------------------------------------------------------- /configs/verilogFileList.json: -------------------------------------------------------------------------------- 1 | { 2 | "comments": { 3 | "lineComment": ["//", "#"] 4 | }, 5 | "brackets": [ 6 | ["{", "}"], 7 | ["(", ")"] 8 | ], 9 | "autoClosingPairs": [ 10 | ["{", "}"], 11 | ["(", ")"] 12 | ], 13 | "surroundingPairs": [ 14 | ["{", "}"], 15 | ["(", ")"] 16 | ] 17 | } -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/PrimitiveTerminals.g4: -------------------------------------------------------------------------------- 1 | grammar PrimitiveTerminals; 2 | import PrimitiveGateAndSwitchTypes; 3 | 4 | enable_terminal : expression ; 5 | inout_terminal : net_lvalue ; 6 | input_terminal : expression ; 7 | ncontrol_terminal : expression ; 8 | output_terminal : net_lvalue ; 9 | pcontrol_terminal : expression ; 10 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/BlockItemDeclarations.g4: -------------------------------------------------------------------------------- 1 | grammar BlockItemDeclarations; 2 | import InterfaceDeclarations; 3 | 4 | block_item_declaration : ( attribute_instance )* data_declaration 5 | | ( attribute_instance )* local_parameter_declaration ';' 6 | | ( attribute_instance )* parameter_declaration ';' 7 | | ( attribute_instance )* let_declaration ; 8 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/PrimitiveStrengths.g4: -------------------------------------------------------------------------------- 1 | grammar PrimitiveStrengths; 2 | import PrimitiveTerminals; 3 | 4 | pulldown_strength : '(' strength0 ',' strength1 ')' 5 | | '(' strength1 ',' strength0 ')' 6 | | '(' strength0 ')' ; 7 | pullup_strength : '(' strength0 ',' strength1 ')' 8 | | '(' strength1 ',' strength0 ')' 9 | | '(' strength1 ')' ; 10 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/UDPInstantiation.g4: -------------------------------------------------------------------------------- 1 | grammar UDPInstantiation; 2 | import ContinuousAssignmentAndNetAliasStatements; 3 | 4 | udp_instantiation : udp_identifier ( drive_strength )? ( delay2 )? udp_instance ( ',' udp_instance )* 5 | ';' ; 6 | udp_instance : ( name_of_instance )? '(' output_terminal ',' input_terminal ( ',' input_terminal )* 7 | ')' ; 8 | -------------------------------------------------------------------------------- /verilog-examples/my_invl.vh: -------------------------------------------------------------------------------- 1 | // my_incl.vh 2 | // If we have not included file before, 3 | // this symbol _my_incl_vh_ is not defined. 4 | `ifndef _my_incl_vh_ 5 | `define _my_incl_vh_ 6 | // Start of include contents 7 | `define N 4 8 | // Use parentheses to mitigate any undesired operator precedence issues 9 | `define M (`N << 2) 10 | `endif //_my_incl_vh_ 11 | -------------------------------------------------------------------------------- /verilog-examples/.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | // For tests to work correctly 3 | "systemverilog.forceFastIndexing": false, 4 | "systemverilog.disableIndexing": true, 5 | "systemverilog.documentSymbolsPrecision": "full", 6 | "editor.tabSize": 2, 7 | "files.eol": "\n", 8 | "systemverilog.formatCommand": "C:\\Program Files\\Git\\bin\\git.exe" 9 | } 10 | -------------------------------------------------------------------------------- /.prettierignore: -------------------------------------------------------------------------------- 1 | /.nyc_output/ 2 | /.vscode-test/ 3 | /coverage/ 4 | /out/ 5 | /resources/ 6 | /dist/ 7 | /src/compiling/ANTLR/grammar/ 8 | /src/test/test-files/ 9 | /verilog-examples/ 10 | /snippets/systemverilog.json 11 | /syntaxes/systemverilog.tmLanguage*.json 12 | /.eslintignore 13 | /.gitignore 14 | /.prettierignore 15 | /.vscodeignore 16 | /LICENSE 17 | /results.xml 18 | *.vsix 19 | -------------------------------------------------------------------------------- /src/test/test-files/VCSCompiler.test/baz.sv: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in; 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/ANTLRCompiler.test/correct.sv: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in; 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/ANTLRCompiler.test/several_error.sv: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in; 13 | B_out <= B_in 14 | C_out <= C_in; 15 | end 16 | endmodul -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/baz.sv: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in; 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/ANTLRCompiler.test/single_error.sv: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/ANTLRCompiler.test/single_error.txt: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/ANTLRCompiler.test/single_error.v: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/ANTLRCompiler.test/unicode.sv: -------------------------------------------------------------------------------- 1 | module baz ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_😊n, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg 💣_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in; 13 | B_ou🥌 <= B_in; 14 | C_out <= C_in; 15 | end 16 | endmodule -------------------------------------------------------------------------------- /verilog-examples/interface.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------------------------------- 4 | interface intf(input logic clk,reset); 5 | 6 | //declaring the signals 7 | logic valid; 8 | logic [3:0] a; 9 | logic [3:0] b; 10 | logic [6:0] c; 11 | 12 | endinterface -------------------------------------------------------------------------------- /verilog-examples/package.sv: -------------------------------------------------------------------------------- 1 | package pa_Package; 2 | 3 | parameter PARAMETER = 1; 4 | localparam PARAMETER2 = 2; 5 | 6 | typedef struct packed 7 | { 8 | logic foo; 9 | logic bar; 10 | } my_dumb_struct; 11 | 12 | 13 | struct packed 14 | { 15 | logic foo; 16 | logic bar; 17 | } my_struct; 18 | 19 | 20 | 21 | my_dumb_struct a_dumb_struct; 22 | 23 | typedef int [7:0] int_8; 24 | 25 | endpackage -------------------------------------------------------------------------------- /src/test/test-files/VeribleCompiler.test/baz.sv: -------------------------------------------------------------------------------- 1 | `include "outermodule.sv" 2 | 3 | module baz ( 4 | clk 5 | ); 6 | input logic clk; 7 | /* verilator lint_off UNDRIVEN */ 8 | wire A_in, B_in, C_in; 9 | /* verilator lint_off UNUSED */ 10 | reg A_out, B_out, C_out; 11 | 12 | always @( posedge clk ) 13 | begin 14 | A_out <= A_in; 15 | B_out <= B_in; 16 | C_out <= C_in; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /configs/sdc.json: -------------------------------------------------------------------------------- 1 | { 2 | "comments": { 3 | "lineComment": "#" 4 | }, 5 | "brackets": [ 6 | ["{", "}"], 7 | ["[", "]"], 8 | ["(", ")"] 9 | ], 10 | "autoClosingPairs": [ 11 | ["{", "}"], 12 | ["[", "]"], 13 | ["(", ")"], 14 | ["\"", "\""], 15 | ["'", "'"] 16 | ], 17 | "surroundingPairs": [ 18 | ["{", "}"], 19 | ["[", "]"], 20 | ["(", ")"], 21 | ["\"", "\""], 22 | ["'", "'"] 23 | ] 24 | } -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/qux.sv: -------------------------------------------------------------------------------- 1 | module qux ( 2 | clk 3 | ); 4 | input logic clk; 5 | /* verilator lint_off UNDRIVEN */ 6 | wire A_in, B_in, C_in; 7 | /* verilator lint_off UNUSED */ 8 | reg A_out, B_out, C_out; 9 | 10 | always @( posedge clk ) 11 | begin 12 | A_out <= A_in; 13 | B_out <= B_in; 14 | C_out <= C_in; 15 | end 16 | 17 | externalModule u_externalModule; 18 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/VeribleCompiler.test/foo_error.stdout.txt: -------------------------------------------------------------------------------- 1 | foo_error.sv:6:5: syntax error, rejected "input" (syntax-error). 2 | foo_error.sv:13:3: syntax error, rejected "always" (syntax-error). 3 | foo_error.sv:16:13: syntax error, rejected "<=" (syntax-error). 4 | foo_error.sv:17:13: syntax error, rejected "<=" (syntax-error). 5 | foo_error.sv:18:3: syntax error, rejected "end" (syntax-error). 6 | foo_error.sv:21:1: syntax error, rejected "endmodule" (syntax-error). 7 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ConditionalStatements.g4: -------------------------------------------------------------------------------- 1 | grammar ConditionalStatements; 2 | import CaseStatements; 3 | 4 | conditional_statement : ( unique_priority )? 'if' '(' cond_predicate ')' statement_or_null 5 | ( 'else' 'if' '(' cond_predicate ')' statement_or_null )* ( 'else' statement_or_null )? ; 6 | unique_priority : 'unique' | 'unique0' | 'priority' ; 7 | cond_predicate : ( expression | expression 'matches' pattern ) ( '&&&' ( expression | expression 'matches' pattern ) )* ; 8 | -------------------------------------------------------------------------------- /src/test/test-files/VCSCompiler.test/foo.sv: -------------------------------------------------------------------------------- 1 | `include "outermodule.sv" 2 | 3 | module qux ( 4 | clk 5 | ); 6 | input logic clk; 7 | /* verilator lint_off UNDRIVEN */ 8 | wire A_in, B_in, C_in; 9 | /* verilator lint_off UNUSED */ 10 | reg A_out, B_out, C_out; 11 | 12 | 13 | always @( posedge clk ) 14 | begin 15 | A_out <= A_in; 16 | B_out <= B_in; 17 | C_out <= C_in; 18 | end 19 | 20 | outermodule u_outermodule(4); 21 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/VeribleCompiler.test/foo.sv: -------------------------------------------------------------------------------- 1 | `include "outermodule.sv" 2 | 3 | module qux ( 4 | clk 5 | ); 6 | input logic clk; 7 | /* verilator lint_off UNDRIVEN */ 8 | wire A_in, B_in, C_in; 9 | /* verilator lint_off UNUSED */ 10 | reg A_out, B_out, C_out; 11 | 12 | 13 | always @( posedge clk ) 14 | begin 15 | A_out <= A_in; 16 | B_out <= B_in; 17 | C_out <= C_in; 18 | end 19 | 20 | outermodule u_outermodule(4); 21 | endmodule -------------------------------------------------------------------------------- /src/test/test-files/illegal_symbols.sv: -------------------------------------------------------------------------------- 1 | // This module contains wire name definitions that begin with illegal symbols. 2 | // The parser should allow these names 3 | module illegal_adder( 4 | input clk, 5 | input reset, 6 | // Some comment here 7 | input [3:0] a, 8 | input [3:0] b, 9 | input valid, 10 | output [6:0] c 11 | ); 12 | 13 | wire begin_state; 14 | wire return_true; 15 | 16 | assign return_true = begin_state | a; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /src/test/test-files/VeribleCompiler.test/foo_error.sv: -------------------------------------------------------------------------------- 1 | `include "outermodule.sv" 2 | 3 | module qux ( 4 | clk 5 | ) 6 | input logic clk; 7 | /* verilator lint_off UNDRIVEN */ 8 | wire A_in, B_in, C_in; 9 | /* verilator lint_off UNUSED */ 10 | reg A_out, B_out, C_out; 11 | 12 | 13 | always @( posedge clk ) 14 | begin 15 | A_out <= A_in; 16 | B_out <= B_in; 17 | C_out <= C_in; 18 | end 19 | 20 | outermodule u_outermodule(4); 21 | endmodule -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/PrimitiveGateAndSwitchTypes.g4: -------------------------------------------------------------------------------- 1 | grammar PrimitiveGateAndSwitchTypes; 2 | import Instantiation; 3 | 4 | cmos_switchtype : 'cmos' | 'rcmos' ; 5 | enable_gatetype : 'bufif0' | 'bufif1' | 'notif0' | 'notif1' ; 6 | mos_switchtype : 'nmos' | 'pmos' | 'rnmos' | 'rpmos' ; 7 | n_input_gatetype : 'and' | 'nand' | 'or' | 'nor' | 'xor' | 'xnor' ; 8 | n_output_gatetype : 'buf' | 'not' ; 9 | pass_en_switchtype : 'tranif0' | 'tranif1' | 'rtranif1' | 'rtranif0' ; 10 | pass_switchtype : 'tran' | 'rtran' ; 11 | -------------------------------------------------------------------------------- /.vscodeignore: -------------------------------------------------------------------------------- 1 | .git/ 2 | .nyc_output/ 3 | .vscode/ 4 | .vscode-test/ 5 | build/ 6 | coverage/ 7 | # dist/ 8 | dist/**/*.LICENSE.txt 9 | dist/**/*.map 10 | node_modules/ 11 | out/ 12 | # out/test/ 13 | # out/wip/ 14 | resources/* 15 | !resources/icon.png 16 | !resources/*.svg 17 | src/ 18 | syntaxes/systemverilog.tmLanguage.yaml 19 | verilog-examples/ 20 | .gitignore 21 | .eslintignore 22 | .eslintrc 23 | .prettierignore 24 | .prettierrc 25 | .vscodeignore 26 | package-lock.json 27 | tsconfig.json 28 | results.xml 29 | *.vsix 30 | -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/bar.sv: -------------------------------------------------------------------------------- 1 | module bar ( 2 | clk, 3 | reset, 4 | //keep 5 | a, 6 | //also this comment 1 7 | b, 8 | // also this comment 2 9 | valid, 10 | c 11 | ); 12 | 13 | input clk; 14 | input reset; 15 | input [3:0] a; 16 | // keep this single comment 17 | input [3:0] b; 18 | /* multiline comment should 19 | be kept*/ 20 | input valid; 21 | output [6:0] c; 22 | 23 | reg [6:0] tmp_c; 24 | assign c = tmp_c; 25 | 26 | 27 | endmodule -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ParallelAndSequentialBlocks.g4: -------------------------------------------------------------------------------- 1 | grammar ParallelAndSequentialBlocks; 2 | import Statements; 3 | 4 | action_block : statement_or_null | ( statement )? 'else' statement_or_null ; 5 | seq_block : 'begin' ( ':' block_identifier )? ( block_item_declaration )* ( statement_or_null )* 'end' 6 | ( ':' block_identifier )? ; 7 | par_block : 'fork' ( ':' block_identifier )? ( block_item_declaration )* ( statement_or_null )* 8 | join_keyword ( ':' block_identifier )? ; 9 | join_keyword : 'join' | 'join_any' | 'join_none' ; 10 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SpecifyBlockTerminals.g4: -------------------------------------------------------------------------------- 1 | grammar SpecifyBlockTerminals; 2 | import SpecifyPathDelays; 3 | 4 | specify_input_terminal_descriptor : input_identifier ( '[' constant_range_expression ']' )? ; 5 | specify_output_terminal_descriptor : output_identifier ( '[' constant_range_expression ']' )? ; input_identifier : input_port_identifier 6 | | inout_port_identifier 7 | | interface_identifier '.' port_identifier ; 8 | output_identifier : output_port_identifier 9 | | inout_port_identifier 10 | | interface_identifier '.' port_identifier ; 11 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/DeclarationRanges.g4: -------------------------------------------------------------------------------- 1 | grammar DeclarationRanges; 2 | import FunctionDeclarations; 3 | 4 | unpacked_dimension : '[' constant_range ']' 5 | | '[' constant_expression ']' ; 6 | packed_dimension : '[' constant_range ']' 7 | | unsized_dimension ; 8 | associative_dimension : '[' data_type ']' 9 | | '[' '*' ']' ; 10 | variable_dimension : unsized_dimension 11 | | unpacked_dimension 12 | | associative_dimension 13 | | queue_dimension ; 14 | queue_dimension : '[' '$' ( ':' constant_expression )? ']' ; 15 | unsized_dimension : '[' ']' ; 16 | -------------------------------------------------------------------------------- /.github/workflows/deploy.yaml: -------------------------------------------------------------------------------- 1 | on: 2 | push: 3 | tags: 4 | - '*' 5 | 6 | name: Deploy Extension 7 | jobs: 8 | deploy: 9 | runs-on: ubuntu-latest 10 | steps: 11 | - uses: actions/checkout@v2 12 | - uses: actions/setup-node@v1 13 | with: 14 | node-version: 16 15 | - run: npm ci 16 | - name: Publish to Visual Studio Marketplace 17 | uses: HaaLeo/publish-vscode-extension@v1 18 | with: 19 | pat: ${{ secrets.VS_MARKETPLACE_TOKEN }} 20 | registryUrl: https://marketplace.visualstudio.com 21 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SpecifyBlockDeclaration.g4: -------------------------------------------------------------------------------- 1 | grammar SpecifyBlockDeclaration; 2 | import SpecifyPathDeclarations; 3 | 4 | specify_block : 'specify' ( specify_item )* 'endspecify' ; 5 | specify_item : specparam_declaration 6 | | pulsestyle_declaration 7 | | showcancelled_declaration 8 | | path_declaration 9 | | system_timing_check ; 10 | pulsestyle_declaration : 'pulsestyle_onevent' list_of_path_outputs ';' 11 | | 'pulsestyle_ondetect' list_of_path_outputs ';' ; 12 | showcancelled_declaration : 'showcancelled' list_of_path_outputs ';' 13 | | 'noshowcancelled' list_of_path_outputs ';' ; 14 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ContinuousAssignmentAndNetAliasStatements.g4: -------------------------------------------------------------------------------- 1 | grammar ContinuousAssignmentAndNetAliasStatements; 2 | import ProceduralBlocksAndAssignments; 3 | 4 | continuous_assign : 'assign' ( drive_strength )? ( delay3 )? list_of_net_assignments ';' 5 | | 'assign' ( delay_control )? list_of_variable_assignments ';' ; 6 | list_of_net_assignments : net_assignment ( ',' net_assignment )* ; 7 | list_of_variable_assignments : variable_assignment ( ',' variable_assignment )* ; 8 | net_alias : 'alias' net_lvalue '=' net_lvalue ( '=' net_lvalue )* ';' ; 9 | net_assignment : net_lvalue '=' expression ; 10 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/InterfaceItems.g4: -------------------------------------------------------------------------------- 1 | grammar InterfaceItems; 2 | import ProgramItems; 3 | 4 | interface_or_generate_item : ( attribute_instance )* module_common_item 5 | | ( attribute_instance )* extern_tf_declaration ; 6 | extern_tf_declaration : 'extern' method_prototype ';' 7 | | 'extern' 'forkjoin' task_prototype ';' ; 8 | interface_item : port_declaration ';' 9 | | non_port_interface_item ; 10 | non_port_interface_item : generate_region 11 | | interface_or_generate_item 12 | | program_declaration 13 | | modport_declaration 14 | | interface_declaration 15 | | timeunits_declaration ; 16 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Operators.g4: -------------------------------------------------------------------------------- 1 | grammar Operators; 2 | import Numbers; 3 | 4 | unary_operator : '+' | '-' | '!' | '~' | '&' | '~&' | '|' | '~|' | '^' | '~^' | '^~' ; 5 | binary_operator : '+' | '-' | '*' | '/' | '%' | '==' | '!=' | '===' | '!==' | '==?' | '!=?' | '&&' | '||' 6 | | '**' | '<' | '<=' | '>' | '>=' | '&' | '|' | '^' | '^~' | '~^' | '>>' | '<<' | '>>>' | '<<<' | '->' 7 | | '<->' ; 8 | inc_or_dec_operator : '++' | '--' ; 9 | unary_module_path_operator : '!' | '~' | '&' | '~&' | '|' | '~|' | '^' | '~^' | '^~' ; 10 | binary_module_path_operator : '==' | '!=' | '&&' | '||' | '&' | '|' | '^' | '^~' | '~^' ; 11 | -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/foo.sv: -------------------------------------------------------------------------------- 1 | `include "environment.sv" 2 | 3 | class my_trans extends transaction; 4 | 5 | bit [1:0] count, test; 6 | 7 | function void pre_randomize(); 8 | a.rand_mode(0); 9 | b.rand_mode(0); 10 | 11 | a = 10; 12 | b = 12; 13 | endfunction 14 | 15 | endclass 16 | 17 | module foo ( 18 | clk, 19 | c 20 | ); 21 | 22 | input clk; 23 | output [6:0] c; 24 | 25 | reg [6:0] tmp_c; 26 | assign c = tmp_c; 27 | 28 | if(valid) tmp_c <= a + b; 29 | 30 | apper u_apper ( 31 | .a (1) 32 | ); 33 | 34 | endmodule -------------------------------------------------------------------------------- /tsconfig.json: -------------------------------------------------------------------------------- 1 | { 2 | "compilerOptions": { 3 | "forceConsistentCasingInFileNames": true, 4 | // "isolatedModules": true, 5 | "lib": ["es2020"], 6 | "module": "commonjs", 7 | "moduleResolution": "node", 8 | "noEmit": false, 9 | // "noFallthroughCasesInSwitch": true, 10 | // "noUnusedLocals": true, 11 | // "noUnusedParameters": true, 12 | "outDir": "out", 13 | "rootDir": "src", 14 | "skipLibCheck": true, 15 | "sourceMap": true, 16 | // "strict": true, 17 | "target": "es2020" 18 | }, 19 | "exclude": ["node_modules", ".vscode-test", "src/wip"] 20 | } 21 | -------------------------------------------------------------------------------- /verilog-examples/excluded_inst.sv: -------------------------------------------------------------------------------- 1 | // Folding example that should work 2 | `ifdef A 3 | A_TEST_ONE; 4 | A_TEST_TWO; 5 | 6 | `ifdef B 7 | B_TEST_ONE; 8 | B_TEST_TWO; 9 | `endif 10 | 11 | `ifdef C 12 | C_TEST_ONE; 13 | C_TEST_TWO; 14 | `endif 15 | 16 | A_TEST_ONE; 17 | A_TEST_TWO; 18 | `endif 19 | 20 | // Folding example that does not work 21 | `ifdef A 22 | A_TEST_ONE; 23 | A_TEST_TWO; 24 | 25 | `elsif B 26 | B_TEST_ONE; 27 | B_TEST_TWO; 28 | 29 | `else C 30 | C_TEST_ONE; 31 | C_TEST_TWO; 32 | 33 | `endif 34 | 35 | 36 | // Excluded from indexing example 37 | module excluded #( 38 | parameter A 39 | )( 40 | input a 41 | ); 42 | 43 | endmodule -------------------------------------------------------------------------------- /verilog-examples/allman_example.sv: -------------------------------------------------------------------------------- 1 | 2 | // Simple memory model 3 | module ram16( 4 | input wire port 5 | ); 6 | // This module colors correctly 7 | ram8 subH( 8 | .write (), 9 | .addr (), 10 | .wdata (), 11 | .rdata () 12 | ); 13 | 14 | 15 | // This module does not color correctly (allman style) 16 | ram8 subL 17 | ( 18 | .clk (), 19 | .write (), 20 | .addr (), 21 | .wdata (), 22 | .rdata () 23 | ); 24 | 25 | endmodule 26 | 27 | module ram8 ( 28 | input wire clk, 29 | input wire write, 30 | input wire addr, 31 | output wire wdata, 32 | ); 33 | // something here 34 | reg [1:0] rdata [1:0]; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /verilog-examples/allman_example.svh: -------------------------------------------------------------------------------- 1 | 2 | // Simple memory model 3 | module ram16( 4 | input wire port 5 | ); 6 | // This module colors correctly 7 | ram8 subH( 8 | .write (), 9 | .addr (), 10 | .wdata (), 11 | .rdata () 12 | ); 13 | 14 | 15 | // This module does not color correctly (allman style) 16 | ram8 subL 17 | ( 18 | .clk (), 19 | .write (), 20 | .addr (), 21 | .wdata (), 22 | .rdata () 23 | ); 24 | 25 | endmodule 26 | 27 | module ram8 ( 28 | input wire clk, 29 | input wire write, 30 | input wire addr, 31 | output wire wdata, 32 | ); 33 | // something here 34 | reg [1:0] rdata [1:0]; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/bar.stderr.txt: -------------------------------------------------------------------------------- 1 | %Warning-UNUSED: FILEPATH_PLACEHOLDER:13: Signal is not used: clk 2 | %Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. 3 | %Warning-UNUSED: FILEPATH_PLACEHOLDER:14: Signal is not used: reset 4 | %Warning-UNUSED: FILEPATH_PLACEHOLDER:15: Signal is not used: a 5 | %Warning-UNUSED: FILEPATH_PLACEHOLDER:17: Signal is not used: b 6 | %Warning-UNUSED: FILEPATH_PLACEHOLDER:20: Signal is not used: valid 7 | %Warning-UNDRIVEN: FILEPATH_PLACEHOLDER:23: Signal is not driven: tmp_c 8 | %Error: Exiting due to 6 warning(s) 9 | %Error: Command Failed /usr/bin/verilator_bin --lint-only -sv -Wall FILEPATH_PLACEHOLDER -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ProgramItems.g4: -------------------------------------------------------------------------------- 1 | grammar ProgramItems; 2 | import CheckerItems; 3 | 4 | program_item : port_declaration ';' 5 | | non_port_program_item ; 6 | non_port_program_item : ( attribute_instance )* continuous_assign 7 | | ( attribute_instance )* module_or_generate_item_declaration 8 | | ( attribute_instance )* initial_construct 9 | | ( attribute_instance )* final_construct 10 | | ( attribute_instance )* concurrent_assertion_item 11 | | timeunits_declaration 12 | | program_generate_item ; 13 | program_generate_item : loop_generate_construct 14 | | conditional_generate_construct 15 | | generate_region 16 | | elaboration_system_task 17 | | simulation_control_task ; 18 | -------------------------------------------------------------------------------- /verilog-examples/transaction.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------------------------------- 4 | class transaction; 5 | $support() 6 | $support() 7 | //declaring the transaction items 8 | rand bit [3:0] a; 9 | rand bit [3:0] b; 10 | bit [6:0] c; 11 | function void display(string name); 12 | $display("-------------------------"); 13 | $display("- %s ",name); 14 | $display("-------------------------"); 15 | $display("- a = %0d, b = %0d",a,b); 16 | $display("- c = %0d",c); 17 | $display("-------------------------"); 18 | endfunction 19 | endclass -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ExpressionLeftsideValues.g4: -------------------------------------------------------------------------------- 1 | grammar ExpressionLeftsideValues; 2 | import Operators; 3 | 4 | net_lvalue : ps_or_hierarchical_net_identifier constant_select 5 | | '{' net_lvalue ( ',' net_lvalue )* '}' 6 | | ( assignment_pattern_expression_type )? assignment_pattern_net_lvalue ; 7 | variable_lvalue : ( implicit_class_handle '.' | package_scope )? hierarchical_variable_identifier select 8 | | '{' variable_lvalue ( ',' variable_lvalue )* '}' 9 | | ( assignment_pattern_expression_type )? assignment_pattern_variable_lvalue 10 | | streaming_concatenation ; 11 | nonrange_variable_lvalue : ( implicit_class_handle '.' | package_scope )? 12 | hierarchical_variable_identifier nonrange_select ; 13 | -------------------------------------------------------------------------------- /resources/va.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/vams.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/sdc_dark.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/sdc_light.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/sv_dark.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/sv_light.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/v_dark.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /resources/v_light.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | -------------------------------------------------------------------------------- /verilog-examples/comment_error.sv: -------------------------------------------------------------------------------- 1 | /* 2 | module abc 3 | */ 4 | 5 | /* 6 | module 123 7 | */ 8 | 9 | /* dog 10 | 11 | module 12 | cat */ 13 | 14 | module cat #( 15 | )( 16 | logic ck 17 | ); 18 | // Module body 19 | endmodule 20 | 21 | module abc #( 22 | )( 23 | logic ck 24 | ); 25 | // Module body 26 | endmodule 27 | 28 | 29 | module 123 #( 30 | )( 31 | logic ck 32 | ); 33 | // Module body 34 | endmodule 35 | 36 | 37 | 38 | // No error 39 | 40 | /*module abc 41 | */ 42 | 43 | /* 44 | moduleabc 45 | */ 46 | 47 | /* 48 | 49 | text module 123 50 | */ 51 | 52 | /* 53 | module ( 123 54 | */ 55 | 56 | /* 57 | Module www 58 | */ 59 | 60 | /* dog 61 | module 62 | */ -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/UDPPorts.g4: -------------------------------------------------------------------------------- 1 | grammar UDPPorts; 2 | import UDPBody; 3 | 4 | udp_port_list : output_port_identifier ',' input_port_identifier ( ',' input_port_identifier )* ; 5 | udp_declaration_port_list : udp_output_declaration ',' udp_input_declaration 6 | ( ',' udp_input_declaration )* ; 7 | udp_port_declaration : udp_output_declaration ';' 8 | | udp_input_declaration ';' 9 | | udp_reg_declaration ';' ; 10 | udp_output_declaration : ( attribute_instance )* 'output' port_identifier 11 | | ( attribute_instance )* 'output' 'reg' port_identifier ( '=' constant_expression )? ; 12 | udp_input_declaration : ( attribute_instance )* 'input' list_of_udp_port_identifiers ; 13 | udp_reg_declaration : ( attribute_instance )* 'reg' variable_identifier ; 14 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/UDPDeclaration.g4: -------------------------------------------------------------------------------- 1 | grammar UDPDeclaration; 2 | import UDPPorts; 3 | 4 | udp_nonansi_declaration : ( attribute_instance )* 'primitive' udp_identifier '(' udp_port_list ')' 5 | ';' ; 6 | udp_ansi_declaration : ( attribute_instance )* 'primitive' udp_identifier 7 | '(' udp_declaration_port_list ')' ';' ; 8 | udp_declaration : udp_nonansi_declaration udp_port_declaration ( udp_port_declaration )* udp_body 9 | 'endprimitive' ( ':' udp_identifier )? 10 | | udp_ansi_declaration udp_body 'endprimitive' ( ':' udp_identifier )? 11 | | 'extern' udp_nonansi_declaration | 'extern' udp_ansi_declaration 12 | | ( attribute_instance )* 'primitive' udp_identifier '(' '.*' ')' ';' ( udp_port_declaration )* 13 | udp_body 'endprimitive' ( ':' udp_identifier )? ; 14 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/SyntaxErrorListener.ts: -------------------------------------------------------------------------------- 1 | // import {SystemVerilogListener} from './grammar/build/SystemVerilogListener'; 2 | import { Recognizer, RecognitionException, ANTLRErrorListener } from 'antlr4ts'; 3 | 4 | /** 5 | * Stores errors in ANTLR parsing in a list for later access 6 | */ 7 | export class SyntaxErrorListener implements ANTLRErrorListener { 8 | public error_list = []; 9 | 10 | public syntaxError( 11 | _recognizer: Recognizer, 12 | offendingSymbol: T, 13 | line: number, 14 | charPositionInLine: number, 15 | msg: string, 16 | _e: RecognitionException | undefined 17 | ): void { 18 | line -= 1; 19 | this.error_list.push({ offendingSymbol, line, charPositionInLine, msg }); 20 | } 21 | } 22 | -------------------------------------------------------------------------------- /.prettierrc: -------------------------------------------------------------------------------- 1 | { 2 | "printWidth": 120, 3 | "tabWidth": 4, 4 | "useTabs": false, 5 | "semi": true, 6 | "singleQuote": true, 7 | "quoteProps": "as-needed", 8 | "jsxSingleQuote": false, 9 | "trailingComma": "none", 10 | "bracketSpacing": true, 11 | "bracketSameLine": false, 12 | "arrowParens": "always", 13 | "rangeStart": 0, 14 | "requirePragma": false, 15 | "insertPragma": false, 16 | "proseWrap": "preserve", 17 | "htmlWhitespaceSensitivity": "strict", 18 | "endOfLine": "lf", 19 | "embeddedLanguageFormatting": "auto", 20 | "overrides": [ 21 | { "files": "*.yaml", "options": { "tabWidth": 2 } }, 22 | { "files": "*.json", "options": { "printWidth": 130 } }, 23 | { "files": "*.md", "options": { "tabWidth": 2 } } 24 | ] 25 | } 26 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SpecifyPathDeclarations.g4: -------------------------------------------------------------------------------- 1 | grammar SpecifyPathDeclarations; 2 | import SpecifyBlockTerminals; 3 | 4 | path_declaration : simple_path_declaration ';' 5 | | edge_sensitive_path_declaration ';' 6 | | state_dependent_path_declaration ';' ; 7 | simple_path_declaration : parallel_path_description '=' path_delay_value 8 | | full_path_description '=' path_delay_value ; 9 | parallel_path_description : '(' specify_input_terminal_descriptor ( polarity_operator )? '=>' 10 | specify_output_terminal_descriptor ')' ; 11 | full_path_description : '(' list_of_path_inputs ( polarity_operator )? '*>' list_of_path_outputs ')' ; 12 | list_of_path_inputs : specify_input_terminal_descriptor ( ',' specify_input_terminal_descriptor )* ; 13 | list_of_path_outputs : specify_output_terminal_descriptor ( ',' specify_output_terminal_descriptor )* ; 14 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/LetDeclarations.g4: -------------------------------------------------------------------------------- 1 | grammar LetDeclarations; 2 | import PrimitiveInstantiationAndInstances; 3 | 4 | let_declaration : 'let' let_identifier ( '(' ( let_port_list )? ')' )? '=' expression ';' ; 5 | let_identifier : identifier ; 6 | let_port_list : let_port_item ( ',' let_port_item )* ; 7 | let_port_item : ( attribute_instance )* let_formal_type formal_port_identifier ( variable_dimension )* 8 | ( '=' expression )? ; 9 | let_formal_type : data_type_or_implicit | 'untyped' ; 10 | let_expression : ( package_scope )? let_identifier ( '(' ( let_list_of_arguments )? ')' )? ; 11 | let_list_of_arguments : ( let_actual_arg )? ( ',' ( let_actual_arg )? )* 12 | ( ',' '.' identifier '(' ( let_actual_arg )? ')' )* 13 | | '.' identifier '(' ( let_actual_arg )? ')' ( ',' '.' identifier '(' ( let_actual_arg )? ')' )* ; 14 | let_actual_arg : expression ; 15 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/InterfaceDeclarations.g4: -------------------------------------------------------------------------------- 1 | grammar InterfaceDeclarations; 2 | import AssertionDeclarations; 3 | 4 | modport_declaration : 'modport' modport_item ( ',' modport_item )* ';' ; 5 | modport_item : modport_identifier '(' modport_ports_declaration 6 | ( ',' modport_ports_declaration )* ')' ; 7 | modport_ports_declaration : ( attribute_instance )* modport_simple_ports_declaration 8 | | ( attribute_instance )* modport_tf_ports_declaration 9 | | ( attribute_instance )* modport_clocking_declaration ; 10 | modport_clocking_declaration : 'clocking' clocking_identifier ; 11 | modport_simple_ports_declaration : port_direction modport_simple_port ( ',' modport_simple_port )* ; 12 | modport_simple_port : port_identifier | '.' port_identifier '(' ( expression )? ')' ; 13 | modport_tf_ports_declaration : import_export modport_tf_port ( ',' modport_tf_port )* ; 14 | modport_tf_port : method_prototype | tf_identifier ; 15 | import_export : 'import' | 'export' ; 16 | -------------------------------------------------------------------------------- /src/compiling/DiagnosticData.ts: -------------------------------------------------------------------------------- 1 | import { DiagnosticSeverity } from 'vscode-languageserver/node'; 2 | 3 | /** Defines the information needed to create a `Diagnostic` object. */ 4 | export class DiagnosticData { 5 | line: number; 6 | problem: string; 7 | diagnosticSeverity: DiagnosticSeverity; 8 | filePath: string; 9 | offendingSymbol: string; 10 | charPosition: number; 11 | } 12 | 13 | /** 14 | Checks if `diagnosticData`'s fields are not `undefined` 15 | 16 | @param diagnosticData the DiagnosticData 17 | @return true if at least one field is `undefined` 18 | */ 19 | export function isDiagnosticDataUndefined(diagnosticData: DiagnosticData): boolean { 20 | if ( 21 | diagnosticData.line === undefined || 22 | diagnosticData.problem === undefined || 23 | diagnosticData.diagnosticSeverity === undefined || 24 | diagnosticData.filePath === undefined 25 | ) { 26 | return true; 27 | } 28 | 29 | return false; 30 | } 31 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/PackageItems.g4: -------------------------------------------------------------------------------- 1 | grammar PackageItems; 2 | import DeclarationTypes; 3 | 4 | package_item : package_or_generate_item_declaration 5 | | anonymous_program 6 | | include_compiler_directive 7 | | package_export_declaration 8 | | timeunits_declaration ; 9 | package_or_generate_item_declaration : net_declaration 10 | | data_declaration 11 | | task_declaration 12 | | function_declaration 13 | | checker_declaration 14 | | dpi_import_export 15 | | extern_constraint_declaration 16 | | class_declaration 17 | | class_constructor_declaration 18 | | local_parameter_declaration ';' 19 | | parameter_declaration ';' 20 | | covergroup_declaration 21 | | assertion_item_declaration 22 | | ';' ; 23 | anonymous_program : 'program' ';' ( anonymous_program_item )* 'endprogram' ; 24 | anonymous_program_item : task_declaration 25 | | function_declaration 26 | | class_declaration 27 | | covergroup_declaration 28 | | class_constructor_declaration 29 | | ';' ; 30 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/LoopingStatements.g4: -------------------------------------------------------------------------------- 1 | grammar LoopingStatements; 2 | import SubroutineCallStatements; 3 | 4 | loop_statement : 'forever' statement_or_null 5 | | 'repeat' '(' expression ')' statement_or_null 6 | | 'while' '(' expression ')' statement_or_null 7 | | 'for' '(' ( for_initialization )? ';' ( expression )? ';' ( for_step )? ')' statement_or_null 8 | | 'do' statement_or_null 'while' '(' expression ')' ';' 9 | | 'foreach' '(' ps_or_hierarchical_array_identifier '[' loop_variables ']' ')' statement ; 10 | for_initialization : list_of_variable_assignments 11 | | for_variable_declaration ( ',' for_variable_declaration )* ; 12 | for_variable_declaration : ( 'var' )? data_type variable_identifier '=' expression 13 | ( ',' variable_identifier '=' expression )* ; 14 | for_step : for_step_assignment ( ',' for_step_assignment )* ; 15 | for_step_assignment : operator_assignment | inc_or_dec_expression | function_subroutine_call ; 16 | loop_variables : ( index_variable_identifier )? ( ',' ( index_variable_identifier )? )* ; 17 | -------------------------------------------------------------------------------- /src/test/test-files/VeribleCompiler.test/foo.stdout.txt: -------------------------------------------------------------------------------- 1 | foo.sv:3:8: Declared module does not match the first dot-delimited component of file name: "foo" [Style: file-names] [module-filename] 2 | foo.sv:5:3: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 3 | foo.sv:8:25: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 4 | foo.sv:10:28: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 5 | foo.sv:11:1: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 6 | foo.sv:12:1: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 7 | foo.sv:13:26: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 8 | foo.sv:14:8: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 9 | foo.sv:15:21: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 10 | foo.sv:16:21: Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces] 11 | foo.sv:21:10: File must end with a newline. [Style: posix-file-endings] [posix-eof] 12 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/UDPBody.g4: -------------------------------------------------------------------------------- 1 | grammar UDPBody; 2 | import UDPInstantiation; 3 | 4 | udp_body : combinational_body | sequential_body ; 5 | combinational_body : 'table' combinational_entry ( combinational_entry )* 'endtable' ; 6 | combinational_entry : level_input_list ':' output_symbol ';' ; 7 | sequential_body : ( udp_initial_statement )? 'table' sequential_entry ( sequential_entry )* 'endtable' ; 8 | udp_initial_statement : 'initial' output_port_identifier '=' init_val ';' ; 9 | init_val : ONE APOSTROPHE B ( ZERO | ONE | X_DIGIT ) | ONE | ZERO ; 10 | sequential_entry : seq_input_list ':' current_state ':' next_state ';' ; 11 | seq_input_list : level_input_list | edge_input_list ; 12 | level_input_list : level_symbol ( level_symbol )* ; 13 | edge_input_list : ( level_symbol )* edge_indicator ( level_symbol )* ; 14 | edge_indicator : '(' level_symbol level_symbol ')' | edge_symbol ; 15 | current_state : level_symbol ; 16 | next_state : output_symbol | '-' ; 17 | output_symbol : ZERO | ONE | X_DIGIT ; 18 | level_symbol : ZERO | ONE | X_DIGIT | QUESTION | B ; 19 | edge_symbol : R | F | P | N | '*' ; 20 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/TaskDeclarations.g4: -------------------------------------------------------------------------------- 1 | grammar TaskDeclarations; 2 | import BlockItemDeclarations; 3 | 4 | task_declaration : 'task' ( lifetime )? task_body_declaration ; 5 | task_body_declaration : ( interface_identifier '.' | class_scope )? task_identifier ';' 6 | ( tf_item_declaration )* ( statement_or_null )* 'endtask' ( ':' task_identifier )? 7 | | ( interface_identifier '.' | class_scope )? task_identifier '(' ( tf_port_list )? ')' ';' 8 | ( block_item_declaration )* ( statement_or_null )* 'endtask' ( ':' task_identifier )? ; 9 | tf_item_declaration : block_item_declaration | tf_port_declaration ; 10 | tf_port_list : tf_port_item ( ',' tf_port_item )* ; 11 | tf_port_item : ( attribute_instance )* ( tf_port_direction )? ( 'var' )? data_type_or_implicit 12 | ( port_identifier ( variable_dimension )* ( '=' expression )? )? ; 13 | tf_port_direction : port_direction | 'const' 'ref' ; 14 | tf_port_declaration : ( attribute_instance )* tf_port_direction ( 'var' )? data_type_or_implicit 15 | list_of_tf_variable_identifiers ';' ; 16 | task_prototype : 'task' task_identifier ( '(' ( tf_port_list )? ')' )? ; 17 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Concatenations.g4: -------------------------------------------------------------------------------- 1 | grammar Concatenations; 2 | import SubroutineCalls; 3 | 4 | concatenation : '{' expression ( ',' expression )* '}' ; 5 | constant_concatenation : '{' constant_expression ( ',' constant_expression )* '}' ; 6 | constant_multiple_concatenation : '{' constant_expression constant_concatenation '}' ; 7 | module_path_concatenation : '{' module_path_expression ( ',' module_path_expression )* '}' ; 8 | module_path_multiple_concatenation : '{' constant_expression module_path_concatenation '}' ; 9 | multiple_concatenation : '{' expression concatenation '}' ; 10 | streaming_concatenation : '{' stream_operator ( slice_size )? stream_concatenation '}' ; 11 | stream_operator : '>>' | '<<' ; 12 | slice_size : simple_type | constant_expression ; 13 | stream_concatenation : '{' stream_expression ( ',' stream_expression )* '}' ; 14 | stream_expression : expression ( 'with' '[' array_range_expression ']' )? ; 15 | array_range_expression : expression 16 | | expression ':' expression 17 | | expression '+:' expression 18 | | expression '-:' expression ; 19 | empty_unpacked_array_concatenation : '{' '}' ; 20 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2018 Eirik Prestegårdshus 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. -------------------------------------------------------------------------------- /schemas/tasks.schema.json: -------------------------------------------------------------------------------- 1 | { 2 | "$schema": "http://json-schema.org/draft-07/schema#", 3 | "$id": "./schemas/tasks.schema.json", 4 | "title": "Verilog/SystemVerilog Tasks", 5 | "type": "object", 6 | "properties": { 7 | "tasks": { 8 | "type": "array", 9 | "items": { 10 | "type": "object", 11 | "default": { 12 | "label": "Verilator", 13 | "type": "shell", 14 | "command": "verilator", 15 | "args": ["-sv", "--language", "1800-2012", "--lint-only", "${relativeFile}"], 16 | "problemMatcher": { 17 | "owner": "systemverilog", 18 | "pattern": { 19 | "regexp": "^%([\\w-]+): ([\\w_\\./-]+):(\\d+):\\s+([\\w\\W]+)$", 20 | "severity": 1, 21 | "file": 2, 22 | "line": 3, 23 | "message": 4 24 | } 25 | } 26 | } 27 | } 28 | } 29 | } 30 | } 31 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/CheckerItems.g4: -------------------------------------------------------------------------------- 1 | grammar CheckerItems; 2 | import ClassItems; 3 | 4 | checker_port_list : checker_port_item ( ',' checker_port_item )* ; 5 | checker_port_item : ( attribute_instance )* ( checker_port_direction )? property_formal_type 6 | formal_port_identifier ( variable_dimension )* ( '=' property_actual_arg )? ; 7 | checker_port_direction : 'input' | 'output' ; 8 | checker_or_generate_item : checker_or_generate_item_declaration 9 | | initial_construct 10 | | always_construct 11 | | final_construct 12 | | assertion_item 13 | | continuous_assign 14 | | checker_generate_item ; 15 | checker_or_generate_item_declaration : ( 'rand' )? data_declaration 16 | | function_declaration 17 | | checker_declaration 18 | | assertion_item_declaration 19 | | covergroup_declaration 20 | | genvar_declaration 21 | | clocking_declaration 22 | | 'default' 'clocking' clocking_identifier ';' 23 | | 'default' 'disable' 'iff' expression_or_dist ';' 24 | | ';' ; 25 | checker_generate_item : loop_generate_construct 26 | | conditional_generate_construct 27 | | generate_region 28 | | elaboration_system_task 29 | | simulation_control_task ; 30 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ConfigurationSourceText.g4: -------------------------------------------------------------------------------- 1 | grammar ConfigurationSourceText; 2 | import InterfaceItems; 3 | 4 | config_declaration : 'config' config_identifier ';' ( local_parameter_declaration ';' )* design_statement 5 | ( config_rule_statement )* 'endconfig' ( ':' config_identifier )? ; 6 | design_statement : 'design' ( ( library_identifier '.' )? cell_identifier )* ';' ; 7 | config_rule_statement : default_clause liblist_clause ';' 8 | | inst_clause liblist_clause ';' 9 | | inst_clause use_clause ';' 10 | | cell_clause liblist_clause ';' 11 | | cell_clause use_clause ';' ; 12 | default_clause : 'default' ; 13 | inst_clause : 'instance' inst_name ; 14 | inst_name : topmodule_identifier ( '.' instance_identifier )* ; 15 | cell_clause : 'cell' ( library_identifier '.' )? cell_identifier ; 16 | liblist_clause : 'liblist' ( library_identifier )* ; 17 | use_clause : 'use' ( library_identifier '.' )? cell_identifier ( ':' 'config' )? 18 | | 'use' named_parameter_assignment ( ',' named_parameter_assignment )* ( ':' 'config' )? 19 | | 'use' ( library_identifier '.' )? cell_identifier named_parameter_assignment 20 | ( ',' named_parameter_assignment )* ( ':' 'config' )? ; 21 | -------------------------------------------------------------------------------- /src/test/test-files/design.sv: -------------------------------------------------------------------------------- 1 | //---------------------------------------------- 2 | // www.verificationguide.com design.sv 3 | //---------------------------------------------- 4 | /* 5 | -------------- 6 | valid ---->| | 7 | | | 8 | a -/--->| | 9 | | adder |---/-> c 10 | b -/--->| | 11 | | | 12 | -------------- 13 | ^ ^ 14 | | | 15 | clk reset 16 | 17 | */ 18 | module adder( 19 | `ifdef FPGA 20 | input alternative_clock, 21 | `endif 22 | input clk, 23 | input reset, 24 | input [3:0] a, 25 | input [3:0] b, 26 | input valid, 27 | output [6:0] c 28 | ); 29 | 30 | reg [6:0] tmp_c; 31 | 32 | //Reset 33 | always_ff @(posedge reset) 34 | tmp_c <= pa_adder::RV_C; 35 | 36 | `ifdef VERBOSE_RESET 37 | always @(posedge reset) begin 38 | wait(posedge reset); 39 | $display("Reset asserted!") 40 | end 41 | `endif 42 | 43 | // Waddition operation 44 | always @(posedge clk) 45 | if(valid) tmp_c <= a + b; 46 | 47 | assign c = tmp_c; 48 | 49 | endmodule -------------------------------------------------------------------------------- /verilog-examples/design.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------- 2 | // www.verificationguide.com design.sv 3 | //---------------------------------------------- 4 | /* 5 | -------------- 6 | valid ---->| | 7 | | | 8 | a -/--->| | 9 | | adder |---/-> c 10 | b -/--->| | 11 | | | 12 | -------------- 13 | ^ ^ 14 | | | 15 | clk reset 16 | 17 | */ 18 | module adder( 19 | `ifdef FPGA 20 | input alternative_clock, 21 | `endif 22 | input clk, 23 | input reset, 24 | input [3:0] a, 25 | input [3:0] b, 26 | input valid, 27 | output [6:0] c 28 | ); 29 | 30 | reg [6:0] tmp_c; 31 | 32 | //Reset 33 | always_ff @(posedge reset) 34 | tmp_c <= pa_adder::RV_C; 35 | 36 | `ifdef VERBOSE_RESET 37 | always @(posedge reset) begin 38 | wait(posedge reset); 39 | $display("Reset asserted!") 40 | end 41 | `endif 42 | 43 | // Waddition operation 44 | always @(posedge clk) 45 | if(valid) tmp_c <= a + b; 46 | 47 | assign c = tmp_c; 48 | 49 | endmodule -------------------------------------------------------------------------------- /verilog-examples/design.vh: -------------------------------------------------------------------------------- 1 | //---------------------------------------------- 2 | // www.verificationguide.com design.sv 3 | //---------------------------------------------- 4 | /* 5 | -------------- 6 | valid ---->| | 7 | | | 8 | a -/--->| | 9 | | adder |---/-> c 10 | b -/--->| | 11 | | | 12 | -------------- 13 | ^ ^ 14 | | | 15 | clk reset 16 | 17 | */ 18 | module adder( 19 | `ifdef FPGA 20 | input alternative_clock, 21 | `endif 22 | input clk, 23 | input reset, 24 | input [3:0] a, 25 | input [3:0] b, 26 | input valid, 27 | output [6:0] c 28 | ); 29 | 30 | reg [6:0] tmp_c; 31 | 32 | //Reset 33 | always_ff @(posedge reset) 34 | tmp_c <= pa_adder::RV_C; 35 | 36 | `ifdef VERBOSE_RESET 37 | always @(posedge reset) begin 38 | wait(posedge reset); 39 | $display("Reset asserted!") 40 | end 41 | `endif 42 | 43 | // Waddition operation 44 | always @(posedge clk) 45 | if(valid) tmp_c <= a + b; 46 | 47 | assign c = tmp_c; 48 | 49 | endmodule -------------------------------------------------------------------------------- /src/utils/client.ts: -------------------------------------------------------------------------------- 1 | import { TextDocument } from 'vscode'; 2 | 3 | /** 4 | Check if a given `document` is a SystemVerilog file. 5 | 6 | @param document the document to check 7 | @return true if the document is a SystemVerilog file 8 | */ 9 | export function isSystemVerilogDocument(document: TextDocument | undefined): boolean { 10 | return document?.languageId === 'systemverilog' || document?.languageId === 'systemverilogheader'; 11 | } 12 | 13 | /** 14 | Check if a given `document` is a Verilog file. 15 | 16 | @param document the document to check 17 | @return true if the document is a Verilog file 18 | */ 19 | export function isVerilogDocument(document: TextDocument | undefined): boolean { 20 | return document?.languageId === 'verilog' || document?.languageId === 'verilogheader'; 21 | } 22 | 23 | /** 24 | Check if a given `document` is a VerilogA/VerilogAMS file. 25 | 26 | @param document the document to check 27 | @return true if the document is a Verilog file 28 | */ 29 | export function isVerilogAMSDocument(document: TextDocument | undefined): boolean { 30 | return document?.languageId === 'veriloga' || document?.languageId === 'verilogams'; 31 | } 32 | -------------------------------------------------------------------------------- /verilog-examples/class_example.sv: -------------------------------------------------------------------------------- 1 | //-------------------------------------------------- 2 | // Copyright (c) 2019 ChipVerify. All Rights Reserved. 3 | // Author : Admin 4 | // Article : SystemVerilog Class 5 | // Category : SystemVerilog 6 | //-------------------------------------------------- 7 | 8 | 9 | 10 | //testing 11 | //---------------------------------- 12 | // Testbench 13 | //---------------------------------- 14 | // Create a new class with a single member called 15 | // count that stores integer values 16 | class Packet; 17 | int count; 18 | endclass 19 | 20 | module tb; 21 | // Create a "handle" for the class Packet that can point to an 22 | // object of the class type Packet 23 | // Note: This "handle" now points to NULL 24 | Packet pkt; 25 | 26 | initial begin 27 | if (pkt == null) 28 | $display("Packet handle 'pkt' is null"); 29 | 30 | // Display the class member using the "handle" 31 | // Expect a run-time error because pkt is not an object 32 | // yet, and is still pointing to NULL. So pkt is not 33 | // aware that it should hold a member 34 | $display ("count = %0d", pkt.count); 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /verilog-examples/.vscode/tasks.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "2.0.0", 3 | "tasks": [ 4 | { 5 | "label": "SystemVerilog: Verilator", 6 | "command": "verilator", 7 | "args": ["-sv", "--language", "1800-2012", "--lint-only", "${file}"], 8 | "problemMatcher": { 9 | "owner": "systemverilog", 10 | "pattern": [ 11 | { 12 | "regexp": "%((?:Warning|Error)(?:-[A-Z0-9]+)?): ((\\S+):(\\d+):((\\d+):)? )?(.*)$", 13 | "severity": 1, 14 | "file": 2, 15 | "line": 3, 16 | "column": 4, 17 | "message": 5 18 | } 19 | ] 20 | }, 21 | "group": { 22 | "kind": "build", 23 | "isDefault": true 24 | }, 25 | "presentation": { 26 | "echo": true, 27 | "reveal": "always", 28 | "focus": false, 29 | "panel": "shared", 30 | "showReuseMessage": true, 31 | "clear": false 32 | } 33 | } 34 | ] 35 | } 36 | -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/foo.stderr.txt: -------------------------------------------------------------------------------- 1 | %Error: FILEPATH_PLACEHOLDER:1: Cannot find include file: environment.sv 2 | %Error: FILEPATH_PLACEHOLDER:1: This may be because there's no search path specified with -I. 3 | %Error: FILEPATH_PLACEHOLDER:1: Looked in: 4 | %Error: FILEPATH_PLACEHOLDER:1: environment.sv 5 | %Error: FILEPATH_PLACEHOLDER:1: environment.sv.v 6 | %Error: FILEPATH_PLACEHOLDER:1: environment.sv.sv 7 | %Error: FILEPATH_PLACEHOLDER:1: obj_dir/environment.sv 8 | %Error: FILEPATH_PLACEHOLDER:1: obj_dir/environment.sv.v 9 | %Error: FILEPATH_PLACEHOLDER:1: obj_dir/environment.sv.sv 10 | %Error: FILEPATH_PLACEHOLDER:3: Unsupported: SystemVerilog 2005 reserved word not implemented: class 11 | %Error: FILEPATH_PLACEHOLDER:3: syntax error, unexpected IDENTIFIER 12 | %Error: FILEPATH_PLACEHOLDER:3: Unsupported: SystemVerilog 2005 reserved word not implemented: extends 13 | %Error: FILEPATH_PLACEHOLDER:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass 14 | %Error: FILEPATH_PLACEHOLDER:28: syntax error, unexpected <=, expecting IDENTIFIER 15 | %Error: Exiting due to 14 error(s) 16 | %Error: Command Failed /usr/bin/verilator_bin --lint-only -sv -Wall FILEPATH_PLACEHOLDER -------------------------------------------------------------------------------- /src/test/test-files/VerilatorCompiler.test/qux.stderr.txt: -------------------------------------------------------------------------------- 1 | %Warning-DECLFILENAME: test-files/DocumentCompiler.test/qux.sv:17: Filename 'qux' does not match NOTFOUNDMODULE name: externalModule 2 | %Warning-DECLFILENAME: Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. 3 | %Error: test-files/DocumentCompiler.test/qux.sv:17: Cannot find file containing module: externalModule 4 | %Error: test-files/DocumentCompiler.test/qux.sv:17: This may be because there's no search path specified with -I. 5 | %Error: test-files/DocumentCompiler.test/qux.sv:17: Looked in: 6 | %Error: test-files/DocumentCompiler.test/qux.sv:17: externalModule 7 | %Error: test-files/DocumentCompiler.test/qux.sv:17: externalModule.v 8 | %Error: test-files/DocumentCompiler.test/qux.sv:17: externalModule.sv 9 | %Error: test-files/DocumentCompiler.test/qux.sv:17: obj_dir/externalModule 10 | %Error: test-files/DocumentCompiler.test/qux.sv:17: obj_dir/externalModule.v 11 | %Error: test-files/DocumentCompiler.test/qux.sv:17: obj_dir/externalModule.sv 12 | %Error: Exiting due to 9 error(s), 1 warning(s) 13 | %Error: Command Failed /usr/bin/verilator_bin --lint-only -sv -Wall test-files/DocumentCompiler.test/qux.sv -------------------------------------------------------------------------------- /verilog-examples/inheritance_example.sv: -------------------------------------------------------------------------------- 1 | class Packet; 2 | int addr; 3 | 4 | function new (int addr); 5 | this.addr = addr; 6 | endfunction 7 | 8 | function display (); 9 | $display ("[Base] addr=0x%0h", addr); 10 | endfunction 11 | endclass 12 | 13 | // A subclass called 'ExtPacket' is derived from the base class 'Packet' using 14 | // 'extends' keyword which makes 'EthPacket' a child of the parent class 'Packet' 15 | // The child class inherits all variables and methods from the parent class 16 | class ExtPacket extends Packet; 17 | 18 | // This is a new variable only available in child class 19 | int data; 20 | 21 | function new (int addr, data); 22 | super.new (addr); // Calls 'new' method of parent class 23 | this.data = data; 24 | endfunction 25 | 26 | function display (); 27 | $display ("[Child] addr=0x%0h data=0x%0h", addr, data); 28 | endfunction 29 | endclass 30 | 31 | module tb; 32 | Packet bc; // bc stands for BaseClass 33 | ExtPacket sc; // sc stands for SubClass 34 | 35 | initial begin 36 | bc = new (32'hface_cafe); 37 | bc.display (); 38 | 39 | sc = new (32'hfeed_feed, 32'h1234_5678); 40 | sc.display (); 41 | end 42 | endmodule -------------------------------------------------------------------------------- /verilog-examples/random_test.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------------------------------- 4 | `include "environment.sv" 5 | program test(intf i_intf); 6 | 7 | //declaring environment instance 8 | environment env; 9 | 10 | initial begin 11 | //creating environment 12 | env = new(i_intf); 13 | 14 | //setting the repeat count of generator as 4, means to generate 4 packets 15 | env.gen.repeat_count = 4; 16 | 17 | //calling run of env, it interns calls generator and driver main tasks. 18 | env.run(); 19 | end 20 | endprogram 21 | 22 | typedef int my_int; 23 | 24 | class foo; 25 | 26 | int x; 27 | 28 | endclass; 29 | 30 | 31 | 32 | class bar extends foo; 33 | 34 | int y; 35 | 36 | endclass; 37 | 38 | 39 | foo z; 40 | z = new bar(); 41 | 42 | z.//it should suggest both x and y as field inputs to autocomplete with 43 | 44 | 45 | 46 | int y; //it should recognize that the scope of y here is outside of bar 47 | 48 | 49 | 50 | y = 0; /*if `go to definition` is used on y in the line 51 | 52 | it should go to the line above it, instead of inside the class bar*/ 53 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ProceduralBlocksAndAssignments.g4: -------------------------------------------------------------------------------- 1 | grammar ProceduralBlocksAndAssignments; 2 | import ParallelAndSequentialBlocks; 3 | 4 | initial_construct : 'initial' statement_or_null ; 5 | always_construct : always_keyword statement ; 6 | always_keyword : 'always' | 'always_comb' | 'always_latch' | 'always_ff' ; 7 | final_construct : 'final' function_statement ; 8 | blocking_assignment : variable_lvalue '=' delay_or_event_control expression 9 | | nonrange_variable_lvalue '=' dynamic_array_new 10 | | ( implicit_class_handle '.' | class_scope | package_scope )? hierarchical_variable_identifier 11 | select '=' class_new 12 | | operator_assignment ; 13 | operator_assignment : variable_lvalue assignment_operator expression ; 14 | assignment_operator : '=' | '+=' | '-=' | '*=' | '/=' | '%=' | '&=' | '|=' | '^=' | '<<=' | '>>=' 15 | | '<<<=' | '>>>=' ; 16 | nonblocking_assignment : variable_lvalue '<=' ( delay_or_event_control )? expression ; 17 | procedural_continuous_assignment : 'assign' variable_assignment 18 | | 'deassign' variable_lvalue 19 | | 'force' variable_assignment 20 | | 'force' net_assignment 21 | | 'release' variable_lvalue 22 | | 'release' net_lvalue ; 23 | variable_assignment : variable_lvalue '=' expression ; 24 | -------------------------------------------------------------------------------- /verilog-examples/generator.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------- 4 | class generator; 5 | 6 | //declaring transaction class 7 | rand transaction trans; 8 | 9 | //repeat count, to specify number of items to generate 10 | int repeat_count; 11 | 12 | //mailbox, to generate and send the packet to driver 13 | mailbox gen2driv; 14 | 15 | //event, to indicate the end of transaction generation 16 | event ended; 17 | 18 | //constructor 19 | function new(mailbox gen2driv); 20 | //getting the mailbox handle from env, in order to share the transaction packet between the generator and driver, the same mailbox is shared between both. 21 | this.gen2driv = gen2driv; 22 | endfunction 23 | 24 | //main task, generates(create and randomizes) the repeat_count number of transaction packets and puts into mailbox 25 | task main(); 26 | repeat(repeat_count) begin 27 | trans = new(); 28 | if( !trans.randomize() ) $fatal("Gen:: trans randomization failed"); 29 | trans.display("[ Generator ]"); 30 | gen2driv.put(trans); 31 | end 32 | -> ended; //triggering indicatesthe end of generation 33 | endtask 34 | 35 | endclass -------------------------------------------------------------------------------- /src/test/runTest.ts: -------------------------------------------------------------------------------- 1 | import * as path from 'path'; 2 | import { runTests } from '@vscode/test-electron'; 3 | 4 | async function main() { 5 | try { 6 | // The folder containing the Extension Manifest package.json 7 | // Passed to `--extensionDevelopmentPath` 8 | const extensionDevelopmentPath = path.resolve(__dirname, '../../'); 9 | 10 | // The path to the extension test script 11 | // Passed to --extensionTestsPath 12 | const extensionTestsPath = path.resolve( 13 | __dirname, 14 | `./index${typeof process.argv[2] !== 'undefined' ? process.argv[2] : ''}` 15 | ); 16 | 17 | const workspacePath = path.resolve(__dirname, '../../verilog-examples'); 18 | 19 | // Download VS Code, unzip it and run the integration test 20 | await runTests({ 21 | extensionDevelopmentPath, 22 | extensionTestsPath, 23 | launchArgs: [workspacePath, '--disable-workspace-trust', '--disable-extensions'], 24 | version: 'stable', 25 | timeout: 30000 // 30 seconds (default was 10) 26 | }); 27 | } catch (err) { 28 | console.error('Failed to run tests'); 29 | process.exit(1); 30 | } 31 | } 32 | 33 | main(); 34 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Randsequence.g4: -------------------------------------------------------------------------------- 1 | grammar Randsequence; 2 | import SpecifyBlockDeclaration; 3 | 4 | randsequence_statement : 'randsequence' '(' ( production_identifier )? ')' production ( production )* 5 | 'endsequence' ; 6 | production : ( data_type_or_void )? production_identifier ( '(' tf_port_list ')' )? ':' rs_rule 7 | ( '|' rs_rule )* ';' ; 8 | rs_rule : rs_production_list ( ':=' weight_specification ( rs_code_block )? )? ; 9 | rs_production_list : rs_prod ( rs_prod )* 10 | | 'rand' 'join' ( '(' expression ')' )? production_item production_item ( production_item )* ; 11 | weight_specification : integral_number | ps_identifier | '(' expression ')' ; 12 | rs_code_block : '{' ( data_declaration )* ( statement_or_null )* '}' ; 13 | rs_prod : production_item | rs_code_block | rs_if_else | rs_repeat | rs_case ; 14 | production_item : production_identifier ( '(' list_of_arguments ')' )? ; 15 | rs_if_else : 'if' '(' expression ')' production_item ( 'else' production_item )? ; 16 | rs_repeat : 'repeat' '(' expression ')' production_item ; 17 | rs_case : 'case' '(' case_expression ')' rs_case_item ( rs_case_item )* 'endcase' ; 18 | rs_case_item : case_item_expression ( ',' case_item_expression )* ':' production_item ';' 19 | | 'default' ( ':' )? production_item ';' ; 20 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/GeneratedInstantiation.g4: -------------------------------------------------------------------------------- 1 | grammar GeneratedInstantiation; 2 | import UDPDeclaration; 3 | 4 | generate_region : 'generate' ( generate_item )* 'endgenerate'; 5 | loop_generate_construct : 6 | 'for' '(' genvar_initialization ';' genvar_expression ';' genvar_iteration ')' generate_block ; 7 | genvar_initialization : ( 'genvar' )? genvar_identifier '=' constant_expression ; 8 | genvar_iteration : genvar_identifier assignment_operator genvar_expression 9 | | inc_or_dec_operator genvar_identifier 10 | | genvar_identifier inc_or_dec_operator ; 11 | conditional_generate_construct : if_generate_construct | case_generate_construct ; 12 | if_generate_construct : 'if' '(' constant_expression ')' generate_block ( 'else' generate_block )? ; 13 | case_generate_construct : 'case' '(' constant_expression ')' case_generate_item ( case_generate_item )* 14 | 'endcase' ; 15 | case_generate_item : constant_expression ( ',' constant_expression )* ':' generate_block 16 | | 'default' ( ':' )? generate_block ; 17 | generate_block : generate_item | ( generate_block_identifier ':' )? 'begin' 18 | ( ':' generate_block_identifier )? ( generate_item )* 'end' ( ':' generate_block_identifier )? ; 19 | generate_item : module_or_generate_item | interface_or_generate_item | checker_or_generate_item ; 20 | -------------------------------------------------------------------------------- /verilog-examples/parameter_test.sv: -------------------------------------------------------------------------------- 1 | module portTest ( 2 | input dataIn, 3 | output dataOut 4 | ); 5 | 6 | assign dataOut = dataIn + 1; 7 | 8 | endmodule 9 | 10 | module parameterTest #( 11 | parameter EMPTY_PARAMETER, 12 | parameter DEFINED_PARAMETER = 1, 13 | parameter bit BIT_PARAMETER = 1, 14 | parameter bit [31:0] BIT_ARRAY_PARAMETER = 32'b1, 15 | parameter int INT_PARAMETER = 10, 16 | parameter int unsigned INT_UNSIGNED_PARAMETER = 10, 17 | parameter PACKAGE_PARAMETER = pa_Package::PARAMETER 18 | )( 19 | input logic ck, 20 | input logic arst, 21 | output logic [31:0] data 22 | ); 23 | 24 | localparam LPARAM_0 = EMPTY_PARAMETER; 25 | localparam LPARAM_1 = DEFINED_PARAMETER; 26 | localparam LPARAM_2 = BIT_PARAMETER; 27 | localparam LPARAM_3 = BIT_ARRAY_PARAMETER; 28 | localparam LPARAM_4 = INT_PARAMETER; 29 | localparam LPARAM_5 = INT_UNSIGNED_PARAMETER; 30 | localparam LPARAM_6 = PACKAGE_PARAMETER; 31 | 32 | logic [31:0] currentData; 33 | logic [31:0] nextData; 34 | 35 | assign data = currentData; 36 | 37 | always_ff @(posedge ck or arst) begin 38 | if(arst) begin 39 | currentData <= '0; 40 | end else begin 41 | currentData <= nextData; 42 | end 43 | end 44 | 45 | portTest u_test ( 46 | .dataIn (currentData), 47 | .dataOut (nextData) 48 | ); 49 | 50 | endmodule 51 | 52 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ClockingBlock.g4: -------------------------------------------------------------------------------- 1 | grammar ClockingBlock; 2 | import Randsequence; 3 | 4 | clocking_declaration : ( 'default' )? 'clocking' ( clocking_identifier )? clocking_event ';' 5 | ( clocking_item )* 'endclocking' ( ':' clocking_identifier )? 6 | | 'global' 'clocking' ( clocking_identifier )? clocking_event ';' 'endclocking' 7 | ( ':' clocking_identifier )? ; 8 | clocking_event : '@' identifier | '@' '(' event_expression ')' ; 9 | clocking_item : 'default' default_skew ';' 10 | | clocking_direction list_of_clocking_decl_assign ';' 11 | | ( attribute_instance )* assertion_item_declaration ; 12 | default_skew : 'input' clocking_skew 13 | | 'output' clocking_skew 14 | | 'input' clocking_skew 'output' clocking_skew ; 15 | clocking_direction : 'input' ( clocking_skew )? 16 | | 'output' ( clocking_skew )? 17 | | 'input' ( clocking_skew )? 'output' ( clocking_skew )? 18 | | 'inout' ; 19 | list_of_clocking_decl_assign : clocking_decl_assign ( ',' clocking_decl_assign )* ; 20 | clocking_decl_assign : signal_identifier ( '=' expression )? ; 21 | clocking_skew : edge_identifier ( delay_control )? | delay_control ; 22 | clocking_drive : clockvar_expression '<=' ( cycle_delay )? expression ; 23 | cycle_delay : '##' integral_number | '##' identifier | '##' '(' expression ')' ; 24 | clockvar : hierarchical_identifier ; 25 | clockvar_expression : clockvar select ; 26 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/DeclarationAssignments.g4: -------------------------------------------------------------------------------- 1 | grammar DeclarationAssignments; 2 | import DeclarationRanges; 3 | 4 | defparam_assignment : hierarchical_parameter_identifier '=' constant_mintypmax_expression ; 5 | net_decl_assignment : net_identifier ( unpacked_dimension )* ( '=' expression )? ; 6 | param_assignment : parameter_identifier ( unpacked_dimension )* ( '=' constant_param_expression )? ; 7 | specparam_assignment : specparam_identifier '=' constant_mintypmax_expression 8 | | pulse_control_specparam ; 9 | type_assignment : type_identifier ( '=' data_type )? ; 10 | pulse_control_specparam : 'PATHPULSE$' '=' '(' reject_limit_value ( ',' error_limit_value )? ')' 11 | | 'PATHPULSE$' specify_input_terminal_descriptor '$' specify_output_terminal_descriptor '=' 12 | '(' reject_limit_value ( ',' error_limit_value )? ')' ; 13 | error_limit_value : limit_value ; 14 | reject_limit_value : limit_value ; 15 | limit_value : constant_mintypmax_expression ; 16 | variable_decl_assignment : variable_identifier ( variable_dimension )* ( '=' expression )? 17 | | dynamic_array_variable_identifier unsized_dimension ( variable_dimension )* ( '=' dynamic_array_new )? 18 | | class_variable_identifier ( '=' class_new )? ; 19 | class_new : ( class_scope )? 'new' ( '(' list_of_arguments ')' )? 20 | | 'new' expression ; 21 | dynamic_array_new : 'new' '[' expression ']' ( '(' expression ')' )? ; 22 | -------------------------------------------------------------------------------- /verilog-examples/environment.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------------------------------- 4 | `include "transaction.sv" 5 | `include "generator.sv" 6 | `include "driver.sv" 7 | class environment; 8 | 9 | //generator and driver instance 10 | generator gen; 11 | driver driv; 12 | 13 | //mailbox handle's 14 | mailbox gen2driv; 15 | 16 | //virtual interface 17 | virtual intf vif; 18 | automatic a b; 19 | 20 | //constructor 21 | function new(virtual intf vif); 22 | //get the interface from test 23 | this.vif = vif; 24 | 25 | //creating the mailbox (Same handle will be shared across generator and driver) 26 | gen2driv = new(); 27 | 28 | //creating generator and driver 29 | gen = new(gen2driv); 30 | driv = new(vif,gen2driv); 31 | endfunction 32 | 33 | // 34 | task pre_test(); 35 | driv.reset(); 36 | endtask 37 | 38 | task test(); 39 | fork 40 | gen.main(); 41 | driv.main(); 42 | join_any 43 | endtask 44 | 45 | task post_test(); 46 | wait(gen.ended.triggered); 47 | wait(gen.repeat_count == driv.no_transactions); 48 | endtask 49 | 50 | driver another_driver; 51 | 52 | //run task 53 | task run; 54 | pre_test(); 55 | test(); 56 | post_test(); 57 | $finish; 58 | endtask 59 | 60 | endclass -------------------------------------------------------------------------------- /verilog-examples/directed_test.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------------------------------- 4 | `include "environment.sv" 5 | program automatic test(intf i_intf); 6 | 7 | class my_trans extends transaction; 8 | 9 | bit [1:0] count, test; 10 | 11 | function void pre_randomize(); 12 | a.rand_mode(0); 13 | b.rand_mode(0); 14 | 15 | a = 10; 16 | b = 12; 17 | endfunction 18 | 19 | endclass 20 | 21 | //declaring environment instance 22 | environment env; 23 | my_trans my_tr; 24 | 25 | initial begin 26 | //creating environment 27 | env = new(i_intf); 28 | 29 | my_tr = new(); 30 | 31 | //setting the repeat count of generator as 4, means to generate 4 packets 32 | env.gen.repeat_count = 10; 33 | 34 | env.gen.trans = my_tr; 35 | 36 | //calling run of env, it interns calls generator and driver main tasks. 37 | env.run(); 38 | 39 | // Unique case colorization test 40 | typedef enum [2:0] {A,B,C,D,e,f} state_e; 41 | 42 | begin a(); 43 | 44 | always_ff @(posedge ck, posedge arst) begin 45 | if (arst) 46 | cal_counter <= '0; 47 | else begin 48 | unique case(current_state_r) 49 | A: // ... 50 | B: // ... 51 | endcase 52 | end 53 | end 54 | 55 | 56 | end 57 | endprogram -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/TimingControlStatements.g4: -------------------------------------------------------------------------------- 1 | grammar TimingControlStatements; 2 | import ConditionalStatements; 3 | 4 | procedural_timing_control_statement : procedural_timing_control statement_or_null ; 5 | delay_or_event_control : delay_control | event_control | 'repeat' '(' expression ')' event_control ; 6 | delay_control : '#' delay_value | '#' '(' mintypmax_expression ')' ; 7 | event_control : '@' hierarchical_event_identifier 8 | | '@' '(' event_expression ')' 9 | | '@*' 10 | | '@' '(*)' 11 | | '@' ps_or_hierarchical_sequence_identifier ; 12 | event_expression : ( edge_identifier )? expression ( 'iff' expression )? 13 | | sequence_instance ( 'iff' expression )? 14 | | event_expression 'or' event_expression 15 | | event_expression ',' event_expression 16 | | '(' event_expression ')' ; 17 | procedural_timing_control : delay_control | event_control | cycle_delay ; 18 | jump_statement : 'return' ( expression )? ';' 19 | | 'break' ';' 20 | | 'continue' ';' ; 21 | wait_statement : 'wait' '(' expression ')' statement_or_null 22 | | 'wait' 'fork' ';' 23 | | 'wait_order' '(' hierarchical_identifier ( ',' hierarchical_identifier )* ')' action_block ; 24 | event_trigger : '->' hierarchical_event_identifier ';' 25 | | '->>' ( delay_or_event_control )? hierarchical_event_identifier ';' ; 26 | disable_statement : 'disable' hierarchical_task_identifier ';' 27 | | 'disable' hierarchical_block_identifier ';' 28 | | 'disable' 'fork' ';' ; 29 | -------------------------------------------------------------------------------- /verilog-examples/instantiation_example.sv: -------------------------------------------------------------------------------- 1 | // ------------------------------------------------------- 2 | // -- Example without parameters 3 | // ------------------------------------------------------- 4 | module adder( 5 | input clk, 6 | input reset, 7 | // Some comment here 8 | input [3:0] a, 9 | input [3:0] b, 10 | input valid, 11 | output [6:0] c 12 | ); 13 | 14 | // ------------------------------------------------------- 15 | 16 | adder u_adder ( 17 | .clk (clk), 18 | .reset (reset), 19 | // Some comment here 20 | .a (a), 21 | .b (b), 22 | .valid (valid), 23 | .c (c) 24 | ); 25 | 26 | 27 | 28 | 29 | // ------------------------------------------------------- 30 | // -- Example with parameters 31 | // ------------------------------------------------------- 32 | 33 | module adder #( 34 | parameter SIZE, 35 | parameter SIZE_TWO, 36 | )( 37 | input clk, 38 | input reset, 39 | // Some comment here 40 | input [3:0] a, 41 | input [3:0] b, 42 | input valid, 43 | output [6:0] c 44 | ); 45 | 46 | // ------------------------------------------------------- 47 | 48 | adder #( 49 | .SIZE (SIZE), 50 | .SIZE_TWO (SIZE_TWO), 51 | ) u_adder ( 52 | .clk (clk), 53 | .reset (reset), 54 | // Some comment here 55 | .a (a), 56 | .b (b), 57 | .valid (valid), 58 | .c (c) 59 | ); 60 | 61 | 62 | 63 | -------------------------------------------------------------------------------- /verilog-examples/cover_example.sv: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // Copyright (c) 2015, ChipVerify 3 | //----------------------------------------------------------------------------- 4 | // Author : Admin 5 | // Email : info@chipverify.com 6 | // Description : A basic class based functional coverage using sample () 7 | //----------------------------------------------------------------------------- 8 | 9 | class packet; 10 | 11 | rand bit [7:0] data; 12 | constraint c_data {data > 8'h30; data <8'h40; } 13 | 14 | covergroup cg; 15 | coverpoint data { 16 | bins low_th = {8'h30}; 17 | bins high_th = {8'h40}; 18 | bins low [] = {[8'h31:8'h39]}; 19 | } 20 | endgroup 21 | 22 | function display (); 23 | $display ("%0t, data = 0x%0h", $time, data); 24 | endfunction 25 | endclass 26 | 27 | module cov_101; 28 | 29 | bit clk; 30 | 31 | always #10 clk <= ~clk; 32 | 33 | packet pkt = new (); 34 | 35 | initial begin 36 | $display ("------------Start Test-------------"); 37 | repeat (10) @ (posedge clk) begin 38 | pkt.randomize (); 39 | pkt.display (); 40 | pkt.cg.sample (); 41 | end 42 | $display ("------------End Test-------------"); 43 | 44 | // Because of the clock that runs forever, we need to explicitly call $finish; 45 | $finish; 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/FunctionDeclarations.g4: -------------------------------------------------------------------------------- 1 | grammar FunctionDeclarations; 2 | import TaskDeclarations; 3 | 4 | function_data_type_or_implicit : data_type_or_void 5 | | implicit_data_type ; 6 | function_declaration : 'function' ( lifetime )? function_body_declaration ; 7 | function_body_declaration : function_data_type_or_implicit 8 | ( interface_identifier '.' | class_scope )? function_identifier ';' 9 | ( tf_item_declaration )* 10 | ( function_statement_or_null )* 11 | 'endfunction' ( ':' function_identifier )? 12 | | function_data_type_or_implicit 13 | ( interface_identifier '.' | class_scope )? function_identifier '(' ( tf_port_list )? ')' ';' 14 | ( block_item_declaration )* 15 | ( function_statement_or_null )* 16 | 'endfunction' ( ':' function_identifier )? ; 17 | function_prototype : 'function' data_type_or_void function_identifier ( '(' ( tf_port_list )? ')' )? ; 18 | dpi_import_export : 'import' dpi_spec_string ( dpi_function_import_property )? ( c_identifier '=' )? 19 | dpi_function_proto ';' 20 | | 'import' dpi_spec_string ( dpi_task_import_property )? ( c_identifier '=' )? dpi_task_proto ';' 21 | | 'export' dpi_spec_string ( c_identifier '=' )? 'function' function_identifier ';' 22 | | 'export' dpi_spec_string ( c_identifier '=' )? 'task' task_identifier ';' ; 23 | dpi_spec_string : '"DPI-C"' | '"DPI"' ; 24 | dpi_function_import_property : 'context' | 'pure' ; 25 | dpi_task_import_property : 'context' ; 26 | dpi_function_proto : function_prototype ; 27 | dpi_task_proto : task_prototype ; 28 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Constraints.g4: -------------------------------------------------------------------------------- 1 | grammar Constraints; 2 | import PackageItems; 3 | 4 | constraint_declaration : ( 'static' )? 'constraint' constraint_identifier constraint_block ; 5 | constraint_block : '{' ( constraint_block_item )* '}' ; 6 | constraint_block_item : 'solve' solve_before_list 'before' solve_before_list ';' 7 | | constraint_expression ; 8 | solve_before_list : constraint_primary ( ',' constraint_primary )* ; 9 | constraint_primary : ( implicit_class_handle '.' | class_scope )? hierarchical_identifier select ; 10 | constraint_expression : ( 'soft' )? expression_or_dist ';' 11 | | uniqueness_constraint ';' 12 | | expression '–>' constraint_set 13 | | 'if' '(' expression ')' constraint_set ( 'else' constraint_set )? 14 | | 'foreach' '(' ps_or_hierarchical_array_identifier '[' loop_variables ']' ')' constraint_set 15 | | 'disable' 'soft' constraint_primary ';' ; 16 | uniqueness_constraint : 'unique' '{' open_range_list '}' ; 17 | constraint_set : constraint_expression 18 | | '{' ( constraint_expression )* '}' ; 19 | dist_list : dist_item ( ',' dist_item )* ; 20 | dist_item : value_range ( dist_weight )? ; 21 | dist_weight : ':=' expression | ':/' expression ; 22 | constraint_prototype : ( constraint_prototype_qualifier )? ( 'static' )? 'constraint' 23 | constraint_identifier ';' ; 24 | constraint_prototype_qualifier : 'extern' | 'pure' ; 25 | extern_constraint_declaration : ( 'static' )? 'constraint' class_scope constraint_identifier 26 | constraint_block ; 27 | identifier_list : identifier ( ',' identifier )* ; 28 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/DeclarationLists.g4: -------------------------------------------------------------------------------- 1 | grammar DeclarationLists; 2 | import DeclarationAssignments; 3 | 4 | list_of_defparam_assignments : defparam_assignment ( ',' defparam_assignment )* ; 5 | list_of_genvar_identifiers : genvar_identifier ( ',' genvar_identifier )* ; 6 | list_of_interface_identifiers : interface_identifier ( unpacked_dimension )* 7 | ( ',' interface_identifier ( unpacked_dimension )* )* ; 8 | list_of_net_decl_assignments : net_decl_assignment ( ',' net_decl_assignment )* ; 9 | list_of_param_assignments : param_assignment ( ',' param_assignment )* ; 10 | list_of_port_identifiers : port_identifier ( unpacked_dimension )* 11 | ( ',' port_identifier ( unpacked_dimension )* )* ; 12 | list_of_udp_port_identifiers : port_identifier ( ',' port_identifier )* ; 13 | list_of_specparam_assignments : specparam_assignment ( ',' specparam_assignment )* ; 14 | list_of_tf_variable_identifiers : port_identifier ( variable_dimension )* ( '=' expression )? 15 | ( ',' port_identifier ( variable_dimension )* ( '=' expression )? )* ; 16 | list_of_type_assignments : type_assignment ( ',' type_assignment )* ; 17 | list_of_variable_decl_assignments : variable_decl_assignment ( ',' variable_decl_assignment )* ; 18 | list_of_variable_identifiers : variable_identifier ( variable_dimension )* 19 | ( ',' variable_identifier ( variable_dimension )* )* ; 20 | list_of_variable_port_identifiers : port_identifier ( variable_dimension )* ( '=' constant_expression )? 21 | ( ',' port_identifier ( variable_dimension )* ( '=' constant_expression )? )* ; 22 | -------------------------------------------------------------------------------- /src/test/index.ts: -------------------------------------------------------------------------------- 1 | // This file is providing the test runner to use when running extension tests. 2 | // By default the test runner in use is Mocha-based. 3 | 4 | import * as path from 'path'; 5 | import * as Mocha from 'mocha'; 6 | import * as glob from 'glob'; 7 | 8 | export function run(): Promise { 9 | // Create the Mocha test 10 | const mocha = new Mocha({ 11 | ui: 'tdd', 12 | color: true, 13 | reporter: 'mocha-multi-reporters', 14 | reporterOptions: { 15 | reporterEnabled: 'spec, xunit', 16 | xunitReporterOptions: { 17 | output: path.join(__dirname, '..', '..', 'results.xml') 18 | } 19 | } 20 | }); 21 | 22 | const testsRoot = path.resolve(__dirname, '.'); 23 | 24 | return new Promise((c, e) => { 25 | glob('**/**.test.js', { cwd: testsRoot }, (err, files) => { 26 | if (err) { 27 | return e(err); 28 | } 29 | 30 | // Add files to the test suite 31 | files.forEach((f) => mocha.addFile(path.resolve(testsRoot, f))); 32 | 33 | try { 34 | // Run the mocha test 35 | mocha.run((failures) => { 36 | if (failures > 0) { 37 | e(new Error(`${failures} tests failed.`)); 38 | } else { 39 | c(); 40 | } 41 | }); 42 | } catch (err) { 43 | e(err); 44 | } 45 | }); 46 | }); 47 | } 48 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/AssertionStatements.g4: -------------------------------------------------------------------------------- 1 | grammar AssertionStatements; 2 | import ClockingBlock; 3 | 4 | assertion_item : concurrent_assertion_item | deferred_immediate_assertion_item ; 5 | deferred_immediate_assertion_item : ( block_identifier ':' )? deferred_immediate_assertion_statement ; 6 | procedural_assertion_statement : concurrent_assertion_statement 7 | | immediate_assertion_statement 8 | | checker_instantiation ; 9 | immediate_assertion_statement : simple_immediate_assertion_statement 10 | | deferred_immediate_assertion_statement ; 11 | simple_immediate_assertion_statement : simple_immediate_assert_statement 12 | | simple_immediate_assume_statement 13 | | simple_immediate_cover_statement ; 14 | simple_immediate_assert_statement : 'assert' '(' expression ')' action_block ; 15 | simple_immediate_assume_statement : 'assume' '(' expression ')' action_block ; 16 | simple_immediate_cover_statement : 'cover' '(' expression ')' statement_or_null ; 17 | deferred_immediate_assertion_statement : deferred_immediate_assert_statement 18 | | deferred_immediate_assume_statement 19 | | deferred_immediate_cover_statement ; 20 | deferred_immediate_assert_statement : 'assert' '#0' '(' expression ')' action_block 21 | | 'assert' 'final' '(' expression ')' action_block ; 22 | deferred_immediate_assume_statement : 'assume' '#0' '(' expression ')' action_block 23 | | 'assume' 'final' '(' expression ')' action_block ; 24 | deferred_immediate_cover_statement : 'cover' '#0' '(' expression ')' statement_or_null 25 | | 'cover' 'final' '(' expression ')' statement_or_null ; 26 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Statements.g4: -------------------------------------------------------------------------------- 1 | grammar Statements; 2 | import TimingControlStatements; 3 | 4 | statement_or_null : statement | ( attribute_instance )* ';' ; 5 | statement : ( block_identifier ':' )? ( attribute_instance )* statement_item ; 6 | statement_item : blocking_assignment ';' 7 | | nonblocking_assignment ';' 8 | | procedural_continuous_assignment ';' 9 | | case_statement 10 | | conditional_statement 11 | | inc_or_dec_expression ';' 12 | | subroutine_call_statement 13 | | disable_statement 14 | | event_trigger 15 | | loop_statement 16 | | jump_statement 17 | | par_block 18 | | procedural_timing_control_statement 19 | | seq_block 20 | | wait_statement 21 | | procedural_assertion_statement 22 | | clocking_drive ';' 23 | | randsequence_statement 24 | | randcase_statement 25 | | expect_property_statement 26 | | display_tasks 27 | | monitor_tasks 28 | | timescale_compiler_directive 29 | | include_compiler_directive 30 | | simulation_control_task ; 31 | display_tasks : display_task_name ( '(' list_of_arguments_with_strings ')' )? ';' ; 32 | display_task_name : '$display' | '$displayb' | '$displayo' | '$displayh' 33 | | '$write' | '$writeb' | '$writeo' | '$writeh' ; 34 | monitor_tasks : monitor_task_name ( '(' list_of_arguments_with_strings ')' )? ';' 35 | | '$monitoron' ';' 36 | | '$monitoroff' ';' ; 37 | monitor_task_name : '$monitor' | '$monitorb' | '$monitoro' | '$monitorh' ; 38 | function_statement : statement ; 39 | function_statement_or_null : function_statement | ( attribute_instance )* ';' ; 40 | variable_identifier_list : variable_identifier ( ',' variable_identifier )* ; 41 | -------------------------------------------------------------------------------- /src/providers/HoverProvider.ts: -------------------------------------------------------------------------------- 1 | import { HoverProvider, TextDocument, Position, CancellationToken, ProviderResult, Hover, workspace, commands, Location } from 'vscode'; // prettier-ignore 2 | 3 | export class SystemVerilogHoverProvider implements HoverProvider { 4 | provideHover(document: TextDocument, position: Position, token: CancellationToken): ProviderResult { 5 | return new Promise((resolve, _reject) => { 6 | const lookupRange = document.getWordRangeAtPosition(position); 7 | 8 | if (!lookupRange) { 9 | return resolve(undefined); 10 | } 11 | 12 | resolve( 13 | commands 14 | .executeCommand('vscode.executeDefinitionProvider', document.uri, position, token) 15 | .then((loc: Location[]): Thenable => { 16 | if (loc.length === 0) { 17 | return undefined; 18 | } 19 | return workspace 20 | .openTextDocument(loc[0].uri) 21 | .then((doc) => doc.lineAt(loc[0].range.start.line).text.trim()); 22 | }) 23 | .then( 24 | (str: string): Hover => 25 | new Hover([ 26 | { 27 | language: 'systemverilog', 28 | value: str 29 | } 30 | ]) 31 | ) 32 | ); 33 | }); 34 | } 35 | } 36 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ClassItems.g4: -------------------------------------------------------------------------------- 1 | grammar ClassItems; 2 | import Constraints; 3 | 4 | class_item : ( attribute_instance )* class_property 5 | | ( attribute_instance )* class_method 6 | | ( attribute_instance )* class_constraint 7 | | ( attribute_instance )* class_declaration 8 | | ( attribute_instance )* covergroup_declaration 9 | | local_parameter_declaration ';' 10 | | parameter_declaration ';' 11 | | ';' ; 12 | class_property : ( property_qualifier )* data_declaration 13 | | 'const' ( class_item_qualifier )* data_type const_identifier ( '=' constant_expression )? ';' ; 14 | class_method : ( method_qualifier )* task_declaration 15 | | ( method_qualifier )* function_declaration 16 | | 'pure' 'virtual' ( class_item_qualifier )* method_prototype ';' 17 | | 'extern' ( method_qualifier )* method_prototype ';' 18 | | ( method_qualifier )* class_constructor_declaration 19 | | 'extern' ( method_qualifier )* class_constructor_prototype ; 20 | class_constructor_prototype : 'function' 'new' ( '(' ( tf_port_list )? ')' )? ';' ; 21 | class_constraint : constraint_prototype | constraint_declaration ; 22 | class_item_qualifier : 'static' | 'protected' | 'local' ; 23 | property_qualifier : random_qualifier | class_item_qualifier ; 24 | random_qualifier : 'rand' | 'randc' ; 25 | method_qualifier : ( 'pure' )? 'virtual' | class_item_qualifier ; 26 | method_prototype : task_prototype | function_prototype ; 27 | class_constructor_declaration : 'function' ( class_scope )? 'new' ( '(' ( tf_port_list )? ')' )? ';' 28 | ( block_item_declaration )* ( 'super' '.' 'new' ( '(' list_of_arguments ')' )? ';' )? 29 | ( function_statement_or_null )* 'endfunction' ( ':' 'new' )? ; 30 | -------------------------------------------------------------------------------- /.vscode/launch.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "0.2.0", 3 | "configurations": [ 4 | { 5 | "name": "Extension", 6 | "type": "extensionHost", 7 | "request": "launch", 8 | "runtimeExecutable": "${execPath}", 9 | "args": ["--disable-extensions", "--extensionDevelopmentPath=${workspaceRoot}"], 10 | "outFiles": ["${workspaceRoot}/dist/client/**/*.js"], 11 | "preLaunchTask": { 12 | "type": "npm", 13 | "script": "webpack:dev" 14 | } 15 | }, 16 | { 17 | "name": "Attach", 18 | "type": "node", 19 | "request": "attach", 20 | "port": 6009, 21 | "restart": true, 22 | "outFiles": ["${workspaceRoot}/dist/server/**/*.js"] 23 | }, 24 | { 25 | "name": "Extension Tests", 26 | "type": "extensionHost", 27 | "request": "launch", 28 | "runtimeExecutable": "${execPath}", 29 | "args": [ 30 | "--disable-extensions", 31 | "--extensionDevelopmentPath=${workspaceRoot}", 32 | "--extensionTestsPath=${workspaceRoot}/out/test/index", 33 | "${workspaceRoot}/verilog-examples" 34 | ], 35 | "outFiles": ["${workspaceRoot}/out/test/**/*.js"], 36 | "preLaunchTask": { 37 | "type": "npm", 38 | "script": "compile" 39 | } 40 | } 41 | ], 42 | "compounds": [ 43 | { 44 | "name": "Client + Server", 45 | "configurations": ["Extension", "Attach"] 46 | } 47 | ] 48 | } 49 | -------------------------------------------------------------------------------- /verilog-examples/testbench.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com testbench.sv 3 | //------------------------------------------------------------------------- 4 | //tbench_top or testbench top, this is the top most file, in which DUT(Design Under Test) and Verification environment are connected. 5 | //------------------------------------------------------------------------- 6 | 7 | //including interfcae and testcase files 8 | `include "interface.sv" 9 | 10 | //-------------------------[NOTE]--------------------------------- 11 | //Particular testcase can be run by uncommenting, and commenting the rest 12 | `include "random_test.sv" 13 | //`include "directed_test.sv" 14 | //---------------------------------------------------------------- 15 | 16 | module tbench_top; 17 | 18 | //clock and reset signal declaration 19 | bit clk; 20 | bit reset; 21 | 22 | //clock generation 23 | always #5 clk = ~clk; 24 | 25 | //reset Generation 26 | initial begin 27 | reset = 1; 28 | #5 reset =0; 29 | end 30 | 31 | 32 | //creatinng instance of interface, inorder to connect DUT and testcase 33 | intf i_intf(clk,reset); 34 | 35 | //Testcase instance, interface handle is passed to test as an argument 36 | test t1(i_intf); 37 | 38 | //DUT instance, interface signals are connected to the DUT ports 39 | adder DUT ( 40 | .clk(i_intf.clk), 41 | .reset(i_intf.reset), 42 | .a(i_intf.a), 43 | .b(i_intf.b), 44 | .valid(i_intf.valid), 45 | .c(i_intf.c) 46 | ); 47 | 48 | //enabling the wave dump 49 | initial begin 50 | $dumpfile("dump.vcd"); $dumpvars; 51 | end 52 | endmodule -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Numbers.g4: -------------------------------------------------------------------------------- 1 | grammar Numbers; 2 | import Strings; 3 | 4 | number : integral_number | real_number ; 5 | integral_number : decimal_number | octal_number | binary_number | hex_number ; 6 | decimal_number : unsigned_number 7 | | ( size )? decimal_base unsigned_number 8 | | ( size )? decimal_base x_digit ( UNDERSCORE )* 9 | | ( size )? decimal_base z_digit ( UNDERSCORE )* ; 10 | binary_number : ( size )? binary_base binary_value ; 11 | octal_number : ( size )? octal_base octal_value ; 12 | hex_number : ( size )? hex_base hex_value ; 13 | sign : '+' | '-' ; 14 | size : non_zero_unsigned_number ; 15 | non_zero_unsigned_number : non_zero_decimal_digit ( UNDERSCORE | decimal_digit )* ; 16 | real_number : fixed_point_number 17 | | unsigned_number ( '.' unsigned_number )? exp ( sign )? unsigned_number ; 18 | fixed_point_number : unsigned_number '.' unsigned_number ; 19 | exp : EXP ; 20 | unsigned_number : decimal_digit ( UNDERSCORE | decimal_digit )* ; 21 | binary_value : binary_digit ( UNDERSCORE | binary_digit )* ; 22 | octal_value : octal_digit ( UNDERSCORE | octal_digit )* ; 23 | hex_value : hex_digit ( UNDERSCORE | hex_digit )* ; 24 | decimal_base : DECIMAL_BASE ; 25 | binary_base : BINARY_BASE ; 26 | octal_base : OCTAL_BASE ; 27 | hex_base : HEX_BASE ; 28 | non_zero_decimal_digit : ONE | TWO | OCTAL_DIGIT | DECIMAL_DIGIT ; 29 | decimal_digit : ZERO | non_zero_decimal_digit ; 30 | binary_digit : x_digit | z_digit | ZERO | ONE ; 31 | octal_digit : binary_digit | TWO | OCTAL_DIGIT ; 32 | hex_digit : octal_digit | DECIMAL_DIGIT | HEX_DIGIT | B | F ; 33 | x_digit : X_DIGIT ; 34 | z_digit : Z_DIGIT | QUESTION ; 35 | unbased_unsized_literal : APOSTROPHE_ZERO | APOSTROPHE_ONE | APOSTROPHE_Z_OR_X ; 36 | -------------------------------------------------------------------------------- /.eslintrc.json: -------------------------------------------------------------------------------- 1 | { 2 | "parser": "@typescript-eslint/parser", 3 | "parserOptions": { 4 | "project": "tsconfig.json" 5 | }, 6 | "plugins": ["@typescript-eslint", "import"], 7 | "extends": [ 8 | "eslint:recommended", 9 | "airbnb-typescript/base", 10 | "plugin:import/recommended", 11 | "plugin:import/typescript", 12 | "plugin:prettier/recommended" 13 | ], 14 | "rules": { 15 | "no-plusplus": ["error", { "allowForLoopAfterthoughts": true }], 16 | "import/no-extraneous-dependencies": ["error", { "devDependencies": ["**/src/test/*.ts"] }], 17 | "import/no-unresolved": ["error", { "ignore": ["^vscode$"] }], 18 | "@typescript-eslint/indent": ["error", 4], 19 | "@typescript-eslint/no-empty-function": ["error", { "allow": ["arrowFunctions", "methods"] }], 20 | "@typescript-eslint/lines-between-class-members": ["error", "always", { "exceptAfterSingleLine": true }], 21 | "@typescript-eslint/no-shadow": ["error", { "allow": ["err"] }], 22 | "@typescript-eslint/no-use-before-define": ["error", { "functions": false, "classes": true, "variables": true }], 23 | "@typescript-eslint/no-unused-vars": ["error", { "varsIgnorePattern": "^_", "argsIgnorePattern": "^_" }], 24 | "@typescript-eslint/naming-convention": [ 25 | "error", 26 | { "selector": "variable", "format": ["camelCase", "PascalCase", "UPPER_CASE"], "leadingUnderscore": "allow" }, 27 | { "selector": "function", "format": ["camelCase", "PascalCase"] }, 28 | { "selector": "typeLike", "format": ["PascalCase"] } 29 | ] 30 | // "@typescript-eslint/no-explicit-any": "off" 31 | } 32 | } 33 | -------------------------------------------------------------------------------- /.github/workflows/test.yaml: -------------------------------------------------------------------------------- 1 | name: Test and QA 2 | on: 3 | push: 4 | branches: 5 | - 'master' 6 | pull_request: 7 | branches: 8 | - '**' 9 | 10 | jobs: 11 | test: 12 | strategy: 13 | fail-fast: false 14 | matrix: 15 | os: [macos-latest, ubuntu-latest, windows-latest] 16 | name: Run extension tests (Node.js 16 on ${{ matrix.os }}) 17 | runs-on: ${{ matrix.os }} 18 | steps: 19 | - name: Clone vscode-systemverilog 20 | uses: actions/checkout@v2 21 | - name: Setup Node.js 22 | uses: actions/setup-node@v2 23 | id: node 24 | with: 25 | node-version: '16' 26 | - name: Install NPM dependencies 27 | run: npm ci --production=false --unsafe-perm 28 | - name: Compile extension 29 | run: npm run compile 30 | - name: Create bundle 31 | run: npm run webpack 32 | - name: Run headless tests and collect coverage 33 | uses: GabrielBB/xvfb-action@v1 34 | with: 35 | run: npm run coverage 36 | working-directory: ./ 37 | options: '' 38 | - name: Verify files 39 | if: runner.os == 'Linux' 40 | run: ls -l dist/client/extension.js dist/server/server.js coverage/index.html 41 | qa: 42 | name: Run quality checks 43 | runs-on: ubuntu-latest 44 | steps: 45 | - name: Clone vscode-systemverilog 46 | uses: actions/checkout@v2 47 | - name: Install NPM dependencies 48 | run: npm ci --production=false --unsafe-perm 49 | - name: Compile ANTLR 50 | run: npm run compile:antlr4ts 51 | - name: Run ESLint 52 | run: npm run lint 53 | - name: Run Prettier 54 | run: npm run pretty:check 55 | -------------------------------------------------------------------------------- /resources/f_dark.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /resources/svh_dark.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /resources/svh_light.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /resources/vh_dark.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /resources/vh_light.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /resources/f_light.svg: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ModuleParametersAndPorts.g4: -------------------------------------------------------------------------------- 1 | grammar ModuleParametersAndPorts; 2 | import ModuleItems; 3 | 4 | parameter_port_list : '#' '(' list_of_param_assignments ( ',' parameter_port_declaration )* ')' 5 | | '#' '(' parameter_port_declaration ( ',' parameter_port_declaration )* ')' 6 | | '#' '(' ')' ; 7 | parameter_port_declaration : parameter_declaration 8 | | local_parameter_declaration 9 | | data_type list_of_param_assignments 10 | | 'type' list_of_type_assignments ; 11 | list_of_ports : '(' port ( ',' port )* ')' ; 12 | list_of_port_declarations : '(' ( ( attribute_instance )* ansi_port_declaration 13 | ( ',' ( attribute_instance )* ansi_port_declaration )* )? ')' ; 14 | port_declaration : ( attribute_instance )* inout_declaration 15 | | ( attribute_instance )* input_declaration 16 | | ( attribute_instance )* output_declaration 17 | | ( attribute_instance )* ref_declaration 18 | | ( attribute_instance )* interface_port_declaration ; 19 | port : ( port_expression )? 20 | | '.' port_identifier '(' ( port_expression )? ')' ; 21 | port_expression : port_reference 22 | | '{' port_reference ( ',' port_reference )* '}' ; 23 | port_reference : port_identifier constant_select ; 24 | port_direction : 'input' | 'output' | 'inout' | 'ref' ; 25 | net_port_header : ( port_direction )? net_port_type ; 26 | variable_port_header : ( port_direction )? variable_port_type ; 27 | interface_port_header : interface_identifier ( '.' modport_identifier )? 28 | | 'interface' ( '.' modport_identifier )? ; 29 | ansi_port_declaration : ( net_port_header | interface_port_header )? port_identifier ( unpacked_dimension )* 30 | ( '=' constant_expression )? 31 | | ( variable_port_header )? port_identifier ( variable_dimension )* ( '=' constant_expression )? 32 | | ( port_direction )? '.' port_identifier '(' ( expression )? ')' ; 33 | -------------------------------------------------------------------------------- /src/test/test-files/VCSCompiler.test/foo.stdout.txt: -------------------------------------------------------------------------------- 1 | Loading tools/cadence/xcelium/18.09.011 2 | Loading requirement: tools/cadence/license/2018.12 3 | Loading tools/realintent/versions/2018.A.p2 4 | Loading requirement: tools/realintent/license/2019.01 5 | Loading tools/mentor/questa/2019.1 6 | Loading requirement: tools/mentor/license/2019.01 7 | Chronologic VCS (TM) 8 | Version O-2018.09-SP2_Full64 -- Sat Aug 3 17:45:19 2019 9 | Copyright (c) 1991-2018 by Synopsys Inc. 10 | ALL RIGHTS RESERVED 11 | 12 | This program is proprietary and confidential information of Synopsys Inc. 13 | and may be used and disclosed only as authorized in a license agreement 14 | controlling such use and disclosure. 15 | 16 | Parsing design file 'FILEPATH_PLACEHOLDER' 17 | 18 | Error-[UTOPN] Unknown type or port name 19 | The type name 'soc_top_asserts' is unknown, or the identifier 20 | 'u_outermodule1' has not been listed as a port, or the declaration might 21 | represent an instance missing parentheses. 22 | "FILEPATH_PLACEHOLDER", 13 23 | Source info: soc_top_asserts u_outermodule1; 24 | 25 | 26 | Error-[UTOPN] Unknown type or port name 27 | The type name 'soc_top_assertsdd' is unknown, or the identifier 28 | 'u_outermsodule1f' has not been listed as a port, or the declaration might 29 | represent an instance missing parentheses. 30 | "FILEPATH_PLACEHOLDER", 14 31 | Source info: soc_top_assertsdd u_outermsodule1f; 32 | 33 | 34 | Error-[IND] Identifier not declared 35 | FILEPATH_PLACEHOLDER, 23 36 | Identifier 'en' has not been declared yet. If this error is not expected, 37 | please check if you have set `default_nettype to none. 38 | 39 | 40 | 41 | Error-[SE] Syntax error 42 | Following verilog source has syntax error : 43 | "FILEPATH_PLACEHOLDER", 23: 44 | token is 'endmodule' 45 | 46 | 4 errors 47 | CPU time: .692 seconds to compile -------------------------------------------------------------------------------- /verilog-examples/error_test.sv: -------------------------------------------------------------------------------- 1 | // hello 2 | module segdetect( CLOCK, RESET, C, Z ); 3 | input CLOCK, RESET, C; 4 | output Z; 5 | reg Z; 6 | reg [2:0] Sreg, Snext // State register and next state 7 | parameter [2:0] S0 = 3'b000, // Define the states 8 | S1 = 3'b001, 9 | S2 = 3'b010, 10 | S3 = 3'b011, 11 | S4 = 3'b100, 12 | S5 = 3'b101, 13 | S6 = 3'b111; 14 | 15 | always @ (posedge CLOCK or posedge RESET) // Create state memory 16 | if (RESET==1) Sreg <= S0; else Sreg <= Snext; 17 | 18 | always @ (C, Sreg) begin // Next-state logic 19 | case (Sreg) 20 | S0: if (C==0) Snext = S0; 21 | else Snext = S1; 22 | S1: if (C==0) Snext = S1; 23 | else Snext = S2; 24 | S2: if (C==0) Snext = S2; 25 | else Snext = S3; 26 | S3: if (C==0) Snext = S3; 27 | else Snext = S4; 28 | S4: if (C==0) Snext = S4; 29 | else Snext = S5; 30 | S5: if (C==0) Snext = S5; 31 | else Snext = S6; 32 | S6: if (C==0) Snext = S6; 33 | else Snext = S0; 34 | default Snext = S0; 35 | endcase 36 | end 37 | 38 | always @ (Sreg) // Output logic 39 | case (Sreg) 40 | S0, S1, S2, S3, S4: Z = 0; 41 | S5: if (C==0) Z = 1; 42 | else Z=0; 43 | default Z = 0; 44 | endcase 45 | endmodule 46 | 47 | module correct(my_input, my_output); 48 | input my_input; 49 | output my_output; 50 | wire my_output; 51 | always @ (my_input) begin 52 | my_output <= !my_input; 53 | end 54 | 55 | 56 | module correct2(my_input, my_output); 57 | input my_input; 58 | output my_output; 59 | wire my_output; 60 | always @ (my_input) begin 61 | my_output <= !my_input; 62 | end 63 | endmodule 64 | -------------------------------------------------------------------------------- /verilog-examples/segdetect.v: -------------------------------------------------------------------------------- 1 | // hello 2 | module segdetect( CLOCK, RESET, C, Z ); 3 | input CLOCK, RESET, C; 4 | output Z; 5 | reg Z; 6 | reg [2:0] Sreg, Snext; // State register and next state 7 | parameter [2:0] S0 = 3'b000, // Define the states 8 | S1 = 3'b001, 9 | S2 = 3'b010, 10 | S3 = 3'b011, 11 | S4 = 3'b100, 12 | S5 = 3'b101, 13 | S6 = 3'b111; 14 | 15 | always @ (posedge CLOCK or posedge RESET) // Create state memory 16 | if (RESET==1) Sreg <= S0; else Sreg <= Snext; 17 | 18 | always @ (C, Sreg) begin // Next-state logic 19 | randcase (Sreg) 20 | S0: if (C==0) Snext = S0; 21 | else Snext = S1; 22 | S1: if (C==0) Snext = S1; 23 | else Snext = S2; 24 | S2: if (C==0) Snext = S2; 25 | else Snext = S3; 26 | S3: if (C==0) Snext = S3; 27 | else Snext = S4; 28 | S4: if (C==0) Snext = S4; 29 | else Snext = S5; 30 | S5: if (C==0) Snext = S5; 31 | else Snext = S6; 32 | S6: if (C==0) Snext = S6; 33 | else Snext = S0; 34 | default Snext = S0; 35 | endcase 36 | end 37 | 38 | always @ (Sreg) // Output logic 39 | case (Sreg) 40 | S0, S1, S2, S3, S4: Z = 0; 41 | S5: if (C==0) Z = 1; 42 | else Z=0; 43 | default Z = 0; 44 | endcase 45 | endmodule 46 | 47 | module correct(my_input, my_output); 48 | input my_input; 49 | output my_output; 50 | wire my_output; 51 | always @ (my_input) begin 52 | my_output <= !my_input; 53 | end 54 | endmodule 55 | 56 | module correct2(my_input, my_output); 57 | input my_input; 58 | output my_output; 59 | wire my_output; 60 | always @ (my_input) begin 61 | my_output <= !my_input; 62 | end 63 | endmodule 64 | -------------------------------------------------------------------------------- /configs/systemVerilog.json: -------------------------------------------------------------------------------- 1 | { 2 | "comments": { 3 | "lineComment": "//", 4 | "blockComment": ["/*", "*/"] 5 | }, 6 | "brackets": [ 7 | ["{", "}"], 8 | ["[", "]"], 9 | ["(", ")"], 10 | ["begin", "end"], 11 | ["randcase", "endcase"], 12 | ["casex", "endcase"], 13 | ["casez", "endcase"], 14 | ["case", "endcase"], 15 | ["checker", "endchecker"], 16 | ["class", "endclass"], 17 | ["clocking", "endclocking"], 18 | ["config", "endconfig"], 19 | ["coverage", "endcoverage"], 20 | ["covergroup", "endgroup"], 21 | ["fork", "join"], 22 | ["fork", "join_any"], 23 | ["fork", "join_none"], 24 | ["function", "endfunction"], 25 | ["generate", "endgenerate"], 26 | ["interface", "endinterface"], 27 | ["macromodule", "endmodule"], 28 | ["module", "endmodule"], 29 | ["package", "endpackage"], 30 | ["primitive", "endprimitive"], 31 | ["program", "endprogram"], 32 | ["property", "endproperty"], 33 | ["specify", "endspecify"], 34 | ["sequence", "endsequence"], 35 | ["table", "endtable"], 36 | ["task", "endtask"] 37 | ], 38 | "autoClosingPairs": [ 39 | { "open": "(", "close": ")" }, 40 | { "open": "[", "close": "]" }, 41 | { "open": "{", "close": "}" }, 42 | { "open": "\"", "close": "\"", "notIn": ["string"] } 43 | ], 44 | "surroundingPairs": [ 45 | ["{", "}"], 46 | ["[", "]"], 47 | ["(", ")"], 48 | ["'", "'"], 49 | ["\"", "\""] 50 | ], 51 | "folding": { 52 | "markers": { 53 | "start": "^[ \\t\\n]*(?://[ \\t\\n]*#?region|`(?:ifdef|ifndef|elsif|else)\\b|\\b(?:(?:macro)?module|class)\\b)", 54 | "end": "^[ \\t\\n]*(?://[ \\t\\n]*#?endregion|`(?:elsif|else|endif)\\b|\\b(?:endmodule|endclass)\\b)" 55 | } 56 | } 57 | } 58 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/PrimitiveInstantiationAndInstances.g4: -------------------------------------------------------------------------------- 1 | grammar PrimitiveInstantiationAndInstances; 2 | import PrimitiveStrengths; 3 | 4 | gate_instantiation : cmos_switchtype ( delay3 )? cmos_switch_instance ( ',' cmos_switch_instance )* ';' 5 | | enable_gatetype ( drive_strength )? ( delay3 )? enable_gate_instance ( ',' enable_gate_instance )* ';' 6 | | mos_switchtype ( delay3 )? mos_switch_instance ( ',' mos_switch_instance )* ';' 7 | | n_input_gatetype ( drive_strength )? ( delay2 )? n_input_gate_instance 8 | ( ',' n_input_gate_instance )* ';' 9 | | n_output_gatetype ( drive_strength )? ( delay2 )? n_output_gate_instance 10 | ( ',' n_output_gate_instance )* ';' 11 | | pass_en_switchtype ( delay2 )? pass_enable_switch_instance ( ',' pass_enable_switch_instance )* ';' 12 | | pass_switchtype pass_switch_instance ( ',' pass_switch_instance )* ';' 13 | | 'pulldown' ( pulldown_strength )? pull_gate_instance ( ',' pull_gate_instance )* ';' 14 | | 'pullup' ( pullup_strength )? pull_gate_instance ( ',' pull_gate_instance )* ';' ; 15 | cmos_switch_instance : ( name_of_instance )? 16 | '(' output_terminal ',' input_terminal ',' ncontrol_terminal ',' pcontrol_terminal ')' ; 17 | enable_gate_instance : ( name_of_instance )? 18 | '(' output_terminal ',' input_terminal ',' enable_terminal ')' ; 19 | mos_switch_instance : ( name_of_instance )? 20 | '(' output_terminal ',' input_terminal ',' enable_terminal ')' ; 21 | n_input_gate_instance : ( name_of_instance )? 22 | '(' output_terminal ',' input_terminal ( ',' input_terminal )* ')' ; 23 | n_output_gate_instance : ( name_of_instance )? 24 | '(' output_terminal ( ',' output_terminal )* ',' input_terminal ')' ; 25 | pass_switch_instance : ( name_of_instance )? '(' inout_terminal ',' inout_terminal ')' ; pass_enable_switch_instance : ( name_of_instance )? 26 | '(' inout_terminal ',' inout_terminal ',' enable_terminal ')' ; 27 | pull_gate_instance : ( name_of_instance )? '(' output_terminal ')' ; 28 | -------------------------------------------------------------------------------- /syntaxes/verilog-filelist.json: -------------------------------------------------------------------------------- 1 | { 2 | "fileTypes": [ 3 | "f" 4 | ], 5 | "name": "verilog-filelist", 6 | "scopeName": "source.verilog-filelist", 7 | "patterns": [ 8 | { 9 | "match": "^\\s*//.*$", 10 | "name": "comment.line" 11 | }, 12 | { 13 | "match": "^\\s*#.*$", 14 | "name": "comment.line" 15 | }, 16 | { 17 | "match": "^\\s*-f\\s", 18 | "name": "keyword" 19 | }, 20 | { 21 | "match": "^\\s*-v\\s", 22 | "name": "keyword" 23 | }, 24 | { 25 | "match": "^\\s*-F\\s", 26 | "name": "keyword" 27 | }, 28 | { 29 | "match": "(\\$\\()(\\w*)(\\))", 30 | "captures": { 31 | "1": {"name": "variable.other.constant"}, 32 | "2": {"name": "variable"}, 33 | "3": {"name": "variable.other.constant"} 34 | } 35 | }, 36 | { 37 | "match": "(\\$\\{)(\\w*)(\\})", 38 | "captures": { 39 | "1": {"name": "variable.other.constant"}, 40 | "2": {"name": "variable"}, 41 | "3": {"name": "variable.other.constant"} 42 | } 43 | }, 44 | { 45 | "match": "\\+incdir\\+", 46 | "name": "entity.name.function" 47 | }, 48 | { 49 | "match": "\\-incdir\\s", 50 | "name": "entity.name.function" 51 | }, 52 | { 53 | "match": "(-define)\\s(.*)\\s*", 54 | "captures": { 55 | "1": {"name": "entity.name.type"}, 56 | "2": {"name": "variable.other.constant"} 57 | } 58 | }, 59 | { 60 | "match": "(\\+define\\+)\\s*(.*)\\s*", 61 | "captures": { 62 | "1": {"name": "entity.name.type"}, 63 | "2": {"name": "variable.other.constant"} 64 | } 65 | } 66 | ] 67 | } -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Instantiation.g4: -------------------------------------------------------------------------------- 1 | grammar Instantiation; 2 | import GeneratedInstantiation; 3 | 4 | module_instantiation : module_identifier ( parameter_value_assignment )? hierarchical_instance 5 | ( ',' hierarchical_instance )* ';' ; 6 | parameter_value_assignment : '#' '(' ( list_of_parameter_assignments )? ')' ; 7 | list_of_parameter_assignments : ordered_parameter_assignment ( ',' ordered_parameter_assignment )* 8 | | named_parameter_assignment ( ',' named_parameter_assignment )* ; 9 | ordered_parameter_assignment : param_expression ; 10 | named_parameter_assignment : '.' parameter_identifier '(' ( param_expression )? ')' ; 11 | hierarchical_instance : name_of_instance '(' ( list_of_port_connections )? ')' ; 12 | name_of_instance : instance_identifier ( unpacked_dimension )* ; 13 | list_of_port_connections : ordered_port_connection ( ',' ordered_port_connection )* 14 | | named_port_connection ( ',' named_port_connection )* ; 15 | ordered_port_connection : ( attribute_instance )* ( expression )? ; 16 | named_port_connection : ( attribute_instance )* '.' port_identifier ( '(' ( expression )? ')' )? 17 | | ( attribute_instance )* '.*' ; 18 | interface_instantiation : interface_identifier ( parameter_value_assignment )? hierarchical_instance 19 | ( ',' hierarchical_instance )* ';' ; 20 | program_instantiation : program_identifier ( parameter_value_assignment )? hierarchical_instance 21 | ( ',' hierarchical_instance )* ';' ; 22 | checker_instantiation : ps_checker_identifier name_of_instance 23 | '(' ( list_of_checker_port_connections )? ')' ';' ; 24 | list_of_checker_port_connections : ordered_checker_port_connection 25 | ( ',' ordered_checker_port_connection )* 26 | | named_checker_port_connection ( ',' named_checker_port_connection )* ; 27 | ordered_checker_port_connection : ( attribute_instance )* ( property_actual_arg )? ; 28 | named_checker_port_connection : ( attribute_instance )* '.' formal_port_identifier 29 | ( '(' ( property_actual_arg )? ')' )? 30 | | ( attribute_instance )* '.*' ; 31 | -------------------------------------------------------------------------------- /src/utils/common.ts: -------------------------------------------------------------------------------- 1 | import * as uriJs from 'uri-js'; 2 | import { Position, TextDocument } from 'vscode'; 3 | 4 | /** 5 | Get the indexs of the given regex in the given document 6 | 7 | @param uri the uri 8 | @param rootPath the root path 9 | @return the path 10 | */ 11 | export function regexGetIndexes(document: TextDocument, input: string, regex: RegExp, offset: number): Array { 12 | const indexes = []; 13 | let match: RegExpExecArray = null; 14 | while ((match = regex.exec(input)) !== null) { 15 | indexes.push(document.positionAt(match.index + offset)); 16 | } 17 | return indexes; 18 | } 19 | 20 | /** 21 | Get path from a given `uri` 22 | 23 | @param uri the uri 24 | @param rootPath the root path 25 | @return the path 26 | */ 27 | export function getPathFromUri(uri: string, rootPath: string): string { 28 | if (!uri || !rootPath) { 29 | return ''; 30 | } 31 | let matches; 32 | 33 | const lUri = decodeURIComponent(uri); // convert hexadecimal characters to ASCII 34 | // don't parse if it is a windows path starting with a single letter followed by a colon 35 | const dontParseUri = new RegExp(`^[a-zA-Z]:.*`); 36 | let parsedPath = null; 37 | let windowsPath = false; 38 | if ((matches = dontParseUri.exec(lUri)) !== null && matches.length === 1) { 39 | parsedPath = uri.replace(/\\/g, '/'); 40 | windowsPath = true; 41 | } else { 42 | const parsedUri = uriJs.parse(lUri); 43 | parsedPath = parsedUri.path; 44 | } 45 | if (!parsedPath) { 46 | return ''; 47 | } 48 | 49 | const lRootPath = rootPath.replace(/\\/g, '/'); 50 | const regex = new RegExp(`/?${lRootPath}(.*)`); 51 | if ((matches = regex.exec(parsedPath)) != null && matches.length > 1) { 52 | const foundPath = lRootPath + matches[1]; 53 | if (windowsPath) { 54 | return foundPath.replace(/\//g, '\\'); 55 | } 56 | return foundPath; 57 | } 58 | 59 | return ''; 60 | } 61 | -------------------------------------------------------------------------------- /src/utils/server.ts: -------------------------------------------------------------------------------- 1 | import { Range, Position } from 'vscode-languageserver/node'; 2 | import { TextDocument } from 'vscode-languageserver-textdocument'; 3 | 4 | /** 5 | Check if a given `document` is a SystemVerilog file. 6 | 7 | @param document the document to check 8 | @return true if the document is a SystemVerilog file 9 | */ 10 | export function isSystemVerilogDocument(document: TextDocument | undefined): boolean { 11 | return document?.languageId === 'systemverilog' || document?.languageId === 'systemverilogheader'; 12 | } 13 | 14 | /** 15 | Check if a given `document` is a Verilog file. 16 | 17 | @param document the document to check 18 | @return true if the document is a Verilog file 19 | */ 20 | export function isVerilogDocument(document: TextDocument | undefined): boolean { 21 | return document?.languageId === 'verilog' || document?.languageId === 'verilogheader'; 22 | } 23 | 24 | /** 25 | Check if a given `document` is a Verilog file. 26 | 27 | @param document the document to check 28 | @return true if the document is a Verilog file 29 | */ 30 | export function isVerilogAMSDocument(document: TextDocument | undefined): boolean { 31 | return document?.languageId === 'veriloga' || document?.languageId === 'verilogams'; 32 | } 33 | 34 | /** 35 | Gets the `range` of a line given the line number 36 | 37 | @param line the line number 38 | @return the line's range 39 | */ 40 | export function getLineRange(line: number, offendingSymbol: string, startPosition: number): Range { 41 | let endPosition: number; 42 | if (startPosition == null) { 43 | startPosition = 0; 44 | } 45 | if (offendingSymbol == null || offendingSymbol === undefined) { 46 | // When offendingSymbol is null, assume the error is marked to the end of the line 47 | endPosition = Number.MAX_VALUE; 48 | } else { 49 | endPosition = startPosition + offendingSymbol.length; 50 | } 51 | return Range.create(Position.create(line, startPosition), Position.create(line, endPosition)); 52 | } 53 | -------------------------------------------------------------------------------- /.vscode/tasks.json: -------------------------------------------------------------------------------- 1 | { 2 | "version": "2.0.0", 3 | "tasks": [ 4 | { 5 | "type": "npm", 6 | "script": "watch", 7 | "problemMatcher": "$tsc-watch", 8 | "isBackground": true, 9 | "presentation": { 10 | "reveal": "never", 11 | "panel": "dedicated" 12 | }, 13 | "group": { 14 | "kind": "build", 15 | "isDefault": true 16 | } 17 | }, 18 | { 19 | "type": "npm", 20 | "script": "compile", 21 | "isBackground": false, 22 | "group": "build", 23 | "presentation": { 24 | "reveal": "never", 25 | "panel": "dedicated" 26 | }, 27 | "problemMatcher": ["$tsc"] 28 | }, 29 | { 30 | "label": "Verilator: Compile", 31 | "isBackground": true, 32 | // "runOptions": { 33 | // "runOn": "folderOpen", 34 | // "reevaluateOnRerun": true 35 | // }, 36 | "presentation": { 37 | "echo": true, 38 | "reveal": "always", 39 | "focus": false, 40 | "panel": "shared", 41 | "showReuseMessage": true, 42 | "clear": false 43 | }, 44 | "command": "wsl", 45 | "args": ["verilator", "-sv", "--language", "1800-2012", "--lint-only", "`wslpath", "'${relativeFile}'`"], 46 | "problemMatcher": { 47 | "owner": "systemverilog", 48 | "pattern": [ 49 | { 50 | "regexp": "^%([\\w-]+): ([\\w_\\./-]+):(\\d+):\\s+([\\w\\W]+)$", 51 | "severity": 1, 52 | "file": 2, 53 | "line": 3, 54 | "message": 4 55 | } 56 | ] 57 | }, 58 | "group": { 59 | "kind": "build", 60 | "isDefault": true 61 | } 62 | } 63 | ] 64 | } 65 | -------------------------------------------------------------------------------- /verilog-examples/ekv.va: -------------------------------------------------------------------------------- 1 | `include "std.va" 2 | `include "const.va" 3 | 4 | // **************************************************************** 5 | // * EKV MOS model (long channel) based on version 2.6 rev.15 6 | // * Function name : ekv26_dc_long for verilog-a implementation 7 | // * The model documetation: http://legwww.epfl.ch/ekv 8 | // **************************************************************** 9 | 10 | module ekv(d,g,s,b); 11 | // 12 | // Node definitions 13 | // 14 | inout d,g,s,b ; // external nodes 15 | electrical d,g,s,b ; // external nodes 16 | // 17 | //*** Local variables 18 | // 19 | real x, VG, VS, VD, VGprime, VP; 20 | real beta, n, iff, ir, Ispec, Id; 21 | // 22 | //*** model parameter definitions 23 | // 24 | parameter real L = 10E-6 from[0.0:inf]; 25 | parameter real W = 10E-6 from[0.0:inf]; 26 | 27 | //*** Threshold voltage 28 | // substrate effect parameters (long-channel) 29 | parameter real VTO = 0.5 from[0.0:inf]; 30 | parameter real GAMMA = 0.7 from[0.0:inf]; 31 | parameter real PHI = 0.5 from[0.2:inf]; 32 | 33 | //*** Mobility parameters (long-channel) 34 | parameter real KP = 20E-6 from[0.0:inf]; 35 | parameter real THETA = 50.0E-3 from[0.0:inf]; 36 | 37 | analog begin // EKV v2.6 long-channel 38 | 39 | VG = V(g, b); VS = V(s, b); VD = V(d, b); 40 | 41 | // Effective gate voltage (33) 42 | VGprime = VG - VTO + PHI + GAMMA * sqrt(PHI); 43 | 44 | // Pinch-off voltage (34) 45 | VP = VGprime - PHI - GAMMA 46 | * (sqrt(VGprime+(GAMMA/2.0)*(GAMMA/2.0))-(GAMMA/2.0)); 47 | 48 | // Slope factor (39) 49 | n = 1.0 + GAMMA / (2.0*sqrt(PHI + VP + 4.0*$vt)); 50 | 51 | // Mobility equation (58), (64) 52 | beta = KP * (W/L) * (1.0/(1.0 + THETA * VP)); 53 | 54 | // forward (44) and reverse (56) currents 55 | x=(VP-VS)/$vt; iff = (ln(1.0+exp( x /2.0)))*(ln(1.0+exp( x /2.0))); 56 | x=(VP-VD)/$vt; ir = (ln(1.0+exp( x /2.0)))*(ln(1.0+exp( x /2.0))); 57 | 58 | // Specific current (65) 59 | Ispec = 2 * n * beta * $vt * $vt; 60 | 61 | // Drain current (66) 62 | Id = Ispec * (iff - ir); 63 | 64 | // 65 | // Branch contributions to EKV v2.6 model (long-channel) 66 | // 67 | I(d,s) <+ Id; 68 | 69 | end // analog 70 | endmodule -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/LexRules.g4: -------------------------------------------------------------------------------- 1 | grammar LexRules; 2 | 3 | MACROMODULE : 'macromodule' ; 4 | MODULE : 'module' ; 5 | EXP : [eE] ; 6 | 7 | fragment APOSTROPHE_FRAG : ['] ; 8 | fragment S_FRAG : [sS] ; 9 | fragment D_FRAG : [dD] ; 10 | fragment B_FRAG : [bB] ; 11 | fragment O_FRAG : [oO] ; 12 | fragment H_FRAG : [hH] ; 13 | fragment Z_FRAG : [zZ] ; 14 | fragment X_FRAG : [xX] ; 15 | fragment ZERO_FRAG : [0] ; 16 | fragment ONE_FRAG : [1] ; 17 | 18 | DECIMAL_BASE : APOSTROPHE_FRAG S_FRAG? D_FRAG ; 19 | BINARY_BASE : APOSTROPHE_FRAG S_FRAG? B_FRAG ; 20 | OCTAL_BASE : APOSTROPHE_FRAG S_FRAG? O_FRAG ; 21 | HEX_BASE : APOSTROPHE_FRAG S_FRAG? H_FRAG ; 22 | APOSTROPHE_ZERO : APOSTROPHE_FRAG ZERO_FRAG ; 23 | APOSTROPHE_ONE : APOSTROPHE_FRAG ONE_FRAG ; 24 | APOSTROPHE_Z_OR_X : APOSTROPHE_FRAG ( Z_FRAG | X_FRAG ) ; 25 | ZERO : [0] ; 26 | ONE : [1] ; 27 | TWO : [2] ; 28 | OCTAL_DIGIT : [3-7] ; 29 | DECIMAL_DIGIT : [89] ; 30 | 31 | APOSTROPHE : ['] ; 32 | 33 | B : [bB] ; 34 | F : [fF] ; 35 | R : [rR] ; 36 | P : [pP] ; 37 | N : [nN] ; 38 | LOWER_S : [s] ; 39 | LOWER_MS : [m][s] ; 40 | LOWER_US : [u][s] ; 41 | LOWER_NS : [n][s] ; 42 | LOWER_PS : [p][s] ; 43 | LOWER_FS : [f][s] ; 44 | HEX_DIGIT : [a-fA-F] ; 45 | X_DIGIT : [xX] ; 46 | Z_DIGIT : [zZ] ; 47 | UNDERSCORE : [_] ; 48 | QUESTION : [?] ; 49 | 50 | C_IDENTIFIER : [a-zA-Z_] ( [a-zA-Z0-9_] )* ; 51 | SIMPLE_IDENTIFIER : [a-zA-Z_] ( [a-zA-Z0-9_$] )* ; 52 | SYSTEM_TF_IDENTIFIER : '$' [a-zA-Z0-9_$] ( [a-zA-Z0-9_$] )* ; 53 | 54 | ESCAPED_IDENTIFIER : '\\' ( ANY_PRINTABLE_ASCII_CHARACTER_EXCEPT_WHITE_SPACE )* ; 55 | 56 | SPACE : ' ' -> skip ; 57 | TAB : '\t' -> skip ; 58 | NEWLINE : '\r'? '\n' -> skip ; 59 | 60 | /* ANY_PRINTABLE_ASCII_CHARACTER_EXCEPT_WHITE_SPACE : [\u0021-\u007E] ; */ 61 | fragment ANY_PRINTABLE_ASCII_CHARACTER_EXCEPT_WHITE_SPACE : [\u0021-\u007E] ; 62 | 63 | /* ANY_ASCII_CHARACTER : [\u0000-\u007F] ; */ 64 | ANY_ASCII_CHARACTER : [\u0000-\u007F] ; 65 | 66 | ONE_LINE_COMMENT : '//' (~[\n])* '\n' -> skip ; 67 | BLOCK_COMMENT : '/*' .*? '*/' -> skip ; 68 | 69 | FILENAME : '<' [a-zA-Z0-9_./\\\-]+ '.' ('v' | 'sv' | 'svh' | 'vh' | 'sva' | 'svi' | 'svp' | 'svhp') '>' 70 | | '"' [a-zA-Z0-9_./\\\-]+ '.' ('v' | 'sv' | 'svh' | 'vh' | 'sva' | 'svi' | 'svp' | 'svhp') '"' 71 | | '"' [a-zA-Z0-9_/\\\-]+ '"' ; 72 | 73 | STRING_LITERAL : '"' (~["] | '\\"')* '"' ; 74 | -------------------------------------------------------------------------------- /src/test/utils.client.test.ts: -------------------------------------------------------------------------------- 1 | import * as assert from 'assert'; 2 | import * as path from 'path'; 3 | import { workspace, Uri } from 'vscode'; 4 | import { isSystemVerilogDocument, isVerilogDocument } from '../utils/client'; 5 | 6 | const testFolderLocation = '../../src/test'; 7 | 8 | suite('Utils Client Tests', () => { 9 | test('test #1: isSystemVerilogDocument', async () => { 10 | const svUri = Uri.file(path.join(__dirname, testFolderLocation, 'test-files', 'design.sv')); 11 | const vUri = Uri.file(path.join(__dirname, testFolderLocation, 'test-files', 'ModuleInstantiator.test.1.v')); 12 | const nonSVUri = Uri.file(path.join(__dirname, testFolderLocation, 'test-files', 'foo.txt')); 13 | 14 | const sVDocument = await workspace.openTextDocument(svUri); 15 | const vDocument = await workspace.openTextDocument(vUri); 16 | const nonSVDocument = await workspace.openTextDocument(nonSVUri); 17 | 18 | assert.strictEqual(true, isSystemVerilogDocument(sVDocument)); 19 | assert.strictEqual(false, isSystemVerilogDocument(vDocument)); 20 | assert.strictEqual(false, isSystemVerilogDocument(nonSVDocument)); 21 | 22 | // undefined/null document 23 | assert.strictEqual(false, isSystemVerilogDocument(undefined)); 24 | assert.strictEqual(false, isSystemVerilogDocument(null)); 25 | }); 26 | 27 | test('test #2: isVerilogDocument', async () => { 28 | const svUri = Uri.file(path.join(__dirname, testFolderLocation, 'test-files', 'design.sv')); 29 | const vUri = Uri.file(path.join(__dirname, testFolderLocation, 'test-files', 'ModuleInstantiator.test.1.v')); 30 | const nonSVUri = Uri.file(path.join(__dirname, testFolderLocation, 'test-files', 'foo.txt')); 31 | 32 | const sVDocument = await workspace.openTextDocument(svUri); 33 | const vDocument = await workspace.openTextDocument(vUri); 34 | const nonSVDocument = await workspace.openTextDocument(nonSVUri); 35 | 36 | assert.strictEqual(false, isVerilogDocument(sVDocument)); 37 | assert.strictEqual(true, isVerilogDocument(vDocument)); 38 | assert.strictEqual(false, isVerilogDocument(nonSVDocument)); 39 | 40 | // undefined/null document 41 | assert.strictEqual(false, isVerilogDocument(undefined)); 42 | assert.strictEqual(false, isVerilogDocument(null)); 43 | }); 44 | }); 45 | -------------------------------------------------------------------------------- /src/test/utils.common.test.ts: -------------------------------------------------------------------------------- 1 | import * as assert from 'assert'; 2 | import { getPathFromUri } from '../utils/common'; 3 | 4 | suite('Utils Common Tests', () => { 5 | test('test #1: getPathFromUri-file', async () => { 6 | const rootPath = 'c:/home/users/workspace'; 7 | const expectedPath = 'c:/home/users/workspace/directory/design.sv'; 8 | const uri = 'file:///c%3A/home/users/workspace/directory/design.sv'; 9 | 10 | assert.strictEqual(expectedPath, getPathFromUri(uri, rootPath)); 11 | }); 12 | 13 | test('test #2: getPathFromUri-windows', async () => { 14 | const rootPath = 'c:\\home\\users\\workspace'; 15 | const expectedPath = 'c:\\home\\users\\workspace\\directory\\design.sv'; 16 | const uri = 'c:\\home\\users\\workspace\\directory\\design.sv'; 17 | const got = getPathFromUri(uri, rootPath); 18 | assert.strictEqual(expectedPath, got); 19 | }); 20 | 21 | test('test #3: getPathFromUri-linux', async () => { 22 | const rootPath = '/home/users/workspace'; 23 | const expectedPath = '/home/users/workspace/directory/design.sv'; 24 | const uri = 'file:///home/users/workspace/directory/design.sv'; 25 | 26 | assert.strictEqual(expectedPath, getPathFromUri(uri, rootPath)); 27 | }); 28 | 29 | test('test #4: getPathFromUri-undef', async () => { 30 | // URI without a path 31 | assert.strictEqual('', getPathFromUri('file:///', '')); 32 | 33 | // undefined/null/empty document 34 | assert.strictEqual('', getPathFromUri('', '')); 35 | assert.strictEqual('', getPathFromUri(undefined, undefined)); 36 | assert.strictEqual('', getPathFromUri(null, null)); 37 | }); 38 | 39 | test('test #5: getPathFromUri-linux', async () => { 40 | const rootPath = '/home/users/workspace'; 41 | const expectedPath = '/home/users/workspace/directory/design.sv'; 42 | const uri = '/home/users/workspace/directory/design.sv'; 43 | 44 | assert.strictEqual(expectedPath, getPathFromUri(uri, rootPath)); 45 | }); 46 | 47 | test('test #6: getPathFromUri-linux', async () => { 48 | const rootPath = '/home/users/workspace'; 49 | const expectedPath = '/home/users/workspace'; 50 | const uri = '/home/users/workspace'; 51 | 52 | assert.strictEqual(expectedPath, getPathFromUri(uri, rootPath)); 53 | }); 54 | }); 55 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/ModuleItems.g4: -------------------------------------------------------------------------------- 1 | grammar ModuleItems; 2 | import ConfigurationSourceText; 3 | 4 | elaboration_system_task : '$fatal' ( '(' finish_number ( ',' list_of_arguments )? ')' )? ';' 5 | | '$error' ( '(' ( list_of_arguments )? ')' )? ';' 6 | | '$warning' ( '(' ( list_of_arguments )? ')' )? ';' 7 | | '$info' ( '(' ( list_of_arguments )? ')' )? ';' ; 8 | finish_number : ZERO | ONE | TWO ; 9 | module_common_item : module_or_generate_item_declaration 10 | | interface_instantiation 11 | | program_instantiation 12 | | assertion_item 13 | | bind_directive 14 | | continuous_assign 15 | | net_alias 16 | | initial_construct 17 | | final_construct 18 | | always_construct 19 | | loop_generate_construct 20 | | conditional_generate_construct 21 | | elaboration_system_task 22 | | simulation_control_task ; 23 | simulation_control_task : '$stop' ( '(' finish_number ')' )? ';' 24 | | '$finish' ( '(' finish_number ')' )? ';' 25 | | '$exit' ( '(' finish_number ')' )? ';' ; 26 | module_item : port_declaration ';' 27 | | non_port_module_item ; 28 | module_or_generate_item : ( attribute_instance )* parameter_override 29 | | ( attribute_instance )* gate_instantiation 30 | | ( attribute_instance )* udp_instantiation 31 | | ( attribute_instance )* module_instantiation 32 | | ( attribute_instance )* module_common_item ; 33 | module_or_generate_item_declaration : package_or_generate_item_declaration 34 | | genvar_declaration 35 | | clocking_declaration 36 | | 'default' 'clocking' clocking_identifier ';' 37 | | 'default' 'disable' 'iff' expression_or_dist ';' ; 38 | non_port_module_item : generate_region 39 | | module_or_generate_item 40 | | specify_block 41 | | ( attribute_instance )* specparam_declaration 42 | | program_declaration 43 | | module_declaration 44 | | interface_declaration 45 | | timeunits_declaration ; 46 | parameter_override : 'defparam' list_of_defparam_assignments ';' ; 47 | bind_directive : 'bind' bind_target_scope ( ':' bind_target_instance_list )? bind_instantiation ';' 48 | | 'bind' bind_target_instance bind_instantiation ';' ; 49 | bind_target_scope : module_identifier 50 | | interface_identifier ; 51 | bind_target_instance : hierarchical_identifier constant_bit_select ; 52 | bind_target_instance_list : bind_target_instance ( ',' bind_target_instance )* ; 53 | bind_instantiation : program_instantiation 54 | | module_instantiation 55 | | interface_instantiation 56 | | checker_instantiation ; 57 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/CaseStatements.g4: -------------------------------------------------------------------------------- 1 | grammar CaseStatements; 2 | import LoopingStatements; 3 | 4 | case_statement : ( unique_priority )? case_keyword '(' case_expression ')' case_item ( case_item )* 5 | 'endcase' 6 | | ( unique_priority )? case_keyword '(' case_expression ')' 'matches' case_pattern_item 7 | ( case_pattern_item )* 'endcase' 8 | | ( unique_priority )? 'case' '(' case_expression ')' 'inside' case_inside_item ( case_inside_item )* 9 | 'endcase' ; 10 | case_keyword : 'case' | 'casez' | 'casex' ; 11 | case_expression : expression ; 12 | case_item : case_item_expression ( ',' case_item_expression )* ':' statement_or_null 13 | | 'default' ( ':' )? statement_or_null ; 14 | case_pattern_item : pattern ( '&&&' expression )? ':' statement_or_null 15 | | 'default' ( ':' )? statement_or_null ; 16 | case_inside_item : open_range_list ':' statement_or_null | 'default' ( ':' )? statement_or_null ; 17 | case_item_expression : expression ; 18 | randcase_statement : 'randcase' randcase_item ( randcase_item )* 'endcase' ; 19 | randcase_item : expression ':' statement_or_null ; 20 | open_range_list : open_value_range ( ',' open_value_range )* ; 21 | open_value_range : value_range ; 22 | pattern : '.' variable_identifier 23 | | '.*' 24 | | constant_expression 25 | | 'tagged' member_identifier ( pattern )? 26 | | APOSTROPHE '{' pattern ( ',' pattern )* '}' 27 | | APOSTROPHE '{' member_identifier ':' pattern ( ',' member_identifier ':' pattern )* '}' ; 28 | assignment_pattern : APOSTROPHE '{' expression ( ',' expression )* '}' 29 | | APOSTROPHE '{' structure_pattern_key ':' expression ( ',' structure_pattern_key ':' expression )* '}' 30 | | APOSTROPHE '{' array_pattern_key ':' expression ( ',' array_pattern_key ':' expression )* '}' 31 | | APOSTROPHE '{' constant_expression '{' expression ( ',' expression )* '}' '}' ; 32 | structure_pattern_key : member_identifier | assignment_pattern_key ; 33 | array_pattern_key : constant_expression | assignment_pattern_key ; 34 | assignment_pattern_key : simple_type | 'default' ; 35 | assignment_pattern_expression : ( assignment_pattern_expression_type )? assignment_pattern ; 36 | assignment_pattern_expression_type : ps_type_identifier 37 | | ps_parameter_identifier 38 | | integer_atom_type 39 | | type_reference ; 40 | constant_assignment_pattern_expression : assignment_pattern_expression ; 41 | assignment_pattern_net_lvalue : APOSTROPHE '{' net_lvalue ( ',' net_lvalue )* '}' ; assignment_pattern_variable_lvalue : APOSTROPHE '{' variable_lvalue ( ',' variable_lvalue )* '}' ; 42 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/DeclarationTypes.g4: -------------------------------------------------------------------------------- 1 | grammar DeclarationTypes; 2 | import DeclarationDataTypes; 3 | 4 | local_parameter_declaration : 'localparam' data_type_or_implicit list_of_param_assignments 5 | | 'localparam' 'type' list_of_type_assignments ; 6 | parameter_declaration : 'parameter' data_type_or_implicit list_of_param_assignments 7 | | 'parameter' 'type' list_of_type_assignments ; 8 | specparam_declaration : 'specparam' ( packed_dimension )? list_of_specparam_assignments ';' ; 9 | inout_declaration : 'inout' net_port_type list_of_port_identifiers ; 10 | input_declaration : 'input' net_port_type list_of_port_identifiers 11 | | 'input' variable_port_type list_of_variable_identifiers ; 12 | output_declaration : 'output' net_port_type list_of_port_identifiers 13 | | 'output' variable_port_type list_of_variable_port_identifiers ; 14 | interface_port_declaration : interface_identifier list_of_interface_identifiers 15 | | interface_identifier '.' modport_identifier list_of_interface_identifiers ; 16 | ref_declaration : 'ref' variable_port_type list_of_variable_identifiers ; 17 | data_declaration : ( 'const' )? ( 'var' )? ( lifetime )? data_type_or_implicit 18 | list_of_variable_decl_assignments ';' 19 | | type_declaration 20 | | package_import_declaration 21 | | net_type_declaration ; 22 | package_import_declaration : 'import' package_import_item ( ',' package_import_item )* ';' ; 23 | package_import_item : package_identifier '::' identifier 24 | | package_identifier '::' '*' ; 25 | package_export_declaration : 'export' '*::*' ';' 26 | | 'export' package_import_item ( ',' package_import_item )* ';' ; 27 | genvar_declaration : 'genvar' list_of_genvar_identifiers ';' ; 28 | net_declaration : net_type ( drive_strength | charge_strength )? ( 'vectored' | 'scalared' )? 29 | data_type_or_implicit ( delay3 )? list_of_net_decl_assignments ';' 30 | | net_type_identifier ( delay_control )? list_of_net_decl_assignments ';' 31 | | 'interconnect' implicit_data_type ( '#' delay_value )? net_identifier ( unpacked_dimension )* 32 | ( ',' net_identifier ( unpacked_dimension )* )? ';' ; 33 | type_declaration : 'typedef' data_type type_identifier ( variable_dimension )* ';' 34 | | 'typedef' interface_instance_identifier constant_bit_select '.' type_identifier type_identifier ';' 35 | | 'typedef' ( 'enum' | 'struct' | 'union' | 'class' | 'interface' 'class' )? type_identifier ';' ; 36 | net_type_declaration : 'nettype' data_type net_type_identifier ( 'with' 37 | ( package_scope | class_scope )? tf_identifier )? ';' 38 | | 'nettype' ( package_scope | class_scope )? net_type_identifier net_type_identifier ';' ; 39 | lifetime : 'static' | 'automatic' ; 40 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Primaries.g4: -------------------------------------------------------------------------------- 1 | grammar Primaries; 2 | import ExpressionLeftsideValues; 3 | 4 | constant_primary : primary_literal 5 | | ps_parameter_identifier constant_select 6 | | specparam_identifier ( '[' constant_range_expression ']' )? 7 | | genvar_identifier 8 | | formal_port_identifier constant_select 9 | | ( package_scope | class_scope )? enum_identifier 10 | | constant_concatenation ( '[' constant_range_expression ']' )? 11 | | constant_multiple_concatenation ( '[' constant_range_expression ']' )? 12 | | subroutine_call 13 | | constant_let_expression 14 | | '(' constant_mintypmax_expression ')' 15 | | ( simple_type | signing | 'string' | 'const' ) APOSTROPHE '(' constant_expression ')' 16 | | constant_primary APOSTROPHE '(' constant_expression ')' 17 | | constant_assignment_pattern_expression 18 | | type_reference 19 | | 'null' ; 20 | primary : primary_literal 21 | | ( class_qualifier | package_scope )? hierarchical_identifier select 22 | | empty_unpacked_array_concatenation 23 | | concatenation ( '[' range_expression ']' )? 24 | | multiple_concatenation ( '[' range_expression ']' )? 25 | | function_subroutine_call 26 | | let_expression 27 | | '(' mintypmax_expression ')' 28 | | ( simple_type | constant_primary | signing | 'string' | 'const' ) APOSTROPHE '(' expression ')' 29 | | assignment_pattern_expression 30 | | streaming_concatenation 31 | | sequence_method_call 32 | | 'this' 33 | | '$' 34 | | 'null' ; 35 | module_path_primary : number 36 | | identifier 37 | | module_path_concatenation 38 | | module_path_multiple_concatenation 39 | | function_subroutine_call 40 | | '(' module_path_mintypmax_expression ')' ; 41 | class_qualifier : ( 'local' '::' )? ( implicit_class_handle '.' | class_scope )? ; 42 | range_expression : expression | part_select_range ; 43 | primary_literal : number | time_literal | unbased_unsized_literal | string_literal ; 44 | time_literal : unsigned_number time_unit | fixed_point_number time_unit ; 45 | time_unit : LOWER_S | LOWER_MS | LOWER_US | LOWER_NS | LOWER_PS | LOWER_FS ; 46 | implicit_class_handle : 'this' | 'super' | 'this' '.' 'super' ; 47 | bit_select : ( '[' expression ']' )* ; 48 | select : ( ( '.' member_identifier bit_select )* '.' member_identifier )? bit_select 49 | ( '[' part_select_range ']' )? ; 50 | nonrange_select : ( ( '.' member_identifier bit_select )* '.' member_identifier )? bit_select ; 51 | constant_bit_select : ( '[' constant_expression ']' )* ; 52 | constant_select : ( ( '.' member_identifier constant_bit_select )* '.' member_identifier )? 53 | constant_bit_select ( '[' constant_part_select_range ']' )? ; 54 | constant_let_expression : let_expression ; 55 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SpecifyPathDelays.g4: -------------------------------------------------------------------------------- 1 | grammar SpecifyPathDelays; 2 | import SystemTimingChecks; 3 | 4 | path_delay_value : list_of_path_delay_expressions | '(' list_of_path_delay_expressions ')' ; 5 | list_of_path_delay_expressions : t_path_delay_expression 6 | | trise_path_delay_expression ',' tfall_path_delay_expression 7 | | trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression 8 | | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ',' 9 | tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression 10 | | t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ',' 11 | tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ',' 12 | t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' 13 | tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression ; 14 | t_path_delay_expression : path_delay_expression ; 15 | trise_path_delay_expression : path_delay_expression ; 16 | tfall_path_delay_expression : path_delay_expression ; 17 | tz_path_delay_expression : path_delay_expression ; 18 | t01_path_delay_expression : path_delay_expression ; 19 | t10_path_delay_expression : path_delay_expression ; 20 | t0z_path_delay_expression : path_delay_expression ; 21 | tz1_path_delay_expression : path_delay_expression ; 22 | t1z_path_delay_expression : path_delay_expression ; 23 | tz0_path_delay_expression : path_delay_expression ; 24 | t0x_path_delay_expression : path_delay_expression ; 25 | tx1_path_delay_expression : path_delay_expression ; 26 | t1x_path_delay_expression : path_delay_expression ; 27 | tx0_path_delay_expression : path_delay_expression ; 28 | txz_path_delay_expression : path_delay_expression ; 29 | tzx_path_delay_expression : path_delay_expression ; 30 | path_delay_expression : constant_mintypmax_expression ; 31 | edge_sensitive_path_declaration : parallel_edge_sensitive_path_description '=' path_delay_value 32 | | full_edge_sensitive_path_description '=' path_delay_value ; 33 | parallel_edge_sensitive_path_description : 34 | '(' ( edge_identifier )? specify_input_terminal_descriptor ( polarity_operator )? '=>' 35 | '(' specify_output_terminal_descriptor ( polarity_operator )? ':' data_source_expression ')' ')' ; 36 | full_edge_sensitive_path_description : '(' ( edge_identifier )? list_of_path_inputs 37 | ( polarity_operator )? '*>' '(' list_of_path_outputs ( polarity_operator )? ':' 38 | data_source_expression ')' ')' ; 39 | data_source_expression : expression ; 40 | edge_identifier : 'posedge' | 'negedge' | 'edge' ; 41 | state_dependent_path_declaration : 'if' '(' module_path_expression ')' simple_path_declaration 42 | | 'if' '(' module_path_expression ')' edge_sensitive_path_declaration 43 | | 'ifnone' simple_path_declaration ; 44 | polarity_operator : '+' | '-' ; 45 | -------------------------------------------------------------------------------- /verilog-examples/driver.sv: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------------- 2 | // www.verificationguide.com 3 | //------------------------------------------------------------------------- 4 | //gets the packet from generator and drive the transaction paket items into interface (interface is connected to DUT, so the items driven into interface signal will get driven in to DUT) 5 | 6 | `define MY_MACRO HELP! :-) 7 | 8 | class driver; 9 | localparam P1 = pa_Package::PARAMETER; 10 | localparam P2 = pa_Package::PARAMETER2; 11 | 12 | pa_Package::my_dumb_struct a_struct; 13 | 14 | 15 | typedef struct packed 16 | { 17 | logic foo; 18 | logic bar; 19 | } my_dumb_struct; 20 | 21 | 22 | cov_101 cov_101(); 23 | a23 u_123(); 24 | abc u_abc(); 25 | 26 | //used to count the number of transactions 27 | int no_transactions; 28 | 29 | //creating virtual interface handle 30 | virtual intf vif; 31 | 32 | //creating mailbox handle 33 | mailbox gen2driv; 34 | 35 | //constructor 36 | function new(virtual intf vif,mailbox gen2driv); 37 | //getting the interface 38 | this.vif = vif; 39 | //getting the mailbox handles from environment 40 | this.gen2driv = gen2driv; 41 | endfunction 42 | 43 | //Reset task, Reset the Interface signals to default/initial values 44 | task reset; 45 | wait(vif.reset); 46 | $display("[ DRIVER ] ----- Reset Started -----"); 47 | vif.a <= 0; 48 | vif.b <= 0; 49 | vif.valid <= 0; 50 | wait(!vif.reset); 51 | $display("[ DRIVER ] ----- Reset Ended -----"); 52 | endtask 53 | 54 | //drivers the transaction items to interface signals 55 | task main; 56 | forever begin 57 | transaction trans; 58 | gen2driv.get(trans); 59 | @(posedge vif.clk); 60 | vif.valid <= 1; 61 | vif.a <= trans.a; 62 | vif.b <= trans.b; 63 | @(posedge vif.clk); 64 | vif.valid <= 0; 65 | trans.c = vif.c; 66 | @(posedge vif.clk); 67 | trans.display("[ Driver ]"); 68 | no_transactions++; 69 | end 70 | endtask 71 | 72 | endclass 73 | 74 | class typedef_test; 75 | typedef int unsigned uint_t; 76 | typedef logic [0:15] packed_array_t; 77 | 78 | typedef int unsigned uint_array[10]; 79 | typedef int unsigned uint_queue[$]; 80 | typedef int unsigned uint_dynamic_array[]; 81 | typedef int unsigned uint_associative_array[uint_t]; 82 | typedef int unsigned uint_array_2d[10][10]; 83 | typedef logic unpacked_array_t [10]; 84 | typedef logic [0:15] packed_unpacked_array_t [10]; 85 | 86 | // Working: 87 | uint_t number; 88 | packed_array_t packed_array; 89 | 90 | // Not working: 91 | uint_array array; 92 | uint_queue queue; 93 | uint_dynamic_array dynamic_array; 94 | uint_associative_array associative_array; 95 | uint_array_2d array_2d; 96 | unpacked_array_t unpacked_array; 97 | packed_unpacked_array_t packed_unpacked_array; 98 | endclass 99 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/Expressions.g4: -------------------------------------------------------------------------------- 1 | grammar Expressions; 2 | import Primaries; 3 | 4 | inc_or_dec_expression : inc_or_dec_operator ( attribute_instance )* variable_lvalue 5 | | variable_lvalue ( attribute_instance )* inc_or_dec_operator ; 6 | constant_expression : constant_primary 7 | | unary_operator ( attribute_instance )* constant_primary 8 | | constant_expression binary_operator ( attribute_instance )* constant_expression 9 | | constant_expression '?' ( attribute_instance )* constant_expression ':' constant_expression ; 10 | constant_mintypmax_expression : constant_expression 11 | | constant_expression ':' constant_expression ':' constant_expression ; 12 | constant_param_expression : constant_mintypmax_expression | data_type | '$' ; 13 | param_expression : mintypmax_expression | data_type | '$' ; 14 | constant_range_expression : constant_expression | constant_part_select_range ; 15 | constant_part_select_range : constant_range | constant_indexed_range ; 16 | constant_range : constant_expression ':' constant_expression ; 17 | constant_indexed_range : constant_expression '+:' constant_expression 18 | | constant_expression '-:' constant_expression ; 19 | string_or_expression : string_literal | expression ; 20 | expression : primary 21 | | unary_operator ( attribute_instance )* primary 22 | | inc_or_dec_expression 23 | | '(' operator_assignment ')' 24 | | expression binary_operator ( attribute_instance )* expression 25 | | expression ( '&&&' expression )* '?' ( attribute_instance )* expression ':' expression 26 | | expression ( '&&&' expression 'matches' pattern )* '?' ( attribute_instance )* expression ':' expression 27 | | expression 'matches' pattern ( '&&&' expression )* '?' ( attribute_instance )* expression ':' expression 28 | | expression 'matches' pattern ( '&&&' expression 'matches' pattern )* '?' ( attribute_instance )* expression ':' expression 29 | | expression 'inside' '{' open_range_list '}' 30 | | tagged_union_expression ; 31 | tagged_union_expression : 'tagged' member_identifier ( expression )? ; 32 | value_range : expression | '[' expression ':' expression ']' ; 33 | mintypmax_expression : expression | expression ':' expression ':' expression ; 34 | module_path_conditional_expression : module_path_expression '?' ( attribute_instance )* 35 | module_path_expression ':' module_path_expression ; 36 | module_path_expression : module_path_primary 37 | | unary_module_path_operator ( attribute_instance )* module_path_primary 38 | | module_path_expression binary_module_path_operator ( attribute_instance )* module_path_expression 39 | | module_path_expression '?' ( attribute_instance )* module_path_expression ':' module_path_expression ; 40 | module_path_mintypmax_expression : module_path_expression 41 | | module_path_expression ':' module_path_expression ':' module_path_expression ; 42 | part_select_range : constant_range | indexed_range ; 43 | indexed_range : expression '+:' constant_expression 44 | | expression '-:' constant_expression ; 45 | genvar_expression : constant_expression ; 46 | -------------------------------------------------------------------------------- /syntaxes/codeblock.json: -------------------------------------------------------------------------------- 1 | { 2 | "fileTypes": [], 3 | "scopeName": "markdown.verilog.codeblock", 4 | "injectionSelector": "L:text.html.markdown", 5 | "patterns": [ 6 | { 7 | "include": "#fenced_code_block_systemverilog" 8 | }, 9 | { 10 | "include": "#fenced_code_block_verilog" 11 | } 12 | ], 13 | "repository": { 14 | "fenced_code_block_systemverilog": { 15 | "begin": "(^|\\G)(\\s*)(`{3,}|~{3,})\\s*(?i:(sv|systemverilog)(\\s+[^`~]*)?$)", 16 | "name": "markup.fenced_code.block.markdown", 17 | "end": "(^|\\G)(\\2|\\s{0,3})(\\3)\\s*$", 18 | "beginCaptures": { 19 | "3": { 20 | "name": "punctuation.definition.markdown" 21 | }, 22 | "5": { 23 | "name": "fenced_code.block.language" 24 | }, 25 | "6": { 26 | "name": "fenced_code.block.language.attributes" 27 | } 28 | }, 29 | "endCaptures": { 30 | "3": { 31 | "name": "punctuation.definition.markdown" 32 | } 33 | }, 34 | "patterns": [ 35 | { 36 | "begin": "(^|\\G)(\\s*)(.*)", 37 | "while": "(^|\\G)(?!\\s*([`~]{3,})\\s*$)", 38 | "contentName": "meta.embedded.block.systemverilog", 39 | "patterns": [ 40 | { 41 | "include": "source.systemverilog" 42 | } 43 | ] 44 | } 45 | ] 46 | }, 47 | "fenced_code_block_verilog": { 48 | "begin": "(^|\\G)(\\s*)(`{3,}|~{3,})\\s*(?i:(v|verilog)(\\s+[^`~]*)?$)", 49 | "name": "markup.fenced_code.block.markdown", 50 | "end": "(^|\\G)(\\2|\\s{0,3})(\\3)\\s*$", 51 | "beginCaptures": { 52 | "3": { 53 | "name": "punctuation.definition.markdown" 54 | }, 55 | "5": { 56 | "name": "fenced_code.block.language" 57 | }, 58 | "6": { 59 | "name": "fenced_code.block.language.attributes" 60 | } 61 | }, 62 | "endCaptures": { 63 | "3": { 64 | "name": "punctuation.definition.markdown" 65 | } 66 | }, 67 | "patterns": [ 68 | { 69 | "begin": "(^|\\G)(\\s*)(.*)", 70 | "while": "(^|\\G)(?!\\s*([`~]{3,})\\s*$)", 71 | "contentName": "meta.embedded.block.verilog", 72 | "patterns": [ 73 | { 74 | "include": "source.systemverilog" 75 | } 76 | ] 77 | } 78 | ] 79 | } 80 | } 81 | } 82 | -------------------------------------------------------------------------------- /src/compiling/SystemVerilogCompiler.ts: -------------------------------------------------------------------------------- 1 | import { Connection, Diagnostic, TextDocuments } from 'vscode-languageserver/node'; 2 | import { TextDocument } from 'vscode-languageserver-textdocument'; 3 | import { DocumentCompiler } from './DocumentCompiler'; 4 | import { VerilatorCompiler } from './VerilatorCompiler'; 5 | import { VCSCompiler } from './VCSCompiler'; 6 | import { VeribleCompiler } from './VeribleCompiler'; 7 | 8 | /* defines supported simulators/compilers */ 9 | export enum CompilerType { 10 | Verilator = 1, 11 | VCS = 2, 12 | Verible = 3 13 | } 14 | 15 | /* 16 | SystemVerilog Compiler handles functionality for compiling documents using the supported simulators. 17 | Used by the LSP's `connection` to handle getting `Diagnostics` for `documents` 18 | */ 19 | export class SystemVerilogCompiler { 20 | compiler: DocumentCompiler; 21 | connection: Connection; 22 | documents: TextDocuments; 23 | workspaceRootPath: string; 24 | configurations: Map; 25 | compilerConfigurationsKeys: string[]; 26 | 27 | constructor( 28 | connection: Connection, 29 | documents: TextDocuments, 30 | workspaceRootPath: string, 31 | configurations: Map, 32 | compilerConfigurationsKeys: string[] 33 | ) { 34 | this.connection = connection; 35 | this.documents = documents; 36 | this.workspaceRootPath = workspaceRootPath; 37 | this.configurations = configurations; 38 | this.compilerConfigurationsKeys = compilerConfigurationsKeys; 39 | } 40 | 41 | /** 42 | Compiles the given `document` using the compiler/simulator specified by `type`. 43 | 44 | @returns a `Promise` of a map of entries mapping each uri to a `Diagnostic` array 45 | */ 46 | public async validateTextDocument(document: TextDocument, type: CompilerType): Promise> { 47 | if (type === CompilerType.Verilator) { 48 | this.compiler = new VerilatorCompiler( 49 | this.connection, 50 | this.documents, 51 | this.workspaceRootPath, 52 | this.configurations, 53 | this.compilerConfigurationsKeys 54 | ); 55 | } else if (type === CompilerType.VCS) { 56 | this.compiler = new VCSCompiler( 57 | this.connection, 58 | this.documents, 59 | this.workspaceRootPath, 60 | this.configurations, 61 | this.compilerConfigurationsKeys 62 | ); 63 | } else if (type === CompilerType.Verible) { 64 | this.compiler = new VeribleCompiler( 65 | this.connection, 66 | this.documents, 67 | this.workspaceRootPath, 68 | this.configurations, 69 | this.compilerConfigurationsKeys 70 | ); 71 | } else { 72 | this.connection.console.log(`SystemVerilog: '${type}' is an invalid compiler type.`); 73 | return; 74 | } 75 | 76 | return this.compiler.getTextDocumentDiagnostics(document); 77 | } 78 | } 79 | -------------------------------------------------------------------------------- /verilog-examples/varistor.vams: -------------------------------------------------------------------------------- 1 | // Varistor Model 2 | // Equations taken from "Modeling Varistors with PSpice: Simulation 3 | // Beats Trial and Error" by M. Holzer and W. Zapsky, found in 4 | // Compliance Engineering, May/June 1999. 5 | // http://www.ce-mag.com/archive/1999/mayjune/Holzer.html 6 | // Verilog-A translation by Geoffrey Coram, Analog Devices, Inc. 7 | // 8 | // Version 1a, 28 July 03 9 | // 10 | // Downloaded from The Designer's Guide (www.designers-guide.org). 11 | // Post any questions on www.designers-guide.org/Forum. 12 | // 13 | // The constitutive equation in the paper is applied for I > Imin 14 | // and reflected for I < -Imin. A simple linear interpolation is 15 | // used between (Imin,V(Imin)) and (-Imin,V(-Imin)). 16 | // 17 | // Note that these equations use LOG10 instead of LN (natural log); 18 | // this was required to match Figure 2 in the paper, though one 19 | // might have expected LN to go with the exponentials. 20 | // Also, the paper mentions in a 100uOhm series resistor, but I don't 21 | // understand its purpose. You may set R=0 in this formulation. 22 | 23 | `include "disciplines.vams" 24 | `include "constants.vams" 25 | 26 | module varistor(p, n); 27 | inout p, n; 28 | electrical p, n; 29 | electrical pi, mid; 30 | branch (p,pi) br_rseries; 31 | branch (pi,mid) br_lseries; 32 | branch (mid,n) br_cparallel; 33 | branch (mid,n) br_nonlin; 34 | 35 | parameter real R = 100u from [0:inf); 36 | parameter real T = 1.0 from (0:inf); 37 | parameter real C = 1.0e-12 from (0:inf); 38 | parameter real L = 1.0e-9 from (0:inf); 39 | parameter real B1 = 1.0 from (0:inf); 40 | parameter real B2 = 1.0 from (0:inf); 41 | parameter real B3 = 0.0 from (-inf:inf); 42 | parameter real B4 = 0.0 from (0:inf); 43 | parameter real Imax = 1.0e7 from (0:inf); 44 | parameter real Imin = 1.0e-7 from (0:inf); 45 | 46 | analog function real powlogV; 47 | input logibr, B1, B2, B3, B4; 48 | real logibr, B1, B2, B3, B4; 49 | 50 | powlogV = pow(10.0,B1 + B2*(logibr) + B3*exp(-logibr) + B4*exp(logibr)); 51 | endfunction 52 | 53 | analog begin : the_module 54 | real ibranch, logibr, vbranch, rlin; 55 | 56 | // series resistance (may be 0) 57 | V(br_rseries) <+ R * I(br_rseries); 58 | 59 | // series inductance 60 | V(br_lseries) <+ L * ddt(I(br_lseries)); 61 | 62 | // parallel capacitance 63 | I(br_cparallel) <+ C * ddt(V(br_cparallel)); 64 | 65 | // nonlinear branch 66 | ibranch = I(br_nonlin); 67 | if (ibranch > Imin) begin 68 | logibr = log(ibranch); 69 | vbranch = powlogV(logibr,B1,B2,B3,B4); 70 | end else if (ibranch < -Imin) begin 71 | logibr = log(-ibranch); 72 | vbranch = -powlogV(logibr,B1,B2,B3,B4); 73 | end else begin 74 | // linear interpolation for -Imin < I < Imin 75 | logibr = log(Imin); 76 | rlin = powlogV(logibr,B1,B2,B3,B4)/Imin; 77 | vbranch = rlin * ibranch; 78 | end 79 | V(br_nonlin) <+ T * vbranch; 80 | 81 | // check maximum current 82 | @(cross(abs(ibranch)-Imax, +1)) 83 | $strobe("Varistor current exceeds Imax."); 84 | 85 | if (analysis("static") && abs(ibranch) > Imax) 86 | $strobe("Varistor current exceeds Imax."); 87 | 88 | end 89 | endmodule -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/DeclarationDataTypes.g4: -------------------------------------------------------------------------------- 1 | grammar DeclarationDataTypes; 2 | import DeclarationLists; 3 | 4 | data_type : integer_vector_type ( signing )? ( packed_dimension )* 5 | | integer_atom_type ( signing )? 6 | | non_integer_type 7 | | struct_union ( 'packed' ( signing )? )? '{' struct_union_member ( struct_union_member )* '}' 8 | ( packed_dimension )* 9 | | 'enum' ( enum_base_type )? '{' enum_name_declaration ( ',' enum_name_declaration )* '}' 10 | ( packed_dimension )* 11 | | 'string' 12 | | 'chandle' 13 | | 'virtual' ( 'interface' )? interface_identifier ( parameter_value_assignment )? 14 | ( '.' modport_identifier )? 15 | | ( class_scope | package_scope )? type_identifier ( packed_dimension )* 16 | | class_type 17 | | 'event' 18 | | ps_covergroup_identifier 19 | | type_reference ; 20 | data_type_or_implicit : data_type | implicit_data_type ; 21 | implicit_data_type : ( signing )? ( packed_dimension )* ; 22 | enum_base_type : integer_atom_type ( signing )? 23 | | integer_vector_type ( signing )? ( packed_dimension )? 24 | | type_identifier ( packed_dimension )? ; 25 | enum_name_declaration : enum_identifier ( '[' integral_number ( ':' integral_number )? ']' )? 26 | ( '=' constant_expression )? ; 27 | class_scope : class_type '::' ; 28 | class_type : ps_class_identifier ( parameter_value_assignment )? 29 | ( '::' class_identifier ( parameter_value_assignment )? )* ; 30 | integer_type : integer_vector_type | integer_atom_type ; 31 | integer_atom_type : 'byte' | 'shortint' | 'int' | 'longint' | 'integer' | 'time' ; 32 | integer_vector_type : 'bit' | 'logic' | 'reg' ; 33 | non_integer_type : 'shortreal' | 'real' | 'realtime' ; 34 | net_type : 'supply0' | 'supply1' | 'tri' | 'triand' | 'trior' | 'trireg' | 'tri0' | 'tri1' | 'uwire' 35 | | 'wire' | 'wand' | 'wor' ; 36 | net_port_type : ( net_type )? data_type_or_implicit 37 | | net_type_identifier 38 | | 'interconnect' implicit_data_type ; 39 | variable_port_type : var_data_type ; 40 | var_data_type : data_type | 'var' data_type_or_implicit ; 41 | signing : 'signed' | 'unsigned' ; 42 | simple_type : integer_type | non_integer_type | ps_type_identifier | ps_parameter_identifier ; 43 | struct_union_member : ( attribute_instance )* ( random_qualifier )? data_type_or_void 44 | list_of_variable_decl_assignments ';' ; 45 | data_type_or_void : data_type | 'void' ; 46 | struct_union : 'struct' | 'union' ( 'tagged' )? ; 47 | type_reference : 'type' '(' expression ')' | 'type' '(' data_type ')' ; 48 | drive_strength : '(' strength0 ',' strength1 ')' 49 | | '(' strength1 ',' strength0 ')' 50 | | '(' strength0 ',' 'highz1' ')' 51 | | '(' strength1 ',' 'highz0' ')' 52 | | '(' 'highz0' ',' strength1 ')' 53 | | '(' 'highz1' ',' strength0 ')' ; 54 | strength0 : 'supply0' | 'strong0' | 'pull0' | 'weak0' ; 55 | strength1 : 'supply1' | 'strong1' | 'pull1' | 'weak1' ; 56 | charge_strength : '(' 'small' ')' | '(' 'medium' ')' | '(' 'large' ')' ; 57 | delay3 : '#' delay_value | '#' '(' mintypmax_expression ( ',' mintypmax_expression 58 | ( ',' mintypmax_expression )? )? ')' ; 59 | delay2 : '#' delay_value | '#' '(' mintypmax_expression ( ',' mintypmax_expression )? ')' ; 60 | delay_value : unsigned_number | real_number | ps_identifier | time_literal | '1step' ; 61 | -------------------------------------------------------------------------------- /src/wip/TreeDataProvider.ts: -------------------------------------------------------------------------------- 1 | import { TreeDataProvider, TreeItem, EventEmitter, Event, TreeItemCollapsibleState, window } from 'vscode'; 2 | import { SystemVerilogDocumentSymbolProvider } from '../providers/DocumentSymbolProvider'; 3 | 4 | export class SystemVerilogTreeDataProvider implements TreeDataProvider { 5 | private _onDidChangeTreeData: EventEmitter = new EventEmitter(); 6 | readonly onDidChangeTreeData: Event = this._onDidChangeTreeData.event; 7 | 8 | public getTreeItem(element: TreeItem): Promise { 9 | return new Promise((resolve, _reject) => { 10 | resolve(element); 11 | }); 12 | } 13 | 14 | public getChildren(element?: TreeItem): Thenable { 15 | return new Promise((resolve, _reject) => { 16 | if (!element) { 17 | resolve([new TreeItem('testRoot', TreeItemCollapsibleState.Collapsed)]); 18 | } else { 19 | resolve([new TreeItem('testChild')]); 20 | } 21 | }); 22 | } 23 | } 24 | 25 | export class SystemVerilogDocumentSymbolTreeProvider implements TreeDataProvider { 26 | // TODO: Not updating when active file changes 27 | private _onDidChangeTreeData: EventEmitter = new EventEmitter(); 28 | readonly onDidChangeTreeData: Event = this._onDidChangeTreeData.event; 29 | 30 | private provider: SystemVerilogDocumentSymbolProvider; 31 | 32 | public getTreeItem(element: TreeItem): Promise { 33 | return new Promise((resolve, _reject) => { 34 | resolve(element); 35 | }); 36 | } 37 | 38 | public getChildren(element?: TreeItem): Thenable { 39 | return new Promise((resolve, _reject) => { 40 | let items = []; 41 | if (!element) { 42 | this.provider.provideDocumentSymbols(window.activeTextEditor.document).then((symbols) => { 43 | symbols.forEach((symbol) => { 44 | if (symbol.containerName == '') { 45 | let item = new TreeItem(symbol.name); 46 | item.resourceUri = window.activeTextEditor.document.uri; 47 | if (symbols.map((a) => a.containerName).indexOf(symbol.name) != 0) { 48 | item.collapsibleState = TreeItemCollapsibleState.Collapsed; 49 | } 50 | items.push(item); 51 | } 52 | }); 53 | }); 54 | } else { 55 | this.provider.provideDocumentSymbols(window.activeTextEditor.document).then((symbols) => { 56 | symbols.forEach((symbol) => { 57 | if (element.label == symbol.containerName) { 58 | let item = new TreeItem(symbol.name); 59 | item.resourceUri = window.activeTextEditor.document.uri; 60 | item.id = symbol.location.uri.toString(); 61 | item.id += ',line:' + symbol.location.range.start.line.toString(); 62 | item.id += ',char:' + symbol.location.range.start.line.toString(); 63 | if (symbols.map((a) => a.containerName).indexOf(symbol.name) != -1) { 64 | item.collapsibleState = TreeItemCollapsibleState.Collapsed; 65 | } 66 | items.push(item); 67 | } 68 | }); 69 | }); 70 | } 71 | resolve(items); 72 | }); 73 | } 74 | } 75 | -------------------------------------------------------------------------------- /src/symbol.ts: -------------------------------------------------------------------------------- 1 | import { SymbolInformation, SymbolKind, Location } from 'vscode'; 2 | 3 | export class SystemVerilogSymbol extends SymbolInformation { 4 | public type: string; 5 | 6 | /** 7 | * Creates a new symbol information object. 8 | * 9 | * @param name The name of the symbol. 10 | * @param type The name of the symbol. 11 | * @param containerName The name of the symbol containing the symbol. 12 | * @param location The location of the symbol. 13 | */ 14 | constructor(name: string, type: string, containerName: string, location: Location) { 15 | super(name, getSymbolKind(type), containerName, location); 16 | this.type = type; 17 | } 18 | } 19 | 20 | // See resources/SymbolKind_icons.png for an overview of the available icons 21 | // Use show_SymbolKinds to see the latest symbols 22 | export function getSymbolKind(name: string): SymbolKind { 23 | if (name === undefined || name === '') { 24 | // Ports may be declared without type 25 | return SymbolKind.Variable; 26 | } 27 | if (name.indexOf('[') !== -1) { 28 | return SymbolKind.Array; 29 | } 30 | switch (name) { 31 | case 'parameter': 32 | case 'localparam': 33 | case 'Constant': 34 | return SymbolKind.Constant; 35 | case 'potential_reference': 36 | case 'Key': 37 | return SymbolKind.Key; 38 | case 'package': 39 | case 'program': 40 | case 'import': 41 | case 'Package': 42 | return SymbolKind.Package; 43 | case 'begin': // Labels 44 | case 'string': 45 | case 'String': 46 | return SymbolKind.String; 47 | case 'class': 48 | case 'Class': 49 | return SymbolKind.Class; 50 | case 'task': 51 | case 'Method': 52 | return SymbolKind.Method; 53 | case 'function': 54 | case 'Function': 55 | return SymbolKind.Function; 56 | case 'interface': 57 | case 'Interface': 58 | return SymbolKind.Interface; 59 | case 'input': 60 | case 'output': 61 | case 'inout': 62 | return SymbolKind.Boolean; 63 | case 'assert': 64 | case 'event': 65 | case 'Event': 66 | return SymbolKind.Event; 67 | case 'struct': 68 | case 'Struct': 69 | return SymbolKind.Struct; 70 | case 'typedef': 71 | case 'TypeParameter': 72 | return SymbolKind.TypeParameter; 73 | case 'genvar': 74 | case 'Operator': 75 | return SymbolKind.Operator; 76 | case 'enum': 77 | case 'Enum': 78 | return SymbolKind.Enum; 79 | case 'modport': 80 | case 'Null': 81 | return SymbolKind.Null; 82 | case 'define': 83 | case 'property': 84 | case 'Property': 85 | return SymbolKind.Property; 86 | case 'wire': 87 | case 'reg': 88 | case 'bit': 89 | case 'logic': 90 | case 'int': 91 | case 'integer': 92 | case 'char': 93 | case 'time': 94 | case 'float': 95 | case 'Variable': 96 | return SymbolKind.Variable; 97 | case 'module': // It is important that modules don't share a case with any other kind for the module instantiator to work 98 | return SymbolKind.Enum; 99 | default: 100 | return SymbolKind.Field; 101 | } 102 | /* Unused/Free SymbolKind icons 103 | return SymbolKind.Number; 104 | return SymbolKind.Enum; 105 | return SymbolKind.EnumMember; 106 | return SymbolKind.Operator; 107 | return SymbolKind.Array; 108 | */ 109 | } 110 | -------------------------------------------------------------------------------- /src/test/ReferenceProvider.test.ts: -------------------------------------------------------------------------------- 1 | import * as vscode from 'vscode'; 2 | import * as path from 'path'; 3 | import * as assert from 'assert'; 4 | 5 | const rootFolderLocation = '../../'; 6 | 7 | suite('ReferenceProvider Tests', () => { 8 | // Require waiting for #1 build_index 9 | require('./extension.test.js'); 10 | 11 | test('test #1: find references of post_test() task from definition', async () => { 12 | const filepath = path.join(__dirname, rootFolderLocation, 'verilog-examples/environment.sv'); 13 | const uri = vscode.Uri.file(filepath); 14 | const inputLocation = new vscode.Location(uri, new vscode.Position(44, 7)); 15 | const expectedLocations = [ 16 | new vscode.Location(uri, new vscode.Position(44, 7)), 17 | new vscode.Location(uri, new vscode.Position(55, 4)) 18 | ]; 19 | await referenceProviderTest(inputLocation, expectedLocations); 20 | }).timeout(10000); 21 | 22 | test('test #2: find references of post_test() task from call', async () => { 23 | const filepath = path.join(__dirname, rootFolderLocation, 'verilog-examples/environment.sv'); 24 | const uri = vscode.Uri.file(filepath); 25 | const inputLocation = new vscode.Location(uri, new vscode.Position(55, 6)); 26 | const expectedLocations = [ 27 | new vscode.Location(uri, new vscode.Position(44, 7)), 28 | new vscode.Location(uri, new vscode.Position(55, 4)) 29 | ]; 30 | await referenceProviderTest(inputLocation, expectedLocations); 31 | }).timeout(10000); 32 | 33 | test('test #3: find references from definition across files', async () => { 34 | const driver = path.join(__dirname, rootFolderLocation, 'verilog-examples/driver.sv'); 35 | const environment = path.join(__dirname, rootFolderLocation, 'verilog-examples/environment.sv'); 36 | const driverUri = vscode.Uri.file(driver); 37 | const environmentUri = vscode.Uri.file(environment); 38 | const inputLocation = new vscode.Location(driverUri, new vscode.Position(7, 8)); 39 | const expectedLocations = [ 40 | new vscode.Location(driverUri, new vscode.Position(7, 6)), 41 | new vscode.Location(environmentUri, new vscode.Position(5, 10)), 42 | new vscode.Location(environmentUri, new vscode.Position(10, 2)), 43 | new vscode.Location(environmentUri, new vscode.Position(49, 2)) 44 | ]; 45 | await referenceProviderTest(inputLocation, expectedLocations); 46 | }).timeout(10000); 47 | }); 48 | 49 | /** 50 | * Tests that the output of referenceProvider when given a document location and comparing against an expected list of found locations. 51 | * @param inputLocation The Location to retrieve the input text from 52 | * @param expectedLocations The list of expected locations 53 | */ 54 | async function referenceProviderTest(inputLocation: vscode.Location, expectedLocations: vscode.Location[]) { 55 | const references = (await vscode.commands.executeCommand( 56 | 'vscode.executeReferenceProvider', 57 | inputLocation.uri, 58 | inputLocation.range.start 59 | )) as vscode.Location[]; 60 | 61 | assert.strictEqual(references.length, expectedLocations.length); 62 | 63 | // depending on the modify date of the file, they may be accessed in different order, so we need to accoutn for that 64 | for (let i = 0; i < expectedLocations.length; i++) { 65 | let found = false; 66 | for (let j = 0; j < references.length; j++) { 67 | if ( 68 | expectedLocations[i].uri.path === references[j].uri.path && 69 | expectedLocations[i].range.start.isEqual(references[j].range.start) 70 | ) { 71 | found = true; 72 | } 73 | } 74 | assert(found === true); 75 | } 76 | } 77 | -------------------------------------------------------------------------------- /src/compiling/ANTLR/grammar/SubroutineCalls.g4: -------------------------------------------------------------------------------- 1 | grammar SubroutineCalls; 2 | import Expressions; 3 | 4 | tf_call : ps_or_hierarchical_tf_identifier ( attribute_instance )* ( '(' list_of_arguments ')' )? ; 5 | system_tf_call : SYSTEM_TF_IDENTIFIER ( '(' list_of_arguments ')' )? 6 | | SYSTEM_TF_IDENTIFIER '(' data_type ( ',' expression )? ')' 7 | | SYSTEM_TF_IDENTIFIER '(' expression ( ',' ( expression )? )* ( ',' ( clocking_event )? )? ')' ; 8 | subroutine_call : tf_call | system_tf_call | ( ( primary_literal 9 | | ( class_qualifier | package_scope )? hierarchical_identifier select 10 | | empty_unpacked_array_concatenation 11 | | concatenation ( '[' range_expression ']' )? 12 | | multiple_concatenation ( '[' range_expression ']' )? 13 | | let_expression 14 | | '(' mintypmax_expression ')' 15 | | ( ( simple_type | signing | 'string' | 'const' ) APOSTROPHE '(' expression ')' ) 16 | | ( primary_literal 17 | | ps_parameter_identifier constant_select 18 | | specparam_identifier ( '[' constant_range_expression ']' )? 19 | | genvar_identifier 20 | | formal_port_identifier constant_select 21 | | ( package_scope | class_scope )? enum_identifier 22 | | constant_concatenation ( '[' constant_range_expression ']' )? 23 | | constant_multiple_concatenation ( '[' constant_range_expression ']' )? 24 | | constant_let_expression 25 | | '(' constant_mintypmax_expression ')' 26 | | ( ( simple_type | signing | 'string' | 'const' ) APOSTROPHE '(' constant_expression ')' ) 27 | | ( primary_literal 28 | | ps_parameter_identifier constant_select 29 | | specparam_identifier ( '[' constant_range_expression ']' )? 30 | | genvar_identifier 31 | | formal_port_identifier constant_select 32 | | ( package_scope | class_scope )? enum_identifier 33 | | constant_concatenation ( '[' constant_range_expression ']' )? 34 | | constant_multiple_concatenation ( '[' constant_range_expression ']' )? 35 | | constant_let_expression 36 | | '(' constant_mintypmax_expression ')' 37 | | constant_assignment_pattern_expression 38 | | type_reference 39 | | 'null' ) APOSTROPHE '(' constant_expression ')' 40 | | constant_assignment_pattern_expression 41 | | type_reference 42 | | 'null' ) APOSTROPHE '(' expression ')' 43 | | assignment_pattern_expression 44 | | streaming_concatenation 45 | | sequence_method_call 46 | | 'this' 47 | | '$' 48 | | 'null' 49 | | implicit_class_handle ) '.' method_call_body ) 50 | | subroutine_call ( ( APOSTROPHE '(' constant_expression ')' )? APOSTROPHE '(' expression ')' )? '.' method_call_body 51 | | ( 'std' '::' )? randomize_call ; 52 | function_subroutine_call : subroutine_call ; 53 | list_of_arguments : ( expression )? ( ',' ( expression )? )* ( ',' '.' identifier '(' ( expression )? ')' )* 54 | | '.' identifier '(' ( expression )? ')' ( ',' '.' identifier '(' ( expression )? ')' )* ; 55 | list_of_arguments_with_strings : ( string_or_expression )? ( ',' ( string_or_expression )? )* ( ',' '.' identifier '(' ( expression )? ')' )* 56 | | '.' identifier '(' ( expression )? ')' ( ',' '.' identifier '(' ( expression )? ')' )* ; 57 | method_call_body : method_identifier ( attribute_instance )* ( '(' list_of_arguments ')' )? 58 | | built_in_method_call ; 59 | built_in_method_call : array_manipulation_call | randomize_call ; 60 | array_manipulation_call : array_method_name ( attribute_instance )* ( '(' list_of_arguments ')' )? 61 | ( 'with' '(' expression ')' )? 62 | | array_method_call ; 63 | array_method_call : expression '.' array_method_name ( attribute_instance )* ( ( '(' iterator_argument ')' )? 'with' '(' expression ')' )? ; 64 | iterator_argument : identifier ; 65 | randomize_call : 'randomize' ( attribute_instance )* ( '(' ( variable_identifier_list | 'null' )? ')' )? 66 | ( 'with' ( '(' ( identifier_list )? ')' )? constraint_block )? ; 67 | array_method_name : method_identifier | 'unique' | 'and' | 'or' | 'xor' ; 68 | -------------------------------------------------------------------------------- /src/test/index-coverage.ts: -------------------------------------------------------------------------------- 1 | import * as path from 'path'; 2 | import * as Mocha from 'mocha'; 3 | import * as glob from 'glob'; 4 | import * as Nyc from 'nyc'; 5 | import * as baseConfig from '@istanbuljs/nyc-config-typescript'; 6 | 7 | // Recommended modules, loading them here to speed up NYC initialization 8 | // and minimize risk of race conditions. 9 | import 'ts-node/register'; 10 | import 'source-map-support/register'; 11 | 12 | // In Linux, prevent a weird NPE when Mocha on Linux requires the window size from the TTY. 13 | // Since not running in a TTY environment, implementt the method statically. 14 | const tty = require('tty'); 15 | if (!tty.getWindowSize) { 16 | tty.getWindowSize = (): number[] => { 17 | return [80, 75]; 18 | }; 19 | } 20 | 21 | export async function run(): Promise { 22 | // Create the Mocha test 23 | const mocha = new Mocha({ 24 | ui: 'tdd', 25 | color: true, 26 | reporter: 'mocha-multi-reporters', 27 | reporterOptions: { 28 | reporterEnabled: 'spec, xunit', 29 | xunitReporterOptions: { 30 | output: path.join(__dirname, '..', '..', 'results.xml') 31 | } 32 | } 33 | }); 34 | 35 | // Setup coverage pre-test, including post-test hook to report 36 | const nyc = new Nyc({ 37 | ...baseConfig, 38 | cwd: path.join(__dirname, '..', '..'), 39 | reporter: ['text-summary', 'html'], 40 | all: true, 41 | silent: false, 42 | instrument: true, 43 | hookRequire: true, 44 | hookRunInContext: true, 45 | hookRunInThisContext: true, 46 | include: ['out/**/*.js'], 47 | exclude: ['out/test/**'], 48 | // require: ['ts-node/register', 'source-map-support/register'], 49 | sourceMap: true 50 | }); 51 | await nyc.reset(); 52 | await nyc.wrap(); 53 | 54 | // Check the modules already loaded and warn in case of a race condition 55 | // (ideally, at this point the require cache should only contain one file - this module). 56 | const filesRegex = /vscode-systemverilog\/out/; 57 | const filterFn = filesRegex.test.bind(filesRegex); 58 | if (Object.keys(require.cache).filter(filterFn).length > 1) { 59 | console.warn('NYC initialized after modules were loaded', Object.keys(require.cache).filter(filterFn)); 60 | } 61 | 62 | // Debug which files will be included/excluded 63 | // console.log('Glob verification', await nyc.exclude.glob(nyc.cwd)); 64 | 65 | const testsRoot = path.resolve(__dirname, '.'); 66 | 67 | const fails: number = await new Promise((c, e) => { 68 | glob('**/**.test.js', { cwd: testsRoot }, (err, files) => { 69 | if (err) { 70 | return e(err); 71 | } 72 | 73 | // Add files to the test suite 74 | files.forEach((f) => mocha.addFile(path.resolve(testsRoot, f))); 75 | 76 | try { 77 | // Run the mocha test 78 | mocha.run((failures) => { 79 | if (failures > 0) { 80 | e(new Error(`${failures} tests failed.`)); 81 | } else { 82 | c(failures); 83 | } 84 | }); 85 | } catch (err) { 86 | e(err); 87 | } 88 | }); 89 | }); 90 | 91 | await nyc.writeCoverageFile(); 92 | console.log(await captureStdout(nyc.report.bind(nyc))); // Capture `text-summary` reporter's output and log it to the console 93 | 94 | if (fails > 0) { 95 | throw new Error(`${fails} tests failed.`); 96 | } 97 | } 98 | 99 | async function captureStdout(fn) { 100 | let w = process.stdout.write, 101 | buffer = ''; 102 | process.stdout.write = (s) => { 103 | buffer = buffer + s; 104 | return true; 105 | }; 106 | await fn(); 107 | process.stdout.write = w; 108 | return buffer; 109 | } 110 | -------------------------------------------------------------------------------- /src/compiling/VCSCompiler.ts: -------------------------------------------------------------------------------- 1 | import { Diagnostic } from 'vscode-languageserver/node'; 2 | import { TextDocument } from 'vscode-languageserver-textdocument'; 3 | import * as child from 'child_process'; 4 | import { DocumentCompiler } from './DocumentCompiler'; 5 | import { DiagnosticData, isDiagnosticDataUndefined } from './DiagnosticData'; 6 | 7 | /** 8 | * VCS Compiler class contains functionality for compiling SystemVerilog/Verilog files using VCS simulator. 9 | * Generates and takes in predefined runtime arguments, 10 | * and eventually parses the errors/warnings in `stdout` into `Diagnostic` array mapped to each unique document's uri. 11 | */ 12 | export class VCSCompiler extends DocumentCompiler { 13 | /** 14 | Parses `stdout` into `Diagnostics` that are added to `collection` by adding each `Diagnostic` to an array 15 | The array is mapped in `collection` to the referred document's uri. 16 | 17 | @param _error the process's error 18 | @param stdout the process's stdout 19 | @param _stderr the process's stderr 20 | @param compiledDocument the document been compiled 21 | @param documentFilePath the `document`'s file path 22 | @param collection the collection to add the Diagnostics to 23 | @returns a message if an error occurred. 24 | */ 25 | public parseDiagnostics( 26 | _error: child.ExecException, 27 | stdout: string, 28 | _stderr: string, 29 | compiledDocument: TextDocument, 30 | documentFilePath: string, 31 | collection: Map 32 | ): void { 33 | if (stdout === undefined || stdout == null || !compiledDocument) { 34 | return; 35 | } 36 | 37 | const regexError = new RegExp(`(.*)-\\[(.*)\\] (.*)"?${documentFilePath}"?, ([0-9]+)(.*)`); 38 | 39 | stdout = stdout.replace(/\r\n/g, '\n').trim(); 40 | 41 | const errors = stdout.split(/\n\n/g); 42 | 43 | const visitedDocuments = new Map(); 44 | 45 | for (let i = 0; i < errors.length; i++) { 46 | const error = this.formatError(errors[i]); 47 | const diagnosticData: DiagnosticData = new DiagnosticData(); 48 | let matches; 49 | 50 | if ((matches = regexError.exec(error))) { 51 | diagnosticData.filePath = documentFilePath; 52 | diagnosticData.line = parseInt(matches[4], 10) - 1; 53 | diagnosticData.diagnosticSeverity = this.getDiagnosticSeverity(matches[1]); 54 | 55 | // Format Diagnostic's problem 56 | const problem = []; 57 | 58 | // remove preceding/trailing special characters 59 | problem.push(`[${matches[2].replace(/^\W+|\W+$/g, '')}]: `); 60 | problem.push(`${matches[3].replace(/^\W+|\W+$/g, '')}. `); 61 | problem.push(`${matches[5].replace(/^\W+|\W+$/g, '')}.`); 62 | 63 | diagnosticData.problem = problem.join('').trim(); 64 | } 65 | 66 | // Push Diagnostic 67 | if (!isDiagnosticDataUndefined(diagnosticData)) { 68 | if (visitedDocuments.has(diagnosticData.filePath)) { 69 | this.publishDiagnosticForDocument(compiledDocument, false, diagnosticData, collection); 70 | } else { 71 | this.publishDiagnosticForDocument(compiledDocument, true, diagnosticData, collection); 72 | visitedDocuments.set(diagnosticData.filePath, true); 73 | } 74 | } 75 | } 76 | } 77 | 78 | /** 79 | Formats an error by removing new line characters, and cleaning up multiple space characters. 80 | 81 | @param error the error output to format 82 | @returns the formatted error 83 | */ 84 | formatError(error: string): string { 85 | error = error.trim(); 86 | 87 | let regex = new RegExp('( +)?,( +)?\n', 'g'); // eslint-disable-line no-control-regex 88 | error = error.replace(regex, ', '); 89 | 90 | regex = new RegExp('( +)?\n( +)?', 'g'); // eslint-disable-line no-control-regex 91 | error = error.replace(regex, '. '); 92 | 93 | error = error.replace(/ +/g, ' '); 94 | 95 | return error.trim(); 96 | } 97 | } 98 | -------------------------------------------------------------------------------- /verilog-examples/jtag.xdc: -------------------------------------------------------------------------------- 1 | #**************************************************************************** 2 | # 3 | # SPDX-License-Identifier: MIT-0 4 | # Copyright(c) 2015-2020 Intel Corporation. 5 | # 6 | #**************************************************************************** 7 | # 8 | # Sample SDC for A10 GHRD. Targeting JTAG. 9 | # 10 | #**************************************************************************** 11 | # For USB BlasterII running at 24MHz or 41.666 ns period 12 | set t_period 41.666 13 | create_clock -name {altera_reserved_tck} -period $t_period [get_ports {altera_reserved_tck}] 14 | set_clock_groups -asynchronous -group {altera_reserved_tck} 15 | 16 | #Datasheet parameters from UBII IP on EPM570F100C5 17 | #TCO/TSU/TH are measured w.r.t usb_clk inside UBII IP which is used to generate TCK signal 18 | set tck_blaster_tco_max 14.603 19 | set tck_blaster_tco_min 14.603 20 | set tdi_blaster_tco_max 8.551 21 | set tdi_blaster_tco_min 8.551 22 | set tms_blaster_tco_max 9.468 23 | set tms_blaster_tco_min 9.468 24 | 25 | #In bitbang mode, TDO is sampled through MAX at FX2 26 | set tdo_blaster_tpd_max 10.718 27 | set tdo_blaster_tpd_min 10.718 28 | set fx2_pb0_trace_max 0.152 29 | set fx2_pb0_trace_min 0.152 30 | 31 | #Cable delays are from USB Blaster II 32 | #TCK 33 | set tck_cable_max 11.627 34 | set tck_cable_min 10.00 35 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 36 | set tck_header_trace_max 0.5 37 | set tck_header_trace_min 0.1 38 | 39 | #TMS 40 | set tms_cable_max 11.627 41 | set tms_cable_min 10.0 42 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 43 | set tms_header_trace_max 0.5 44 | set tms_header_trace_min 0.1 45 | 46 | #TDI 47 | set tdi_cable_max 11.627 48 | set tdi_cable_min 10.0 49 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 50 | set tdi_header_trace_max 0.5 51 | set tdi_header_trace_min 0.1 52 | 53 | #TDO 54 | set tdo_cable_max 11.627 55 | set tdo_cable_min 10.0 56 | #*USER MODIFY* This depends on the trace length from JTAG 10-pin header to FPGA on board 57 | set tdo_header_trace_max 0.5 58 | set tdo_header_trace_min 0.1 59 | 60 | derive_clock_uncertainty 61 | 62 | #TMS 63 | set tms_in_max [expr {$tms_cable_max + $tms_header_trace_max + $tms_blaster_tco_max - $tck_blaster_tco_min - $tck_cable_min - $tck_header_trace_min }] 64 | set tms_in_min [expr {$tms_cable_min + $tms_header_trace_min + $tms_blaster_tco_min - $tck_blaster_tco_max - $tck_cable_max - $tck_header_trace_max }] 65 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tms_in_max [get_ports {altera_reserved_tms}] 66 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tms_in_min [get_ports {altera_reserved_tms}] 67 | 68 | #TDI 69 | set tdi_in_max [expr {$tdi_cable_max + $tdi_header_trace_max + $tdi_blaster_tco_max - $tck_blaster_tco_min - $tck_cable_min - $tck_header_trace_min }] 70 | set tdi_in_min [expr {$tdi_cable_min + $tdi_header_trace_min + $tdi_blaster_tco_min - $tck_blaster_tco_max - $tck_cable_max - $tck_header_trace_max }] 71 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -max $tdi_in_max [get_ports {altera_reserved_tdi}] 72 | set_input_delay -add_delay -clock_fall -clock altera_reserved_tck -min $tdi_in_min [get_ports {altera_reserved_tdi}] 73 | 74 | #TDO Timing in Bitbang Mode 75 | #TDO timing delays must take into account the TCK delay from the Blaster to the FPGA TCK input pin 76 | set tdo_out_max [expr {$tdo_cable_max + $tdo_header_trace_max + $tdo_blaster_tpd_max + $fx2_pb0_trace_max + $tck_blaster_tco_max + $tck_cable_max + $tck_header_trace_max }] 77 | set tdo_out_min [expr {$tdo_cable_min + $tdo_header_trace_min + $tdo_blaster_tpd_min + $fx2_pb0_trace_min + $tck_blaster_tco_min + $tck_cable_min + $tck_header_trace_min }] 78 | 79 | #TDO does not latch inside the USB Blaster II at the rising edge of TCK, it actually is passed through to the Cypress FX2 and is latched 3 FX2 cycles later (equivalent to 1.5 JTAG cycles) 80 | set_output_delay -add_delay -clock altera_reserved_tck -max $tdo_out_max [get_ports {altera_reserved_tdo}] 81 | set_output_delay -add_delay -clock altera_reserved_tck -min $tdo_out_min [get_ports {altera_reserved_tdo}] 82 | 83 | set_multicycle_path -setup -end 2 -from * -to [get_ports {altera_reserved_tdo}] --------------------------------------------------------------------------------