├── .gitignore ├── Makefile ├── README.md ├── bootload.c ├── bootload.h ├── cc253x.h ├── clock.c ├── clock.h ├── compiler.h ├── config.h ├── errnum.h ├── example.c ├── flash.c ├── flash.h ├── sfr-bits.h ├── uart.c ├── uart.h └── userprog.c /.gitignore: -------------------------------------------------------------------------------- 1 | .settings 2 | .cproject 3 | .project 4 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # CCBOOT requires 2219 byte of SRAM, we try to put it at the upper XDATA location 2 | # by assigning --xram-loc and --xram-size closer to 0x2000 (CC253F256 has 8K SRAM) 3 | SDCCCFLAGS = --model-large --opt-code-size --no-xinit-opt 4 | ASLINKFLAGS = --model-large --code-loc 0x0000 --xram-loc 0x1400 --xram-size 0x0C00 5 | 6 | # User program may overwrite any SRAM location of bootloader, except the passkey_index 7 | # The --xram-size limit is exaclty the location of passkey_index (look at bootload.map) 8 | EXSDCCCFLAGS = --model-large --opt-code-size --no-xinit-opt 9 | EXASLINKFLAGS = --model-large --code-loc 0x1000 --xram-loc 0x0000 --xram-size 0x1400 10 | 11 | %.rel : %.c 12 | sdcc $(SDCCCFLAGS) -c -mmcs51 $< 13 | 14 | all: bootload example 15 | 16 | bootload: bootload.rel clock.rel uart.rel flash.rel userprog.rel 17 | sdcc $(SDCCCFLAGS) $(ASLINKFLAGS) $^ 18 | packihx bootload.ihx > bootload.hex 19 | srec_cat bootload.hex -intel -o bootload.bin -binary 20 | 21 | example: example.rel clock.rel uart.rel 22 | sdcc $(EXSDCCCFLAGS) $(EXASLINKFLAGS) $^ 23 | packihx example.ihx > example.hex 24 | srec_cat example.hex -intel -o example.bin -binary 25 | 26 | clean: 27 | rm -f bootload.asm bootload.cdb bootload.lk bootload.mem bootload.omf 28 | rm -f example.asm example.cdb example.lk example.mem example.omf 29 | rm -f *.asm *.bin *.hex *.ihx *.lnk *.lst *.map *.rel *.rst *.sym -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ccboot-CC2530 2 | ============= 3 | 4 | Serial and RF Bootloader for CC2530 5 | -------------------------------------------------------------------------------- /bootload.c: -------------------------------------------------------------------------------- 1 | /* 2 | * bootload.c 3 | * 4 | * Created on: May 29, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #include "compiler.h" 38 | #include "cc253x.h" 39 | #include "sfr-bits.h" 40 | #include "errnum.h" 41 | #include "clock.h" 42 | #include "uart.h" 43 | #include "flash.h" 44 | #include "bootload.h" 45 | 46 | /* string constants within code memory */ 47 | 48 | __code const uint8_t txt_space[] = " "; 49 | __code const uint8_t txt_press_button[] = "passkey to flash "; 50 | __code const uint8_t txt_running[] = "running..."; 51 | __code const uint8_t txt_nodino[] = "CCBOOT v0.1 - CC253x"; 52 | __code const uint8_t txt_xmodem[] = "- xmodem 115200 bps"; 53 | __code const uint8_t txt_filetype[] = "- user program at 0x1000"; 54 | __code const uint8_t txt_please_send[] = "please send a file (ENTER to cancel)... "; 55 | __code const uint8_t txt_rebooting[] = "rebooting..."; 56 | __code const uint8_t txt_done[] = "done!"; 57 | 58 | /* define the passkey and the length here, please a unique passkey 59 | * starting with character other than '0-9', 'A-Z', or 'a-z' like '@' 60 | */ 61 | 62 | #define PASSKEY_LENGTH 5 63 | __code const uint8_t txt_passkey[] = "@boot"; 64 | 65 | /* allocates variables in the upper XDATA memory area, see Makefile */ 66 | 67 | __xdata uint8_t flash_buffer[FLASH_PAGE_SIZE]; 68 | __xdata uint8_t xmodem_buffer[XMODEM_PAGE_SIZE]; 69 | __xdata uint8_t * pxmodem_buffer; 70 | __xdata uint8_t * pflash_buffer; 71 | __xdata uint8_t flash_page_number; 72 | __xdata uint8_t passkey_index; 73 | //__xdata uint8_t jmp_code[3]; 74 | 75 | /* function prototypes */ 76 | 77 | void lnprint (uint8_t * ptext); 78 | 79 | //---------------------------------------------------------------------------// 80 | // URX0_interceptor (void): serial port listener/interceptor // 81 | //---------------------------------------------------------------------------// 82 | // input: none, it gets called by interrupt vector // 83 | // return: if keypressed/passkey is matched, it invokes bootloader // 84 | // // 85 | // this service routine listens/intercepts incoming serial data. if a // 86 | // a key or a sequence of keys are matched, it gives a bootloader a full // 87 | // control over the cpu. // 88 | //---------------------------------------------------------------------------// 89 | 90 | void URX0_interceptor (void) 91 | { 92 | int16_t serial_data; 93 | 94 | serial_data = U0DBUF; 95 | if (serial_data == txt_passkey[passkey_index]) passkey_index++; 96 | else passkey_index = 0; 97 | 98 | if (passkey_index == PASSKEY_LENGTH) { 99 | passkey_index = 0; 100 | bootloader(); 101 | } 102 | } 103 | 104 | //---------------------------------------------------------------------------// 105 | // lnprint ("string"): put string to standard output // 106 | //---------------------------------------------------------------------------// 107 | // input: array/string pointer // 108 | // return: none // 109 | //---------------------------------------------------------------------------// 110 | 111 | void lnprint (uint8_t * ptext) 112 | { 113 | putchar(0x0D); 114 | putchar(0x0A); 115 | do { 116 | putchar(*ptext); 117 | ptext++; 118 | } while (*ptext); 119 | } 120 | 121 | /*void printhex (uint8_t number) 122 | { 123 | uint8_t high_number, low_number; 124 | 125 | high_number = (number & 0xF0) >> 4; 126 | low_number = number & 0x0F; 127 | 128 | putchar('0'); putchar('x'); 129 | if (high_number > 9) putchar(high_number + 55); else putchar(high_number + 48); 130 | if (low_number > 9) putchar(low_number + 55); else putchar(low_number + 48); 131 | putchar(' '); 132 | }*/ 133 | 134 | //---------------------------------------------------------------------------// 135 | // nodino_getchar (timeout): get one character from serial port // 136 | //---------------------------------------------------------------------------// 137 | // input: timeout period // 138 | // return: 0-255 ascii received // 139 | // return: -1 timeout detected // 140 | //---------------------------------------------------------------------------// 141 | 142 | int16_t nodino_getchar (uint16_t timeout) 143 | { 144 | uint8_t serial_data; 145 | 146 | U0CSR &= ~0x04; 147 | do { 148 | timeout--; 149 | } while (!(U0CSR & 0x04) && timeout); 150 | 151 | if (U0CSR & 0x04) { 152 | serial_data = U0DBUF; 153 | U0CSR &= ~0x04; 154 | return serial_data; 155 | } 156 | else { 157 | U0CSR &= ~0x04; 158 | return ERR_TIMEOUT_DETECTED; 159 | } 160 | } 161 | 162 | //---------------------------------------------------------------------------// 163 | // xmodem_wait_for_sender (timeout): waiting until sender ready to transfer // 164 | //---------------------------------------------------------------------------// 165 | // input: timeout period // 166 | // return: 0-255 ascii received // 167 | // return: -1 timeout detected // 168 | //---------------------------------------------------------------------------// 169 | 170 | int16_t xmodem_wait_for_sender(uint8_t timeout) 171 | { 172 | int16_t serial_data; 173 | 174 | /* sender waits for NACK (XMODEM) to start data transmission */ 175 | do { 176 | serial_data = nodino_getchar(60000); 177 | } while (serial_data == ERR_TIMEOUT_DETECTED && timeout--); 178 | 179 | putchar(XMODEM_NACK); 180 | serial_data = nodino_getchar(60000); 181 | 182 | return serial_data; 183 | } 184 | 185 | //---------------------------------------------------------------------------// 186 | // flash_packets (void) // 187 | //---------------------------------------------------------------------------// 188 | // input: none // 189 | // return: erase, flash, and increase page number counter // 190 | //---------------------------------------------------------------------------// 191 | 192 | void flash_packets (void) 193 | { 194 | if (flash_page_number >= USER_PROGRAM_PAGE) { 195 | flash_erase_page(flash_page_number); 196 | flash_dma_write(flash_buffer, FLASH_PAGE_SIZE, flash_page_number << 11); 197 | } 198 | flash_page_number++; 199 | } 200 | 201 | //---------------------------------------------------------------------------// 202 | // bootloader (void): bootloader program // 203 | //---------------------------------------------------------------------------// 204 | // input: none, it gets called when a passkey is received // 205 | // return: jump to user program after flashing or canceled by // 206 | // rebooting the system // 207 | //---------------------------------------------------------------------------// 208 | 209 | void bootloader (void) 210 | { 211 | int16_t serial_data = 0; 212 | int16_t flash_successful = 0; 213 | int16_t i, page_count = 0; 214 | uint8_t checksum = 0; 215 | 216 | clock_init(); 217 | uart_init(); 218 | EA = 0; /* disable global interrupt */ 219 | 220 | lnprint((uint8_t *) txt_space); 221 | lnprint((uint8_t *) txt_nodino); 222 | lnprint((uint8_t *) txt_xmodem); 223 | lnprint((uint8_t *) txt_filetype); 224 | lnprint((uint8_t *) txt_space); 225 | lnprint((uint8_t *) txt_please_send); 226 | 227 | pxmodem_buffer = xmodem_buffer; 228 | pflash_buffer = flash_buffer; 229 | flash_clear_buffer(flash_buffer); 230 | flash_page_number = 0; 231 | 232 | serial_data = xmodem_wait_for_sender(XMODEM_TIMEOUT); 233 | 234 | /* XMODEM_SOH is detected */ 235 | if (serial_data == XMODEM_SOH) { 236 | 237 | /* put it in the xmodem buffer */ 238 | *pxmodem_buffer = (uint8_t)serial_data; 239 | checksum += serial_data; 240 | pxmodem_buffer++; 241 | 242 | /* start receiving the rest of packets */ 243 | do { 244 | serial_data = nodino_getchar(60000); 245 | 246 | *pxmodem_buffer = (uint8_t)serial_data; 247 | pxmodem_buffer++; 248 | 249 | /* end of transmission */ 250 | if (xmodem_buffer[0] == XMODEM_EOT) { 251 | pxmodem_buffer = xmodem_buffer; 252 | /* do write the flash buffer if there is left */ 253 | /* TODO test for flash memory overflow */ 254 | flash_packets(); 255 | putchar(XMODEM_ACK); 256 | /* done, reboot the system */ 257 | WDCTL = 0x0B; 258 | while(1); 259 | } 260 | 261 | /* when xmodem buffer is full */ 262 | if (pxmodem_buffer == (xmodem_buffer + XMODEM_PAGE_SIZE)) { 263 | if (*(pxmodem_buffer-1) == checksum) { 264 | /* skip SOH and page numbering */ 265 | pxmodem_buffer = xmodem_buffer + 3; 266 | /* transfer xmodem payload to flash buffer */ 267 | for (i = 0; i < XMODEM_PAYLOAD_SIZE; i++) { 268 | *pflash_buffer++ = *pxmodem_buffer++; 269 | } 270 | /* do write when the flash buffer is full */ 271 | if (pflash_buffer == (flash_buffer + FLASH_PAGE_SIZE)) { 272 | /* TODO test for flash memory overflow */ 273 | flash_packets(); 274 | pflash_buffer = flash_buffer; 275 | flash_clear_buffer(flash_buffer); 276 | } 277 | putchar(XMODEM_ACK); 278 | } else { 279 | putchar(XMODEM_NACK); 280 | } 281 | pxmodem_buffer = xmodem_buffer; 282 | checksum = 0; 283 | } else { 284 | checksum += serial_data; 285 | } 286 | } while(1); 287 | } 288 | else { 289 | /* nothing to do, reboot the system */ 290 | WDCTL = 0x0B; 291 | while(1); 292 | } 293 | 294 | /* bootloader never arrives here, it exits to system reset vector 295 | * after flashing done/failed/canceled. 296 | */ 297 | } 298 | 299 | 300 | //---------------------------------------------------------------------------// 301 | // main program // 302 | //---------------------------------------------------------------------------// 303 | // input: none // 304 | // return: never returns, it gives full control to user program // 305 | // // 306 | // when no key or passkey are given, the bootloader with load // 307 | // user program. if the serial interrrupt remains active, the bootloader // 308 | // can be called within user application. // 309 | //---------------------------------------------------------------------------// 310 | 311 | void main (void) 312 | { 313 | uint8_t timeout = BOOTLOADER_TIMEOUT; 314 | 315 | clock_init(); 316 | uart_init(); 317 | EA = 1; /* enable global interrupt */ 318 | 319 | passkey_index = 0; 320 | 321 | lnprint((uint8_t *) txt_space); 322 | lnprint((uint8_t *) txt_press_button); 323 | 324 | do { 325 | nodino_getchar(60000); 326 | putchar('*'); 327 | timeout--; 328 | } while (timeout); 329 | 330 | lnprint((uint8_t *) txt_running); 331 | 332 | __asm_begin 333 | ASM (ljmp USER_PROGRAM_PAGE * 0x800) 334 | __asm_end; 335 | 336 | /* the bootloader never arrives to this area */ 337 | } 338 | 339 | void isr_uart0_rx (void) __interrupt (INUM_URX0) __naked 340 | { 341 | __asm_begin 342 | ASM (push acc) 343 | ASM (push b) 344 | ASM (push dpl) 345 | ASM (push dph) 346 | ASM (push 0x02) 347 | ASM (push 0x03) 348 | ASM (push 0x04) 349 | ASM (push 0x05) 350 | ASM (push 0x06) 351 | ASM (push 0x07) 352 | ASM (push 0x00) 353 | ASM (push 0x01) 354 | ASM (push psw) 355 | __asm_end; 356 | 357 | URX0_interceptor(); 358 | 359 | __asm_begin 360 | ASM (pop psw) 361 | ASM (pop 0x01) 362 | ASM (pop 0x00) 363 | ASM (pop 0x07) 364 | ASM (pop 0x06) 365 | ASM (pop 0x05) 366 | ASM (pop 0x04) 367 | ASM (pop 0x03) 368 | ASM (pop 0x02) 369 | ASM (pop dph) 370 | ASM (pop dpl) 371 | ASM (pop b) 372 | ASM (pop acc) 373 | __asm_end; 374 | 375 | __asm_begin 376 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x13) 377 | __asm_end; 378 | } 379 | 380 | void isr_uart0_tx (void) __interrupt (INUM_UTX0) 381 | { 382 | __asm_begin 383 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x3B) 384 | __asm_end; 385 | } 386 | 387 | void RFERR_VECTOR_redirected(void) __interrupt (INUM_RFERR) 388 | { 389 | __asm_begin 390 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x03) 391 | __asm_end; 392 | } 393 | 394 | void ADC_VECTOR_redirected(void) __interrupt (INUM_ADC) 395 | { 396 | __asm_begin 397 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x0B) 398 | __asm_end; 399 | } 400 | 401 | void URX1_VECTOR_redirected(void) __interrupt (INUM_URX1) 402 | { 403 | __asm_begin 404 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x1B) 405 | __asm_end; 406 | } 407 | 408 | void ENC_VECTOR_redirected(void) __interrupt (INUM_ENC) 409 | { 410 | __asm_begin 411 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x23) 412 | __asm_end; 413 | } 414 | 415 | void ST_VECTOR_redirected(void) __interrupt (INUM_ST) 416 | { 417 | __asm_begin 418 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x2B) 419 | __asm_end; 420 | } 421 | 422 | void P2INT_VECTOR_redirected(void) __interrupt (INUM_P2INT) 423 | { 424 | __asm_begin 425 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x33) 426 | __asm_end; 427 | } 428 | 429 | void DMA_VECTOR_redirected(void) __interrupt (INUM_DMA) 430 | { 431 | __asm_begin 432 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x43) 433 | __asm_end; 434 | } 435 | 436 | void T1_VECTOR_redirected(void) __interrupt (INUM_T1) 437 | { 438 | __asm_begin 439 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x4B) 440 | __asm_end; 441 | } 442 | 443 | void T2_VECTOR_redirected(void) __interrupt (INUM_T2) 444 | { 445 | __asm_begin 446 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x53) 447 | __asm_end; 448 | } 449 | 450 | void T3_VECTOR_redirected(void) __interrupt (INUM_T3) 451 | { 452 | __asm_begin 453 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x5B) 454 | __asm_end; 455 | } 456 | 457 | void T4_VECTOR_redirected(void) __interrupt (INUM_T4) 458 | { 459 | __asm_begin 460 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x63) 461 | __asm_end; 462 | } 463 | 464 | void P0INT_VECTOR_redirected(void) __interrupt (INUM_P0INT) 465 | { 466 | __asm_begin 467 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x6B) 468 | __asm_end; 469 | } 470 | 471 | void UTX1_VECTOR_redirected(void) __interrupt (INUM_UTX1) 472 | { 473 | __asm_begin 474 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x73) 475 | __asm_end; 476 | } 477 | 478 | void P1INT_VECTOR_redirected(void) __interrupt (INUM_P1INT) 479 | { 480 | __asm_begin 481 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x7B) 482 | __asm_end; 483 | } 484 | 485 | void RF_VECTOR_redirected(void) __interrupt (INUM_RF) 486 | { 487 | __asm_begin 488 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x83) 489 | __asm_end; 490 | } 491 | 492 | void WDT_VECTOR_redirected(void) __interrupt (INUM_WDT) 493 | { 494 | __asm_begin 495 | ASM (ljmp (USER_PROGRAM_PAGE * 0x800) + 0x8B) 496 | __asm_end; 497 | } 498 | -------------------------------------------------------------------------------- /bootload.h: -------------------------------------------------------------------------------- 1 | /* 2 | * bootload.h 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #ifndef BOOTLOAD_H_ 38 | #define BOOTLOAD_H_ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | #include 45 | 46 | #define INUM_RFERR 0 47 | #define INUM_ADC 1 48 | #define INUM_URX0 2 49 | #define INUM_URX1 3 50 | #define INUM_ENC 4 51 | #define INUM_ST 5 52 | #define INUM_P2INT 6 53 | #define INUM_UTX0 7 54 | #define INUM_DMA 8 55 | #define INUM_T1 9 56 | #define INUM_T2 10 57 | #define INUM_T3 11 58 | #define INUM_T4 12 59 | #define INUM_P0INT 13 60 | #define INUM_UTX1 14 61 | #define INUM_P1INT 15 62 | #define INUM_RF 16 63 | #define INUM_WDT 17 64 | 65 | #define BOOTLOADER_TIMEOUT 10 /* min value is 1 = 0.1 sec */ 66 | #define XMODEM_TIMEOUT 150 /* minimum value is 1 = 0.1 sec */ 67 | 68 | #define XMODEM_SOH 0x01 69 | #define XMODEM_EOT 0x04 70 | #define XMODEM_ACK 0x06 71 | #define XMODEM_NACK 0x15 72 | #define XMODEM_ETB 0x17 73 | #define XMODEM_CAN 0x18 74 | #define XMODEM_C 0x43 75 | #define XMODEM_BAUDRATE BAUD115200 76 | 77 | #define XMODEM_PAGE_SIZE 132 78 | #define XMODEM_PAYLOAD_SIZE 128 79 | 80 | #define USER_PROGRAM_PAGE 2 81 | 82 | extern __xdata uint8_t flash_page_number; 83 | 84 | void bootloader (void); 85 | 86 | #ifdef __cplusplus 87 | } 88 | #endif 89 | 90 | #endif /* BOOTLOAD_H_ */ 91 | -------------------------------------------------------------------------------- /cc253x.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011, George Oikonomou - 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions 7 | * are met: 8 | * 1. Redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution. 13 | * 3. Neither the name of the Institute nor the names of its contributors 14 | * may be used to endorse or promote products derived from this software 15 | * without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 | * SUCH DAMAGE. 28 | * 29 | * This file is part of the Contiki operating system. 30 | */ 31 | 32 | /** 33 | * \file 34 | * Definitions for TI/Chipcon cc2530, cc2531 and cc2533 SFR registers. 35 | * 36 | * Based on information in: 37 | * "CC253x System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee® 38 | * Applications" 39 | * Literature Number: SWRU191B. April 2009–Revised September 2010 40 | * 41 | * \author 42 | * George Oikonomou - 43 | */ 44 | 45 | #ifndef CC253X_H_ 46 | #define CC253X_H_ 47 | 48 | /*---------------------------------------------------------------------------*/ 49 | /* Compiler Abstraction */ 50 | #include 51 | /*--------------------------------------------------------------------------- 52 | * Interrupt Vectors 53 | * (Table 2.5, page 40) 54 | *---------------------------------------------------------------------------*/ 55 | #define RFERR_VECTOR 0 /* RF TXFIFO underflow and RXFIFO overflow. */ 56 | #define ADC_VECTOR 1 /* ADC end of conversion */ 57 | #define URX0_VECTOR 2 /* USART 0 RX complete */ 58 | #define URX1_VECTOR 3 /* USART 1 RX complete */ 59 | #define ENC_VECTOR 4 /* AES encryption/decryption complete */ 60 | #define ST_VECTOR 5 /* Sleep Timer compare */ 61 | #define P2INT_VECTOR 6 /* Port 2 inputs/USB/I2C */ 62 | #define UTX0_VECTOR 7 /* USART 0 TX complete */ 63 | #define DMA_VECTOR 8 /* DMA transfer complete */ 64 | #define T1_VECTOR 9 /* Timer 1 (16-bit) capture/compare/overflow */ 65 | #define T2_VECTOR 10 /* Timer 2 (MAC Timer) */ 66 | #define T3_VECTOR 11 /* Timer 3 (8-bit) compare/overflow */ 67 | #define T4_VECTOR 12 /* Timer 4 (8-bit) compare/overflow */ 68 | #define P0INT_VECTOR 13 /* Port 0 inputs */ 69 | #define UTX1_VECTOR 14 /* USART1 TX complete */ 70 | #define P1INT_VECTOR 15 /* Port 1 inputs */ 71 | #define RF_VECTOR 16 /* RF general interrupts */ 72 | #define WDT_VECTOR 17 /* Watchdog overflow in timer mode */ 73 | /*--------------------------------------------------------------------------- 74 | * Special Function Registers and BITs 75 | * (Table 2.1, page 27) 76 | *---------------------------------------------------------------------------*/ 77 | /* 8051 Internals */ 78 | SFR(P0, 0x80); /* Port 0 */ 79 | SBIT(P0_7, 0x80, 7); /* Port 0 bit 7 */ 80 | SBIT(P0_6, 0x80, 6); /* Port 0 bit 6 */ 81 | SBIT(P0_5, 0x80, 5); /* Port 0 bit 5 */ 82 | SBIT(P0_4, 0x80, 4); /* Port 0 bit 4 */ 83 | SBIT(P0_3, 0x80, 3); /* Port 0 bit 3 */ 84 | SBIT(P0_2, 0x80, 2); /* Port 0 bit 2 */ 85 | SBIT(P0_1, 0x80, 1); /* Port 0 bit 1 */ 86 | SBIT(P0_0, 0x80, 0); /* Port 0 bit 0 */ 87 | SFR(SP, 0x81); /* Stack pointer */ 88 | SFR(DPL0, 0x82); /* Data pointer 0 low byte */ 89 | SFR(DPH0, 0x83); /* Data pointer 0 high byte */ 90 | SFR(DPL1, 0x84); /* Data pointer 1 low byte */ 91 | SFR(DPH1, 0x85); /* Data pointer 1 high byte */ 92 | SFR(PCON, 0x87); /* Power mode control */ 93 | SFR(TCON, 0x88); /* Interrupt flags */ 94 | SBIT(URX1IF, 0x88, 7); /* USART1 RX interrupt flag */ 95 | SBIT(ADCIF, 0x88, 5); /* ADC interrupt flag */ 96 | SBIT(URX0IF, 0x88, 3); /* USART0 RX interrupt flag */ 97 | SBIT(IT1, 0x88, 2); /* Reserved. Must always be set to 1 */ 98 | SBIT(RFERRIF, 0x88, 1); /* RF TXFIFO/RXFIFO interrupt flag */ 99 | SBIT(IT0, 0x88, 0); /* Reserved. Must always be set to 1 */ 100 | SFR(P1, 0x90); /* Port 1 */ 101 | SBIT(P1_7, 0x90, 7); /* Port 1 bit 7 */ 102 | SBIT(P1_6, 0x90, 6); /* Port 1 bit 6 */ 103 | SBIT(P1_5, 0x90, 5); /* Port 1 bit 5 */ 104 | SBIT(P1_4, 0x90, 4); /* Port 1 bit 4 */ 105 | SBIT(P1_3, 0x90, 3); /* Port 1 bit 3 */ 106 | SBIT(P1_2, 0x90, 2); /* Port 1 bit 2 */ 107 | SBIT(P1_1, 0x90, 1); /* Port 1 bit 1 */ 108 | SBIT(P1_0, 0x90, 0); /* Port 1 bit 0 */ 109 | SFR(DPS, 0x92); /* Data pointer select */ 110 | SFR(S0CON, 0x98); /* Interrupt flags 2 */ 111 | SBIT(ENCIF_1, 0x98, 1); /* AES Interrupt flag 1 */ 112 | SBIT(ENCIF_0, 0x98, 0); /* AES Interrupt flag 0 */ 113 | SFR(IEN2, 0x9A); /* Interrupt enable 2 */ 114 | SFR(S1CON, 0x9B); /* Interrupt flags 3 */ 115 | SFR(P2, 0xA0); /* Port 2 */ 116 | SBIT(P2_7, 0xA0, 7); /* Port 2 bit 7 */ 117 | SBIT(P2_6, 0xA0, 6); /* Port 2 bit 6 */ 118 | SBIT(P2_5, 0xA0, 5); /* Port 2 bit 5 */ 119 | SBIT(P2_4, 0xA0, 4); /* Port 2 bit 4 */ 120 | SBIT(P2_3, 0xA0, 3); /* Port 2 bit 3 */ 121 | SBIT(P2_2, 0xA0, 2); /* Port 2 bit 2 */ 122 | SBIT(P2_1, 0xA0, 1); /* Port 2 bit 1 */ 123 | SBIT(P2_0, 0xA0, 0); /* Port 2 bit 0 */ 124 | SFR(IEN0, 0xA8); /* Interrupt enable 0 */ 125 | SBIT(EA, 0xA8, 7); /* All interrupts - enable/disable */ 126 | SBIT(STIE, 0xA8, 5); /* Sleep Timer interrupt enable */ 127 | SBIT(ENCIE, 0xA8, 4); /* AES encryption/decryption interrupt enable */ 128 | SBIT(URX1IE, 0xA8, 3); /* USART1 RX interrupt enable */ 129 | SBIT(URX0IE, 0xA8, 2); /* USART0 RX interrupt enable */ 130 | SBIT(ADCIE, 0xA8, 1); /* ADC interrupt enable */ 131 | SBIT(RFERRIE, 0xA8, 0); /* RF TXFIFO/RXFIFO interrupt enable */ 132 | SFR(IP0, 0xA9); /* Interrupt priority 0 */ 133 | SFR(IEN1, 0xB8); /* Interrupt enable 1 */ 134 | SBIT(P0IE, 0xB8, 5); /* Port 0 interrupt enable */ 135 | SBIT(T4IE, 0xB8, 4); /* Timer 4 interrupt enable */ 136 | SBIT(T3IE, 0xB8, 3); /* Timer 3 interrupt enable */ 137 | SBIT(T2IE, 0xB8, 2); /* Timer 2 interrupt enable */ 138 | SBIT(T1IE, 0xB8, 1); /* Timer 1 interrupt enable */ 139 | SBIT(DMAIE, 0xB8, 0); /* DMA Transfer interrupt enable */ 140 | SFR(IP1, 0xB9); /* Interrupt priority 1 */ 141 | SFR(IRCON, 0xC0); /* Interrupt flags 4 */ 142 | SBIT(STIF, 0xC0, 7); /* Sleep Timer interrupt flag */ 143 | SBIT(P0IF, 0xC0, 5); /* Port 0 interrupt flag */ 144 | SBIT(T4IF, 0xC0, 4); /* Timer 4 interrupt flag */ 145 | SBIT(T3IF, 0xC0, 3); /* Timer 3 interrupt flag */ 146 | SBIT(T2IF, 0xC0, 2); /* Timer 2 interrupt flag */ 147 | SBIT(T1IF, 0xC0, 1); /* Timer 1 interrupt flag */ 148 | SBIT(DMAIF, 0xC0, 0); /* DMA-complete interrupt flag */ 149 | SFR(PSW, 0xD0); /* Program status word */ 150 | SBIT(CY, 0xD0, 7); /* Carry flag */ 151 | SBIT(AC, 0xD0, 6); /* Auxiliary carry flag */ 152 | SBIT(F0, 0xD0, 5); /* User-defined flag 1, bit addressable */ 153 | SBIT(RS1, 0xD0, 4); /* Register bank select, bit 1 */ 154 | SBIT(RS0, 0xD0, 3); /* Register bank select, bit 0 */ 155 | SBIT(OV, 0xD0, 2); /* Overflow flag */ 156 | SBIT(F1, 0xD0, 1); /* User-defined flag 0, bit addressable */ 157 | SBIT(P, 0xD0, 0); /* Parity flag */ 158 | SFR(ACC, 0xE0); /* Accumulator */ 159 | SBIT(ACC_7, 0xE0, 7); /* Accumulator bit 7 */ 160 | SBIT(ACC_6, 0xE0, 6); /* Accumulator bit 6 */ 161 | SBIT(ACC_5, 0xE0, 5); /* Accumulator bit 5 */ 162 | SBIT(ACC_4, 0xE0, 4); /* Accumulator bit 4 */ 163 | SBIT(ACC_3, 0xE0, 3); /* Accumulator bit 3 */ 164 | SBIT(ACC_2, 0xE0, 2); /* Accumulator bit 2 */ 165 | SBIT(ACC_1, 0xE0, 1); /* Accumulator bit 1 */ 166 | SBIT(ACC_0, 0xE0, 0); /* Accumulator bit 0 */ 167 | SFR(IRCON2, 0xE8); /* Interrupt flags 5 */ 168 | SBIT(WDTIF, 0xE8, 4); /* Watchdog Timer interrupt flag */ 169 | SBIT(P1IF, 0xE8, 3); /* Port 1 Interrupt flag */ 170 | SBIT(UTX1IF, 0xE8, 2); /* USART1 TX interrupt flag */ 171 | SBIT(UTX0IF, 0xE8, 1); /* USART0 TX interrupt flag */ 172 | SBIT(P2IF, 0xE8, 0); /* Port 2 interrupt flag */ 173 | SFR(B, 0xF0); /* B Register */ 174 | SBIT(B_7, 0xF0, 7); /* Register B bit 7 */ 175 | SBIT(B_6, 0xF0, 6); /* Register B bit 6 */ 176 | SBIT(B_5, 0xF0, 5); /* Register B bit 5 */ 177 | SBIT(B_4, 0xF0, 4); /* Register B bit 4 */ 178 | SBIT(B_3, 0xF0, 3); /* Register B bit 3 */ 179 | SBIT(B_2, 0xF0, 2); /* Register B bit 2 */ 180 | SBIT(B_1, 0xF0, 1); /* Register B bit 1 */ 181 | SBIT(B_0, 0xF0, 0); /* Register B bit 0 */ 182 | 183 | /* ADC */ 184 | SFR(ADCCON1, 0xB4); /* ADC control 1 */ 185 | SFR(ADCCON2, 0xB5); /* ADC control 2 */ 186 | SFR(ADCCON3, 0xB6); /* ADC control 3 */ 187 | SFR(ADCL, 0xBA); /* ADC data low */ 188 | SFR(ADCH, 0xBB); /* ADC data high */ 189 | SFR(RNDL, 0xBC); /* Random number generator data low */ 190 | SFR(RNDH, 0xBD); /* Random number generator data high */ 191 | 192 | /* AES Coprocessor */ 193 | SFR(ENCDI, 0xB1); /* Encryption/decryption input data */ 194 | SFR(ENCDO, 0xB2); /* Encryption/decryption output data */ 195 | SFR(ENCCS, 0xB3); /* Encryption/decryption control and status */ 196 | 197 | /* DMA Controller */ 198 | SFR(DMAIRQ, 0xD1); /* DMA interrupt flag */ 199 | SFR(DMA1CFGL, 0xD2); /* DMA channel 1–4 configuration address low */ 200 | SFR(DMA1CFGH, 0xD3); /* DMA channel 1–4 configuration address high */ 201 | SFR(DMA0CFGL, 0xD4); /* DMA channel 0 configuration address low */ 202 | SFR(DMA0CFGH, 0xD5); /* DMA channel 0 configuration address high */ 203 | SFR(DMAARM, 0xD6); /* DMA channel armed */ 204 | SFR(DMAREQ, 0xD7); /* DMA channel start request and status */ 205 | 206 | /* I/O */ 207 | SFR(P0IFG, 0x89); /* Port 0 interrupt status flag */ 208 | SFR(P1IFG, 0x8A); /* Port 1 interrupt status flag */ 209 | SFR(P2IFG, 0x8B); /* Port 2 interrupt status flag */ 210 | SFR(PICTL, 0x8C); /* Port pins interrupt mask and edge */ 211 | SFR(P0IEN, 0xAB); /* Port 0 interrupt mask */ 212 | SFR(P1IEN, 0x8D); /* Port 1 interrupt mask */ 213 | SFR(P2IEN, 0xAC); /* Port 2 interrupt mask */ 214 | SFR(P0INP, 0x8F); /* Port 0 input Mode */ 215 | SFR(PERCFG, 0xF1); /* Peripheral I/O control */ 216 | SFR(APCFG, 0xF2); /* Analog peripheral I/O configuration */ 217 | SFR(P0SEL, 0xF3); /* Port 0 function select */ 218 | SFR(P1SEL, 0xF4); /* Port 1 function select */ 219 | SFR(P2SEL, 0xF5); /* Port 2 function select */ 220 | SFR(P1INP, 0xF6); /* Port 1 input mode */ 221 | SFR(P2INP, 0xF7); /* Port 2 input mode */ 222 | SFR(P0DIR, 0xFD); /* Port 0 direction */ 223 | SFR(P1DIR, 0xFE); /* Port 1 direction */ 224 | SFR(P2DIR, 0xFF); /* Port 2 direction */ 225 | SFR(PMUX, 0xAE); /* Power-down signal mux */ 226 | 227 | /* Memory */ 228 | SFR(MPAGE, 0x93); /* Memory page select */ 229 | SFR(_XPAGE, 0x93); /* Memory page select - SDCC name */ 230 | SFR(MEMCTR, 0xC7); /* Memory system control */ 231 | SFR(FMAP, 0x9F); /* Flash-memory bank mapping */ 232 | SFR(PSBANK, 0x9F); /* Flash-memory bank mapping - SDCC name */ 233 | 234 | /* RF */ 235 | SFR(RFIRQF1, 0x91); /* RF interrupt flags MSB */ 236 | SFR(RFD, 0xD9); /* RF data */ 237 | SFR(RFST, 0xE1); /* RF command strobe */ 238 | SFR(RFIRQF0, 0xE9); /* RF interrupt flags LSB */ 239 | SFR(RFERRF, 0xBF); /* RF error interrupt flags */ 240 | 241 | /* Sleep Timer */ 242 | SFR(ST0, 0x95); /* Sleep Timer 0 */ 243 | SFR(ST1, 0x96); /* Sleep Timer 1 */ 244 | SFR(ST2, 0x97); /* Sleep Timer 2 */ 245 | SFR(STLOAD, 0xAD); /* Sleep-timer load status */ 246 | SFR(SLEEPCMD, 0xBE); /* Sleep-mode control command */ 247 | SFR(SLEEPSTA, 0x9D); /* Sleep-mode control status */ 248 | 249 | /* Power Management and Clocks */ 250 | SFR(CLKCONCMD, 0xC6); /* Clock control command */ 251 | SFR(CLKCONSTA, 0x9E); /* Clock control status */ 252 | 253 | /* Timer 1 */ 254 | SFR(T1CC0L, 0xDA); /* Timer 1 channel 0 capture/compare value low */ 255 | SFR(T1CC0H, 0xDB); /* Timer 1 channel 0 capture/compare value high */ 256 | SFR(T1CC1L, 0xDC); /* Timer 1 channel 1 capture/compare value low */ 257 | SFR(T1CC1H, 0xDD); /* Timer 1 channel 1 capture/compare value high */ 258 | SFR(T1CC2L, 0xDE); /* Timer 1 channel 2 capture/compare value low */ 259 | SFR(T1CC2H, 0xDF); /* Timer 1 channel 2 capture/compare value high */ 260 | SFR(T1CNTL, 0xE2); /* Timer 1 counter low */ 261 | SFR(T1CNTH, 0xE3); /* Timer 1 counter high */ 262 | SFR(T1CTL, 0xE4); /* Timer 1 control and status */ 263 | SFR(T1CCTL0, 0xE5); /* Timer 1 channel 0 capture/compare control */ 264 | SFR(T1CCTL1, 0xE6); /* Timer 1 channel 1 capture/compare control */ 265 | SFR(T1CCTL2, 0xE7); /* Timer 1 channel 2 capture/compare control */ 266 | SFR(T1STAT, 0xAF); /* Timer 1 status */ 267 | 268 | /* Timer 2 (MAC Timer) */ 269 | SFR(T2CTRL, 0x94); /* Timer 2 control */ 270 | SFR(T2EVTCFG, 0x9C); /* Timer 2 event configuration */ 271 | SFR(T2IRQF, 0xA1); /* Timer 2 interrupt flags */ 272 | SFR(T2M0, 0xA2); /* Timer 2 multiplexed register 0 */ 273 | SFR(T2M1, 0xA3); /* Timer 2 multiplexed register 1 */ 274 | SFR(T2MOVF0, 0xA4); /* Timer 2 multiplexed overflow register 0 */ 275 | SFR(T2MOVF1, 0xA5); /* Timer 2 multiplexed overflow register 1 */ 276 | SFR(T2MOVF2, 0xA6); /* Timer 2 multiplexed overflow register 2 */ 277 | SFR(T2IRQM, 0xA7); /* Timer 2 interrupt mask */ 278 | SFR(T2MSEL, 0xC3); /* Timer 2 multiplex select */ 279 | 280 | /* Timer 3 */ 281 | SFR(T3CNT, 0xCA); /* Timer 3 counter */ 282 | SFR(T3CTL, 0xCB); /* Timer 3 control */ 283 | SFR(T3CCTL0, 0xCC); /* Timer 3 channel 0 compare control */ 284 | SFR(T3CC0, 0xCD); /* Timer 3 channel 0 compare value */ 285 | SFR(T3CCTL1, 0xCE); /* Timer 3 channel 1 compare control */ 286 | SFR(T3CC1, 0xCF); /* Timer 3 channel 1 compare value */ 287 | 288 | /* Timer 4 */ 289 | SFR(T4CNT, 0xEA); /* Timer 4 counter */ 290 | SFR(T4CTL, 0xEB); /* Timer 4 control */ 291 | SFR(T4CCTL0, 0xEC); /* Timer 4 channel 0 compare control */ 292 | SFR(T4CC0, 0xED); /* Timer 4 channel 0 compare value */ 293 | SFR(T4CCTL1, 0xEE); /* Timer 4 channel 1 compare control */ 294 | SFR(T4CC1, 0xEF); /* Timer 4 channel 1 compare value */ 295 | 296 | /* Timer 1, 3, 4 join Interrupts */ 297 | SFR(TIMIF, 0xD8); /* Timers 1/3/4 joint interrupt mask/flags */ 298 | SBIT(OVFIM, 0xD8, 6); /* Timer 1 overflow interrupt mask */ 299 | SBIT(T4CH1IF, 0xD8, 5); /* Timer 4 channel 1 interrupt flag */ 300 | SBIT(T4CH0IF, 0xD8, 4); /* Timer 4 channel 0 interrupt flag */ 301 | SBIT(T4OVFIF, 0xD8, 3); /* Timer 4 overflow interrupt flag */ 302 | SBIT(T3CH1IF, 0xD8, 2); /* Timer 3 channel 1 interrupt flag */ 303 | SBIT(T3CH0IF, 0xD8, 1); /* Timer 3 channel 0 interrupt flag */ 304 | SBIT(T3OVFIF, 0xD8, 0); /* Timer 3 overflow interrupt flag */ 305 | 306 | /* USART 0 */ 307 | SFR(U0CSR, 0x86); /* USART 0 control and status */ 308 | SFR(U0DBUF, 0xC1); /* USART 0 receive/transmit data buffer */ 309 | SFR(U0BAUD, 0xC2); /* USART 0 baud-rate control */ 310 | SFR(U0UCR, 0xC4); /* USART 0 UART control */ 311 | SFR(U0GCR, 0xC5); /* USART 0 generic control */ 312 | 313 | /* USART 1 */ 314 | SFR(U1CSR, 0xF8); /* USART 1 control and status */ 315 | SBIT(MODE, 0xF8, 7); /* USART mode select */ 316 | SBIT(RE, 0xF8, 6); /* UART receiver enable */ 317 | SBIT(SLAVE, 0xF8, 5); /* SPI master- or slave mode select */ 318 | SBIT(FE, 0xF8, 4); /* UART framing error status */ 319 | SBIT(ERR, 0xF8, 3); /* UART parity error status */ 320 | SBIT(RX_BYTE, 0xF8, 2); /* Receive byte status */ 321 | SBIT(TX_BYTE, 0xF8, 1); /* Transmit byte status */ 322 | SBIT(ACTIVE, 0xF8, 0); /* USART transmit/receive active status */ 323 | SFR(U1DBUF, 0xF9); /* USART 1 receive/transmit data buffer */ 324 | SFR(U1BAUD, 0xFA); /* USART 1 baud-rate control */ 325 | SFR(U1UCR, 0xFB); /* USART 1 UART control */ 326 | SFR(U1GCR, 0xFC); /* USART 1 Generic control */ 327 | 328 | /* Watchdog Timer */ 329 | SFR(WDCTL, 0xC9); /* Watchdog Timer Control */ 330 | /*--------------------------------------------------------------------------- 331 | * XREG Registers (0x6000–0x63FF), excluding RF and USB registers 332 | * (Table 2.2, page 31) 333 | *---------------------------------------------------------------------------*/ 334 | SFRX(MONMUX , 0x61A6); /* Operational amplifier mode control (cc2530/31) */ 335 | SFRX(OPAMPMC, 0x61A6); /* Battery monitor MUX (cc2533) */ 336 | /* I2C registers - cc2533 only */ 337 | SFRX(I2CCFG, 0x6230); /* I2C control */ 338 | SFRX(I2CSTAT, 0x6231); /* I2C status */ 339 | SFRX(I2CDATA, 0x6232); /* I2C data */ 340 | SFRX(I2CADDR, 0x6233); /* I2C own slave address */ 341 | SFRX(I2CWC, 0x6234); /* Wrapper Control */ 342 | SFRX(I2CIO, 0x6235); /* GPIO */ 343 | /* End I2C registers */ 344 | SFRX(OBSSEL0, 0x6243); /* Observation output control - register 0 */ 345 | SFRX(OBSSEL1, 0x6244); /* Observation output control - register 1 */ 346 | SFRX(OBSSEL2, 0x6245); /* Observation output control - register 2 */ 347 | SFRX(OBSSEL3, 0x6246); /* Observation output control - register 3 */ 348 | SFRX(OBSSEL4, 0x6247); /* Observation output control - register 4 */ 349 | SFRX(OBSSEL5, 0x6248); /* Observation output control - register 5 */ 350 | SFRX(CHVER, 0x6249); /* Chip version */ 351 | SFRX(CHIPID, 0x624A); /* Chip identification */ 352 | 353 | /* TR0 below is renamed to TESTREG0 to avoid namespace conflicts with the 354 | * bit-addressable TCON.TR0 on the default 8051. See SDCC bug 3513300 */ 355 | SFRX(TESTREG0, 0x624B); /* Test register 0 */ 356 | 357 | SFRX(DBGDATA, 0x6260); /* Debug interface write data */ 358 | SFRX(SRCRC, 0x6262); /* Sleep reset CRC */ 359 | SFRX(BATTMON, 0x6264); /* Battery monitor */ 360 | SFRX(IVCTRL, 0x6265); /* Analog control register */ 361 | SFRX(FCTL, 0x6270); /* Flash control */ 362 | SFRX(FADDRL, 0x6271); /* Flash address low */ 363 | SFRX(FADDRH, 0x6272); /* Flash address high */ 364 | SFRX(FWDATA, 0x6273); /* Flash write data */ 365 | SFRX(CHIPINFO0, 0x6276); /* Chip information byte 0 */ 366 | SFRX(CHIPINFO1, 0x6277); /* Chip information byte 1 */ 367 | SFRX(IRCTL, 0x6281); /* Timer 1 IR generation control */ 368 | SFRX(CLD, 0x6290); /* Clock-loss detection */ 369 | SFRX(XX_T1CCTL0, 0x62A0); /* Timer 1 channel 0 capture/compare control (additional XREG mapping of SFR) */ 370 | SFRX(XX_T1CCTL1, 0x62A1); /* Timer 1 channel 1 capture/compare control (additional XREG mapping of SFR register) */ 371 | SFRX(XX_T1CCTL2, 0x62A2); /* Timer 1 channel 2 capture/compare control (additional XREG mapping of SFR register) */ 372 | SFRX(T1CCTL3, 0x62A3); /* Timer 1 channel 3 capture/compare control */ 373 | SFRX(T1CCTL4, 0x62A4); /* Timer 1 channel 4 capture/compare control */ 374 | SFRX(XX_T1CC0L, 0x62A6); /* Timer 1 channel 0 capture/compare value low (additional XREG mapping of SFR register) */ 375 | SFRX(XX_T1CC0H, 0x62A7); /* Timer 1 channel 0 capture/compare value high (additional XREG mapping of SFR register) */ 376 | SFRX(XX_T1CC1L, 0x62A8); /* Timer 1 channel 1 capture/compare value low (additional XREG mapping of SFR register) */ 377 | SFRX(XX_T1CC1H, 0x62A9); /* Timer 1 channel 1 capture/compare value high (additional XREG mapping of SFR register) */ 378 | SFRX(XX_T1CC2L, 0x62AA); /* Timer 1 channel 2 capture/compare value low (additional XREG mapping of SFR register) */ 379 | SFRX(XX_T1CC2H, 0x62AB); /* Timer 1 channel 2 capture/compare value high (additional XREG mapping of SFR register) */ 380 | SFRX(T1CC3L, 0x62AC); /* Timer 1 channel 3 capture/compare value low */ 381 | SFRX(T1CC3H, 0x62AD); /* Timer 1 channel 3 capture/compare value high */ 382 | SFRX(T1CC4L, 0x62AE); /* Timer 1 channel 4 capture/compare value low */ 383 | SFRX(T1CC4H, 0x62AF); /* Timer 1 channel 4 capture/compare value high */ 384 | SFRX(STCC, 0x62B0); /* Sleep Timer capture control */ 385 | SFRX(STCS, 0x62B1); /* Sleep Timer capture status */ 386 | SFRX(STCV0, 0x62B2); /* Sleep Timer capture value byte 0 */ 387 | SFRX(STCV1, 0x62B3); /* Sleep Timer capture value byte 1 */ 388 | SFRX(STCV2, 0x62B4); /* Sleep Timer capture value byte 2 */ 389 | SFRX(OPAMPC, 0x62C0); /* Operational amplifier control */ 390 | SFRX(OPAMPS, 0x62C1); /* Operational amplifier status */ 391 | SFRX(CMPCTL, 0x62D0); /* Analog comparator control and status */ 392 | /*--------------------------------------------------------------------------- 393 | * Radio Registers 394 | * (Sec. 23, page 211) 395 | *---------------------------------------------------------------------------*/ 396 | SFRX(RFCORE_RAM, 0x6000); /* RF Core Memory Map (0x6000 to 0x0617F) */ 397 | SFRX(RXFIFO, 0x6000); /* TXFIFO Direct Access (0x6000 to 0x607F) */ 398 | SFRX(TXFIFO, 0x6080); /* TXFIFO Direct Access (0x6080 to 0x60FF) */ 399 | 400 | SFRX(SRC_ADDR_TABLE, 0x6100); /* Source Address Table Start */ 401 | 402 | /* Source Address Matching Result */ 403 | SFRX(SRCRESMASK0, 0x6160); /* Extended address matching */ 404 | SFRX(SRCRESMASK1, 0x6161); /* Short address matching */ 405 | SFRX(SRCRESMASK2, 0x6162); /* Source address match - 24-bit mask */ 406 | SFRX(SRCRESINDEX, 0x6163); /* Bit index of least-significant 1 in SRCRESMASK */ 407 | 408 | /* Source Address Matching Control */ 409 | SFRX(SRCEXTPENDEN0, 0x6164); /* Ext. Address bit-mask 0 (LSB) */ 410 | SFRX(SRCEXTPENDEN1, 0x6165); /* Ext. Address bit-mask 1 */ 411 | SFRX(SRCEXTPENDEN2, 0x6166); /* Ext. Address bit-mask 2 (MSB) */ 412 | SFRX(SRCSHORTPENDEN0, 0x6167); /* Short Address bit-mask 0 (LSB) */ 413 | SFRX(SRCSHORTPENDEN1, 0x6168); /* Short Address bit-mask 1 */ 414 | SFRX(SRCSHORTPENDEN2, 0x6169); /* Short Address bit-mask 2 (MSB) */ 415 | 416 | /* Local Address Information (used during destination address filtering) */ 417 | SFRX(EXT_ADDR0, 0x616A); /* IEEE extended address 0 */ 418 | SFRX(EXT_ADDR1, 0x616B); /* IEEE extended address 1 */ 419 | SFRX(EXT_ADDR2, 0x616C); /* IEEE extended address 2 */ 420 | SFRX(EXT_ADDR3, 0x616D); /* IEEE extended address 3 */ 421 | SFRX(EXT_ADDR4, 0x616E); /* IEEE extended address 4 */ 422 | SFRX(EXT_ADDR5, 0x616F); /* IEEE extended address 5 */ 423 | SFRX(EXT_ADDR6, 0x6170); /* IEEE extended address 6 */ 424 | SFRX(EXT_ADDR7, 0x6171); /* IEEE extended address 7 */ 425 | SFRX(PAN_ID0, 0x6172); /* PAN ID 0 */ 426 | SFRX(PAN_ID1, 0x6173); /* PAN ID 1 */ 427 | SFRX(SHORT_ADDR0, 0x6174); /* Short Address 0 */ 428 | SFRX(SHORT_ADDR1, 0x6175); /* Short Address 1 */ 429 | 430 | SFRX(FRMFILT0, 0x6180); /* Frame Filtering 0 */ 431 | SFRX(FRMFILT1, 0x6181); /* Frame Filtering 1 */ 432 | SFRX(SRCMATCH, 0x6182); /* Source Address Matching and Pending Bits */ 433 | SFRX(SRCSHORTEN0, 0x6183); /* Short Address Matching 0 */ 434 | SFRX(SRCSHORTEN1, 0x6184); /* Short Address Matching 1 */ 435 | SFRX(SRCSHORTEN2, 0x6185); /* Short Address Matching 2 */ 436 | SFRX(SRCEXTEN0, 0x6186); /* Extended Address Matching 0 */ 437 | SFRX(SRCEXTEN1, 0x6187); /* Extended Address Matching 1 */ 438 | SFRX(SRCEXTEN2, 0x6188); /* Extended Address Matching 2 */ 439 | SFRX(FRMCTRL0, 0x6189); /* Frame Handling */ 440 | SFRX(FRMCTRL1, 0x618A); /* Frame Handling */ 441 | SFRX(RXENABLE, 0x618B); /* RX Enabling */ 442 | SFRX(RXMASKSET, 0x618C); /* RX Enabling */ 443 | SFRX(RXMASKCLR, 0x618D); /* RX Disabling */ 444 | SFRX(FREQTUNE, 0x618E); /* Crystal Oscillator Frequency Tuning */ 445 | SFRX(FREQCTRL, 0x618F); /* RF Frequency Control */ 446 | SFRX(TXPOWER, 0x6190); /* Controls the Output Power */ 447 | SFRX(TXCTRL, 0x6191); /* Controls the TX Settings */ 448 | SFRX(FSMSTAT0, 0x6192); /* Radio Status Register */ 449 | SFRX(FSMSTAT1, 0x6193); /* Radio Status Register */ 450 | SFRX(FIFOPCTRL, 0x6194); /* FIFOP Threshold */ 451 | SFRX(FSMCTRL, 0x6195); /* FSM Options */ 452 | SFRX(CCACTRL0, 0x6196); /* CCA Threshold */ 453 | SFRX(CCACTRL1, 0x6197); /* Other CCA Options */ 454 | SFRX(RSSI, 0x6198); /* RSSI Status Register */ 455 | SFRX(RSSISTAT, 0x6199); /* RSSI Valid Status Register */ 456 | SFRX(RXFIRST, 0x619A); /* First Byte in RXFIFO */ 457 | SFRX(RXFIFOCNT, 0x619B); /* Number of Bytes in RXFIFO */ 458 | SFRX(TXFIFOCNT, 0x619C); /* Number of Bytes in TXFIFO */ 459 | SFRX(RXFIRST_PTR, 0x619D); /* RXFIFO Pointer */ 460 | SFRX(RXLAST_PTR, 0x619E); /* RXFIFO Pointer */ 461 | SFRX(RXP1_PTR, 0x619F); /* RXFIFO Pointer */ 462 | SFRX(TXFIRST_PTR, 0x61A1); /* TXFIFO Pointer */ 463 | SFRX(TXLAST_PTR, 0x61A2); /* TXFIFO Pointer */ 464 | SFRX(RFIRQM0, 0x61A3); /* RF Interrupt Masks 0 */ 465 | SFRX(RFIRQM1, 0x61A4); /* RF Interrupt Masks 1 */ 466 | SFRX(RFERRM, 0x61A5); /* RF Error Interrupt Mask */ 467 | SFRX(RFRND, 0x61A7); /* Random Data */ 468 | SFRX(MDMCTRL0, 0x61A8); /* Controls Modem 0 */ 469 | SFRX(MDMCTRL1, 0x61A9); /* Controls Modem 1 */ 470 | SFRX(FREQEST, 0x61AA); /* Estimated RF Frequency Offset */ 471 | SFRX(RXCTRL, 0x61AB); /* Tune Receive Section */ 472 | SFRX(FSCTRL, 0x61AC); /* Tune Frequency Synthesizer */ 473 | SFRX(FSCAL0, 0x61AD); /* Tune Frequency Calibration 0 */ 474 | SFRX(FSCAL1, 0x61AE); /* Tune Frequency Calibration 1 */ 475 | SFRX(FSCAL2, 0x61AF); /* Tune Frequency Calibration 2 */ 476 | SFRX(FSCAL3, 0x61B0); /* Tune Frequency Calibration 3 */ 477 | SFRX(AGCCTRL0, 0x61B1); /* AGC Dynamic Range Control */ 478 | SFRX(AGCCTRL1, 0x61B2); /* AGC Reference Level */ 479 | SFRX(AGCCTRL2, 0x61B3); /* AGC Gain Override */ 480 | SFRX(AGCCTRL3, 0x61B4); /* AGC Control */ 481 | SFRX(ADCTEST0, 0x61B5); /* ADC Tuning 0 */ 482 | SFRX(ADCTEST1, 0x61B6); /* ADC Tuning 1 */ 483 | SFRX(ADCTEST2, 0x61B7); /* ADC Tuning 2 */ 484 | SFRX(MDMTEST0, 0x61B8); /* Test Register for Modem 0 */ 485 | SFRX(MDMTEST1, 0x61B9); /* Test Register for Modem 1 */ 486 | SFRX(DACTEST0, 0x61BA); /* DAC Override Value */ 487 | SFRX(DACTEST1, 0x61BB); /* DAC Override Value */ 488 | SFRX(DACTEST2, 0x61BC); /* DAC Test Setting */ 489 | SFRX(ATEST, 0x61BD); /* Analog Test Control */ 490 | SFRX(PTEST0, 0x61BE); /* Override Power-Down Register 0 */ 491 | SFRX(PTEST1, 0x61BF); /* Override Power-Down Register 1 */ 492 | SFRX(TXFILTCFG, 0x61FA); /* TX Filter Configuration */ 493 | SFRX(RFC_OBS_CTRL0, 0x61EB); /* RF Observation Mux Control 0 */ 494 | SFRX(RFC_OBS_CTRL1, 0x61EC); /* RF Observation Mux Control 1 */ 495 | SFRX(RFC_OBS_CTRL2, 0x61ED); /* RF Observation Mux Control 2 */ 496 | 497 | /* Command Strobe/CSMA-CA Processor Registers */ 498 | SFRX(CSPPROG0, 0x61C0); /* CSP Program Memory, Byte 0 */ 499 | SFRX(CSPPROG1, 0x61C1); /* CSP Program Memory, Byte 1 */ 500 | SFRX(CSPPROG2, 0x61C2); /* CSP Program Memory, Byte 2 */ 501 | SFRX(CSPPROG3, 0x61C3); /* CSP Program Memory, Byte 3 */ 502 | SFRX(CSPPROG4, 0x61C4); /* CSP Program Memory, Byte 4 */ 503 | SFRX(CSPPROG5, 0x61C5); /* CSP Program Memory, Byte 5 */ 504 | SFRX(CSPPROG6, 0x61C6); /* CSP Program Memory, Byte 6 */ 505 | SFRX(CSPPROG7, 0x61C7); /* CSP Program Memory, Byte 7 */ 506 | SFRX(CSPPROG8, 0x61C8); /* CSP Program Memory, Byte 8 */ 507 | SFRX(CSPPROG9, 0x61C9); /* CSP Program Memory, Byte 9 */ 508 | SFRX(CSPPROG10, 0x61CA); /* CSP Program Memory, Byte 10 */ 509 | SFRX(CSPPROG11, 0x61CB); /* CSP Program Memory, Byte 11 */ 510 | SFRX(CSPPROG12, 0x61CC); /* CSP Program Memory, Byte 12 */ 511 | SFRX(CSPPROG13, 0x61CD); /* CSP Program Memory, Byte 13 */ 512 | SFRX(CSPPROG14, 0x61CE); /* CSP Program Memory, Byte 14 */ 513 | SFRX(CSPPROG15, 0x61CF); /* CSP Program Memory, Byte 15 */ 514 | SFRX(CSPPROG16, 0x61D0); /* CSP Program Memory, Byte 16 */ 515 | SFRX(CSPPROG17, 0x61D1); /* CSP Program Memory, Byte 17 */ 516 | SFRX(CSPPROG18, 0x61D2); /* CSP Program Memory, Byte 18 */ 517 | SFRX(CSPPROG19, 0x61D3); /* CSP Program Memory, Byte 19 */ 518 | SFRX(CSPPROG20, 0x61D4); /* CSP Program Memory, Byte 20 */ 519 | SFRX(CSPPROG21, 0x61D5); /* CSP Program Memory, Byte 21 */ 520 | SFRX(CSPPROG22, 0x61D6); /* CSP Program Memory, Byte 22 */ 521 | SFRX(CSPPROG23, 0x61D7); /* CSP Program Memory, Byte 23 */ 522 | SFRX(CSPCTRL, 0x61E0); /* CSP Control Bit */ 523 | SFRX(CSPSTAT, 0x61E1); /* CSP Status Register */ 524 | SFRX(CSPX, 0x61E2); /* CSP X Register */ 525 | SFRX(CSPY, 0x61E3); /* CSP Y Register */ 526 | SFRX(CSPZ, 0x61E4); /* CSP Z Register */ 527 | SFRX(CSPT, 0x61E5); /* CSP T Register */ 528 | /*--------------------------------------------------------------------------- 529 | * cc2531 USB Registers 530 | * (Sec. 21.12, page 196) 531 | *---------------------------------------------------------------------------*/ 532 | SFRX(USBADDR, 0x6200); /* Function Address */ 533 | SFRX(USBPOW, 0x6201); /* Power/Control Register */ 534 | SFRX(USBIIF, 0x6202); /* IN Endpoints and EP0 Interrupt Flags */ 535 | SFRX(USBOIF, 0x6204); /* OUT-Endpoint Interrupt Flags */ 536 | SFRX(USBCIF, 0x6206); /* Common USB Interrupt Flags */ 537 | SFRX(USBIIE, 0x6207); /* IN Endpoints and EP0 Interrupt-Enable Mask */ 538 | SFRX(USBOIE, 0x6209); /* Out Endpoints Interrupt Enable Mask */ 539 | SFRX(USBCIE, 0x620B); /* Common USB Interrupt-Enable Mask */ 540 | SFRX(USBFRML, 0x620C); /* Current Frame Number (Low Byte) */ 541 | SFRX(USBFRMH, 0x620D); /* Current Frame Number (High Byte) */ 542 | SFRX(USBINDEX, 0x620E); /* Current-Endpoint Index Register */ 543 | SFRX(USBCTRL, 0x620F); /* USB Control Register */ 544 | SFRX(USBMAXI, 0x6210); /* Max. Packet Size for IN Endpoint{1–5} */ 545 | SFRX(USBCS0, 0x6211); /* EP0 Control and Status (USBINDEX = 0) */ 546 | SFRX(USBCSIL, 0x6211); /* IN EP{1–5} Control and Status, Low */ 547 | SFRX(USBCSIH, 0x6212); /* IN EP{1–5} Control and Status, High */ 548 | SFRX(USBMAXO, 0x6213); /* Max. Packet Size for OUT EP{1–5} */ 549 | SFRX(USBCSOL, 0x6214); /* OUT EP{1–5} Control and Status, Low */ 550 | SFRX(USBCSOH, 0x6215); /* OUT EP{1–5} Control and Status, High */ 551 | SFRX(USBCNT0, 0x6216); /* Number of Received Bytes in EP0 FIFO (USBINDEX = 0) */ 552 | SFRX(USBCNTL, 0x6216); /* Number of Bytes in EP{1–5} OUT FIFO, Low */ 553 | SFRX(USBCNTH, 0x6217); /* Number of Bytes in EP{1–5} OUT FIFO, High */ 554 | SFRX(USBF0, 0x6220); /* Endpoint-0 FIFO */ 555 | SFRX(USBF1, 0x6222); /* Endpoint-1 FIFO */ 556 | SFRX(USBF2, 0x6224); /* Endpoint-2 FIFO */ 557 | SFRX(USBF3, 0x6226); /* Endpoint-3 FIFO */ 558 | SFRX(USBF4, 0x6228); /* Endpoint-4 FIFO */ 559 | SFRX(USBF5, 0x622A); /* Endpoint-5 FIFO */ 560 | /*--------------------------------------------------------------------------- 561 | * SFR Access via XDATA (0x7080 - 0x70FF) 562 | *---------------------------------------------------------------------------*/ 563 | SFRX(X_P0, 0x7080); /* Port 0 - Read Only */ 564 | SFRX(X_U0CSR, 0x7086); /* USART 0 control and status */ 565 | SFRX(X_P0IFG, 0x7089); /* Port 0 interrupt status flag */ 566 | SFRX(X_P1IFG, 0x708A); /* Port 1 interrupt status flag */ 567 | SFRX(X_P2IFG, 0x708B); /* Port 2 interrupt status flag */ 568 | SFRX(X_PICTL, 0x708C); /* Port pins interrupt mask and edge */ 569 | SFRX(X_P1IEN, 0x708D); /* Port 1 interrupt mask */ 570 | SFRX(X_P0INP, 0x708F); /* Port 0 input Mode */ 571 | SFRX(X_P1, 0x7090); /* Port 1 - Read Only */ 572 | SFRX(X_RFIRQF1, 0x7091); /* RF interrupt flags MSB */ 573 | SFRX(X_MPAGE, 0x7093); /* Memory page select */ 574 | SFRX(X__XPAGE, 0x7093); /* Memory page select - SDCC name */ 575 | SFRX(X_T2CTRL, 0x7094); /* Timer 2 control */ 576 | SFRX(X_ST0, 0x7095); /* Sleep Timer 0 */ 577 | SFRX(X_ST1, 0x7096); /* Sleep Timer 1 */ 578 | SFRX(X_ST2, 0x7097); /* Sleep Timer 2 */ 579 | SFRX(X_T2EVTCFG, 0x709C); /* Timer 2 event configuration */ 580 | SFRX(X_SLEEPSTA, 0x709D); /* Sleep-mode control status */ 581 | SFRX(X_CLKCONSTA, 0x709E); /* Clock control status */ 582 | SFRX(X_FMAP, 0x709F); /* Flash-memory bank mapping */ 583 | SFRX(X_PSBANK, 0x709F); /* Flash-memory bank mapping - SDCC name */ 584 | SFRX(X_P2, 0x70A0); /* Port 2 - Read Only */ 585 | SFRX(X_T2IRQF, 0x70A1); /* Timer 2 interrupt flags */ 586 | SFRX(X_T2M0, 0x70A2); /* Timer 2 multiplexed register 0 */ 587 | SFRX(X_T2M1, 0x70A3); /* Timer 2 multiplexed register 1 */ 588 | SFRX(X_T2MOVF0, 0x70A4); /* Timer 2 multiplexed overflow register 0 */ 589 | SFRX(X_T2MOVF1, 0x70A5); /* Timer 2 multiplexed overflow register 1 */ 590 | SFRX(X_T2MOVF2, 0x70A6); /* Timer 2 multiplexed overflow register 2 */ 591 | SFRX(X_T2IRQM, 0x70A7); /* Timer 2 interrupt mask */ 592 | SFRX(X_P0IEN, 0x70AB); /* Port 0 interrupt mask */ 593 | SFRX(X_P2IEN, 0x70AC); /* Port 2 interrupt mask */ 594 | SFRX(X_STLOAD, 0x70AD); /* Sleep-timer load status */ 595 | SFRX(X_PMUX, 0x70AE); /* Power-down signal mux */ 596 | SFRX(X_T1STAT, 0x70AF); /* Timer 1 status */ 597 | SFRX(X_ENCDI, 0x70B1); /* Encryption/decryption input data */ 598 | SFRX(X_ENCDO, 0x70B2); /* Encryption/decryption output data */ 599 | SFRX(X_ENCCS, 0x70B3); /* Encryption/decryption control and status */ 600 | SFRX(X_ADCCON1, 0x70B4); /* ADC control 1 */ 601 | SFRX(X_ADCCON2, 0x70B5); /* ADC control 2 */ 602 | SFRX(X_ADCCON3, 0x70B6); /* ADC control 3 */ 603 | SFRX(X_ADCL, 0x70BA); /* ADC data low */ 604 | SFRX(X_ADCH, 0x70BB); /* ADC data high */ 605 | SFRX(X_RNDL, 0x70BC); /* Random number generator data low */ 606 | SFRX(X_RNDH, 0x70BD); /* Random number generator data high */ 607 | SFRX(X_SLEEPCMD, 0x70BE); /* Sleep-mode control command */ 608 | SFRX(X_RFERRF, 0x70BF); /* RF error interrupt flags */ 609 | SFRX(X_U0DBUF, 0x70C1); /* USART 0 receive/transmit data buffer */ 610 | SFRX(X_U0BAUD, 0x70C2); /* USART 0 baud-rate control */ 611 | SFRX(X_T2MSEL, 0x70C3); /* Timer 2 multiplex select */ 612 | SFRX(X_U0UCR, 0x70C4); /* USART 0 UART control */ 613 | SFRX(X_U0GCR, 0x70C5); /* USART 0 generic control */ 614 | SFRX(X_CLKCONCMD, 0x70C6); /* Clock control command */ 615 | SFRX(X_MEMCTR, 0x70C7); /* Memory system control */ 616 | SFRX(X_WDCTL, 0x70C9); /* Watchdog Timer Control */ 617 | SFRX(X_T3CNT, 0x70CA); /* Timer 3 counter */ 618 | SFRX(X_T3CTL, 0x70CB); /* Timer 3 control */ 619 | SFRX(X_T3CCTL0, 0x70CC); /* Timer 3 channel 0 compare control */ 620 | SFRX(X_T3CC0, 0x70CD); /* Timer 3 channel 0 compare value */ 621 | SFRX(X_T3CCTL1, 0x70CE); /* Timer 3 channel 1 compare control */ 622 | SFRX(X_T3CC1, 0x70CF); /* Timer 3 channel 1 compare value */ 623 | SFRX(X_DMAIRQ, 0x70D1); /* DMA interrupt flag */ 624 | SFRX(X_DMA1CFGL, 0x70D2); /* DMA channel 1–4 configuration address low */ 625 | SFRX(X_DMA1CFGH, 0x70D3); /* DMA channel 1–4 configuration address high */ 626 | SFRX(X_DMA0CFGL, 0x70D4); /* DMA channel 0 configuration address low */ 627 | SFRX(X_DMA0CFGH, 0x70D5); /* DMA channel 0 configuration address high */ 628 | SFRX(X_DMAARM, 0x70D6); /* DMA channel armed */ 629 | SFRX(X_DMAREQ, 0x70D7); /* DMA channel start request and status */ 630 | SFRX(X_TIMIF, 0x70D8); /* Timers 1/3/4 joint interrupt mask/flags */ 631 | SFRX(X_RFD, 0x70D9); /* RF data */ 632 | SFRX(X_T1CC0L, 0x70DA); /* Timer 1 channel 0 capture/compare value low */ 633 | SFRX(X_T1CC0H, 0x70DB); /* Timer 1 channel 0 capture/compare value high */ 634 | SFRX(X_T1CC1L, 0x70DC); /* Timer 1 channel 1 capture/compare value low */ 635 | SFRX(X_T1CC1H, 0x70DD); /* Timer 1 channel 1 capture/compare value high */ 636 | SFRX(X_T1CC2L, 0x70DE); /* Timer 1 channel 2 capture/compare value low */ 637 | SFRX(X_T1CC2H, 0x70DF); /* Timer 1 channel 2 capture/compare value high */ 638 | SFRX(X_RFST, 0x70E1); /* RF command strobe */ 639 | SFRX(X_T1CNTL, 0x70E2); /* Timer 1 counter low */ 640 | SFRX(X_T1CNTH, 0x70E3); /* Timer 1 counter high */ 641 | SFRX(X_T1CTL, 0x70E4); /* Timer 1 control and status */ 642 | SFRX(X_T1CCTL0, 0x70E5); /* Timer 1 channel 0 capture/compare control */ 643 | SFRX(X_T1CCTL1, 0x70E6); /* Timer 1 channel 1 capture/compare control */ 644 | SFRX(X_T1CCTL2, 0x70E7); /* Timer 1 channel 2 capture/compare control */ 645 | SFRX(X_RFIRQF0, 0x70E9); /* RF interrupt flags LSB */ 646 | SFRX(X_T4CNT, 0x70EA); /* Timer 4 counter */ 647 | SFRX(X_T4CTL, 0x70EB); /* Timer 4 control */ 648 | SFRX(X_T4CCTL0, 0x70EC); /* Timer 4 channel 0 compare control */ 649 | SFRX(X_T4CC0, 0x70ED); /* Timer 4 channel 0 compare value */ 650 | SFRX(X_T4CCTL1, 0x70EE); /* Timer 4 channel 1 compare control */ 651 | SFRX(X_T4CC1, 0x70EF); /* Timer 4 channel 1 compare value */ 652 | SFRX(X_PERCFG, 0x70F1); /* Peripheral I/O control */ 653 | SFRX(X_APCFG, 0x70F2); /* Analog peripheral I/O configuration */ 654 | SFRX(X_P0SEL, 0x70F3); /* Port 0 function select */ 655 | SFRX(X_P1SEL, 0x70F4); /* Port 1 function select */ 656 | SFRX(X_P2SEL, 0x70F5); /* Port 2 function select */ 657 | SFRX(X_P1INP, 0x70F6); /* Port 1 input mode */ 658 | SFRX(X_P2INP, 0x70F7); /* Port 2 input mode */ 659 | SFRX(X_U1CSR, 0x70F8); /* USART 1 control and status */ 660 | SFRX(X_U1DBUF, 0x70F9); /* USART 1 receive/transmit data buffer */ 661 | SFRX(X_U1BAUD, 0x70FA); /* USART 1 baud-rate control */ 662 | SFRX(X_U1UCR, 0x70FB); /* USART 1 UART control */ 663 | SFRX(X_U1GCR, 0x70FC); /* USART 1 Generic control */ 664 | SFRX(X_P0DIR, 0x70FD); /* Port 0 direction */ 665 | SFRX(X_P1DIR, 0x70FE); /* Port 1 direction */ 666 | SFRX(X_P2DIR, 0x70FF); /* Port 2 direction */ 667 | /*--------------------------------------------------------------------------- 668 | * Information Page (Read Only) 669 | *---------------------------------------------------------------------------*/ 670 | SFRX(X_INFOPAGE, 0x7800); /* Start of Information Page */ 671 | SFRX(X_IEEE_ADDR, 0x780C); /* Start of unique IEEE Address */ 672 | 673 | #endif /* CC253X_H_ */ 674 | -------------------------------------------------------------------------------- /clock.c: -------------------------------------------------------------------------------- 1 | /* 2 | * clock.c 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #include "compiler.h" 38 | #include "cc253x.h" 39 | #include "sfr-bits.h" 40 | #include "clock.h" 41 | 42 | void clock_init(void) 43 | { 44 | /* Make sure we know where we stand */ 45 | CLKCONCMD = CLKCONCMD_OSC32K | CLKCONCMD_OSC; 46 | while(!(CLKCONSTA & CLKCONCMD_OSC)); 47 | 48 | /* Stay with 32 KHz RC OSC, change system clock to 32 MHz */ 49 | CLKCONCMD &= ~CLKCONCMD_OSC; 50 | while(CLKCONSTA & CLKCONCMD_OSC); 51 | } 52 | 53 | void clock_delay_usec(uint16_t len) 54 | { 55 | while(len--) { 56 | __asm_begin 57 | ASM(nop) 58 | __asm_end; 59 | } 60 | } 61 | -------------------------------------------------------------------------------- /clock.h: -------------------------------------------------------------------------------- 1 | /* 2 | * clock.h 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #ifndef CLOCK_H_ 38 | #define CLOCK_H_ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | #include 45 | 46 | void clock_init(void); 47 | void clock_delay_usec(uint16_t usec); 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif /* CLOCK_H_ */ 54 | -------------------------------------------------------------------------------- /compiler.h: -------------------------------------------------------------------------------- 1 | /** \file compiler.h 2 | * \author Maarten Brock 3 | * 4 | * This library is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU Lesser General Public 6 | * License as published by the Free Software Foundation; either 7 | * version 2.1 of the License, or (at your option) any later version. 8 | * 9 | * This library is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 | * Lesser General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU Lesser General Public 15 | * License along with this library; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 | * 18 | * In other words, you are welcome to use, share and improve this program. 19 | * You are forbidden to forbid anyone else to use, share and improve 20 | * what you give them. Help stamp out software-hoarding! 21 | * 22 | * Header file to overcome 8051 compiler differences for specifying 23 | * special function registers. The following compilers are supported: 24 | * SDCC, Keil, Raisonance, IAR, Hi-Tech, Tasking, Crossware, Wickenhaeuser. 25 | * Unfortunately not for use with Dunfield. The compilers are identified by 26 | * their unique predefined macros. See also: 27 | * http://predef.sourceforge.net/precomp.html 28 | * 29 | * SBIT and SFR define special bit and special function registers at the given 30 | * address. SFR16 and SFR32 define sfr combinations at adjacent addresses in 31 | * little-endian format. SFR16E and SFR32E define sfr combinations without 32 | * prerequisite byte order or adjacency. None of these multi-byte sfr 33 | * combinations will guarantee the order in which they are accessed when read 34 | * or written. 35 | * SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined 36 | * to avoid portability issues because of compiler endianness. 37 | * This file is to be included in every microcontroller specific header file. 38 | * Example: 39 | * 40 | * // my_mcu.h: sfr definitions for my mcu 41 | * #include 42 | * 43 | * SBIT (P0_1, 0x80, 1); // Port 0 pin 1 44 | * 45 | * SFR (P0, 0x80); // Port 0 46 | * 47 | * SFRX (CPUCS, 0xE600); // Cypress FX2 Control and Status register in xdata memory at 0xE600 48 | * 49 | * SFR16 (TMR2, 0xCC); // Timer 2, lsb at 0xCC, msb at 0xCD 50 | * 51 | * SFR16E(TMR0, 0x8C8A); // Timer 0, lsb at 0x8A, msb at 0x8C 52 | * 53 | * SFR32 (MAC0ACC, 0x93); // SiLabs C8051F120 32 bits MAC0 Accumulator, lsb at 0x93, msb at 0x96 54 | * 55 | * SFR32E(SUMR, 0xE5E4E3E2); // TI MSC1210 SUMR 32 bits Summation register, lsb at 0xE2, msb at 0xE5 56 | * 57 | */ 58 | 59 | /*------------------------------------------------------------------------- 60 | Updated by - Ekawahyu Susilo / ekawahyu at yahoo dot com (September 2009) 61 | 62 | Added/redefined: 63 | - VECT(num, addr) 64 | - SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit3, bit2, bit1, bit0) 65 | - ASM(instruction) 66 | 67 | -------------------------------------------------------------------------*/ 68 | 69 | #ifndef COMPILER_H 70 | #define COMPILER_H 71 | 72 | /** SDCC - Small Device C Compiler 73 | * http://sdcc.sf.net 74 | */ 75 | #if defined SDCC || defined __SDCC 76 | # define VECT(num, addr) num 77 | # define SBIT(name, addr, bit) __sbit __at(addr+bit) name 78 | # define SFR(name, addr) __sfr __at(addr) name 79 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 80 | # define SFRX(name, addr) __xdata volatile unsigned char __at(addr) name 81 | # define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name 82 | # define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name 83 | # define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name 84 | # define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name 85 | # define ASM(...) __VA_ARGS__ 86 | # define __asm_begin __asm 87 | # define __asm_end __endasm 88 | 89 | /** Keil C51 90 | * http://www.keil.com 91 | */ 92 | #elif defined __CX51__ 93 | # define VECT(num, addr) num 94 | # define SBIT(name, addr, bit) sbit name = addr^bit 95 | # define SFR(name, addr) sfr name = addr 96 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 97 | # define SFRX(name, addr) volatile unsigned char xdata name _at_ addr 98 | # define SFR16(name, addr) sfr16 name = addr 99 | # define SFR16E(name, fulladdr) /* not supported */ 100 | # define SFR32(name, fulladdr) /* not supported */ 101 | # define SFR32E(name, fulladdr) /* not supported */ 102 | # define ASM(...) __VA_ARGS__ 103 | # define __asm_begin __asm{ 104 | # define __asm_end } 105 | 106 | /** Raisonance 107 | * http://www.raisonance.com 108 | */ 109 | #elif defined __RC51__ 110 | # define VECT(num, addr) num 111 | # define SBIT(name, addr, bit) at (addr+bit) sbit name 112 | # define SFR(name, addr) sfr at addr name 113 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 114 | # define SFRX(name, addr) xdata at addr volatile unsigned char name 115 | # define SFR16(name, addr) sfr16 at addr name 116 | # define SFR16E(name, fulladdr) /* not supported */ 117 | # define SFR32(name, fulladdr) /* not supported */ 118 | # define SFR32E(name, fulladdr) /* not supported */ 119 | 120 | /** IAR 8051 121 | * http://www.iar.com 122 | */ 123 | #elif __IAR_SYSTEMS_ICC__ 124 | # define __SFRBIT_IN_USE__ 125 | # define VECT(num, addr) addr 126 | # define SBIT(name, addr, bit) /* not used (to be removed) */ 127 | # define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr 128 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) \ 129 | __sfr __no_init volatile union \ 130 | { \ 131 | unsigned char name; \ 132 | struct { \ 133 | unsigned char bit0 : 1; \ 134 | unsigned char bit1 : 1; \ 135 | unsigned char bit2 : 1; \ 136 | unsigned char bit3 : 1; \ 137 | unsigned char bit4 : 1; \ 138 | unsigned char bit5 : 1; \ 139 | unsigned char bit6 : 1; \ 140 | unsigned char bit7 : 1; \ 141 | }; \ 142 | } @ addr; 143 | # define SFRX(name, addr) __xdata __no_init volatile unsigned char name @ addr 144 | # define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr 145 | # define SFR16E(name, fulladdr) /* not supported */ 146 | # define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr 147 | # define SFR32E(name, fulladdr) /* not supported */ 148 | # define ASM(...) asm(#__VA_ARGS__); 149 | # define __asm_begin 150 | # define __asm_end 151 | 152 | /** Tasking / Altium 153 | * http://www.altium.com/tasking 154 | */ 155 | #elif defined _CC51 156 | # define VECT(num, addr) num 157 | # define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) 158 | # define SFR(name, addr) _sfrbyte name _at(addr) 159 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 160 | # define SFRX(name, addr) _xdat volatile unsigned char name _at(addr) 161 | #if _CC51 > 71 162 | # define SFR16(name, addr) _sfrword _little name _at(addr) 163 | #else 164 | # define SFR16(name, addr) /* not supported */ 165 | #endif 166 | # define SFR16E(name, fulladdr) /* not supported */ 167 | # define SFR32(name, fulladdr) /* not supported */ 168 | # define SFR32E(name, fulladdr) /* not supported */ 169 | 170 | /** Hi-Tech 8051 171 | * http://www.htsoft.com 172 | */ 173 | #elif defined HI_TECH_C 174 | # define VECT(num, addr) addr 175 | # define SBIT(name, addr, bit) volatile bit name @ (addr+bit) 176 | # define SFR(name, addr) volatile unsigned char name @ addr 177 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 178 | # define SFRX(name, addr) volatile far unsigned char name @ addr 179 | # define SFR16(name, addr) /* not supported */ 180 | # define SFR16E(name, fulladdr) /* not supported */ 181 | # define SFR32(name, fulladdr) /* not supported */ 182 | # define SFR32E(name, fulladdr) /* not supported */ 183 | 184 | /** Crossware 185 | * http://www.crossware.com 186 | */ 187 | #elif defined _XC51_VER 188 | # define VECT(num, addr) num 189 | # define SBIT(name, addr, bit) _sfrbit name = (addr+bit) 190 | # define SFR(name, addr) _sfr name = addr 191 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 192 | # define SFRX(name, addr) volatile unsigned char _xdata name _at addr 193 | # define SFR16(name, addr) _sfrword name = addr 194 | # define SFR16E(name, fulladdr) /* not supported */ 195 | # define SFR32(name, fulladdr) /* not supported */ 196 | # define SFR32E(name, fulladdr) /* not supported */ 197 | 198 | /** Wickenhaeuser 199 | * http://www.wickenhaeuser.de 200 | */ 201 | #elif defined __UC__ 202 | # define VECT(num, addr) addr 203 | # define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit) 204 | # define SFR(name, addr) near unsigned char name @ addr 205 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) /* not used */ 206 | # define SFRX(name, addr) xdata volatile unsigned char name @ addr 207 | # define SFR16(name, addr) /* not supported */ 208 | # define SFR16E(name, fulladdr) /* not supported */ 209 | # define SFR32(name, fulladdr) /* not supported */ 210 | # define SFR32E(name, fulladdr) /* not supported */ 211 | 212 | /** default 213 | * unrecognized compiler 214 | */ 215 | #else 216 | # warning unrecognized compiler 217 | # define VECT(num, addr) num 218 | # define SBIT(name, addr, bit) volatile bool name 219 | # define SFR(name, addr) volatile unsigned char name 220 | # define SFRBIT(name, addr, bit7, bit6, bit5, bit4, bit3, bit2, bit1, bit0) name 221 | # define SFRX(name, addr) volatile unsigned char name 222 | # define SFR16(name, addr) volatile unsigned short name 223 | # define SFR16E(name, fulladdr) volatile unsigned short name 224 | # define SFR32(name, fulladdr) volatile unsigned long name 225 | # define SFR32E(name, fulladdr) volatile unsigned long name 226 | 227 | #endif 228 | 229 | #endif //COMPILER_H 230 | -------------------------------------------------------------------------------- /config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * config.h 3 | * 4 | * Created on: May 29, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #ifndef CONFIG_H_ 38 | #define CONFIG_H_ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | #define UART_CONF_STDOUT_PORT 0 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif /* CONFIG_H_ */ 51 | -------------------------------------------------------------------------------- /errnum.h: -------------------------------------------------------------------------------- 1 | /* 2 | * errnum.h 3 | * 4 | * Created on: May 29, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #ifndef ERRNUM_H_ 38 | #define ERRNUM_H_ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | #define ERR_TIMEOUT_DETECTED -1 45 | #define ERR_DEVICE_IN_USE -2 46 | #define ERR_UART_INVALID_BAUDRATE -3 47 | #define ERR_UART_INVALID_PORT_NUMBER -4 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif /* ERRNUM_H_ */ 54 | -------------------------------------------------------------------------------- /example.c: -------------------------------------------------------------------------------- 1 | /* 2 | * example.c 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #include 38 | 39 | #include "compiler.h" 40 | #include "cc253x.h" 41 | #include "clock.h" 42 | #include "uart.h" 43 | 44 | void isr_uart0_rx (void) __interrupt (URX0_VECTOR) 45 | { 46 | URX0IF = 0; 47 | } 48 | 49 | void isr_uart0_tx (void) __interrupt (UTX0_VECTOR) 50 | { 51 | UTX0IF = 0; 52 | } 53 | 54 | void main (void) 55 | { 56 | clock_init(); 57 | uart_init(); 58 | 59 | P1SEL &= ~(0x10 | 0x02 | 0x01); 60 | P1DIR |= (0x10 | 0x02 | 0x01); 61 | 62 | P2SEL &= ~0x01; 63 | P2DIR |= 0x01; 64 | 65 | while(1) { 66 | P1_0 = 1; 67 | P1_1 = 1; 68 | P1_4 = 1; 69 | printf("Hello\n"); 70 | clock_delay_usec(60000); 71 | P1_0 = 0; 72 | P1_1 = 0; 73 | P1_4 = 0; 74 | printf("World\n"); 75 | clock_delay_usec(60000); 76 | } 77 | } 78 | -------------------------------------------------------------------------------- /flash.c: -------------------------------------------------------------------------------- 1 | /* 2 | * flash.c 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #include "compiler.h" 38 | #include "cc253x.h" 39 | #include "flash.h" 40 | 41 | void flash_clear_buffer(uint8_t * pflash_buffer) 42 | { 43 | uint8_t * plimit = pflash_buffer+FLASH_PAGE_SIZE; 44 | 45 | do { 46 | *pflash_buffer++ = 0x00; 47 | } while (pflash_buffer <= plimit); 48 | } 49 | 50 | void flash_erase_page(uint8_t page) 51 | { 52 | FADDRH = (page) << 1; 53 | FADDRL = 0x00; 54 | FLASH_CONFIG(ERASE); 55 | __asm_begin 56 | ASM(NOP) 57 | __asm_end; 58 | } 59 | 60 | void flash_dma_write(uint8_t *buffer, uint16_t length, uint16_t flashadr) // length is multiplication of 4 61 | { 62 | dma_config_t dmaConfig0; 63 | 64 | dmaConfig0.src_h = ((uint16_t)buffer >> 8) & 0x00FF; /* source address high byte*/ 65 | dmaConfig0.src_l = (uint16_t)buffer & 0x00FF; /* source address low byte*/ 66 | dmaConfig0.dst_h = (((uint16_t)&FWDATA) >> 8) & 0x00FF; /* dest. address high byte*/ 67 | dmaConfig0.dst_l = ((uint16_t)&FWDATA) & 0x00FF; /* dest. address low byte*/ 68 | dmaConfig0.len_h = (length>>8) & 0x00FF; /* [7:5] VLEN, [4:0] length high byte, 5 lowest bits*/ 69 | dmaConfig0.len_l = length & 0x00FF; /* length low byte*/ 70 | dmaConfig0.wtt = 18; /* 7: wordsize, [6:5] transfer mode, [4:0] trigger */ 71 | dmaConfig0.inc_prio = 0x42; /* [7:6] src inc, [5:4] dst_inc, 3: IRQ, 2: M8(vlen), [1-0] prio */ 72 | 73 | FLASH_BUSY_WAIT(); 74 | 75 | FADDRH = (flashadr >> 10) & 0x00FF; 76 | FADDRL = (flashadr >> 2) & 0x00FF; 77 | DMA0CFGH = (((uint16_t)&dmaConfig0) >> 8) & 0x00FF; 78 | DMA0CFGL = ((uint16_t)&dmaConfig0) & 0x00FF; 79 | 80 | DMAARM |= 0x01; /* arm the DMA */ 81 | FLASH_CONFIG(WRITE); /* trigger the DMA transfer */ 82 | while (!(DMAIRQ & 0x01)); /* wait until write complete */ 83 | DMAIRQ &= 0xFE; /* clear any DMA interrupt flag */ 84 | 85 | FLASH_BUSY_WAIT(); 86 | } 87 | -------------------------------------------------------------------------------- /flash.h: -------------------------------------------------------------------------------- 1 | /* 2 | * flash.h 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #ifndef FLASH_H_ 38 | #define FLASH_H_ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | #include 45 | 46 | #define FLASH_PAGE_SIZE 2048 47 | 48 | #define READ_WHEN_NEED 0x00 49 | #define CONTINOUS_READ 0x10 50 | #define WRITE 0x02 51 | #define ERASE 0x01 52 | #define FLASH_FULL 0x40 53 | #define FLASH_BUSY 0x80 54 | 55 | #define FLASH_WRITE_PAGE(page) \ 56 | do{ \ 57 | FLASH_CONFIG(WRITE); \ 58 | FADDRH = ((page)+1) << 3; \ 59 | FADDRL = 0x00; \ 60 | }while (0) 61 | 62 | 63 | #define FLASH_BUSY_WAIT() \ 64 | do{ \ 65 | }while (FCTL & FLASH_BUSY) 66 | 67 | 68 | #define FLASH_FULL_WAIT() \ 69 | do{ \ 70 | }while (FCTL & FLASH_FULL) 71 | 72 | 73 | #define FLASH_CONFIG(options) \ 74 | do { \ 75 | FCTL = options; \ 76 | } while (0) 77 | 78 | void flash_erase_page(unsigned char page); 79 | void flash_clear_buffer(uint8_t * pflash_buffer); 80 | 81 | /** DMA configuration structure */ 82 | typedef struct dma_config { 83 | uint8_t src_h; /* source address high byte*/ 84 | uint8_t src_l; /* source address low byte*/ 85 | uint8_t dst_h; /* dest. address high byte*/ 86 | uint8_t dst_l; /* dest. address low byte*/ 87 | uint8_t len_h; /* [7:5] VLEN, [4:0] length high byte, 5 lowest bits*/ 88 | uint8_t len_l; /* length low byte*/ 89 | uint8_t wtt; /* 7: wordsize, [6:5] transfer mode, [4:0] trigger */ 90 | /* [7:6] src inc, [5:4] dst_inc, 3: IRQ, 2: M8(vlen), [1-0] prio */ 91 | uint8_t inc_prio; 92 | } dma_config_t; 93 | 94 | void flash_dma_write(uint8_t *buffer, uint16_t length, uint16_t flashadr); 95 | 96 | #ifdef __cplusplus 97 | } 98 | #endif 99 | 100 | #endif /* FLASH_H_ */ 101 | -------------------------------------------------------------------------------- /sfr-bits.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2011, George Oikonomou - 3 | * All rights reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions 7 | * are met: 8 | * 1. Redistributions of source code must retain the above copyright 9 | * notice, this list of conditions and the following disclaimer. 10 | * 2. Redistributions in binary form must reproduce the above copyright 11 | * notice, this list of conditions and the following disclaimer in the 12 | * documentation and/or other materials provided with the distribution. 13 | * 3. Neither the name of the Institute nor the names of its contributors 14 | * may be used to endorse or promote products derived from this software 15 | * without specific prior written permission. 16 | * 17 | * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 | * SUCH DAMAGE. 28 | * 29 | * This file is part of the Contiki operating system. 30 | */ 31 | 32 | /** 33 | * \file 34 | * Header file with definitions of bit masks for some cc2530 SFRs 35 | * 36 | * \author 37 | * George Oikonomou - 38 | */ 39 | 40 | 41 | #ifndef SFR_BITS_H_ 42 | #define SFR_BITS_H_ 43 | 44 | /* CLKCON */ 45 | #define CLKCONCMD_OSC32K 0x80 46 | #define CLKCONCMD_OSC 0x40 47 | #define CLKCONCMD_TICKSPD2 0x20 48 | #define CLKCONCMD_TICKSPD1 0x10 49 | #define CLKCONCMD_TICKSPD0 0x08 50 | #define CLKCONCMD_CLKSPD2 0x04 51 | #define CLKCONCMD_CLKSPD1 0x02 52 | #define CLKCONCMD_CLKSPD0 0x01 53 | 54 | /* SLEEPCMD and SLEEPSTA */ 55 | #define SLEEP_OSC32K_CALDIS 0x80 56 | #define SLEEP_XOSC_STB 0x40 57 | #define SLEEP_HFRC_STB 0x20 58 | #define SLEEP_RST1 0x10 /* SLEEPSTA only */ 59 | #define SLEEP_RST0 0x08 /* SLEEPSTA only */ 60 | #define SLEEP_OSC_PD 0x04 61 | #define SLEEP_MODE1 0x02 62 | #define SLEEP_MODE0 0x01 63 | 64 | /* PCON */ 65 | #define PCON_IDLE 0x01 66 | 67 | /* T1CTL */ 68 | #define T1CTL_DIV1 0x08 69 | #define T1CTL_DIV0 0x04 70 | #define T1CTL_MODE1 0x02 71 | #define T1CTL_MODE0 0x01 72 | 73 | /* T1CCTLx */ 74 | #define T1CCTL_RFIRQ 0x80 75 | #define T1CCTL_IM 0x40 76 | #define T1CCTL_CMP2 0x20 77 | #define T1CCTL_CMP1 0x10 78 | #define T1CCTL_CMP0 0x08 79 | #define T1CCTL_MODE 0x04 80 | #define T1CCTL_CAP1 0x02 81 | #define T1CCTL_CAP0 0x01 82 | 83 | /* T1STAT */ 84 | #define T1STAT_OVFIF 0x20 85 | #define T1STAT_CH4IF 0x10 86 | #define T1STAT_CH3IF 0x08 87 | #define T1STAT_CH2IF 0x04 88 | #define T1STAT_CH1IF 0x02 89 | #define T1STAT_CH0IF 0x01 90 | 91 | /* WDCTL */ 92 | #define WDCTL_CLR3 0x80 93 | #define WDCTL_CLR2 0x40 94 | #define WDCTL_CLR1 0x20 95 | #define WDCTL_CLR0 0x10 96 | #define WDCTL_MODE1 0x08 97 | #define WDCTL_MODE0 0x04 98 | #define WDCTL_INT1 0x02 99 | #define WDCTL_INT0 0x01 100 | 101 | /* ADCCON1 */ 102 | #define ADCCON1_EOC 0x80 103 | #define ADCCON1_ST 0x40 104 | #define ADCCON1_STSEL1 0x20 105 | #define ADCCON1_STSEL0 0x10 106 | /* ADCCON1 - RNG bits */ 107 | #define ADCCON1_RCTRL1 0x08 108 | #define ADCCON1_RCTRL0 0x04 109 | 110 | /* ADCCON3 */ 111 | #define ADCCON3_EREF1 0x80 112 | #define ADCCON3_EREF0 0x40 113 | #define ADCCON3_EDIV1 0x20 114 | #define ADCCON3_EDIV0 0x10 115 | #define ADCCON3_ECH3 0x08 116 | #define ADCCON3_ECH2 0x04 117 | #define ADCCON3_ECH1 0x02 118 | #define ADCCON3_ECH0 0x01 119 | 120 | /* PERCFG */ 121 | #define PERCFG_T1CFG 0x40 122 | #define PERCFG_T3CFG 0x20 123 | #define PERCFG_T4CFG 0x10 124 | #define PERCFG_U1CFG 0x02 125 | #define PERCFG_U0CFG 0x01 126 | 127 | /* UxCSR */ 128 | #define UCSR_MODE 0x80 129 | #define UCSR_RE 0x40 130 | #define UCSR_SLAVE 0x20 131 | #define UCSR_FE 0x10 132 | #define UCSR_ERR 0x08 133 | #define UCSR_RX_BYTE 0x04 134 | #define UCSR_TX_BYTE 0x02 135 | #define UCSR_ACTIVE 0x01 136 | 137 | /* IEN2 */ 138 | #define IEN2_WDTIE 0x20 139 | #define IEN2_P1IE 0x10 140 | #define IEN2_UTX1IE 0x08 141 | #define IEN2_UTX0IE 0x04 142 | #define IEN2_P2IE 0x02 143 | #define IEN2_RFIE 0x01 144 | 145 | /* PICTL */ 146 | #define PICTL_PADSC 0x40 147 | #define PICTL_P2ICON 0x08 148 | #define PICTL_P1ICONH 0x04 149 | #define PICTL_P1ICONL 0x02 150 | #define PICTL_P0ICON 0x01 151 | 152 | /* DMAARM */ 153 | #define DMAARM_ABORT 0x80 154 | #define DMAARM_DMAARM4 0x10 155 | #define DMAARM_DMAARM3 0x08 156 | #define DMAARM_DMAARM2 0x04 157 | #define DMAARM_DMAARM1 0x02 158 | #define DMAARM_DMAARM0 0x01 159 | 160 | /* DMAREQ */ 161 | #define DMAREQ_DMAREQ4 0x10 162 | #define DMAREQ_DMAREQ3 0x08 163 | #define DMAREQ_DMAREQ2 0x04 164 | #define DMAREQ_DMAREQ1 0x02 165 | #define DMAREQ_DMAREQ0 0x01 166 | 167 | /* DMAIRQ */ 168 | #define DMAIRQ_DMAIF4 0x10 169 | #define DMAIRQ_DMAIF3 0x08 170 | #define DMAIRQ_DMAIF2 0x04 171 | #define DMAIRQ_DMAIF1 0x02 172 | #define DMAIRQ_DMAIF0 0x01 173 | /*--------------------------------------------------------------------------- 174 | * XREG bits, excluding RF and USB 175 | *---------------------------------------------------------------------------*/ 176 | /* FCTL */ 177 | #define FCTL_BUSY 0x80 178 | #define FCTL_FULL 0x40 179 | #define FCTL_ABORT 0x20 180 | #define FCTL_CM1 0x08 181 | #define FCTL_CM0 0x04 182 | #define FCTL_WRITE 0x02 183 | #define FCTL_ERASE 0x01 184 | /*--------------------------------------------------------------------------- 185 | * Radio Register Bits 186 | *---------------------------------------------------------------------------*/ 187 | /* FRMCTRL0 */ 188 | #define FRMCTRL0_APPEND_DATA_MODE 0x80 189 | #define FRMCTRL0_AUTOCRC 0x40 190 | #define FRMCTRL0_AUTOACK 0x20 191 | #define FRMCTRL0_ENERGY_SCAN 0x10 192 | #define FRMCTRL0_RX_MODE1 0x08 193 | #define FRMCTRL0_RX_MODE0 0x04 194 | #define FRMCTRL0_TX_MODE1 0x02 195 | #define FRMCTRL0_TX_MODE0 0x01 196 | 197 | /* FRMCTRL1 */ 198 | #define FRMCTRL1_PENDING_OR 0x04 199 | #define FRMCTRL1_IGNORE_TX_UNDERF 0x02 200 | #define FRMCTRL1_SET_RXENMASK_ON_TX 0x01 201 | 202 | /* FSMSTAT1 */ 203 | #define FSMSTAT1_FIFO 0x80 204 | #define FSMSTAT1_FIFOP 0x40 205 | #define FSMSTAT1_SFD 0x20 206 | #define FSMSTAT1_CCA 0x10 207 | #define FSMSTAT1_TX_ACTIVE 0x02 208 | #define FSMSTAT1_RX_ACTIVE 0x01 209 | 210 | /* RSSISTAT */ 211 | #define RSSISTAT_RSSI_VALID 0x01 212 | 213 | /* RFRND */ 214 | #define RFRND_QRND 0x02 215 | #define RFRND_IRND 0x01 216 | 217 | #endif /* SFR_BITS_H_ */ 218 | -------------------------------------------------------------------------------- /uart.c: -------------------------------------------------------------------------------- 1 | /* 2 | * uart.c 3 | * 4 | * Created on: May 29, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #include "config.h" 38 | #include "cc253x.h" 39 | #include "sfr-bits.h" 40 | #include "uart.h" 41 | #include "errnum.h" 42 | 43 | void uart_init (void) 44 | { 45 | #if (UART_STDOUT_PORT == 0) 46 | UART_SET_SPEED(0, UART_115_M, UART_115_E); 47 | PERCFG &= ~PERCFG_U0CFG; /* alternative 1 = P0.2-5 */ 48 | P0SEL |= 0x0C; /* peripheral select for TX and RX */ 49 | P0DIR |= 0x08; /* TX out */ 50 | P0DIR &= ~0x04; /* RX in */ 51 | U0UCR = 0x02; /* defaults: 8N1, no flow, high stop bit */ 52 | U0CSR = UCSR_MODE | UCSR_RE; /* UART mode, RX enabled */ 53 | U0UCR |= 0x80; /* flush it */ 54 | URX0IE = 1; /* enable RX interrupt */ 55 | #elif (UART_STDOUT_PORT == 1) 56 | /* TODO */ 57 | #endif 58 | } 59 | 60 | void putchar (uint8_t byte) 61 | { 62 | #if (UART_STDOUT_PORT == 0) 63 | U0CSR &= ~UCSR_TX_BYTE; /* Clear TX_BYTE status */ 64 | U0DBUF = byte; 65 | while(!(U0CSR & UCSR_TX_BYTE)); /* Wait until byte has been transmitted. */ 66 | U0CSR &= ~UCSR_TX_BYTE; /* Clear TX_BYTE status */ 67 | #elif (UART_STDOUT_PORT == 1) 68 | U1CSR &= ~UCSR_TX_BYTE; /* Clear TX_BYTE status */ 69 | U1DBUF = byte; 70 | while(!UTX1IF); /* Wait until byte has been transmitted. */ 71 | while(!(U1CSR & UCSR_TX_BYTE)); /* Wait until byte has been transmitted. */ 72 | U1CSR &= ~UCSR_TX_BYTE; /* Clear TX_BYTE status */ 73 | #endif 74 | } 75 | -------------------------------------------------------------------------------- /uart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * uart.h 3 | * 4 | * Created on: May 29, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #ifndef UART_H_ 38 | #define UART_H_ 39 | 40 | #ifdef __cplusplus 41 | extern "C" { 42 | #endif 43 | 44 | #include 45 | 46 | #ifdef UART_CONF_STDOUT_PORT 47 | #define UART_STDOUT_PORT UART_CONF_STDOUT_PORT 48 | #else 49 | #define UART_STDOUT_PORT 0 50 | #endif 51 | 52 | #define UART_SET_SPEED(N, M, E) do{ U##N##BAUD = M; U##N##GCR = E; } while(0) 53 | #define UART_115_M 216 54 | #define UART_115_E 11 55 | 56 | #define UART_LOCK 0x80 57 | 58 | void uart_init (void); 59 | void putchar (uint8_t byte); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* UART_H_ */ 66 | -------------------------------------------------------------------------------- /userprog.c: -------------------------------------------------------------------------------- 1 | /* 2 | * userprog.c 3 | * 4 | * Created on: May 31, 2014 5 | * Author: Ekawahyu Susilo 6 | * 7 | * Copyright (c) 2014, Chongqing Aisenke Electronic Technology Co., Ltd. 8 | * All rights reserved. 9 | * 10 | * Redistribution and use in source and binary forms, with or without 11 | * modification, are permitted provided that the following conditions are met: 12 | * 13 | * 1. Redistributions of source code must retain the above copyright notice, 14 | * this list of conditions and the following disclaimer. 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, 16 | * this list of conditions and the following disclaimer in the documentation 17 | * and/or other materials provided with the distribution. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | * The views and conclusions contained in the software and documentation are 32 | * those of the authors and should not be interpreted as representing official 33 | * policies, either expressed or implied, of the copyright holder. 34 | * 35 | */ 36 | 37 | #include "bootload.h" 38 | 39 | 40 | // this is necessary when the system is still empty 41 | // the line below creates a loop blocking in assembly @ user program start 42 | 43 | __code const __at(USER_PROGRAM_PAGE * 0x800) unsigned char MNEMC_SJMP_NOP[3] = {0x00, 0x80, 0xFD}; 44 | 45 | 46 | // this is necessary when the system is still empty 47 | // the line below puts RETI @ user URX0 interrupt vector address 48 | 49 | __code const __at(USER_PROGRAM_PAGE * 0x800 + 0x13) unsigned char URX0_RETI[1] = {0x32}; 50 | 51 | 52 | // this is necessary when the system is still empty 53 | // the line below puts RETI @ user UTX0 interrupt vector address 54 | 55 | __code const __at(USER_PROGRAM_PAGE * 0x800 + 0x3B) unsigned char UTX0_RETI[1] = {0x32}; 56 | --------------------------------------------------------------------------------