├── .editorconfig ├── .github └── workflows │ └── ci.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── Makefile ├── README.md ├── Vagrantfile ├── analysis ├── .gitignore ├── analysis.py ├── e2e.py ├── format.py ├── launch.py ├── riscv.py └── test │ ├── icache.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ └── entry_0013.json │ ├── sodor1.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ ├── entry_0013.json │ ├── entry_0014.json │ ├── entry_0015.json │ ├── entry_0016.json │ ├── entry_0017.json │ ├── entry_0018.json │ ├── entry_0019.json │ ├── entry_0020.json │ ├── entry_0021.json │ ├── entry_0022.json │ ├── entry_0023.json │ ├── entry_0024.json │ ├── entry_0025.json │ ├── entry_0026.json │ ├── entry_0027.json │ ├── entry_0028.json │ ├── entry_0029.json │ ├── entry_0030.json │ ├── entry_0031.json │ ├── entry_0032.json │ ├── entry_0033.json │ ├── entry_0034.json │ ├── entry_0035.json │ ├── entry_0036.json │ ├── entry_0037.json │ ├── entry_0038.json │ ├── entry_0039.json │ ├── entry_0040.json │ ├── entry_0041.json │ ├── entry_0042.json │ ├── entry_0043.json │ ├── entry_0044.json │ ├── entry_0045.json │ ├── entry_0046.json │ ├── entry_0047.json │ ├── entry_0048.json │ ├── entry_0049.json │ ├── entry_0050.json │ ├── entry_0051.json │ ├── entry_0052.json │ ├── entry_0053.json │ ├── entry_0054.json │ ├── entry_0055.json │ ├── entry_0056.json │ ├── entry_0057.json │ ├── entry_0058.json │ ├── entry_0059.json │ ├── entry_0060.json │ ├── entry_0061.json │ ├── entry_0062.json │ ├── entry_0063.json │ ├── entry_0064.json │ ├── entry_0065.json │ ├── entry_0066.json │ ├── entry_0067.json │ ├── entry_0068.json │ ├── entry_0069.json │ ├── entry_0070.json │ ├── entry_0071.json │ ├── entry_0072.json │ ├── entry_0073.json │ ├── entry_0074.json │ ├── entry_0075.json │ ├── entry_0076.json │ ├── entry_0077.json │ ├── entry_0078.json │ ├── entry_0079.json │ ├── entry_0080.json │ ├── entry_0081.json │ ├── entry_0082.json │ ├── entry_0083.json │ ├── entry_0084.json │ ├── entry_0085.json │ ├── entry_0086.json │ ├── entry_0087.json │ ├── entry_0088.json │ ├── entry_0089.json │ ├── entry_0090.json │ ├── entry_0091.json │ ├── entry_0092.json │ ├── entry_0093.json │ ├── entry_0094.json │ ├── entry_0095.json │ ├── entry_0096.json │ ├── entry_0097.json │ ├── entry_0098.json │ ├── entry_0099.json │ ├── entry_0100.json │ ├── entry_0101.json │ ├── entry_0102.json │ ├── entry_0103.json │ ├── entry_0104.json │ ├── entry_0105.json │ ├── entry_0106.json │ ├── entry_0107.json │ ├── entry_0108.json │ ├── entry_0109.json │ ├── entry_0110.json │ ├── entry_0111.json │ ├── entry_0112.json │ ├── entry_0113.json │ ├── entry_0114.json │ ├── entry_0115.json │ ├── entry_0116.json │ ├── entry_0117.json │ ├── entry_0118.json │ ├── entry_0119.json │ ├── entry_0120.json │ ├── entry_0121.json │ ├── entry_0122.json │ ├── entry_0123.json │ ├── entry_0124.json │ ├── entry_0125.json │ ├── entry_0126.json │ ├── entry_0127.json │ ├── entry_0128.json │ ├── entry_0129.json │ ├── entry_0130.json │ ├── entry_0131.json │ ├── entry_0132.json │ ├── entry_0133.json │ ├── entry_0134.json │ ├── entry_0135.json │ ├── entry_0136.json │ ├── entry_0137.json │ ├── entry_0138.json │ ├── entry_0139.json │ ├── entry_0140.json │ ├── entry_0141.json │ ├── entry_0142.json │ ├── entry_0143.json │ ├── entry_0144.json │ ├── entry_0145.json │ ├── entry_0146.json │ ├── entry_0147.json │ ├── entry_0148.json │ ├── entry_0149.json │ ├── entry_0150.json │ ├── entry_0151.json │ ├── entry_0152.json │ ├── entry_0153.json │ ├── entry_0154.json │ ├── entry_0155.json │ ├── entry_0156.json │ ├── entry_0157.json │ ├── entry_0158.json │ ├── entry_0159.json │ ├── entry_0160.json │ ├── entry_0161.json │ ├── entry_0162.json │ ├── entry_0163.json │ ├── entry_0164.json │ ├── entry_0165.json │ ├── entry_0166.json │ ├── entry_0167.json │ ├── entry_0168.json │ ├── entry_0169.json │ ├── entry_0170.json │ ├── entry_0171.json │ ├── entry_0172.json │ ├── entry_0173.json │ ├── entry_0174.json │ ├── entry_0175.json │ ├── entry_0176.json │ ├── entry_0177.json │ ├── entry_0178.json │ ├── entry_0179.json │ ├── entry_0180.json │ ├── entry_0181.json │ ├── entry_0182.json │ ├── entry_0183.json │ ├── entry_0184.json │ ├── entry_0185.json │ ├── entry_0186.json │ ├── entry_0187.json │ ├── entry_0188.json │ ├── entry_0189.json │ ├── entry_0190.json │ ├── entry_0191.json │ ├── entry_0192.json │ ├── entry_0193.json │ ├── entry_0194.json │ ├── entry_0195.json │ ├── entry_0196.json │ ├── entry_0197.json │ ├── entry_0198.json │ ├── entry_0199.json │ ├── entry_0200.json │ ├── entry_0201.json │ ├── entry_0202.json │ ├── entry_0203.json │ ├── entry_0204.json │ ├── entry_0205.json │ ├── entry_0206.json │ ├── entry_0207.json │ ├── entry_0208.json │ ├── entry_0209.json │ ├── entry_0210.json │ ├── entry_0211.json │ ├── entry_0212.json │ ├── entry_0213.json │ ├── entry_0214.json │ ├── entry_0215.json │ ├── entry_0216.json │ ├── entry_0217.json │ ├── entry_0218.json │ ├── entry_0219.json │ ├── entry_0220.json │ ├── entry_0221.json │ ├── entry_0222.json │ ├── entry_0223.json │ ├── entry_0224.json │ ├── entry_0225.json │ ├── entry_0226.json │ ├── entry_0227.json │ ├── entry_0228.json │ ├── entry_0229.json │ ├── entry_0230.json │ ├── entry_0231.json │ ├── entry_0232.json │ ├── entry_0233.json │ ├── entry_0234.json │ ├── entry_0235.json │ ├── entry_0236.json │ ├── entry_0237.json │ ├── entry_0238.json │ ├── entry_0239.json │ ├── entry_0240.json │ ├── entry_0241.json │ ├── entry_0242.json │ ├── entry_0243.json │ ├── entry_0244.json │ ├── entry_0245.json │ ├── entry_0246.json │ ├── entry_0247.json │ ├── entry_0248.json │ ├── entry_0249.json │ ├── entry_0250.json │ ├── entry_0251.json │ ├── entry_0252.json │ ├── entry_0253.json │ ├── entry_0254.json │ ├── entry_0255.json │ ├── entry_0256.json │ ├── entry_0257.json │ ├── entry_0258.json │ ├── entry_0259.json │ ├── entry_0260.json │ ├── entry_0261.json │ ├── entry_0262.json │ ├── entry_0263.json │ ├── entry_0264.json │ ├── entry_0265.json │ ├── entry_0266.json │ ├── entry_0267.json │ ├── entry_0268.json │ ├── entry_0269.json │ └── entry_0270.json │ ├── sodor3.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ ├── entry_0013.json │ ├── entry_0014.json │ ├── entry_0015.json │ ├── entry_0016.json │ ├── entry_0017.json │ ├── entry_0018.json │ ├── entry_0019.json │ ├── entry_0020.json │ ├── entry_0021.json │ ├── entry_0022.json │ ├── entry_0023.json │ ├── entry_0024.json │ ├── entry_0025.json │ ├── entry_0026.json │ ├── entry_0027.json │ ├── entry_0028.json │ ├── entry_0029.json │ ├── entry_0030.json │ ├── entry_0031.json │ ├── entry_0032.json │ ├── entry_0033.json │ ├── entry_0034.json │ ├── entry_0035.json │ ├── entry_0036.json │ ├── entry_0037.json │ ├── entry_0038.json │ ├── entry_0039.json │ ├── entry_0040.json │ ├── entry_0041.json │ ├── entry_0042.json │ ├── entry_0043.json │ ├── entry_0044.json │ ├── entry_0045.json │ ├── entry_0046.json │ ├── entry_0047.json │ ├── entry_0048.json │ ├── entry_0049.json │ ├── entry_0050.json │ ├── entry_0051.json │ ├── entry_0052.json │ ├── entry_0053.json │ ├── entry_0054.json │ ├── entry_0055.json │ ├── entry_0056.json │ ├── entry_0057.json │ ├── entry_0058.json │ ├── entry_0059.json │ ├── entry_0060.json │ ├── entry_0061.json │ ├── entry_0062.json │ ├── entry_0063.json │ ├── entry_0064.json │ ├── entry_0065.json │ ├── entry_0066.json │ ├── entry_0067.json │ ├── entry_0068.json │ ├── entry_0069.json │ ├── entry_0070.json │ ├── entry_0071.json │ ├── entry_0072.json │ ├── entry_0073.json │ ├── entry_0074.json │ ├── entry_0075.json │ ├── entry_0076.json │ ├── entry_0077.json │ ├── entry_0078.json │ ├── entry_0079.json │ ├── entry_0080.json │ ├── entry_0081.json │ ├── entry_0082.json │ ├── entry_0083.json │ ├── entry_0084.json │ ├── entry_0085.json │ ├── entry_0086.json │ ├── entry_0087.json │ ├── entry_0088.json │ ├── entry_0089.json │ ├── entry_0090.json │ ├── entry_0091.json │ ├── entry_0092.json │ ├── entry_0093.json │ ├── entry_0094.json │ ├── entry_0095.json │ ├── entry_0096.json │ ├── entry_0097.json │ ├── entry_0098.json │ ├── entry_0099.json │ ├── entry_0100.json │ ├── entry_0101.json │ ├── entry_0102.json │ ├── entry_0103.json │ ├── entry_0104.json │ ├── entry_0105.json │ ├── entry_0106.json │ ├── entry_0107.json │ ├── entry_0108.json │ ├── entry_0109.json │ ├── entry_0110.json │ ├── entry_0111.json │ ├── entry_0112.json │ ├── entry_0113.json │ ├── entry_0114.json │ ├── entry_0115.json │ ├── entry_0116.json │ ├── entry_0117.json │ ├── entry_0118.json │ ├── entry_0119.json │ ├── entry_0120.json │ ├── entry_0121.json │ ├── entry_0122.json │ ├── entry_0123.json │ ├── entry_0124.json │ ├── entry_0125.json │ ├── entry_0126.json │ ├── entry_0127.json │ ├── entry_0128.json │ ├── entry_0129.json │ ├── entry_0130.json │ ├── entry_0131.json │ ├── entry_0132.json │ ├── entry_0133.json │ ├── entry_0134.json │ ├── entry_0135.json │ ├── entry_0136.json │ ├── entry_0137.json │ ├── entry_0138.json │ ├── entry_0139.json │ ├── entry_0140.json │ ├── entry_0141.json │ ├── entry_0142.json │ ├── entry_0143.json │ ├── entry_0144.json │ ├── entry_0145.json │ └── entry_0146.json │ └── uart.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ ├── entry_0013.json │ ├── entry_0014.json │ ├── entry_0015.json │ ├── entry_0016.json │ ├── entry_0017.json │ ├── entry_0018.json │ ├── entry_0019.json │ ├── entry_0020.json │ ├── entry_0021.json │ ├── entry_0022.json │ ├── entry_0023.json │ ├── entry_0024.json │ ├── entry_0025.json │ ├── entry_0026.json │ ├── entry_0027.json │ ├── entry_0028.json │ ├── entry_0029.json │ ├── entry_0030.json │ ├── entry_0031.json │ ├── entry_0032.json │ ├── entry_0033.json │ ├── entry_0034.json │ ├── entry_0035.json │ ├── entry_0036.json │ ├── entry_0037.json │ ├── entry_0038.json │ ├── entry_0039.json │ ├── entry_0040.json │ ├── entry_0041.json │ ├── entry_0042.json │ ├── entry_0043.json │ ├── entry_0044.json │ ├── entry_0045.json │ ├── entry_0046.json │ ├── entry_0047.json │ ├── entry_0048.json │ ├── entry_0049.json │ ├── entry_0050.json │ ├── entry_0051.json │ ├── entry_0052.json │ ├── entry_0053.json │ ├── entry_0054.json │ └── entry_0055.json ├── benchmarks ├── FFTSmall.fir ├── ICache.fir ├── ICacheCover.fir ├── NonBlockingDCache.fir ├── Readme.md ├── RocketTile.fir ├── Sodor1Stage.fir ├── Sodor2Stage.fir ├── Sodor3Stage.fir ├── Sodor5Stage.fir ├── TLI2C.fir ├── TLPWM.fir ├── TLSPI.fir ├── TLUART.fir └── gcd.fir ├── doc ├── 2017-12-18_fpga_pc_debugging.log.md └── 2018-03-12_sodor_benchmark_investigation.md ├── e2e ├── .gitignore ├── end_to_end_top.cpp ├── meson.build └── meson_options.txt ├── fpga ├── .gitignore ├── Makefile ├── Readme.md ├── ip │ └── harness │ │ └── component.xml ├── make_bitstream.tcl └── system.tcl ├── fuzzer ├── .cargo │ └── config ├── .gitignore ├── Cargo.toml ├── Readme.md ├── logs │ ├── 2018-02-06_ICache_with_only_deterministic.log │ ├── 2018-02-06_ICache_with_only_deterministic_and_4_cylces.log │ ├── 2018-02-06_ICache_with_only_random.log │ ├── 2018-02-06_ICache_with_random.log │ ├── 2018-02-13_ICache_with_havoc_12_cycle_input.log │ ├── 2018-02-13_ICache_with_havoc_15_cycle_input_assertion_violation.log │ ├── 2018-02-22_ICache_with_new_havoc_for_1h+_18_billion_cycles.log │ ├── 2018-03-06_DCache_havoc_90_min.log │ └── 2018-03-15_Sodor_1Stage_T_F_Latch_4h.log └── src │ ├── analysis.rs │ ├── config.rs │ ├── main.rs │ ├── mutation │ ├── format.rs │ ├── mod.rs │ └── mutators.rs │ ├── queue.rs │ ├── run │ ├── afl.rs │ ├── buffered.rs │ ├── history.rs │ ├── mod.rs │ ├── pynq.rs │ ├── pynqchannel.rs │ ├── rwint.rs │ └── shmem.rs │ ├── stats.rs │ └── test.rs ├── harness ├── .gitignore ├── build.sbt ├── src │ ├── freechips │ │ └── rocketchip │ │ │ └── util │ │ │ └── RecordMap.scala │ └── rfuzz │ │ ├── Config.scala │ │ ├── DUT.scala │ │ ├── HarnessGenerator.scala │ │ ├── VerilatorHarness.scala │ │ └── coverage.scala └── test │ └── rfuzz │ └── HarnessSpec.scala ├── instrumentation ├── .gitignore ├── build.sbt ├── project │ └── build.properties ├── src │ ├── .editorconfig │ └── rfuzz │ │ ├── MetaReset.scala │ │ ├── NoDedup.scala │ │ ├── ProfilingTransform.scala │ │ ├── ReplaceMems.scala │ │ ├── SparseMem.scala │ │ ├── SplitMuxConditions.scala │ │ ├── TomlGenerator.scala │ │ └── package.scala └── test │ └── rfuzz │ └── SparseMemSpec.scala ├── midas ├── .gitignore ├── Makefile ├── build.sbt ├── lib │ └── src │ │ └── main │ │ └── scala │ │ ├── config │ │ └── Config.scala │ │ └── util │ │ ├── Arbiters.scala │ │ ├── Misc.scala │ │ └── MultiWidthFifo.scala ├── project │ ├── build.properties │ └── plugins.sbt ├── src │ └── main │ │ ├── cc │ │ ├── rfuzz-emul.cc │ │ ├── rfuzz-zynq.cc │ │ └── rfuzz.h │ │ └── scala │ │ └── midas.scala └── zynq.mk ├── results ├── 1.jqf2.i2c.log ├── 1.jqf2.i2c.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ ├── entry_0013.json │ ├── entry_0014.json │ ├── entry_0015.json │ ├── entry_0016.json │ ├── entry_0017.json │ ├── entry_0018.json │ ├── entry_0019.json │ ├── entry_0020.json │ ├── entry_0021.json │ ├── entry_0022.json │ ├── entry_0023.json │ ├── entry_0024.json │ ├── entry_0025.json │ ├── entry_0026.json │ ├── entry_0027.json │ ├── entry_0028.json │ ├── entry_0029.json │ ├── entry_0030.json │ ├── entry_0031.json │ ├── entry_0032.json │ ├── entry_0033.json │ ├── entry_0034.json │ ├── entry_0035.json │ ├── entry_0036.json │ ├── entry_0037.json │ ├── entry_0038.json │ ├── entry_0039.json │ ├── entry_0040.json │ ├── entry_0041.json │ ├── entry_0042.json │ ├── entry_0043.json │ ├── entry_0044.json │ ├── entry_0045.json │ ├── entry_0046.json │ ├── entry_0047.json │ ├── entry_0048.json │ ├── entry_0049.json │ ├── entry_0050.json │ ├── entry_0051.json │ ├── entry_0052.json │ ├── entry_0053.json │ ├── entry_0054.json │ ├── entry_0055.json │ ├── entry_0056.json │ ├── entry_0057.json │ ├── entry_0058.json │ ├── entry_0059.json │ ├── entry_0060.json │ ├── entry_0061.json │ ├── entry_0062.json │ ├── entry_0063.json │ ├── entry_0064.json │ ├── entry_0065.json │ ├── entry_0066.json │ ├── entry_0067.json │ ├── entry_0068.json │ ├── entry_0069.json │ ├── entry_0070.json │ ├── entry_0071.json │ ├── entry_0072.json │ ├── entry_0073.json │ ├── entry_0074.json │ ├── entry_0075.json │ ├── entry_0076.json │ ├── entry_0077.json │ ├── entry_0078.json │ ├── entry_0079.json │ ├── entry_0080.json │ ├── entry_0081.json │ ├── entry_0082.json │ ├── entry_0083.json │ ├── entry_0084.json │ ├── entry_0085.json │ ├── entry_0086.json │ ├── entry_0087.json │ ├── entry_0088.json │ ├── entry_0089.json │ ├── entry_0090.json │ ├── entry_0091.json │ ├── entry_0092.json │ ├── entry_0093.json │ ├── entry_0094.json │ ├── entry_0095.json │ └── entry_0096.json ├── 4.jqf2.i2c.log ├── 4.jqf2.i2c.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ ├── entry_0013.json │ ├── entry_0014.json │ ├── entry_0015.json │ ├── entry_0016.json │ ├── entry_0017.json │ ├── entry_0018.json │ ├── entry_0019.json │ ├── entry_0020.json │ ├── entry_0021.json │ ├── entry_0022.json │ ├── entry_0023.json │ ├── entry_0024.json │ ├── entry_0025.json │ ├── entry_0026.json │ ├── entry_0027.json │ ├── entry_0028.json │ ├── entry_0029.json │ ├── entry_0030.json │ ├── entry_0031.json │ ├── entry_0032.json │ ├── entry_0033.json │ ├── entry_0034.json │ ├── entry_0035.json │ ├── entry_0036.json │ ├── entry_0037.json │ ├── entry_0038.json │ ├── entry_0039.json │ ├── entry_0040.json │ ├── entry_0041.json │ ├── entry_0042.json │ ├── entry_0043.json │ ├── entry_0044.json │ ├── entry_0045.json │ ├── entry_0046.json │ ├── entry_0047.json │ ├── entry_0048.json │ ├── entry_0049.json │ ├── entry_0050.json │ ├── entry_0051.json │ ├── entry_0052.json │ ├── entry_0053.json │ ├── entry_0054.json │ ├── entry_0055.json │ ├── entry_0056.json │ ├── entry_0057.json │ ├── entry_0058.json │ ├── entry_0059.json │ ├── entry_0060.json │ ├── entry_0061.json │ ├── entry_0062.json │ ├── entry_0063.json │ ├── entry_0064.json │ ├── entry_0065.json │ ├── entry_0066.json │ ├── entry_0067.json │ ├── entry_0068.json │ ├── entry_0069.json │ ├── entry_0070.json │ ├── entry_0071.json │ ├── entry_0072.json │ ├── entry_0073.json │ ├── entry_0074.json │ ├── entry_0075.json │ ├── entry_0076.json │ ├── entry_0077.json │ ├── entry_0078.json │ ├── entry_0079.json │ ├── entry_0080.json │ ├── entry_0081.json │ ├── entry_0082.json │ ├── entry_0083.json │ ├── entry_0084.json │ ├── entry_0085.json │ ├── entry_0086.json │ ├── entry_0087.json │ ├── entry_0088.json │ ├── entry_0089.json │ ├── entry_0090.json │ ├── entry_0091.json │ ├── entry_0092.json │ ├── entry_0093.json │ ├── entry_0094.json │ ├── entry_0095.json │ ├── entry_0096.json │ ├── entry_0097.json │ ├── entry_0098.json │ ├── entry_0099.json │ ├── entry_0100.json │ └── entry_0101.json ├── Readme.md └── rocket.out │ ├── config.json │ ├── entry_0000.json │ ├── entry_0001.json │ ├── entry_0002.json │ ├── entry_0003.json │ ├── entry_0004.json │ ├── entry_0005.json │ ├── entry_0006.json │ ├── entry_0007.json │ ├── entry_0008.json │ ├── entry_0009.json │ ├── entry_0010.json │ ├── entry_0011.json │ ├── entry_0012.json │ ├── entry_0013.json │ ├── entry_0014.json │ ├── entry_0015.json │ ├── entry_0016.json │ ├── entry_0017.json │ ├── entry_0018.json │ ├── entry_0019.json │ ├── entry_0020.json │ ├── entry_0021.json │ ├── entry_0022.json │ ├── entry_0023.json │ ├── entry_0024.json │ ├── entry_0025.json │ ├── entry_0026.json │ ├── entry_0027.json │ ├── entry_0028.json │ ├── entry_0029.json │ ├── entry_0030.json │ ├── entry_0031.json │ ├── entry_0032.json │ ├── entry_0033.json │ ├── entry_0034.json │ ├── entry_0035.json │ ├── entry_0036.json │ ├── entry_0037.json │ ├── entry_0038.json │ ├── entry_0039.json │ ├── entry_0040.json │ ├── entry_0041.json │ ├── entry_0042.json │ ├── entry_0043.json │ ├── entry_0044.json │ ├── entry_0045.json │ ├── entry_0046.json │ ├── entry_0047.json │ ├── entry_0048.json │ ├── entry_0049.json │ ├── entry_0050.json │ ├── entry_0051.json │ ├── entry_0052.json │ ├── entry_0053.json │ ├── entry_0054.json │ ├── entry_0055.json │ ├── entry_0056.json │ ├── entry_0057.json │ ├── entry_0058.json │ ├── entry_0059.json │ ├── entry_0060.json │ ├── entry_0061.json │ ├── entry_0062.json │ ├── entry_0063.json │ ├── entry_0064.json │ ├── entry_0065.json │ ├── entry_0066.json │ ├── entry_0067.json │ ├── entry_0068.json │ ├── entry_0069.json │ ├── entry_0070.json │ ├── entry_0071.json │ ├── entry_0072.json │ ├── entry_0073.json │ ├── entry_0074.json │ ├── entry_0075.json │ ├── entry_0076.json │ ├── entry_0077.json │ ├── entry_0078.json │ ├── entry_0079.json │ ├── entry_0080.json │ ├── entry_0081.json │ ├── entry_0082.json │ ├── entry_0083.json │ ├── entry_0084.json │ ├── entry_0085.json │ └── entry_0086.json └── verilator ├── .gitignore ├── afl.c ├── afl.h ├── afl.hpp ├── dut_gen.py ├── fpga_queue.cpp ├── fpga_queue.hpp ├── fuzzer.hpp ├── meson.build ├── meson_options.txt ├── top.cpp └── verilator.py /.editorconfig: -------------------------------------------------------------------------------- 1 | # EditorConfig is awesome: http://EditorConfig.org 2 | 3 | # top-most EditorConfig file 4 | root = true 5 | 6 | # Kevin's Scala Style 7 | 8 | [*.scala] 9 | end_of_line = lf 10 | charset = utf-8 11 | indent_style = tab 12 | 13 | # indent_size = 4 14 | 15 | [*.py] 16 | end_of_line = lf 17 | charset = utf-8 18 | indent_style = tab 19 | -------------------------------------------------------------------------------- /.github/workflows/ci.yml: -------------------------------------------------------------------------------- 1 | name: rfuzz Instrumentation and Harness CI 2 | 3 | on: 4 | push: 5 | branches: [ master ] 6 | pull_request: 7 | branches: [ master ] 8 | 9 | jobs: 10 | icache: 11 | name: Instrument ICaches 12 | runs-on: ubuntu-latest 13 | 14 | steps: 15 | - uses: actions/checkout@v2 16 | 17 | - name: Install Dependencies 18 | run: sudo apt-get install -y build-essential meson pkg-config verilator python3-toml 19 | 20 | - name: Set up JDK 11 21 | uses: actions/setup-java@v1 22 | with: 23 | java-version: 11 24 | 25 | - name: ICache 26 | run: make FIR=ICache.fir DUT=ICache bin 27 | 28 | - name: ICache w/ Coverage 29 | run: | 30 | make FIR=ICacheCover.fir DUT=ICache clean 31 | make FIR=ICacheCover.fir DUT=ICache bin 32 | 33 | dcache: 34 | name: Instrument DCache 35 | runs-on: ubuntu-latest 36 | 37 | steps: 38 | - uses: actions/checkout@v2 39 | 40 | - name: Install Dependencies 41 | run: sudo apt-get install -y build-essential meson pkg-config verilator python3-toml 42 | 43 | - name: Set up JDK 11 44 | uses: actions/setup-java@v1 45 | with: 46 | java-version: 11 47 | 48 | - name: Non-Blocking Data Cache 49 | run: make FIR=NonBlockingDCache.fir DUT=NonBlockingDCache bin 50 | 51 | sodor: 52 | name: Instrument Sodor Cores 53 | runs-on: ubuntu-latest 54 | 55 | steps: 56 | - uses: actions/checkout@v2 57 | 58 | - name: Install Dependencies 59 | run: sudo apt-get install -y build-essential meson pkg-config verilator python3-toml 60 | 61 | - name: Set up JDK 11 62 | uses: actions/setup-java@v1 63 | with: 64 | java-version: 11 65 | 66 | - name: Sodor 1-Stage 67 | run: make FIR=Sodor1Stage.fir DUT=Sodor1Stage bin 68 | 69 | - name: Sodor 3-Stage 70 | run: make FIR=Sodor3Stage.fir DUT=Sodor3Stage bin 71 | 72 | - name: Sodor 5-Stage 73 | run: make FIR=Sodor5Stage.fir DUT=Sodor5Stage bin 74 | 75 | 76 | peripheral: 77 | name: Instrument TileLink Peripherals 78 | runs-on: ubuntu-latest 79 | 80 | steps: 81 | - uses: actions/checkout@v2 82 | 83 | - name: Install Dependencies 84 | run: sudo apt-get install -y build-essential meson pkg-config verilator python3-toml 85 | 86 | - name: Set up JDK 11 87 | uses: actions/setup-java@v1 88 | with: 89 | java-version: 11 90 | 91 | - name: I2C Peripheral 92 | run: make FIR=TLI2C.fir DUT=TLI2C bin 93 | 94 | - name: PWM Peripheral 95 | run: make FIR=TLPWM.fir DUT=TLPWM bin 96 | 97 | - name: SPI Peripheral 98 | run: make FIR=TLSPI.fir DUT=TLSPI bin 99 | 100 | - name: UART Peripheral 101 | run: make FIR=TLUART.fir DUT=TLUART bin 102 | 103 | 104 | fft: 105 | name: Instrument FFT 106 | runs-on: ubuntu-latest 107 | 108 | steps: 109 | - uses: actions/checkout@v2 110 | 111 | - name: Install Dependencies 112 | run: sudo apt-get install -y build-essential meson pkg-config verilator python3-toml 113 | 114 | - name: Set up JDK 11 115 | uses: actions/setup-java@v1 116 | with: 117 | java-version: 11 118 | 119 | - name: FFT Small 120 | run: make FIR=FFTSmall.fir DUT=FFTSmall bin 121 | 122 | 123 | rocket: 124 | name: Instrument Rocket Chip w/o Verilator Compilation 125 | runs-on: ubuntu-latest 126 | 127 | steps: 128 | - uses: actions/checkout@v2 129 | 130 | - name: Install Dependencies 131 | run: sudo apt-get install -y python3-toml 132 | 133 | - name: Set up JDK 11 134 | uses: actions/setup-java@v1 135 | with: 136 | java-version: 11 137 | 138 | - name: Rocket Chip Tile 139 | run: make FIR=RocketTile.fir DUT=RocketTile 140 | 141 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | .ivy2 3 | *.stamp 4 | 5 | # toplevel log files are ignored 6 | # move them to doc or fuzzer/log 7 | # if you want to commit them 8 | /*.log 9 | 10 | # CPython 11 | __pycache__/ 12 | *.pyc 13 | 14 | # Vim 15 | *.swp 16 | 17 | # IntelliJ Idea 18 | .idea/ 19 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "harness/midas"] 2 | path = midas/midas 3 | url = git@github.com:ucb-bar/midas.git 4 | [submodule "midas/barstools"] 5 | path = midas/barstools 6 | url = git@github.com:ucb-bar/barstools.git 7 | [submodule "midas/platforms/zynq"] 8 | path = midas/platforms/zynq 9 | url = git@github.com:ucb-bar/midas-zynq.git 10 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2017 - 2018, The Regents of the University of California 4 | All rights reserved. 5 | 6 | Redistribution and use in source and binary forms, with or without 7 | modification, are permitted provided that the following conditions are met: 8 | 9 | * Redistributions of source code must retain the above copyright notice, this 10 | list of conditions and the following disclaimer. 11 | 12 | * Redistributions in binary form must reproduce the above copyright notice, 13 | this list of conditions and the following disclaimer in the documentation 14 | and/or other materials provided with the distribution. 15 | 16 | * Neither the name of the copyright holder nor the names of its 17 | contributors may be used to endorse or promote products derived from 18 | this software without specific prior written permission. 19 | 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 24 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 27 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | -------------------------------------------------------------------------------- /Vagrantfile: -------------------------------------------------------------------------------- 1 | # -*- mode: ruby -*- 2 | 3 | $box = "ubuntu/bionic64" 4 | $mem = "2048" 5 | 6 | $install_script = <<-SCRIPT 7 | apt-get update -y 8 | apt-get upgrade -y 9 | apt-get install build-essential meson pkg-config openjdk-8-jdk verilator cargo -y 10 | apt-get install python3-toml python3-numpy python3-matplotlib graphviz -y 11 | echo "Installing SBT" 12 | echo "deb https://dl.bintray.com/sbt/debian /" | tee -a /etc/apt/sources.list.d/sbt.list 13 | apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823 14 | apt-get update -y 15 | apt-get install sbt -y 16 | SCRIPT 17 | 18 | $config_script = <<-SCRIPT 19 | mkdir -p ~/.config/matplotlib/ 20 | echo "backend: agg" > ~/.config/matplotlib/matplotlibrc 21 | SCRIPT 22 | 23 | $clone_script = <<-SCRIPT 24 | git clone https://github.com/ekiwi/rfuzz.git 25 | cd rfuzz 26 | sed -i 's/git@github.com:/https:\\/\\/github.com\\//' .gitmodules 27 | git submodule update --init 28 | SCRIPT 29 | 30 | Vagrant.configure("2") do |config| 31 | config.vm.box = $box 32 | config.vm.provider "virtualbox" do |vb| 33 | vb.memory = $mem 34 | end 35 | config.vm.provision "install", type: "shell", privileged: true, inline: $install_script 36 | config.vm.provision "config", type: "shell", privileged: false, inline: $config_script 37 | config.vm.provision "clone", type: "shell", privileged: false, inline: $clone_script 38 | end 39 | -------------------------------------------------------------------------------- /analysis/.gitignore: -------------------------------------------------------------------------------- 1 | # analysis artifacts 2 | *.dot 3 | *.png 4 | *.pdf 5 | 6 | # launch.py 7 | *.out 8 | -------------------------------------------------------------------------------- /analysis/riscv.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # -*- coding: utf-8 -*- 3 | 4 | # Copyright 2018, University of California, Berkeley 5 | # author: Kevin Laeufer 6 | 7 | import os, subprocess 8 | from format import InputFormat, Input 9 | 10 | dasm_bin = None if 'RISCV' not in os.environ else os.path.join(os.environ['RISCV'], 'bin', 'spike-dasm') 11 | 12 | def dasm(instruction): 13 | hx = "DASM({:x})\n".format(instruction).encode('ASCII') 14 | rr = subprocess.run([dasm_bin], input=hx, check=True, stdout=subprocess.PIPE) 15 | return rr.stdout.decode('ASCII').strip() 16 | 17 | def print_instructions(inputs): 18 | for inp in inputs: 19 | print("-------------------------------------------") 20 | print("- {} Entry:".format(inp.id)) 21 | # for ii, cc, bb, raw in zip(range(inp.cycles), inp.formated, inp.bytes, inp.inputs): 22 | # print("{}: {}".format(ii, raw)) 23 | # print("{}: {}".format(ii, bb)) 24 | # print("{}: {}".format(ii, cc)) 25 | for ii, cc in enumerate(inp.formated): 26 | valid = cc['io_imem_resp_valid'] 27 | #skip = (valid == 0) 28 | skip = False 29 | if not skip: 30 | binary = cc['io_imem_resp_bits_data'] 31 | instruction = dasm(binary) 32 | print("{}: ({}) {:08x} -> {}".format(ii, valid, binary, instruction)) -------------------------------------------------------------------------------- /analysis/test/sodor3.out/entry_0000.json: -------------------------------------------------------------------------------- 1 | {"entry":{"id":0,"inputs":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lineage":null,"discovered_after":{"secs":0,"nanos":0},"mutation_history":{"finished":[]}},"stats":{"mutators":[{"name":"arith 8/8","id":30064836608,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 2/1","id":8590000128,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 8/8","id":17179934720,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 1/1","id":4295032832,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"interest 16/8","id":47244705792,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"arith 32/8","id":38654771200,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 4/1","id":12884967424,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 32/8","id":25769869312,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"interest 32/8","id":51539673088,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"random biflips","id":429496729601,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 16/8","id":21474902016,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"interest 8/8","id":42949738496,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"arith 16/8","id":34359803904,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"afl havoc","id":472446402561,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}}],"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0},"cycles_per_test":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0},"cycles_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0},"runtime":{"secs":0,"nanos":337017}}} -------------------------------------------------------------------------------- /analysis/test/sodor3.out/entry_0001.json: -------------------------------------------------------------------------------- 1 | {"entry":{"id":1,"inputs":[1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lineage":{"parent":0,"mutation":{"mutator":{"id":4295032832,"seed":null},"ii":0}},"discovered_after":{"secs":0,"nanos":99364878},"mutation_history":{"finished":[]}},"stats":{"mutators":[{"name":"arith 8/8","id":30064836608,"test_count":2800,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":13822860.048478745,"global_numerator":2800.0,"global_denominator":0.000202563,"local":13822860.048478745,"local_numerator":2800.0,"local_denominator":0.000202563}},{"name":"bitflip 2/1","id":8590000128,"test_count":319,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":13671037.970343704,"global_numerator":319.0,"global_denominator":0.000023334,"local":13671037.970343704,"local_numerator":319.0,"local_denominator":0.000023334}},{"name":"bitflip 8/8","id":17179934720,"test_count":40,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":13812154.696132595,"global_numerator":40.0,"global_denominator":0.0000028960000000000005,"local":13812154.696132595,"local_numerator":40.0,"local_denominator":0.0000028960000000000005}},{"name":"bitflip 1/1","id":4295032832,"test_count":320,"discovery_count":1,"last_discovery_after":{"secs":0,"nanos":99364878},"tests_per_second":{"global":399683.2510235638,"global_numerator":320.0,"global_denominator":0.000800634,"local":399683.2510235638,"local_numerator":320.0,"local_denominator":0.000800634}},{"name":"interest 16/8","id":47244705792,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"arith 32/8","id":38654771200,"test_count":0,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":null,"global_numerator":0.0,"global_denominator":0.0,"local":null,"local_numerator":0.0,"local_denominator":0.0}},{"name":"bitflip 4/1","id":12884967424,"test_count":317,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":13889497.436796213,"global_numerator":317.0,"global_denominator":0.000022823,"local":13889497.436796213,"local_numerator":317.0,"local_denominator":0.000022823}},{"name":"bitflip 32/8","id":25769869312,"test_count":37,"discovery_count":0,"last_discovery_after":null,"tests_per_second":{"global":13988657.844990548,"global_numerator":37.0,"global_denominator":0.000002645,"local":13988657.844990548,"local_numerator":37.0,"local_denominator":0.000002645}},{"name":"interest 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-------------------------------------------------------------------------------- 1 | circuit gcd : 2 | module gcd: 3 | input clock : Clock 4 | input reset : UInt<1> 5 | output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : UInt<32>, b : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}} 6 | io is invalid 7 | 8 | reg busy : UInt<1>, clock with : 9 | reset => (reset, UInt<1>("h0")) 10 | reg done : UInt<1>, clock with : 11 | reset => (reset, UInt<1>("h0")) 12 | reg x : UInt<32>, clock with : 13 | reset => (reset, UInt<32>("h0")) 14 | reg y : UInt<32>, clock with : 15 | reset => (reset, UInt<32>("h0")) 16 | node T_40 = eq(busy, UInt<1>("h0")) 17 | io.in.ready <= T_40 18 | io.out.valid <= done 19 | node T_42 = eq(y, UInt<1>("h0")) 20 | node T_43 = and(busy, T_42) 21 | when T_43 : 22 | done <= UInt<1>("h1") 23 | skip 24 | node T_45 = and(done, io.out.ready) 25 | when T_45 : 26 | busy <= UInt<1>("h0") 27 | skip 28 | node start = and(io.in.valid, io.in.ready) 29 | when start : 30 | busy <= UInt<1>("h1") 31 | done <= UInt<1>("h0") 32 | skip 33 | node T_50 = gt(x, y) 34 | when T_50 : 35 | node T_51 = sub(x, y) 36 | node T_52 = tail(T_51, 1) 37 | x <= T_52 38 | skip 39 | node T_54 = eq(T_50, UInt<1>("h0")) 40 | when T_54 : 41 | node T_55 = sub(y, x) 42 | node T_56 = tail(T_55, 1) 43 | y <= T_56 44 | skip 45 | when start : 46 | x <= io.in.bits.a 47 | y <= io.in.bits.b 48 | skip 49 | io.out.bits <= x 50 | 51 | -------------------------------------------------------------------------------- /doc/2017-12-18_fpga_pc_debugging.log.md: -------------------------------------------------------------------------------- 1 | # Problem on the PC 2 | get_info(TestId(17601)) -> BufferSlot { id: 12, offset: 1220 } 3 | 4 | Pc + one_fuzz: 5 | -------------- 6 | input: [1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] 7 | -> cov: [3, 0, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0, 0] 8 | 9 | 10 | PC + normal fuzzing: 11 | -------------------- 12 | input: [1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] 13 | -> cov: [3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 0, 0, 0, 0] 14 | 15 | 16 | => difference in coverage... 17 | 18 | -> cov: [3, 0, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0, 0] 19 | vs 20 | -> cov: [3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 3, 0, 0, 0, 0, 0] 21 | ^ ^ 22 | ---- 23 | 24 | hm.... 25 | 26 | 27 | ################################################################################ 28 | 29 | # Problem on the FPGA 30 | get_info(TestId(17728)) -> BufferSlot { id: 12, offset: 1347 } 31 | 32 | 33 | FPGA: 34 | ----- 35 | 36 | New Interesting Input: TestId(17728) 37 | input: [1, 0, 0, 0, 0, 0, 0, 0, 38 | 0, 0, 0, 0, 0, 0, 0, 0, 39 | 0, 0, 0, 0, 0, 0, 0, 0, 40 | 128, 0, 0, 0, 0, 0, 0, 0, 41 | 0, 0, 0, 0, 0, 0, 0, 0, 42 | 0, 0, 0, 0, 0, 0, 0, 0] 43 | -> cov: [2, 0, 3, 1, 2, 0, 3, 1, 2, 1, 2, 0, 0, 0, 0, 0] 44 | -> cov: [2, 0, 3, 1, 2, 0, 3, 1, 2, 1, 2, 0, 0, 0, 0, 0] 45 | 46 | FPGA fuzz_one: 47 | -------------- 48 | -> cov: [2, 0, 3, 1, 2, 0, 3, 3, 0, 1, 2, 0, 0, 0, 0, 0] 49 | 50 | 51 | PC + one_fuzz 52 | ------------- 53 | input: [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] 54 | -> cov: [2, 0, 3, 1, 2, 0, 3, 3, 0, 1, 2, 0, 0, 0, 0, 0] 55 | 56 | 57 | 58 | 59 | => difference in coverage .... 60 | 61 | -> cov: [2, 0, 3, 1, 2, 0, 3, 1, 2, 1, 2, 0, 0, 0, 0, 0] 62 | vs 63 | -> cov: [2, 0, 3, 1, 2, 0, 3, 3, 0, 1, 2, 0, 0, 0, 0, 0] 64 | ^ ^ 65 | 66 | 67 | --> seems to all depend on position in buffer .... hm 68 | 69 | 70 | 71 | [1, 0, 0, 0, 0, 0, 0, 0,80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] 72 | [1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] 73 | 74 | 75 | -------------------------------------------------------------------------------- /doc/2018-03-12_sodor_benchmark_investigation.md: -------------------------------------------------------------------------------- 1 | # RISC-V Sodor Benchmark Investigation 2 | 3 | Trying to see if the riscv sodor educational cores would make for a 4 | good benchmark for our fuzzer. 5 | 6 | ## Potentially interesting bugs 7 | * 41ae6c Fixed bug with Seq/NonSeq memories 8 | * 080afd Fixed unbypassed 5-stage 9 | 10 | -------------------------------------------------------------------------------- /e2e/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | build/ 3 | -------------------------------------------------------------------------------- /e2e/end_to_end_top.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2018, University of California, Berkeley 2 | // author: Kevin Laeufer 3 | 4 | // This file contains the top level for measuring the end -to-end coverage 5 | // of a test input corpus generated by our fuzzer. 6 | // This allows us to measure very detailed coverage in a manner independent 7 | // from our fuzzer which makes things easier and more reliable to compare. 8 | 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | #include 17 | #include 18 | 19 | #define E2E 20 | #include "dut.hpp" 21 | 22 | 23 | #include 24 | #if VM_TRACE 25 | # include // Trace file format header 26 | #endif 27 | 28 | // Override Verilator definition so first $finish ends simulation 29 | // Note: VL_USER_FINISH needs to be defined when compiling Verilator code 30 | void vl_finish(const char* filename, int linenum, const char* hier) { 31 | Verilated::flushCall(); 32 | exit(0); 33 | } 34 | 35 | using namespace std; 36 | 37 | struct Simulation { 38 | TOP_TYPE* top = nullptr; 39 | vluint64_t main_time = 0; 40 | VerilatedVcdC* tfp = nullptr; 41 | void step() { 42 | top->clock = 0; 43 | top->eval(); 44 | #if VM_TRACE 45 | if (tfp) { tfp->dump(main_time); } 46 | #endif 47 | main_time++; 48 | top->clock = 1; 49 | top->eval(); 50 | #if VM_TRACE 51 | if (tfp) { tfp->dump(main_time); } 52 | #endif 53 | main_time++; 54 | } 55 | uint64_t cycles() { return main_time / 2; } 56 | }; 57 | 58 | static inline std::vector load_test(const std::string& filename) { 59 | std::ifstream in(filename, std::ios::binary); 60 | assert(in.is_open()); 61 | in.seekg(0, std::ios::end); 62 | auto len = in.tellg(); 63 | in.seekg(0, std::ios::beg); 64 | std::vector out; 65 | out.resize(len); 66 | in.read((char*)out.data(), len); 67 | return out; 68 | } 69 | 70 | double sc_time_stamp () { throw std::logic_error("calling sc_time_stamp is not supported!"); } 71 | #define ERROR(reason) { std::cout << "{\"error\": \"" reason "\"}" << std::endl; return 1; } 72 | int main(int argc, char** argv) { 73 | 74 | if(argc != 2) { ERROR("argcount"); } 75 | std::string filename(argv[1]); 76 | 77 | Simulation sim; 78 | sim.top = new TOP_TYPE; 79 | 80 | // load test data 81 | const auto in = load_test(filename); 82 | const int64_t cycles = in.size() / InputSize; 83 | if(cycles * InputSize != in.size()) { ERROR("size"); } 84 | 85 | // If verilator was invoked with --trace 86 | #if VM_TRACE 87 | Verilated::traceEverOn(true); 88 | sim.tfp = new VerilatedVcdC; 89 | sim.top->trace(sim.tfp, 99); 90 | sim.tfp->open ("dump.vcd"); 91 | #endif 92 | 93 | sim.top->reset = 0; 94 | // meta reset circuit for one cycle 95 | sim.top->io_meta_reset = 1; 96 | sim.step(); 97 | sim.top->io_meta_reset = 0; 98 | // reset circuit for one cycles 99 | sim.top->reset = 1; 100 | sim.step(); 101 | sim.top->reset = 0; 102 | // run for as many cycles as we get data 103 | for(auto ii = 0; ii < cycles; ++ii) { 104 | auto input = in.data() + (InputSize * ii); 105 | apply_input(sim.top, input); 106 | sim.step(); 107 | } 108 | uint8_t coverage[CoverageSize]; 109 | read_coverage(sim.top, coverage); 110 | std::cout << "{\"coverage\": [" << (int)coverage[0]; 111 | for(auto ii = 1; ii < (int)CoverageSize; ++ii) { 112 | std::cout << ", " << (int)coverage[ii]; 113 | } 114 | std::cout << "]}" << std::endl; 115 | 116 | 117 | // finish last cycle 118 | sim.top->eval(); 119 | #if VM_TRACE 120 | if (sim.tfp) { sim.tfp->dump(sim.main_time); } 121 | if (sim.tfp) { sim.tfp->close(); } 122 | #endif 123 | } 124 | 125 | -------------------------------------------------------------------------------- /e2e/meson.build: -------------------------------------------------------------------------------- 1 | project('coverage', 'cpp', default_options : ['cpp_std=c++11'], version: '0.0.1') 2 | 3 | 4 | # generate verilator 5 | # TODO: integrate sbt 6 | # sbt = find_program('sbt') 7 | # verilog = custom_target('chisel', 8 | # output : 'UartDecoder.v', 9 | # input : '../src/main/scala/UartDecoder.scala', 10 | # depend_files: '../build.sbt', 11 | # command : [sbt, '"run -X verilog --target-dir ."']) 12 | 13 | dut = get_option('dut') 14 | build = get_option('build_dir') 15 | top = '@0@/@1@_E2EHarness.v'.format(build, dut) 16 | dependencies = ['@0@/@1@.v'.format(build, dut)] 17 | toml = '@0@/@1@.toml'.format(build, dut) 18 | exe = 'cov' 19 | 20 | # custom verilator target 21 | verilator_py = find_program('../verilator/verilator.py') 22 | verilator = dependency('verilator', version: '>= 3.886') 23 | verilator_defines = ['-DVL_PRINTF=printf', '-DVM_COVERAGE=0', '-DVM_SC=0', '-DVL_USER_FINISH'] 24 | verilator_warnings = ['-Wno-char-subscripts', '-Wno-sign-compare', 25 | '-Wno-uninitialized', '-Wno-unused-but-set-variable', 26 | '-Wno-unused-parameter', '-Wno-unused-variable'] 27 | toplevel = '@0@_E2EHarness'.format(dut) 28 | verilator_files = ['V@0@.h'.format(toplevel), 29 | 'V@0@__Syms.h'.format(toplevel), 30 | #'V@0@__Inlines.h'.format(toplevel), 31 | 'V@0@.cpp'.format(toplevel), 32 | 'V@0@__Syms.cpp'.format(toplevel), 33 | 'verilated_vcd_c.cpp', 'verilated.cpp'] 34 | if get_option('trace') 35 | verilator_cmd = [verilator_py, '--trace'] 36 | verilator_defines += ['-DVM_TRACE=1'] 37 | verilator_files += ['V@0@__Trace.cpp'.format(toplevel), 38 | 'V@0@__Trace__Slow.cpp'.format(toplevel)] 39 | else 40 | verilator_cmd = [verilator_py] 41 | endif 42 | # TODO: potentially change to be a `generator`: http://mesonbuild.com/Generating-sources.html 43 | verilator_src = custom_target('verilator', 44 | output : verilator_files, 45 | input : [top] + dependencies, 46 | command : verilator_cmd + ['-o', '@OUTPUT@', '-i', '@INPUT@']) 47 | libsim = static_library('sim', verilator_src, dependencies: [verilator], 48 | cpp_args: verilator_defines + verilator_warnings + ['-faligned-new']) 49 | libsim_dep = declare_dependency( 50 | # TODO: is there a less hacky way to filter out the headerfiles? 51 | sources: [verilator_src[0], verilator_src[1]], 52 | link_with: libsim) 53 | 54 | 55 | # DUT adapter header file generator 56 | dut_gen_py = find_program('../verilator/dut_gen.py') 57 | dut_hpp = custom_target('dut_hpp', output : 'dut.hpp', input : toml, 58 | command : [dut_gen_py, '-o', '@OUTPUT@', '-i', '@INPUT@']) 59 | 60 | 61 | sources = ['end_to_end_top.cpp', dut_hpp] 62 | executable(exe, sources, 63 | cpp_args: verilator_defines + ['-faligned-new'], 64 | dependencies: [libsim_dep, verilator]) 65 | -------------------------------------------------------------------------------- /e2e/meson_options.txt: -------------------------------------------------------------------------------- 1 | option('trace', type: 'boolean', value: false) 2 | option('build_dir', type: 'string', value: '../build') 3 | option('dut', type: 'string', value: 'nan') 4 | -------------------------------------------------------------------------------- /fpga/.gitignore: -------------------------------------------------------------------------------- 1 | # vivado project directory 2 | ekiwi/ 3 | 4 | # bitstream 5 | *.bit 6 | 7 | # vivado 8 | *.jou 9 | *.log 10 | .Xil 11 | 12 | # verilog generation artifacts 13 | chisel/AxisQueue.anno 14 | chisel/AxisQueue.fir 15 | chisel/AxisQueue.v 16 | -------------------------------------------------------------------------------- /fpga/Makefile: -------------------------------------------------------------------------------- 1 | all: system.bit 2 | 3 | system.bit: system.tcl 4 | vivado -mode batch -source make_bitstream.tcl 5 | clean: 6 | rm -rf ekiwi 7 | rm -rf vivado* 8 | rm -f system.bit 9 | 10 | deploy: system.bit system.tcl 11 | scp system.bit system.tcl pynq:~ 12 | -------------------------------------------------------------------------------- /fpga/Readme.md: -------------------------------------------------------------------------------- 1 | # FPGA Test Harness 2 | 3 | Tested on a PYNQ board using the standard SD-Card image v2 4 | on `2017-11-06` @ `189864f9febf8a05e44f9c486ac1863c2676fdd9`. 5 | 6 | On the host computer: 7 | 8 | ``` 9 | > make 10 | > scp scp system.bit system.tcl pynq:~ 11 | ``` 12 | 13 | On the PYNQ target via `ssh`: 14 | 15 | ``` 16 | > sudo ipython3 17 | In [1]: import numpy as n 18 | In [2]: from pynq import Xlnk, Overlay 19 | In [3]: xlnk = Xlnk() 20 | In [4]: ov = Overlay('/home/xilinx/system.bit') 21 | In [5]: def send(vals): 22 | ...: in_buffer = xlnk.cma_array(shape=(len(vals),), dtype=np.uint64) 23 | ...: for vv,ii in zip(vals,range(len(vals))): in_buffer[ii] = vv 24 | ...: dma = ov.axi_dma_0 25 | ...: dma.sendchannel.transfer(in_buffer) 26 | ...: dma.sendchannel.wait() 27 | In [6]: def recv(count): 28 | ...: out_buffer = xlnk.cma_array(shape=(count,), dtype=np.uint64) 29 | ...: dma = ov.axi_dma_0 30 | ...: dma.recvchannel.transfer(out_buffer) 31 | ...: dma.recvchannel.wait() 32 | ...: return out_buffer 33 | In [7]: d0 = (400 << 32) | 100 34 | In [8]: d1 = 1 << 63 | 1 << 62 35 | In [9]: payload = [0x19931993 << 32 | 1 << 16 | 3, 0x12345678, d0, d1, d0, d1, d0, d1] 36 | In [10]: send(payload) 37 | In [13]: recv(3) 38 | Out[13]: ContiguousArray([ 305419896, 216176080698999555, 3298534883328], dtype=uint64) 39 | In [14]: "{:x}".format(305419896) 40 | Out[14]: '12345678' 41 | In [15]: "{:x}".format(216176080698999555) 42 | Out[15]: '300030003000303' 43 | In [16]: "{:x}".format(3298534883328) 44 | Out[16]: '30000000000' 45 | ``` 46 | 47 | This matches the expected values tested in our unittest! 48 | -------------------------------------------------------------------------------- /fpga/make_bitstream.tcl: -------------------------------------------------------------------------------- 1 | source system.tcl 2 | 3 | # call implement 4 | launch_runs impl_1 -to_step write_bitstream -jobs 8 5 | wait_on_run impl_1 6 | 7 | # move and rename bitstream to final location 8 | file copy -force ./ekiwi/ekiwi.runs/impl_1/system_wrapper.bit system.bit 9 | -------------------------------------------------------------------------------- /fuzzer/.cargo/config: -------------------------------------------------------------------------------- 1 | [target.armv7-unknown-linux-gnueabihf] 2 | linker = "arm-linux-gnueabihf-gcc" 3 | [target.armv7-unknown-linux-musleabihf] 4 | linker = "arm-linux-gnueabihf-gcc" 5 | -------------------------------------------------------------------------------- /fuzzer/.gitignore: -------------------------------------------------------------------------------- 1 | /target/ 2 | **/*.rs.bk 3 | 4 | # ProgramUnderTest 5 | put/ 6 | 7 | # for now ignore Cargo.lock 8 | Cargo.lock 9 | 10 | # runtime files 11 | cur_input 12 | *out/ 13 | 14 | # top level logs 15 | /*.log 16 | -------------------------------------------------------------------------------- /fuzzer/Cargo.toml: -------------------------------------------------------------------------------- 1 | [package] 2 | name = "kfuzz" 3 | version = "0.1.0" 4 | authors = ["Kevin Laeufer "] 5 | 6 | [features] 7 | default = ["shmem"] 8 | shmem = [] 9 | dma = [] 10 | 11 | [dependencies] 12 | libc = "0.2.21" 13 | time = "0.1" 14 | twox-hash = "1.1.0" 15 | toml = "0.4" 16 | serde = "1.0" 17 | serde_derive = "1.0" 18 | serde_json = "1.0" 19 | colored = "1.6" 20 | prettytable-rs = "^0.6" 21 | rand = "0.4" 22 | ctrlc = "3.0" 23 | clap = "2.30.0" 24 | -------------------------------------------------------------------------------- /fuzzer/Readme.md: -------------------------------------------------------------------------------- 1 | # kfuzz 2 | 3 | Kevin's own fuzzer. 4 | Right now mostly a reimplementation of afl in Rust for learning purposes. 5 | Will be extended and modified to suit my purposes later. 6 | -------------------------------------------------------------------------------- /fuzzer/logs/2018-02-13_ICache_with_havoc_15_cycle_input_assertion_violation.log: -------------------------------------------------------------------------------- 1 | # running havoc with an input size of 15 on the ICache 2 | 3 | This seems to leads to an assertion failure which crashes verilator 4 | and thus our fuzzer. Therefore we do not get the actual bug causing input. 5 | 6 | Since the fuzzer is playing the role of all external components, it might 7 | just be misbehaving and that is caught by the assertion. Thus this might 8 | not be a bug in the actual ICache implementation. 9 | 10 | Running with longer inputs like 100 cycles also leads to an input that 11 | violates the same assertion. 12 | 13 | ## kfuzz output 14 | 15 | ``` 16 | Fuzzing ICache 17 | Instrumented on: 2018-02-01T18:30:00-08:00 18 | Coverage Signals: 21 19 | Input Fields: 28 20 | Total Input Width: 313 21 | Allocated Bytes per Input: 40 22 | Allocated Bytes for Coverage: 8 23 | Test Buffer: 64 KiB 24 | Coverage Buffer: 64 KiB 25 | Max Inputs: 1365 26 | New branch covered! 27 | fuzzing a maximum of 1000 queue entries 28 | 0. Queue Entry 29 | New branch covered! 30 | New branch covered! 31 | New branch covered! 32 | New branch covered! 33 | New branch covered! 34 | New branch covered! 35 | New branch covered! 36 | 1. Queue Entry 37 | Generated from 0. Entry 38 | In stage 1 of mutation algorithm "afl havoc". 39 | 2. Queue Entry 40 | Generated from 0. Entry 41 | In stage 7 of mutation algorithm "afl havoc". 42 | 3. Queue Entry 43 | Generated from 0. Entry 44 | In stage 16 of mutation algorithm "afl havoc". 45 | thread 'main' panicked at 'assertion failed: `(left == right)` 46 | left: `0`, 47 | right: `8`: tx pipe was closed unexpectedly!', src/run/shmem.rs:206:3 48 | note: Run with `RUST_BACKTRACE=1` for a backtrace. 49 | 50 | ``` 51 | 52 | ## verilator output 53 | 54 | 55 | ``` 56 | 57 | Assertion failed 58 | at ICache.scala:222 assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1) 59 | [10298767] %Error: ICache.v:1364: Assertion failed in TOP.VerilatorHarness.dut.bb 60 | %Error: ../../ICache.v:1364: Verilog $stop 61 | Aborting... 62 | [1] 11538 abort (core dumped) ./decoder 63 | 64 | ``` 65 | -------------------------------------------------------------------------------- /fuzzer/src/mutation/mod.rs: -------------------------------------------------------------------------------- 1 | mod format; 2 | mod mutators; 3 | 4 | use std::collections::{ HashMap, HashSet }; 5 | use rand; 6 | use rand::Rng; 7 | use self::format::InputFormat; 8 | use run::TestSize; 9 | 10 | /// saved with each entry in the queue 11 | /// this is used so that we don't repeat history 12 | /// (and thus not waste any cycles) 13 | #[derive(Default,Debug,Clone,Serialize,Deserialize)] 14 | pub struct MutationHistory { 15 | finished: HashSet 16 | } 17 | 18 | pub struct MutationScheduleConfig { 19 | pub skip_deterministic: bool, 20 | pub skip_non_deterministic: bool, 21 | pub independent_random: bool, 22 | } 23 | 24 | /// contains a list of possible mutations 25 | pub struct MutationSchedule { 26 | config: MutationScheduleConfig, 27 | format: InputFormat, 28 | /// length of input in bytes including padding 29 | input_size: usize, 30 | /// 31 | mutators: Vec, 32 | mutator_id_to_name: HashMap 33 | } 34 | 35 | impl MutationSchedule { 36 | pub fn initialize(config: MutationScheduleConfig, test_size: TestSize, input: Vec<(String,u32)>) -> Self { 37 | let input_size = test_size.input; 38 | let format = InputFormat::new(input, input_size); 39 | let mutators = mutators::get_list(); 40 | let mut mutator_id_to_name = HashMap::with_capacity(mutators.len()); 41 | for mutator in &mutators { 42 | mutator_id_to_name.insert(mutator.id, mutator.name.clone()); 43 | } 44 | // TODO: fix horrible hack!!! 45 | mutator_id_to_name.insert(mutators::RANDOM_BITFLIP_MUTATOR_ID, "random biflips".to_string()); 46 | mutator_id_to_name.insert(mutators::AFL_HAVOC_MUTATOR_ID, "afl havoc".to_string()); 47 | mutator_id_to_name.insert(mutators::RANDOM_GENERATOR_MUTATOR_ID, "random".to_string()); 48 | MutationSchedule { config, format, input_size, mutators, mutator_id_to_name } 49 | } 50 | 51 | pub fn get_mutator(&self, history: &mut MutationHistory, inputs: &[u8]) -> Option> { 52 | if self.config.independent_random { 53 | let mut rng = rand::thread_rng(); 54 | let seed : Seed = [rng.next_u32(), rng.next_u32(), rng.next_u32(), rng.next_u32()]; 55 | let mutator = Box::new(mutators::RandomGenerator::create(inputs.len(), seed)); 56 | Some(mutator) 57 | } else { 58 | if !self.config.skip_deterministic { 59 | for mutator in &self.mutators { 60 | assert!(mutator.deterministic, "non-deterministic mutators not suported at the moment!"); 61 | // TODO: for non-deterministic mutators, the single hash set is not really going to work.... 62 | if !history.finished.contains(&mutator.id) { 63 | history.finished.insert(mutator.id); 64 | return Some((mutator.create)(&self.format, inputs)); 65 | } 66 | } 67 | } 68 | // hacky non-deterministic stage 69 | if !self.config.skip_non_deterministic { 70 | let mut rng = rand::thread_rng(); 71 | let seed : Seed = [rng.next_u32(), rng.next_u32(), rng.next_u32(), rng.next_u32()]; 72 | //let mutator = Box::new(mutators::RandomBitflipMutator::create(&self.format, inputs, seed)); 73 | let mutator = Box::new(mutators::AflHavocMutator::create(&self.format, inputs, seed)); 74 | return Some(mutator); 75 | } 76 | None 77 | } 78 | } 79 | 80 | pub fn get_name(&self, id: MutatorId) -> &str { 81 | &self.mutator_id_to_name[&id.id] 82 | } 83 | 84 | pub fn get_names(&self) -> Vec<(String, u64)> { 85 | self.mutator_id_to_name.iter().map(|(id, name)| (name.clone(), *id)).collect() 86 | } 87 | } 88 | 89 | pub fn identity(seed: &[u8]) -> Box { 90 | Box::new(mutators::IdentityMutator::create(seed)) 91 | } 92 | 93 | pub(crate) struct MutatorEntry { 94 | id: u64, 95 | name: String, 96 | version: u32, 97 | deterministic: bool, 98 | create: Box Box>, 99 | } 100 | 101 | pub trait Mutator { 102 | /// unique id + Option 103 | fn id(&self) -> MutatorId; 104 | /// number of different mutations that can be performed for this instance 105 | fn max(&self) -> u32; 106 | /// the number of bytes that *all* mutation results have, None if the output size is variable 107 | fn output_size(&self) -> Option; 108 | /// apply mutation `ii` on input (`ii` in [0, max]) and write it to output 109 | fn apply(&mut self, ii: u32, output: &mut [u8]) -> usize; 110 | } 111 | 112 | pub(crate) type Seed = [u32; 4]; 113 | 114 | #[derive(Hash,Copy,Clone,Debug,PartialEq,Eq,PartialOrd,Serialize,Deserialize)] 115 | pub struct MutatorId { 116 | pub id: u64, 117 | seed: Option, 118 | } 119 | 120 | #[derive(Copy,Clone,Debug,PartialEq,PartialOrd,Serialize,Deserialize)] 121 | pub struct MutationInfo { 122 | pub mutator: MutatorId, 123 | pub ii: u32, 124 | } 125 | -------------------------------------------------------------------------------- /fuzzer/src/run/mod.rs: -------------------------------------------------------------------------------- 1 | pub mod buffered; 2 | mod history; 3 | mod rwint; 4 | #[cfg(feature = "shmem")] 5 | mod shmem; 6 | #[cfg(feature = "dma")] 7 | mod pynq; 8 | #[cfg(feature = "dma")] 9 | mod pynqchannel; 10 | 11 | use super::mutation::{MutationInfo, Mutator}; 12 | 13 | #[derive(Copy,Clone,Debug,PartialEq,PartialOrd,Default)] 14 | pub struct TestId(u64); 15 | impl TestId { 16 | fn next(&self) -> TestId { TestId(self.0 + 1) } 17 | } 18 | 19 | #[derive(Copy, Clone)] 20 | pub struct TestSize { 21 | pub coverage: usize, 22 | pub input: usize, 23 | } 24 | 25 | // TODO: return reference to coverage instead of copy 26 | pub struct BasicFeedback { pub id: TestId, pub cycles: u16, pub data: Vec } 27 | 28 | pub enum Run { Done(u32, u32), Yield(u32) } 29 | 30 | pub trait FuzzServer { 31 | /// shedule test input for execution 32 | fn run(&mut self, mutator: &mut Box, start: u32) -> Run; 33 | /// get a copy of the coverage information from a test 34 | /// the TestId can be used to retrieve further info if needed 35 | fn pop_coverage(&mut self) -> Option; 36 | /// must be called directly after `pop_coverage` 37 | fn get_info(&mut self, test: TestId) -> (MutationInfo, &[u8]); 38 | /// send all waiting tests to the fuzz server and wait 39 | /// until the fuzz server returns all coverage 40 | fn sync(&mut self); 41 | } 42 | -------------------------------------------------------------------------------- /fuzzer/src/run/pynqchannel.rs: -------------------------------------------------------------------------------- 1 | use super::buffered::CommunicationChannel; 2 | use super::pynq; 3 | 4 | pub struct DmaChannel { 5 | dma: pynq::Dma, 6 | busy: bool 7 | } 8 | 9 | #[derive(Clone, Copy, PartialEq, Debug)] 10 | pub struct DmaChannelToken { tx: pynq::DmaBufferId, rx: pynq::DmaBufferId } 11 | 12 | impl CommunicationChannel for DmaChannel { 13 | type BufferT = pynq::DmaBuffer; 14 | type TokenT = DmaChannelToken; 15 | fn get_token(tx: &Self::BufferT, rx: &Self::BufferT) -> Self::TokenT { 16 | DmaChannelToken { tx: tx.id(), rx: rx.id() } 17 | } 18 | fn alloc(&mut self, size: usize) -> Self::BufferT { 19 | let buf = pynq::DmaBuffer::allocate(size); 20 | //println!("DMA: new buf: {:?}", buf.id()); 21 | buf 22 | } 23 | fn try_send(&mut self, token: Self::TokenT, tx_bytes: usize, rx_bytes: usize) -> Result<(), ()> { 24 | if self.is_busy() { Err(()) } else { 25 | self.send(token, tx_bytes, rx_bytes); 26 | Ok(()) 27 | } 28 | } 29 | fn try_receive(&mut self) -> Option { 30 | if self.is_busy() && self.is_dma_done() { 31 | let tx = self.dma.finish_send(); 32 | let rx = self.dma.finish_receive(); 33 | let token = DmaChannelToken { tx, rx }; 34 | self.busy = false; 35 | //println!("DMA Channel: received back buffers: {:?}", token); 36 | Some(token) 37 | } else { None } 38 | } 39 | /// blocking receive, will panic if nothing was sent 40 | fn receive(&mut self) -> Self::TokenT { 41 | assert!(self.is_busy(), "empty channel!"); 42 | //println!("DMA Channel: going to wait for DMA to finish."); 43 | while !self.is_dma_done() {} 44 | self.try_receive().unwrap() 45 | } 46 | } 47 | 48 | impl DmaChannel { 49 | pub fn connect() -> Self { 50 | let dma = pynq::Dma::get(); 51 | let busy = false; 52 | //println!("DMA Channel connected!"); 53 | DmaChannel { dma, busy } 54 | } 55 | fn is_busy(&self) -> bool { self.busy } 56 | fn is_dma_done(&mut self) -> bool { 57 | self.dma.is_send_done() && self.dma.is_receive_done() 58 | } 59 | /// blocking send 60 | fn send(&mut self, token: DmaChannelToken, tx_bytes: usize, rx_bytes: usize) { 61 | assert!(!self.is_busy(), "Dma is busy!"); 62 | self.dma.start_send(token.tx, tx_bytes as u32); 63 | self.dma.start_receive(token.rx, rx_bytes as u32); 64 | self.busy = true; 65 | //println!("DMA Channel: start send of {:?}", token); 66 | //println!("DMA Channel: tx bytes: {}", tx_bytes); 67 | //println!("DMA Channel: rx bytes: {}", rx_bytes); 68 | } 69 | } 70 | -------------------------------------------------------------------------------- /fuzzer/src/run/rwint.rs: -------------------------------------------------------------------------------- 1 | use std; 2 | 3 | pub trait ReadIntsBigEndian : std::io::Read { 4 | fn read_u16(&mut self) -> std::io::Result { 5 | let mut data: [u8; 2] = [0; 2]; 6 | self.read_exact(&mut data)?; 7 | let val = (data[0] as u16) << 8 | (data[1] as u16) << 0; 8 | Ok(val) 9 | } 10 | 11 | fn read_u32(&mut self) -> std::io::Result { 12 | let mut data: [u8; 4] = [0; 4]; 13 | self.read_exact(&mut data)?; 14 | let val = (data[0] as u32) << 24 | (data[1] as u32) << 16 | 15 | (data[2] as u32) << 8 | (data[3] as u32) << 0; 16 | Ok(val) 17 | } 18 | 19 | fn read_u64(&mut self) -> std::io::Result { 20 | let mut data: [u8; 8] = [0; 8]; 21 | self.read_exact(&mut data)?; 22 | let val = (data[0] as u64) << 56 | (data[1] as u64) << 48 | 23 | (data[2] as u64) << 40 | (data[3] as u64) << 32 | 24 | (data[4] as u64) << 24 | (data[5] as u64) << 16 | 25 | (data[6] as u64) << 8 | (data[7] as u64) << 0; 26 | Ok(val) 27 | } 28 | } 29 | 30 | pub trait WriteIntsBigEndian : std::io::Write { 31 | fn write_u16(&mut self, val: u16) -> std::io::Result<()> { 32 | let data = [(val >> 8) as u8, (val >> 0) as u8]; 33 | self.write_all(&data) 34 | } 35 | 36 | fn write_u32(&mut self, val: u32) -> std::io::Result<()> { 37 | let data = [(val >> 24) as u8, (val >> 16) as u8, 38 | (val >> 8) as u8, (val >> 0) as u8]; 39 | self.write_all(&data) 40 | } 41 | 42 | fn write_u64(&mut self, val: u64) -> std::io::Result<()> { 43 | let data = [(val >> 56) as u8, (val >> 48) as u8, 44 | (val >> 40) as u8, (val >> 32) as u8, 45 | (val >> 24) as u8, (val >> 16) as u8, 46 | (val >> 8) as u8, (val >> 0) as u8]; 47 | self.write_all(&data) 48 | } 49 | } 50 | 51 | pub trait ReadIntsLittleEndian : std::io::Read { 52 | fn read_u16(&mut self) -> std::io::Result { 53 | let mut data: [u8; 2] = [0; 2]; 54 | self.read_exact(&mut data)?; 55 | let val = (data[1] as u16) << 8 | (data[0] as u16) << 0; 56 | Ok(val) 57 | } 58 | 59 | fn read_u32(&mut self) -> std::io::Result { 60 | let mut data: [u8; 4] = [0; 4]; 61 | self.read_exact(&mut data)?; 62 | let val = (data[3] as u32) << 24 | (data[2] as u32) << 16 | 63 | (data[1] as u32) << 8 | (data[0] as u32) << 0; 64 | Ok(val) 65 | } 66 | 67 | fn read_u64(&mut self) -> std::io::Result { 68 | let mut data: [u8; 8] = [0; 8]; 69 | self.read_exact(&mut data)?; 70 | let val = (data[7] as u64) << 56 | (data[6] as u64) << 48 | 71 | (data[5] as u64) << 40 | (data[4] as u64) << 32 | 72 | (data[3] as u64) << 24 | (data[2] as u64) << 16 | 73 | (data[1] as u64) << 8 | (data[0] as u64) << 0; 74 | Ok(val) 75 | } 76 | } 77 | 78 | pub trait WriteIntsLittleEndian : std::io::Write { 79 | fn write_u16(&mut self, val: u16) -> std::io::Result<()> { 80 | let data = [(val >> 0) as u8, (val >> 8) as u8]; 81 | self.write_all(&data) 82 | } 83 | 84 | fn write_u32(&mut self, val: u32) -> std::io::Result<()> { 85 | let data = [(val >> 0) as u8, (val >> 8) as u8, 86 | (val >> 16) as u8, (val >> 24) as u8]; 87 | self.write_all(&data) 88 | } 89 | 90 | fn write_u64(&mut self, val: u64) -> std::io::Result<()> { 91 | let data = [(val >> 0) as u8, (val >> 8) as u8, 92 | (val >> 16) as u8, (val >> 24) as u8, 93 | (val >> 32) as u8, (val >> 40) as u8, 94 | (val >> 48) as u8, (val >> 56) as u8]; 95 | self.write_all(&data) 96 | } 97 | } 98 | -------------------------------------------------------------------------------- /harness/.gitignore: -------------------------------------------------------------------------------- 1 | # build artifacts 2 | project/ 3 | target/ 4 | test_run_dir/ 5 | 6 | *.v 7 | *.fir 8 | *.anno 9 | *.f 10 | -------------------------------------------------------------------------------- /harness/build.sbt: -------------------------------------------------------------------------------- 1 | name := "rfuzz-harness" 2 | version := "0.1" 3 | organization := "edu.berkeley.cs" 4 | scalaVersion := "2.12.10" 5 | 6 | scalacOptions := Seq("-deprecation", "-unchecked", "-Xsource:2.11") 7 | libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.3.2" 8 | // toml-scala: https://github.com/sparsetech/toml-scala 9 | // (stoml does not support dates) 10 | libraryDependencies += "tech.sparse" %% "toml-scala" % "0.1.0" 11 | 12 | scalaSource in Compile := baseDirectory.value / "src" 13 | scalaSource in Test := baseDirectory.value / "test" 14 | -------------------------------------------------------------------------------- /harness/src/freechips/rocketchip/util/RecordMap.scala: -------------------------------------------------------------------------------- 1 | // Apache License 2.0 2 | 3 | // src: https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/RecordMap.scala 4 | 5 | package freechips.rocketchip.util 6 | 7 | import chisel3._ 8 | import scala.collection.immutable.ListMap 9 | import chisel3.internal.requireIsChiselType 10 | import chisel3.experimental.DataMirror.internal.chiselTypeClone 11 | 12 | final class RecordMap[T <: Data] private (eltMap: ListMap[String, T]) 13 | extends Record { 14 | 15 | eltMap.foreach { case (name, elt) => requireIsChiselType(elt, name) } 16 | 17 | // This is needed for Record 18 | val elements = ListMap[String, T]() ++ eltMap.mapValues(chiselTypeClone(_).asInstanceOf[T]) // mapValues return value is lazy 19 | 20 | def apply(x: Int) = elements.values.toSeq(x) 21 | def apply(x: String) = elements.get(x) 22 | def size = elements.size 23 | def data = elements.values 24 | 25 | override def cloneType: this.type = (new RecordMap(eltMap)).asInstanceOf[this.type] 26 | 27 | } 28 | 29 | object RecordMap { 30 | 31 | def apply[T <: Data](eltMap: ListMap[String, T]) = new RecordMap(eltMap) 32 | 33 | def apply[T <: Data](elements: (String, T)*): RecordMap[T] = { 34 | new RecordMap[T](ListMap[String, T](elements:_*)) 35 | } 36 | } -------------------------------------------------------------------------------- /harness/src/rfuzz/Config.scala: -------------------------------------------------------------------------------- 1 | // Copyright 2017 Kevin Laeufer 2 | package rfuzz 3 | // this file contains code to load our TOML config files and 4 | // extract the information needed to generate the harness 5 | 6 | case class DUTConfig(src: String, name: String, 7 | input: Seq[Config.Input], inputBits: Int, 8 | coveragePorts: Seq[Config.Port], 9 | coverageSignals: Seq[Config.Coverage], coverageBits: Int) 10 | 11 | 12 | 13 | object Config { 14 | import java.nio.charset.StandardCharsets 15 | import java.nio.file.{Files, Paths} 16 | import java.time.OffsetDateTime 17 | 18 | import toml.Codecs._ 19 | import toml._ 20 | 21 | case class General(filename: String, instrumented: String, top: String, timestamp: OffsetDateTime) 22 | case class Coverage(port: String, name: String, index: Int, filename: String, line: Int, column: Int, human: String) 23 | case class Input(name: String, width: Int) 24 | case class Port(name: String, width: Int) 25 | case class Counter(name: String, width: Int, max: Int, scale: Boolean, index: Int, signal: Int, fail: Boolean = false) 26 | case class Test(general: General, coverage: List[Coverage], input: List[Input], port: List[Port]) 27 | 28 | implicit val booleanCodec: toml.Codec[Boolean] = toml.Codec[Boolean]( { 29 | case toml.Value.Bool(value) => Right(value) 30 | case value => 31 | Left((List.empty, s"Boolean expected, $value provided")) 32 | }) 33 | // TODO: why does this not work out of the box? why do we need to reimplement this here? 34 | implicit val offsetDateTimeCodec: toml.Codec[OffsetDateTime] = toml.Codec[OffsetDateTime]( { 35 | case toml.Value.OffsetDateTime(value) => Right(value) 36 | case value => 37 | Left((List.empty, s"OffsetDateTime expected, $value provided")) 38 | }) 39 | // TODO: this seems like quite a hack .... why does the `tableCodec` from the lib not work? 40 | implicit val intTableCodec: toml.Codec[Seq[(String,Int)]] = toml.Codec[Seq[(String,Int)]]( { 41 | case toml.Value.Tbl(values) => { 42 | Right(values.map{ 43 | case (key: String, num: toml.Value.Num) => (key, num.value.toInt) 44 | case (k, v) => throw new Exception(s"Unexpected ${k} -> ${v}, expected String -> Int") 45 | }.toSeq) 46 | } 47 | case value => 48 | Left((List.empty, s"Table expected, $value provided")) 49 | }) 50 | 51 | def loadFileContent(filename: String) : String = { 52 | new String(Files.readAllBytes(Paths.get(filename)), StandardCharsets.UTF_8) 53 | } 54 | def loadToml(filename: String) : DUTConfig = { 55 | val Right(toml) = Toml.parseAs[Test](loadFileContent(filename)) 56 | // DEBUG print 57 | // println(s"Module: ${toml.general.module}") 58 | // println(s"Created on: ${toml.general.timestamp}") 59 | // println(s"Inputs:") 60 | // for((name, width) <- toml.input) { 61 | // println(s"${name}: ${width}") 62 | // } 63 | // extract relevant values 64 | val src = toml.general.instrumented 65 | val name = toml.general.top 66 | val input = toml.input 67 | val inputBits = input.map{ case input: Input => input.width }.reduce(_+_) 68 | val coveragePorts = toml.port 69 | val coverageSignals = toml.coverage 70 | val coverageBits = coverageSignals.size 71 | new DUTConfig(src, name, input, inputBits, coveragePorts, coverageSignals, coverageBits) 72 | } 73 | def dumpCounters(out: java.io.PrintWriter, counters: Seq[Counter]) = { 74 | val q = "\"" // Workaround for Vim Scala syntax highlighting 75 | for(count <- counters) { 76 | out.println(s"""[[counter]]""") 77 | out.println(s"""name = "${count.name}$q""") 78 | out.println(s"""width = ${count.width}""") 79 | out.println(s"""max = ${count.max}""") 80 | out.println(s"""scale = ${count.scale}""") 81 | out.println(s"""index = ${count.index}""") 82 | out.println(s"""signal = ${count.signal}""") 83 | out.println(s"""fail = ${count.fail}""") 84 | out.println() 85 | } 86 | } 87 | def writeAugmentedToml(inFile: String, outFile: String, counters: Seq[Counter]) = { 88 | val out = new java.io.PrintWriter(outFile) 89 | out.print(loadFileContent(inFile)) 90 | out.println("# Counter info generated by the Harness Generator:") 91 | dumpCounters(out, counters) 92 | out.close 93 | } 94 | } 95 | -------------------------------------------------------------------------------- /harness/src/rfuzz/DUT.scala: -------------------------------------------------------------------------------- 1 | package rfuzz 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | import freechips.rocketchip.util.RecordMap 6 | 7 | import scala.collection.immutable.ListMap 8 | 9 | 10 | class DUTBlackBox(conf: DUTConfig) extends HasBlackBoxInline { 11 | override def desiredName = conf.name 12 | val io = this.IO(RecordMap( { 13 | ListMap("clock" -> Input(Clock()), "reset" -> Input(Bool()), 14 | "metaReset" -> Input(Bool())) ++ 15 | conf.input.map{ case inp => inp.name -> Input(UInt(inp.width.W)) } ++ 16 | conf.coveragePorts.map{ case port => port.name -> Output(UInt(port.width.W)) } 17 | // TODO: is it ok to just ignore the output? 18 | })) 19 | setInline(conf.src, 20 | scala.io.Source.fromFile("../build/" + conf.src).mkString) 21 | } 22 | 23 | class DUT(conf: DUTConfig) extends Module { 24 | val io = this.IO(new Bundle { 25 | val meta_reset = Input(Bool()) 26 | val inputs = Input(UInt(conf.inputBits.W)) 27 | val coverage = Output(Vec(conf.coverageBits, Bool())) 28 | }) 29 | val bb = Module(new DUTBlackBox(conf)) 30 | val pins = bb.io.elements 31 | 32 | // connect clock and reset 33 | pins("clock") := this.clock 34 | pins("reset") := this.reset.toBool 35 | pins("metaReset") := this.io.meta_reset 36 | 37 | // extract inputs 38 | var left = conf.inputBits - 1 39 | conf.input.map{ case Config.Input(n,w) => 40 | pins(n) := io.inputs(left, left - w + 1) 41 | left = left - w 42 | } 43 | 44 | // connect coverage 45 | val coverage = for(sig <- conf.coverageSignals) yield { 46 | val port = pins(sig.port) 47 | val bit = port.getWidth - 1 - sig.index 48 | port.asInstanceOf[UInt](bit) 49 | } 50 | for((cov, ii) <- coverage.zipWithIndex) { 51 | io.coverage(ii) := cov 52 | } 53 | } 54 | -------------------------------------------------------------------------------- /harness/src/rfuzz/HarnessGenerator.scala: -------------------------------------------------------------------------------- 1 | package rfuzz 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | // WARN: all circuts designed with 64bit AXIS interface in mind 7 | 8 | object div2Ceil { 9 | def apply(dividend: Int, divisor: Int): Int = (dividend + divisor - 1) / divisor 10 | } 11 | 12 | class WrappingCounter(width : Int) extends Module { 13 | val io = this.IO(new Bundle { 14 | val enable = Input(Bool()) 15 | val max = Input(UInt(width.W)) 16 | val value = Output(UInt(width.W)) 17 | val last = Output(Bool()) 18 | }) 19 | val count = RegInit(0.U(width.W)) 20 | io.value := count 21 | io.last := count === io.max 22 | count := Mux(!io.enable, count, Mux(io.last, 0.U, count + 1.U)) 23 | } 24 | 25 | class TestExecControl extends Bundle { 26 | val run_cycles = Input(UInt(16.W)) 27 | val test_count = Input(UInt(16.W)) 28 | } 29 | 30 | class DUTDriverInterface(input_width: Int) extends Bundle { 31 | // TODO: why does this fail when wrapped in Input(...)? 32 | val data = DeqIO(UInt(input_width.W)) 33 | val start_next = Input(Bool()) 34 | val ready_next = Output(Bool()) 35 | override def cloneType: this.type = new DUTDriverInterface(input_width).asInstanceOf[this.type] 36 | } 37 | 38 | object Convert64BitEndianess { 39 | def apply(in : UInt) : UInt = { 40 | require(in.widthKnown) 41 | // TODO: how do we get the width? 42 | val width = 64 43 | // bytes from right to left 44 | val bytes = for(ii <- 0 until (width/8)) yield in(((ii+1) * 8) - 1, ii * 8) 45 | // concat bytes from left to right 46 | Cat(bytes) 47 | } 48 | } 49 | 50 | object HarnessGenerator extends App { 51 | require(args.length > 2, "Please provide the toml form the instrumentation pass as well as the 2 output toml as arguments!") 52 | val inToml = args(0) 53 | val outToml = args(1) 54 | val outE2EToml = args(2) 55 | val conf = Config.loadToml(inToml) 56 | println(s"Conf: ${conf}") 57 | // super hacky "out parameter" to get list of counters from Harness design 58 | val counters = collection.mutable.ArrayBuffer[Config.Counter]() 59 | chisel3.Driver.execute(args, () => new VerilatorHarness(conf, counters)) 60 | Config.writeAugmentedToml(inToml, outToml, counters.toSeq) 61 | // end-to-end coverage 62 | val e2e_counters = collection.mutable.ArrayBuffer[Config.Counter]() 63 | chisel3.Driver.execute(args, () => new E2ECoverageHarness(conf, e2e_counters)) 64 | Config.writeAugmentedToml(inToml, outE2EToml, e2e_counters.toSeq) 65 | } 66 | 67 | -------------------------------------------------------------------------------- /instrumentation/.gitignore: -------------------------------------------------------------------------------- 1 | *.class 2 | *.log 3 | 4 | # sbt specific 5 | .cache/ 6 | .history/ 7 | .lib/ 8 | dist/* 9 | target/ 10 | lib_managed/ 11 | src_managed/ 12 | project/boot/ 13 | project/plugins/project/ 14 | 15 | # sometimes we generate random toml files 16 | *.toml 17 | 18 | # tests 19 | test_run_dir/ 20 | -------------------------------------------------------------------------------- /instrumentation/build.sbt: -------------------------------------------------------------------------------- 1 | name := "rfuzz-instrumentation" 2 | organization := "edu.berkeley.cs" 3 | scalaVersion := "2.12.10" 4 | 5 | scalacOptions := Seq("-deprecation", "-unchecked", "-Xsource:2.11") 6 | libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.3.2" 7 | 8 | scalaSource in Compile := baseDirectory.value / "src" 9 | scalaSource in Test := baseDirectory.value / "test" 10 | -------------------------------------------------------------------------------- /instrumentation/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.3.10 2 | -------------------------------------------------------------------------------- /instrumentation/src/.editorconfig: -------------------------------------------------------------------------------- 1 | # EditorConfig is awesome: http://EditorConfig.org 2 | 3 | 4 | # Jack's Scala Style 5 | 6 | [*.scala] 7 | end_of_line = lf 8 | charset = utf-8 9 | indent_style = space 10 | indent_size = 2 11 | -------------------------------------------------------------------------------- /instrumentation/src/rfuzz/MetaReset.scala: -------------------------------------------------------------------------------- 1 | 2 | package rfuzz 3 | 4 | import firrtl.Mappers._ 5 | import firrtl.Utils.throwInternalError 6 | import firrtl._ 7 | import firrtl.analyses.InstanceGraph 8 | import firrtl.ir._ 9 | import firrtl.passes.RemoveValidIf 10 | 11 | // Add a meta-reset to all registers 12 | class AddMetaResetTransform extends Transform { 13 | def inputForm = LowForm 14 | def outputForm = LowForm 15 | 16 | val metaResetPort = Port(NoInfo, "metaReset", Input, Utils.BoolType) 17 | val metaResetInput = WRef(metaResetPort.name, metaResetPort.tpe, PortKind, SourceFlow) 18 | def metaResetInstPort(inst: WDefInstance) = { 19 | val instRef = WRef(inst.name, inst.tpe, InstanceKind, DuplexFlow) 20 | WSubField(instRef, metaResetPort.name, metaResetPort.tpe, SourceFlow) 21 | } 22 | val metaResetSinkRef = metaResetInput.copy(flow = SinkFlow) 23 | 24 | // Make a firrtl util 25 | private def getZero(tpe: Type): Literal = tpe match { 26 | case gtpe: GroundType => 27 | RemoveValidIf.getGroundZero(gtpe).map { w: Width => gtpe.width }.asInstanceOf[Literal] 28 | case other => throwInternalError(s"Unexpected non-GroundType $other") 29 | } 30 | 31 | private def onStmt(modType: Map[String, Type])(stmt: Statement): Statement = 32 | stmt.map(onStmt(modType)) match { 33 | case reg: DefRegister => 34 | if (reg.reset != Utils.zero) { 35 | throwInternalError(s"Resets must have been removed! Got ${reg.serialize}") 36 | } 37 | val zero = getZero(reg.tpe) 38 | reg.copy(reset = metaResetInput, tpe = zero.tpe, init = zero) 39 | case inst: WDefInstance if (modType.contains(inst.module)) => 40 | val instx = inst.copy(tpe = modType(inst.module)) 41 | val con = Connect(NoInfo, metaResetInstPort(instx), metaResetInput) 42 | Block(Seq(instx, con)) 43 | case other => other 44 | } 45 | private def onMod(modType: Map[String, Type])(m: Module): Module = { 46 | val portsx = metaResetPort +: m.ports 47 | val bodyx = onStmt(modType)(m.body) 48 | m.copy(ports = portsx, body = bodyx) 49 | } 50 | def cleanup: Seq[Transform] = Seq(firrtl.transforms.RemoveReset) 51 | 52 | def execute(state: CircuitState): CircuitState = { 53 | val modSet = state.circuit.modules.collect({ case m: Module => m }).toSet 54 | val modsLeafToRoot = (new InstanceGraph(state.circuit)).moduleOrder.reverse 55 | val (modsUpdate, _) = 56 | modsLeafToRoot.foldLeft((Map.empty[String, DefModule], Map.empty[String, Type])) { 57 | case ((acc, types), m) => m match { 58 | case mod: Module => 59 | val modx = onMod(types)(mod) 60 | (acc + (modx.name -> modx), types + (modx.name -> Utils.module_type(modx))) 61 | case ext: ExtModule => (acc, types) 62 | } 63 | } 64 | // Maintain order 65 | val modsx = state.circuit.modules.map(m => modsUpdate.getOrElse(m.name, m)) 66 | val res = state.copy(circuit = state.circuit.copy(modules = modsx)) 67 | cleanup.foldLeft(res) { case (in, xform) => xform.runTransform(in) } 68 | } 69 | } 70 | 71 | -------------------------------------------------------------------------------- /instrumentation/src/rfuzz/NoDedup.scala: -------------------------------------------------------------------------------- 1 | package rfuzz 2 | 3 | import firrtl.Mappers._ 4 | import firrtl._ 5 | import firrtl.annotations._ 6 | import firrtl.ir._ 7 | import firrtl.transforms.NoDedupAnnotation 8 | 9 | import scala.collection.mutable 10 | 11 | // Annotate every module with NoDedupAnnotation 12 | // Also check that there is only one instance of each module 13 | // We need this because the WiringTransform cannot handle deduplicated modules 14 | // Turning off dedup should be a feature of FIRRTL 15 | // Note that we can't use InstanceGraph because it only works on WIR (needs to be checked) 16 | class NoDedupTransform extends Transform { 17 | def inputForm = ChirrtlForm 18 | def outputForm = ChirrtlForm 19 | 20 | // Returns a *relative* count of modules, ie. how many times the DefInstance shows up in the 21 | // Module graph 22 | def countInsts(circuit: Circuit): Map[String, Int] = { 23 | val counts = mutable.HashMap.empty[String, Int] 24 | counts(circuit.main) = 1 25 | def onStmt(stmt: Statement): Statement = stmt.map(onStmt) match { 26 | case inst @ DefInstance(_,_, mname) => 27 | counts(mname) = counts.getOrElse(mname, 0) + 1 28 | inst 29 | case (_: WDefInstance | _: WDefInstanceConnector) => 30 | throw new FIRRTLException("Unexpected non-Chirrtl Instance!") 31 | case other => other 32 | } 33 | def onMod(mod: DefModule): DefModule = mod.map(onStmt) 34 | circuit.map(onMod) 35 | counts.toMap 36 | } 37 | 38 | // NoDedupAnnotation 39 | def execute(state: CircuitState): CircuitState = { 40 | val counts = countInsts(state.circuit) 41 | // Check counts 42 | require(counts.forall(_._2 == 1), s"There must be no deduplicated modules! " + 43 | counts.filter(_._2 > 1) 44 | ) 45 | // create annotations 46 | val circuitName = CircuitName(state.circuit.main) 47 | val modNames = state.circuit.modules.map(m => ModuleName(m.name, circuitName)) 48 | val annos = modNames.map(NoDedupAnnotation(_)) 49 | state.copy(annotations = state.annotations ++ annos) 50 | } 51 | } 52 | -------------------------------------------------------------------------------- /instrumentation/src/rfuzz/SparseMem.scala: -------------------------------------------------------------------------------- 1 | package rfuzz 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | object SparseMem { 7 | def getMaskWidth(data: Data): Int = data match { 8 | case agg: Aggregate => 9 | agg.getElements.map(getMaskWidth).sum 10 | case _: Element => 1 11 | } 12 | } 13 | 14 | class MemReaderIO[T <: Data](private val dataType: T, private val addrWidth: Int) extends Bundle { 15 | val addr = Input(UInt(addrWidth.W)) 16 | val en = Input(Bool()) 17 | val data = Output(dataType) 18 | def check(addr: UInt, expected: T): Unit = { 19 | en := true.B 20 | this.addr := addr 21 | assert(data.asUInt === expected.asUInt) 22 | } 23 | } 24 | class MemWriterIO[T <: Data](private val dataType: T, private val addrWidth: Int) extends Bundle { 25 | val addr = Input(UInt(addrWidth.W)) 26 | val en = Input(Bool()) 27 | // We have to emulate firrtl's memlib mask type with is Vector for aggregate or Bool for GroundType 28 | val mask: Data = dataType match { 29 | case _: Vec[_] => Input(Vec(SparseMem.getMaskWidth(dataType), Bool())) 30 | case _: Bits => Input(UInt(SparseMem.getMaskWidth(dataType).W)) 31 | } 32 | val data = Input(dataType) 33 | def write(addr: UInt, data: T): Unit = { 34 | en := true.B 35 | this.addr := addr 36 | this.data := data 37 | } 38 | } 39 | class SparseMem[T <: Data] 40 | (dataType: T, 41 | depth: Int, 42 | addrWidth: Int, 43 | nR: Int, 44 | nW: Int, 45 | syncRead: Boolean) 46 | (implicit maybe: MaybeVec[T]) extends Module with RequireSyncReset { 47 | val io = IO(new Bundle { 48 | val w = Vec(nW, new MemWriterIO(dataType, addrWidth)) 49 | val r = Vec(nR, new MemReaderIO(dataType, addrWidth)) 50 | }) 51 | 52 | val mem = Mem(depth, dataType) 53 | val addresses = RegInit(VecInit(Seq.fill(depth) { 54 | val w = Wire(Valid(UInt(addrWidth.W))) 55 | w.valid := false.B 56 | w.bits := DontCare 57 | w 58 | })) 59 | 60 | def addrMatch(addr: UInt): (Bool, UInt) = { 61 | val matches = VecInit(addresses.map(v => v.valid && v.bits === addr)).asUInt 62 | (matches =/= 0.U, OHToUInt(matches)) 63 | } 64 | def read(en: Bool, addr: UInt): Data = { 65 | val (valid, addrIdx) = addrMatch(addr) 66 | Mux(valid && en, mem(addrIdx), 0.U.asTypeOf(dataType)) 67 | } 68 | 69 | val readers = if (syncRead) RegNext(io.r) else io.r 70 | 71 | for (r <- io.r) { 72 | r.data := read(r.en, r.addr) 73 | } 74 | 75 | // Increase addr width by 1 so we can detect overflow 76 | val nextAddr = RegInit(0.U((log2Ceil(depth) + 1).W)) 77 | 78 | val nextAddrs = io.w.foldLeft(nextAddr) { 79 | case (na, w) => Mux(w.en, na +% 1.U, na) 80 | } 81 | 82 | val nextAddrUpdate = io.w.foldLeft(nextAddr) { case (naddr, w) => 83 | val (found, faddr) = addrMatch(w.addr) 84 | val allocate = w.en && !found 85 | when (w.en) { 86 | val addr = Mux(found, faddr, naddr) 87 | addresses(addr).valid := true.B 88 | addresses(addr).bits := w.addr 89 | maybe.evidence match { 90 | case Some(ev) => 91 | implicit val evidence = ev 92 | mem.write(addr, w.data, w.mask.asUInt.toBools) 93 | case None => 94 | mem.write(addr, w.data) 95 | } 96 | } 97 | Mux(allocate, naddr +% 1.U, naddr) 98 | } 99 | nextAddr := nextAddrUpdate 100 | 101 | // make sure that we never write beyond the allocated space 102 | assert(nextAddrUpdate <= depth.U, 103 | "SparseMem ran out of space with size %d, increase size in ReplaceMemsTransform!", depth.U) 104 | } 105 | 106 | -------------------------------------------------------------------------------- /instrumentation/src/rfuzz/SplitMuxConditions.scala: -------------------------------------------------------------------------------- 1 | package rfuzz 2 | 3 | import firrtl.Mappers._ 4 | import firrtl._ 5 | import firrtl.ir._ 6 | 7 | import scala.collection.mutable 8 | 9 | // Removes compound expressions from mux conditions 10 | // Ensures they are a reference 11 | // Borrows from Firrtl's SplitExpressions 12 | class SplitMuxConditions extends Transform { 13 | def inputForm = MidForm 14 | def outputForm = MidForm 15 | 16 | private def isRef(expr: Expression): Boolean = expr match { 17 | case ref @ (_: WRef | _: WSubField | _: WSubIndex) => true 18 | case _ => false 19 | } 20 | 21 | private def onModule(mod: Module): Module = { 22 | val namespace = Namespace(mod) 23 | def onStmt(s: Statement): Statement = { 24 | val stmts = mutable.ArrayBuffer.empty[Statement] 25 | def onExpr(e: Expression): Expression = e map onExpr match { 26 | case Mux(cond, tval, fval, mtpe) if !isRef(cond) => 27 | val n = DefNode(Utils.get_info(s), namespace.newTemp, cond) 28 | stmts.append(n) 29 | Mux(WRef(n.name, cond.tpe, NodeKind, SourceFlow), tval, fval, mtpe) 30 | case mux: Mux => 31 | mux 32 | case other => other 33 | } 34 | 35 | stmts += s.map(onExpr).map(onStmt) 36 | stmts.size match { 37 | case 1 => stmts.head 38 | case _ => Block(stmts) 39 | } 40 | } 41 | mod.copy(body = onStmt(mod.body)) 42 | } 43 | def execute(state: CircuitState): CircuitState = { 44 | state.copy(circuit = state.circuit.copy(modules = state.circuit.modules map { 45 | case mod: Module => onModule(mod) 46 | case ext: ExtModule => ext 47 | })) 48 | } 49 | } -------------------------------------------------------------------------------- /instrumentation/src/rfuzz/package.scala: -------------------------------------------------------------------------------- 1 | 2 | import chisel3._ 3 | 4 | package object rfuzz { 5 | // Some magic to help SparseMem generically handle Mems of type Vec and not (for use of mask) 6 | case class MaybeVec[-T](evidence: Option[T <:< Vec[_]]) 7 | implicit def isVec[T](implicit ev: T <:< Vec[_]): MaybeVec[T] = MaybeVec(Some(ev)) 8 | implicit val notVec: MaybeVec[Any] = MaybeVec(None) 9 | } 10 | -------------------------------------------------------------------------------- /instrumentation/test/rfuzz/SparseMemSpec.scala: -------------------------------------------------------------------------------- 1 | 2 | package rfuzz 3 | 4 | import chisel3._ 5 | import chisel3.util._ 6 | import chisel3.testers._ 7 | 8 | class SparseMemTester extends BasicTester { 9 | val mod = Module(new SparseMem(UInt(32.W), 4, 8, 1, 1, false)) 10 | // Defaults 11 | mod.io <> DontCare 12 | mod.io.w(0).en := false.B 13 | mod.io.r(0).en := false.B 14 | 15 | val (cycle, done) = Counter(true.B, 8) 16 | printf(p" ***** Cycle $cycle *****\n") 17 | printf(p"${mod.io}\n") 18 | when (cycle === 0.U) { 19 | mod.io.w(0).write(100.U, 123.U) 20 | mod.io.r(0).check(5.U, 0.U) 21 | } 22 | .elsewhen(cycle === 1.U) { 23 | mod.io.r(0).check(100.U, 123.U) 24 | } 25 | .elsewhen(cycle === 2.U) { 26 | mod.io.w(0).write(8.U, 456.U) 27 | mod.io.r(0).check(8.U, 0.U) 28 | } 29 | .elsewhen(cycle === 3.U) { 30 | mod.io.r(0).check(8.U, 456.U) 31 | } 32 | when (done) { 33 | stop() 34 | } 35 | } 36 | 37 | class SparseMemMaxWritesTester extends BasicTester { 38 | val depth = 2 39 | val addrWidth = 2 40 | val mod = Module(new SparseMem(UInt(32.W), depth, addrWidth, 1, 1, false)) 41 | // Defaults 42 | mod.io <> DontCare 43 | mod.io.w(0).en := false.B 44 | mod.io.r(0).en := false.B 45 | 46 | val (cycle, done) = Counter(true.B, 8) 47 | printf(p" ***** Cycle $cycle *****\n") 48 | printf(p"${mod.io}\n") 49 | when (cycle === 0.U) { 50 | mod.io.w(0).write(1.U, 123.U) 51 | } 52 | .elsewhen(cycle === 1.U) { 53 | // if we change this to write to address 2 or 3, this test should fail! 54 | mod.io.w(0).write(1.U, 123.U) 55 | } 56 | .elsewhen(cycle === 2.U) { 57 | // this should not lead to an assertion violation since the memory can hold 58 | // two entries! 59 | mod.io.w(0).write(0.U, 123.U) 60 | } 61 | when (done) { 62 | stop() 63 | } 64 | } 65 | 66 | object TestSparseMem extends App { 67 | assert(TesterDriver.execute(() => new SparseMemTester), "Test must work!") 68 | assert(TesterDriver.execute(() => new SparseMemMaxWritesTester), "No assertion should fire!") 69 | } 70 | -------------------------------------------------------------------------------- /midas/.gitignore: -------------------------------------------------------------------------------- 1 | target 2 | *.log 3 | *.vcd 4 | *.tmp 5 | -------------------------------------------------------------------------------- /midas/Makefile: -------------------------------------------------------------------------------- 1 | PLATFORM ?= zynq 2 | DUT ?= ICache 3 | 4 | base_dir = $(abspath ..) 5 | build_dir = $(base_dir)/build 6 | bmark_dir = $(base_dir)/benchmarks 7 | verilator_dir = $(base_dir)/verilator 8 | simif_dir = $(abspath midas/src/main/cc) 9 | driver_dir = $(abspath src/main/cc) 10 | fpga_dir = $(abspath platforms/$(PLATFORM)) 11 | 12 | firrtl = $(build_dir)/$(DUT).lo.fir 13 | in_toml = $(build_dir)/$(DUT)_InstrumentationInfo.toml 14 | out_toml = $(build_dir)/$(DUT).toml 15 | 16 | SBT ?= sbt 17 | SBT_FLAGS ?= -J-Xmx16G -J-Xss8M -J-XX:MaxMetaspaceSize=512M 18 | 19 | $(firrtl) $(in_toml): 20 | $(MAKE) -C $(base_dir) instrumentation 21 | 22 | verilog = $(build_dir)/FPGATop.v 23 | header = $(build_dir)/VerilatorHarness-const.h 24 | $(verilog) $(header): $(firrtl) $(in_toml) $(shell find . -name "*.scala") 25 | $(SBT) $(SBT_FLAGS) "run $(build_dir) $(firrtl) $(in_toml) $(out_toml)" 26 | 27 | verilog: $(verilog) 28 | 29 | harness_h = $(addprefix $(verilator_dir)/,fpga_queue.hpp fuzzer.hpp) 30 | harness_cc = $(addprefix $(verilator_dir)/,fpga_queue.cpp) 31 | 32 | driver_h = $(addprefix $(driver_dir)/,rfuzz.h) 33 | emul_cc = $(addprefix $(driver_dir)/,rfuzz-emul.cc) 34 | 35 | verilator = $(build_dir)/VVerilatorHarness 36 | verilator_debug = $(build_dir)/VVerilatorHarness-debug 37 | 38 | $(verilator) $(verilator_debug): export CXXFLAGS := $(CXXFLAGS) -std=c++14 -I$(verilator_dir) 39 | 40 | $(verilator): $(emul_cc) $(driver_h) $(harness_cc) $(harness_h) $(verilog) 41 | $(MAKE) -C $(simif_dir) verilator \ 42 | PLATFORM=$(PLATFORM) DESIGN=VerilatorHarness GEN_DIR=$(build_dir) \ 43 | DRIVER="$(emul_cc) $(harness_cc)" 44 | 45 | $(verilator_debug): $(emul_cc) $(driver_h) $(harness_cc) $(harness_h) $(verilog) 46 | $(MAKE) -C $(simif_dir) verilator-debug \ 47 | PLATFORM=$(PLATFORM) DESIGN=VerilatorHarness GEN_DIR=$(build_dir) \ 48 | DRIVER="$(emul_cc) $(harness_cc)" 49 | 50 | verilator: $(verilator) 51 | $< 2> $<.out 52 | 53 | verilator-debug: $(verilator_debug) 54 | $< +waveform=$<.vcd 2> $<.out 55 | 56 | vcs = $(build_dir)/VerilatorHarness 57 | vcs_debug = $(build_dir)/VerilatorHarness-debug 58 | 59 | $(vcs) $(vcs_debug): export CXXFLAGS := $(CXXFLAGS) -std=c++14 -I$(verilator_dir) 60 | 61 | $(vcs): $(emul_cc) $(driver_h) $(harness_cc) $(harness_h) $(verilog) 62 | $(MAKE) -C $(simif_dir) vcs \ 63 | PLATFORM=$(PLATFORM) DESIGN=VerilatorHarness GEN_DIR=$(build_dir) \ 64 | DRIVER="$(emul_cc) $(harness_cc)" 65 | 66 | $(vcs_debug): $(emul_cc) $(driver_h) $(harness_cc) $(harness_h) $(verilog) 67 | $(MAKE) -C $(simif_dir) vcs-debug \ 68 | PLATFORM=$(PLATFORM) DESIGN=VerilatorHarness GEN_DIR=$(build_dir) \ 69 | DRIVER="$(emul_cc) $(harness_cc)" 70 | 71 | vcs: $(vcs) 72 | $< 2> $<.out 73 | 74 | vcs-debug: $(vcs_debug) 75 | $< +waveform=$<.vpd 2> $<.out 76 | 77 | ifeq ($(PLATFORM),zynq) 78 | board ?= zedboard 79 | board_dir := $(fpga_dir)/$(board) 80 | bitstream := fpga-images-$(board)/boot.bin 81 | 82 | $(board_dir)/src/verilog/$(DUT)/FPGATop.v: $(verilog) 83 | $(MAKE) -C $(board_dir) clean DESIGN=$(DUT) 84 | mkdir -p $(dir $@) 85 | cp $< $@ 86 | 87 | fpga: $(board_dir)/src/verilog/$(DUT)/FPGATop.v 88 | mkdir -p $(build_dir)/$(board) 89 | $(MAKE) -C $(board_dir) $(bitstream) DESIGN=$(DUT) 90 | cp $(board_dir)/$(bitstream) $(build_dir)/$(board) 91 | 92 | include zynq.mk 93 | endif 94 | 95 | driver_cc = $(addprefix $(driver_dir)/,rfuzz-$(PLATFORM).cc) 96 | $(PLATFORM) = $(build_dir)/$(DUT)-$(PLATFORM) 97 | 98 | $($(PLATFORM)): $(driver_cc) $(simif_cc) $(simif_h) $(header) $(gmp) 99 | mkdir -p $(build_dir)/$(PLATFORM) 100 | cp $(header) $(build_dir)/$(PLATFORM) 101 | $(MAKE) -C $(simif_dir) $(PLATFORM) DESIGN=VerilatorHarness \ 102 | GEN_DIR=$(build_dir)/$(PLATFORM) DRIVER="$(driver_cc) $(harness_cc)" 103 | 104 | $(PLATFORM): $($(PLATFORM)) 105 | 106 | .PHONY: verilog 107 | .PHONY: verilator verilator-debug 108 | .PHONY: vcs vcs-debug 109 | .PHONY: fpga $(PLATFORM) 110 | -------------------------------------------------------------------------------- /midas/build.sbt: -------------------------------------------------------------------------------- 1 | // Provide a managed dependency on X if -DXVersion="" is supplied on the command line. 2 | val defaultVersions = Map( 3 | "chisel3" -> "3.0.0-RC1" 4 | ) 5 | 6 | val commonSettings = Seq( 7 | scalaVersion := "2.11.12", 8 | 9 | scalacOptions := Seq("-deprecation"), 10 | 11 | resolvers ++= Seq( 12 | Resolver.sonatypeRepo("snapshots"), 13 | Resolver.sonatypeRepo("releases") 14 | ), 15 | 16 | libraryDependencies ++= (Seq("chisel3").map { 17 | dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse( 18 | dep + "Version", defaultVersions(dep)) 19 | }), 20 | 21 | // toml-scala: https://github.com/sparsetech/toml-scala 22 | // (stoml does not support dates) 23 | libraryDependencies += "tech.sparse" %% "toml-scala" % "0.1.0", 24 | 25 | // For MIDAS 26 | libraryDependencies += "org.json4s" %% "json4s-native" % "3.5.3", 27 | 28 | // For MDF 29 | libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.2" 30 | ) 31 | 32 | lazy val mdf = (project in file("barstools/mdf/scalalib")) 33 | .settings(commonSettings) 34 | lazy val barstools = (project in file("barstools/macros")) 35 | .settings(commonSettings) 36 | .dependsOn(mdf) 37 | // Code taken from rocketchip for midas 38 | // Should be deleted when we decide to 39 | // import rocketchip 40 | lazy val lib = project 41 | .settings(commonSettings) 42 | lazy val midas = project 43 | .settings(commonSettings) 44 | .dependsOn(lib, barstools) 45 | 46 | lazy val harness = RootProject(file("../harness")) 47 | lazy val root = (project in file(".")) 48 | .settings(commonSettings ++ Seq( 49 | name := "rfuzz", 50 | version := "0.1")) 51 | .dependsOn(midas, harness) 52 | -------------------------------------------------------------------------------- /midas/lib/src/main/scala/config/Config.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE.SiFive for license details. 2 | 3 | package freechips.rocketchip.config 4 | 5 | abstract class Field[T] private (val default: Option[T]) 6 | { 7 | def this() = this(None) 8 | def this(default: T) = this(Some(default)) 9 | } 10 | 11 | abstract class View { 12 | final def apply[T](pname: Field[T]): T = apply(pname, this) 13 | final def apply[T](pname: Field[T], site: View): T = { 14 | val out = find(pname, site) 15 | require (out.isDefined, s"Key ${pname} is not defined in Parameters") 16 | out.get 17 | } 18 | 19 | final def lift[T](pname: Field[T]): Option[T] = lift(pname, this) 20 | final def lift[T](pname: Field[T], site: View): Option[T] = find(pname, site).map(_.asInstanceOf[T]) 21 | 22 | protected[config] def find[T](pname: Field[T], site: View): Option[T] 23 | } 24 | 25 | abstract class Parameters extends View { 26 | final def ++ (x: Parameters): Parameters = new ChainParameters(this, x) 27 | final def alter(f: (View, View, View) => PartialFunction[Any,Any]): Parameters = Parameters(f) ++ this 28 | final def alterPartial(f: PartialFunction[Any,Any]): Parameters = Parameters((_,_,_) => f) ++ this 29 | 30 | protected[config] def chain[T](site: View, tail: View, pname: Field[T]): Option[T] 31 | protected[config] def find[T](pname: Field[T], site: View) = chain(site, new TerminalView, pname) 32 | } 33 | 34 | object Parameters { 35 | def empty: Parameters = new EmptyParameters 36 | def apply(f: (View, View, View) => PartialFunction[Any,Any]): Parameters = new PartialParameters(f) 37 | def root(p: Parameters) = p 38 | } 39 | 40 | class Config(p: Parameters) extends Parameters { 41 | def this(f: (View, View, View) => PartialFunction[Any,Any]) = this(Parameters(f)) 42 | 43 | protected[config] def chain[T](site: View, tail: View, pname: Field[T]) = p.chain(site, tail, pname) 44 | override def toString = this.getClass.getSimpleName 45 | def toInstance = this 46 | } 47 | 48 | // Internal implementation: 49 | 50 | private class TerminalView extends View { 51 | def find[T](pname: Field[T], site: View): Option[T] = pname.default 52 | } 53 | 54 | private class ChainView(head: Parameters, tail: View) extends View { 55 | def find[T](pname: Field[T], site: View) = head.chain(site, tail, pname) 56 | } 57 | 58 | private class ChainParameters(x: Parameters, y: Parameters) extends Parameters { 59 | def chain[T](site: View, tail: View, pname: Field[T]) = x.chain(site, new ChainView(y, tail), pname) 60 | } 61 | 62 | private class EmptyParameters extends Parameters { 63 | def chain[T](site: View, tail: View, pname: Field[T]) = tail.find(pname, site) 64 | } 65 | 66 | private class PartialParameters(f: (View, View, View) => PartialFunction[Any,Any]) extends Parameters { 67 | protected[config] def chain[T](site: View, tail: View, pname: Field[T]) = { 68 | val g = f(site, this, tail) 69 | if (g.isDefinedAt(pname)) Some(g.apply(pname).asInstanceOf[T]) else tail.find(pname, site) 70 | } 71 | } 72 | -------------------------------------------------------------------------------- /midas/lib/src/main/scala/util/Arbiters.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE.Berkeley for license details. 2 | 3 | package junctions 4 | 5 | import Chisel._ 6 | import freechips.rocketchip.config.Parameters 7 | 8 | /** A generalized locking RR arbiter that addresses the limitations of the 9 | * version in the Chisel standard library */ 10 | abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false) 11 | extends Module { 12 | 13 | val io = new Bundle { 14 | val in = Vec(arbN, Decoupled(typ.cloneType)).flip 15 | val out = Decoupled(typ.cloneType) 16 | } 17 | 18 | def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = { 19 | val n = norm.size 20 | Vec.tabulate(n) { i => 21 | Mux(rot < UInt(n - i), norm(UInt(i) + rot), norm(rot - UInt(n - i))) 22 | } 23 | } 24 | 25 | val lockIdx = Reg(init = UInt(0, log2Up(arbN))) 26 | val locked = Reg(init = Bool(false)) 27 | 28 | val choice = if (rr) { 29 | PriorityMux( 30 | rotateLeft(Vec(io.in.map(_.valid)), lockIdx + UInt(1)), 31 | rotateLeft(Vec((0 until arbN).map(UInt(_))), lockIdx + UInt(1))) 32 | } else { 33 | PriorityEncoder(io.in.map(_.valid)) 34 | } 35 | 36 | val chosen = Mux(locked, lockIdx, choice) 37 | 38 | for (i <- 0 until arbN) { 39 | io.in(i).ready := io.out.ready && chosen === UInt(i) 40 | } 41 | 42 | io.out.valid := io.in(chosen).valid 43 | io.out.bits := io.in(chosen).bits 44 | } 45 | 46 | /** This locking arbiter determines when it is safe to unlock 47 | * by peeking at the data */ 48 | class HellaPeekingArbiter[T <: Data]( 49 | typ: T, arbN: Int, 50 | canUnlock: T => Bool, 51 | needsLock: Option[T => Bool] = None, 52 | rr: Boolean = false) 53 | extends HellaLockingArbiter(typ, arbN, rr) { 54 | 55 | def realNeedsLock(data: T): Bool = 56 | needsLock.map(_(data)).getOrElse(Bool(true)) 57 | 58 | when (io.out.fire()) { 59 | when (!locked && realNeedsLock(io.out.bits)) { 60 | lockIdx := choice 61 | locked := Bool(true) 62 | } 63 | // the unlock statement takes precedent 64 | when (canUnlock(io.out.bits)) { 65 | locked := Bool(false) 66 | } 67 | } 68 | } 69 | -------------------------------------------------------------------------------- /midas/lib/src/main/scala/util/Misc.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE.SiFive for license details. 2 | 3 | package freechips.rocketchip.util 4 | 5 | import Chisel._ 6 | import freechips.rocketchip.config.Parameters 7 | 8 | class ParameterizedBundle(implicit p: Parameters) extends Bundle { 9 | override def cloneType = { 10 | try { 11 | this.getClass.getConstructors.head.newInstance(p).asInstanceOf[this.type] 12 | } catch { 13 | case e: java.lang.IllegalArgumentException => 14 | throwException("Unable to use ParamaterizedBundle.cloneType on " + 15 | this.getClass + ", probably because " + this.getClass + 16 | "() takes more than one argument. Consider overriding " + 17 | "cloneType() on " + this.getClass, e) 18 | } 19 | } 20 | } 21 | 22 | abstract class GenericParameterizedBundle[+T <: Object](val params: T) extends Bundle 23 | { 24 | override def cloneType = { 25 | try { 26 | this.getClass.getConstructors.head.newInstance(params).asInstanceOf[this.type] 27 | } catch { 28 | case e: java.lang.IllegalArgumentException => 29 | throw new Exception("Unable to use GenericParameterizedBundle.cloneType on " + 30 | this.getClass + ", probably because " + this.getClass + 31 | "() takes more than one argument. Consider overriding " + 32 | "cloneType() on " + this.getClass, e) 33 | } 34 | } 35 | } 36 | 37 | object DecoupledHelper { 38 | def apply(rvs: Bool*) = new DecoupledHelper(rvs) 39 | } 40 | 41 | class DecoupledHelper(val rvs: Seq[Bool]) { 42 | def fire(exclude: Bool, includes: Bool*) = { 43 | (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) 44 | } 45 | } 46 | 47 | object MaskGen { 48 | def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { 49 | require (groupBy >= 1 && beatBytes >= groupBy) 50 | require (isPow2(beatBytes) && isPow2(groupBy)) 51 | val lgBytes = log2Ceil(beatBytes) 52 | val sizeOH = UIntToOH(lgSize, log2Up(beatBytes)) | UInt(groupBy*2 - 1) 53 | 54 | def helper(i: Int): Seq[(Bool, Bool)] = { 55 | if (i == 0) { 56 | Seq((lgSize >= UInt(lgBytes), Bool(true))) 57 | } else { 58 | val sub = helper(i-1) 59 | val size = sizeOH(lgBytes - i) 60 | val bit = addr_lo(lgBytes - i) 61 | val nbit = !bit 62 | Seq.tabulate (1 << i) { j => 63 | val (sub_acc, sub_eq) = sub(j/2) 64 | val eq = sub_eq && (if (j % 2 == 1) bit else nbit) 65 | val acc = sub_acc || (size && eq) 66 | (acc, eq) 67 | } 68 | } 69 | } 70 | 71 | if (groupBy == beatBytes) UInt(1) else 72 | Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) 73 | } 74 | } 75 | -------------------------------------------------------------------------------- /midas/lib/src/main/scala/util/MultiWidthFifo.scala: -------------------------------------------------------------------------------- 1 | // See LICENSE.Berkeley for license details. 2 | 3 | package freechips.rocketchip.util 4 | 5 | import Chisel._ 6 | 7 | class MultiWidthFifo(inW: Int, outW: Int, n: Int) extends Module { 8 | val io = new Bundle { 9 | val in = Decoupled(Bits(width = inW)).flip 10 | val out = Decoupled(Bits(width = outW)) 11 | val count = UInt(OUTPUT, log2Up(n + 1)) 12 | } 13 | 14 | if (inW == outW) { 15 | val q = Module(new Queue(Bits(width = inW), n)) 16 | q.io.enq <> io.in 17 | io.out <> q.io.deq 18 | io.count := q.io.count 19 | } else if (inW > outW) { 20 | val nBeats = inW / outW 21 | 22 | require(inW % outW == 0, s"MultiWidthFifo: in: $inW not divisible by out: $outW") 23 | require(n % nBeats == 0, s"Cannot store $n output words when output beats is $nBeats") 24 | 25 | val wdata = Reg(Vec(n / nBeats, Bits(width = inW))) 26 | val rdata = Vec(wdata.flatMap { indat => 27 | (0 until nBeats).map(i => indat(outW * (i + 1) - 1, outW * i)) }) 28 | 29 | val head = Reg(init = UInt(0, log2Up(n / nBeats))) 30 | val tail = Reg(init = UInt(0, log2Up(n))) 31 | val size = Reg(init = UInt(0, log2Up(n + 1))) 32 | 33 | when (io.in.fire()) { 34 | wdata(head) := io.in.bits 35 | head := head + UInt(1) 36 | } 37 | 38 | when (io.out.fire()) { tail := tail + UInt(1) } 39 | 40 | size := MuxCase(size, Seq( 41 | (io.in.fire() && io.out.fire()) -> (size + UInt(nBeats - 1)), 42 | io.in.fire() -> (size + UInt(nBeats)), 43 | io.out.fire() -> (size - UInt(1)))) 44 | 45 | io.out.valid := size > UInt(0) 46 | io.out.bits := rdata(tail) 47 | io.in.ready := size < UInt(n) 48 | io.count := size 49 | } else { 50 | val nBeats = outW / inW 51 | 52 | require(outW % inW == 0, s"MultiWidthFifo: out: $outW not divisible by in: $inW") 53 | 54 | val wdata = Reg(Vec(n * nBeats, Bits(width = inW))) 55 | val rdata = Vec.tabulate(n) { i => 56 | Cat(wdata.slice(i * nBeats, (i + 1) * nBeats).reverse)} 57 | 58 | val head = Reg(init = UInt(0, log2Up(n * nBeats))) 59 | val tail = Reg(init = UInt(0, log2Up(n))) 60 | val size = Reg(init = UInt(0, log2Up(n * nBeats + 1))) 61 | 62 | when (io.in.fire()) { 63 | wdata(head) := io.in.bits 64 | head := head + UInt(1) 65 | } 66 | 67 | when (io.out.fire()) { tail := tail + UInt(1) } 68 | 69 | size := MuxCase(size, Seq( 70 | (io.in.fire() && io.out.fire()) -> (size - UInt(nBeats - 1)), 71 | io.in.fire() -> (size + UInt(1)), 72 | io.out.fire() -> (size - UInt(nBeats)))) 73 | 74 | io.count := size >> UInt(log2Up(nBeats)) 75 | io.out.valid := io.count > UInt(0) 76 | io.out.bits := rdata(tail) 77 | io.in.ready := size < UInt(n * nBeats) 78 | } 79 | } 80 | -------------------------------------------------------------------------------- /midas/project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version=1.1.0 2 | -------------------------------------------------------------------------------- /midas/project/plugins.sbt: -------------------------------------------------------------------------------- 1 | addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") 2 | -------------------------------------------------------------------------------- /midas/src/main/cc/rfuzz-emul.cc: -------------------------------------------------------------------------------- 1 | #include "simif_emul.h" 2 | #include "rfuzz.h" 3 | 4 | class rfuzz_emul_t: 5 | public simif_emul_t, 6 | public rfuzz_t { }; 7 | 8 | int main(int argc, char** argv) 9 | { 10 | rfuzz_emul_t rfuzz; 11 | rfuzz.init(argc, argv, true); 12 | rfuzz.run(); 13 | return rfuzz.finish(); 14 | } 15 | -------------------------------------------------------------------------------- /midas/src/main/cc/rfuzz-zynq.cc: -------------------------------------------------------------------------------- 1 | #include "simif_zynq.h" 2 | #include "rfuzz.h" 3 | 4 | class rfuzz_zynq_t: 5 | public simif_zynq_t, 6 | public rfuzz_t { }; 7 | 8 | int main(int argc, char** argv) 9 | { 10 | rfuzz_zynq_t rfuzz; 11 | rfuzz.init(argc, argv, true); 12 | rfuzz.run(); 13 | return rfuzz.finish(); 14 | } 15 | -------------------------------------------------------------------------------- /midas/src/main/cc/rfuzz.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "simif.h" 4 | 5 | class rfuzz_t: virtual simif_t { 6 | public: 7 | rfuzz_t() { 8 | fuzzer.init(PEEK_SIZE); 9 | } 10 | void run() { 11 | while (!fuzzer.done()) run_test(); 12 | } 13 | 14 | private: 15 | ActiveFuzzer fuzzer; 16 | 17 | inline void apply_input(const uint8_t* input) { 18 | // exclude reset 19 | for (size_t i = 0 ; i < POKE_SIZE-1 ; i++) { 20 | poke(i+1, input[i]); 21 | } 22 | fprintf(stderr, "[rfuzz] sent input\n"); 23 | } 24 | 25 | inline void read_coverage(uint8_t* output) { 26 | for (size_t i = 0 ; i < PEEK_SIZE ; i++) { 27 | output[i] = peek(i); 28 | } 29 | fprintf(stderr, "[rfuzz] read coverage\n"); 30 | } 31 | 32 | inline void run_test() { 33 | target_reset(); 34 | uint8_t input[POKE_SIZE-1]; 35 | while (fuzzer.pop(input, POKE_SIZE-1)) { 36 | apply_input(input); 37 | step(1); 38 | } 39 | step(1); 40 | uint8_t coverage[PEEK_SIZE]; 41 | read_coverage(coverage); 42 | fuzzer.push(coverage, PEEK_SIZE); 43 | } 44 | }; 45 | -------------------------------------------------------------------------------- /midas/src/main/scala/midas.scala: -------------------------------------------------------------------------------- 1 | package rfuzz 2 | 3 | import pynq._ 4 | import midas._ 5 | import firrtl._ 6 | import firrtl.ir._ 7 | import freechips.rocketchip.config.Parameters 8 | import java.io.{File, FileWriter} 9 | 10 | private[rfuzz] class ReplaceDUT(dut: Circuit) extends firrtl.passes.Pass { 11 | override def name = "[rfuzz] Replace DUT" 12 | 13 | def run(c: Circuit): Circuit = { 14 | c.copy(modules = dut.modules ++ (c.modules flatMap { 15 | case m: ExtModule if m.name == dut.main => None 16 | case m => Some(m) 17 | })) 18 | } 19 | } 20 | 21 | private[rfuzz] class FuzzTransforms(dut: Circuit) extends SeqTransform { 22 | def inputForm = HighForm 23 | def outputForm = HighForm 24 | def transforms = Seq( 25 | new ReplaceDUT(dut), 26 | new IRToWorkingIR, 27 | firrtl.passes.InferTypes, 28 | firrtl.passes.CheckTypes, 29 | firrtl.passes.InferWidths, 30 | firrtl.passes.CheckWidths 31 | ) 32 | } 33 | 34 | class CustomVerilogCompiler extends Compiler { 35 | def emitter = new VerilogEmitter 36 | def transforms = Seq(new LowFirrtlOptimization) 37 | } 38 | 39 | object MidasGenerator extends App { 40 | require(args.length == 4, "[usage] ") 41 | val dir = args(0) 42 | val benchmark = args(1) 43 | val inToml = args(2) 44 | val outToml = args(3) 45 | 46 | /* 47 | val state = hardwareafl.firrtltransforms.CustomTop.compile(Array( 48 | "-i", benchmark, 49 | "-o", (new File(dir, s"${dut}.v")).toString, 50 | "-X", "verilog", 51 | "-ll", "info", 52 | "-fct", Seq( 53 | "hardwareafl.firrtltransforms.SplitMuxConditions", 54 | "hardwareafl.firrtltransforms.ProfilingTransform", 55 | "firrtl.passes.wiring.WiringTransform") mkString ",")) 56 | */ 57 | 58 | val ir = Parser.parse(io.Source.fromFile(benchmark).getLines) 59 | val conf = Config.loadToml(inToml) 60 | println(s"Conf: ${conf}") 61 | // super hacky "out parameter" to get list of counters from Harness design 62 | val counters = collection.mutable.ArrayBuffer[Config.Counter]() 63 | MidasCompiler( 64 | new VerilatorHarness(conf, counters), 65 | new File(dir), 66 | customTransforms = Seq(new FuzzTransforms(ir)))( 67 | Parameters.root(new midas.ZynqConfig)) 68 | Config.writeAugmentedToml(inToml, outToml, counters.toSeq) 69 | } 70 | -------------------------------------------------------------------------------- /midas/zynq.mk: -------------------------------------------------------------------------------- 1 | host = arm-xilinx-linux-gnueabi 2 | 3 | # Compile gmp 4 | GMP_VERSION ?= 6.1.2 5 | gmp_src_dir := $(build_dir)/$(PLATFORM)/gmp-$(GMP_VERSION) 6 | gmp_build_dir := $(gmp_src_dir)/build 7 | gmp_install_dir := $(gmp_src_dir)/install 8 | gmp_lib := $(gmp_install_dir)/lib/libgmp.so 9 | gmp := $(build_dir)/$(PLATFORM)/libgmp.so.10 10 | 11 | $(build_dir)/$(PLATFORM)/gmp-$(GMP_VERSION).tar.bz2: 12 | mkdir -p $(dir $@) 13 | cd $(dir $@) && wget https://gmplib.org/download/gmp/gmp-$(GMP_VERSION).tar.bz2 14 | 15 | $(gmp_src_dir): $(build_dir)/$(PLATFORM)/gmp-$(GMP_VERSION).tar.bz2 16 | cd $(dir $<) && tar -xf $< 17 | 18 | $(gmp_lib): $(gmp_src_dir) 19 | mkdir -p $(gmp_build_dir) 20 | cd $(gmp_build_dir) && \ 21 | ../configure --prefix=$(gmp_install_dir) --host=$(host) && \ 22 | $(MAKE) && $(MAKE) install 23 | 24 | $(gmp): $(gmp_lib) 25 | cp $< $@ 26 | 27 | export AR := $(host)-ar 28 | export CXX := $(host)-g++ 29 | export CXXFLAGS := $(CXXFLAGS) -I$(gmp_install_dir)/include 30 | export LDFLAGS := -L$(gmp_install_dir)/lib -Wl,-rpath,/usr/local/lib 31 | -------------------------------------------------------------------------------- /results/Readme.md: -------------------------------------------------------------------------------- 1 | # Results 2 | 3 | This directory hold some preliminary results from various stages 4 | of the development. 5 | 6 | Please document the circumstances under which the results were 7 | produced in this Readme. 8 | 9 | ## 4.jqf2.i2c 10 | 11 | This is a run fuzzing the TLI2C circuit with the newly implemented 12 | full JQF (level 2) with a separate coverage map. 13 | The results look incredibly good, achieving 95% mux toggle coverage 14 | compared to the 25% achieved by the base line (counting only valid inputs). 15 | We will need to verify whether these results are credible... 16 | 17 | Git SHA: ad844b0f15547fafbf08e0e3507b09ad24acb322 18 | 19 | ## 1.jqf2.i2c 20 | 21 | We were able to reproduce the coverage from `4.jqf2.i2c` by fuzzing for an hour. 22 | This time it took ~40min to reach the same coverage as the previous run achieved 23 | in ~4min. However at least it seems reproducible. 24 | 25 | ## rocket 26 | 27 | Some early rocket results from running it in simulation for about 2h @ ~16kHz. -------------------------------------------------------------------------------- /verilator/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | -------------------------------------------------------------------------------- /verilator/afl.c: -------------------------------------------------------------------------------- 1 | // Based on code by Laszlo Szekeres and 2 | // Michal Zalewski 3 | // LLVM integration design comes from Laszlo Szekeres. 4 | // 5 | // Copyright 2015, 2016 Google Inc. All rights reserved. 6 | // Copyright 2017, Kevin Laeufer 7 | // 8 | // Licensed under the Apache License, Version 2.0 (the "License"); 9 | // you may not use this file except in compliance with the License. 10 | // You may obtain a copy of the License at: 11 | // http://www.apache.org/licenses/LICENSE-2.0 12 | 13 | #include 14 | #include 15 | #include 16 | 17 | #include 18 | #include 19 | 20 | // from `config.h` in AFL 21 | #define MAP_SIZE_POW2 16 22 | #define MAP_SIZE (1 << MAP_SIZE_POW2) 23 | #define SHM_ENV_VAR "__AFL_SHM_ID" 24 | #define FORKSRV_FD 198 25 | 26 | /* Globals needed by the injected instrumentation. The __afl_area_initial region 27 | is used for instrumentation output before __afl_map_shm() has a chance to run. 28 | It will end up as .comm, so it shouldn't be too wasteful. */ 29 | uint8_t __afl_area_initial[MAP_SIZE]; 30 | uint8_t* __afl_area_ptr = __afl_area_initial; 31 | 32 | __thread uint32_t __afl_prev_loc; 33 | 34 | static void __afl_map_shm() { 35 | char *id_str = getenv(SHM_ENV_VAR); 36 | 37 | // If we're running under AFL, attach to the appropriate region, replacing the 38 | // early-stage __afl_area_initial region that is needed to allow some really 39 | //hacky .init code to work correctly in projects such as OpenSSL. 40 | if (id_str) { 41 | uint32_t shm_id = atoi(id_str); 42 | __afl_area_ptr = (uint8_t*)shmat(shm_id, NULL, 0); 43 | 44 | // Whooooops. 45 | if (__afl_area_ptr == (void *)-1) { _exit(1); } 46 | 47 | // Write something into the bitmap so that even with low AFL_INST_RATIO, 48 | // our parent doesn't give up on us. 49 | __afl_area_ptr[0] = 1; 50 | } 51 | } 52 | 53 | 54 | /* Fork server logic. */ 55 | 56 | static void __afl_start_forkserver() { 57 | // Phone home and tell the parent that we're OK. If parent isn't there, 58 | // assume we're not running in forkserver mode and just execute program. 59 | uint8_t tmp[4] = {0, 0, 0, 0}; 60 | if (write(FORKSRV_FD + 1, tmp, 4) != 4) { return; } 61 | 62 | pid_t child_pid; 63 | while (1) { 64 | 65 | uint32_t was_killed; 66 | int status; 67 | 68 | // Wait for parent by reading from the pipe. Abort if read fails. 69 | if (read(FORKSRV_FD, &was_killed, 4) != 4) _exit(1); 70 | 71 | // Once woken up, create a clone of our process. 72 | child_pid = fork(); 73 | if (child_pid < 0) { _exit(1); } 74 | 75 | // In child process: close fds, resume execution. 76 | if (!child_pid) { 77 | close(FORKSRV_FD); 78 | close(FORKSRV_FD + 1); 79 | return; 80 | } 81 | 82 | // In parent process: write PID to pipe, then wait for child. 83 | if (write(FORKSRV_FD + 1, &child_pid, 4) != 4) { _exit(1); } 84 | if (waitpid(child_pid, &status, 0) < 0) { _exit(1); } 85 | 86 | // Relay wait status to pipe, then loop back. 87 | if (write(FORKSRV_FD + 1, &status, 4) != 4) { _exit(1); } 88 | } 89 | } 90 | 91 | void afl_init() { 92 | static uint8_t init_done; 93 | if (!init_done) { 94 | __afl_map_shm(); 95 | __afl_start_forkserver(); 96 | init_done = 1; 97 | } 98 | } 99 | -------------------------------------------------------------------------------- /verilator/afl.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017, Kevin Laeufer 2 | // 3 | // Licensed under the Apache License, Version 2.0 (the "License"); 4 | // you may not use this file except in compliance with the License. 5 | // You may obtain a copy of the License at: 6 | // http://www.apache.org/licenses/LICENSE-2.0 7 | 8 | #ifndef AFL_H 9 | #define AFL_H 10 | 11 | #include 12 | 13 | /// call at the beginning of main to start fork server 14 | void afl_init(); 15 | 16 | extern uint8_t* __afl_area_ptr; 17 | static inline void afl_increment(uint16_t id) 18 | { __afl_area_ptr[id]++; } 19 | static inline void afl_set(uint16_t id, uint8_t value) 20 | { __afl_area_ptr[id] = value; } 21 | static inline uint8_t afl_get(uint16_t id) 22 | { return __afl_area_ptr[id]; } 23 | static inline void afl_copy(const void* src, size_t len) 24 | { memcpy(__afl_area_ptr, src, len); } 25 | 26 | #endif // AFL_H 27 | -------------------------------------------------------------------------------- /verilator/afl.hpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017, Kevin Laeufer 2 | 3 | // implements the fuzzer interface for working with afl 4 | 5 | #ifndef AFL_HPP 6 | #define AFL_HPP 7 | 8 | #include 9 | #include 10 | 11 | class AflFuzzer : public Fuzzer { 12 | private: 13 | static constexpr size_t MaxInputBytes = sizeof(InputType) * 1024; 14 | // afl only does a one shot test, after that the program is reset by the forkserver 15 | bool first_test = true; 16 | std::vector inputs; 17 | int next_input = 0; 18 | void read_input() { 19 | char input_buffer[MaxInputBytes]; 20 | cin.read(input_buffer, MaxInputBytes); 21 | const auto len = cin.gcount(); 22 | const auto input_count = len / sizeof(InputType); 23 | auto items = reinterpret_cast(input_buffer); 24 | std::cout << "input_count: " << input_count << std::endl; 25 | for(int ii = 0; ii < input_count; ii++) { 26 | inputs.push_back(items[ii]); 27 | } 28 | } 29 | public: 30 | void init() override { 31 | afl_init(); 32 | read_input(); 33 | } 34 | bool done() override { 35 | if(first_test) { first_test = false; return false; } 36 | else { return true; } 37 | } 38 | bool pop(InputType* input) override { 39 | if(next_input >= inputs.size()) { 40 | return false; 41 | } else { 42 | *input = inputs[next_input]; 43 | next_input += 1; 44 | return true; 45 | } 46 | } 47 | void push(const CoverageType& coverage) override { 48 | afl_copy(static_cast(&coverage), sizeof(CoverageType)); 49 | } 50 | }; 51 | 52 | using ActiveFuzzer = AflFuzzer; 53 | #endif // AFL_HPP 54 | -------------------------------------------------------------------------------- /verilator/dut_gen.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # -*- coding: utf-8 -*- 3 | 4 | # Copyright 2018, Kevin Laeufer 5 | 6 | # Generates the `dut.hpp` file which contains dut specific interface code 7 | # from the TOML dut description file. 8 | 9 | import os, sys, argparse 10 | import toml 11 | 12 | template = """ 13 | // This file was generated from {conf_toml} using the dut_gen.py script. 14 | // It contains DUt specific interface code for the verilator C++ test harness. 15 | 16 | #ifndef DUT_CONF_HPP 17 | #define DUT_CONF_HPP 18 | 19 | #if defined(E2E) 20 | #include 21 | #define TOP_TYPE V{toplevel}_E2EHarness 22 | #else 23 | #include 24 | #define TOP_TYPE V{toplevel}_VHarness 25 | #endif 26 | 27 | #define TOPLEVEL_STR "{toplevel}" 28 | 29 | static constexpr size_t CoverageSize = {cov_size}; 30 | static constexpr size_t InputSize = {input_size}; 31 | 32 | static inline void apply_input(TOP_TYPE* top, const uint8_t* input) {{ 33 | {apply_input} 34 | }} 35 | static inline void read_coverage(TOP_TYPE* top, uint8_t* coverage) {{ 36 | {read_coverage} 37 | }} 38 | 39 | #endif // DUT_CONF_HPP 40 | """ 41 | 42 | 43 | align = 8 44 | def bits_to_size(bits): 45 | bytes = (bits + 7) // 8 46 | words = (bytes + align - 1) // align 47 | return words * align 48 | 49 | if __name__ == '__main__': 50 | parser = argparse.ArgumentParser( 51 | description='generate DUT specific verilator code') 52 | parser.add_argument('-o', '--output', help='dut header file name', required=True) 53 | parser.add_argument('-i', '--input', help='toml dut description', required=True) 54 | args = parser.parse_args() 55 | 56 | 57 | conf_toml = args.input 58 | if not os.path.isfile(conf_toml): 59 | sys.stderr.write("dur config file `{}` not found\n".format(conf_toml)) 60 | sys.exit(1) 61 | 62 | header = args.output 63 | header_dir = os.path.dirname(os.path.abspath(header)) 64 | if not os.path.isdir(header_dir): 65 | sys.stderr.write("output directory `{}` does not exist\n".format(header_dir)) 66 | sys.exit(1) 67 | 68 | conf = toml.loads(open(conf_toml).read()) 69 | input_bits = sum(ii['width'] for ii in conf['input']) 70 | input_size = bits_to_size(input_bits) 71 | cov_bits = sum(counter['width'] for counter in conf['counter']) 72 | # the cycles count in front of the coverage feedback takes 16bit 73 | cov_size = bits_to_size(cov_bits + 2 * 8) - 2 74 | 75 | i_line = "\ttop->io_input_bytes_{0: <3} = input[{0: >3}];" 76 | c_line = "\tcoverage[{0: >3}] = top->io_coverage_bytes_{0};" 77 | dd = { 'conf_toml': conf_toml, 'toplevel': conf['general']['top'], 78 | 'cov_size': cov_size, 'input_size': input_size, 79 | 'apply_input': "\n".join(i_line.format(ii) for ii in range(input_size)), 80 | 'read_coverage': "\n".join(c_line.format(ii) for ii in range(cov_size)) 81 | } 82 | 83 | output = template.format(**dd) 84 | open(header, 'w').write(output) -------------------------------------------------------------------------------- /verilator/fuzzer.hpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017, Kevin Laeufer 2 | 3 | // this file contains a C++ interface for interacting with a fuzzer 4 | 5 | #ifndef FUZZER_HPP 6 | #define FUZZER_HPP 7 | #include 8 | #include 9 | #include 10 | struct Fuzzer { 11 | /// called before the simulation is initialized 12 | virtual void init(size_t coverage_size, size_t input_size, const std::string&) { 13 | this->coverage_size = coverage_size; 14 | this->input_size = input_size; 15 | } 16 | /// called inbetween tests to check if there is more data availabel 17 | virtual bool done() { return true; } 18 | /// returns false on last input of a single test 19 | virtual bool pop(uint8_t* input, size_t len) = 0; 20 | virtual void push(const uint8_t* coverage, size_t len) = 0; 21 | virtual ~Fuzzer(){} 22 | protected: 23 | size_t coverage_size = 0; 24 | size_t input_size = 0; 25 | }; 26 | 27 | #endif // FUZZER_HPP 28 | -------------------------------------------------------------------------------- /verilator/meson.build: -------------------------------------------------------------------------------- 1 | project('fuzz-server', 'cpp', default_options : ['cpp_std=c++11'], version: '0.0.1') 2 | 3 | 4 | # generate verilator 5 | # TODO: integrate sbt 6 | # sbt = find_program('sbt') 7 | # verilog = custom_target('chisel', 8 | # output : 'UartDecoder.v', 9 | # input : '../src/main/scala/UartDecoder.scala', 10 | # depend_files: '../build.sbt', 11 | # command : [sbt, '"run -X verilog --target-dir ."']) 12 | 13 | dut = get_option('dut') 14 | build = get_option('build_dir') 15 | top = '@0@/@1@_VHarness.v'.format(build, dut) 16 | dependencies = ['@0@/@1@.v'.format(build, dut)] 17 | toml = '@0@/@1@.toml'.format(build, dut) 18 | exe = 'server' 19 | 20 | # custom verilator target 21 | verilator_py = find_program('verilator.py') 22 | verilator = dependency('verilator', version: '>= 3.886') 23 | verilator_defines = ['-DVL_PRINTF=printf', '-DVM_COVERAGE=0', '-DVM_SC=0', '-DVL_USER_FINISH'] 24 | verilator_warnings = ['-Wno-char-subscripts', '-Wno-sign-compare', 25 | '-Wno-uninitialized', '-Wno-unused-but-set-variable', 26 | '-Wno-unused-parameter', '-Wno-unused-variable'] 27 | toplevel = '@0@_VHarness'.format(dut) 28 | verilator_files = ['V@0@.h'.format(toplevel), 29 | 'V@0@__Syms.h'.format(toplevel), 30 | #'V@0@__Inlines.h'.format(toplevel), 31 | 'V@0@.cpp'.format(toplevel), 32 | 'V@0@__Syms.cpp'.format(toplevel), 33 | 'verilated_vcd_c.cpp', 'verilated.cpp'] 34 | if get_option('trace') 35 | verilator_cmd = [verilator_py, '--trace'] 36 | verilator_defines += ['-DVM_TRACE=1'] 37 | verilator_files += ['V@0@__Trace.cpp'.format(toplevel), 38 | 'V@0@__Trace__Slow.cpp'.format(toplevel)] 39 | else 40 | verilator_cmd = [verilator_py] 41 | endif 42 | # TODO: potentially change to be a `generator`: http://mesonbuild.com/Generating-sources.html 43 | verilator_src = custom_target('verilator', 44 | output : verilator_files, 45 | input : [top] + dependencies, 46 | command : verilator_cmd + ['-o', '@OUTPUT@', '-i', '@INPUT@']) 47 | libsim = static_library('sim', verilator_src, dependencies: [verilator], 48 | cpp_args: verilator_defines + verilator_warnings + ['-faligned-new']) 49 | libsim_dep = declare_dependency( 50 | # TODO: is there a less hacky way to filter out the headerfiles? 51 | sources: [verilator_src[0], verilator_src[1]], 52 | link_with: libsim) 53 | 54 | 55 | # DUT adapter header file generator 56 | dut_gen_py = find_program('dut_gen.py') 57 | dut_hpp = custom_target('dut_hpp', output : 'dut.hpp', input : toml, 58 | command : [dut_gen_py, '-o', '@OUTPUT@', '-i', '@INPUT@']) 59 | 60 | 61 | sources = ['top.cpp', 'fpga_queue.cpp', dut_hpp] 62 | executable(exe, sources, 63 | cpp_args: verilator_defines + ['-faligned-new'], 64 | dependencies: [libsim_dep, verilator]) 65 | -------------------------------------------------------------------------------- /verilator/meson_options.txt: -------------------------------------------------------------------------------- 1 | option('trace', type: 'boolean', value: false) 2 | option('build_dir', type: 'string', value: '../build') 3 | option('dut', type: 'string', value: 'nan') 4 | --------------------------------------------------------------------------------