├── .github └── workflows │ ├── release.yml │ └── test.yml ├── .gitignore ├── Cargo.toml ├── LICENSE ├── Readme.md ├── pywellen ├── .gitignore ├── Cargo.toml ├── Makefile ├── Readme.md ├── pyproject.toml ├── pywellen │ ├── __init__.py │ └── pywellen.pyi ├── src │ ├── convert.rs │ └── lib.rs └── tests │ └── test_waveform.py ├── wellen ├── Cargo.toml ├── LICENSE ├── Readme.md ├── benches │ └── wavemem.rs ├── examples │ └── load_signals.rs ├── inputs │ ├── VCD_file_with_errors.vcd │ ├── VCD_file_with_errors.vcd.fst │ ├── aldec │ │ ├── SPI_Write.vcd │ │ └── SPI_Write.vcd.fst │ ├── amaranth │ │ ├── array-names_wellen_issue_36.vcd │ │ ├── up_counter.vcd │ │ └── up_counter.vcd.fst │ ├── gameroy │ │ └── trace_prefix.vcd │ ├── ghdl │ │ ├── alu.vcd │ │ ├── alu.vcd.fst │ │ ├── ghdl_issue_538.ghw │ │ ├── idea.vcd │ │ ├── idea.vcd.fst │ │ ├── oscar │ │ │ ├── ali.ghw │ │ │ ├── ali.vhdl │ │ │ ├── ghdl.fst │ │ │ ├── ghdl.fst.vcd │ │ │ ├── test.ghw │ │ │ ├── test.vhdl │ │ │ ├── test2.ghw │ │ │ ├── test2.vhdl │ │ │ ├── vhdl3.fst │ │ │ ├── vhdl3.fst.vcd │ │ │ ├── vhdl3.vcd │ │ │ ├── vhdl3_conv.vcd │ │ │ └── vhdltype.vcd │ │ ├── pcpu.vcd │ │ ├── pcpu.vcd.fst │ │ ├── tb_recv.ghw │ │ ├── time_test.ghw │ │ ├── time_test.vhdl │ │ ├── wellen_issue_12.ghw │ │ ├── wellen_issue_32.ghw │ │ ├── wellen_issue_34.ghw │ │ ├── wellen_issue_35.ghw │ │ ├── wellen_issue_53.ghw │ │ └── wellen_issue_6.ghw │ ├── github_issues │ │ ├── issue18.vcd │ │ ├── issue28.vcd │ │ ├── issue40.vcd │ │ └── issue42.vcd │ ├── gtkwave-analyzer │ │ ├── des.fst │ │ ├── perm_current.vcd │ │ ├── perm_current.vcd.fst │ │ ├── transaction.fst │ │ └── vcd_extensions.vcd │ ├── icarus │ │ ├── CPU.vcd │ │ ├── CPU.vcd.fst │ │ ├── DCCrossbar.vcd │ │ ├── gatelevel_netlist_large_hierarchy_wellen_pull_61.vcd │ │ ├── rv32_soc_TB.vcd │ │ ├── rv32_soc_TB.vcd.fst │ │ ├── surfer_issue_256.vcd │ │ ├── test1.vcd │ │ └── test1.vcd.fst │ ├── jtag │ │ └── atxmega256a3u-bmda-jtag.vcd │ ├── migen │ │ ├── fractional_time_stamp.vcd │ │ ├── migen.vcd │ │ └── migen_original.vcd │ ├── model-sim │ │ ├── CPU_Design.msim.vcd │ │ ├── CPU_Design.msim.vcd.fst │ │ ├── clkdiv2n_tb.vcd │ │ └── clkdiv2n_tb.vcd.fst │ ├── my-hdl │ │ ├── Simple_Memory.vcd │ │ ├── Simple_Memory.vcd.fst │ │ ├── sigmoid_tb.vcd │ │ ├── sigmoid_tb.vcd.fst │ │ ├── top.vcd │ │ └── top.vcd.fst │ ├── ncsim │ │ ├── ffdiv_32bit_tb.vcd │ │ └── ffdiv_32bit_tb.vcd.fst │ ├── nvc │ │ ├── overlay_tb_issue_21.fst │ │ ├── vhdl_test_bool_issue_16.fst │ │ ├── xwb_fofb_shaper_filt_tb.fst │ │ ├── xwb_fofb_shaper_filt_tb_arrays.fst │ │ └── xwb_fofb_shaper_filt_tb_arrays.fst.vcd │ ├── pymtl3 │ │ └── CGRA.vcd │ ├── quartus │ │ ├── mipsHardware.vcd │ │ ├── mipsHardware.vcd.fst │ │ ├── wave_registradores.vcd │ │ └── wave_registradores.vcd.fst │ ├── questa-sim │ │ ├── dump.vcd │ │ ├── dump.vcd.fst │ │ ├── test.vcd │ │ ├── test.vcd.fst │ │ └── wellen-issue-57-uart.vcd │ ├── riviera-pro │ │ ├── dump.vcd │ │ └── dump.vcd.fst │ ├── scope_with_comment.vcd │ ├── scope_with_comment.vcd.fst │ ├── sigrok │ │ ├── libsigrok.vcd │ │ └── libsigrok.vcd.fst │ ├── sources.csv │ ├── specs │ │ ├── Readme.md │ │ └── tracefile.vcd │ ├── surfer │ │ ├── counter.vcd │ │ ├── counter.vcd.fst │ │ ├── issue_145.vcd │ │ ├── issue_145.vcd.fst │ │ ├── picorv32.vcd │ │ ├── picorv32.vcd.fst │ │ ├── spade.vcd │ │ ├── spade.vcd.fst │ │ ├── verilator_empty_scope.vcd │ │ ├── verilator_empty_scope.vcd.fst │ │ ├── xx_1.vcd │ │ ├── xx_1.vcd.fst │ │ ├── xx_2.vcd │ │ └── xx_2.vcd.fst │ ├── systemc │ │ ├── waveform.vcd │ │ ├── waveform.vcd.dual_lz4.fst │ │ ├── waveform.vcd.fastlz.fst │ │ ├── waveform.vcd.fastlz_lvl2.fst │ │ └── waveform.vcd.fst │ ├── treadle │ │ ├── GCD.vcd │ │ └── GCD.vcd.fst │ ├── vcs │ │ ├── Apb_slave_uvm_new.vcd │ │ ├── Apb_slave_uvm_new.vcd.fst │ │ ├── datapath_log.vcd │ │ ├── datapath_log.vcd.fst │ │ ├── processor.vcd │ │ └── processor.vcd.fst │ ├── verilator │ │ ├── basic_test.fst │ │ ├── many_sv_datatypes.fst │ │ ├── surfer_issue_201.fst │ │ ├── surfer_issue_201.vcd │ │ ├── swerv1.vcd │ │ ├── swerv1.vcd.fst │ │ ├── verilator-incomplete.fst │ │ ├── verilator-incomplete.fst.hier │ │ ├── vlt_dump.vcd │ │ └── vlt_dump.vcd.fst │ ├── vivado │ │ ├── iladata.vcd │ │ ├── iladata.vcd.fst │ │ └── vivado_surfer_test.vcd │ ├── wellen │ │ └── issue_5.vcd │ ├── wikipedia │ │ └── example.vcd │ ├── xilinx_isim │ │ ├── test.vcd │ │ ├── test.vcd.fst │ │ ├── test1.vcd │ │ ├── test1.vcd.fst │ │ ├── test2x2_regex22_string1.vcd │ │ └── test2x2_regex22_string1.vcd.fst │ └── yosys_smtbmc │ │ └── surfer_issue_315.vcd ├── src │ ├── compressed.rs │ ├── fst.rs │ ├── ghw │ │ ├── common.rs │ │ ├── hierarchy.rs │ │ ├── mod.rs │ │ └── signals.rs │ ├── hierarchy.rs │ ├── lib.rs │ ├── signals.rs │ ├── simple.rs │ ├── stream.rs │ ├── vcd.rs │ ├── viewers.rs │ └── wavemem.rs └── tests │ ├── compressed.rs │ ├── detect.rs │ ├── diff_ghw.rs │ ├── diff_tests.rs │ ├── fst.rs │ ├── ghw.rs │ ├── stream.rs │ ├── surfer.rs │ ├── utils.rs │ ├── vcd.rs │ └── vhdl.rs └── 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