├── .gitignore ├── .gitmodules ├── LICENSE ├── README.md ├── doc ├── fossi.parallela.risc-v.proposal.pdf └── images │ ├── old │ ├── vivado.parallella.riscv.bd.png │ └── vivado.parallella.riscv.rv64g.bd.png │ ├── timing │ ├── vivado.parallella.riscv.setup.violations.erx.fifos.sync.reset.png │ └── vivado.parallella.riscv.setup.violations.etx.mmcm.clk.slow.75MHz.io.edgealign.png │ └── vivado.parallella.riscv.system.bd.png ├── examples └── hello │ ├── .gitignore │ └── hello.c ├── ip ├── .gitignore ├── RISCV_Rocket_Core_RV64_1.0 │ ├── LICENSE │ ├── bd │ │ └── bd.tcl │ ├── component.xml │ ├── drivers │ │ └── RISCV_Rocket_Core_RV64_v1_0 │ │ │ ├── data │ │ │ ├── RISCV_Rocket_Core_RV64.mdd │ │ │ └── RISCV_Rocket_Core_RV64.tcl │ │ │ └── src │ │ │ ├── Makefile │ │ │ ├── RISCV_Rocket_Core_RV64.c │ │ │ ├── RISCV_Rocket_Core_RV64.h │ │ │ └── RISCV_Rocket_Core_RV64_selftest.c │ ├── example_designs │ │ ├── bfm_design │ │ │ ├── RISCV_Rocket_Core_RV64_v1_0_tb.v │ │ │ └── design.tcl │ │ └── debug_hw_design │ │ │ ├── RISCV_Rocket_Core_RV64_v1_0_hw_test.tcl │ │ │ └── design.tcl │ ├── src │ │ ├── AsyncResetReg.v │ │ ├── RISCV_Rocket_Core_RV64.v │ │ ├── RISCV_Rocket_Core_RV64_AXI.v │ │ ├── RV64IMAFD.Core.vh │ │ ├── plusarg_reader.v │ │ └── settings.vh │ └── xgui │ │ └── RISCV_Rocket_Core_RV64_v1_0.tcl └── rocket-zynq │ ├── .gitignore │ ├── LICENSE │ ├── csrc │ ├── fesvr_zynq.cc │ ├── zynq_driver.cc │ └── zynq_driver.h │ ├── generate-pkg-mk.sh │ ├── project │ ├── .gitignore │ ├── build.properties │ └── build.scala │ └── src │ └── main │ └── scala │ ├── Configs.scala │ ├── Drivers.scala │ ├── Generator.scala │ ├── Serdes.scala │ ├── TestHarness.scala │ ├── Top.scala │ └── ZynqAdapter.scala ├── parallella ├── Makefile ├── dts │ ├── settings.h │ ├── skeleton.dtsi │ ├── zynq-7000.dtsi │ ├── zynq-parallella-headless.dts │ ├── zynq-parallella.dts │ └── zynq-parallella1.dtsi ├── dv │ ├── dut_riscv_rv64g.v │ ├── run.sh │ └── tests │ │ └── hello_world.emf ├── fpga │ ├── .gitignore │ ├── ip_package_parallella.tcl │ ├── ip_package_riscv.tcl │ ├── ip_params_parallella.tcl │ ├── ip_params_riscv.tcl │ ├── system_bd.tcl │ ├── system_bitstream.tcl │ ├── system_params.tcl │ └── system_project.tcl ├── hdl │ └── riscv.rv64 ├── kernel │ └── parallella_defconfig ├── output │ ├── boot │ │ ├── .gitignore │ │ ├── bit2bin.bif │ │ └── dummy.elf │ └── final │ │ ├── .gitignore │ │ ├── empty │ │ └── riscv │ │ ├── .gitignore │ │ └── empty └── uboot │ └── adapteva_parallella.h ├── scripts ├── Makefile ├── build.fpga.bitstream.sh ├── build.host.software.sh ├── build.riscv.baremetal.sh ├── build.riscv.emulator.sh ├── build.riscv.linux.sh ├── build.riscv.rocketcore.sh ├── build.riscv.root.sh ├── build.riscv.toolchain.sh ├── parallella │ ├── mount.sd.boot.sh │ └── umount.sd.boot.sh ├── set.env.sh ├── settings.sh ├── setup.parallella.oh.submodule.sh ├── setup.rocketchip.submodule.sh ├── setup.verilator.sh └── vivado │ ├── create_ip.tcl │ ├── system_build.tcl │ └── system_init.tcl └── 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