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ACM Computing Surveys (April 2022). https://doi.org/10.1145/3532989 7 | 8 | and follows the same taxonomy to cluster state-of-the-art **Hardware Description Languages (HDLs)**, **High-Level Synthesis (HLS) tools**, and **Domain-Specific Languages (DSLs)**. 9 | 10 | Please feel free to contribute and help maintain this list updated. 11 | 12 | ## Hardware Description Languages (HDLs) 13 | 14 | The HDL taxonomy is based on the characteristics of the programming model employed in the embedded languages exploited as input. Here, we report high-level HDLs that, eventually, translates into standard HDLs, namely, VHDL/(System)Verilog. 15 | 16 | ### Functional-based HDLs 17 | 18 | HDLs embedding the characteristics of the functional languages from which they derive (e.g., SML, Haskell, and Scala). 19 | 20 | - ***Chisel*** 21 | 22 | *Year*: 2012 23 | 24 | *Paper*: J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avizienis, J. Wawrzynek, and K. Asanovic. 2012. Chisel: Constructing hardware in a Scala embedded language. In DAC Design Automation Conference 2012. 1212–1221. https://doi.org/10.1145/2228360.2228584 25 | 26 | *Repository*: https://github.com/chipsalliance/chisel3 27 | 28 | *Website*: https://www.chisel-lang.org 29 | 30 | - ***Clash*** 31 | 32 | *Year*: 2009 33 | 34 | *Paper*: C. Baaij, M. Kooijman, J. Kuper, A. Boeijink, and M. Gerards. 2010. C𝜆ash: Structural descriptions of synchronous hardware using haskell. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. IEEE, 714–721. https://doi.org/10.1109/DSD.2010.21 35 | 36 | *Repository*: https://github.com/clash-lang/clash-compiler 37 | 38 | *Website*: https://clash-lang.org 39 | 40 | - ***DFiant*** 41 | 42 | *Year*: 2017 43 | 44 | *Paper*: O. Port and Y. Etsion. 2017. DFiant: A dataflow hardware description language. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 1–4. https://doi.org/10.23919/FPL.2017.8056858 45 | 46 | *Repository*: https://github.com/DFiantHDL/DFiant 47 | 48 | *Website*: https://dfianthdl.github.io 49 | 50 | 51 | - ***Hardware ML (HML)*** 52 | 53 | *Year*: 2000 54 | 55 | *Paper*: Y. Li and M. Leeser. 2000. HML, a Novel Hardware Description Language and Its Translation to VHDL. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, 1 (2000), 1–8. https://doi.org/10.1109/92.820756 56 | 57 | - ***SpinalHDL*** 58 | 59 | *Year*: 2014 60 | 61 | *Paper*: C. Papon. 2017. SpinalHDL: An alternative hardware description language. FOSDEM (2017). https://doi.org/10.5446/43800 62 | 63 | *Repository*: https://github.com/SpinalHDL/SpinalHDL 64 | 65 | *Website*: https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html 66 | 67 | - ***VeriScala*** 68 | 69 | *Year*: 2019 70 | 71 | *Paper*: Y. Liu, Y. Li, Z. Qi, and H. Guan. 2019. A scala based framework for developing acceleration systems with FPGAs. Journal of Systems Architecture 98 (2019), 231–242. https://doi.org/10.1016/j.sysarc.2019.08.001 72 | 73 | *Repository*: https://github.com/VeriScala/VeriScala 74 | 75 | 76 | ### Imperative-based HDLs 77 | 78 | HDLs embedding the characteristics of the imperative languages from which they derive (e.g., Java, Python, and C++). 79 | 80 | - ***ArchHDL*** 81 | 82 | *Year*: 2013 83 | 84 | *Paper*: S. Sato and K. Kise. 2013. ArchHDL: a new hardware description language for high-speed architectural evaluation. In 2013 IEEE 7th International Symposium on Embedded Multicore Socs. IEEE, 107–112. https://doi.org/10.1109/MCSoC.2013.38 85 | 86 | 87 | - ***HDLRuby*** 88 | 89 | *Year*: 2018 90 | 91 | *Paper*: L. Gauthier and Y. Ishikawa, "HDLRuby, a new high productivity hardware description language," 2018 5th International Conference on Business and Industrial Research (ICBIR), 2018, pp. 215-220, doi: https://doi.org/10.1109/ICBIR.2018.8391195. 92 | 93 | *Repository*: https://github.com/civol/HDLRuby 94 | 95 | *Website*: https://rubygems.org/gems/HDLRuby/versions/2.5.0 96 | 97 | 98 | - ***Just Another HDL (JHDL)*** 99 | 100 | *Year*: 1998 101 | 102 | *Paper*: P. Bellows and B. Hutchings. 1998. JHDL - An HDL for Reconfigurable Systems. In IEEE Symposium on FPGAs for Custom Computing Machines. IEEE. https://doi.org/10.1109/FPGA.1998.707895 103 | 104 | *Website*: https://web.archive.org/web/20061205060548/http://jhdl.org/ 105 | 106 | 107 | - ***MaxJ*** 108 | 109 | *Year*: 2009 110 | 111 | *Paper*: O. Lindtjorn, R. G. Clapp, O. Pell, O. Mencer, and M. J. Flynn. 2010. Surviving the end of scaling of traditional microprocessors in HPC. IEEE Hot Chips 22 (2010), 22–24. 112 | 113 | *Website*: https://www.maxeler.com/products/software/maxcompiler/ 114 | 115 | 116 | - ***MyHDL*** 117 | 118 | *Year*: 2004 119 | 120 | *Paper*: J. Decaluwe. 2004. MyHDL: a Python-Based Hardware Description Language. Linux journal 127 (2004), 84–87. https://www.linuxjournal.com/article/7542 121 | 122 | *Code*: https://sourceforge.net/projects/myhdl/ 123 | 124 | 125 | - ***Python HDL (PHDL)*** 126 | 127 | *Year*: 2007 128 | 129 | *Paper*: A. Mashtizadeh. 2007. PHDL: A Python Hardware Design Framework. https://dspace.mit.edu/handle/1721.1/41543. 130 | 131 | *Repository*: https://github.com/wnew/phdl 132 | 133 | 134 | - ***PyMTL*** 135 | 136 | *Year*: 2014 137 | 138 | *Paper*: D. Lockhart, G. Zibrat, and C. Batten. 2014. PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research. In 47th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE. https://doi.org/10.1109/MICRO.2014.50 139 | 140 | *Paper*: S. Jiang, C. Torng. and C. Batten. 2018. An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework. In Workshop on Open-Source EDA Technology (WOSET’18). 1–5. https://www.csl.cornell.edu/~cbatten/pdfs/jiang-pymtl-woset2018.pdf 141 | 142 | *Repository*: https://github.com/pymtl/pymtl3 143 | 144 | *Website*: https://pymtl.github.io 145 | 146 | 147 | - ***PyRTL*** 148 | 149 | *Year*: 2017 150 | 151 | *Paper*: J. Clow, G. Tzimpragos, D. Dangwal, S. Guo, J. McMahan, and T. Sherwood. 2017. A pythonic approach for rapid hardware prototyping and instrumentation. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 1–7. https://doi.org/10.23919/FPL.2017.8056860 152 | 153 | *Repository*: https://github.com/UCSBarchlab/PyRTL 154 | 155 | *Website*: https://ucsbarchlab.github.io/PyRTL/ 156 | 157 | 158 | - ***PyVerilog*** 159 | 160 | *Year*: 2015 161 | 162 | *Paper*: S. Takamaeda-Yamazaki. 2015. PyVerilog: A Python-Based hardware design processing toolkit for Verilog HDL. In Applied Reconfigurable Computing. Springer, 451–460. https://doi.org/10.1007/978-3-319-16214-0_42 163 | 164 | *Repository*: https://github.com/PyHDI/Pyverilog 165 | 166 | 167 | ### SystemVerilog Extension HDLs 168 | 169 | HDLs extending SystemVerilog. 170 | 171 | - ***BlueSpec SystemVerilog (BSV)*** 172 | 173 | *Year*: 2004 174 | 175 | *Paper*: R. Nikhil. 2004. Bluespec System Verilog: efficient, correct RTL from high level specifications. In Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE’04. https://doi.org/10.1109/MEMCOD.2004.1459818 176 | 177 | *Paper*: T. Bourgeat, C. Pit-Claudel, A. Chlipala, and Arvind. 2020. The essence of Bluespec: a core language for rule-based hardware design. In Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation. 243–257. https://doi.org/10.1145/3385412.3385965 178 | 179 | *Repository*: https://github.com/B-Lang-org/bsc 180 | 181 | *Website*: http://wiki.bluespec.com 182 | 183 | 184 | - ***Genesis2*** 185 | 186 | *Year*: 2012 187 | 188 | *Paper*: O. Shacham, S. Galal, S. Sankaranarayanan, M. Wachs, J. Brunhaver, A. Vassiliev, M. Horowitz, A. Danowitz, W. Qadeer, and S. Richardson. 2012. Avoiding Game Over: Bringing Design to the Next Level. In DAC Design Automation Conference. IEEE, 623–629. https://doi.org/10.1145/2228360.2228472 189 | 190 | 191 | - ***Transaction-Level Verilog (TL-Verilog)*** 192 | 193 | *Year*: 2017 194 | 195 | *Paper*: S. F. Hoover. 2017. Timing-abstract circuit design in transaction-level Verilog. In 2017 IEEE International Conference on Computer Design (ICCD). IEEE, 525–532. https://doi.org/10.1109/ICCD.2017.91 196 | 197 | *Repository*: https://github.com/TL-X-org 198 | 199 | *Website*: https://www.redwoodeda.com/tl-verilog 200 | 201 | 202 |
203 | 204 | 205 | ## High-Level Synthesis (HLS) Tools 206 | 207 | The HLS taxonomy is based on the target application and synthesis flow. 208 | 209 | ### High-Level Synthesis (HLS) 210 | 211 | These tools generate RTL for generic IPs described using high-level languages (e.g., C and C++). Here we report only “pure” HLS tools, i.e., tools that do perform the HLS process without delegating it to third-party software. 212 | 213 | - ***Bambu*** 214 | 215 | *Year*: 2012 216 | 217 | *Paper*: C. Pilato and F. Ferrandi. 2013. Bambu: A modular framework for the high level synthesis of memory-intensive applications. In Field Programmable Logic and Applications (FPL), 23rd International Conference on. IEEE. https://doi.org/10.1109/FPL.2013.6645550 218 | 219 | *Repository*: https://github.com/ferrandi/PandA-bambu 220 | 221 | *Website*: https://panda.dei.polimi.it/?page_id=31 222 | 223 | 224 | - ***Catapult-HLS*** 225 | 226 | *Year*: 2004 227 | 228 | *Paper*: T. Bollaert. 2008. Catapult synthesis: a practical introduction to interactive C synthesis. In High-Level Synthesis. Springer, 29–52. https://doi.org/10.1007/978-1-4020-8588-8_3 229 | 230 | *Website*: https://www.mentor.com/hls-lp/catapult-high-level-synthesis/ 231 | 232 | 233 | - ***CyberWorkBench*** 234 | 235 | *Year*: 2011 236 | 237 | *Website*: https://www.nec.com/en/global/prod/cwb/index.html 238 | 239 | 240 | - ***DWARV*** 241 | 242 | *Year*: 2012 243 | 244 | *Paper*: R. Nane, V. Sima, B. Olivier, R. Meeuws, Y. Yankova, and K. Bertels. 2012. DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler. In Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on. IEEE, 619–622. https://doi.org/10.1109/FPL.2012.6339221 245 | 246 | 247 | - ***Dynamatic*** 248 | 249 | *Year*: 2017 250 | 251 | *Paper*: L. Josipović, R. Ghosal, and P. Ienne. 2018. Dynamically Scheduled High-level Synthesis. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '18). Association for Computing Machinery, New York, NY, USA, 127–136. https://doi.org/10.1145/3174243.3174264 252 | 253 | *Paper*: L. Josipović, A. Guerrieri, and P. Ienne. 2020. Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. In The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 1–10. https://doi.org/10.1145/3373087.3375391 254 | 255 | *Paper*: L. Josipović, S. Sheikhha, A. Guerrieri, P. Ienne, and J. Cortadella. 2021. Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. 15, 1, Article 4 (March 2022), 32 pages. https://doi.org/10.1145/3477053 256 | 257 | *Repository*: https://github.com/lana555/dynamatic 258 | 259 | *Website*: https://dynamatic.epfl.ch 260 | 261 | 262 | - ***GAUT*** 263 | 264 | *Year*: 2009 265 | 266 | *Paper*: P. Coussy, C. Chavet, P. Bomel, D. Heller, E. Senn, and E. Martin. 2008. GAUT: A high-level synthesis tool for DSP applications. In High-Level Synthesis. Springer, 147–169. https://doi.org/10.1007/978-1-4020-8588-8_9 267 | 268 | *Website*: http://hls-labsticc.univ-ubs.fr/ 269 | 270 | 271 | - ***Hastlayer*** 272 | 273 | *Year*: 2015 274 | 275 | *Repository*: https://github.com/Lombiq/Hastlayer-SDK 276 | 277 | *Website*: https://hastlayer.com 278 | 279 | 280 | - ***HDL Coder*** 281 | 282 | *Year*: 2003 283 | 284 | *Documentation*: https://www.mathworks.com/help/pdf_doc/hdlcoder/hdlcoder_ug.pdf 285 | 286 | *Website*: https://www.mathworks.com/products/hdl-coder.html 287 | 288 | 289 | - ***Intel HLS Compiler*** 290 | 291 | *Year*: 2017 292 | 293 | *Documentation*: https://www.intel.com/content/www/us/en/docs/programmable/683349/22-1/pro-edition-reference-manual.html 294 | 295 | *Website*: https://www.intel.it/content/www/it/it/software/programmable/quartus-prime/hls-compiler.html 296 | 297 | 298 | - ***Kiwi*** 299 | 300 | *Year*: 2008 301 | 302 | *Paper*: S. Singh and D. J. Greaves. 2008. Kiwi: Synthesis of FPGA circuits from parallel programs. In 2008 16th International Symposium on Field-Programmable Custom Computing Machines. IEEE, 3–12. https://doi.org/10.1109/FCCM.2008.46 303 | 304 | *Website*: https://www.cl.cam.ac.uk/~djg11/kiwi/ 305 | 306 | 307 | - ***LegUp*** 308 | 309 | *Year*: 2009 310 | 311 | *Paper*: A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. H. Anderson, S. Brown, and T. Czajkowski. 2011. LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays. ACM, Association for Computing Machinery, New York, NY, USA, 33–36. https://doi.org/10.1145/1950413.1950423 312 | 313 | *Paper*: A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, T. Czajkowski, S. D. Brown, and J. H. Anderson. 2013. LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13, 2, Article 24 (September 2013), 27 pages. https://doi.org/10.1145/2514740 314 | 315 | *Repository*: https://github.com/wincle626/HLS_Legup 316 | 317 | *Website*: https://www.legupcomputing.com/ 318 | 319 | 320 | - ***ROCCC*** 321 | 322 | *Year*: 2009 323 | 324 | *Paper*: J. Villarreal, A. Park, W. Najjar, and R. Halstead. 2010. Designing modular hardware accelerators in C with ROCCC 2.0. In Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on. IEEE, 127–134. https://doi.org/10.1109/FCCM.2010.28 325 | 326 | *Repository*: https://github.com/nxt4hll/roccc-2.0 327 | 328 | *Website*: http://roccc.cs.ucr.edu/ 329 | 330 | 331 | - ***Stratus HLS*** 332 | 333 | *Year*: 2015 334 | 335 | *Paper*: D. Pursleyand, T. Yeh. 2017. High-level low-power system design optimization. In VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on. IEEE, 1–4. https://doi.org/10.1109/VLSI-DAT.2017.7939656 336 | 337 | *Website*: https://www.cadence.com/ko_KR/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html 338 | 339 | 340 | - ***Vitis HLS*** 341 | 342 | *Year*: 2020 343 | 344 | *Documentation*: https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Getting-Started-with-Vitis-HLS 345 | 346 | 347 | - ***Vivado HLS*** 348 | 349 | *Year*: 2013 350 | 351 | *Documentation*: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0012-vivado-high-level-synthesis-hub.html 352 | 353 | 354 | - ***XLS*** 355 | 356 | *Year*: 2020 357 | 358 | *Repository*: https://github.com/google/xls/ 359 | 360 | *Website*: https://google.github.io/xls/ 361 | 362 | 363 | ### Accelerator-Centric Synthesis (ACS) 364 | 365 | These tools focus on hardware acceleration of algorithms and automatize the whole design flow, from the HLS process to the bitstream generation. 366 | 367 | - ***Altera OpenCL SDK (AOCL)*** 368 | 369 | *Year*: 2012 370 | 371 | *Paper*: T. S. Czajkowski, U. Aydonat, D. Denisenko, J. Freeman, M. Kinsner, D. Neto, J. Wong, P. Yiannacouras, and D. P. Singh. 2012. From OpenCL to high-performance hardware on FPGAs. In 22nd international conference on field programmable logic and applications (FPL). IEEE, 531–534. https://doi.org/10.1109/FPL.2012.6339272 372 | 373 | *Documentation*: https://www.intel.com/content/dam/support/jp/ja/programmable/support-resources/bulk-container/pdfs/literature/hb/opencl-sdk/aocl-getting-started.pdf 374 | 375 | 376 | - ***Intel oneAPI*** 377 | 378 | *Year*: 2019 379 | 380 | *Documentation*: https://www.intel.com/content/www/us/en/developer/tools/oneapi/fpga-documentation.html?s=Newest 381 | 382 | *Website*: https://www.intel.com/content/www/us/en/developer/tools/oneapi/fpga.html 383 | 384 | 385 | - ***Intel OpenCL SDK*** 386 | 387 | *Year*: 2015 388 | 389 | *Documentation*: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/opencl-support.html?s=Newest 390 | 391 | *Website*: https://www.intel.com/content/www/us/en/software/programmable/sdk-for-opencl/overview.html 392 | 393 | 394 | - ***SDAccel*** 395 | 396 | *Year*: 2014 397 | 398 | *Documentation*: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0058-sdaccel-hub.html 399 | 400 | *Website*: https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html 401 | 402 | 403 | - ***SDSoC*** 404 | 405 | *Year*: 2015 406 | 407 | *Documentation*: https://www.xilinx.com/support/documents/sw_manuals/xilinx2019_1/ug1027-sdsoc-user-guide.pdf 408 | 409 | *Website*: https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html 410 | 411 | 412 | - ***TAPAS*** 413 | 414 | *Year*: 2018 415 | 416 | *Paper*: S. Margerm, A. Sharifian, A. Guha, A. Shriraman, and G. Pokam. 2018. TAPAS: Generating parallel accelerators from parallel programs. In 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 245–257. https://doi.org/10.1109/MICRO.2018.00028 417 | 418 | *Repository*: https://github.com/sfu-arch/tapas 419 | 420 | 421 | - ***Xilinx Vitis*** 422 | 423 | *Year*: 2019 424 | 425 | *Documentation*: https://docs.xilinx.com/v/u/en-US/ug1416-vitis-documentation 426 | 427 | *Website*: https://www.xilinx.com/products/design-tools/vitis.html 428 | 429 | 430 |
431 | 432 | 433 | ## Domain-Specific Languages (DSLs) 434 | 435 | We cluster DSLs based on their domain of interest: single application domain, architectural models, intermediate languages and infrastructure for DSLs. 436 | 437 | ### Application Domain 438 | 439 | DSLs concentrating on a given application domain (e.g., image processing and packet processing). 440 | 441 | - ***Darkroom*** 442 | 443 | *Year*: 2014 444 | 445 | *Paper*: J. Hegarty, J. Brunhaver, Z. De Vito, J. Ragan-Kelley, N. Cohen, S. Bell, A. Vasilyev, M. Horowitz, and P. Hanrahan. 2014. Darkroom: compiling high-level image processing code into hardware pipelines. ACM Trans. Graph. 33, 4 (2014), 144–1. https://doi.org/10.1145/2601097.2601174 446 | 447 | *Repository*: https://github.com/jameshegarty/darkroom 448 | 449 | *Website*: http://darkroom-lang.org 450 | 451 | 452 | - ***ExaSlang 4*** 453 | 454 | *Year*: 2014 455 | 456 | *Paper*: C. Schmitt, M. Schmid, F. Hannig, J. Teich, S. Kuckuk, and H. Köstler. 2015. Generation of multigrid-based numerical solvers for FPGA accelerators. In Proceedings of the 2nd International Workshop on High-Performance Stencil Computations (HiStencils). 9–15. http://dx.doi.org/10.13140/2.1.1680.9760 457 | 458 | *Repository*: https://github.com/lssfau/ExaStencils 459 | 460 | *Website*: https://www.exastencils.fau.de 461 | 462 | 463 | - ***Halide-HLS*** 464 | 465 | *Year*: 2017 466 | 467 | *Paper*: J. Pu, S. Bell, X. Yang, J. Setter, S. Richardson, J. Ragan-Kelley, and M. Horowitz. 2017. Programming Heterogeneous Systems from an Image Processing DSL. ACM Trans. Archit. Code Optim. 14, 3, Article 26 (Aug. 2017), 25 pages. https://doi.org/10.1145/3107953 468 | 469 | *Repository*: https://github.com/jingpu/Halide-HLS 470 | 471 | 472 | - ***HeteroHalide*** 473 | 474 | *Year*: 2020 475 | 476 | *Paper*: J. Li, Y. Chi, and J. Cong. 2020. HeteroHalide: From image processing DSL to efficient FPGA acceleration. In Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 51–57. https://doi.org/10.1145/3373087.3375320 477 | 478 | *Repository*: https://github.com/UCLA-VAST/heterohalide 479 | 480 | 481 | - ***Hipacc*** 482 | 483 | *Year*: 2014 484 | 485 | *Paper*: O. Reiche, M. Schmid, F. Hannig, R. Membarth, and J. Teich. 2014. Code generation from a domain-specific language for C-based HLS of hardware accelerators. In 2014 international conference on hardware/software codesign and system synthesis (CODES+ ISSS). IEEE, 1–10. https://doi.org/10.1145/2656075.2656081 486 | 487 | *Paper*: R. Membarth, O. Reiche, F. Hannig, J. Teich, M. Körner, and W. Eckert. 2015. Hipacc: A domain-specific language and compiler for image processing. IEEE Transactions on Parallel and Distributed Systems 27, 1 (2015), 210–224. https://doi.org/10.1109/TPDS.2015.2394802 488 | 489 | *Paper*: O. Reiche, M. A. Özkan, R. Membarth, J. Teich, and F. Hannig. 2017. Generating FPGA-based image processing accelerators with Hipacc. In Proceedings of the 36th International Conference on Computer-Aided Design (ICCAD '17). IEEE Press, 1026–1033. https://doi.org/10.1109/ICCAD.2017.8203894 490 | 491 | *Repository*: https://github.com/hipacc/hipacc-fpga 492 | 493 | *Website*: https://hipacc-lang.org/install.html 494 | 495 | 496 | - ***P4-to-VHDL*** 497 | 498 | *Year*: 2014 499 | 500 | *Paper*: P. Benáček, V. Pu, and H. Kubátová. 2016. P4-to-VHDL: Automatic generation of 100 gbps packet parsers. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE. https://doi.org/10.1109/FCCM.2016.46 501 | 502 | *Paper*: J. Cabal, P. Benáček, L. Kekely, M. Kekely, V. Puš, and J. Kořenek. 2018. Configurable FPGA packet parser for terabit networks with guaranteed wire-speed throughput. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 249–258. https://doi.org/10.1145/3174243.3174250 503 | 504 | 505 | - ***P4FPGA*** 506 | 507 | *Year*: 2017 508 | 509 | *Paper*: H. Wang, R. Soulé, H. T. Dang, K. S. Lee, V. Shrivastav, N. Foster, and H. Weatherspoon. 2017. P4fpga: A rapid prototyping framework for p4. In Proceedings of the Symposium on SDN Research. 122–135. https://doi.org/10.1145/3050220.3050234 510 | 511 | *Repository*: https://github.com/p4fpga/p4fpga 512 | 513 | *Website*: http://p4fpga.github.io 514 | 515 | 516 | - ***P4HLS*** 517 | 518 | *Year*: 2018 519 | 520 | *Paper*: J. S. da Silva, F. Boyer, and J. M. P. Langlois. 2018. P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs. In Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 147–152. https://doi.org/10.1145/3174243.3174270 521 | 522 | *Repository*: https://github.com/engjefersonsantiago/P4HLS 523 | 524 | 525 | - ***PolyMage*** 526 | 527 | *Year*: 2016 528 | 529 | *Paper*: N. Chugh, V. Vasista, S. Purini, and U. Bondhugula. 2016. A DSL compiler for accelerating image processing pipelines on FPGAs. In Proceedings of the 2016 International Conference on Parallel Architectures and Compilation. 327–338. https://doi.org/10.1145/2967938.2967969 530 | 531 | *Repository*: https://bitbucket.org/udayb/polymage/src/master/ 532 | 533 | *Website*: http://mcl.csa.iisc.ernet.in/polymage.html 534 | 535 | 536 | - ***Rigel*** 537 | 538 | *Year*: 2016 539 | 540 | *Paper*: J. Hegarty, R. Daly, Z. DeVito, J. Ragan-Kelley, M. Horowitz, and P. Hanrahan. 2016. Rigel: Flexible Multi-Rate Image Processing Hardware. ACM Trans. Graph. 35, 4, Article 85 (July 2016), 11 pages. https://doi.org/10.1145/2897824.2925892 541 | 542 | *Repository*: https://github.com/jameshegarty/rigel 543 | 544 | 545 | - ***RIPL*** 546 | 547 | *Year*: 2016 548 | 549 | *Paper*: R. Stewart, K. Duncan, G. Michaelson, P. Garcia, D. Bhowmik, and A. M. Wallace. 2018. RIPL: A Parallel Image Processing Language for FPGAs. ACM Transactions on Reconfigurable Technology and Systems 11, 1 (2018), 7:1–7:24. https://doi.org/10.1145/3180481 550 | 551 | *Repository*: https://github.com/robstewart57/ripl 552 | 553 | *Website*: https://robstewart57.github.io/ripl/ 554 | 555 | 556 | - ***Spiral*** 557 | 558 | *Year*: 2012 559 | 560 | *Paper*: P. Milder, F. Franchetti, J. C. Hoe, and M. Püschel. 2012. Computer generation of hardware for linear digital signal processing transforms. ACM Transactions on Design Automation of Electronic Systems 17, 2 (2012), 1–33. https://doi.org/10.1145/2159542.2159547 561 | 562 | *Paper*: F. Franchetti, T. M. Low, D. T. Popovici, R. M. Veras, D. G. Spampinato, J. R. Johnson, M. Püschel, J. C. Hoe, and J. M. F. Moura. 2018. SPIRAL: Extreme performance portability. Proc. IEEE 106, 11 (2018), 1935–1968. https://doi.org/10.1109/JPROC.2018.2873289 563 | 564 | *Website*: http://spiral.net/index.html 565 | 566 | 567 | ### Architectural Domain 568 | 569 | DSLs concentrating on a given architectural model (e.g., spatial architecture and systolic array). 570 | 571 | - ***Spatial*** 572 | 573 | *Year*: 2018 574 | 575 | *Paper*: D. Koeplinger, M. Feldman, R. Prabhakar, Y. Zhang, S. Hadjis, R. Fiszel, T. Zhao, L. Nardi, A. Pedram, C. Kozyrakis, , and K. Olukotun. 2018. Spatial: A language and compiler for application accelerators. In Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation. 296–311. https://doi.org/10.1145/3192366.3192379 576 | 577 | *Repository*: https://github.com/stanford-ppl/spatial 578 | 579 | *Website*: https://spatial-lang.org 580 | 581 | 582 | - ***SPGen*** 583 | 584 | *Year*: 2020 585 | 586 | *Paper*: Y. Watanabe, J. Lee, K. Sano, T. Boku, and M. Sato. 2020. Design and preliminary evaluation of openacc compiler for fpga with opencl and stream processing dsl. In Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region Workshops. 10–16. https://doi.org/10.1145/3373271.3373274 587 | 588 | 589 | - ***SuSy*** 590 | 591 | *Year*: 2020 592 | 593 | *Paper*: Y. Lai, H. Rong, S. Zheng, W. Zhang, X. Cui, Y. Jia, J. Wang, B. Sullivan, Z. Zhang, Y. Liang, Y. Zhang, J. Cong, N. George, J. Alvarez, C. Hughes, and P. Dubey 2020. SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE, 1–9. https://doi.org/10.1145/3400302.3415644 594 | 595 | *Repository*: https://github.com/IntelLabs/t2sp 596 | 597 | 598 | 599 | ### Intermediate Infrastructure 600 | 601 | Solutions proposing an intermediate layer lying between the DSL and the RTL/HLS code. 602 | 603 | - ***AnyHLS*** 604 | 605 | *Year*: 2020 606 | 607 | *Paper*: M. A. Özkan, A. Pérard-Gayot, R. Membarth, P. Slusallek, R. Leißa, S. Hack, J. Teich, and F. Hannig. 2020. AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 11 (2020), 3202–3214. https://doi.org/10.1109/TCAD.2020.3012172 608 | 609 | *Repository*: https://github.com/AnyDSL/anyhls 610 | 611 | *Website*: https://anydsl.github.io 612 | 613 | 614 | - ***Calyx*** 615 | 616 | *Year*: 2021 617 | 618 | *Paper*: R. Nigam, S. Thomas, Z. Li, and A. Sampson. 2021. A compiler infrastructure for accelerator generators. In Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. 804–817. https://doi.org/10.1145/3445814.3446712 619 | 620 | *Repository*: https://github.com/cucapra/calyx 621 | 622 | *Website*: https://calyxir.org 623 | 624 | 625 | - ***Delite Hardware Definition Language (DHDL)*** 626 | 627 | *Year*: 2016 628 | 629 | *Paper*: D. Koeplinger, R. Prabhakar, Y. Zhang, C. Delimitrou, C. Kozyrakis, and K. Olukotun. 2016. Automatic Generation of Efficient Accelerators for Reconfigurable Hardware. In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). 115–127. https://doi.org/10.1109/ISCA.2016.20 630 | 631 | *Paper*: R. Prabhakar, D. Koeplinger, K. J. Brown, H. Lee, C. De Sa, C. Kozyrakis, and K. Olukotun. 2016. Generating configurable hardware from parallel patterns. Acm Sigplan Notices 51, 4 (2016). https://doi.org/10.1145/2872362.2872415 632 | 633 | *Repository*: https://bitbucket.org/raghup17/dhdl/src/master/ 634 | 635 | 636 | - ***FROST*** 637 | 638 | *Year*: 2017 639 | 640 | *Paper*: E. Del Sozzo, R. Baghdadi, S. Amarasinghe, and M. D. Santambrogio. 2017. A Common Backend for Hardware Acceleration on FPGA. In Computer Design (ICCD), 2017 IEEE International Conference on. IEEE, 427–430. https://doi.org/10.1109/ICCD.2017.75 641 | 642 | *Paper*: E. Del Sozzo, R. Baghdadi, S. Amarasinghe, and M. D. Santambrogio. 2018. A unified backend for targeting fpgas from dsls. In 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 1–8. https://doi.org/10.1109/ASAP.2018.8445108 643 | 644 | 645 | - ***HeteroCL*** 646 | 647 | *Year*: 2019 648 | 649 | *Paper*: Y. Lai, Y. Chi, Y. Hu, J. Wang, C. H. Yu, Y. Zhou, J. Cong, and Z. Zhang. 2019. HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 242–251. https://doi.org/10.1145/3289602.3293910 650 | 651 | *Repository*: https://github.com/cornell-zhang/heterocl 652 | 653 | *Website*: https://heterocl.csl.cornell.edu 654 | 655 | 656 | - ***Infrastructure for Delite-based DSLs*** 657 | 658 | *Year*: 2014 659 | 660 | *Paper*: N. George, H. Lee, D. Novo, T. Rompf, K. J. Brown, A. K. Sujeeth, M. Odersky, K. Olukotun, and P. Ienne. 2014. Hardware system synthesis from domain-specific languages. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 1–8. https://doi.org/10.1109/FPL.2014.6927454 661 | 662 | 663 | - ***LIFT*** 664 | 665 | *Year*: 2019 666 | 667 | *Paper*: M. Kristien, B. Bodin, M. Steuwer, and C. Dubach. 2019. High-level synthesis of functional patterns with Lift. In Proceedings of the 6th ACM SIGPLAN International Workshop on Libraries, Languages and Compilers for Array Programming. 35–45. https://doi.org/10.1145/3315454.3329957 668 | 669 | *Repository*: https://github.com/lift-project/lift 670 | 671 | *Website*: http://www.lift-project.org 672 | 673 | 674 | --------------------------------------------------------------------------------